1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Mips target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsTargetMachine.h" 15 #include "Mips.h" 16 #include "llvm/PassManager.h" 17 #include "llvm/CodeGen/Passes.h" 18 #include "llvm/Support/TargetRegistry.h" 19 using namespace llvm; 20 21 extern "C" void LLVMInitializeMipsTarget() { 22 // Register the target. 23 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget); 24 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget); 25 RegisterTargetMachine<Mips64ebTargetMachine> A(TheMips64Target); 26 RegisterTargetMachine<Mips64elTargetMachine> B(TheMips64elTarget); 27 } 28 29 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment 30 // The stack is always 8 byte aligned 31 // On function prologue, the stack is created by decrementing 32 // its pointer. Once decremented, all references are done with positive 33 // offset from the stack/frame pointer, using StackGrowsUp enables 34 // an easier handling. 35 // Using CodeModel::Large enables different CALL behavior. 36 MipsTargetMachine:: 37 MipsTargetMachine(const Target &T, StringRef TT, 38 StringRef CPU, StringRef FS, const TargetOptions &Options, 39 Reloc::Model RM, CodeModel::Model CM, 40 CodeGenOpt::Level OL, 41 bool isLittle) 42 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 43 Subtarget(TT, CPU, FS, isLittle), 44 DataLayout(isLittle ? 45 (Subtarget.isABI_N64() ? 46 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" : 47 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : 48 (Subtarget.isABI_N64() ? 49 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" : 50 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")), 51 InstrInfo(*this), 52 FrameLowering(Subtarget), 53 TLInfo(*this), TSInfo(*this), JITInfo() { 54 } 55 56 void MipsebTargetMachine::anchor() { } 57 58 MipsebTargetMachine:: 59 MipsebTargetMachine(const Target &T, StringRef TT, 60 StringRef CPU, StringRef FS, const TargetOptions &Options, 61 Reloc::Model RM, CodeModel::Model CM, 62 CodeGenOpt::Level OL) 63 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 64 65 void MipselTargetMachine::anchor() { } 66 67 MipselTargetMachine:: 68 MipselTargetMachine(const Target &T, StringRef TT, 69 StringRef CPU, StringRef FS, const TargetOptions &Options, 70 Reloc::Model RM, CodeModel::Model CM, 71 CodeGenOpt::Level OL) 72 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 73 74 void Mips64ebTargetMachine::anchor() { } 75 76 Mips64ebTargetMachine:: 77 Mips64ebTargetMachine(const Target &T, StringRef TT, 78 StringRef CPU, StringRef FS, const TargetOptions &Options, 79 Reloc::Model RM, CodeModel::Model CM, 80 CodeGenOpt::Level OL) 81 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 82 83 void Mips64elTargetMachine::anchor() { } 84 85 Mips64elTargetMachine:: 86 Mips64elTargetMachine(const Target &T, StringRef TT, 87 StringRef CPU, StringRef FS, const TargetOptions &Options, 88 Reloc::Model RM, CodeModel::Model CM, 89 CodeGenOpt::Level OL) 90 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 91 92 namespace { 93 /// Mips Code Generator Pass Configuration Options. 94 class MipsPassConfig : public TargetPassConfig { 95 public: 96 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM) 97 : TargetPassConfig(TM, PM) {} 98 99 MipsTargetMachine &getMipsTargetMachine() const { 100 return getTM<MipsTargetMachine>(); 101 } 102 103 const MipsSubtarget &getMipsSubtarget() const { 104 return *getMipsTargetMachine().getSubtargetImpl(); 105 } 106 107 virtual bool addInstSelector(); 108 virtual bool addPreRegAlloc(); 109 virtual bool addPreSched2(); 110 virtual bool addPreEmitPass(); 111 }; 112 } // namespace 113 114 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { 115 return new MipsPassConfig(this, PM); 116 } 117 118 // Install an instruction selector pass using 119 // the ISelDag to gen Mips code. 120 bool MipsPassConfig::addInstSelector() { 121 PM->add(createMipsISelDag(getMipsTargetMachine())); 122 return false; 123 } 124 125 // Implemented by targets that want to run passes immediately before 126 // machine code is emitted. return true if -print-machineinstrs should 127 // print out the code after the passes. 128 bool MipsPassConfig::addPreEmitPass() { 129 PM->add(createMipsDelaySlotFillerPass(getMipsTargetMachine())); 130 return true; 131 } 132 133 bool MipsPassConfig::addPreRegAlloc() { 134 // Do not restore $gp if target is Mips64. 135 // In N32/64, $gp is a callee-saved register. 136 if (!getMipsSubtarget().hasMips64()) 137 PM->add(createMipsEmitGPRestorePass(getMipsTargetMachine())); 138 return true; 139 } 140 141 bool MipsPassConfig::addPreSched2() { 142 PM->add(createMipsExpandPseudoPass(getMipsTargetMachine())); 143 return true; 144 } 145 146 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM, 147 JITCodeEmitter &JCE) { 148 // Machine code emitter pass for Mips. 149 PM.add(createMipsJITCodeEmitterPass(*this, JCE)); 150 return false; 151 } 152