1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Mips target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Mips.h" 15 #include "MipsTargetMachine.h" 16 #include "llvm/PassManager.h" 17 #include "llvm/Support/TargetRegistry.h" 18 using namespace llvm; 19 20 extern "C" void LLVMInitializeMipsTarget() { 21 // Register the target. 22 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget); 23 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget); 24 RegisterTargetMachine<Mips64ebTargetMachine> A(TheMips64Target); 25 RegisterTargetMachine<Mips64elTargetMachine> B(TheMips64elTarget); 26 } 27 28 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment 29 // The stack is always 8 byte aligned 30 // On function prologue, the stack is created by decrementing 31 // its pointer. Once decremented, all references are done with positive 32 // offset from the stack/frame pointer, using StackGrowsUp enables 33 // an easier handling. 34 // Using CodeModel::Large enables different CALL behavior. 35 MipsTargetMachine:: 36 MipsTargetMachine(const Target &T, StringRef TT, 37 StringRef CPU, StringRef FS, const TargetOptions &Options, 38 Reloc::Model RM, CodeModel::Model CM, 39 CodeGenOpt::Level OL, 40 bool isLittle) 41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 42 Subtarget(TT, CPU, FS, isLittle), 43 DataLayout(isLittle ? 44 (Subtarget.isABI_N64() ? 45 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" : 46 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : 47 (Subtarget.isABI_N64() ? 48 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" : 49 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")), 50 InstrInfo(*this), 51 FrameLowering(Subtarget), 52 TLInfo(*this), TSInfo(*this), JITInfo() { 53 } 54 55 MipsebTargetMachine:: 56 MipsebTargetMachine(const Target &T, StringRef TT, 57 StringRef CPU, StringRef FS, const TargetOptions &Options, 58 Reloc::Model RM, CodeModel::Model CM, 59 CodeGenOpt::Level OL) 60 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 61 62 MipselTargetMachine:: 63 MipselTargetMachine(const Target &T, StringRef TT, 64 StringRef CPU, StringRef FS, const TargetOptions &Options, 65 Reloc::Model RM, CodeModel::Model CM, 66 CodeGenOpt::Level OL) 67 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 68 69 Mips64ebTargetMachine:: 70 Mips64ebTargetMachine(const Target &T, StringRef TT, 71 StringRef CPU, StringRef FS, const TargetOptions &Options, 72 Reloc::Model RM, CodeModel::Model CM, 73 CodeGenOpt::Level OL) 74 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 75 76 Mips64elTargetMachine:: 77 Mips64elTargetMachine(const Target &T, StringRef TT, 78 StringRef CPU, StringRef FS, const TargetOptions &Options, 79 Reloc::Model RM, CodeModel::Model CM, 80 CodeGenOpt::Level OL) 81 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 82 83 // Install an instruction selector pass using 84 // the ISelDag to gen Mips code. 85 bool MipsTargetMachine:: 86 addInstSelector(PassManagerBase &PM) 87 { 88 PM.add(createMipsISelDag(*this)); 89 return false; 90 } 91 92 // Implemented by targets that want to run passes immediately before 93 // machine code is emitted. return true if -print-machineinstrs should 94 // print out the code after the passes. 95 bool MipsTargetMachine:: 96 addPreEmitPass(PassManagerBase &PM) 97 { 98 PM.add(createMipsDelaySlotFillerPass(*this)); 99 return true; 100 } 101 102 bool MipsTargetMachine:: 103 addPreRegAlloc(PassManagerBase &PM) { 104 // Do not restore $gp if target is Mips64. 105 // In N32/64, $gp is a callee-saved register. 106 if (!Subtarget.hasMips64()) 107 PM.add(createMipsEmitGPRestorePass(*this)); 108 return true; 109 } 110 111 bool MipsTargetMachine:: 112 addPostRegAlloc(PassManagerBase &PM) { 113 PM.add(createMipsExpandPseudoPass(*this)); 114 return true; 115 } 116 117 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM, 118 JITCodeEmitter &JCE) { 119 // Machine code emitter pass for Mips. 120 PM.add(createMipsJITCodeEmitterPass(*this, JCE)); 121 return false; 122 } 123