1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MipsMachineFunction.h" 11 #include "MCTargetDesc/MipsABIInfo.h" 12 #include "MipsSubtarget.h" 13 #include "MipsTargetMachine.h" 14 #include "llvm/CodeGen/MachineFrameInfo.h" 15 #include "llvm/CodeGen/MachineRegisterInfo.h" 16 #include "llvm/CodeGen/PseudoSourceValue.h" 17 #include "llvm/CodeGen/TargetRegisterInfo.h" 18 #include "llvm/Support/CommandLine.h" 19 20 using namespace llvm; 21 22 static cl::opt<bool> 23 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true), 24 cl::desc("Always use $gp as the global base register.")); 25 26 MipsFunctionInfo::~MipsFunctionInfo() = default; 27 28 bool MipsFunctionInfo::globalBaseRegSet() const { 29 return GlobalBaseReg; 30 } 31 32 unsigned MipsFunctionInfo::getGlobalBaseReg() { 33 // Return if it has already been initialized. 34 if (GlobalBaseReg) 35 return GlobalBaseReg; 36 37 MipsSubtarget const &STI = 38 static_cast<const MipsSubtarget &>(MF.getSubtarget()); 39 40 const TargetRegisterClass *RC = 41 STI.inMips16Mode() 42 ? &Mips::CPU16RegsRegClass 43 : STI.inMicroMipsMode() 44 ? &Mips::GPRMM16RegClass 45 : static_cast<const MipsTargetMachine &>(MF.getTarget()) 46 .getABI() 47 .IsN64() 48 ? &Mips::GPR64RegClass 49 : &Mips::GPR32RegClass; 50 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); 51 } 52 53 void MipsFunctionInfo::createEhDataRegsFI() { 54 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 55 for (int I = 0; I < 4; ++I) { 56 const TargetRegisterClass &RC = 57 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64() 58 ? Mips::GPR64RegClass 59 : Mips::GPR32RegClass; 60 61 EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), 62 TRI.getSpillAlignment(RC), false); 63 } 64 } 65 66 void MipsFunctionInfo::createISRRegFI() { 67 // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers. 68 // The current implementation only supports Mips32r2+ not Mips64rX. Status 69 // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture, 70 // however Mips32r2+ is the supported architecture. 71 const TargetRegisterClass &RC = Mips::GPR32RegClass; 72 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 73 74 for (int I = 0; I < 2; ++I) 75 ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject( 76 TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false); 77 } 78 79 bool MipsFunctionInfo::isEhDataRegFI(int FI) const { 80 return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1] 81 || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]); 82 } 83 84 bool MipsFunctionInfo::isISRRegFI(int FI) const { 85 return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]); 86 } 87 MachinePointerInfo MipsFunctionInfo::callPtrInfo(const char *ES) { 88 return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES)); 89 } 90 91 MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *GV) { 92 return MachinePointerInfo(MF.getPSVManager().getGlobalValueCallEntry(GV)); 93 } 94 95 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { 96 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); 97 if (MoveF64ViaSpillFI == -1) { 98 MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject( 99 TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false); 100 } 101 return MoveF64ViaSpillFI; 102 } 103 104 void MipsFunctionInfo::anchor() {} 105