1 //===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsAsmBackend and MipsELFObjectWriter classes. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MipsFixupKinds.h" 16 #include "MCTargetDesc/MipsMCTargetDesc.h" 17 #include "llvm/MC/MCAsmBackend.h" 18 #include "llvm/MC/MCAssembler.h" 19 #include "llvm/MC/MCDirectives.h" 20 #include "llvm/MC/MCELFObjectWriter.h" 21 #include "llvm/MC/MCFixupKindInfo.h" 22 #include "llvm/MC/MCObjectWriter.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 using namespace llvm; 28 29 // Prepare value for the target space for it 30 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 31 32 // Add/subtract and shift 33 switch (Kind) { 34 default: 35 return 0; 36 case FK_GPRel_4: 37 case FK_Data_4: 38 case Mips::fixup_Mips_LO16: 39 case Mips::fixup_Mips_GPOFF_HI: 40 case Mips::fixup_Mips_GPOFF_LO: 41 case Mips::fixup_Mips_GOT_PAGE: 42 case Mips::fixup_Mips_GOT_OFST: 43 case Mips::fixup_Mips_GOT_DISP: 44 break; 45 case Mips::fixup_Mips_PC16: 46 // So far we are only using this type for branches. 47 // For branches we start 1 instruction after the branch 48 // so the displacement will be one instruction size less. 49 Value -= 4; 50 // The displacement is then divided by 4 to give us an 18 bit 51 // address range. 52 Value >>= 2; 53 break; 54 case Mips::fixup_Mips_26: 55 // So far we are only using this type for jumps. 56 // The displacement is then divided by 4 to give us an 28 bit 57 // address range. 58 Value >>= 2; 59 break; 60 case Mips::fixup_Mips_HI16: 61 case Mips::fixup_Mips_GOT_Local: 62 // Get the higher 16-bits. Also add 1 if bit 15 is 1. 63 Value = ((Value + 0x8000) >> 16) & 0xffff; 64 break; 65 } 66 67 return Value; 68 } 69 70 namespace { 71 class MipsAsmBackend : public MCAsmBackend { 72 Triple::OSType OSType; 73 bool IsLittle; // Big or little endian 74 bool Is64Bit; // 32 or 64 bit words 75 76 public: 77 MipsAsmBackend(const Target &T, Triple::OSType _OSType, 78 bool _isLittle, bool _is64Bit) 79 :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {} 80 81 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 82 return createMipsELFObjectWriter(OS, 83 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 84 } 85 86 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided 87 /// data fragment, at the offset specified by the fixup and following the 88 /// fixup kind as appropriate. 89 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 90 uint64_t Value) const { 91 MCFixupKind Kind = Fixup.getKind(); 92 Value = adjustFixupValue((unsigned)Kind, Value); 93 94 if (!Value) 95 return; // Doesn't change encoding. 96 97 // Where do we start in the object 98 unsigned Offset = Fixup.getOffset(); 99 // Number of bytes we need to fixup 100 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 101 // Used to point to big endian bytes 102 unsigned FullSize; 103 104 switch ((unsigned)Kind) { 105 case Mips::fixup_Mips_16: 106 FullSize = 2; 107 break; 108 case Mips::fixup_Mips_64: 109 FullSize = 8; 110 break; 111 default: 112 FullSize = 4; 113 break; 114 } 115 116 // Grab current value, if any, from bits. 117 uint64_t CurVal = 0; 118 119 for (unsigned i = 0; i != NumBytes; ++i) { 120 unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 121 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 122 } 123 124 uint64_t Mask = ((uint64_t)(-1) >> 125 (64 - getFixupKindInfo(Kind).TargetSize)); 126 CurVal |= Value & Mask; 127 128 // Write out the fixed up bytes back to the code/data bits. 129 for (unsigned i = 0; i != NumBytes; ++i) { 130 unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 131 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 132 } 133 } 134 135 unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; } 136 137 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 138 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { 139 // This table *must* be in same the order of fixup_* kinds in 140 // MipsFixupKinds.h. 141 // 142 // name offset bits flags 143 { "fixup_Mips_16", 0, 16, 0 }, 144 { "fixup_Mips_32", 0, 32, 0 }, 145 { "fixup_Mips_REL32", 0, 32, 0 }, 146 { "fixup_Mips_26", 0, 26, 0 }, 147 { "fixup_Mips_HI16", 0, 16, 0 }, 148 { "fixup_Mips_LO16", 0, 16, 0 }, 149 { "fixup_Mips_GPREL16", 0, 16, 0 }, 150 { "fixup_Mips_LITERAL", 0, 16, 0 }, 151 { "fixup_Mips_GOT_Global", 0, 16, 0 }, 152 { "fixup_Mips_GOT_Local", 0, 16, 0 }, 153 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 154 { "fixup_Mips_CALL16", 0, 16, 0 }, 155 { "fixup_Mips_GPREL32", 0, 32, 0 }, 156 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 157 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 158 { "fixup_Mips_64", 0, 64, 0 }, 159 { "fixup_Mips_TLSGD", 0, 16, 0 }, 160 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 161 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 162 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 163 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 164 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 165 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 166 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 167 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 168 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 169 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 170 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 171 { "fixup_Mips_GOT_DISP", 0, 16, 0 } 172 }; 173 174 if (Kind < FirstTargetFixupKind) 175 return MCAsmBackend::getFixupKindInfo(Kind); 176 177 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 178 "Invalid kind!"); 179 return Infos[Kind - FirstTargetFixupKind]; 180 } 181 182 /// @name Target Relaxation Interfaces 183 /// @{ 184 185 /// MayNeedRelaxation - Check whether the given instruction may need 186 /// relaxation. 187 /// 188 /// \param Inst - The instruction to test. 189 bool mayNeedRelaxation(const MCInst &Inst) const { 190 return false; 191 } 192 193 /// fixupNeedsRelaxation - Target specific predicate for whether a given 194 /// fixup requires the associated instruction to be relaxed. 195 bool fixupNeedsRelaxation(const MCFixup &Fixup, 196 uint64_t Value, 197 const MCInstFragment *DF, 198 const MCAsmLayout &Layout) const { 199 // FIXME. 200 assert(0 && "RelaxInstruction() unimplemented"); 201 return false; 202 } 203 204 /// RelaxInstruction - Relax the instruction in the given fragment 205 /// to the next wider instruction. 206 /// 207 /// \param Inst - The instruction to relax, which may be the same 208 /// as the output. 209 /// \parm Res [output] - On return, the relaxed instruction. 210 void relaxInstruction(const MCInst &Inst, MCInst &Res) const { 211 } 212 213 /// @} 214 215 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 216 /// to the given output. If the target cannot generate such a sequence, 217 /// it should return an error. 218 /// 219 /// \return - True on success. 220 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { 221 // Check for a less than instruction size number of bytes 222 // FIXME: 16 bit instructions are not handled yet here. 223 // We shouldn't be using a hard coded number for instruction size. 224 if (Count % 4) return false; 225 226 uint64_t NumNops = Count / 4; 227 for (uint64_t i = 0; i != NumNops; ++i) 228 OW->Write32(0); 229 return true; 230 } 231 }; // class MipsAsmBackend 232 233 } // namespace 234 235 // MCAsmBackend 236 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT) { 237 return new MipsAsmBackend(T, Triple(TT).getOS(), 238 /*IsLittle*/true, /*Is64Bit*/false); 239 } 240 241 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT) { 242 return new MipsAsmBackend(T, Triple(TT).getOS(), 243 /*IsLittle*/false, /*Is64Bit*/false); 244 } 245 246 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT) { 247 return new MipsAsmBackend(T, Triple(TT).getOS(), 248 /*IsLittle*/true, /*Is64Bit*/true); 249 } 250 251 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT) { 252 return new MipsAsmBackend(T, Triple(TT).getOS(), 253 /*IsLittle*/false, /*Is64Bit*/true); 254 } 255 256