1 //===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsAsmBackend and MipsELFObjectWriter classes. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MipsFixupKinds.h" 16 #include "MCTargetDesc/MipsMCTargetDesc.h" 17 #include "llvm/MC/MCAsmBackend.h" 18 #include "llvm/MC/MCAssembler.h" 19 #include "llvm/MC/MCContext.h" 20 #include "llvm/MC/MCDirectives.h" 21 #include "llvm/MC/MCELFObjectWriter.h" 22 #include "llvm/MC/MCFixupKindInfo.h" 23 #include "llvm/MC/MCObjectWriter.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 // Prepare value for the target space for it 32 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 33 MCContext *Ctx = NULL) { 34 35 unsigned Kind = Fixup.getKind(); 36 37 // Add/subtract and shift 38 switch (Kind) { 39 default: 40 return 0; 41 case FK_Data_2: 42 case FK_GPRel_4: 43 case FK_Data_4: 44 case FK_Data_8: 45 case Mips::fixup_Mips_LO16: 46 case Mips::fixup_Mips_GPREL16: 47 case Mips::fixup_Mips_GPOFF_HI: 48 case Mips::fixup_Mips_GPOFF_LO: 49 case Mips::fixup_Mips_GOT_PAGE: 50 case Mips::fixup_Mips_GOT_OFST: 51 case Mips::fixup_Mips_GOT_DISP: 52 case Mips::fixup_Mips_GOT_LO16: 53 case Mips::fixup_Mips_CALL_LO16: 54 case Mips::fixup_MICROMIPS_LO16: 55 case Mips::fixup_MICROMIPS_GOT_PAGE: 56 case Mips::fixup_MICROMIPS_GOT_OFST: 57 case Mips::fixup_MICROMIPS_GOT_DISP: 58 break; 59 case Mips::fixup_Mips_PC16: 60 // So far we are only using this type for branches. 61 // For branches we start 1 instruction after the branch 62 // so the displacement will be one instruction size less. 63 Value -= 4; 64 // The displacement is then divided by 4 to give us an 18 bit 65 // address range. Forcing a signed division because Value can be negative. 66 Value = (int64_t)Value / 4; 67 // We now check if Value can be encoded as a 16-bit signed immediate. 68 if (!isIntN(16, Value) && Ctx) 69 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup"); 70 break; 71 case Mips::fixup_Mips_26: 72 // So far we are only using this type for jumps. 73 // The displacement is then divided by 4 to give us an 28 bit 74 // address range. 75 Value >>= 2; 76 break; 77 case Mips::fixup_Mips_HI16: 78 case Mips::fixup_Mips_GOT_Local: 79 case Mips::fixup_Mips_GOT_HI16: 80 case Mips::fixup_Mips_CALL_HI16: 81 case Mips::fixup_MICROMIPS_HI16: 82 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 83 Value = ((Value + 0x8000) >> 16) & 0xffff; 84 break; 85 case Mips::fixup_Mips_HIGHER: 86 // Get the 3rd 16-bits. 87 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 88 break; 89 case Mips::fixup_Mips_HIGHEST: 90 // Get the 4th 16-bits. 91 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 92 break; 93 case Mips::fixup_MICROMIPS_26_S1: 94 Value >>= 1; 95 break; 96 case Mips::fixup_MICROMIPS_PC16_S1: 97 Value -= 4; 98 // Forcing a signed division because Value can be negative. 99 Value = (int64_t)Value / 2; 100 // We now check if Value can be encoded as a 16-bit signed immediate. 101 if (!isIntN(16, Value) && Ctx) 102 Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup"); 103 break; 104 } 105 106 return Value; 107 } 108 109 namespace { 110 class MipsAsmBackend : public MCAsmBackend { 111 Triple::OSType OSType; 112 bool IsLittle; // Big or little endian 113 bool Is64Bit; // 32 or 64 bit words 114 115 public: 116 MipsAsmBackend(const Target &T, Triple::OSType _OSType, 117 bool _isLittle, bool _is64Bit) 118 :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {} 119 120 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 121 return createMipsELFObjectWriter(OS, 122 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 123 } 124 125 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 126 /// data fragment, at the offset specified by the fixup and following the 127 /// fixup kind as appropriate. 128 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 129 uint64_t Value) const { 130 MCFixupKind Kind = Fixup.getKind(); 131 Value = adjustFixupValue(Fixup, Value); 132 133 if (!Value) 134 return; // Doesn't change encoding. 135 136 // Where do we start in the object 137 unsigned Offset = Fixup.getOffset(); 138 // Number of bytes we need to fixup 139 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 140 // Used to point to big endian bytes 141 unsigned FullSize; 142 143 switch ((unsigned)Kind) { 144 case FK_Data_2: 145 case Mips::fixup_Mips_16: 146 FullSize = 2; 147 break; 148 case FK_Data_8: 149 case Mips::fixup_Mips_64: 150 FullSize = 8; 151 break; 152 case FK_Data_4: 153 default: 154 FullSize = 4; 155 break; 156 } 157 158 // Grab current value, if any, from bits. 159 uint64_t CurVal = 0; 160 161 for (unsigned i = 0; i != NumBytes; ++i) { 162 unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 163 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 164 } 165 166 uint64_t Mask = ((uint64_t)(-1) >> 167 (64 - getFixupKindInfo(Kind).TargetSize)); 168 CurVal |= Value & Mask; 169 170 // Write out the fixed up bytes back to the code/data bits. 171 for (unsigned i = 0; i != NumBytes; ++i) { 172 unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 173 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 174 } 175 } 176 177 unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; } 178 179 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 180 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { 181 // This table *must* be in same the order of fixup_* kinds in 182 // MipsFixupKinds.h. 183 // 184 // name offset bits flags 185 { "fixup_Mips_16", 0, 16, 0 }, 186 { "fixup_Mips_32", 0, 32, 0 }, 187 { "fixup_Mips_REL32", 0, 32, 0 }, 188 { "fixup_Mips_26", 0, 26, 0 }, 189 { "fixup_Mips_HI16", 0, 16, 0 }, 190 { "fixup_Mips_LO16", 0, 16, 0 }, 191 { "fixup_Mips_GPREL16", 0, 16, 0 }, 192 { "fixup_Mips_LITERAL", 0, 16, 0 }, 193 { "fixup_Mips_GOT_Global", 0, 16, 0 }, 194 { "fixup_Mips_GOT_Local", 0, 16, 0 }, 195 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 196 { "fixup_Mips_CALL16", 0, 16, 0 }, 197 { "fixup_Mips_GPREL32", 0, 32, 0 }, 198 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 199 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 200 { "fixup_Mips_64", 0, 64, 0 }, 201 { "fixup_Mips_TLSGD", 0, 16, 0 }, 202 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 203 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 204 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 205 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 206 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 207 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 208 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 209 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 210 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 211 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 212 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 213 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 214 { "fixup_Mips_HIGHER", 0, 16, 0 }, 215 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 216 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 217 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 218 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 219 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 220 { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 221 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 222 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 223 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 224 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 225 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 226 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 227 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 228 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 229 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, 230 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, 231 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 232 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 233 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 234 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 } 235 }; 236 237 if (Kind < FirstTargetFixupKind) 238 return MCAsmBackend::getFixupKindInfo(Kind); 239 240 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 241 "Invalid kind!"); 242 return Infos[Kind - FirstTargetFixupKind]; 243 } 244 245 /// @name Target Relaxation Interfaces 246 /// @{ 247 248 /// MayNeedRelaxation - Check whether the given instruction may need 249 /// relaxation. 250 /// 251 /// \param Inst - The instruction to test. 252 bool mayNeedRelaxation(const MCInst &Inst) const { 253 return false; 254 } 255 256 /// fixupNeedsRelaxation - Target specific predicate for whether a given 257 /// fixup requires the associated instruction to be relaxed. 258 bool fixupNeedsRelaxation(const MCFixup &Fixup, 259 uint64_t Value, 260 const MCRelaxableFragment *DF, 261 const MCAsmLayout &Layout) const { 262 // FIXME. 263 assert(0 && "RelaxInstruction() unimplemented"); 264 return false; 265 } 266 267 /// RelaxInstruction - Relax the instruction in the given fragment 268 /// to the next wider instruction. 269 /// 270 /// \param Inst - The instruction to relax, which may be the same 271 /// as the output. 272 /// \param [out] Res On return, the relaxed instruction. 273 void relaxInstruction(const MCInst &Inst, MCInst &Res) const { 274 } 275 276 /// @} 277 278 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 279 /// to the given output. If the target cannot generate such a sequence, 280 /// it should return an error. 281 /// 282 /// \return - True on success. 283 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { 284 // Check for a less than instruction size number of bytes 285 // FIXME: 16 bit instructions are not handled yet here. 286 // We shouldn't be using a hard coded number for instruction size. 287 if (Count % 4) return false; 288 289 uint64_t NumNops = Count / 4; 290 for (uint64_t i = 0; i != NumNops; ++i) 291 OW->Write32(0); 292 return true; 293 } 294 295 /// processFixupValue - Target hook to process the literal value of a fixup 296 /// if necessary. 297 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, 298 const MCFixup &Fixup, const MCFragment *DF, 299 MCValue &Target, uint64_t &Value, 300 bool &IsResolved) { 301 // At this point we'll ignore the value returned by adjustFixupValue as 302 // we are only checking if the fixup can be applied correctly. We have 303 // access to MCContext from here which allows us to report a fatal error 304 // with *possibly* a source code location. 305 (void)adjustFixupValue(Fixup, Value, &Asm.getContext()); 306 } 307 308 }; // class MipsAsmBackend 309 310 } // namespace 311 312 // MCAsmBackend 313 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 314 const MCRegisterInfo &MRI, 315 StringRef TT, 316 StringRef CPU) { 317 return new MipsAsmBackend(T, Triple(TT).getOS(), 318 /*IsLittle*/true, /*Is64Bit*/false); 319 } 320 321 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 322 const MCRegisterInfo &MRI, 323 StringRef TT, 324 StringRef CPU) { 325 return new MipsAsmBackend(T, Triple(TT).getOS(), 326 /*IsLittle*/false, /*Is64Bit*/false); 327 } 328 329 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 330 const MCRegisterInfo &MRI, 331 StringRef TT, 332 StringRef CPU) { 333 return new MipsAsmBackend(T, Triple(TT).getOS(), 334 /*IsLittle*/true, /*Is64Bit*/true); 335 } 336 337 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 338 const MCRegisterInfo &MRI, 339 StringRef TT, 340 StringRef CPU) { 341 return new MipsAsmBackend(T, Triple(TT).getOS(), 342 /*IsLittle*/false, /*Is64Bit*/true); 343 } 344 345