1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the MipsAsmBackend class. 11 // 12 //===----------------------------------------------------------------------===// 13 // 14 15 #include "MCTargetDesc/MipsAsmBackend.h" 16 #include "MCTargetDesc/MipsFixupKinds.h" 17 #include "MCTargetDesc/MipsMCExpr.h" 18 #include "MCTargetDesc/MipsMCTargetDesc.h" 19 #include "llvm/MC/MCAsmBackend.h" 20 #include "llvm/MC/MCAssembler.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDirectives.h" 23 #include "llvm/MC/MCELFObjectWriter.h" 24 #include "llvm/MC/MCFixupKindInfo.h" 25 #include "llvm/MC/MCObjectWriter.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCValue.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/Format.h" 30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/Support/raw_ostream.h" 32 33 using namespace llvm; 34 35 // Prepare value for the target space for it 36 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 37 MCContext &Ctx) { 38 39 unsigned Kind = Fixup.getKind(); 40 41 // Add/subtract and shift 42 switch (Kind) { 43 default: 44 return 0; 45 case FK_Data_2: 46 case Mips::fixup_Mips_LO16: 47 case Mips::fixup_Mips_GPREL16: 48 case Mips::fixup_Mips_GPOFF_HI: 49 case Mips::fixup_Mips_GPOFF_LO: 50 case Mips::fixup_Mips_GOT_PAGE: 51 case Mips::fixup_Mips_GOT_OFST: 52 case Mips::fixup_Mips_GOT_DISP: 53 case Mips::fixup_Mips_GOT_LO16: 54 case Mips::fixup_Mips_CALL_LO16: 55 case Mips::fixup_MICROMIPS_LO16: 56 case Mips::fixup_MICROMIPS_GOT_PAGE: 57 case Mips::fixup_MICROMIPS_GOT_OFST: 58 case Mips::fixup_MICROMIPS_GOT_DISP: 59 case Mips::fixup_MIPS_PCLO16: 60 Value &= 0xffff; 61 break; 62 case FK_DTPRel_4: 63 case FK_DTPRel_8: 64 case FK_TPRel_4: 65 case FK_TPRel_8: 66 case FK_GPRel_4: 67 case FK_Data_4: 68 case FK_Data_8: 69 case Mips::fixup_Mips_SUB: 70 case Mips::fixup_MICROMIPS_SUB: 71 break; 72 case Mips::fixup_Mips_PC16: 73 // The displacement is then divided by 4 to give us an 18 bit 74 // address range. Forcing a signed division because Value can be negative. 75 Value = (int64_t)Value / 4; 76 // We now check if Value can be encoded as a 16-bit signed immediate. 77 if (!isInt<16>(Value)) { 78 Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup"); 79 return 0; 80 } 81 break; 82 case Mips::fixup_MIPS_PC19_S2: 83 case Mips::fixup_MICROMIPS_PC19_S2: 84 // Forcing a signed division because Value can be negative. 85 Value = (int64_t)Value / 4; 86 // We now check if Value can be encoded as a 19-bit signed immediate. 87 if (!isInt<19>(Value)) { 88 Ctx.reportError(Fixup.getLoc(), "out of range PC19 fixup"); 89 return 0; 90 } 91 break; 92 case Mips::fixup_Mips_26: 93 // So far we are only using this type for jumps. 94 // The displacement is then divided by 4 to give us an 28 bit 95 // address range. 96 Value >>= 2; 97 break; 98 case Mips::fixup_Mips_HI16: 99 case Mips::fixup_Mips_GOT: 100 case Mips::fixup_MICROMIPS_GOT16: 101 case Mips::fixup_Mips_GOT_HI16: 102 case Mips::fixup_Mips_CALL_HI16: 103 case Mips::fixup_MICROMIPS_HI16: 104 case Mips::fixup_MIPS_PCHI16: 105 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 106 Value = ((Value + 0x8000) >> 16) & 0xffff; 107 break; 108 case Mips::fixup_Mips_HIGHER: 109 // Get the 3rd 16-bits. 110 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 111 break; 112 case Mips::fixup_Mips_HIGHEST: 113 // Get the 4th 16-bits. 114 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 115 break; 116 case Mips::fixup_MICROMIPS_26_S1: 117 Value >>= 1; 118 break; 119 case Mips::fixup_MICROMIPS_PC7_S1: 120 Value -= 4; 121 // Forcing a signed division because Value can be negative. 122 Value = (int64_t) Value / 2; 123 // We now check if Value can be encoded as a 7-bit signed immediate. 124 if (!isInt<7>(Value)) { 125 Ctx.reportError(Fixup.getLoc(), "out of range PC7 fixup"); 126 return 0; 127 } 128 break; 129 case Mips::fixup_MICROMIPS_PC10_S1: 130 Value -= 2; 131 // Forcing a signed division because Value can be negative. 132 Value = (int64_t) Value / 2; 133 // We now check if Value can be encoded as a 10-bit signed immediate. 134 if (!isInt<10>(Value)) { 135 Ctx.reportError(Fixup.getLoc(), "out of range PC10 fixup"); 136 return 0; 137 } 138 break; 139 case Mips::fixup_MICROMIPS_PC16_S1: 140 Value -= 4; 141 // Forcing a signed division because Value can be negative. 142 Value = (int64_t)Value / 2; 143 // We now check if Value can be encoded as a 16-bit signed immediate. 144 if (!isInt<16>(Value)) { 145 Ctx.reportError(Fixup.getLoc(), "out of range PC16 fixup"); 146 return 0; 147 } 148 break; 149 case Mips::fixup_MIPS_PC18_S3: 150 // Forcing a signed division because Value can be negative. 151 Value = (int64_t)Value / 8; 152 // We now check if Value can be encoded as a 18-bit signed immediate. 153 if (!isInt<18>(Value)) { 154 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); 155 return 0; 156 } 157 break; 158 case Mips::fixup_MICROMIPS_PC18_S3: 159 // Check alignment. 160 if ((Value & 7)) { 161 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); 162 } 163 // Forcing a signed division because Value can be negative. 164 Value = (int64_t)Value / 8; 165 // We now check if Value can be encoded as a 18-bit signed immediate. 166 if (!isInt<18>(Value)) { 167 Ctx.reportError(Fixup.getLoc(), "out of range PC18 fixup"); 168 return 0; 169 } 170 break; 171 case Mips::fixup_MIPS_PC21_S2: 172 // Forcing a signed division because Value can be negative. 173 Value = (int64_t) Value / 4; 174 // We now check if Value can be encoded as a 21-bit signed immediate. 175 if (!isInt<21>(Value)) { 176 Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup"); 177 return 0; 178 } 179 break; 180 case Mips::fixup_MIPS_PC26_S2: 181 // Forcing a signed division because Value can be negative. 182 Value = (int64_t) Value / 4; 183 // We now check if Value can be encoded as a 26-bit signed immediate. 184 if (!isInt<26>(Value)) { 185 Ctx.reportError(Fixup.getLoc(), "out of range PC26 fixup"); 186 return 0; 187 } 188 break; 189 case Mips::fixup_MICROMIPS_PC26_S1: 190 // Forcing a signed division because Value can be negative. 191 Value = (int64_t)Value / 2; 192 // We now check if Value can be encoded as a 26-bit signed immediate. 193 if (!isInt<26>(Value)) { 194 Ctx.reportFatalError(Fixup.getLoc(), "out of range PC26 fixup"); 195 return 0; 196 } 197 break; 198 case Mips::fixup_MICROMIPS_PC21_S1: 199 // Forcing a signed division because Value can be negative. 200 Value = (int64_t)Value / 2; 201 // We now check if Value can be encoded as a 21-bit signed immediate. 202 if (!isInt<21>(Value)) { 203 Ctx.reportError(Fixup.getLoc(), "out of range PC21 fixup"); 204 return 0; 205 } 206 break; 207 } 208 209 return Value; 210 } 211 212 MCObjectWriter * 213 MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const { 214 return createMipsELFObjectWriter(OS, 215 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 216 } 217 218 // Little-endian fixup data byte ordering: 219 // mips32r2: a | b | x | x 220 // microMIPS: x | x | a | b 221 222 static bool needsMMLEByteOrder(unsigned Kind) { 223 return Kind != Mips::fixup_MICROMIPS_PC10_S1 && 224 Kind >= Mips::fixup_MICROMIPS_26_S1 && 225 Kind < Mips::LastTargetFixupKind; 226 } 227 228 // Calculate index for microMIPS specific little endian byte order 229 static unsigned calculateMMLEIndex(unsigned i) { 230 assert(i <= 3 && "Index out of range!"); 231 232 return (1 - i / 2) * 2 + i % 2; 233 } 234 235 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 236 /// data fragment, at the offset specified by the fixup and following the 237 /// fixup kind as appropriate. 238 void MipsAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 239 const MCValue &Target, 240 MutableArrayRef<char> Data, uint64_t Value, 241 bool IsResolved) const { 242 MCFixupKind Kind = Fixup.getKind(); 243 MCContext &Ctx = Asm.getContext(); 244 Value = adjustFixupValue(Fixup, Value, Ctx); 245 246 if (!Value) 247 return; // Doesn't change encoding. 248 249 // Where do we start in the object 250 unsigned Offset = Fixup.getOffset(); 251 // Number of bytes we need to fixup 252 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 253 // Used to point to big endian bytes 254 unsigned FullSize; 255 256 switch ((unsigned)Kind) { 257 case FK_Data_2: 258 case Mips::fixup_Mips_16: 259 case Mips::fixup_MICROMIPS_PC10_S1: 260 FullSize = 2; 261 break; 262 case FK_Data_8: 263 case Mips::fixup_Mips_64: 264 FullSize = 8; 265 break; 266 case FK_Data_4: 267 default: 268 FullSize = 4; 269 break; 270 } 271 272 // Grab current value, if any, from bits. 273 uint64_t CurVal = 0; 274 275 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); 276 277 for (unsigned i = 0; i != NumBytes; ++i) { 278 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 279 : i) 280 : (FullSize - 1 - i); 281 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 282 } 283 284 uint64_t Mask = ((uint64_t)(-1) >> 285 (64 - getFixupKindInfo(Kind).TargetSize)); 286 CurVal |= Value & Mask; 287 288 // Write out the fixed up bytes back to the code/data bits. 289 for (unsigned i = 0; i != NumBytes; ++i) { 290 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) 291 : i) 292 : (FullSize - 1 - i); 293 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 294 } 295 } 296 297 Optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const { 298 return StringSwitch<Optional<MCFixupKind>>(Name) 299 .Case("R_MIPS_NONE", (MCFixupKind)Mips::fixup_Mips_NONE) 300 .Case("R_MIPS_32", FK_Data_4) 301 .Default(MCAsmBackend::getFixupKind(Name)); 302 } 303 304 const MCFixupKindInfo &MipsAsmBackend:: 305 getFixupKindInfo(MCFixupKind Kind) const { 306 const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = { 307 // This table *must* be in same the order of fixup_* kinds in 308 // MipsFixupKinds.h. 309 // 310 // name offset bits flags 311 { "fixup_Mips_NONE", 0, 0, 0 }, 312 { "fixup_Mips_16", 0, 16, 0 }, 313 { "fixup_Mips_32", 0, 32, 0 }, 314 { "fixup_Mips_REL32", 0, 32, 0 }, 315 { "fixup_Mips_26", 0, 26, 0 }, 316 { "fixup_Mips_HI16", 0, 16, 0 }, 317 { "fixup_Mips_LO16", 0, 16, 0 }, 318 { "fixup_Mips_GPREL16", 0, 16, 0 }, 319 { "fixup_Mips_LITERAL", 0, 16, 0 }, 320 { "fixup_Mips_GOT", 0, 16, 0 }, 321 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 322 { "fixup_Mips_CALL16", 0, 16, 0 }, 323 { "fixup_Mips_GPREL32", 0, 32, 0 }, 324 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 325 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 326 { "fixup_Mips_64", 0, 64, 0 }, 327 { "fixup_Mips_TLSGD", 0, 16, 0 }, 328 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 329 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 330 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 331 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 332 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 333 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 334 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 335 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 336 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 337 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 338 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 339 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 340 { "fixup_Mips_HIGHER", 0, 16, 0 }, 341 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 342 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 343 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 344 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 345 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 346 { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 347 { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 348 { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 349 { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 350 { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 351 { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 352 { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 353 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 354 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 355 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 356 { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel }, 357 { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 358 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 359 { "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel }, 360 { "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 361 { "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel }, 362 { "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel }, 363 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 364 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 365 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 366 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 367 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 }, 368 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 }, 369 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 370 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 371 { "fixup_MICROMIPS_GOTTPREL", 0, 16, 0 }, 372 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 373 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }, 374 { "fixup_Mips_SUB", 0, 64, 0 }, 375 { "fixup_MICROMIPS_SUB", 0, 64, 0 } 376 }; 377 378 const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = { 379 // This table *must* be in same the order of fixup_* kinds in 380 // MipsFixupKinds.h. 381 // 382 // name offset bits flags 383 { "fixup_Mips_NONE", 0, 0, 0 }, 384 { "fixup_Mips_16", 16, 16, 0 }, 385 { "fixup_Mips_32", 0, 32, 0 }, 386 { "fixup_Mips_REL32", 0, 32, 0 }, 387 { "fixup_Mips_26", 6, 26, 0 }, 388 { "fixup_Mips_HI16", 16, 16, 0 }, 389 { "fixup_Mips_LO16", 16, 16, 0 }, 390 { "fixup_Mips_GPREL16", 16, 16, 0 }, 391 { "fixup_Mips_LITERAL", 16, 16, 0 }, 392 { "fixup_Mips_GOT", 16, 16, 0 }, 393 { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 394 { "fixup_Mips_CALL16", 16, 16, 0 }, 395 { "fixup_Mips_GPREL32", 0, 32, 0 }, 396 { "fixup_Mips_SHIFT5", 21, 5, 0 }, 397 { "fixup_Mips_SHIFT6", 21, 5, 0 }, 398 { "fixup_Mips_64", 0, 64, 0 }, 399 { "fixup_Mips_TLSGD", 16, 16, 0 }, 400 { "fixup_Mips_GOTTPREL", 16, 16, 0 }, 401 { "fixup_Mips_TPREL_HI", 16, 16, 0 }, 402 { "fixup_Mips_TPREL_LO", 16, 16, 0 }, 403 { "fixup_Mips_TLSLDM", 16, 16, 0 }, 404 { "fixup_Mips_DTPREL_HI", 16, 16, 0 }, 405 { "fixup_Mips_DTPREL_LO", 16, 16, 0 }, 406 { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 407 { "fixup_Mips_GPOFF_HI", 16, 16, 0 }, 408 { "fixup_Mips_GPOFF_LO", 16, 16, 0 }, 409 { "fixup_Mips_GOT_PAGE", 16, 16, 0 }, 410 { "fixup_Mips_GOT_OFST", 16, 16, 0 }, 411 { "fixup_Mips_GOT_DISP", 16, 16, 0 }, 412 { "fixup_Mips_HIGHER", 16, 16, 0 }, 413 { "fixup_Mips_HIGHEST", 16, 16, 0 }, 414 { "fixup_Mips_GOT_HI16", 16, 16, 0 }, 415 { "fixup_Mips_GOT_LO16", 16, 16, 0 }, 416 { "fixup_Mips_CALL_HI16", 16, 16, 0 }, 417 { "fixup_Mips_CALL_LO16", 16, 16, 0 }, 418 { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel }, 419 { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 420 { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel }, 421 { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 422 { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 423 { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel }, 424 { "fixup_MICROMIPS_26_S1", 6, 26, 0 }, 425 { "fixup_MICROMIPS_HI16", 16, 16, 0 }, 426 { "fixup_MICROMIPS_LO16", 16, 16, 0 }, 427 { "fixup_MICROMIPS_GOT16", 16, 16, 0 }, 428 { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel }, 429 { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel }, 430 { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel }, 431 { "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel }, 432 { "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel }, 433 { "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel }, 434 { "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel }, 435 { "fixup_MICROMIPS_CALL16", 16, 16, 0 }, 436 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, 437 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 }, 438 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 }, 439 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 }, 440 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 }, 441 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 }, 442 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 }, 443 { "fixup_MICROMIPS_GOTTPREL", 16, 16, 0 }, 444 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, 445 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }, 446 { "fixup_Mips_SUB", 0, 64, 0 }, 447 { "fixup_MICROMIPS_SUB", 0, 64, 0 } 448 }; 449 450 if (Kind < FirstTargetFixupKind) 451 return MCAsmBackend::getFixupKindInfo(Kind); 452 453 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 454 "Invalid kind!"); 455 456 if (IsLittle) 457 return LittleEndianInfos[Kind - FirstTargetFixupKind]; 458 return BigEndianInfos[Kind - FirstTargetFixupKind]; 459 } 460 461 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 462 /// to the given output. If the target cannot generate such a sequence, 463 /// it should return an error. 464 /// 465 /// \return - True on success. 466 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 467 // Check for a less than instruction size number of bytes 468 // FIXME: 16 bit instructions are not handled yet here. 469 // We shouldn't be using a hard coded number for instruction size. 470 471 // If the count is not 4-byte aligned, we must be writing data into the text 472 // section (otherwise we have unaligned instructions, and thus have far 473 // bigger problems), so just write zeros instead. 474 OW->WriteZeros(Count); 475 return true; 476 } 477 478 // MCAsmBackend 479 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 480 const MCRegisterInfo &MRI, 481 const Triple &TT, StringRef CPU, 482 const MCTargetOptions &Options) { 483 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, 484 /*Is64Bit*/ false); 485 } 486 487 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 488 const MCRegisterInfo &MRI, 489 const Triple &TT, StringRef CPU, 490 const MCTargetOptions &Options) { 491 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, 492 /*Is64Bit*/ false); 493 } 494 495 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 496 const MCRegisterInfo &MRI, 497 const Triple &TT, StringRef CPU, 498 const MCTargetOptions &Options) { 499 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); 500 } 501 502 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 503 const MCRegisterInfo &MRI, 504 const Triple &TT, StringRef CPU, 505 const MCTargetOptions &Options) { 506 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, 507 /*Is64Bit*/ true); 508 } 509