1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Hexagon implementation of the TargetRegisterInfo 10 // class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "HexagonRegisterInfo.h" 15 #include "Hexagon.h" 16 #include "HexagonMachineFunctionInfo.h" 17 #include "HexagonSubtarget.h" 18 #include "HexagonTargetMachine.h" 19 #include "llvm/ADT/BitVector.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/CodeGen/LiveIntervals.h" 22 #include "llvm/CodeGen/MachineFrameInfo.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineFunctionPass.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/CodeGen/PseudoSourceValue.h" 28 #include "llvm/CodeGen/RegisterScavenging.h" 29 #include "llvm/CodeGen/TargetInstrInfo.h" 30 #include "llvm/IR/Function.h" 31 #include "llvm/IR/Type.h" 32 #include "llvm/MC/MachineLocation.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/ErrorHandling.h" 35 #include "llvm/Support/raw_ostream.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 39 #define GET_REGINFO_TARGET_DESC 40 #include "HexagonGenRegisterInfo.inc" 41 42 using namespace llvm; 43 44 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) 45 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, 46 0/*PC*/, HwMode) {} 47 48 49 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const { 50 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 || 51 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1; 52 } 53 54 const MCPhysReg * 55 HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF, 56 const TargetRegisterClass *RC) const { 57 using namespace Hexagon; 58 59 static const MCPhysReg Int32[] = { 60 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0 61 }; 62 static const MCPhysReg Int64[] = { 63 D0, D1, D2, D3, D4, D5, D6, D7, 0 64 }; 65 static const MCPhysReg Pred[] = { 66 P0, P1, P2, P3, 0 67 }; 68 static const MCPhysReg VecSgl[] = { 69 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, 70 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, 71 V28, V29, V30, V31, 0 72 }; 73 static const MCPhysReg VecDbl[] = { 74 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0 75 }; 76 static const MCPhysReg VecPred[] = { 77 Q0, Q1, Q2, Q3, 0 78 }; 79 80 switch (RC->getID()) { 81 case IntRegsRegClassID: 82 return Int32; 83 case DoubleRegsRegClassID: 84 return Int64; 85 case PredRegsRegClassID: 86 return Pred; 87 case HvxVRRegClassID: 88 return VecSgl; 89 case HvxWRRegClassID: 90 return VecDbl; 91 case HvxQRRegClassID: 92 return VecPred; 93 default: 94 break; 95 } 96 97 static const MCPhysReg Empty[] = { 0 }; 98 #ifndef NDEBUG 99 dbgs() << "Register class: " << getRegClassName(RC) << "\n"; 100 #endif 101 llvm_unreachable("Unexpected register class"); 102 return Empty; 103 } 104 105 106 const MCPhysReg * 107 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 108 static const MCPhysReg CalleeSavedRegsV3[] = { 109 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 110 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 111 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 112 }; 113 114 // Functions that contain a call to __builtin_eh_return also save the first 4 115 // parameter registers. 116 static const MCPhysReg CalleeSavedRegsV3EHReturn[] = { 117 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 118 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 119 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 120 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 121 }; 122 123 bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn(); 124 125 return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3; 126 } 127 128 129 const uint32_t *HexagonRegisterInfo::getCallPreservedMask( 130 const MachineFunction &MF, CallingConv::ID) const { 131 return HexagonCSR_RegMask; 132 } 133 134 135 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) 136 const { 137 BitVector Reserved(getNumRegs()); 138 Reserved.set(Hexagon::R29); 139 Reserved.set(Hexagon::R30); 140 Reserved.set(Hexagon::R31); 141 Reserved.set(Hexagon::VTMP); 142 143 // Guest registers. 144 Reserved.set(Hexagon::GELR); // G0 145 Reserved.set(Hexagon::GSR); // G1 146 Reserved.set(Hexagon::GOSP); // G2 147 Reserved.set(Hexagon::G3); // G3 148 149 // Control registers. 150 Reserved.set(Hexagon::SA0); // C0 151 Reserved.set(Hexagon::LC0); // C1 152 Reserved.set(Hexagon::SA1); // C2 153 Reserved.set(Hexagon::LC1); // C3 154 Reserved.set(Hexagon::P3_0); // C4 155 Reserved.set(Hexagon::USR); // C8 156 Reserved.set(Hexagon::PC); // C9 157 Reserved.set(Hexagon::UGP); // C10 158 Reserved.set(Hexagon::GP); // C11 159 Reserved.set(Hexagon::CS0); // C12 160 Reserved.set(Hexagon::CS1); // C13 161 Reserved.set(Hexagon::UPCYCLELO); // C14 162 Reserved.set(Hexagon::UPCYCLEHI); // C15 163 Reserved.set(Hexagon::FRAMELIMIT); // C16 164 Reserved.set(Hexagon::FRAMEKEY); // C17 165 Reserved.set(Hexagon::PKTCOUNTLO); // C18 166 Reserved.set(Hexagon::PKTCOUNTHI); // C19 167 Reserved.set(Hexagon::UTIMERLO); // C30 168 Reserved.set(Hexagon::UTIMERHI); // C31 169 // Out of the control registers, only C8 is explicitly defined in 170 // HexagonRegisterInfo.td. If others are defined, make sure to add 171 // them here as well. 172 Reserved.set(Hexagon::C8); 173 Reserved.set(Hexagon::USR_OVF); 174 175 // Leveraging these registers will require more work to recognize 176 // the new semantics posed, Hi/LoVec patterns, etc. 177 // Note well: if enabled, they should be restricted to only 178 // where `HST.useHVXOps() && HST.hasV67Ops()` is true. 179 for (auto Reg : Hexagon_MC::GetVectRegRev()) 180 Reserved.set(Reg); 181 182 if (MF.getSubtarget<HexagonSubtarget>().hasReservedR19()) 183 Reserved.set(Hexagon::R19); 184 185 for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) 186 markSuperRegs(Reserved, x); 187 188 return Reserved; 189 } 190 191 192 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 193 int SPAdj, unsigned FIOp, 194 RegScavenger *RS) const { 195 // 196 // Hexagon_TODO: Do we need to enforce this for Hexagon? 197 assert(SPAdj == 0 && "Unexpected"); 198 199 MachineInstr &MI = *II; 200 MachineBasicBlock &MB = *MI.getParent(); 201 MachineFunction &MF = *MB.getParent(); 202 auto &HST = MF.getSubtarget<HexagonSubtarget>(); 203 auto &HII = *HST.getInstrInfo(); 204 auto &HFI = *HST.getFrameLowering(); 205 206 Register BP; 207 int FI = MI.getOperand(FIOp).getIndex(); 208 // Select the base pointer (BP) and calculate the actual offset from BP 209 // to the beginning of the object at index FI. 210 int Offset = HFI.getFrameIndexReference(MF, FI, BP).getFixed(); 211 // Add the offset from the instruction. 212 int RealOffset = Offset + MI.getOperand(FIOp+1).getImm(); 213 bool IsKill = false; 214 215 unsigned Opc = MI.getOpcode(); 216 switch (Opc) { 217 case Hexagon::PS_fia: 218 MI.setDesc(HII.get(Hexagon::A2_addi)); 219 MI.getOperand(FIOp).ChangeToImmediate(RealOffset); 220 MI.RemoveOperand(FIOp+1); 221 return; 222 case Hexagon::PS_fi: 223 // Set up the instruction for updating below. 224 MI.setDesc(HII.get(Hexagon::A2_addi)); 225 break; 226 } 227 228 if (!HII.isValidOffset(Opc, RealOffset, this)) { 229 // If the offset is not valid, calculate the address in a temporary 230 // register and use it with offset 0. 231 auto &MRI = MF.getRegInfo(); 232 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); 233 const DebugLoc &DL = MI.getDebugLoc(); 234 BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR) 235 .addReg(BP) 236 .addImm(RealOffset); 237 BP = TmpR; 238 RealOffset = 0; 239 IsKill = true; 240 } 241 242 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill); 243 MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset); 244 } 245 246 247 bool HexagonRegisterInfo::shouldCoalesce(MachineInstr *MI, 248 const TargetRegisterClass *SrcRC, unsigned SubReg, 249 const TargetRegisterClass *DstRC, unsigned DstSubReg, 250 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { 251 // Coalescing will extend the live interval of the destination register. 252 // If the destination register is a vector pair, avoid introducing function 253 // calls into the interval, since it could result in a spilling of a pair 254 // instead of a single vector. 255 MachineFunction &MF = *MI->getParent()->getParent(); 256 const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>(); 257 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) 258 return true; 259 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID(); 260 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); 261 if (!SmallSrc && !SmallDst) 262 return true; 263 264 Register DstReg = MI->getOperand(0).getReg(); 265 Register SrcReg = MI->getOperand(1).getReg(); 266 const SlotIndexes &Indexes = *LIS.getSlotIndexes(); 267 auto HasCall = [&Indexes] (const LiveInterval::Segment &S) { 268 for (SlotIndex I = S.start.getBaseIndex(), E = S.end.getBaseIndex(); 269 I != E; I = I.getNextIndex()) { 270 if (const MachineInstr *MI = Indexes.getInstructionFromIndex(I)) 271 if (MI->isCall()) 272 return true; 273 } 274 return false; 275 }; 276 277 if (SmallSrc == SmallDst) { 278 // Both must be true, because the case for both being false was 279 // checked earlier. Both registers will be coalesced into a register 280 // of a wider class (HvxWR), and we don't want its live range to 281 // span over calls. 282 return !any_of(LIS.getInterval(DstReg), HasCall) && 283 !any_of(LIS.getInterval(SrcReg), HasCall); 284 } 285 286 // If one register is large (HvxWR) and the other is small (HvxVR), then 287 // coalescing is ok if the large is already live across a function call, 288 // or if the small one is not. 289 unsigned SmallReg = SmallSrc ? SrcReg : DstReg; 290 unsigned LargeReg = SmallSrc ? DstReg : SrcReg; 291 return any_of(LIS.getInterval(LargeReg), HasCall) || 292 !any_of(LIS.getInterval(SmallReg), HasCall); 293 } 294 295 296 unsigned HexagonRegisterInfo::getRARegister() const { 297 return Hexagon::R31; 298 } 299 300 301 Register HexagonRegisterInfo::getFrameRegister(const MachineFunction 302 &MF) const { 303 const HexagonFrameLowering *TFI = getFrameLowering(MF); 304 if (TFI->hasFP(MF)) 305 return getFrameRegister(); 306 return getStackRegister(); 307 } 308 309 310 unsigned HexagonRegisterInfo::getFrameRegister() const { 311 return Hexagon::R30; 312 } 313 314 315 unsigned HexagonRegisterInfo::getStackRegister() const { 316 return Hexagon::R29; 317 } 318 319 320 unsigned HexagonRegisterInfo::getHexagonSubRegIndex( 321 const TargetRegisterClass &RC, unsigned GenIdx) const { 322 assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi); 323 324 static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi }; 325 static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi }; 326 static const unsigned WSub[] = { Hexagon::wsub_lo, Hexagon::wsub_hi }; 327 328 switch (RC.getID()) { 329 case Hexagon::CtrRegs64RegClassID: 330 case Hexagon::DoubleRegsRegClassID: 331 return ISub[GenIdx]; 332 case Hexagon::HvxWRRegClassID: 333 return VSub[GenIdx]; 334 case Hexagon::HvxVQRRegClassID: 335 return WSub[GenIdx]; 336 } 337 338 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) 339 return getHexagonSubRegIndex(*SuperRC, GenIdx); 340 341 llvm_unreachable("Invalid register class"); 342 } 343 344 bool HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) 345 const { 346 return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF); 347 } 348 349 const TargetRegisterClass * 350 HexagonRegisterInfo::getPointerRegClass(const MachineFunction &MF, 351 unsigned Kind) const { 352 return &Hexagon::IntRegsRegClass; 353 } 354 355 unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const { 356 return Hexagon::R6; 357 } 358 359