1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Hexagon implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "HexagonRegisterInfo.h" 16 #include "Hexagon.h" 17 #include "HexagonMachineFunctionInfo.h" 18 #include "HexagonSubtarget.h" 19 #include "HexagonTargetMachine.h" 20 #include "llvm/ADT/BitVector.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/CodeGen/MachineFrameInfo.h" 23 #include "llvm/CodeGen/MachineFunction.h" 24 #include "llvm/CodeGen/MachineFunctionPass.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/CodeGen/PseudoSourceValue.h" 28 #include "llvm/CodeGen/RegisterScavenging.h" 29 #include "llvm/CodeGen/TargetInstrInfo.h" 30 #include "llvm/IR/Function.h" 31 #include "llvm/IR/Type.h" 32 #include "llvm/MC/MachineLocation.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/ErrorHandling.h" 35 #include "llvm/Support/raw_ostream.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetOptions.h" 38 39 #define GET_REGINFO_TARGET_DESC 40 #include "HexagonGenRegisterInfo.inc" 41 42 using namespace llvm; 43 44 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) 45 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, 46 0/*PC*/, HwMode) {} 47 48 49 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const { 50 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 || 51 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1; 52 } 53 54 const MCPhysReg * 55 HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF, 56 const TargetRegisterClass *RC) const { 57 using namespace Hexagon; 58 59 static const MCPhysReg Int32[] = { 60 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0 61 }; 62 static const MCPhysReg Int64[] = { 63 D0, D1, D2, D3, D4, D5, D6, D7, 0 64 }; 65 static const MCPhysReg Pred[] = { 66 P0, P1, P2, P3, 0 67 }; 68 static const MCPhysReg VecSgl[] = { 69 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13, 70 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, 71 V28, V29, V30, V31, 0 72 }; 73 static const MCPhysReg VecDbl[] = { 74 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0 75 }; 76 77 switch (RC->getID()) { 78 case IntRegsRegClassID: 79 return Int32; 80 case DoubleRegsRegClassID: 81 return Int64; 82 case PredRegsRegClassID: 83 return Pred; 84 case HvxVRRegClassID: 85 return VecSgl; 86 case HvxWRRegClassID: 87 return VecDbl; 88 default: 89 break; 90 } 91 92 static const MCPhysReg Empty[] = { 0 }; 93 #ifndef NDEBUG 94 dbgs() << "Register class: " << getRegClassName(RC) << "\n"; 95 #endif 96 llvm_unreachable("Unexpected register class"); 97 return Empty; 98 } 99 100 101 const MCPhysReg * 102 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 103 static const MCPhysReg CalleeSavedRegsV3[] = { 104 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 105 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 106 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 107 }; 108 109 // Functions that contain a call to __builtin_eh_return also save the first 4 110 // parameter registers. 111 static const MCPhysReg CalleeSavedRegsV3EHReturn[] = { 112 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 113 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 114 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 115 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 116 }; 117 118 bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn(); 119 120 switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) { 121 case Hexagon::ArchEnum::V4: 122 case Hexagon::ArchEnum::V5: 123 case Hexagon::ArchEnum::V55: 124 case Hexagon::ArchEnum::V60: 125 case Hexagon::ArchEnum::V62: 126 case Hexagon::ArchEnum::V65: 127 return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3; 128 } 129 130 llvm_unreachable("Callee saved registers requested for unknown architecture " 131 "version"); 132 } 133 134 135 const uint32_t *HexagonRegisterInfo::getCallPreservedMask( 136 const MachineFunction &MF, CallingConv::ID) const { 137 return HexagonCSR_RegMask; 138 } 139 140 141 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) 142 const { 143 BitVector Reserved(getNumRegs()); 144 Reserved.set(Hexagon::R29); 145 Reserved.set(Hexagon::R30); 146 Reserved.set(Hexagon::R31); 147 Reserved.set(Hexagon::VTMP); 148 149 // Guest registers. 150 Reserved.set(Hexagon::GELR); // G0 151 Reserved.set(Hexagon::GSR); // G1 152 Reserved.set(Hexagon::GOSP); // G2 153 Reserved.set(Hexagon::G3); // G3 154 155 // Control registers. 156 Reserved.set(Hexagon::SA0); // C0 157 Reserved.set(Hexagon::LC0); // C1 158 Reserved.set(Hexagon::SA1); // C2 159 Reserved.set(Hexagon::LC1); // C3 160 Reserved.set(Hexagon::P3_0); // C4 161 Reserved.set(Hexagon::USR); // C8 162 Reserved.set(Hexagon::PC); // C9 163 Reserved.set(Hexagon::UGP); // C10 164 Reserved.set(Hexagon::GP); // C11 165 Reserved.set(Hexagon::CS0); // C12 166 Reserved.set(Hexagon::CS1); // C13 167 Reserved.set(Hexagon::UPCYCLELO); // C14 168 Reserved.set(Hexagon::UPCYCLEHI); // C15 169 Reserved.set(Hexagon::FRAMELIMIT); // C16 170 Reserved.set(Hexagon::FRAMEKEY); // C17 171 Reserved.set(Hexagon::PKTCOUNTLO); // C18 172 Reserved.set(Hexagon::PKTCOUNTHI); // C19 173 Reserved.set(Hexagon::UTIMERLO); // C30 174 Reserved.set(Hexagon::UTIMERHI); // C31 175 // Out of the control registers, only C8 is explicitly defined in 176 // HexagonRegisterInfo.td. If others are defined, make sure to add 177 // them here as well. 178 Reserved.set(Hexagon::C8); 179 Reserved.set(Hexagon::USR_OVF); 180 181 if (MF.getSubtarget<HexagonSubtarget>().hasReservedR19()) 182 Reserved.set(Hexagon::R19); 183 184 for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) 185 markSuperRegs(Reserved, x); 186 187 return Reserved; 188 } 189 190 191 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 192 int SPAdj, unsigned FIOp, 193 RegScavenger *RS) const { 194 // 195 // Hexagon_TODO: Do we need to enforce this for Hexagon? 196 assert(SPAdj == 0 && "Unexpected"); 197 198 MachineInstr &MI = *II; 199 MachineBasicBlock &MB = *MI.getParent(); 200 MachineFunction &MF = *MB.getParent(); 201 auto &HST = MF.getSubtarget<HexagonSubtarget>(); 202 auto &HII = *HST.getInstrInfo(); 203 auto &HFI = *HST.getFrameLowering(); 204 205 unsigned BP = 0; 206 int FI = MI.getOperand(FIOp).getIndex(); 207 // Select the base pointer (BP) and calculate the actual offset from BP 208 // to the beginning of the object at index FI. 209 int Offset = HFI.getFrameIndexReference(MF, FI, BP); 210 // Add the offset from the instruction. 211 int RealOffset = Offset + MI.getOperand(FIOp+1).getImm(); 212 bool IsKill = false; 213 214 unsigned Opc = MI.getOpcode(); 215 switch (Opc) { 216 case Hexagon::PS_fia: 217 MI.setDesc(HII.get(Hexagon::A2_addi)); 218 MI.getOperand(FIOp).ChangeToImmediate(RealOffset); 219 MI.RemoveOperand(FIOp+1); 220 return; 221 case Hexagon::PS_fi: 222 // Set up the instruction for updating below. 223 MI.setDesc(HII.get(Hexagon::A2_addi)); 224 break; 225 } 226 227 if (!HII.isValidOffset(Opc, RealOffset, this)) { 228 // If the offset is not valid, calculate the address in a temporary 229 // register and use it with offset 0. 230 auto &MRI = MF.getRegInfo(); 231 unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); 232 const DebugLoc &DL = MI.getDebugLoc(); 233 BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR) 234 .addReg(BP) 235 .addImm(RealOffset); 236 BP = TmpR; 237 RealOffset = 0; 238 IsKill = true; 239 } 240 241 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill); 242 MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset); 243 } 244 245 246 unsigned HexagonRegisterInfo::getRARegister() const { 247 return Hexagon::R31; 248 } 249 250 251 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction 252 &MF) const { 253 const HexagonFrameLowering *TFI = getFrameLowering(MF); 254 if (TFI->hasFP(MF)) 255 return getFrameRegister(); 256 return getStackRegister(); 257 } 258 259 260 unsigned HexagonRegisterInfo::getFrameRegister() const { 261 return Hexagon::R30; 262 } 263 264 265 unsigned HexagonRegisterInfo::getStackRegister() const { 266 return Hexagon::R29; 267 } 268 269 270 unsigned HexagonRegisterInfo::getHexagonSubRegIndex( 271 const TargetRegisterClass &RC, unsigned GenIdx) const { 272 assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi); 273 274 static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi }; 275 static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi }; 276 277 switch (RC.getID()) { 278 case Hexagon::CtrRegs64RegClassID: 279 case Hexagon::DoubleRegsRegClassID: 280 return ISub[GenIdx]; 281 case Hexagon::HvxWRRegClassID: 282 return VSub[GenIdx]; 283 } 284 285 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) 286 return getHexagonSubRegIndex(*SuperRC, GenIdx); 287 288 llvm_unreachable("Invalid register class"); 289 } 290 291 bool HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) 292 const { 293 return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF); 294 } 295 296 const TargetRegisterClass * 297 HexagonRegisterInfo::getPointerRegClass(const MachineFunction &MF, 298 unsigned Kind) const { 299 return &Hexagon::IntRegsRegClass; 300 } 301 302 unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const { 303 return Hexagon::R6; 304 } 305 306