1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "mcasmparser" 11 12 #include "Hexagon.h" 13 #include "HexagonRegisterInfo.h" 14 #include "HexagonTargetStreamer.h" 15 #include "MCTargetDesc/HexagonBaseInfo.h" 16 #include "MCTargetDesc/HexagonMCELFStreamer.h" 17 #include "MCTargetDesc/HexagonMCChecker.h" 18 #include "MCTargetDesc/HexagonMCExpr.h" 19 #include "MCTargetDesc/HexagonMCShuffler.h" 20 #include "MCTargetDesc/HexagonMCTargetDesc.h" 21 #include "MCTargetDesc/HexagonMCAsmInfo.h" 22 #include "MCTargetDesc/HexagonShuffler.h" 23 #include "llvm/ADT/SmallString.h" 24 #include "llvm/ADT/SmallVector.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/Twine.h" 27 #include "llvm/MC/MCContext.h" 28 #include "llvm/MC/MCELFStreamer.h" 29 #include "llvm/MC/MCExpr.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/MC/MCParser/MCAsmLexer.h" 32 #include "llvm/MC/MCParser/MCAsmParser.h" 33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 34 #include "llvm/MC/MCStreamer.h" 35 #include "llvm/MC/MCSectionELF.h" 36 #include "llvm/MC/MCSubtargetInfo.h" 37 #include "llvm/MC/MCTargetAsmParser.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ELF.h" 41 #include "llvm/Support/SourceMgr.h" 42 #include "llvm/Support/MemoryBuffer.h" 43 #include "llvm/Support/TargetRegistry.h" 44 #include "llvm/Support/raw_ostream.h" 45 #include <sstream> 46 47 using namespace llvm; 48 49 static cl::opt<bool> EnableFutureRegs("mfuture-regs", 50 cl::desc("Enable future registers")); 51 52 static cl::opt<bool> WarnMissingParenthesis("mwarn-missing-parenthesis", 53 cl::desc("Warn for missing parenthesis around predicate registers"), 54 cl::init(true)); 55 static cl::opt<bool> ErrorMissingParenthesis("merror-missing-parenthesis", 56 cl::desc("Error for missing parenthesis around predicate registers"), 57 cl::init(false)); 58 static cl::opt<bool> WarnSignedMismatch("mwarn-sign-mismatch", 59 cl::desc("Warn for mismatching a signed and unsigned value"), 60 cl::init(true)); 61 static cl::opt<bool> WarnNoncontigiousRegister("mwarn-noncontigious-register", 62 cl::desc("Warn for register names that arent contigious"), 63 cl::init(true)); 64 static cl::opt<bool> ErrorNoncontigiousRegister("merror-noncontigious-register", 65 cl::desc("Error for register names that aren't contigious"), 66 cl::init(false)); 67 68 69 namespace { 70 struct HexagonOperand; 71 72 class HexagonAsmParser : public MCTargetAsmParser { 73 74 HexagonTargetStreamer &getTargetStreamer() { 75 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer(); 76 return static_cast<HexagonTargetStreamer &>(TS); 77 } 78 79 MCAsmParser &Parser; 80 MCAssembler *Assembler; 81 MCInstrInfo const &MCII; 82 MCInst MCB; 83 bool InBrackets; 84 85 MCAsmParser &getParser() const { return Parser; } 86 MCAssembler *getAssembler() const { return Assembler; } 87 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 88 89 bool equalIsAsmAssignment() override { return false; } 90 bool isLabel(AsmToken &Token) override; 91 92 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 93 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 94 bool ParseDirectiveFalign(unsigned Size, SMLoc L); 95 96 virtual bool ParseRegister(unsigned &RegNo, 97 SMLoc &StartLoc, 98 SMLoc &EndLoc) override; 99 bool ParseDirectiveSubsection(SMLoc L); 100 bool ParseDirectiveValue(unsigned Size, SMLoc L); 101 bool ParseDirectiveComm(bool IsLocal, SMLoc L); 102 bool RegisterMatchesArch(unsigned MatchNum) const; 103 104 bool matchBundleOptions(); 105 bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc); 106 bool finishBundle(SMLoc IDLoc, MCStreamer &Out); 107 void canonicalizeImmediates(MCInst &MCI); 108 bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc, 109 OperandVector &InstOperands, uint64_t &ErrorInfo, 110 bool MatchingInlineAsm, bool &MustExtend); 111 112 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 113 OperandVector &Operands, MCStreamer &Out, 114 uint64_t &ErrorInfo, bool MatchingInlineAsm) override; 115 116 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; 117 void OutOfRange(SMLoc IDLoc, long long Val, long long Max); 118 int processInstruction(MCInst &Inst, OperandVector const &Operands, 119 SMLoc IDLoc, bool &MustExtend); 120 121 // Check if we have an assembler and, if so, set the ELF e_header flags. 122 void chksetELFHeaderEFlags(unsigned flags) { 123 if (getAssembler()) 124 getAssembler()->setELFHeaderEFlags(flags); 125 } 126 127 /// @name Auto-generated Match Functions 128 /// { 129 130 #define GET_ASSEMBLER_HEADER 131 #include "HexagonGenAsmMatcher.inc" 132 133 /// } 134 135 public: 136 HexagonAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser, 137 const MCInstrInfo &MII, const MCTargetOptions &Options) 138 : MCTargetAsmParser(Options, _STI), Parser(_Parser), 139 MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) { 140 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); 141 142 MCAsmParserExtension::Initialize(_Parser); 143 144 Assembler = nullptr; 145 // FIXME: need better way to detect AsmStreamer (upstream removed getKind()) 146 if (!Parser.getStreamer().hasRawTextSupport()) { 147 MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer()); 148 Assembler = &MES->getAssembler(); 149 } 150 } 151 152 bool mustExtend(OperandVector &Operands); 153 bool splitIdentifier(OperandVector &Operands); 154 bool parseOperand(OperandVector &Operands); 155 bool parseInstruction(OperandVector &Operands); 156 bool implicitExpressionLocation(OperandVector &Operands); 157 bool parseExpressionOrOperand(OperandVector &Operands); 158 bool parseExpression(MCExpr const *& Expr); 159 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 160 SMLoc NameLoc, OperandVector &Operands) override 161 { 162 llvm_unreachable("Unimplemented"); 163 } 164 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 165 AsmToken ID, OperandVector &Operands) override; 166 167 virtual bool ParseDirective(AsmToken DirectiveID) override; 168 }; 169 170 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine 171 /// instruction. 172 struct HexagonOperand : public MCParsedAsmOperand { 173 enum KindTy { Token, Immediate, Register } Kind; 174 175 SMLoc StartLoc, EndLoc; 176 177 struct TokTy { 178 const char *Data; 179 unsigned Length; 180 }; 181 182 struct RegTy { 183 unsigned RegNum; 184 }; 185 186 struct ImmTy { 187 const MCExpr *Val; 188 bool MustExtend; 189 }; 190 191 struct InstTy { 192 OperandVector *SubInsts; 193 }; 194 195 union { 196 struct TokTy Tok; 197 struct RegTy Reg; 198 struct ImmTy Imm; 199 }; 200 201 HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 202 203 public: 204 HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() { 205 Kind = o.Kind; 206 StartLoc = o.StartLoc; 207 EndLoc = o.EndLoc; 208 switch (Kind) { 209 case Register: 210 Reg = o.Reg; 211 break; 212 case Immediate: 213 Imm = o.Imm; 214 break; 215 case Token: 216 Tok = o.Tok; 217 break; 218 } 219 } 220 221 /// getStartLoc - Get the location of the first token of this operand. 222 SMLoc getStartLoc() const { return StartLoc; } 223 224 /// getEndLoc - Get the location of the last token of this operand. 225 SMLoc getEndLoc() const { return EndLoc; } 226 227 unsigned getReg() const { 228 assert(Kind == Register && "Invalid access!"); 229 return Reg.RegNum; 230 } 231 232 const MCExpr *getImm() const { 233 assert(Kind == Immediate && "Invalid access!"); 234 return Imm.Val; 235 } 236 237 bool isToken() const { return Kind == Token; } 238 bool isImm() const { return Kind == Immediate; } 239 bool isMem() const { llvm_unreachable("No isMem"); } 240 bool isReg() const { return Kind == Register; } 241 242 bool CheckImmRange(int immBits, int zeroBits, bool isSigned, 243 bool isRelocatable, bool Extendable) const { 244 if (Kind == Immediate) { 245 const MCExpr *myMCExpr = getImm(); 246 if (Imm.MustExtend && !Extendable) 247 return false; 248 int64_t Res; 249 if (myMCExpr->evaluateAsAbsolute(Res)) { 250 int bits = immBits + zeroBits; 251 // Field bit range is zerobits + bits 252 // zeroBits must be 0 253 if (Res & ((1 << zeroBits) - 1)) 254 return false; 255 if (isSigned) { 256 if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1))) 257 return true; 258 } else { 259 if (bits == 64) 260 return true; 261 if (Res >= 0) 262 return ((uint64_t)Res < (uint64_t)(1ULL << bits)) ? true : false; 263 else { 264 const int64_t high_bit_set = 1ULL << 63; 265 const uint64_t mask = (high_bit_set >> (63 - bits)); 266 return (((uint64_t)Res & mask) == mask) ? true : false; 267 } 268 } 269 } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable) 270 return true; 271 else if (myMCExpr->getKind() == MCExpr::Binary || 272 myMCExpr->getKind() == MCExpr::Unary) 273 return true; 274 } 275 return false; 276 } 277 278 bool isf32Ext() const { return false; } 279 bool iss32Imm() const { return CheckImmRange(32, 0, true, true, false); } 280 bool iss8Imm() const { return CheckImmRange(8, 0, true, false, false); } 281 bool iss8Imm64() const { return CheckImmRange(8, 0, true, true, false); } 282 bool iss7Imm() const { return CheckImmRange(7, 0, true, false, false); } 283 bool iss6Imm() const { return CheckImmRange(6, 0, true, false, false); } 284 bool iss4Imm() const { return CheckImmRange(4, 0, true, false, false); } 285 bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); } 286 bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); } 287 bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); } 288 bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); } 289 bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); } 290 bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); } 291 bool iss3Imm() const { return CheckImmRange(3, 0, true, false, false); } 292 293 bool isu64Imm() const { return CheckImmRange(64, 0, false, true, true); } 294 bool isu32Imm() const { return CheckImmRange(32, 0, false, true, false); } 295 bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); } 296 bool isu16Imm() const { return CheckImmRange(16, 0, false, true, false); } 297 bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); } 298 bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); } 299 bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); } 300 bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); } 301 bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); } 302 bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); } 303 bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); } 304 bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); } 305 bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); } 306 bool isu10Imm() const { return CheckImmRange(10, 0, false, false, false); } 307 bool isu9Imm() const { return CheckImmRange(9, 0, false, false, false); } 308 bool isu8Imm() const { return CheckImmRange(8, 0, false, false, false); } 309 bool isu7Imm() const { return CheckImmRange(7, 0, false, false, false); } 310 bool isu6Imm() const { return CheckImmRange(6, 0, false, false, false); } 311 bool isu5Imm() const { return CheckImmRange(5, 0, false, false, false); } 312 bool isu4Imm() const { return CheckImmRange(4, 0, false, false, false); } 313 bool isu3Imm() const { return CheckImmRange(3, 0, false, false, false); } 314 bool isu2Imm() const { return CheckImmRange(2, 0, false, false, false); } 315 bool isu1Imm() const { return CheckImmRange(1, 0, false, false, false); } 316 317 bool ism6Imm() const { return CheckImmRange(6, 0, false, false, false); } 318 bool isn8Imm() const { return CheckImmRange(8, 0, false, false, false); } 319 320 bool iss16Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); } 321 bool iss12Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); } 322 bool iss10Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); } 323 bool iss9Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); } 324 bool iss8Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); } 325 bool iss7Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); } 326 bool iss6Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); } 327 bool iss11_0Ext() const { 328 return CheckImmRange(11 + 26, 0, true, true, true); 329 } 330 bool iss11_1Ext() const { 331 return CheckImmRange(11 + 26, 1, true, true, true); 332 } 333 bool iss11_2Ext() const { 334 return CheckImmRange(11 + 26, 2, true, true, true); 335 } 336 bool iss11_3Ext() const { 337 return CheckImmRange(11 + 26, 3, true, true, true); 338 } 339 340 bool isu6Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); } 341 bool isu7Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); } 342 bool isu8Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); } 343 bool isu9Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); } 344 bool isu10Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); } 345 bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); } 346 bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); } 347 bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); } 348 bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); } 349 bool isu32MustExt() const { return isImm() && Imm.MustExtend; } 350 351 void addRegOperands(MCInst &Inst, unsigned N) const { 352 assert(N == 1 && "Invalid number of operands!"); 353 Inst.addOperand(MCOperand::createReg(getReg())); 354 } 355 356 void addImmOperands(MCInst &Inst, unsigned N) const { 357 assert(N == 1 && "Invalid number of operands!"); 358 Inst.addOperand(MCOperand::createExpr(getImm())); 359 } 360 361 void addSignedImmOperands(MCInst &Inst, unsigned N) const { 362 assert(N == 1 && "Invalid number of operands!"); 363 MCExpr const *Expr = getImm(); 364 int64_t Value; 365 if (!Expr->evaluateAsAbsolute(Value)) { 366 Inst.addOperand(MCOperand::createExpr(Expr)); 367 return; 368 } 369 int64_t Extended = SignExtend64 (Value, 32); 370 if ((Extended < 0) == (Value < 0)) { 371 Inst.addOperand(MCOperand::createExpr(Expr)); 372 return; 373 } 374 // Flip bit 33 to signal signed unsigned mismatch 375 Extended ^= 0x100000000; 376 Inst.addOperand(MCOperand::createImm(Extended)); 377 } 378 379 void addf32ExtOperands(MCInst &Inst, unsigned N) const { 380 addImmOperands(Inst, N); 381 } 382 383 void adds32ImmOperands(MCInst &Inst, unsigned N) const { 384 addSignedImmOperands(Inst, N); 385 } 386 void adds8ImmOperands(MCInst &Inst, unsigned N) const { 387 addSignedImmOperands(Inst, N); 388 } 389 void adds8Imm64Operands(MCInst &Inst, unsigned N) const { 390 addSignedImmOperands(Inst, N); 391 } 392 void adds6ImmOperands(MCInst &Inst, unsigned N) const { 393 addSignedImmOperands(Inst, N); 394 } 395 void adds4ImmOperands(MCInst &Inst, unsigned N) const { 396 addSignedImmOperands(Inst, N); 397 } 398 void adds4_0ImmOperands(MCInst &Inst, unsigned N) const { 399 addSignedImmOperands(Inst, N); 400 } 401 void adds4_1ImmOperands(MCInst &Inst, unsigned N) const { 402 addSignedImmOperands(Inst, N); 403 } 404 void adds4_2ImmOperands(MCInst &Inst, unsigned N) const { 405 addSignedImmOperands(Inst, N); 406 } 407 void adds4_3ImmOperands(MCInst &Inst, unsigned N) const { 408 addSignedImmOperands(Inst, N); 409 } 410 void adds3ImmOperands(MCInst &Inst, unsigned N) const { 411 addSignedImmOperands(Inst, N); 412 } 413 414 void addu64ImmOperands(MCInst &Inst, unsigned N) const { 415 addImmOperands(Inst, N); 416 } 417 void addu32ImmOperands(MCInst &Inst, unsigned N) const { 418 addImmOperands(Inst, N); 419 } 420 void addu26_6ImmOperands(MCInst &Inst, unsigned N) const { 421 addImmOperands(Inst, N); 422 } 423 void addu16ImmOperands(MCInst &Inst, unsigned N) const { 424 addImmOperands(Inst, N); 425 } 426 void addu16_0ImmOperands(MCInst &Inst, unsigned N) const { 427 addImmOperands(Inst, N); 428 } 429 void addu16_1ImmOperands(MCInst &Inst, unsigned N) const { 430 addImmOperands(Inst, N); 431 } 432 void addu16_2ImmOperands(MCInst &Inst, unsigned N) const { 433 addImmOperands(Inst, N); 434 } 435 void addu16_3ImmOperands(MCInst &Inst, unsigned N) const { 436 addImmOperands(Inst, N); 437 } 438 void addu11_3ImmOperands(MCInst &Inst, unsigned N) const { 439 addImmOperands(Inst, N); 440 } 441 void addu10ImmOperands(MCInst &Inst, unsigned N) const { 442 addImmOperands(Inst, N); 443 } 444 void addu9ImmOperands(MCInst &Inst, unsigned N) const { 445 addImmOperands(Inst, N); 446 } 447 void addu8ImmOperands(MCInst &Inst, unsigned N) const { 448 addImmOperands(Inst, N); 449 } 450 void addu7ImmOperands(MCInst &Inst, unsigned N) const { 451 addImmOperands(Inst, N); 452 } 453 void addu6ImmOperands(MCInst &Inst, unsigned N) const { 454 addImmOperands(Inst, N); 455 } 456 void addu6_0ImmOperands(MCInst &Inst, unsigned N) const { 457 addImmOperands(Inst, N); 458 } 459 void addu6_1ImmOperands(MCInst &Inst, unsigned N) const { 460 addImmOperands(Inst, N); 461 } 462 void addu6_2ImmOperands(MCInst &Inst, unsigned N) const { 463 addImmOperands(Inst, N); 464 } 465 void addu6_3ImmOperands(MCInst &Inst, unsigned N) const { 466 addImmOperands(Inst, N); 467 } 468 void addu5ImmOperands(MCInst &Inst, unsigned N) const { 469 addImmOperands(Inst, N); 470 } 471 void addu4ImmOperands(MCInst &Inst, unsigned N) const { 472 addImmOperands(Inst, N); 473 } 474 void addu3ImmOperands(MCInst &Inst, unsigned N) const { 475 addImmOperands(Inst, N); 476 } 477 void addu2ImmOperands(MCInst &Inst, unsigned N) const { 478 addImmOperands(Inst, N); 479 } 480 void addu1ImmOperands(MCInst &Inst, unsigned N) const { 481 addImmOperands(Inst, N); 482 } 483 484 void addm6ImmOperands(MCInst &Inst, unsigned N) const { 485 addImmOperands(Inst, N); 486 } 487 void addn8ImmOperands(MCInst &Inst, unsigned N) const { 488 addImmOperands(Inst, N); 489 } 490 491 void adds16ExtOperands(MCInst &Inst, unsigned N) const { 492 addSignedImmOperands(Inst, N); 493 } 494 void adds12ExtOperands(MCInst &Inst, unsigned N) const { 495 addSignedImmOperands(Inst, N); 496 } 497 void adds10ExtOperands(MCInst &Inst, unsigned N) const { 498 addSignedImmOperands(Inst, N); 499 } 500 void adds9ExtOperands(MCInst &Inst, unsigned N) const { 501 addSignedImmOperands(Inst, N); 502 } 503 void adds8ExtOperands(MCInst &Inst, unsigned N) const { 504 addSignedImmOperands(Inst, N); 505 } 506 void adds6ExtOperands(MCInst &Inst, unsigned N) const { 507 addSignedImmOperands(Inst, N); 508 } 509 void adds11_0ExtOperands(MCInst &Inst, unsigned N) const { 510 addSignedImmOperands(Inst, N); 511 } 512 void adds11_1ExtOperands(MCInst &Inst, unsigned N) const { 513 addSignedImmOperands(Inst, N); 514 } 515 void adds11_2ExtOperands(MCInst &Inst, unsigned N) const { 516 addSignedImmOperands(Inst, N); 517 } 518 void adds11_3ExtOperands(MCInst &Inst, unsigned N) const { 519 addSignedImmOperands(Inst, N); 520 } 521 522 void addu6ExtOperands(MCInst &Inst, unsigned N) const { 523 addImmOperands(Inst, N); 524 } 525 void addu7ExtOperands(MCInst &Inst, unsigned N) const { 526 addImmOperands(Inst, N); 527 } 528 void addu8ExtOperands(MCInst &Inst, unsigned N) const { 529 addImmOperands(Inst, N); 530 } 531 void addu9ExtOperands(MCInst &Inst, unsigned N) const { 532 addImmOperands(Inst, N); 533 } 534 void addu10ExtOperands(MCInst &Inst, unsigned N) const { 535 addImmOperands(Inst, N); 536 } 537 void addu6_0ExtOperands(MCInst &Inst, unsigned N) const { 538 addImmOperands(Inst, N); 539 } 540 void addu6_1ExtOperands(MCInst &Inst, unsigned N) const { 541 addImmOperands(Inst, N); 542 } 543 void addu6_2ExtOperands(MCInst &Inst, unsigned N) const { 544 addImmOperands(Inst, N); 545 } 546 void addu6_3ExtOperands(MCInst &Inst, unsigned N) const { 547 addImmOperands(Inst, N); 548 } 549 void addu32MustExtOperands(MCInst &Inst, unsigned N) const { 550 addImmOperands(Inst, N); 551 } 552 553 void adds4_6ImmOperands(MCInst &Inst, unsigned N) const { 554 assert(N == 1 && "Invalid number of operands!"); 555 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 556 Inst.addOperand(MCOperand::createImm(CE->getValue() << 6)); 557 } 558 559 void adds3_6ImmOperands(MCInst &Inst, unsigned N) const { 560 assert(N == 1 && "Invalid number of operands!"); 561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 562 Inst.addOperand(MCOperand::createImm(CE->getValue() << 6)); 563 } 564 565 StringRef getToken() const { 566 assert(Kind == Token && "Invalid access!"); 567 return StringRef(Tok.Data, Tok.Length); 568 } 569 570 virtual void print(raw_ostream &OS) const; 571 572 static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) { 573 HexagonOperand *Op = new HexagonOperand(Token); 574 Op->Tok.Data = Str.data(); 575 Op->Tok.Length = Str.size(); 576 Op->StartLoc = S; 577 Op->EndLoc = S; 578 return std::unique_ptr<HexagonOperand>(Op); 579 } 580 581 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S, 582 SMLoc E) { 583 HexagonOperand *Op = new HexagonOperand(Register); 584 Op->Reg.RegNum = RegNum; 585 Op->StartLoc = S; 586 Op->EndLoc = E; 587 return std::unique_ptr<HexagonOperand>(Op); 588 } 589 590 static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S, 591 SMLoc E) { 592 HexagonOperand *Op = new HexagonOperand(Immediate); 593 Op->Imm.Val = Val; 594 Op->Imm.MustExtend = false; 595 Op->StartLoc = S; 596 Op->EndLoc = E; 597 return std::unique_ptr<HexagonOperand>(Op); 598 } 599 }; 600 601 } // end anonymous namespace. 602 603 void HexagonOperand::print(raw_ostream &OS) const { 604 switch (Kind) { 605 case Immediate: 606 getImm()->print(OS, nullptr); 607 break; 608 case Register: 609 OS << "<register R"; 610 OS << getReg() << ">"; 611 break; 612 case Token: 613 OS << "'" << getToken() << "'"; 614 break; 615 } 616 } 617 618 /// @name Auto-generated Match Functions 619 static unsigned MatchRegisterName(StringRef Name); 620 621 bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) { 622 DEBUG(dbgs() << "Bundle:"); 623 DEBUG(MCB.dump_pretty(dbgs())); 624 DEBUG(dbgs() << "--\n"); 625 626 // Check the bundle for errors. 627 const MCRegisterInfo *RI = getContext().getRegisterInfo(); 628 HexagonMCChecker Check(MCII, getSTI(), MCB, MCB, *RI); 629 630 bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(), 631 getContext(), MCB, 632 &Check); 633 634 while (Check.getNextErrInfo() == true) { 635 unsigned Reg = Check.getErrRegister(); 636 Twine R(RI->getName(Reg)); 637 638 uint64_t Err = Check.getError(); 639 if (Err != HexagonMCErrInfo::CHECK_SUCCESS) { 640 if (HexagonMCErrInfo::CHECK_ERROR_BRANCHES & Err) 641 Error(IDLoc, 642 "unconditional branch cannot precede another branch in packet"); 643 644 if (HexagonMCErrInfo::CHECK_ERROR_NEWP & Err || 645 HexagonMCErrInfo::CHECK_ERROR_NEWV & Err) 646 Error(IDLoc, "register `" + R + 647 "' used with `.new' " 648 "but not validly modified in the same packet"); 649 650 if (HexagonMCErrInfo::CHECK_ERROR_REGISTERS & Err) 651 Error(IDLoc, "register `" + R + "' modified more than once"); 652 653 if (HexagonMCErrInfo::CHECK_ERROR_READONLY & Err) 654 Error(IDLoc, "cannot write to read-only register `" + R + "'"); 655 656 if (HexagonMCErrInfo::CHECK_ERROR_LOOP & Err) 657 Error(IDLoc, "loop-setup and some branch instructions " 658 "cannot be in the same packet"); 659 660 if (HexagonMCErrInfo::CHECK_ERROR_ENDLOOP & Err) { 661 Twine N(HexagonMCInstrInfo::isInnerLoop(MCB) ? '0' : '1'); 662 Error(IDLoc, "packet marked with `:endloop" + N + "' " + 663 "cannot contain instructions that modify register " + 664 "`" + R + "'"); 665 } 666 667 if (HexagonMCErrInfo::CHECK_ERROR_SOLO & Err) 668 Error(IDLoc, 669 "instruction cannot appear in packet with other instructions"); 670 671 if (HexagonMCErrInfo::CHECK_ERROR_NOSLOTS & Err) 672 Error(IDLoc, "too many slots used in packet"); 673 674 if (Err & HexagonMCErrInfo::CHECK_ERROR_SHUFFLE) { 675 uint64_t Erm = Check.getShuffleError(); 676 677 if (HexagonShuffler::SHUFFLE_ERROR_INVALID == Erm) 678 Error(IDLoc, "invalid instruction packet"); 679 else if (HexagonShuffler::SHUFFLE_ERROR_STORES == Erm) 680 Error(IDLoc, "invalid instruction packet: too many stores"); 681 else if (HexagonShuffler::SHUFFLE_ERROR_LOADS == Erm) 682 Error(IDLoc, "invalid instruction packet: too many loads"); 683 else if (HexagonShuffler::SHUFFLE_ERROR_BRANCHES == Erm) 684 Error(IDLoc, "too many branches in packet"); 685 else if (HexagonShuffler::SHUFFLE_ERROR_NOSLOTS == Erm) 686 Error(IDLoc, "invalid instruction packet: out of slots"); 687 else if (HexagonShuffler::SHUFFLE_ERROR_SLOTS == Erm) 688 Error(IDLoc, "invalid instruction packet: slot error"); 689 else if (HexagonShuffler::SHUFFLE_ERROR_ERRATA2 == Erm) 690 Error(IDLoc, "v60 packet violation"); 691 else if (HexagonShuffler::SHUFFLE_ERROR_STORE_LOAD_CONFLICT == Erm) 692 Error(IDLoc, "slot 0 instruction does not allow slot 1 store"); 693 else 694 Error(IDLoc, "unknown error in instruction packet"); 695 } 696 } 697 698 unsigned Warn = Check.getWarning(); 699 if (Warn != HexagonMCErrInfo::CHECK_SUCCESS) { 700 if (HexagonMCErrInfo::CHECK_WARN_CURRENT & Warn) 701 Warning(IDLoc, "register `" + R + "' used with `.cur' " 702 "but not used in the same packet"); 703 else if (HexagonMCErrInfo::CHECK_WARN_TEMPORARY & Warn) 704 Warning(IDLoc, "register `" + R + "' used with `.tmp' " 705 "but not used in the same packet"); 706 } 707 } 708 709 if (CheckOk) { 710 MCB.setLoc(IDLoc); 711 if (HexagonMCInstrInfo::bundleSize(MCB) == 0) { 712 assert(!HexagonMCInstrInfo::isInnerLoop(MCB)); 713 assert(!HexagonMCInstrInfo::isOuterLoop(MCB)); 714 // Empty packets are valid yet aren't emitted 715 return false; 716 } 717 Out.EmitInstruction(MCB, getSTI()); 718 } else { 719 // If compounding and duplexing didn't reduce the size below 720 // 4 or less we have a packet that is too big. 721 if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) { 722 Error(IDLoc, "invalid instruction packet: out of slots"); 723 return true; // Error 724 } 725 } 726 727 return false; // No error 728 } 729 730 bool HexagonAsmParser::matchBundleOptions() { 731 MCAsmParser &Parser = getParser(); 732 MCAsmLexer &Lexer = getLexer(); 733 while (true) { 734 if (!Parser.getTok().is(AsmToken::Colon)) 735 return false; 736 Lexer.Lex(); 737 StringRef Option = Parser.getTok().getString(); 738 if (Option.compare_lower("endloop0") == 0) 739 HexagonMCInstrInfo::setInnerLoop(MCB); 740 else if (Option.compare_lower("endloop1") == 0) 741 HexagonMCInstrInfo::setOuterLoop(MCB); 742 else if (Option.compare_lower("mem_noshuf") == 0) 743 HexagonMCInstrInfo::setMemReorderDisabled(MCB); 744 else if (Option.compare_lower("mem_shuf") == 0) 745 HexagonMCInstrInfo::setMemStoreReorderEnabled(MCB); 746 else 747 return true; 748 Lexer.Lex(); 749 } 750 } 751 752 // For instruction aliases, immediates are generated rather than 753 // MCConstantExpr. Convert them for uniform MCExpr. 754 // Also check for signed/unsigned mismatches and warn 755 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) { 756 MCInst NewInst; 757 NewInst.setOpcode(MCI.getOpcode()); 758 for (MCOperand &I : MCI) 759 if (I.isImm()) { 760 int64_t Value (I.getImm()); 761 if ((Value & 0x100000000) != (Value & 0x80000000)) { 762 // Detect flipped bit 33 wrt bit 32 and signal warning 763 Value ^= 0x100000000; 764 if (WarnSignedMismatch) 765 Warning (MCI.getLoc(), "Signed/Unsigned mismatch"); 766 } 767 NewInst.addOperand(MCOperand::createExpr( 768 MCConstantExpr::create(Value, getContext()))); 769 } 770 else 771 NewInst.addOperand(I); 772 MCI = NewInst; 773 } 774 775 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc, 776 OperandVector &InstOperands, 777 uint64_t &ErrorInfo, 778 bool MatchingInlineAsm, 779 bool &MustExtend) { 780 // Perform matching with tablegen asmmatcher generated function 781 int result = 782 MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm); 783 if (result == Match_Success) { 784 MCI.setLoc(IDLoc); 785 MustExtend = mustExtend(InstOperands); 786 canonicalizeImmediates(MCI); 787 result = processInstruction(MCI, InstOperands, IDLoc, MustExtend); 788 789 DEBUG(dbgs() << "Insn:"); 790 DEBUG(MCI.dump_pretty(dbgs())); 791 DEBUG(dbgs() << "\n\n"); 792 793 MCI.setLoc(IDLoc); 794 } 795 796 // Create instruction operand for bundle instruction 797 // Break this into a separate function Code here is less readable 798 // Think about how to get an instruction error to report correctly. 799 // SMLoc will return the "{" 800 switch (result) { 801 default: 802 break; 803 case Match_Success: 804 return false; 805 case Match_MissingFeature: 806 return Error(IDLoc, "invalid instruction"); 807 case Match_MnemonicFail: 808 return Error(IDLoc, "unrecognized instruction"); 809 case Match_InvalidOperand: 810 SMLoc ErrorLoc = IDLoc; 811 if (ErrorInfo != ~0U) { 812 if (ErrorInfo >= InstOperands.size()) 813 return Error(IDLoc, "too few operands for instruction"); 814 815 ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get())) 816 ->getStartLoc(); 817 if (ErrorLoc == SMLoc()) 818 ErrorLoc = IDLoc; 819 } 820 return Error(ErrorLoc, "invalid operand for instruction"); 821 } 822 llvm_unreachable("Implement any new match types added!"); 823 } 824 825 bool HexagonAsmParser::mustExtend(OperandVector &Operands) { 826 unsigned Count = 0; 827 for (std::unique_ptr<MCParsedAsmOperand> &i : Operands) 828 if (i->isImm()) 829 if (static_cast<HexagonOperand *>(i.get())->Imm.MustExtend) 830 ++Count; 831 // Multiple extenders should have been filtered by iss9Ext et. al. 832 assert(Count < 2 && "Multiple extenders"); 833 return Count == 1; 834 } 835 836 bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 837 OperandVector &Operands, 838 MCStreamer &Out, 839 uint64_t &ErrorInfo, 840 bool MatchingInlineAsm) { 841 if (!InBrackets) { 842 MCB.clear(); 843 MCB.addOperand(MCOperand::createImm(0)); 844 } 845 HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]); 846 if (FirstOperand.isToken() && FirstOperand.getToken() == "{") { 847 assert(Operands.size() == 1 && "Brackets should be by themselves"); 848 if (InBrackets) { 849 getParser().Error(IDLoc, "Already in a packet"); 850 return true; 851 } 852 InBrackets = true; 853 return false; 854 } 855 if (FirstOperand.isToken() && FirstOperand.getToken() == "}") { 856 assert(Operands.size() == 1 && "Brackets should be by themselves"); 857 if (!InBrackets) { 858 getParser().Error(IDLoc, "Not in a packet"); 859 return true; 860 } 861 InBrackets = false; 862 if (matchBundleOptions()) 863 return true; 864 return finishBundle(IDLoc, Out); 865 } 866 MCInst *SubInst = new (getParser().getContext()) MCInst; 867 bool MustExtend = false; 868 if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo, 869 MatchingInlineAsm, MustExtend)) 870 return true; 871 HexagonMCInstrInfo::extendIfNeeded( 872 getParser().getContext(), MCII, MCB, *SubInst, 873 HexagonMCInstrInfo::isExtended(MCII, *SubInst) || MustExtend); 874 MCB.addOperand(MCOperand::createInst(SubInst)); 875 if (!InBrackets) 876 return finishBundle(IDLoc, Out); 877 return false; 878 } 879 880 /// ParseDirective parses the Hexagon specific directives 881 bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) { 882 StringRef IDVal = DirectiveID.getIdentifier(); 883 if ((IDVal.lower() == ".word") || (IDVal.lower() == ".4byte")) 884 return ParseDirectiveValue(4, DirectiveID.getLoc()); 885 if (IDVal.lower() == ".short" || IDVal.lower() == ".hword" || 886 IDVal.lower() == ".half") 887 return ParseDirectiveValue(2, DirectiveID.getLoc()); 888 if (IDVal.lower() == ".falign") 889 return ParseDirectiveFalign(256, DirectiveID.getLoc()); 890 if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon")) 891 return ParseDirectiveComm(true, DirectiveID.getLoc()); 892 if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common")) 893 return ParseDirectiveComm(false, DirectiveID.getLoc()); 894 if (IDVal.lower() == ".subsection") 895 return ParseDirectiveSubsection(DirectiveID.getLoc()); 896 897 return true; 898 } 899 bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) { 900 const MCExpr *Subsection = 0; 901 int64_t Res; 902 903 assert((getLexer().isNot(AsmToken::EndOfStatement)) && 904 "Invalid subsection directive"); 905 getParser().parseExpression(Subsection); 906 907 if (!Subsection->evaluateAsAbsolute(Res)) 908 return Error(L, "Cannot evaluate subsection number"); 909 910 if (getLexer().isNot(AsmToken::EndOfStatement)) 911 return TokError("unexpected token in directive"); 912 913 // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the 914 // negative subsections together and in the same order but at the opposite 915 // end of the section. Only legacy hexagon-gcc created assembly code 916 // used negative subsections. 917 if ((Res < 0) && (Res > -8193)) 918 Subsection = MCConstantExpr::create(8192 + Res, this->getContext()); 919 920 getStreamer().SubSection(Subsection); 921 return false; 922 } 923 924 /// ::= .falign [expression] 925 bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) { 926 927 int64_t MaxBytesToFill = 15; 928 929 // if there is an arguement 930 if (getLexer().isNot(AsmToken::EndOfStatement)) { 931 const MCExpr *Value; 932 SMLoc ExprLoc = L; 933 934 // Make sure we have a number (false is returned if expression is a number) 935 if (getParser().parseExpression(Value) == false) { 936 // Make sure this is a number that is in range 937 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value); 938 uint64_t IntValue = MCE->getValue(); 939 if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue)) 940 return Error(ExprLoc, "literal value out of range (256) for falign"); 941 MaxBytesToFill = IntValue; 942 Lex(); 943 } else { 944 return Error(ExprLoc, "not a valid expression for falign directive"); 945 } 946 } 947 948 getTargetStreamer().emitFAlign(16, MaxBytesToFill); 949 Lex(); 950 951 return false; 952 } 953 954 /// ::= .word [ expression (, expression)* ] 955 bool HexagonAsmParser::ParseDirectiveValue(unsigned Size, SMLoc L) { 956 if (getLexer().isNot(AsmToken::EndOfStatement)) { 957 958 for (;;) { 959 const MCExpr *Value; 960 SMLoc ExprLoc = L; 961 if (getParser().parseExpression(Value)) 962 return true; 963 964 // Special case constant expressions to match code generator. 965 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value)) { 966 assert(Size <= 8 && "Invalid size"); 967 uint64_t IntValue = MCE->getValue(); 968 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 969 return Error(ExprLoc, "literal value out of range for directive"); 970 getStreamer().EmitIntValue(IntValue, Size); 971 } else 972 getStreamer().EmitValue(Value, Size); 973 974 if (getLexer().is(AsmToken::EndOfStatement)) 975 break; 976 977 // FIXME: Improve diagnostic. 978 if (getLexer().isNot(AsmToken::Comma)) 979 return TokError("unexpected token in directive"); 980 Lex(); 981 } 982 } 983 984 Lex(); 985 return false; 986 } 987 988 // This is largely a copy of AsmParser's ParseDirectiveComm extended to 989 // accept a 3rd argument, AccessAlignment which indicates the smallest 990 // memory access made to the symbol, expressed in bytes. If no 991 // AccessAlignment is specified it defaults to the Alignment Value. 992 // Hexagon's .lcomm: 993 // .lcomm Symbol, Length, Alignment, AccessAlignment 994 bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) { 995 // FIXME: need better way to detect if AsmStreamer (upstream removed 996 // getKind()) 997 if (getStreamer().hasRawTextSupport()) 998 return true; // Only object file output requires special treatment. 999 1000 StringRef Name; 1001 if (getParser().parseIdentifier(Name)) 1002 return TokError("expected identifier in directive"); 1003 // Handle the identifier as the key symbol. 1004 MCSymbol *Sym = getContext().getOrCreateSymbol(Name); 1005 1006 if (getLexer().isNot(AsmToken::Comma)) 1007 return TokError("unexpected token in directive"); 1008 Lex(); 1009 1010 int64_t Size; 1011 SMLoc SizeLoc = getLexer().getLoc(); 1012 if (getParser().parseAbsoluteExpression(Size)) 1013 return true; 1014 1015 int64_t ByteAlignment = 1; 1016 SMLoc ByteAlignmentLoc; 1017 if (getLexer().is(AsmToken::Comma)) { 1018 Lex(); 1019 ByteAlignmentLoc = getLexer().getLoc(); 1020 if (getParser().parseAbsoluteExpression(ByteAlignment)) 1021 return true; 1022 if (!isPowerOf2_64(ByteAlignment)) 1023 return Error(ByteAlignmentLoc, "alignment must be a power of 2"); 1024 } 1025 1026 int64_t AccessAlignment = 0; 1027 if (getLexer().is(AsmToken::Comma)) { 1028 // The optional access argument specifies the size of the smallest memory 1029 // access to be made to the symbol, expressed in bytes. 1030 SMLoc AccessAlignmentLoc; 1031 Lex(); 1032 AccessAlignmentLoc = getLexer().getLoc(); 1033 if (getParser().parseAbsoluteExpression(AccessAlignment)) 1034 return true; 1035 1036 if (!isPowerOf2_64(AccessAlignment)) 1037 return Error(AccessAlignmentLoc, "access alignment must be a power of 2"); 1038 } 1039 1040 if (getLexer().isNot(AsmToken::EndOfStatement)) 1041 return TokError("unexpected token in '.comm' or '.lcomm' directive"); 1042 1043 Lex(); 1044 1045 // NOTE: a size of zero for a .comm should create a undefined symbol 1046 // but a size of .lcomm creates a bss symbol of size zero. 1047 if (Size < 0) 1048 return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't " 1049 "be less than zero"); 1050 1051 // NOTE: The alignment in the directive is a power of 2 value, the assembler 1052 // may internally end up wanting an alignment in bytes. 1053 // FIXME: Diagnose overflow. 1054 if (ByteAlignment < 0) 1055 return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive " 1056 "alignment, can't be less than zero"); 1057 1058 if (!Sym->isUndefined()) 1059 return Error(Loc, "invalid symbol redefinition"); 1060 1061 HexagonMCELFStreamer &HexagonELFStreamer = 1062 static_cast<HexagonMCELFStreamer &>(getStreamer()); 1063 if (IsLocal) { 1064 HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment, 1065 AccessAlignment); 1066 return false; 1067 } 1068 1069 HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment, 1070 AccessAlignment); 1071 return false; 1072 } 1073 1074 // validate register against architecture 1075 bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const { 1076 return true; 1077 } 1078 1079 // extern "C" void LLVMInitializeHexagonAsmLexer(); 1080 1081 /// Force static initialization. 1082 extern "C" void LLVMInitializeHexagonAsmParser() { 1083 RegisterMCAsmParser<HexagonAsmParser> X(TheHexagonTarget); 1084 } 1085 1086 #define GET_MATCHER_IMPLEMENTATION 1087 #define GET_REGISTER_MATCHER 1088 #include "HexagonGenAsmMatcher.inc" 1089 1090 namespace { 1091 bool previousEqual(OperandVector &Operands, size_t Index, StringRef String) { 1092 if (Index >= Operands.size()) 1093 return false; 1094 MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1]; 1095 if (!Operand.isToken()) 1096 return false; 1097 return static_cast<HexagonOperand &>(Operand).getToken().equals_lower(String); 1098 } 1099 bool previousIsLoop(OperandVector &Operands, size_t Index) { 1100 return previousEqual(Operands, Index, "loop0") || 1101 previousEqual(Operands, Index, "loop1") || 1102 previousEqual(Operands, Index, "sp1loop0") || 1103 previousEqual(Operands, Index, "sp2loop0") || 1104 previousEqual(Operands, Index, "sp3loop0"); 1105 } 1106 } 1107 1108 bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) { 1109 AsmToken const &Token = getParser().getTok(); 1110 StringRef String = Token.getString(); 1111 SMLoc Loc = Token.getLoc(); 1112 getLexer().Lex(); 1113 do { 1114 std::pair<StringRef, StringRef> HeadTail = String.split('.'); 1115 if (!HeadTail.first.empty()) 1116 Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc)); 1117 if (!HeadTail.second.empty()) 1118 Operands.push_back(HexagonOperand::CreateToken( 1119 String.substr(HeadTail.first.size(), 1), Loc)); 1120 String = HeadTail.second; 1121 } while (!String.empty()); 1122 return false; 1123 } 1124 1125 bool HexagonAsmParser::parseOperand(OperandVector &Operands) { 1126 unsigned Register; 1127 SMLoc Begin; 1128 SMLoc End; 1129 MCAsmLexer &Lexer = getLexer(); 1130 if (!ParseRegister(Register, Begin, End)) { 1131 if (!ErrorMissingParenthesis) 1132 switch (Register) { 1133 default: 1134 break; 1135 case Hexagon::P0: 1136 case Hexagon::P1: 1137 case Hexagon::P2: 1138 case Hexagon::P3: 1139 if (previousEqual(Operands, 0, "if")) { 1140 if (WarnMissingParenthesis) 1141 Warning (Begin, "Missing parenthesis around predicate register"); 1142 static char const *LParen = "("; 1143 static char const *RParen = ")"; 1144 Operands.push_back(HexagonOperand::CreateToken(LParen, Begin)); 1145 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); 1146 AsmToken MaybeDotNew = Lexer.getTok(); 1147 if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) && 1148 MaybeDotNew.getString().equals_lower(".new")) 1149 splitIdentifier(Operands); 1150 Operands.push_back(HexagonOperand::CreateToken(RParen, Begin)); 1151 return false; 1152 } 1153 if (previousEqual(Operands, 0, "!") && 1154 previousEqual(Operands, 1, "if")) { 1155 if (WarnMissingParenthesis) 1156 Warning (Begin, "Missing parenthesis around predicate register"); 1157 static char const *LParen = "("; 1158 static char const *RParen = ")"; 1159 Operands.insert(Operands.end () - 1, 1160 HexagonOperand::CreateToken(LParen, Begin)); 1161 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); 1162 AsmToken MaybeDotNew = Lexer.getTok(); 1163 if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) && 1164 MaybeDotNew.getString().equals_lower(".new")) 1165 splitIdentifier(Operands); 1166 Operands.push_back(HexagonOperand::CreateToken(RParen, Begin)); 1167 return false; 1168 } 1169 break; 1170 } 1171 Operands.push_back(HexagonOperand::CreateReg( 1172 Register, Begin, End)); 1173 return false; 1174 } 1175 return splitIdentifier(Operands); 1176 } 1177 1178 bool HexagonAsmParser::isLabel(AsmToken &Token) { 1179 MCAsmLexer &Lexer = getLexer(); 1180 AsmToken const &Second = Lexer.getTok(); 1181 AsmToken Third = Lexer.peekTok(); 1182 StringRef String = Token.getString(); 1183 if (Token.is(AsmToken::TokenKind::LCurly) || 1184 Token.is(AsmToken::TokenKind::RCurly)) 1185 return false; 1186 if (!Token.is(AsmToken::TokenKind::Identifier)) 1187 return true; 1188 if (!MatchRegisterName(String.lower())) 1189 return true; 1190 (void)Second; 1191 assert(Second.is(AsmToken::Colon)); 1192 StringRef Raw (String.data(), Third.getString().data() - String.data() + 1193 Third.getString().size()); 1194 std::string Collapsed = Raw; 1195 Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace), 1196 Collapsed.end()); 1197 StringRef Whole = Collapsed; 1198 std::pair<StringRef, StringRef> DotSplit = Whole.split('.'); 1199 if (!MatchRegisterName(DotSplit.first.lower())) 1200 return true; 1201 return false; 1202 } 1203 1204 bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) { 1205 if (!Contigious && ErrorNoncontigiousRegister) { 1206 Error(Loc, "Register name is not contigious"); 1207 return true; 1208 } 1209 if (!Contigious && WarnNoncontigiousRegister) 1210 Warning(Loc, "Register name is not contigious"); 1211 return false; 1212 } 1213 1214 bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1215 MCAsmLexer &Lexer = getLexer(); 1216 StartLoc = getLexer().getLoc(); 1217 SmallVector<AsmToken, 5> Lookahead; 1218 StringRef RawString(Lexer.getTok().getString().data(), 0); 1219 bool Again = Lexer.is(AsmToken::Identifier); 1220 bool NeededWorkaround = false; 1221 while (Again) { 1222 AsmToken const &Token = Lexer.getTok(); 1223 RawString = StringRef(RawString.data(), 1224 Token.getString().data() - RawString.data () + 1225 Token.getString().size()); 1226 Lookahead.push_back(Token); 1227 Lexer.Lex(); 1228 bool Contigious = Lexer.getTok().getString().data() == 1229 Lookahead.back().getString().data() + 1230 Lookahead.back().getString().size(); 1231 bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) || 1232 Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) || 1233 Lexer.is(AsmToken::Colon); 1234 bool Workaround = Lexer.is(AsmToken::Colon) || 1235 Lookahead.back().is(AsmToken::Colon); 1236 Again = (Contigious && Type) || (Workaround && Type); 1237 NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type)); 1238 } 1239 std::string Collapsed = RawString; 1240 Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace), 1241 Collapsed.end()); 1242 StringRef FullString = Collapsed; 1243 std::pair<StringRef, StringRef> DotSplit = FullString.split('.'); 1244 unsigned DotReg = MatchRegisterName(DotSplit.first.lower()); 1245 if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) { 1246 if (DotSplit.second.empty()) { 1247 RegNo = DotReg; 1248 EndLoc = Lexer.getLoc(); 1249 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) 1250 return true; 1251 return false; 1252 } else { 1253 RegNo = DotReg; 1254 size_t First = RawString.find('.'); 1255 StringRef DotString (RawString.data() + First, RawString.size() - First); 1256 Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString)); 1257 EndLoc = Lexer.getLoc(); 1258 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) 1259 return true; 1260 return false; 1261 } 1262 } 1263 std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':'); 1264 unsigned ColonReg = MatchRegisterName(ColonSplit.first.lower()); 1265 if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) { 1266 Lexer.UnLex(Lookahead.back()); 1267 Lookahead.pop_back(); 1268 Lexer.UnLex(Lookahead.back()); 1269 Lookahead.pop_back(); 1270 RegNo = ColonReg; 1271 EndLoc = Lexer.getLoc(); 1272 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) 1273 return true; 1274 return false; 1275 } 1276 while (!Lookahead.empty()) { 1277 Lexer.UnLex(Lookahead.back()); 1278 Lookahead.pop_back(); 1279 } 1280 return true; 1281 } 1282 1283 bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) { 1284 if (previousEqual(Operands, 0, "call")) 1285 return true; 1286 if (previousEqual(Operands, 0, "jump")) 1287 if (!getLexer().getTok().is(AsmToken::Colon)) 1288 return true; 1289 if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1)) 1290 return true; 1291 if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") && 1292 (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t"))) 1293 return true; 1294 return false; 1295 } 1296 1297 bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) { 1298 llvm::SmallVector<AsmToken, 4> Tokens; 1299 MCAsmLexer &Lexer = getLexer(); 1300 bool Done = false; 1301 static char const * Comma = ","; 1302 do { 1303 Tokens.emplace_back (Lexer.getTok()); 1304 Lexer.Lex(); 1305 switch (Tokens.back().getKind()) 1306 { 1307 case AsmToken::TokenKind::Hash: 1308 if (Tokens.size () > 1) 1309 if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) { 1310 Tokens.insert(Tokens.end() - 2, 1311 AsmToken(AsmToken::TokenKind::Comma, Comma)); 1312 Done = true; 1313 } 1314 break; 1315 case AsmToken::TokenKind::RCurly: 1316 case AsmToken::TokenKind::EndOfStatement: 1317 case AsmToken::TokenKind::Eof: 1318 Done = true; 1319 break; 1320 default: 1321 break; 1322 } 1323 } while (!Done); 1324 while (!Tokens.empty()) { 1325 Lexer.UnLex(Tokens.back()); 1326 Tokens.pop_back(); 1327 } 1328 return getParser().parseExpression(Expr); 1329 } 1330 1331 bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) { 1332 if (implicitExpressionLocation(Operands)) { 1333 MCAsmParser &Parser = getParser(); 1334 SMLoc Loc = Parser.getLexer().getLoc(); 1335 std::unique_ptr<HexagonOperand> Expr = 1336 HexagonOperand::CreateImm(nullptr, Loc, Loc); 1337 MCExpr const *& Val = Expr->Imm.Val; 1338 Operands.push_back(std::move(Expr)); 1339 return parseExpression(Val); 1340 } 1341 return parseOperand(Operands); 1342 } 1343 1344 /// Parse an instruction. 1345 bool HexagonAsmParser::parseInstruction(OperandVector &Operands) { 1346 MCAsmParser &Parser = getParser(); 1347 MCAsmLexer &Lexer = getLexer(); 1348 while (true) { 1349 AsmToken const &Token = Parser.getTok(); 1350 switch (Token.getKind()) { 1351 case AsmToken::EndOfStatement: { 1352 Lexer.Lex(); 1353 return false; 1354 } 1355 case AsmToken::LCurly: { 1356 if (!Operands.empty()) 1357 return true; 1358 Operands.push_back( 1359 HexagonOperand::CreateToken(Token.getString(), Token.getLoc())); 1360 Lexer.Lex(); 1361 return false; 1362 } 1363 case AsmToken::RCurly: { 1364 if (Operands.empty()) { 1365 Operands.push_back( 1366 HexagonOperand::CreateToken(Token.getString(), Token.getLoc())); 1367 Lexer.Lex(); 1368 } 1369 return false; 1370 } 1371 case AsmToken::Comma: { 1372 Lexer.Lex(); 1373 continue; 1374 } 1375 case AsmToken::EqualEqual: 1376 case AsmToken::ExclaimEqual: 1377 case AsmToken::GreaterEqual: 1378 case AsmToken::GreaterGreater: 1379 case AsmToken::LessEqual: 1380 case AsmToken::LessLess: { 1381 Operands.push_back(HexagonOperand::CreateToken( 1382 Token.getString().substr(0, 1), Token.getLoc())); 1383 Operands.push_back(HexagonOperand::CreateToken( 1384 Token.getString().substr(1, 1), Token.getLoc())); 1385 Lexer.Lex(); 1386 continue; 1387 } 1388 case AsmToken::Hash: { 1389 bool MustNotExtend = false; 1390 bool ImplicitExpression = implicitExpressionLocation(Operands); 1391 std::unique_ptr<HexagonOperand> Expr = HexagonOperand::CreateImm( 1392 nullptr, Lexer.getLoc(), Lexer.getLoc()); 1393 if (!ImplicitExpression) 1394 Operands.push_back( 1395 HexagonOperand::CreateToken(Token.getString(), Token.getLoc())); 1396 Lexer.Lex(); 1397 bool MustExtend = false; 1398 bool HiOnly = false; 1399 bool LoOnly = false; 1400 if (Lexer.is(AsmToken::Hash)) { 1401 Lexer.Lex(); 1402 MustExtend = true; 1403 } else if (ImplicitExpression) 1404 MustNotExtend = true; 1405 AsmToken const &Token = Parser.getTok(); 1406 if (Token.is(AsmToken::Identifier)) { 1407 StringRef String = Token.getString(); 1408 AsmToken IDToken = Token; 1409 if (String.lower() == "hi") { 1410 HiOnly = true; 1411 } else if (String.lower() == "lo") { 1412 LoOnly = true; 1413 } 1414 if (HiOnly || LoOnly) { 1415 AsmToken LParen = Lexer.peekTok(); 1416 if (!LParen.is(AsmToken::LParen)) { 1417 HiOnly = false; 1418 LoOnly = false; 1419 } else { 1420 Lexer.Lex(); 1421 } 1422 } 1423 } 1424 if (parseExpression(Expr->Imm.Val)) 1425 return true; 1426 int64_t Value; 1427 MCContext &Context = Parser.getContext(); 1428 assert(Expr->Imm.Val != nullptr); 1429 if (Expr->Imm.Val->evaluateAsAbsolute(Value)) { 1430 if (HiOnly) 1431 Expr->Imm.Val = MCBinaryExpr::createLShr( 1432 Expr->Imm.Val, MCConstantExpr::create(16, Context), Context); 1433 if (HiOnly || LoOnly) 1434 Expr->Imm.Val = MCBinaryExpr::createAnd( 1435 Expr->Imm.Val, MCConstantExpr::create(0xffff, Context), Context); 1436 } 1437 if (MustNotExtend) 1438 Expr->Imm.Val = HexagonNoExtendOperand::Create(Expr->Imm.Val, Context); 1439 Expr->Imm.MustExtend = MustExtend; 1440 Operands.push_back(std::move(Expr)); 1441 continue; 1442 } 1443 default: 1444 break; 1445 } 1446 if (parseExpressionOrOperand(Operands)) 1447 return true; 1448 } 1449 } 1450 1451 bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info, 1452 StringRef Name, 1453 AsmToken ID, 1454 OperandVector &Operands) { 1455 getLexer().UnLex(ID); 1456 return parseInstruction(Operands); 1457 } 1458 1459 namespace { 1460 MCInst makeCombineInst(int opCode, MCOperand &Rdd, 1461 MCOperand &MO1, MCOperand &MO2) { 1462 MCInst TmpInst; 1463 TmpInst.setOpcode(opCode); 1464 TmpInst.addOperand(Rdd); 1465 TmpInst.addOperand(MO1); 1466 TmpInst.addOperand(MO2); 1467 1468 return TmpInst; 1469 } 1470 } 1471 1472 // Define this matcher function after the auto-generated include so we 1473 // have the match class enum definitions. 1474 unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1475 unsigned Kind) { 1476 HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp); 1477 1478 switch (Kind) { 1479 case MCK_0: { 1480 int64_t Value; 1481 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0 1482 ? Match_Success 1483 : Match_InvalidOperand; 1484 } 1485 case MCK_1: { 1486 int64_t Value; 1487 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1 1488 ? Match_Success 1489 : Match_InvalidOperand; 1490 } 1491 case MCK__MINUS_1: { 1492 int64_t Value; 1493 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == -1 1494 ? Match_Success 1495 : Match_InvalidOperand; 1496 } 1497 } 1498 if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) { 1499 StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length); 1500 if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind) 1501 return Match_Success; 1502 if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind) 1503 return Match_Success; 1504 } 1505 1506 DEBUG(dbgs() << "Unmatched Operand:"); 1507 DEBUG(Op->dump()); 1508 DEBUG(dbgs() << "\n"); 1509 1510 return Match_InvalidOperand; 1511 } 1512 1513 void HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) { 1514 std::stringstream errStr; 1515 errStr << "value " << Val << "(0x" << std::hex << Val << std::dec 1516 << ") out of range: "; 1517 if (Max >= 0) 1518 errStr << "0-" << Max; 1519 else 1520 errStr << Max << "-" << (-Max - 1); 1521 Error(IDLoc, errStr.str().c_str()); 1522 } 1523 1524 int HexagonAsmParser::processInstruction(MCInst &Inst, 1525 OperandVector const &Operands, 1526 SMLoc IDLoc, bool &MustExtend) { 1527 MCContext &Context = getParser().getContext(); 1528 const MCRegisterInfo *RI = getContext().getRegisterInfo(); 1529 std::string r = "r"; 1530 std::string v = "v"; 1531 std::string Colon = ":"; 1532 1533 bool is32bit = false; // used to distinguish between CONST32 and CONST64 1534 switch (Inst.getOpcode()) { 1535 default: 1536 break; 1537 1538 case Hexagon::M4_mpyrr_addr: 1539 case Hexagon::S4_addi_asl_ri: 1540 case Hexagon::S4_addi_lsr_ri: 1541 case Hexagon::S4_andi_asl_ri: 1542 case Hexagon::S4_andi_lsr_ri: 1543 case Hexagon::S4_ori_asl_ri: 1544 case Hexagon::S4_ori_lsr_ri: 1545 case Hexagon::S4_or_andix: 1546 case Hexagon::S4_subi_asl_ri: 1547 case Hexagon::S4_subi_lsr_ri: { 1548 MCOperand &Ry = Inst.getOperand(0); 1549 MCOperand &src = Inst.getOperand(2); 1550 if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg())) 1551 return Match_InvalidOperand; 1552 break; 1553 } 1554 1555 case Hexagon::C2_cmpgei: { 1556 MCOperand &MO = Inst.getOperand(2); 1557 MO.setExpr(MCBinaryExpr::createSub( 1558 MO.getExpr(), MCConstantExpr::create(1, Context), Context)); 1559 Inst.setOpcode(Hexagon::C2_cmpgti); 1560 break; 1561 } 1562 1563 case Hexagon::C2_cmpgeui: { 1564 MCOperand &MO = Inst.getOperand(2); 1565 int64_t Value; 1566 bool Success = MO.getExpr()->evaluateAsAbsolute(Value); 1567 (void)Success; 1568 assert(Success && "Assured by matcher"); 1569 if (Value == 0) { 1570 MCInst TmpInst; 1571 MCOperand &Pd = Inst.getOperand(0); 1572 MCOperand &Rt = Inst.getOperand(1); 1573 TmpInst.setOpcode(Hexagon::C2_cmpeq); 1574 TmpInst.addOperand(Pd); 1575 TmpInst.addOperand(Rt); 1576 TmpInst.addOperand(Rt); 1577 Inst = TmpInst; 1578 } else { 1579 MO.setExpr(MCBinaryExpr::createSub( 1580 MO.getExpr(), MCConstantExpr::create(1, Context), Context)); 1581 Inst.setOpcode(Hexagon::C2_cmpgtui); 1582 } 1583 break; 1584 } 1585 case Hexagon::J2_loop1r: 1586 case Hexagon::J2_loop1i: 1587 case Hexagon::J2_loop0r: 1588 case Hexagon::J2_loop0i: { 1589 MCOperand &MO = Inst.getOperand(0); 1590 // Loop has different opcodes for extended vs not extended, but we should 1591 // not use the other opcode as it is a legacy artifact of TD files. 1592 int64_t Value; 1593 if (MO.getExpr()->evaluateAsAbsolute(Value)) { 1594 // if the the operand can fit within a 7:2 field 1595 if (Value < (1 << 8) && Value >= -(1 << 8)) { 1596 SMLoc myLoc = Operands[2]->getStartLoc(); 1597 // # is left in startLoc in the case of ## 1598 // If '##' found then force extension. 1599 if (*myLoc.getPointer() == '#') { 1600 MustExtend = true; 1601 break; 1602 } 1603 } else { 1604 // If immediate and out of 7:2 range. 1605 MustExtend = true; 1606 } 1607 } 1608 break; 1609 } 1610 1611 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)" 1612 case Hexagon::A2_tfrp: { 1613 MCOperand &MO = Inst.getOperand(1); 1614 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); 1615 std::string R1 = r + llvm::utostr_32(RegPairNum + 1); 1616 StringRef Reg1(R1); 1617 MO.setReg(MatchRegisterName(Reg1)); 1618 // Add a new operand for the second register in the pair. 1619 std::string R2 = r + llvm::utostr_32(RegPairNum); 1620 StringRef Reg2(R2); 1621 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); 1622 Inst.setOpcode(Hexagon::A2_combinew); 1623 break; 1624 } 1625 1626 case Hexagon::A2_tfrpt: 1627 case Hexagon::A2_tfrpf: { 1628 MCOperand &MO = Inst.getOperand(2); 1629 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); 1630 std::string R1 = r + llvm::utostr_32(RegPairNum + 1); 1631 StringRef Reg1(R1); 1632 MO.setReg(MatchRegisterName(Reg1)); 1633 // Add a new operand for the second register in the pair. 1634 std::string R2 = r + llvm::utostr_32(RegPairNum); 1635 StringRef Reg2(R2); 1636 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); 1637 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) 1638 ? Hexagon::C2_ccombinewt 1639 : Hexagon::C2_ccombinewf); 1640 break; 1641 } 1642 case Hexagon::A2_tfrptnew: 1643 case Hexagon::A2_tfrpfnew: { 1644 MCOperand &MO = Inst.getOperand(2); 1645 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); 1646 std::string R1 = r + llvm::utostr_32(RegPairNum + 1); 1647 StringRef Reg1(R1); 1648 MO.setReg(MatchRegisterName(Reg1)); 1649 // Add a new operand for the second register in the pair. 1650 std::string R2 = r + llvm::utostr_32(RegPairNum); 1651 StringRef Reg2(R2); 1652 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); 1653 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew) 1654 ? Hexagon::C2_ccombinewnewt 1655 : Hexagon::C2_ccombinewnewf); 1656 break; 1657 } 1658 1659 // Translate a "$Rx = CONST32(#imm)" to "$Rx = memw(gp+#LABEL) " 1660 case Hexagon::CONST32: 1661 case Hexagon::CONST32_Float_Real: 1662 case Hexagon::CONST32_Int_Real: 1663 case Hexagon::FCONST32_nsdata: 1664 is32bit = true; 1665 // Translate a "$Rx:y = CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) " 1666 case Hexagon::CONST64_Float_Real: 1667 case Hexagon::CONST64_Int_Real: 1668 1669 // FIXME: need better way to detect AsmStreamer (upstream removed getKind()) 1670 if (!Parser.getStreamer().hasRawTextSupport()) { 1671 MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer()); 1672 MCOperand &MO_1 = Inst.getOperand(1); 1673 MCOperand &MO_0 = Inst.getOperand(0); 1674 1675 // push section onto section stack 1676 MES->PushSection(); 1677 1678 std::string myCharStr; 1679 MCSectionELF *mySection; 1680 1681 // check if this as an immediate or a symbol 1682 int64_t Value; 1683 bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value); 1684 if (Absolute) { 1685 // Create a new section - one for each constant 1686 // Some or all of the zeros are replaced with the given immediate. 1687 if (is32bit) { 1688 std::string myImmStr = utohexstr(static_cast<uint32_t>(Value)); 1689 myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000") 1690 .drop_back(myImmStr.size()) 1691 .str() + 1692 myImmStr; 1693 } else { 1694 std::string myImmStr = utohexstr(Value); 1695 myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000") 1696 .drop_back(myImmStr.size()) 1697 .str() + 1698 myImmStr; 1699 } 1700 1701 mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS, 1702 ELF::SHF_ALLOC | ELF::SHF_WRITE); 1703 } else if (MO_1.isExpr()) { 1704 // .lita - for expressions 1705 myCharStr = ".lita"; 1706 mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS, 1707 ELF::SHF_ALLOC | ELF::SHF_WRITE); 1708 } else 1709 llvm_unreachable("unexpected type of machine operand!"); 1710 1711 MES->SwitchSection(mySection); 1712 unsigned byteSize = is32bit ? 4 : 8; 1713 getStreamer().EmitCodeAlignment(byteSize, byteSize); 1714 1715 MCSymbol *Sym; 1716 1717 // for symbols, get rid of prepended ".gnu.linkonce.lx." 1718 1719 // emit symbol if needed 1720 if (Absolute) { 1721 Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16)); 1722 if (Sym->isUndefined()) { 1723 getStreamer().EmitLabel(Sym); 1724 getStreamer().EmitSymbolAttribute(Sym, MCSA_Global); 1725 getStreamer().EmitIntValue(Value, byteSize); 1726 } 1727 } else if (MO_1.isExpr()) { 1728 const char *StringStart = 0; 1729 const char *StringEnd = 0; 1730 if (*Operands[4]->getStartLoc().getPointer() == '#') { 1731 StringStart = Operands[5]->getStartLoc().getPointer(); 1732 StringEnd = Operands[6]->getStartLoc().getPointer(); 1733 } else { // no pound 1734 StringStart = Operands[4]->getStartLoc().getPointer(); 1735 StringEnd = Operands[5]->getStartLoc().getPointer(); 1736 } 1737 1738 unsigned size = StringEnd - StringStart; 1739 std::string DotConst = ".CONST_"; 1740 Sym = getContext().getOrCreateSymbol(DotConst + 1741 StringRef(StringStart, size)); 1742 1743 if (Sym->isUndefined()) { 1744 // case where symbol is not yet defined: emit symbol 1745 getStreamer().EmitLabel(Sym); 1746 getStreamer().EmitSymbolAttribute(Sym, MCSA_Local); 1747 getStreamer().EmitValue(MO_1.getExpr(), 4); 1748 } 1749 } else 1750 llvm_unreachable("unexpected type of machine operand!"); 1751 1752 MES->PopSection(); 1753 1754 if (Sym) { 1755 MCInst TmpInst; 1756 if (is32bit) // 32 bit 1757 TmpInst.setOpcode(Hexagon::L2_loadrigp); 1758 else // 64 bit 1759 TmpInst.setOpcode(Hexagon::L2_loadrdgp); 1760 1761 TmpInst.addOperand(MO_0); 1762 TmpInst.addOperand( 1763 MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext()))); 1764 Inst = TmpInst; 1765 } 1766 } 1767 break; 1768 1769 // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)" 1770 case Hexagon::A2_tfrpi: { 1771 MCOperand &Rdd = Inst.getOperand(0); 1772 MCOperand &MO = Inst.getOperand(1); 1773 int64_t Value; 1774 int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0; 1775 MCOperand imm(MCOperand::createExpr(MCConstantExpr::create(sVal, Context))); 1776 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO); 1777 break; 1778 } 1779 1780 // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)" 1781 case Hexagon::TFRI64_V4: { 1782 MCOperand &Rdd = Inst.getOperand(0); 1783 MCOperand &MO = Inst.getOperand(1); 1784 int64_t Value; 1785 if (MO.getExpr()->evaluateAsAbsolute(Value)) { 1786 unsigned long long u64 = Value; 1787 signed int s8 = (u64 >> 32) & 0xFFFFFFFF; 1788 if (s8 < -128 || s8 > 127) 1789 OutOfRange(IDLoc, s8, -128); 1790 MCOperand imm(MCOperand::createExpr( 1791 MCConstantExpr::create(s8, Context))); // upper 32 1792 MCOperand imm2(MCOperand::createExpr( 1793 MCConstantExpr::create(u64 & 0xFFFFFFFF, Context))); // lower 32 1794 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); 1795 } else { 1796 MCOperand imm(MCOperand::createExpr( 1797 MCConstantExpr::create(0, Context))); // upper 32 1798 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO); 1799 } 1800 break; 1801 } 1802 1803 // Handle $Rdd = combine(##imm, #imm)" 1804 case Hexagon::TFRI64_V2_ext: { 1805 MCOperand &Rdd = Inst.getOperand(0); 1806 MCOperand &MO1 = Inst.getOperand(1); 1807 MCOperand &MO2 = Inst.getOperand(2); 1808 int64_t Value; 1809 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { 1810 int s8 = Value; 1811 if (s8 < -128 || s8 > 127) 1812 OutOfRange(IDLoc, s8, -128); 1813 } 1814 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); 1815 break; 1816 } 1817 1818 // Handle $Rdd = combine(#imm, ##imm)" 1819 case Hexagon::A4_combineii: { 1820 MCOperand &Rdd = Inst.getOperand(0); 1821 MCOperand &MO1 = Inst.getOperand(1); 1822 int64_t Value; 1823 if (MO1.getExpr()->evaluateAsAbsolute(Value)) { 1824 int s8 = Value; 1825 if (s8 < -128 || s8 > 127) 1826 OutOfRange(IDLoc, s8, -128); 1827 } 1828 MCOperand &MO2 = Inst.getOperand(2); 1829 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); 1830 break; 1831 } 1832 1833 case Hexagon::S2_tableidxb_goodsyntax: { 1834 Inst.setOpcode(Hexagon::S2_tableidxb); 1835 break; 1836 } 1837 1838 case Hexagon::S2_tableidxh_goodsyntax: { 1839 MCInst TmpInst; 1840 MCOperand &Rx = Inst.getOperand(0); 1841 MCOperand &_dst_ = Inst.getOperand(1); 1842 MCOperand &Rs = Inst.getOperand(2); 1843 MCOperand &Imm4 = Inst.getOperand(3); 1844 MCOperand &Imm6 = Inst.getOperand(4); 1845 Imm6.setExpr(MCBinaryExpr::createSub( 1846 Imm6.getExpr(), MCConstantExpr::create(1, Context), Context)); 1847 TmpInst.setOpcode(Hexagon::S2_tableidxh); 1848 TmpInst.addOperand(Rx); 1849 TmpInst.addOperand(_dst_); 1850 TmpInst.addOperand(Rs); 1851 TmpInst.addOperand(Imm4); 1852 TmpInst.addOperand(Imm6); 1853 Inst = TmpInst; 1854 break; 1855 } 1856 1857 case Hexagon::S2_tableidxw_goodsyntax: { 1858 MCInst TmpInst; 1859 MCOperand &Rx = Inst.getOperand(0); 1860 MCOperand &_dst_ = Inst.getOperand(1); 1861 MCOperand &Rs = Inst.getOperand(2); 1862 MCOperand &Imm4 = Inst.getOperand(3); 1863 MCOperand &Imm6 = Inst.getOperand(4); 1864 Imm6.setExpr(MCBinaryExpr::createSub( 1865 Imm6.getExpr(), MCConstantExpr::create(2, Context), Context)); 1866 TmpInst.setOpcode(Hexagon::S2_tableidxw); 1867 TmpInst.addOperand(Rx); 1868 TmpInst.addOperand(_dst_); 1869 TmpInst.addOperand(Rs); 1870 TmpInst.addOperand(Imm4); 1871 TmpInst.addOperand(Imm6); 1872 Inst = TmpInst; 1873 break; 1874 } 1875 1876 case Hexagon::S2_tableidxd_goodsyntax: { 1877 MCInst TmpInst; 1878 MCOperand &Rx = Inst.getOperand(0); 1879 MCOperand &_dst_ = Inst.getOperand(1); 1880 MCOperand &Rs = Inst.getOperand(2); 1881 MCOperand &Imm4 = Inst.getOperand(3); 1882 MCOperand &Imm6 = Inst.getOperand(4); 1883 Imm6.setExpr(MCBinaryExpr::createSub( 1884 Imm6.getExpr(), MCConstantExpr::create(3, Context), Context)); 1885 TmpInst.setOpcode(Hexagon::S2_tableidxd); 1886 TmpInst.addOperand(Rx); 1887 TmpInst.addOperand(_dst_); 1888 TmpInst.addOperand(Rs); 1889 TmpInst.addOperand(Imm4); 1890 TmpInst.addOperand(Imm6); 1891 Inst = TmpInst; 1892 break; 1893 } 1894 1895 case Hexagon::M2_mpyui: { 1896 Inst.setOpcode(Hexagon::M2_mpyi); 1897 break; 1898 } 1899 case Hexagon::M2_mpysmi: { 1900 MCInst TmpInst; 1901 MCOperand &Rd = Inst.getOperand(0); 1902 MCOperand &Rs = Inst.getOperand(1); 1903 MCOperand &Imm = Inst.getOperand(2); 1904 int64_t Value; 1905 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); 1906 assert(Absolute); 1907 (void)Absolute; 1908 if (!MustExtend) { 1909 if (Value < 0 && Value > -256) { 1910 Imm.setExpr(MCConstantExpr::create(Value * -1, Context)); 1911 TmpInst.setOpcode(Hexagon::M2_mpysin); 1912 } else if (Value < 256 && Value >= 0) 1913 TmpInst.setOpcode(Hexagon::M2_mpysip); 1914 else 1915 return Match_InvalidOperand; 1916 } else { 1917 if (Value >= 0) 1918 TmpInst.setOpcode(Hexagon::M2_mpysip); 1919 else 1920 return Match_InvalidOperand; 1921 } 1922 TmpInst.addOperand(Rd); 1923 TmpInst.addOperand(Rs); 1924 TmpInst.addOperand(Imm); 1925 Inst = TmpInst; 1926 break; 1927 } 1928 1929 case Hexagon::S2_asr_i_r_rnd_goodsyntax: { 1930 MCOperand &Imm = Inst.getOperand(2); 1931 MCInst TmpInst; 1932 int64_t Value; 1933 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); 1934 assert(Absolute); 1935 (void)Absolute; 1936 if (Value == 0) { // convert to $Rd = $Rs 1937 TmpInst.setOpcode(Hexagon::A2_tfr); 1938 MCOperand &Rd = Inst.getOperand(0); 1939 MCOperand &Rs = Inst.getOperand(1); 1940 TmpInst.addOperand(Rd); 1941 TmpInst.addOperand(Rs); 1942 } else { 1943 Imm.setExpr(MCBinaryExpr::createSub( 1944 Imm.getExpr(), MCConstantExpr::create(1, Context), Context)); 1945 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd); 1946 MCOperand &Rd = Inst.getOperand(0); 1947 MCOperand &Rs = Inst.getOperand(1); 1948 TmpInst.addOperand(Rd); 1949 TmpInst.addOperand(Rs); 1950 TmpInst.addOperand(Imm); 1951 } 1952 Inst = TmpInst; 1953 break; 1954 } 1955 1956 case Hexagon::S2_asr_i_p_rnd_goodsyntax: { 1957 MCOperand &Rdd = Inst.getOperand(0); 1958 MCOperand &Rss = Inst.getOperand(1); 1959 MCOperand &Imm = Inst.getOperand(2); 1960 int64_t Value; 1961 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); 1962 assert(Absolute); 1963 (void)Absolute; 1964 if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1]) 1965 MCInst TmpInst; 1966 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); 1967 std::string R1 = r + llvm::utostr_32(RegPairNum + 1); 1968 StringRef Reg1(R1); 1969 Rss.setReg(MatchRegisterName(Reg1)); 1970 // Add a new operand for the second register in the pair. 1971 std::string R2 = r + llvm::utostr_32(RegPairNum); 1972 StringRef Reg2(R2); 1973 TmpInst.setOpcode(Hexagon::A2_combinew); 1974 TmpInst.addOperand(Rdd); 1975 TmpInst.addOperand(Rss); 1976 TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); 1977 Inst = TmpInst; 1978 } else { 1979 Imm.setExpr(MCBinaryExpr::createSub( 1980 Imm.getExpr(), MCConstantExpr::create(1, Context), Context)); 1981 Inst.setOpcode(Hexagon::S2_asr_i_p_rnd); 1982 } 1983 break; 1984 } 1985 1986 case Hexagon::A4_boundscheck: { 1987 MCOperand &Rs = Inst.getOperand(1); 1988 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); 1989 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 1990 Inst.setOpcode(Hexagon::A4_boundscheck_hi); 1991 std::string Name = 1992 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1); 1993 StringRef RegPair = Name; 1994 Rs.setReg(MatchRegisterName(RegPair)); 1995 } else { // raw:lo 1996 Inst.setOpcode(Hexagon::A4_boundscheck_lo); 1997 std::string Name = 1998 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum); 1999 StringRef RegPair = Name; 2000 Rs.setReg(MatchRegisterName(RegPair)); 2001 } 2002 break; 2003 } 2004 2005 case Hexagon::A2_addsp: { 2006 MCOperand &Rs = Inst.getOperand(1); 2007 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); 2008 if (RegNum & 1) { // Odd mapped to raw:hi 2009 Inst.setOpcode(Hexagon::A2_addsph); 2010 std::string Name = 2011 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1); 2012 StringRef RegPair = Name; 2013 Rs.setReg(MatchRegisterName(RegPair)); 2014 } else { // Even mapped raw:lo 2015 Inst.setOpcode(Hexagon::A2_addspl); 2016 std::string Name = 2017 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum); 2018 StringRef RegPair = Name; 2019 Rs.setReg(MatchRegisterName(RegPair)); 2020 } 2021 break; 2022 } 2023 2024 case Hexagon::M2_vrcmpys_s1: { 2025 MCOperand &Rt = Inst.getOperand(2); 2026 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); 2027 if (RegNum & 1) { // Odd mapped to sat:raw:hi 2028 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h); 2029 std::string Name = 2030 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1); 2031 StringRef RegPair = Name; 2032 Rt.setReg(MatchRegisterName(RegPair)); 2033 } else { // Even mapped sat:raw:lo 2034 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l); 2035 std::string Name = 2036 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum); 2037 StringRef RegPair = Name; 2038 Rt.setReg(MatchRegisterName(RegPair)); 2039 } 2040 break; 2041 } 2042 2043 case Hexagon::M2_vrcmpys_acc_s1: { 2044 MCInst TmpInst; 2045 MCOperand &Rxx = Inst.getOperand(0); 2046 MCOperand &Rss = Inst.getOperand(2); 2047 MCOperand &Rt = Inst.getOperand(3); 2048 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); 2049 if (RegNum & 1) { // Odd mapped to sat:raw:hi 2050 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h); 2051 std::string Name = 2052 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1); 2053 StringRef RegPair = Name; 2054 Rt.setReg(MatchRegisterName(RegPair)); 2055 } else { // Even mapped sat:raw:lo 2056 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l); 2057 std::string Name = 2058 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum); 2059 StringRef RegPair = Name; 2060 Rt.setReg(MatchRegisterName(RegPair)); 2061 } 2062 // Registers are in different positions 2063 TmpInst.addOperand(Rxx); 2064 TmpInst.addOperand(Rxx); 2065 TmpInst.addOperand(Rss); 2066 TmpInst.addOperand(Rt); 2067 Inst = TmpInst; 2068 break; 2069 } 2070 2071 case Hexagon::M2_vrcmpys_s1rp: { 2072 MCOperand &Rt = Inst.getOperand(2); 2073 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); 2074 if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi 2075 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h); 2076 std::string Name = 2077 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1); 2078 StringRef RegPair = Name; 2079 Rt.setReg(MatchRegisterName(RegPair)); 2080 } else { // Even mapped rnd:sat:raw:lo 2081 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l); 2082 std::string Name = 2083 r + llvm::utostr_32(RegNum + 1) + Colon + llvm::utostr_32(RegNum); 2084 StringRef RegPair = Name; 2085 Rt.setReg(MatchRegisterName(RegPair)); 2086 } 2087 break; 2088 } 2089 2090 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: { 2091 MCOperand &Imm = Inst.getOperand(2); 2092 int64_t Value; 2093 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); 2094 assert(Absolute); 2095 (void)Absolute; 2096 if (Value == 0) 2097 Inst.setOpcode(Hexagon::S2_vsathub); 2098 else { 2099 Imm.setExpr(MCBinaryExpr::createSub( 2100 Imm.getExpr(), MCConstantExpr::create(1, Context), Context)); 2101 Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat); 2102 } 2103 break; 2104 } 2105 2106 case Hexagon::S5_vasrhrnd_goodsyntax: { 2107 MCOperand &Rdd = Inst.getOperand(0); 2108 MCOperand &Rss = Inst.getOperand(1); 2109 MCOperand &Imm = Inst.getOperand(2); 2110 int64_t Value; 2111 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); 2112 assert(Absolute); 2113 (void)Absolute; 2114 if (Value == 0) { 2115 MCInst TmpInst; 2116 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); 2117 std::string R1 = r + llvm::utostr_32(RegPairNum + 1); 2118 StringRef Reg1(R1); 2119 Rss.setReg(MatchRegisterName(Reg1)); 2120 // Add a new operand for the second register in the pair. 2121 std::string R2 = r + llvm::utostr_32(RegPairNum); 2122 StringRef Reg2(R2); 2123 TmpInst.setOpcode(Hexagon::A2_combinew); 2124 TmpInst.addOperand(Rdd); 2125 TmpInst.addOperand(Rss); 2126 TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); 2127 Inst = TmpInst; 2128 } else { 2129 Imm.setExpr(MCBinaryExpr::createSub( 2130 Imm.getExpr(), MCConstantExpr::create(1, Context), Context)); 2131 Inst.setOpcode(Hexagon::S5_vasrhrnd); 2132 } 2133 break; 2134 } 2135 2136 case Hexagon::A2_not: { 2137 MCInst TmpInst; 2138 MCOperand &Rd = Inst.getOperand(0); 2139 MCOperand &Rs = Inst.getOperand(1); 2140 TmpInst.setOpcode(Hexagon::A2_subri); 2141 TmpInst.addOperand(Rd); 2142 TmpInst.addOperand( 2143 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 2144 TmpInst.addOperand(Rs); 2145 Inst = TmpInst; 2146 break; 2147 } 2148 } // switch 2149 2150 return Match_Success; 2151 } 2152