1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "mcasmparser" 11 12 #include "Hexagon.h" 13 #include "HexagonRegisterInfo.h" 14 #include "HexagonTargetStreamer.h" 15 #include "MCTargetDesc/HexagonBaseInfo.h" 16 #include "MCTargetDesc/HexagonMCAsmInfo.h" 17 #include "MCTargetDesc/HexagonMCChecker.h" 18 #include "MCTargetDesc/HexagonMCELFStreamer.h" 19 #include "MCTargetDesc/HexagonMCExpr.h" 20 #include "MCTargetDesc/HexagonMCShuffler.h" 21 #include "MCTargetDesc/HexagonMCTargetDesc.h" 22 #include "MCTargetDesc/HexagonShuffler.h" 23 #include "llvm/ADT/SmallString.h" 24 #include "llvm/ADT/SmallVector.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/Twine.h" 27 #include "llvm/MC/MCContext.h" 28 #include "llvm/MC/MCELFStreamer.h" 29 #include "llvm/MC/MCExpr.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/MC/MCParser/MCAsmLexer.h" 32 #include "llvm/MC/MCParser/MCAsmParser.h" 33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 34 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 35 #include "llvm/MC/MCSectionELF.h" 36 #include "llvm/MC/MCStreamer.h" 37 #include "llvm/MC/MCSubtargetInfo.h" 38 #include "llvm/Support/CommandLine.h" 39 #include "llvm/Support/Debug.h" 40 #include "llvm/Support/ELF.h" 41 #include "llvm/Support/Format.h" 42 #include "llvm/Support/MemoryBuffer.h" 43 #include "llvm/Support/SourceMgr.h" 44 #include "llvm/Support/TargetRegistry.h" 45 #include "llvm/Support/raw_ostream.h" 46 #include <sstream> 47 48 using namespace llvm; 49 50 static cl::opt<bool> EnableFutureRegs("mfuture-regs", 51 cl::desc("Enable future registers")); 52 53 static cl::opt<bool> WarnMissingParenthesis("mwarn-missing-parenthesis", 54 cl::desc("Warn for missing parenthesis around predicate registers"), 55 cl::init(true)); 56 static cl::opt<bool> ErrorMissingParenthesis("merror-missing-parenthesis", 57 cl::desc("Error for missing parenthesis around predicate registers"), 58 cl::init(false)); 59 static cl::opt<bool> WarnSignedMismatch("mwarn-sign-mismatch", 60 cl::desc("Warn for mismatching a signed and unsigned value"), 61 cl::init(true)); 62 static cl::opt<bool> WarnNoncontigiousRegister("mwarn-noncontigious-register", 63 cl::desc("Warn for register names that arent contigious"), 64 cl::init(true)); 65 static cl::opt<bool> ErrorNoncontigiousRegister("merror-noncontigious-register", 66 cl::desc("Error for register names that aren't contigious"), 67 cl::init(false)); 68 69 70 namespace { 71 struct HexagonOperand; 72 73 class HexagonAsmParser : public MCTargetAsmParser { 74 75 HexagonTargetStreamer &getTargetStreamer() { 76 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer(); 77 return static_cast<HexagonTargetStreamer &>(TS); 78 } 79 80 MCAsmParser &Parser; 81 MCAssembler *Assembler; 82 MCInstrInfo const &MCII; 83 MCInst MCB; 84 bool InBrackets; 85 86 MCAsmParser &getParser() const { return Parser; } 87 MCAssembler *getAssembler() const { return Assembler; } 88 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 89 90 bool equalIsAsmAssignment() override { return false; } 91 bool isLabel(AsmToken &Token) override; 92 93 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 94 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 95 bool ParseDirectiveFalign(unsigned Size, SMLoc L); 96 97 virtual bool ParseRegister(unsigned &RegNo, 98 SMLoc &StartLoc, 99 SMLoc &EndLoc) override; 100 bool ParseDirectiveSubsection(SMLoc L); 101 bool ParseDirectiveValue(unsigned Size, SMLoc L); 102 bool ParseDirectiveComm(bool IsLocal, SMLoc L); 103 bool RegisterMatchesArch(unsigned MatchNum) const; 104 105 bool matchBundleOptions(); 106 bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc); 107 bool finishBundle(SMLoc IDLoc, MCStreamer &Out); 108 void canonicalizeImmediates(MCInst &MCI); 109 bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc, 110 OperandVector &InstOperands, uint64_t &ErrorInfo, 111 bool MatchingInlineAsm); 112 113 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 114 OperandVector &Operands, MCStreamer &Out, 115 uint64_t &ErrorInfo, bool MatchingInlineAsm) override; 116 117 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; 118 void OutOfRange(SMLoc IDLoc, long long Val, long long Max); 119 int processInstruction(MCInst &Inst, OperandVector const &Operands, 120 SMLoc IDLoc); 121 122 // Check if we have an assembler and, if so, set the ELF e_header flags. 123 void chksetELFHeaderEFlags(unsigned flags) { 124 if (getAssembler()) 125 getAssembler()->setELFHeaderEFlags(flags); 126 } 127 128 /// @name Auto-generated Match Functions 129 /// { 130 131 #define GET_ASSEMBLER_HEADER 132 #include "HexagonGenAsmMatcher.inc" 133 134 /// } 135 136 public: 137 HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser, 138 const MCInstrInfo &MII, const MCTargetOptions &Options) 139 : MCTargetAsmParser(Options, _STI), Parser(_Parser), 140 MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) { 141 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); 142 143 MCAsmParserExtension::Initialize(_Parser); 144 145 Assembler = nullptr; 146 // FIXME: need better way to detect AsmStreamer (upstream removed getKind()) 147 if (!Parser.getStreamer().hasRawTextSupport()) { 148 MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer()); 149 Assembler = &MES->getAssembler(); 150 } 151 } 152 153 bool mustExtend(OperandVector &Operands); 154 bool splitIdentifier(OperandVector &Operands); 155 bool parseOperand(OperandVector &Operands); 156 bool parseInstruction(OperandVector &Operands); 157 bool implicitExpressionLocation(OperandVector &Operands); 158 bool parseExpressionOrOperand(OperandVector &Operands); 159 bool parseExpression(MCExpr const *& Expr); 160 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 161 SMLoc NameLoc, OperandVector &Operands) override 162 { 163 llvm_unreachable("Unimplemented"); 164 } 165 virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 166 AsmToken ID, OperandVector &Operands) override; 167 168 virtual bool ParseDirective(AsmToken DirectiveID) override; 169 }; 170 171 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine 172 /// instruction. 173 struct HexagonOperand : public MCParsedAsmOperand { 174 enum KindTy { Token, Immediate, Register } Kind; 175 176 SMLoc StartLoc, EndLoc; 177 178 struct TokTy { 179 const char *Data; 180 unsigned Length; 181 }; 182 183 struct RegTy { 184 unsigned RegNum; 185 }; 186 187 struct ImmTy { 188 const MCExpr *Val; 189 }; 190 191 struct InstTy { 192 OperandVector *SubInsts; 193 }; 194 195 union { 196 struct TokTy Tok; 197 struct RegTy Reg; 198 struct ImmTy Imm; 199 }; 200 201 HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 202 203 public: 204 HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() { 205 Kind = o.Kind; 206 StartLoc = o.StartLoc; 207 EndLoc = o.EndLoc; 208 switch (Kind) { 209 case Register: 210 Reg = o.Reg; 211 break; 212 case Immediate: 213 Imm = o.Imm; 214 break; 215 case Token: 216 Tok = o.Tok; 217 break; 218 } 219 } 220 221 /// getStartLoc - Get the location of the first token of this operand. 222 SMLoc getStartLoc() const { return StartLoc; } 223 224 /// getEndLoc - Get the location of the last token of this operand. 225 SMLoc getEndLoc() const { return EndLoc; } 226 227 unsigned getReg() const { 228 assert(Kind == Register && "Invalid access!"); 229 return Reg.RegNum; 230 } 231 232 const MCExpr *getImm() const { 233 assert(Kind == Immediate && "Invalid access!"); 234 return Imm.Val; 235 } 236 237 bool isToken() const { return Kind == Token; } 238 bool isImm() const { return Kind == Immediate; } 239 bool isMem() const { llvm_unreachable("No isMem"); } 240 bool isReg() const { return Kind == Register; } 241 242 bool CheckImmRange(int immBits, int zeroBits, bool isSigned, 243 bool isRelocatable, bool Extendable) const { 244 if (Kind == Immediate) { 245 const MCExpr *myMCExpr = &HexagonMCInstrInfo::getExpr(*getImm()); 246 if (HexagonMCInstrInfo::mustExtend(*Imm.Val) && !Extendable) 247 return false; 248 int64_t Res; 249 if (myMCExpr->evaluateAsAbsolute(Res)) { 250 int bits = immBits + zeroBits; 251 // Field bit range is zerobits + bits 252 // zeroBits must be 0 253 if (Res & ((1 << zeroBits) - 1)) 254 return false; 255 if (isSigned) { 256 if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1))) 257 return true; 258 } else { 259 if (bits == 64) 260 return true; 261 if (Res >= 0) 262 return ((uint64_t)Res < (uint64_t)(1ULL << bits)) ? true : false; 263 else { 264 const int64_t high_bit_set = 1ULL << 63; 265 const uint64_t mask = (high_bit_set >> (63 - bits)); 266 return (((uint64_t)Res & mask) == mask) ? true : false; 267 } 268 } 269 } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable) 270 return true; 271 else if (myMCExpr->getKind() == MCExpr::Binary || 272 myMCExpr->getKind() == MCExpr::Unary) 273 return true; 274 } 275 return false; 276 } 277 278 bool isf32Ext() const { return false; } 279 bool iss32Imm() const { return CheckImmRange(32, 0, true, true, false); } 280 bool iss23_2Imm() const { return CheckImmRange(23, 2, true, true, false); } 281 bool iss8Imm() const { return CheckImmRange(8, 0, true, false, false); } 282 bool iss8Imm64() const { return CheckImmRange(8, 0, true, true, false); } 283 bool iss7Imm() const { return CheckImmRange(7, 0, true, false, false); } 284 bool iss6Imm() const { return CheckImmRange(6, 0, true, false, false); } 285 bool iss4Imm() const { return CheckImmRange(4, 0, true, false, false); } 286 bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); } 287 bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); } 288 bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); } 289 bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); } 290 bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); } 291 bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); } 292 bool iss3Imm() const { return CheckImmRange(3, 0, true, false, false); } 293 294 bool isu64Imm() const { return CheckImmRange(64, 0, false, true, true); } 295 bool isu32Imm() const { return CheckImmRange(32, 0, false, true, false); } 296 bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); } 297 bool isu16Imm() const { return CheckImmRange(16, 0, false, true, false); } 298 bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); } 299 bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); } 300 bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); } 301 bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); } 302 bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); } 303 bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); } 304 bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); } 305 bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); } 306 bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); } 307 bool isu10Imm() const { return CheckImmRange(10, 0, false, false, false); } 308 bool isu9Imm() const { return CheckImmRange(9, 0, false, false, false); } 309 bool isu8Imm() const { return CheckImmRange(8, 0, false, false, false); } 310 bool isu7Imm() const { return CheckImmRange(7, 0, false, false, false); } 311 bool isu6Imm() const { return CheckImmRange(6, 0, false, false, false); } 312 bool isu5Imm() const { return CheckImmRange(5, 0, false, false, false); } 313 bool isu4Imm() const { return CheckImmRange(4, 0, false, false, false); } 314 bool isu3Imm() const { return CheckImmRange(3, 0, false, false, false); } 315 bool isu2Imm() const { return CheckImmRange(2, 0, false, false, false); } 316 bool isu1Imm() const { return CheckImmRange(1, 0, false, false, false); } 317 318 bool ism6Imm() const { return CheckImmRange(6, 0, false, false, false); } 319 bool isn8Imm() const { return CheckImmRange(8, 0, false, false, false); } 320 321 bool iss16Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); } 322 bool iss12Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); } 323 bool iss10Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); } 324 bool iss9Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); } 325 bool iss8Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); } 326 bool iss7Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); } 327 bool iss6Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); } 328 bool iss11_0Ext() const { 329 return CheckImmRange(11 + 26, 0, true, true, true); 330 } 331 bool iss11_1Ext() const { 332 return CheckImmRange(11 + 26, 1, true, true, true); 333 } 334 bool iss11_2Ext() const { 335 return CheckImmRange(11 + 26, 2, true, true, true); 336 } 337 bool iss11_3Ext() const { 338 return CheckImmRange(11 + 26, 3, true, true, true); 339 } 340 341 bool isu6Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); } 342 bool isu7Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); } 343 bool isu8Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); } 344 bool isu9Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); } 345 bool isu10Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); } 346 bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); } 347 bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); } 348 bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); } 349 bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); } 350 bool isu32MustExt() const { return isImm(); } 351 352 void addRegOperands(MCInst &Inst, unsigned N) const { 353 assert(N == 1 && "Invalid number of operands!"); 354 Inst.addOperand(MCOperand::createReg(getReg())); 355 } 356 357 void addImmOperands(MCInst &Inst, unsigned N) const { 358 assert(N == 1 && "Invalid number of operands!"); 359 Inst.addOperand(MCOperand::createExpr(getImm())); 360 } 361 362 void addSignedImmOperands(MCInst &Inst, unsigned N) const { 363 assert(N == 1 && "Invalid number of operands!"); 364 HexagonMCExpr *Expr = 365 const_cast<HexagonMCExpr *>(cast<HexagonMCExpr>(getImm())); 366 int64_t Value; 367 if (!Expr->evaluateAsAbsolute(Value)) { 368 Inst.addOperand(MCOperand::createExpr(Expr)); 369 return; 370 } 371 int64_t Extended = SignExtend64(Value, 32); 372 if ((Extended < 0) != (Value < 0)) 373 Expr->setSignMismatch(); 374 Inst.addOperand(MCOperand::createExpr(Expr)); 375 } 376 377 void addf32ExtOperands(MCInst &Inst, unsigned N) const { 378 addImmOperands(Inst, N); 379 } 380 381 void adds32ImmOperands(MCInst &Inst, unsigned N) const { 382 addSignedImmOperands(Inst, N); 383 } 384 void adds23_2ImmOperands(MCInst &Inst, unsigned N) const { 385 addSignedImmOperands(Inst, N); 386 } 387 void adds8ImmOperands(MCInst &Inst, unsigned N) const { 388 addSignedImmOperands(Inst, N); 389 } 390 void adds8Imm64Operands(MCInst &Inst, unsigned N) const { 391 addSignedImmOperands(Inst, N); 392 } 393 void adds6ImmOperands(MCInst &Inst, unsigned N) const { 394 addSignedImmOperands(Inst, N); 395 } 396 void adds4ImmOperands(MCInst &Inst, unsigned N) const { 397 addSignedImmOperands(Inst, N); 398 } 399 void adds4_0ImmOperands(MCInst &Inst, unsigned N) const { 400 addSignedImmOperands(Inst, N); 401 } 402 void adds4_1ImmOperands(MCInst &Inst, unsigned N) const { 403 addSignedImmOperands(Inst, N); 404 } 405 void adds4_2ImmOperands(MCInst &Inst, unsigned N) const { 406 addSignedImmOperands(Inst, N); 407 } 408 void adds4_3ImmOperands(MCInst &Inst, unsigned N) const { 409 addSignedImmOperands(Inst, N); 410 } 411 void adds3ImmOperands(MCInst &Inst, unsigned N) const { 412 addSignedImmOperands(Inst, N); 413 } 414 415 void addu64ImmOperands(MCInst &Inst, unsigned N) const { 416 addImmOperands(Inst, N); 417 } 418 void addu32ImmOperands(MCInst &Inst, unsigned N) const { 419 addImmOperands(Inst, N); 420 } 421 void addu26_6ImmOperands(MCInst &Inst, unsigned N) const { 422 addImmOperands(Inst, N); 423 } 424 void addu16ImmOperands(MCInst &Inst, unsigned N) const { 425 addImmOperands(Inst, N); 426 } 427 void addu16_0ImmOperands(MCInst &Inst, unsigned N) const { 428 addImmOperands(Inst, N); 429 } 430 void addu16_1ImmOperands(MCInst &Inst, unsigned N) const { 431 addImmOperands(Inst, N); 432 } 433 void addu16_2ImmOperands(MCInst &Inst, unsigned N) const { 434 addImmOperands(Inst, N); 435 } 436 void addu16_3ImmOperands(MCInst &Inst, unsigned N) const { 437 addImmOperands(Inst, N); 438 } 439 void addu11_3ImmOperands(MCInst &Inst, unsigned N) const { 440 addImmOperands(Inst, N); 441 } 442 void addu10ImmOperands(MCInst &Inst, unsigned N) const { 443 addImmOperands(Inst, N); 444 } 445 void addu9ImmOperands(MCInst &Inst, unsigned N) const { 446 addImmOperands(Inst, N); 447 } 448 void addu8ImmOperands(MCInst &Inst, unsigned N) const { 449 addImmOperands(Inst, N); 450 } 451 void addu7ImmOperands(MCInst &Inst, unsigned N) const { 452 addImmOperands(Inst, N); 453 } 454 void addu6ImmOperands(MCInst &Inst, unsigned N) const { 455 addImmOperands(Inst, N); 456 } 457 void addu6_0ImmOperands(MCInst &Inst, unsigned N) const { 458 addImmOperands(Inst, N); 459 } 460 void addu6_1ImmOperands(MCInst &Inst, unsigned N) const { 461 addImmOperands(Inst, N); 462 } 463 void addu6_2ImmOperands(MCInst &Inst, unsigned N) const { 464 addImmOperands(Inst, N); 465 } 466 void addu6_3ImmOperands(MCInst &Inst, unsigned N) const { 467 addImmOperands(Inst, N); 468 } 469 void addu5ImmOperands(MCInst &Inst, unsigned N) const { 470 addImmOperands(Inst, N); 471 } 472 void addu4ImmOperands(MCInst &Inst, unsigned N) const { 473 addImmOperands(Inst, N); 474 } 475 void addu3ImmOperands(MCInst &Inst, unsigned N) const { 476 addImmOperands(Inst, N); 477 } 478 void addu2ImmOperands(MCInst &Inst, unsigned N) const { 479 addImmOperands(Inst, N); 480 } 481 void addu1ImmOperands(MCInst &Inst, unsigned N) const { 482 addImmOperands(Inst, N); 483 } 484 485 void addm6ImmOperands(MCInst &Inst, unsigned N) const { 486 addImmOperands(Inst, N); 487 } 488 void addn8ImmOperands(MCInst &Inst, unsigned N) const { 489 addImmOperands(Inst, N); 490 } 491 492 void adds16ExtOperands(MCInst &Inst, unsigned N) const { 493 addSignedImmOperands(Inst, N); 494 } 495 void adds12ExtOperands(MCInst &Inst, unsigned N) const { 496 addSignedImmOperands(Inst, N); 497 } 498 void adds10ExtOperands(MCInst &Inst, unsigned N) const { 499 addSignedImmOperands(Inst, N); 500 } 501 void adds9ExtOperands(MCInst &Inst, unsigned N) const { 502 addSignedImmOperands(Inst, N); 503 } 504 void adds8ExtOperands(MCInst &Inst, unsigned N) const { 505 addSignedImmOperands(Inst, N); 506 } 507 void adds6ExtOperands(MCInst &Inst, unsigned N) const { 508 addSignedImmOperands(Inst, N); 509 } 510 void adds11_0ExtOperands(MCInst &Inst, unsigned N) const { 511 addSignedImmOperands(Inst, N); 512 } 513 void adds11_1ExtOperands(MCInst &Inst, unsigned N) const { 514 addSignedImmOperands(Inst, N); 515 } 516 void adds11_2ExtOperands(MCInst &Inst, unsigned N) const { 517 addSignedImmOperands(Inst, N); 518 } 519 void adds11_3ExtOperands(MCInst &Inst, unsigned N) const { 520 addSignedImmOperands(Inst, N); 521 } 522 523 void addu6ExtOperands(MCInst &Inst, unsigned N) const { 524 addImmOperands(Inst, N); 525 } 526 void addu7ExtOperands(MCInst &Inst, unsigned N) const { 527 addImmOperands(Inst, N); 528 } 529 void addu8ExtOperands(MCInst &Inst, unsigned N) const { 530 addImmOperands(Inst, N); 531 } 532 void addu9ExtOperands(MCInst &Inst, unsigned N) const { 533 addImmOperands(Inst, N); 534 } 535 void addu10ExtOperands(MCInst &Inst, unsigned N) const { 536 addImmOperands(Inst, N); 537 } 538 void addu6_0ExtOperands(MCInst &Inst, unsigned N) const { 539 addImmOperands(Inst, N); 540 } 541 void addu6_1ExtOperands(MCInst &Inst, unsigned N) const { 542 addImmOperands(Inst, N); 543 } 544 void addu6_2ExtOperands(MCInst &Inst, unsigned N) const { 545 addImmOperands(Inst, N); 546 } 547 void addu6_3ExtOperands(MCInst &Inst, unsigned N) const { 548 addImmOperands(Inst, N); 549 } 550 void addu32MustExtOperands(MCInst &Inst, unsigned N) const { 551 addImmOperands(Inst, N); 552 } 553 554 void adds4_6ImmOperands(MCInst &Inst, unsigned N) const { 555 assert(N == 1 && "Invalid number of operands!"); 556 const MCConstantExpr *CE = 557 dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm())); 558 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); 559 } 560 561 void adds3_6ImmOperands(MCInst &Inst, unsigned N) const { 562 assert(N == 1 && "Invalid number of operands!"); 563 const MCConstantExpr *CE = 564 dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm())); 565 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); 566 } 567 568 StringRef getToken() const { 569 assert(Kind == Token && "Invalid access!"); 570 return StringRef(Tok.Data, Tok.Length); 571 } 572 573 virtual void print(raw_ostream &OS) const; 574 575 static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) { 576 HexagonOperand *Op = new HexagonOperand(Token); 577 Op->Tok.Data = Str.data(); 578 Op->Tok.Length = Str.size(); 579 Op->StartLoc = S; 580 Op->EndLoc = S; 581 return std::unique_ptr<HexagonOperand>(Op); 582 } 583 584 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S, 585 SMLoc E) { 586 HexagonOperand *Op = new HexagonOperand(Register); 587 Op->Reg.RegNum = RegNum; 588 Op->StartLoc = S; 589 Op->EndLoc = E; 590 return std::unique_ptr<HexagonOperand>(Op); 591 } 592 593 static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S, 594 SMLoc E) { 595 HexagonOperand *Op = new HexagonOperand(Immediate); 596 Op->Imm.Val = Val; 597 Op->StartLoc = S; 598 Op->EndLoc = E; 599 return std::unique_ptr<HexagonOperand>(Op); 600 } 601 }; 602 603 } // end anonymous namespace. 604 605 void HexagonOperand::print(raw_ostream &OS) const { 606 switch (Kind) { 607 case Immediate: 608 getImm()->print(OS, nullptr); 609 break; 610 case Register: 611 OS << "<register R"; 612 OS << getReg() << ">"; 613 break; 614 case Token: 615 OS << "'" << getToken() << "'"; 616 break; 617 } 618 } 619 620 /// @name Auto-generated Match Functions 621 static unsigned MatchRegisterName(StringRef Name); 622 623 bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) { 624 DEBUG(dbgs() << "Bundle:"); 625 DEBUG(MCB.dump_pretty(dbgs())); 626 DEBUG(dbgs() << "--\n"); 627 628 // Check the bundle for errors. 629 const MCRegisterInfo *RI = getContext().getRegisterInfo(); 630 HexagonMCChecker Check(MCII, getSTI(), MCB, MCB, *RI); 631 632 bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(), 633 getContext(), MCB, 634 &Check); 635 636 while (Check.getNextErrInfo() == true) { 637 unsigned Reg = Check.getErrRegister(); 638 Twine R(RI->getName(Reg)); 639 640 uint64_t Err = Check.getError(); 641 if (Err != HexagonMCErrInfo::CHECK_SUCCESS) { 642 if (HexagonMCErrInfo::CHECK_ERROR_BRANCHES & Err) 643 Error(IDLoc, 644 "unconditional branch cannot precede another branch in packet"); 645 646 if (HexagonMCErrInfo::CHECK_ERROR_NEWP & Err || 647 HexagonMCErrInfo::CHECK_ERROR_NEWV & Err) 648 Error(IDLoc, "register `" + R + 649 "' used with `.new' " 650 "but not validly modified in the same packet"); 651 652 if (HexagonMCErrInfo::CHECK_ERROR_REGISTERS & Err) 653 Error(IDLoc, "register `" + R + "' modified more than once"); 654 655 if (HexagonMCErrInfo::CHECK_ERROR_READONLY & Err) 656 Error(IDLoc, "cannot write to read-only register `" + R + "'"); 657 658 if (HexagonMCErrInfo::CHECK_ERROR_LOOP & Err) 659 Error(IDLoc, "loop-setup and some branch instructions " 660 "cannot be in the same packet"); 661 662 if (HexagonMCErrInfo::CHECK_ERROR_ENDLOOP & Err) { 663 Twine N(HexagonMCInstrInfo::isInnerLoop(MCB) ? '0' : '1'); 664 Error(IDLoc, "packet marked with `:endloop" + N + "' " + 665 "cannot contain instructions that modify register " + 666 "`" + R + "'"); 667 } 668 669 if (HexagonMCErrInfo::CHECK_ERROR_SOLO & Err) 670 Error(IDLoc, 671 "instruction cannot appear in packet with other instructions"); 672 673 if (HexagonMCErrInfo::CHECK_ERROR_NOSLOTS & Err) 674 Error(IDLoc, "too many slots used in packet"); 675 676 if (Err & HexagonMCErrInfo::CHECK_ERROR_SHUFFLE) { 677 uint64_t Erm = Check.getShuffleError(); 678 679 if (HexagonShuffler::SHUFFLE_ERROR_INVALID == Erm) 680 Error(IDLoc, "invalid instruction packet"); 681 else if (HexagonShuffler::SHUFFLE_ERROR_STORES == Erm) 682 Error(IDLoc, "invalid instruction packet: too many stores"); 683 else if (HexagonShuffler::SHUFFLE_ERROR_LOADS == Erm) 684 Error(IDLoc, "invalid instruction packet: too many loads"); 685 else if (HexagonShuffler::SHUFFLE_ERROR_BRANCHES == Erm) 686 Error(IDLoc, "too many branches in packet"); 687 else if (HexagonShuffler::SHUFFLE_ERROR_NOSLOTS == Erm) 688 Error(IDLoc, "invalid instruction packet: out of slots"); 689 else if (HexagonShuffler::SHUFFLE_ERROR_SLOTS == Erm) 690 Error(IDLoc, "invalid instruction packet: slot error"); 691 else if (HexagonShuffler::SHUFFLE_ERROR_ERRATA2 == Erm) 692 Error(IDLoc, "v60 packet violation"); 693 else if (HexagonShuffler::SHUFFLE_ERROR_STORE_LOAD_CONFLICT == Erm) 694 Error(IDLoc, "slot 0 instruction does not allow slot 1 store"); 695 else 696 Error(IDLoc, "unknown error in instruction packet"); 697 } 698 } 699 700 unsigned Warn = Check.getWarning(); 701 if (Warn != HexagonMCErrInfo::CHECK_SUCCESS) { 702 if (HexagonMCErrInfo::CHECK_WARN_CURRENT & Warn) 703 Warning(IDLoc, "register `" + R + "' used with `.cur' " 704 "but not used in the same packet"); 705 else if (HexagonMCErrInfo::CHECK_WARN_TEMPORARY & Warn) 706 Warning(IDLoc, "register `" + R + "' used with `.tmp' " 707 "but not used in the same packet"); 708 } 709 } 710 711 if (CheckOk) { 712 MCB.setLoc(IDLoc); 713 if (HexagonMCInstrInfo::bundleSize(MCB) == 0) { 714 assert(!HexagonMCInstrInfo::isInnerLoop(MCB)); 715 assert(!HexagonMCInstrInfo::isOuterLoop(MCB)); 716 // Empty packets are valid yet aren't emitted 717 return false; 718 } 719 Out.EmitInstruction(MCB, getSTI()); 720 } else { 721 // If compounding and duplexing didn't reduce the size below 722 // 4 or less we have a packet that is too big. 723 if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) { 724 Error(IDLoc, "invalid instruction packet: out of slots"); 725 return true; // Error 726 } 727 } 728 729 return false; // No error 730 } 731 732 bool HexagonAsmParser::matchBundleOptions() { 733 MCAsmParser &Parser = getParser(); 734 MCAsmLexer &Lexer = getLexer(); 735 while (true) { 736 if (!Parser.getTok().is(AsmToken::Colon)) 737 return false; 738 Lexer.Lex(); 739 StringRef Option = Parser.getTok().getString(); 740 if (Option.compare_lower("endloop0") == 0) 741 HexagonMCInstrInfo::setInnerLoop(MCB); 742 else if (Option.compare_lower("endloop1") == 0) 743 HexagonMCInstrInfo::setOuterLoop(MCB); 744 else if (Option.compare_lower("mem_noshuf") == 0) 745 HexagonMCInstrInfo::setMemReorderDisabled(MCB); 746 else if (Option.compare_lower("mem_shuf") == 0) 747 HexagonMCInstrInfo::setMemStoreReorderEnabled(MCB); 748 else 749 return true; 750 Lexer.Lex(); 751 } 752 } 753 754 // For instruction aliases, immediates are generated rather than 755 // MCConstantExpr. Convert them for uniform MCExpr. 756 // Also check for signed/unsigned mismatches and warn 757 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) { 758 MCInst NewInst; 759 NewInst.setOpcode(MCI.getOpcode()); 760 for (MCOperand &I : MCI) 761 if (I.isImm()) { 762 int64_t Value (I.getImm()); 763 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( 764 MCConstantExpr::create(Value, getContext()), getContext()))); 765 } 766 else { 767 if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() && 768 WarnSignedMismatch) 769 Warning (MCI.getLoc(), "Signed/Unsigned mismatch"); 770 NewInst.addOperand(I); 771 } 772 MCI = NewInst; 773 } 774 775 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc, 776 OperandVector &InstOperands, 777 uint64_t &ErrorInfo, 778 bool MatchingInlineAsm) { 779 // Perform matching with tablegen asmmatcher generated function 780 int result = 781 MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm); 782 if (result == Match_Success) { 783 MCI.setLoc(IDLoc); 784 canonicalizeImmediates(MCI); 785 result = processInstruction(MCI, InstOperands, IDLoc); 786 787 DEBUG(dbgs() << "Insn:"); 788 DEBUG(MCI.dump_pretty(dbgs())); 789 DEBUG(dbgs() << "\n\n"); 790 791 MCI.setLoc(IDLoc); 792 } 793 794 // Create instruction operand for bundle instruction 795 // Break this into a separate function Code here is less readable 796 // Think about how to get an instruction error to report correctly. 797 // SMLoc will return the "{" 798 switch (result) { 799 default: 800 break; 801 case Match_Success: 802 return false; 803 case Match_MissingFeature: 804 return Error(IDLoc, "invalid instruction"); 805 case Match_MnemonicFail: 806 return Error(IDLoc, "unrecognized instruction"); 807 case Match_InvalidOperand: 808 SMLoc ErrorLoc = IDLoc; 809 if (ErrorInfo != ~0U) { 810 if (ErrorInfo >= InstOperands.size()) 811 return Error(IDLoc, "too few operands for instruction"); 812 813 ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get())) 814 ->getStartLoc(); 815 if (ErrorLoc == SMLoc()) 816 ErrorLoc = IDLoc; 817 } 818 return Error(ErrorLoc, "invalid operand for instruction"); 819 } 820 llvm_unreachable("Implement any new match types added!"); 821 } 822 823 bool HexagonAsmParser::mustExtend(OperandVector &Operands) { 824 unsigned Count = 0; 825 for (std::unique_ptr<MCParsedAsmOperand> &i : Operands) 826 if (i->isImm()) 827 if (HexagonMCInstrInfo::mustExtend( 828 *static_cast<HexagonOperand *>(i.get())->Imm.Val)) 829 ++Count; 830 // Multiple extenders should have been filtered by iss9Ext et. al. 831 assert(Count < 2 && "Multiple extenders"); 832 return Count == 1; 833 } 834 835 bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 836 OperandVector &Operands, 837 MCStreamer &Out, 838 uint64_t &ErrorInfo, 839 bool MatchingInlineAsm) { 840 if (!InBrackets) { 841 MCB.clear(); 842 MCB.addOperand(MCOperand::createImm(0)); 843 } 844 HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]); 845 if (FirstOperand.isToken() && FirstOperand.getToken() == "{") { 846 assert(Operands.size() == 1 && "Brackets should be by themselves"); 847 if (InBrackets) { 848 getParser().Error(IDLoc, "Already in a packet"); 849 return true; 850 } 851 InBrackets = true; 852 return false; 853 } 854 if (FirstOperand.isToken() && FirstOperand.getToken() == "}") { 855 assert(Operands.size() == 1 && "Brackets should be by themselves"); 856 if (!InBrackets) { 857 getParser().Error(IDLoc, "Not in a packet"); 858 return true; 859 } 860 InBrackets = false; 861 if (matchBundleOptions()) 862 return true; 863 return finishBundle(IDLoc, Out); 864 } 865 MCInst *SubInst = new (getParser().getContext()) MCInst; 866 if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo, 867 MatchingInlineAsm)) 868 return true; 869 HexagonMCInstrInfo::extendIfNeeded( 870 getParser().getContext(), MCII, MCB, *SubInst); 871 MCB.addOperand(MCOperand::createInst(SubInst)); 872 if (!InBrackets) 873 return finishBundle(IDLoc, Out); 874 return false; 875 } 876 877 /// ParseDirective parses the Hexagon specific directives 878 bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) { 879 StringRef IDVal = DirectiveID.getIdentifier(); 880 if ((IDVal.lower() == ".word") || (IDVal.lower() == ".4byte")) 881 return ParseDirectiveValue(4, DirectiveID.getLoc()); 882 if (IDVal.lower() == ".short" || IDVal.lower() == ".hword" || 883 IDVal.lower() == ".half") 884 return ParseDirectiveValue(2, DirectiveID.getLoc()); 885 if (IDVal.lower() == ".falign") 886 return ParseDirectiveFalign(256, DirectiveID.getLoc()); 887 if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon")) 888 return ParseDirectiveComm(true, DirectiveID.getLoc()); 889 if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common")) 890 return ParseDirectiveComm(false, DirectiveID.getLoc()); 891 if (IDVal.lower() == ".subsection") 892 return ParseDirectiveSubsection(DirectiveID.getLoc()); 893 894 return true; 895 } 896 bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) { 897 const MCExpr *Subsection = 0; 898 int64_t Res; 899 900 assert((getLexer().isNot(AsmToken::EndOfStatement)) && 901 "Invalid subsection directive"); 902 getParser().parseExpression(Subsection); 903 904 if (!Subsection->evaluateAsAbsolute(Res)) 905 return Error(L, "Cannot evaluate subsection number"); 906 907 if (getLexer().isNot(AsmToken::EndOfStatement)) 908 return TokError("unexpected token in directive"); 909 910 // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the 911 // negative subsections together and in the same order but at the opposite 912 // end of the section. Only legacy hexagon-gcc created assembly code 913 // used negative subsections. 914 if ((Res < 0) && (Res > -8193)) 915 Subsection = HexagonMCExpr::create( 916 MCConstantExpr::create(8192 + Res, getContext()), getContext()); 917 918 getStreamer().SubSection(Subsection); 919 return false; 920 } 921 922 /// ::= .falign [expression] 923 bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) { 924 925 int64_t MaxBytesToFill = 15; 926 927 // if there is an arguement 928 if (getLexer().isNot(AsmToken::EndOfStatement)) { 929 const MCExpr *Value; 930 SMLoc ExprLoc = L; 931 932 // Make sure we have a number (false is returned if expression is a number) 933 if (getParser().parseExpression(Value) == false) { 934 // Make sure this is a number that is in range 935 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value); 936 uint64_t IntValue = MCE->getValue(); 937 if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue)) 938 return Error(ExprLoc, "literal value out of range (256) for falign"); 939 MaxBytesToFill = IntValue; 940 Lex(); 941 } else { 942 return Error(ExprLoc, "not a valid expression for falign directive"); 943 } 944 } 945 946 getTargetStreamer().emitFAlign(16, MaxBytesToFill); 947 Lex(); 948 949 return false; 950 } 951 952 /// ::= .word [ expression (, expression)* ] 953 bool HexagonAsmParser::ParseDirectiveValue(unsigned Size, SMLoc L) { 954 if (getLexer().isNot(AsmToken::EndOfStatement)) { 955 956 for (;;) { 957 const MCExpr *Value; 958 SMLoc ExprLoc = L; 959 if (getParser().parseExpression(Value)) 960 return true; 961 962 // Special case constant expressions to match code generator. 963 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value)) { 964 assert(Size <= 8 && "Invalid size"); 965 uint64_t IntValue = MCE->getValue(); 966 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 967 return Error(ExprLoc, "literal value out of range for directive"); 968 getStreamer().EmitIntValue(IntValue, Size); 969 } else 970 getStreamer().EmitValue(Value, Size); 971 972 if (getLexer().is(AsmToken::EndOfStatement)) 973 break; 974 975 // FIXME: Improve diagnostic. 976 if (getLexer().isNot(AsmToken::Comma)) 977 return TokError("unexpected token in directive"); 978 Lex(); 979 } 980 } 981 982 Lex(); 983 return false; 984 } 985 986 // This is largely a copy of AsmParser's ParseDirectiveComm extended to 987 // accept a 3rd argument, AccessAlignment which indicates the smallest 988 // memory access made to the symbol, expressed in bytes. If no 989 // AccessAlignment is specified it defaults to the Alignment Value. 990 // Hexagon's .lcomm: 991 // .lcomm Symbol, Length, Alignment, AccessAlignment 992 bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) { 993 // FIXME: need better way to detect if AsmStreamer (upstream removed 994 // getKind()) 995 if (getStreamer().hasRawTextSupport()) 996 return true; // Only object file output requires special treatment. 997 998 StringRef Name; 999 if (getParser().parseIdentifier(Name)) 1000 return TokError("expected identifier in directive"); 1001 // Handle the identifier as the key symbol. 1002 MCSymbol *Sym = getContext().getOrCreateSymbol(Name); 1003 1004 if (getLexer().isNot(AsmToken::Comma)) 1005 return TokError("unexpected token in directive"); 1006 Lex(); 1007 1008 int64_t Size; 1009 SMLoc SizeLoc = getLexer().getLoc(); 1010 if (getParser().parseAbsoluteExpression(Size)) 1011 return true; 1012 1013 int64_t ByteAlignment = 1; 1014 SMLoc ByteAlignmentLoc; 1015 if (getLexer().is(AsmToken::Comma)) { 1016 Lex(); 1017 ByteAlignmentLoc = getLexer().getLoc(); 1018 if (getParser().parseAbsoluteExpression(ByteAlignment)) 1019 return true; 1020 if (!isPowerOf2_64(ByteAlignment)) 1021 return Error(ByteAlignmentLoc, "alignment must be a power of 2"); 1022 } 1023 1024 int64_t AccessAlignment = 0; 1025 if (getLexer().is(AsmToken::Comma)) { 1026 // The optional access argument specifies the size of the smallest memory 1027 // access to be made to the symbol, expressed in bytes. 1028 SMLoc AccessAlignmentLoc; 1029 Lex(); 1030 AccessAlignmentLoc = getLexer().getLoc(); 1031 if (getParser().parseAbsoluteExpression(AccessAlignment)) 1032 return true; 1033 1034 if (!isPowerOf2_64(AccessAlignment)) 1035 return Error(AccessAlignmentLoc, "access alignment must be a power of 2"); 1036 } 1037 1038 if (getLexer().isNot(AsmToken::EndOfStatement)) 1039 return TokError("unexpected token in '.comm' or '.lcomm' directive"); 1040 1041 Lex(); 1042 1043 // NOTE: a size of zero for a .comm should create a undefined symbol 1044 // but a size of .lcomm creates a bss symbol of size zero. 1045 if (Size < 0) 1046 return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't " 1047 "be less than zero"); 1048 1049 // NOTE: The alignment in the directive is a power of 2 value, the assembler 1050 // may internally end up wanting an alignment in bytes. 1051 // FIXME: Diagnose overflow. 1052 if (ByteAlignment < 0) 1053 return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive " 1054 "alignment, can't be less than zero"); 1055 1056 if (!Sym->isUndefined()) 1057 return Error(Loc, "invalid symbol redefinition"); 1058 1059 HexagonMCELFStreamer &HexagonELFStreamer = 1060 static_cast<HexagonMCELFStreamer &>(getStreamer()); 1061 if (IsLocal) { 1062 HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment, 1063 AccessAlignment); 1064 return false; 1065 } 1066 1067 HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment, 1068 AccessAlignment); 1069 return false; 1070 } 1071 1072 // validate register against architecture 1073 bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const { 1074 return true; 1075 } 1076 1077 // extern "C" void LLVMInitializeHexagonAsmLexer(); 1078 1079 /// Force static initialization. 1080 extern "C" void LLVMInitializeHexagonAsmParser() { 1081 RegisterMCAsmParser<HexagonAsmParser> X(TheHexagonTarget); 1082 } 1083 1084 #define GET_MATCHER_IMPLEMENTATION 1085 #define GET_REGISTER_MATCHER 1086 #include "HexagonGenAsmMatcher.inc" 1087 1088 namespace { 1089 bool previousEqual(OperandVector &Operands, size_t Index, StringRef String) { 1090 if (Index >= Operands.size()) 1091 return false; 1092 MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1]; 1093 if (!Operand.isToken()) 1094 return false; 1095 return static_cast<HexagonOperand &>(Operand).getToken().equals_lower(String); 1096 } 1097 bool previousIsLoop(OperandVector &Operands, size_t Index) { 1098 return previousEqual(Operands, Index, "loop0") || 1099 previousEqual(Operands, Index, "loop1") || 1100 previousEqual(Operands, Index, "sp1loop0") || 1101 previousEqual(Operands, Index, "sp2loop0") || 1102 previousEqual(Operands, Index, "sp3loop0"); 1103 } 1104 } 1105 1106 bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) { 1107 AsmToken const &Token = getParser().getTok(); 1108 StringRef String = Token.getString(); 1109 SMLoc Loc = Token.getLoc(); 1110 getLexer().Lex(); 1111 do { 1112 std::pair<StringRef, StringRef> HeadTail = String.split('.'); 1113 if (!HeadTail.first.empty()) 1114 Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc)); 1115 if (!HeadTail.second.empty()) 1116 Operands.push_back(HexagonOperand::CreateToken( 1117 String.substr(HeadTail.first.size(), 1), Loc)); 1118 String = HeadTail.second; 1119 } while (!String.empty()); 1120 return false; 1121 } 1122 1123 bool HexagonAsmParser::parseOperand(OperandVector &Operands) { 1124 unsigned Register; 1125 SMLoc Begin; 1126 SMLoc End; 1127 MCAsmLexer &Lexer = getLexer(); 1128 if (!ParseRegister(Register, Begin, End)) { 1129 if (!ErrorMissingParenthesis) 1130 switch (Register) { 1131 default: 1132 break; 1133 case Hexagon::P0: 1134 case Hexagon::P1: 1135 case Hexagon::P2: 1136 case Hexagon::P3: 1137 if (previousEqual(Operands, 0, "if")) { 1138 if (WarnMissingParenthesis) 1139 Warning (Begin, "Missing parenthesis around predicate register"); 1140 static char const *LParen = "("; 1141 static char const *RParen = ")"; 1142 Operands.push_back(HexagonOperand::CreateToken(LParen, Begin)); 1143 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); 1144 AsmToken MaybeDotNew = Lexer.getTok(); 1145 if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) && 1146 MaybeDotNew.getString().equals_lower(".new")) 1147 splitIdentifier(Operands); 1148 Operands.push_back(HexagonOperand::CreateToken(RParen, Begin)); 1149 return false; 1150 } 1151 if (previousEqual(Operands, 0, "!") && 1152 previousEqual(Operands, 1, "if")) { 1153 if (WarnMissingParenthesis) 1154 Warning (Begin, "Missing parenthesis around predicate register"); 1155 static char const *LParen = "("; 1156 static char const *RParen = ")"; 1157 Operands.insert(Operands.end () - 1, 1158 HexagonOperand::CreateToken(LParen, Begin)); 1159 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); 1160 AsmToken MaybeDotNew = Lexer.getTok(); 1161 if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) && 1162 MaybeDotNew.getString().equals_lower(".new")) 1163 splitIdentifier(Operands); 1164 Operands.push_back(HexagonOperand::CreateToken(RParen, Begin)); 1165 return false; 1166 } 1167 break; 1168 } 1169 Operands.push_back(HexagonOperand::CreateReg( 1170 Register, Begin, End)); 1171 return false; 1172 } 1173 return splitIdentifier(Operands); 1174 } 1175 1176 bool HexagonAsmParser::isLabel(AsmToken &Token) { 1177 MCAsmLexer &Lexer = getLexer(); 1178 AsmToken const &Second = Lexer.getTok(); 1179 AsmToken Third = Lexer.peekTok(); 1180 StringRef String = Token.getString(); 1181 if (Token.is(AsmToken::TokenKind::LCurly) || 1182 Token.is(AsmToken::TokenKind::RCurly)) 1183 return false; 1184 if (!Token.is(AsmToken::TokenKind::Identifier)) 1185 return true; 1186 if (!MatchRegisterName(String.lower())) 1187 return true; 1188 (void)Second; 1189 assert(Second.is(AsmToken::Colon)); 1190 StringRef Raw (String.data(), Third.getString().data() - String.data() + 1191 Third.getString().size()); 1192 std::string Collapsed = Raw; 1193 Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace), 1194 Collapsed.end()); 1195 StringRef Whole = Collapsed; 1196 std::pair<StringRef, StringRef> DotSplit = Whole.split('.'); 1197 if (!MatchRegisterName(DotSplit.first.lower())) 1198 return true; 1199 return false; 1200 } 1201 1202 bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) { 1203 if (!Contigious && ErrorNoncontigiousRegister) { 1204 Error(Loc, "Register name is not contigious"); 1205 return true; 1206 } 1207 if (!Contigious && WarnNoncontigiousRegister) 1208 Warning(Loc, "Register name is not contigious"); 1209 return false; 1210 } 1211 1212 bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1213 MCAsmLexer &Lexer = getLexer(); 1214 StartLoc = getLexer().getLoc(); 1215 SmallVector<AsmToken, 5> Lookahead; 1216 StringRef RawString(Lexer.getTok().getString().data(), 0); 1217 bool Again = Lexer.is(AsmToken::Identifier); 1218 bool NeededWorkaround = false; 1219 while (Again) { 1220 AsmToken const &Token = Lexer.getTok(); 1221 RawString = StringRef(RawString.data(), 1222 Token.getString().data() - RawString.data () + 1223 Token.getString().size()); 1224 Lookahead.push_back(Token); 1225 Lexer.Lex(); 1226 bool Contigious = Lexer.getTok().getString().data() == 1227 Lookahead.back().getString().data() + 1228 Lookahead.back().getString().size(); 1229 bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) || 1230 Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) || 1231 Lexer.is(AsmToken::Colon); 1232 bool Workaround = Lexer.is(AsmToken::Colon) || 1233 Lookahead.back().is(AsmToken::Colon); 1234 Again = (Contigious && Type) || (Workaround && Type); 1235 NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type)); 1236 } 1237 std::string Collapsed = RawString; 1238 Collapsed.erase(std::remove_if(Collapsed.begin(), Collapsed.end(), isspace), 1239 Collapsed.end()); 1240 StringRef FullString = Collapsed; 1241 std::pair<StringRef, StringRef> DotSplit = FullString.split('.'); 1242 unsigned DotReg = MatchRegisterName(DotSplit.first.lower()); 1243 if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) { 1244 if (DotSplit.second.empty()) { 1245 RegNo = DotReg; 1246 EndLoc = Lexer.getLoc(); 1247 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) 1248 return true; 1249 return false; 1250 } else { 1251 RegNo = DotReg; 1252 size_t First = RawString.find('.'); 1253 StringRef DotString (RawString.data() + First, RawString.size() - First); 1254 Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString)); 1255 EndLoc = Lexer.getLoc(); 1256 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) 1257 return true; 1258 return false; 1259 } 1260 } 1261 std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':'); 1262 unsigned ColonReg = MatchRegisterName(ColonSplit.first.lower()); 1263 if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) { 1264 Lexer.UnLex(Lookahead.back()); 1265 Lookahead.pop_back(); 1266 Lexer.UnLex(Lookahead.back()); 1267 Lookahead.pop_back(); 1268 RegNo = ColonReg; 1269 EndLoc = Lexer.getLoc(); 1270 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) 1271 return true; 1272 return false; 1273 } 1274 while (!Lookahead.empty()) { 1275 Lexer.UnLex(Lookahead.back()); 1276 Lookahead.pop_back(); 1277 } 1278 return true; 1279 } 1280 1281 bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) { 1282 if (previousEqual(Operands, 0, "call")) 1283 return true; 1284 if (previousEqual(Operands, 0, "jump")) 1285 if (!getLexer().getTok().is(AsmToken::Colon)) 1286 return true; 1287 if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1)) 1288 return true; 1289 if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") && 1290 (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t"))) 1291 return true; 1292 return false; 1293 } 1294 1295 bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) { 1296 llvm::SmallVector<AsmToken, 4> Tokens; 1297 MCAsmLexer &Lexer = getLexer(); 1298 bool Done = false; 1299 static char const * Comma = ","; 1300 do { 1301 Tokens.emplace_back (Lexer.getTok()); 1302 Lexer.Lex(); 1303 switch (Tokens.back().getKind()) 1304 { 1305 case AsmToken::TokenKind::Hash: 1306 if (Tokens.size () > 1) 1307 if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) { 1308 Tokens.insert(Tokens.end() - 2, 1309 AsmToken(AsmToken::TokenKind::Comma, Comma)); 1310 Done = true; 1311 } 1312 break; 1313 case AsmToken::TokenKind::RCurly: 1314 case AsmToken::TokenKind::EndOfStatement: 1315 case AsmToken::TokenKind::Eof: 1316 Done = true; 1317 break; 1318 default: 1319 break; 1320 } 1321 } while (!Done); 1322 while (!Tokens.empty()) { 1323 Lexer.UnLex(Tokens.back()); 1324 Tokens.pop_back(); 1325 } 1326 return getParser().parseExpression(Expr); 1327 } 1328 1329 bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) { 1330 if (implicitExpressionLocation(Operands)) { 1331 MCAsmParser &Parser = getParser(); 1332 SMLoc Loc = Parser.getLexer().getLoc(); 1333 MCExpr const *Expr = nullptr; 1334 bool Error = parseExpression(Expr); 1335 Expr = HexagonMCExpr::create(Expr, getContext()); 1336 if (!Error) 1337 Operands.push_back(HexagonOperand::CreateImm(Expr, Loc, Loc)); 1338 return Error; 1339 } 1340 return parseOperand(Operands); 1341 } 1342 1343 /// Parse an instruction. 1344 bool HexagonAsmParser::parseInstruction(OperandVector &Operands) { 1345 MCAsmParser &Parser = getParser(); 1346 MCAsmLexer &Lexer = getLexer(); 1347 while (true) { 1348 AsmToken const &Token = Parser.getTok(); 1349 switch (Token.getKind()) { 1350 case AsmToken::EndOfStatement: { 1351 Lexer.Lex(); 1352 return false; 1353 } 1354 case AsmToken::LCurly: { 1355 if (!Operands.empty()) 1356 return true; 1357 Operands.push_back( 1358 HexagonOperand::CreateToken(Token.getString(), Token.getLoc())); 1359 Lexer.Lex(); 1360 return false; 1361 } 1362 case AsmToken::RCurly: { 1363 if (Operands.empty()) { 1364 Operands.push_back( 1365 HexagonOperand::CreateToken(Token.getString(), Token.getLoc())); 1366 Lexer.Lex(); 1367 } 1368 return false; 1369 } 1370 case AsmToken::Comma: { 1371 Lexer.Lex(); 1372 continue; 1373 } 1374 case AsmToken::EqualEqual: 1375 case AsmToken::ExclaimEqual: 1376 case AsmToken::GreaterEqual: 1377 case AsmToken::GreaterGreater: 1378 case AsmToken::LessEqual: 1379 case AsmToken::LessLess: { 1380 Operands.push_back(HexagonOperand::CreateToken( 1381 Token.getString().substr(0, 1), Token.getLoc())); 1382 Operands.push_back(HexagonOperand::CreateToken( 1383 Token.getString().substr(1, 1), Token.getLoc())); 1384 Lexer.Lex(); 1385 continue; 1386 } 1387 case AsmToken::Hash: { 1388 bool MustNotExtend = false; 1389 bool ImplicitExpression = implicitExpressionLocation(Operands); 1390 SMLoc ExprLoc = Lexer.getLoc(); 1391 if (!ImplicitExpression) 1392 Operands.push_back( 1393 HexagonOperand::CreateToken(Token.getString(), Token.getLoc())); 1394 Lexer.Lex(); 1395 bool MustExtend = false; 1396 bool HiOnly = false; 1397 bool LoOnly = false; 1398 if (Lexer.is(AsmToken::Hash)) { 1399 Lexer.Lex(); 1400 MustExtend = true; 1401 } else if (ImplicitExpression) 1402 MustNotExtend = true; 1403 AsmToken const &Token = Parser.getTok(); 1404 if (Token.is(AsmToken::Identifier)) { 1405 StringRef String = Token.getString(); 1406 AsmToken IDToken = Token; 1407 if (String.lower() == "hi") { 1408 HiOnly = true; 1409 } else if (String.lower() == "lo") { 1410 LoOnly = true; 1411 } 1412 if (HiOnly || LoOnly) { 1413 AsmToken LParen = Lexer.peekTok(); 1414 if (!LParen.is(AsmToken::LParen)) { 1415 HiOnly = false; 1416 LoOnly = false; 1417 } else { 1418 Lexer.Lex(); 1419 } 1420 } 1421 } 1422 MCExpr const *Expr = nullptr; 1423 if (parseExpression(Expr)) 1424 return true; 1425 int64_t Value; 1426 MCContext &Context = Parser.getContext(); 1427 assert(Expr != nullptr); 1428 if (Expr->evaluateAsAbsolute(Value)) { 1429 if (HiOnly) 1430 Expr = MCBinaryExpr::createLShr( 1431 Expr, MCConstantExpr::create(16, Context), Context); 1432 if (HiOnly || LoOnly) 1433 Expr = MCBinaryExpr::createAnd(Expr, 1434 MCConstantExpr::create(0xffff, Context), 1435 Context); 1436 } 1437 Expr = HexagonMCExpr::create(Expr, Context); 1438 HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend); 1439 HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend); 1440 std::unique_ptr<HexagonOperand> Operand = 1441 HexagonOperand::CreateImm(Expr, ExprLoc, ExprLoc); 1442 Operands.push_back(std::move(Operand)); 1443 continue; 1444 } 1445 default: 1446 break; 1447 } 1448 if (parseExpressionOrOperand(Operands)) 1449 return true; 1450 } 1451 } 1452 1453 bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info, 1454 StringRef Name, 1455 AsmToken ID, 1456 OperandVector &Operands) { 1457 getLexer().UnLex(ID); 1458 return parseInstruction(Operands); 1459 } 1460 1461 namespace { 1462 MCInst makeCombineInst(int opCode, MCOperand &Rdd, 1463 MCOperand &MO1, MCOperand &MO2) { 1464 MCInst TmpInst; 1465 TmpInst.setOpcode(opCode); 1466 TmpInst.addOperand(Rdd); 1467 TmpInst.addOperand(MO1); 1468 TmpInst.addOperand(MO2); 1469 1470 return TmpInst; 1471 } 1472 } 1473 1474 // Define this matcher function after the auto-generated include so we 1475 // have the match class enum definitions. 1476 unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1477 unsigned Kind) { 1478 HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp); 1479 1480 switch (Kind) { 1481 case MCK_0: { 1482 int64_t Value; 1483 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0 1484 ? Match_Success 1485 : Match_InvalidOperand; 1486 } 1487 case MCK_1: { 1488 int64_t Value; 1489 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1 1490 ? Match_Success 1491 : Match_InvalidOperand; 1492 } 1493 case MCK__MINUS_1: { 1494 int64_t Value; 1495 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == -1 1496 ? Match_Success 1497 : Match_InvalidOperand; 1498 } 1499 } 1500 if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) { 1501 StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length); 1502 if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind) 1503 return Match_Success; 1504 if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind) 1505 return Match_Success; 1506 } 1507 1508 DEBUG(dbgs() << "Unmatched Operand:"); 1509 DEBUG(Op->dump()); 1510 DEBUG(dbgs() << "\n"); 1511 1512 return Match_InvalidOperand; 1513 } 1514 1515 void HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) { 1516 std::string errStr; 1517 raw_string_ostream ES(errStr); 1518 ES << "value " << Val << "(" << format_hex(Val, 0) << ") out of range: "; 1519 if (Max >= 0) 1520 ES << "0-" << Max; 1521 else 1522 ES << Max << "-" << (-Max - 1); 1523 Error(IDLoc, ES.str().c_str()); 1524 } 1525 1526 int HexagonAsmParser::processInstruction(MCInst &Inst, 1527 OperandVector const &Operands, 1528 SMLoc IDLoc) { 1529 MCContext &Context = getParser().getContext(); 1530 const MCRegisterInfo *RI = getContext().getRegisterInfo(); 1531 std::string r = "r"; 1532 std::string v = "v"; 1533 std::string Colon = ":"; 1534 1535 bool is32bit = false; // used to distinguish between CONST32 and CONST64 1536 switch (Inst.getOpcode()) { 1537 default: 1538 break; 1539 1540 case Hexagon::A2_iconst: { 1541 Inst.setOpcode(Hexagon::A2_addi); 1542 MCOperand Reg = Inst.getOperand(0); 1543 MCOperand S16 = Inst.getOperand(1); 1544 HexagonMCInstrInfo::setMustNotExtend(*S16.getExpr()); 1545 HexagonMCInstrInfo::setS23_2_reloc(*S16.getExpr()); 1546 Inst.clear(); 1547 Inst.addOperand(Reg); 1548 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); 1549 Inst.addOperand(S16); 1550 break; 1551 } 1552 case Hexagon::M4_mpyrr_addr: 1553 case Hexagon::S4_addi_asl_ri: 1554 case Hexagon::S4_addi_lsr_ri: 1555 case Hexagon::S4_andi_asl_ri: 1556 case Hexagon::S4_andi_lsr_ri: 1557 case Hexagon::S4_ori_asl_ri: 1558 case Hexagon::S4_ori_lsr_ri: 1559 case Hexagon::S4_or_andix: 1560 case Hexagon::S4_subi_asl_ri: 1561 case Hexagon::S4_subi_lsr_ri: { 1562 MCOperand &Ry = Inst.getOperand(0); 1563 MCOperand &src = Inst.getOperand(2); 1564 if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg())) 1565 return Match_InvalidOperand; 1566 break; 1567 } 1568 1569 case Hexagon::C2_cmpgei: { 1570 MCOperand &MO = Inst.getOperand(2); 1571 MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( 1572 MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context)); 1573 Inst.setOpcode(Hexagon::C2_cmpgti); 1574 break; 1575 } 1576 1577 case Hexagon::C2_cmpgeui: { 1578 MCOperand &MO = Inst.getOperand(2); 1579 int64_t Value; 1580 bool Success = MO.getExpr()->evaluateAsAbsolute(Value); 1581 (void)Success; 1582 assert(Success && "Assured by matcher"); 1583 if (Value == 0) { 1584 MCInst TmpInst; 1585 MCOperand &Pd = Inst.getOperand(0); 1586 MCOperand &Rt = Inst.getOperand(1); 1587 TmpInst.setOpcode(Hexagon::C2_cmpeq); 1588 TmpInst.addOperand(Pd); 1589 TmpInst.addOperand(Rt); 1590 TmpInst.addOperand(Rt); 1591 Inst = TmpInst; 1592 } else { 1593 MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( 1594 MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context)); 1595 Inst.setOpcode(Hexagon::C2_cmpgtui); 1596 } 1597 break; 1598 } 1599 1600 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)" 1601 case Hexagon::A2_tfrp: { 1602 MCOperand &MO = Inst.getOperand(1); 1603 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); 1604 std::string R1 = r + llvm::utostr(RegPairNum + 1); 1605 StringRef Reg1(R1); 1606 MO.setReg(MatchRegisterName(Reg1)); 1607 // Add a new operand for the second register in the pair. 1608 std::string R2 = r + llvm::utostr(RegPairNum); 1609 StringRef Reg2(R2); 1610 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); 1611 Inst.setOpcode(Hexagon::A2_combinew); 1612 break; 1613 } 1614 1615 case Hexagon::A2_tfrpt: 1616 case Hexagon::A2_tfrpf: { 1617 MCOperand &MO = Inst.getOperand(2); 1618 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); 1619 std::string R1 = r + llvm::utostr(RegPairNum + 1); 1620 StringRef Reg1(R1); 1621 MO.setReg(MatchRegisterName(Reg1)); 1622 // Add a new operand for the second register in the pair. 1623 std::string R2 = r + llvm::utostr(RegPairNum); 1624 StringRef Reg2(R2); 1625 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); 1626 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) 1627 ? Hexagon::C2_ccombinewt 1628 : Hexagon::C2_ccombinewf); 1629 break; 1630 } 1631 case Hexagon::A2_tfrptnew: 1632 case Hexagon::A2_tfrpfnew: { 1633 MCOperand &MO = Inst.getOperand(2); 1634 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg()); 1635 std::string R1 = r + llvm::utostr(RegPairNum + 1); 1636 StringRef Reg1(R1); 1637 MO.setReg(MatchRegisterName(Reg1)); 1638 // Add a new operand for the second register in the pair. 1639 std::string R2 = r + llvm::utostr(RegPairNum); 1640 StringRef Reg2(R2); 1641 Inst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); 1642 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew) 1643 ? Hexagon::C2_ccombinewnewt 1644 : Hexagon::C2_ccombinewnewf); 1645 break; 1646 } 1647 1648 // Translate a "$Rx = CONST32(#imm)" to "$Rx = memw(gp+#LABEL) " 1649 case Hexagon::CONST32: 1650 case Hexagon::CONST32_Float_Real: 1651 case Hexagon::CONST32_Int_Real: 1652 case Hexagon::FCONST32_nsdata: 1653 is32bit = true; 1654 // Translate a "$Rx:y = CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) " 1655 case Hexagon::CONST64_Float_Real: 1656 case Hexagon::CONST64_Int_Real: 1657 1658 // FIXME: need better way to detect AsmStreamer (upstream removed getKind()) 1659 if (!Parser.getStreamer().hasRawTextSupport()) { 1660 MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer()); 1661 MCOperand &MO_1 = Inst.getOperand(1); 1662 MCOperand &MO_0 = Inst.getOperand(0); 1663 1664 // push section onto section stack 1665 MES->PushSection(); 1666 1667 std::string myCharStr; 1668 MCSectionELF *mySection; 1669 1670 // check if this as an immediate or a symbol 1671 int64_t Value; 1672 bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value); 1673 if (Absolute) { 1674 // Create a new section - one for each constant 1675 // Some or all of the zeros are replaced with the given immediate. 1676 if (is32bit) { 1677 std::string myImmStr = utohexstr(static_cast<uint32_t>(Value)); 1678 myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000") 1679 .drop_back(myImmStr.size()) 1680 .str() + 1681 myImmStr; 1682 } else { 1683 std::string myImmStr = utohexstr(Value); 1684 myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000") 1685 .drop_back(myImmStr.size()) 1686 .str() + 1687 myImmStr; 1688 } 1689 1690 mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS, 1691 ELF::SHF_ALLOC | ELF::SHF_WRITE); 1692 } else if (MO_1.isExpr()) { 1693 // .lita - for expressions 1694 myCharStr = ".lita"; 1695 mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS, 1696 ELF::SHF_ALLOC | ELF::SHF_WRITE); 1697 } else 1698 llvm_unreachable("unexpected type of machine operand!"); 1699 1700 MES->SwitchSection(mySection); 1701 unsigned byteSize = is32bit ? 4 : 8; 1702 getStreamer().EmitCodeAlignment(byteSize, byteSize); 1703 1704 MCSymbol *Sym; 1705 1706 // for symbols, get rid of prepended ".gnu.linkonce.lx." 1707 1708 // emit symbol if needed 1709 if (Absolute) { 1710 Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16)); 1711 if (Sym->isUndefined()) { 1712 getStreamer().EmitLabel(Sym); 1713 getStreamer().EmitSymbolAttribute(Sym, MCSA_Global); 1714 getStreamer().EmitIntValue(Value, byteSize); 1715 } 1716 } else if (MO_1.isExpr()) { 1717 const char *StringStart = 0; 1718 const char *StringEnd = 0; 1719 if (*Operands[4]->getStartLoc().getPointer() == '#') { 1720 StringStart = Operands[5]->getStartLoc().getPointer(); 1721 StringEnd = Operands[6]->getStartLoc().getPointer(); 1722 } else { // no pound 1723 StringStart = Operands[4]->getStartLoc().getPointer(); 1724 StringEnd = Operands[5]->getStartLoc().getPointer(); 1725 } 1726 1727 unsigned size = StringEnd - StringStart; 1728 std::string DotConst = ".CONST_"; 1729 Sym = getContext().getOrCreateSymbol(DotConst + 1730 StringRef(StringStart, size)); 1731 1732 if (Sym->isUndefined()) { 1733 // case where symbol is not yet defined: emit symbol 1734 getStreamer().EmitLabel(Sym); 1735 getStreamer().EmitSymbolAttribute(Sym, MCSA_Local); 1736 getStreamer().EmitValue(MO_1.getExpr(), 4); 1737 } 1738 } else 1739 llvm_unreachable("unexpected type of machine operand!"); 1740 1741 MES->PopSection(); 1742 1743 if (Sym) { 1744 MCInst TmpInst; 1745 if (is32bit) // 32 bit 1746 TmpInst.setOpcode(Hexagon::L2_loadrigp); 1747 else // 64 bit 1748 TmpInst.setOpcode(Hexagon::L2_loadrdgp); 1749 1750 TmpInst.addOperand(MO_0); 1751 TmpInst.addOperand( 1752 MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext()))); 1753 Inst = TmpInst; 1754 } 1755 } 1756 break; 1757 1758 // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)" 1759 case Hexagon::A2_tfrpi: { 1760 MCOperand &Rdd = Inst.getOperand(0); 1761 MCOperand &MO = Inst.getOperand(1); 1762 int64_t Value; 1763 int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0; 1764 MCOperand imm(MCOperand::createExpr( 1765 HexagonMCExpr::create(MCConstantExpr::create(sVal, Context), Context))); 1766 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO); 1767 break; 1768 } 1769 1770 // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)" 1771 case Hexagon::TFRI64_V4: { 1772 MCOperand &Rdd = Inst.getOperand(0); 1773 MCOperand &MO = Inst.getOperand(1); 1774 int64_t Value; 1775 if (MO.getExpr()->evaluateAsAbsolute(Value)) { 1776 unsigned long long u64 = Value; 1777 signed int s8 = (u64 >> 32) & 0xFFFFFFFF; 1778 if (s8 < -128 || s8 > 127) 1779 OutOfRange(IDLoc, s8, -128); 1780 MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create( 1781 MCConstantExpr::create(s8, Context), Context))); // upper 32 1782 auto Expr = HexagonMCExpr::create( 1783 MCConstantExpr::create(u64 & 0xFFFFFFFF, Context), 1784 Context); 1785 HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr())); 1786 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 1787 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); 1788 } else { 1789 MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create( 1790 MCConstantExpr::create(0, Context), Context))); // upper 32 1791 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO); 1792 } 1793 break; 1794 } 1795 1796 // Handle $Rdd = combine(##imm, #imm)" 1797 case Hexagon::TFRI64_V2_ext: { 1798 MCOperand &Rdd = Inst.getOperand(0); 1799 MCOperand &MO1 = Inst.getOperand(1); 1800 MCOperand &MO2 = Inst.getOperand(2); 1801 int64_t Value; 1802 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { 1803 int s8 = Value; 1804 if (s8 < -128 || s8 > 127) 1805 OutOfRange(IDLoc, s8, -128); 1806 } 1807 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); 1808 break; 1809 } 1810 1811 // Handle $Rdd = combine(#imm, ##imm)" 1812 case Hexagon::A4_combineii: { 1813 MCOperand &Rdd = Inst.getOperand(0); 1814 MCOperand &MO1 = Inst.getOperand(1); 1815 int64_t Value; 1816 if (MO1.getExpr()->evaluateAsAbsolute(Value)) { 1817 int s8 = Value; 1818 if (s8 < -128 || s8 > 127) 1819 OutOfRange(IDLoc, s8, -128); 1820 } 1821 MCOperand &MO2 = Inst.getOperand(2); 1822 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); 1823 break; 1824 } 1825 1826 case Hexagon::S2_tableidxb_goodsyntax: { 1827 Inst.setOpcode(Hexagon::S2_tableidxb); 1828 break; 1829 } 1830 1831 case Hexagon::S2_tableidxh_goodsyntax: { 1832 MCInst TmpInst; 1833 MCOperand &Rx = Inst.getOperand(0); 1834 MCOperand &_dst_ = Inst.getOperand(1); 1835 MCOperand &Rs = Inst.getOperand(2); 1836 MCOperand &Imm4 = Inst.getOperand(3); 1837 MCOperand &Imm6 = Inst.getOperand(4); 1838 Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( 1839 Imm6.getExpr(), MCConstantExpr::create(1, Context), Context), Context)); 1840 TmpInst.setOpcode(Hexagon::S2_tableidxh); 1841 TmpInst.addOperand(Rx); 1842 TmpInst.addOperand(_dst_); 1843 TmpInst.addOperand(Rs); 1844 TmpInst.addOperand(Imm4); 1845 TmpInst.addOperand(Imm6); 1846 Inst = TmpInst; 1847 break; 1848 } 1849 1850 case Hexagon::S2_tableidxw_goodsyntax: { 1851 MCInst TmpInst; 1852 MCOperand &Rx = Inst.getOperand(0); 1853 MCOperand &_dst_ = Inst.getOperand(1); 1854 MCOperand &Rs = Inst.getOperand(2); 1855 MCOperand &Imm4 = Inst.getOperand(3); 1856 MCOperand &Imm6 = Inst.getOperand(4); 1857 Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( 1858 Imm6.getExpr(), MCConstantExpr::create(2, Context), Context), Context)); 1859 TmpInst.setOpcode(Hexagon::S2_tableidxw); 1860 TmpInst.addOperand(Rx); 1861 TmpInst.addOperand(_dst_); 1862 TmpInst.addOperand(Rs); 1863 TmpInst.addOperand(Imm4); 1864 TmpInst.addOperand(Imm6); 1865 Inst = TmpInst; 1866 break; 1867 } 1868 1869 case Hexagon::S2_tableidxd_goodsyntax: { 1870 MCInst TmpInst; 1871 MCOperand &Rx = Inst.getOperand(0); 1872 MCOperand &_dst_ = Inst.getOperand(1); 1873 MCOperand &Rs = Inst.getOperand(2); 1874 MCOperand &Imm4 = Inst.getOperand(3); 1875 MCOperand &Imm6 = Inst.getOperand(4); 1876 Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( 1877 Imm6.getExpr(), MCConstantExpr::create(3, Context), Context), Context)); 1878 TmpInst.setOpcode(Hexagon::S2_tableidxd); 1879 TmpInst.addOperand(Rx); 1880 TmpInst.addOperand(_dst_); 1881 TmpInst.addOperand(Rs); 1882 TmpInst.addOperand(Imm4); 1883 TmpInst.addOperand(Imm6); 1884 Inst = TmpInst; 1885 break; 1886 } 1887 1888 case Hexagon::M2_mpyui: { 1889 Inst.setOpcode(Hexagon::M2_mpyi); 1890 break; 1891 } 1892 case Hexagon::M2_mpysmi: { 1893 MCInst TmpInst; 1894 MCOperand &Rd = Inst.getOperand(0); 1895 MCOperand &Rs = Inst.getOperand(1); 1896 MCOperand &Imm = Inst.getOperand(2); 1897 int64_t Value; 1898 MCExpr const &Expr = *Imm.getExpr(); 1899 bool Absolute = Expr.evaluateAsAbsolute(Value); 1900 assert(Absolute); 1901 (void)Absolute; 1902 if (!HexagonMCInstrInfo::mustExtend(Expr)) { 1903 if (Value < 0 && Value > -256) { 1904 Imm.setExpr(HexagonMCExpr::create( 1905 MCConstantExpr::create(Value * -1, Context), Context)); 1906 TmpInst.setOpcode(Hexagon::M2_mpysin); 1907 } else if (Value < 256 && Value >= 0) 1908 TmpInst.setOpcode(Hexagon::M2_mpysip); 1909 else 1910 return Match_InvalidOperand; 1911 } else { 1912 if (Value >= 0) 1913 TmpInst.setOpcode(Hexagon::M2_mpysip); 1914 else 1915 return Match_InvalidOperand; 1916 } 1917 TmpInst.addOperand(Rd); 1918 TmpInst.addOperand(Rs); 1919 TmpInst.addOperand(Imm); 1920 Inst = TmpInst; 1921 break; 1922 } 1923 1924 case Hexagon::S2_asr_i_r_rnd_goodsyntax: { 1925 MCOperand &Imm = Inst.getOperand(2); 1926 MCInst TmpInst; 1927 int64_t Value; 1928 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); 1929 assert(Absolute); 1930 (void)Absolute; 1931 if (Value == 0) { // convert to $Rd = $Rs 1932 TmpInst.setOpcode(Hexagon::A2_tfr); 1933 MCOperand &Rd = Inst.getOperand(0); 1934 MCOperand &Rs = Inst.getOperand(1); 1935 TmpInst.addOperand(Rd); 1936 TmpInst.addOperand(Rs); 1937 } else { 1938 Imm.setExpr(HexagonMCExpr::create( 1939 MCBinaryExpr::createSub(Imm.getExpr(), 1940 MCConstantExpr::create(1, Context), Context), 1941 Context)); 1942 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd); 1943 MCOperand &Rd = Inst.getOperand(0); 1944 MCOperand &Rs = Inst.getOperand(1); 1945 TmpInst.addOperand(Rd); 1946 TmpInst.addOperand(Rs); 1947 TmpInst.addOperand(Imm); 1948 } 1949 Inst = TmpInst; 1950 break; 1951 } 1952 1953 case Hexagon::S2_asr_i_p_rnd_goodsyntax: { 1954 MCOperand &Rdd = Inst.getOperand(0); 1955 MCOperand &Rss = Inst.getOperand(1); 1956 MCOperand &Imm = Inst.getOperand(2); 1957 int64_t Value; 1958 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); 1959 assert(Absolute); 1960 (void)Absolute; 1961 if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1]) 1962 MCInst TmpInst; 1963 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); 1964 std::string R1 = r + llvm::utostr(RegPairNum + 1); 1965 StringRef Reg1(R1); 1966 Rss.setReg(MatchRegisterName(Reg1)); 1967 // Add a new operand for the second register in the pair. 1968 std::string R2 = r + llvm::utostr(RegPairNum); 1969 StringRef Reg2(R2); 1970 TmpInst.setOpcode(Hexagon::A2_combinew); 1971 TmpInst.addOperand(Rdd); 1972 TmpInst.addOperand(Rss); 1973 TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); 1974 Inst = TmpInst; 1975 } else { 1976 Imm.setExpr(HexagonMCExpr::create( 1977 MCBinaryExpr::createSub(Imm.getExpr(), 1978 MCConstantExpr::create(1, Context), Context), 1979 Context)); 1980 Inst.setOpcode(Hexagon::S2_asr_i_p_rnd); 1981 } 1982 break; 1983 } 1984 1985 case Hexagon::A4_boundscheck: { 1986 MCOperand &Rs = Inst.getOperand(1); 1987 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); 1988 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 1989 Inst.setOpcode(Hexagon::A4_boundscheck_hi); 1990 std::string Name = 1991 r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1); 1992 StringRef RegPair = Name; 1993 Rs.setReg(MatchRegisterName(RegPair)); 1994 } else { // raw:lo 1995 Inst.setOpcode(Hexagon::A4_boundscheck_lo); 1996 std::string Name = 1997 r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum); 1998 StringRef RegPair = Name; 1999 Rs.setReg(MatchRegisterName(RegPair)); 2000 } 2001 break; 2002 } 2003 2004 case Hexagon::A2_addsp: { 2005 MCOperand &Rs = Inst.getOperand(1); 2006 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); 2007 if (RegNum & 1) { // Odd mapped to raw:hi 2008 Inst.setOpcode(Hexagon::A2_addsph); 2009 std::string Name = 2010 r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1); 2011 StringRef RegPair = Name; 2012 Rs.setReg(MatchRegisterName(RegPair)); 2013 } else { // Even mapped raw:lo 2014 Inst.setOpcode(Hexagon::A2_addspl); 2015 std::string Name = 2016 r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum); 2017 StringRef RegPair = Name; 2018 Rs.setReg(MatchRegisterName(RegPair)); 2019 } 2020 break; 2021 } 2022 2023 case Hexagon::M2_vrcmpys_s1: { 2024 MCOperand &Rt = Inst.getOperand(2); 2025 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); 2026 if (RegNum & 1) { // Odd mapped to sat:raw:hi 2027 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h); 2028 std::string Name = 2029 r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1); 2030 StringRef RegPair = Name; 2031 Rt.setReg(MatchRegisterName(RegPair)); 2032 } else { // Even mapped sat:raw:lo 2033 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l); 2034 std::string Name = 2035 r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum); 2036 StringRef RegPair = Name; 2037 Rt.setReg(MatchRegisterName(RegPair)); 2038 } 2039 break; 2040 } 2041 2042 case Hexagon::M2_vrcmpys_acc_s1: { 2043 MCInst TmpInst; 2044 MCOperand &Rxx = Inst.getOperand(0); 2045 MCOperand &Rss = Inst.getOperand(2); 2046 MCOperand &Rt = Inst.getOperand(3); 2047 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); 2048 if (RegNum & 1) { // Odd mapped to sat:raw:hi 2049 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h); 2050 std::string Name = 2051 r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1); 2052 StringRef RegPair = Name; 2053 Rt.setReg(MatchRegisterName(RegPair)); 2054 } else { // Even mapped sat:raw:lo 2055 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l); 2056 std::string Name = 2057 r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum); 2058 StringRef RegPair = Name; 2059 Rt.setReg(MatchRegisterName(RegPair)); 2060 } 2061 // Registers are in different positions 2062 TmpInst.addOperand(Rxx); 2063 TmpInst.addOperand(Rxx); 2064 TmpInst.addOperand(Rss); 2065 TmpInst.addOperand(Rt); 2066 Inst = TmpInst; 2067 break; 2068 } 2069 2070 case Hexagon::M2_vrcmpys_s1rp: { 2071 MCOperand &Rt = Inst.getOperand(2); 2072 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); 2073 if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi 2074 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h); 2075 std::string Name = 2076 r + llvm::utostr(RegNum) + Colon + llvm::utostr(RegNum - 1); 2077 StringRef RegPair = Name; 2078 Rt.setReg(MatchRegisterName(RegPair)); 2079 } else { // Even mapped rnd:sat:raw:lo 2080 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l); 2081 std::string Name = 2082 r + llvm::utostr(RegNum + 1) + Colon + llvm::utostr(RegNum); 2083 StringRef RegPair = Name; 2084 Rt.setReg(MatchRegisterName(RegPair)); 2085 } 2086 break; 2087 } 2088 2089 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: { 2090 MCOperand &Imm = Inst.getOperand(2); 2091 int64_t Value; 2092 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); 2093 assert(Absolute); 2094 (void)Absolute; 2095 if (Value == 0) 2096 Inst.setOpcode(Hexagon::S2_vsathub); 2097 else { 2098 Imm.setExpr(HexagonMCExpr::create( 2099 MCBinaryExpr::createSub(Imm.getExpr(), 2100 MCConstantExpr::create(1, Context), Context), 2101 Context)); 2102 Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat); 2103 } 2104 break; 2105 } 2106 2107 case Hexagon::S5_vasrhrnd_goodsyntax: { 2108 MCOperand &Rdd = Inst.getOperand(0); 2109 MCOperand &Rss = Inst.getOperand(1); 2110 MCOperand &Imm = Inst.getOperand(2); 2111 int64_t Value; 2112 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value); 2113 assert(Absolute); 2114 (void)Absolute; 2115 if (Value == 0) { 2116 MCInst TmpInst; 2117 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); 2118 std::string R1 = r + llvm::utostr(RegPairNum + 1); 2119 StringRef Reg1(R1); 2120 Rss.setReg(MatchRegisterName(Reg1)); 2121 // Add a new operand for the second register in the pair. 2122 std::string R2 = r + llvm::utostr(RegPairNum); 2123 StringRef Reg2(R2); 2124 TmpInst.setOpcode(Hexagon::A2_combinew); 2125 TmpInst.addOperand(Rdd); 2126 TmpInst.addOperand(Rss); 2127 TmpInst.addOperand(MCOperand::createReg(MatchRegisterName(Reg2))); 2128 Inst = TmpInst; 2129 } else { 2130 Imm.setExpr(HexagonMCExpr::create( 2131 MCBinaryExpr::createSub(Imm.getExpr(), 2132 MCConstantExpr::create(1, Context), Context), 2133 Context)); 2134 Inst.setOpcode(Hexagon::S5_vasrhrnd); 2135 } 2136 break; 2137 } 2138 2139 case Hexagon::A2_not: { 2140 MCInst TmpInst; 2141 MCOperand &Rd = Inst.getOperand(0); 2142 MCOperand &Rs = Inst.getOperand(1); 2143 TmpInst.setOpcode(Hexagon::A2_subri); 2144 TmpInst.addOperand(Rd); 2145 TmpInst.addOperand(MCOperand::createExpr( 2146 HexagonMCExpr::create(MCConstantExpr::create(-1, Context), Context))); 2147 TmpInst.addOperand(Rs); 2148 Inst = TmpInst; 2149 break; 2150 } 2151 } // switch 2152 2153 return Match_Success; 2154 } 2155