xref: /llvm-project/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp (revision a98fc08396cb71f9e0cce4ac8f1525db46f22a9c) 
1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "HexagonTargetStreamer.h"
10 #include "MCTargetDesc/HexagonMCChecker.h"
11 #include "MCTargetDesc/HexagonMCELFStreamer.h"
12 #include "MCTargetDesc/HexagonMCExpr.h"
13 #include "MCTargetDesc/HexagonMCInstrInfo.h"
14 #include "MCTargetDesc/HexagonMCTargetDesc.h"
15 #include "MCTargetDesc/HexagonShuffler.h"
16 #include "TargetInfo/HexagonTargetInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/ADT/StringRef.h"
21 #include "llvm/ADT/Twine.h"
22 #include "llvm/BinaryFormat/ELF.h"
23 #include "llvm/MC/MCAssembler.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCDirectives.h"
26 #include "llvm/MC/MCELFStreamer.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/MC/MCInst.h"
29 #include "llvm/MC/MCParser/MCAsmLexer.h"
30 #include "llvm/MC/MCParser/MCAsmParser.h"
31 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
32 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
33 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSectionELF.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCValue.h"
40 #include "llvm/MC/TargetRegistry.h"
41 #include "llvm/Support/Casting.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/Format.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/SMLoc.h"
48 #include "llvm/Support/SourceMgr.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include <algorithm>
51 #include <cassert>
52 #include <cctype>
53 #include <cstddef>
54 #include <cstdint>
55 #include <memory>
56 #include <string>
57 #include <utility>
58 
59 #define DEBUG_TYPE "mcasmparser"
60 
61 using namespace llvm;
62 
63 static cl::opt<bool> WarnMissingParenthesis(
64     "mwarn-missing-parenthesis",
65     cl::desc("Warn for missing parenthesis around predicate registers"),
66     cl::init(true));
67 static cl::opt<bool> ErrorMissingParenthesis(
68     "merror-missing-parenthesis",
69     cl::desc("Error for missing parenthesis around predicate registers"),
70     cl::init(false));
71 static cl::opt<bool> WarnSignedMismatch(
72     "mwarn-sign-mismatch",
73     cl::desc("Warn for mismatching a signed and unsigned value"),
74     cl::init(true));
75 static cl::opt<bool> WarnNoncontigiousRegister(
76     "mwarn-noncontigious-register",
77     cl::desc("Warn for register names that arent contigious"), cl::init(true));
78 static cl::opt<bool> ErrorNoncontigiousRegister(
79     "merror-noncontigious-register",
80     cl::desc("Error for register names that aren't contigious"),
81     cl::init(false));
82 
83 namespace {
84 
85 struct HexagonOperand;
86 
87 class HexagonAsmParser : public MCTargetAsmParser {
88 
89   HexagonTargetStreamer &getTargetStreamer() {
90     MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
91     return static_cast<HexagonTargetStreamer &>(TS);
92   }
93 
94   MCAsmParser &Parser;
95   MCInst MCB;
96   bool InBrackets;
97 
98   MCAsmParser &getParser() const { return Parser; }
99   MCAssembler *getAssembler() const {
100     MCAssembler *Assembler = nullptr;
101     // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
102     if (!Parser.getStreamer().hasRawTextSupport()) {
103       MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
104       Assembler = &MES->getAssembler();
105     }
106     return Assembler;
107   }
108 
109   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
110 
111   bool equalIsAsmAssignment() override { return false; }
112   bool isLabel(AsmToken &Token) override;
113 
114   void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
115   bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
116   bool ParseDirectiveFalign(unsigned Size, SMLoc L);
117 
118   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
119   OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
120                                         SMLoc &EndLoc) override;
121   bool ParseDirectiveSubsection(SMLoc L);
122   bool ParseDirectiveComm(bool IsLocal, SMLoc L);
123   bool RegisterMatchesArch(unsigned MatchNum) const;
124 
125   bool matchBundleOptions();
126   bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);
127   bool finishBundle(SMLoc IDLoc, MCStreamer &Out);
128   void canonicalizeImmediates(MCInst &MCI);
129   bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
130                            OperandVector &InstOperands, uint64_t &ErrorInfo,
131                            bool MatchingInlineAsm);
132   void eatToEndOfPacket();
133   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
134                                OperandVector &Operands, MCStreamer &Out,
135                                uint64_t &ErrorInfo,
136                                bool MatchingInlineAsm) override;
137 
138   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
139                                       unsigned Kind) override;
140   bool OutOfRange(SMLoc IDLoc, long long Val, long long Max);
141   int processInstruction(MCInst &Inst, OperandVector const &Operands,
142                          SMLoc IDLoc);
143 
144   unsigned matchRegister(StringRef Name);
145 
146 /// @name Auto-generated Match Functions
147 /// {
148 
149 #define GET_ASSEMBLER_HEADER
150 #include "HexagonGenAsmMatcher.inc"
151 
152   /// }
153 
154 public:
155   HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
156                    const MCInstrInfo &MII, const MCTargetOptions &Options)
157     : MCTargetAsmParser(Options, _STI, MII), Parser(_Parser),
158       InBrackets(false) {
159     MCB.setOpcode(Hexagon::BUNDLE);
160     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
161 
162     Parser.addAliasForDirective(".half", ".2byte");
163     Parser.addAliasForDirective(".hword", ".2byte");
164     Parser.addAliasForDirective(".word", ".4byte");
165 
166     MCAsmParserExtension::Initialize(_Parser);
167   }
168 
169   bool splitIdentifier(OperandVector &Operands);
170   bool parseOperand(OperandVector &Operands);
171   bool parseInstruction(OperandVector &Operands);
172   bool implicitExpressionLocation(OperandVector &Operands);
173   bool parseExpressionOrOperand(OperandVector &Operands);
174   bool parseExpression(MCExpr const *&Expr);
175 
176   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
177                         SMLoc NameLoc, OperandVector &Operands) override {
178     llvm_unreachable("Unimplemented");
179   }
180 
181   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, AsmToken ID,
182                         OperandVector &Operands) override;
183 
184   bool ParseDirective(AsmToken DirectiveID) override;
185 };
186 
187 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
188 /// instruction.
189 struct HexagonOperand : public MCParsedAsmOperand {
190   enum KindTy { Token, Immediate, Register } Kind;
191   MCContext &Context;
192 
193   SMLoc StartLoc, EndLoc;
194 
195   struct TokTy {
196     const char *Data;
197     unsigned Length;
198   };
199 
200   struct RegTy {
201     unsigned RegNum;
202   };
203 
204   struct ImmTy {
205     const MCExpr *Val;
206   };
207 
208   union {
209     struct TokTy Tok;
210     struct RegTy Reg;
211     struct ImmTy Imm;
212   };
213 
214   HexagonOperand(KindTy K, MCContext &Context) : Kind(K), Context(Context) {}
215 
216 public:
217   HexagonOperand(const HexagonOperand &o)
218       : MCParsedAsmOperand(), Context(o.Context) {
219     Kind = o.Kind;
220     StartLoc = o.StartLoc;
221     EndLoc = o.EndLoc;
222     switch (Kind) {
223     case Register:
224       Reg = o.Reg;
225       break;
226     case Immediate:
227       Imm = o.Imm;
228       break;
229     case Token:
230       Tok = o.Tok;
231       break;
232     }
233   }
234 
235   /// getStartLoc - Get the location of the first token of this operand.
236   SMLoc getStartLoc() const override { return StartLoc; }
237 
238   /// getEndLoc - Get the location of the last token of this operand.
239   SMLoc getEndLoc() const override { return EndLoc; }
240 
241   unsigned getReg() const override {
242     assert(Kind == Register && "Invalid access!");
243     return Reg.RegNum;
244   }
245 
246   const MCExpr *getImm() const {
247     assert(Kind == Immediate && "Invalid access!");
248     return Imm.Val;
249   }
250 
251   bool isToken() const override { return Kind == Token; }
252   bool isImm() const override { return Kind == Immediate; }
253   bool isMem() const override { llvm_unreachable("No isMem"); }
254   bool isReg() const override { return Kind == Register; }
255 
256   bool CheckImmRange(int immBits, int zeroBits, bool isSigned,
257                      bool isRelocatable, bool Extendable) const {
258     if (Kind == Immediate) {
259       const MCExpr *myMCExpr = &HexagonMCInstrInfo::getExpr(*getImm());
260       if (HexagonMCInstrInfo::mustExtend(*Imm.Val) && !Extendable)
261         return false;
262       int64_t Res;
263       if (myMCExpr->evaluateAsAbsolute(Res)) {
264         int bits = immBits + zeroBits;
265         // Field bit range is zerobits + bits
266         // zeroBits must be 0
267         if (Res & ((1 << zeroBits) - 1))
268           return false;
269         if (isSigned) {
270           if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1)))
271             return true;
272         } else {
273           if (bits == 64)
274             return true;
275           if (Res >= 0)
276             return ((uint64_t)Res < (uint64_t)(1ULL << bits));
277           else {
278             const int64_t high_bit_set = 1ULL << 63;
279             const uint64_t mask = (high_bit_set >> (63 - bits));
280             return (((uint64_t)Res & mask) == mask);
281           }
282         }
283       } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable)
284         return true;
285       else if (myMCExpr->getKind() == MCExpr::Binary ||
286                myMCExpr->getKind() == MCExpr::Unary)
287         return true;
288     }
289     return false;
290   }
291 
292   bool isa30_2Imm() const { return CheckImmRange(30, 2, true, true, true); }
293   bool isb30_2Imm() const { return CheckImmRange(30, 2, true, true, true); }
294   bool isb15_2Imm() const { return CheckImmRange(15, 2, true, true, false); }
295   bool isb13_2Imm() const { return CheckImmRange(13, 2, true, true, false); }
296 
297   bool ism32_0Imm() const { return true; }
298 
299   bool isf32Imm() const { return false; }
300   bool isf64Imm() const { return false; }
301   bool iss32_0Imm() const { return true; }
302   bool iss31_1Imm() const { return true; }
303   bool iss30_2Imm() const { return true; }
304   bool iss29_3Imm() const { return true; }
305   bool iss27_2Imm() const { return CheckImmRange(27, 2, true, true, false); }
306   bool iss10_0Imm() const { return CheckImmRange(10, 0, true, false, false); }
307   bool iss10_6Imm() const { return CheckImmRange(10, 6, true, false, false); }
308   bool iss9_0Imm() const { return CheckImmRange(9, 0, true, false, false); }
309   bool iss8_0Imm() const { return CheckImmRange(8, 0, true, false, false); }
310   bool iss8_0Imm64() const { return CheckImmRange(8, 0, true, true, false); }
311   bool iss7_0Imm() const { return CheckImmRange(7, 0, true, false, false); }
312   bool iss6_0Imm() const { return CheckImmRange(6, 0, true, false, false); }
313   bool iss6_3Imm() const { return CheckImmRange(6, 3, true, false, false); }
314   bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); }
315   bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
316   bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
317   bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
318   bool iss3_0Imm() const { return CheckImmRange(3, 0, true, false, false); }
319 
320   bool isu64_0Imm() const { return CheckImmRange(64, 0, false, true, true); }
321   bool isu32_0Imm() const { return true; }
322   bool isu31_1Imm() const { return true; }
323   bool isu30_2Imm() const { return true; }
324   bool isu29_3Imm() const { return true; }
325   bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); }
326   bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); }
327   bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); }
328   bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); }
329   bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); }
330   bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); }
331   bool isu10_0Imm() const { return CheckImmRange(10, 0, false, false, false); }
332   bool isu9_0Imm() const { return CheckImmRange(9, 0, false, false, false); }
333   bool isu8_0Imm() const { return CheckImmRange(8, 0, false, false, false); }
334   bool isu7_0Imm() const { return CheckImmRange(7, 0, false, false, false); }
335   bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
336   bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); }
337   bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); }
338   bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); }
339   bool isu5_0Imm() const { return CheckImmRange(5, 0, false, false, false); }
340   bool isu5_2Imm() const { return CheckImmRange(5, 2, false, false, false); }
341   bool isu5_3Imm() const { return CheckImmRange(5, 3, false, false, false); }
342   bool isu4_0Imm() const { return CheckImmRange(4, 0, false, false, false); }
343   bool isu4_2Imm() const { return CheckImmRange(4, 2, false, false, false); }
344   bool isu3_0Imm() const { return CheckImmRange(3, 0, false, false, false); }
345   bool isu3_1Imm() const { return CheckImmRange(3, 1, false, false, false); }
346   bool isu2_0Imm() const { return CheckImmRange(2, 0, false, false, false); }
347   bool isu1_0Imm() const { return CheckImmRange(1, 0, false, false, false); }
348 
349   bool isn1Const() const {
350     if (!isImm())
351       return false;
352     int64_t Value;
353     if (!getImm()->evaluateAsAbsolute(Value))
354       return false;
355     return Value == -1;
356   }
357   bool issgp10Const() const {
358     if (!isReg())
359       return false;
360     return getReg() == Hexagon::SGP1_0;
361   }
362   bool iss11_0Imm() const {
363     return CheckImmRange(11 + 26, 0, true, true, true);
364   }
365   bool iss11_1Imm() const {
366     return CheckImmRange(11 + 26, 1, true, true, true);
367   }
368   bool iss11_2Imm() const {
369     return CheckImmRange(11 + 26, 2, true, true, true);
370   }
371   bool iss11_3Imm() const {
372     return CheckImmRange(11 + 26, 3, true, true, true);
373   }
374   bool isu32_0MustExt() const { return isImm(); }
375 
376   void addRegOperands(MCInst &Inst, unsigned N) const {
377     assert(N == 1 && "Invalid number of operands!");
378     Inst.addOperand(MCOperand::createReg(getReg()));
379   }
380 
381   void addImmOperands(MCInst &Inst, unsigned N) const {
382     assert(N == 1 && "Invalid number of operands!");
383     Inst.addOperand(MCOperand::createExpr(getImm()));
384   }
385 
386   void addSignedImmOperands(MCInst &Inst, unsigned N) const {
387     assert(N == 1 && "Invalid number of operands!");
388     HexagonMCExpr *Expr =
389         const_cast<HexagonMCExpr *>(cast<HexagonMCExpr>(getImm()));
390     int64_t Value;
391     if (!Expr->evaluateAsAbsolute(Value)) {
392       Inst.addOperand(MCOperand::createExpr(Expr));
393       return;
394     }
395     int64_t Extended = SignExtend64(Value, 32);
396     HexagonMCExpr *NewExpr = HexagonMCExpr::create(
397         MCConstantExpr::create(Extended, Context), Context);
398     if ((Extended < 0) != (Value < 0))
399       NewExpr->setSignMismatch();
400     NewExpr->setMustExtend(Expr->mustExtend());
401     NewExpr->setMustNotExtend(Expr->mustNotExtend());
402     Inst.addOperand(MCOperand::createExpr(NewExpr));
403   }
404 
405   void addn1ConstOperands(MCInst &Inst, unsigned N) const {
406     addImmOperands(Inst, N);
407   }
408   void addsgp10ConstOperands(MCInst &Inst, unsigned N) const {
409     addRegOperands(Inst, N);
410   }
411 
412   StringRef getToken() const {
413     assert(Kind == Token && "Invalid access!");
414     return StringRef(Tok.Data, Tok.Length);
415   }
416 
417   void print(raw_ostream &OS) const override;
418 
419   static std::unique_ptr<HexagonOperand> CreateToken(MCContext &Context,
420                                                      StringRef Str, SMLoc S) {
421     HexagonOperand *Op = new HexagonOperand(Token, Context);
422     Op->Tok.Data = Str.data();
423     Op->Tok.Length = Str.size();
424     Op->StartLoc = S;
425     Op->EndLoc = S;
426     return std::unique_ptr<HexagonOperand>(Op);
427   }
428 
429   static std::unique_ptr<HexagonOperand>
430   CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) {
431     HexagonOperand *Op = new HexagonOperand(Register, Context);
432     Op->Reg.RegNum = RegNum;
433     Op->StartLoc = S;
434     Op->EndLoc = E;
435     return std::unique_ptr<HexagonOperand>(Op);
436   }
437 
438   static std::unique_ptr<HexagonOperand>
439   CreateImm(MCContext &Context, const MCExpr *Val, SMLoc S, SMLoc E) {
440     HexagonOperand *Op = new HexagonOperand(Immediate, Context);
441     Op->Imm.Val = Val;
442     Op->StartLoc = S;
443     Op->EndLoc = E;
444     return std::unique_ptr<HexagonOperand>(Op);
445   }
446 };
447 
448 } // end anonymous namespace
449 
450 void HexagonOperand::print(raw_ostream &OS) const {
451   switch (Kind) {
452   case Immediate:
453     getImm()->print(OS, nullptr);
454     break;
455   case Register:
456     OS << "<register R";
457     OS << getReg() << ">";
458     break;
459   case Token:
460     OS << "'" << getToken() << "'";
461     break;
462   }
463 }
464 
465 bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
466   LLVM_DEBUG(dbgs() << "Bundle:");
467   LLVM_DEBUG(MCB.dump_pretty(dbgs()));
468   LLVM_DEBUG(dbgs() << "--\n");
469 
470   MCB.setLoc(IDLoc);
471 
472   // Check the bundle for errors.
473   const MCRegisterInfo *RI = getContext().getRegisterInfo();
474   MCSubtargetInfo const &STI = getSTI();
475 
476   MCInst OrigBundle = MCB;
477   HexagonMCChecker Check(getContext(), MII, STI, MCB, *RI, true);
478 
479   bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(
480       MII, STI, getContext(), MCB, &Check, true);
481 
482   if (CheckOk) {
483     if (HexagonMCInstrInfo::bundleSize(MCB) == 0) {
484       assert(!HexagonMCInstrInfo::isInnerLoop(MCB));
485       assert(!HexagonMCInstrInfo::isOuterLoop(MCB));
486       // Empty packets are valid yet aren't emitted
487       return false;
488     }
489 
490     assert(HexagonMCInstrInfo::isBundle(MCB));
491 
492     Out.emitInstruction(MCB, STI);
493   } else
494     return true; // Error
495 
496   return false; // No error
497 }
498 
499 bool HexagonAsmParser::matchBundleOptions() {
500   MCAsmParser &Parser = getParser();
501   while (true) {
502     if (!Parser.getTok().is(AsmToken::Colon))
503       return false;
504     Lex();
505     char const *MemNoShuffMsg =
506         "invalid instruction packet: mem_noshuf specifier not "
507         "supported with this architecture";
508     StringRef Option = Parser.getTok().getString();
509     auto IDLoc = Parser.getTok().getLoc();
510     if (Option.compare_insensitive("endloop01") == 0) {
511       HexagonMCInstrInfo::setInnerLoop(MCB);
512       HexagonMCInstrInfo::setOuterLoop(MCB);
513     } else if (Option.compare_insensitive("endloop0") == 0) {
514       HexagonMCInstrInfo::setInnerLoop(MCB);
515     } else if (Option.compare_insensitive("endloop1") == 0) {
516       HexagonMCInstrInfo::setOuterLoop(MCB);
517     } else if (Option.compare_insensitive("mem_noshuf") == 0) {
518       if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])
519         HexagonMCInstrInfo::setMemReorderDisabled(MCB);
520       else
521         return getParser().Error(IDLoc, MemNoShuffMsg);
522     } else if (Option.compare_insensitive("mem_no_order") == 0) {
523       // Nothing.
524     } else
525       return getParser().Error(IDLoc, llvm::Twine("'") + Option +
526                                           "' is not a valid bundle option");
527     Lex();
528   }
529 }
530 
531 // For instruction aliases, immediates are generated rather than
532 // MCConstantExpr.  Convert them for uniform MCExpr.
533 // Also check for signed/unsigned mismatches and warn
534 void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
535   MCInst NewInst;
536   NewInst.setOpcode(MCI.getOpcode());
537   for (MCOperand &I : MCI)
538     if (I.isImm()) {
539       int64_t Value(I.getImm());
540       NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
541           MCConstantExpr::create(Value, getContext()), getContext())));
542     } else {
543       if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() &&
544           WarnSignedMismatch)
545         Warning(MCI.getLoc(), "Signed/Unsigned mismatch");
546       NewInst.addOperand(I);
547     }
548   MCI = NewInst;
549 }
550 
551 bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
552                                            OperandVector &InstOperands,
553                                            uint64_t &ErrorInfo,
554                                            bool MatchingInlineAsm) {
555   // Perform matching with tablegen asmmatcher generated function
556   int result =
557       MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);
558   if (result == Match_Success) {
559     MCI.setLoc(IDLoc);
560     canonicalizeImmediates(MCI);
561     result = processInstruction(MCI, InstOperands, IDLoc);
562 
563     LLVM_DEBUG(dbgs() << "Insn:");
564     LLVM_DEBUG(MCI.dump_pretty(dbgs()));
565     LLVM_DEBUG(dbgs() << "\n\n");
566 
567     MCI.setLoc(IDLoc);
568   }
569 
570   // Create instruction operand for bundle instruction
571   //   Break this into a separate function Code here is less readable
572   //   Think about how to get an instruction error to report correctly.
573   //   SMLoc will return the "{"
574   switch (result) {
575   default:
576     break;
577   case Match_Success:
578     return false;
579   case Match_MissingFeature:
580     return Error(IDLoc, "invalid instruction");
581   case Match_MnemonicFail:
582     return Error(IDLoc, "unrecognized instruction");
583   case Match_InvalidOperand:
584     [[fallthrough]];
585   case Match_InvalidTiedOperand:
586     SMLoc ErrorLoc = IDLoc;
587     if (ErrorInfo != ~0U) {
588       if (ErrorInfo >= InstOperands.size())
589         return Error(IDLoc, "too few operands for instruction");
590 
591       ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get()))
592                      ->getStartLoc();
593       if (ErrorLoc == SMLoc())
594         ErrorLoc = IDLoc;
595     }
596     return Error(ErrorLoc, "invalid operand for instruction");
597   }
598   llvm_unreachable("Implement any new match types added!");
599 }
600 
601 void HexagonAsmParser::eatToEndOfPacket() {
602   assert(InBrackets);
603   MCAsmLexer &Lexer = getLexer();
604   while (!Lexer.is(AsmToken::RCurly))
605     Lexer.Lex();
606   Lexer.Lex();
607   InBrackets = false;
608 }
609 
610 bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
611                                                OperandVector &Operands,
612                                                MCStreamer &Out,
613                                                uint64_t &ErrorInfo,
614                                                bool MatchingInlineAsm) {
615   if (!InBrackets) {
616     MCB.clear();
617     MCB.addOperand(MCOperand::createImm(0));
618   }
619   HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]);
620   if (FirstOperand.isToken() && FirstOperand.getToken() == "{") {
621     assert(Operands.size() == 1 && "Brackets should be by themselves");
622     if (InBrackets) {
623       getParser().Error(IDLoc, "Already in a packet");
624       InBrackets = false;
625       return true;
626     }
627     InBrackets = true;
628     return false;
629   }
630   if (FirstOperand.isToken() && FirstOperand.getToken() == "}") {
631     assert(Operands.size() == 1 && "Brackets should be by themselves");
632     if (!InBrackets) {
633       getParser().Error(IDLoc, "Not in a packet");
634       return true;
635     }
636     InBrackets = false;
637     if (matchBundleOptions())
638       return true;
639     return finishBundle(IDLoc, Out);
640   }
641   MCInst *SubInst = getParser().getContext().createMCInst();
642   if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
643                           MatchingInlineAsm)) {
644     if (InBrackets)
645       eatToEndOfPacket();
646     return true;
647   }
648   HexagonMCInstrInfo::extendIfNeeded(
649       getParser().getContext(), MII, MCB, *SubInst);
650   MCB.addOperand(MCOperand::createInst(SubInst));
651   if (!InBrackets)
652     return finishBundle(IDLoc, Out);
653   return false;
654 }
655 
656 /// ParseDirective parses the Hexagon specific directives
657 bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
658   StringRef IDVal = DirectiveID.getIdentifier();
659   if (IDVal.lower() == ".falign")
660     return ParseDirectiveFalign(256, DirectiveID.getLoc());
661   if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon"))
662     return ParseDirectiveComm(true, DirectiveID.getLoc());
663   if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common"))
664     return ParseDirectiveComm(false, DirectiveID.getLoc());
665   if (IDVal.lower() == ".subsection")
666     return ParseDirectiveSubsection(DirectiveID.getLoc());
667 
668   return true;
669 }
670 bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) {
671   const MCExpr *Subsection = nullptr;
672   int64_t Res;
673 
674   assert((getLexer().isNot(AsmToken::EndOfStatement)) &&
675          "Invalid subsection directive");
676   getParser().parseExpression(Subsection);
677 
678   if (!Subsection->evaluateAsAbsolute(Res))
679     return Error(L, "Cannot evaluate subsection number");
680 
681   if (getLexer().isNot(AsmToken::EndOfStatement))
682     return TokError("unexpected token in directive");
683 
684   // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the
685   // negative subsections together and in the same order but at the opposite
686   // end of the section.  Only legacy hexagon-gcc created assembly code
687   // used negative subsections.
688   if ((Res < 0) && (Res > -8193))
689     Subsection = HexagonMCExpr::create(
690         MCConstantExpr::create(8192 + Res, getContext()), getContext());
691 
692   getStreamer().subSection(Subsection);
693   return false;
694 }
695 
696 ///  ::= .falign [expression]
697 bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) {
698 
699   int64_t MaxBytesToFill = 15;
700 
701   // if there is an argument
702   if (getLexer().isNot(AsmToken::EndOfStatement)) {
703     const MCExpr *Value;
704     SMLoc ExprLoc = L;
705 
706     // Make sure we have a number (false is returned if expression is a number)
707     if (!getParser().parseExpression(Value)) {
708       // Make sure this is a number that is in range
709       auto *MCE = cast<MCConstantExpr>(Value);
710       uint64_t IntValue = MCE->getValue();
711       if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue))
712         return Error(ExprLoc, "literal value out of range (256) for falign");
713       MaxBytesToFill = IntValue;
714       Lex();
715     } else {
716       return Error(ExprLoc, "not a valid expression for falign directive");
717     }
718   }
719 
720   getTargetStreamer().emitFAlign(16, MaxBytesToFill);
721   Lex();
722 
723   return false;
724 }
725 
726 // This is largely a copy of AsmParser's ParseDirectiveComm extended to
727 // accept a 3rd argument, AccessAlignment which indicates the smallest
728 // memory access made to the symbol, expressed in bytes.  If no
729 // AccessAlignment is specified it defaults to the Alignment Value.
730 // Hexagon's .lcomm:
731 //   .lcomm Symbol, Length, Alignment, AccessAlignment
732 bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
733   // FIXME: need better way to detect if AsmStreamer (upstream removed
734   // getKind())
735   if (getStreamer().hasRawTextSupport())
736     return true; // Only object file output requires special treatment.
737 
738   StringRef Name;
739   if (getParser().parseIdentifier(Name))
740     return TokError("expected identifier in directive");
741   // Handle the identifier as the key symbol.
742   MCSymbol *Sym = getContext().getOrCreateSymbol(Name);
743 
744   if (getLexer().isNot(AsmToken::Comma))
745     return TokError("unexpected token in directive");
746   Lex();
747 
748   int64_t Size;
749   SMLoc SizeLoc = getLexer().getLoc();
750   if (getParser().parseAbsoluteExpression(Size))
751     return true;
752 
753   int64_t ByteAlignment = 1;
754   SMLoc ByteAlignmentLoc;
755   if (getLexer().is(AsmToken::Comma)) {
756     Lex();
757     ByteAlignmentLoc = getLexer().getLoc();
758     if (getParser().parseAbsoluteExpression(ByteAlignment))
759       return true;
760     if (!isPowerOf2_64(ByteAlignment))
761       return Error(ByteAlignmentLoc, "alignment must be a power of 2");
762   }
763 
764   int64_t AccessAlignment = 0;
765   if (getLexer().is(AsmToken::Comma)) {
766     // The optional access argument specifies the size of the smallest memory
767     //   access to be made to the symbol, expressed in bytes.
768     SMLoc AccessAlignmentLoc;
769     Lex();
770     AccessAlignmentLoc = getLexer().getLoc();
771     if (getParser().parseAbsoluteExpression(AccessAlignment))
772       return true;
773 
774     if (!isPowerOf2_64(AccessAlignment))
775       return Error(AccessAlignmentLoc, "access alignment must be a power of 2");
776   }
777 
778   if (getLexer().isNot(AsmToken::EndOfStatement))
779     return TokError("unexpected token in '.comm' or '.lcomm' directive");
780 
781   Lex();
782 
783   // NOTE: a size of zero for a .comm should create a undefined symbol
784   // but a size of .lcomm creates a bss symbol of size zero.
785   if (Size < 0)
786     return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't "
787                           "be less than zero");
788 
789   // NOTE: The alignment in the directive is a power of 2 value, the assembler
790   // may internally end up wanting an alignment in bytes.
791   // FIXME: Diagnose overflow.
792   if (ByteAlignment < 0)
793     return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive "
794                                    "alignment, can't be less than zero");
795 
796   if (!Sym->isUndefined())
797     return Error(Loc, "invalid symbol redefinition");
798 
799   HexagonMCELFStreamer &HexagonELFStreamer =
800       static_cast<HexagonMCELFStreamer &>(getStreamer());
801   if (IsLocal) {
802     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment,
803                                                       AccessAlignment);
804     return false;
805   }
806 
807   HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment,
808                                                AccessAlignment);
809   return false;
810 }
811 
812 // validate register against architecture
813 bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
814   if (HexagonMCRegisterClasses[Hexagon::V62RegsRegClassID].contains(MatchNum))
815     if (!getSTI().getFeatureBits()[Hexagon::ArchV62])
816       return false;
817   return true;
818 }
819 
820 // extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonAsmLexer();
821 
822 /// Force static initialization.
823 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonAsmParser() {
824   RegisterMCAsmParser<HexagonAsmParser> X(getTheHexagonTarget());
825 }
826 
827 #define GET_MATCHER_IMPLEMENTATION
828 #define GET_REGISTER_MATCHER
829 #include "HexagonGenAsmMatcher.inc"
830 
831 static bool previousEqual(OperandVector &Operands, size_t Index,
832                           StringRef String) {
833   if (Index >= Operands.size())
834     return false;
835   MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1];
836   if (!Operand.isToken())
837     return false;
838   return static_cast<HexagonOperand &>(Operand).getToken().equals_insensitive(
839       String);
840 }
841 
842 static bool previousIsLoop(OperandVector &Operands, size_t Index) {
843   return previousEqual(Operands, Index, "loop0") ||
844          previousEqual(Operands, Index, "loop1") ||
845          previousEqual(Operands, Index, "sp1loop0") ||
846          previousEqual(Operands, Index, "sp2loop0") ||
847          previousEqual(Operands, Index, "sp3loop0");
848 }
849 
850 bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {
851   AsmToken const &Token = getParser().getTok();
852   StringRef String = Token.getString();
853   SMLoc Loc = Token.getLoc();
854   Lex();
855   do {
856     std::pair<StringRef, StringRef> HeadTail = String.split('.');
857     if (!HeadTail.first.empty())
858       Operands.push_back(
859           HexagonOperand::CreateToken(getContext(), HeadTail.first, Loc));
860     if (!HeadTail.second.empty())
861       Operands.push_back(HexagonOperand::CreateToken(
862           getContext(), String.substr(HeadTail.first.size(), 1), Loc));
863     String = HeadTail.second;
864   } while (!String.empty());
865   return false;
866 }
867 
868 bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
869   unsigned Register;
870   SMLoc Begin;
871   SMLoc End;
872   MCAsmLexer &Lexer = getLexer();
873   if (!ParseRegister(Register, Begin, End)) {
874     if (!ErrorMissingParenthesis)
875       switch (Register) {
876       default:
877         break;
878       case Hexagon::P0:
879       case Hexagon::P1:
880       case Hexagon::P2:
881       case Hexagon::P3:
882         if (previousEqual(Operands, 0, "if")) {
883           if (WarnMissingParenthesis)
884             Warning(Begin, "Missing parenthesis around predicate register");
885           static char const *LParen = "(";
886           static char const *RParen = ")";
887           Operands.push_back(
888               HexagonOperand::CreateToken(getContext(), LParen, Begin));
889           Operands.push_back(
890               HexagonOperand::CreateReg(getContext(), Register, Begin, End));
891           const AsmToken &MaybeDotNew = Lexer.getTok();
892           if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
893               MaybeDotNew.getString().equals_insensitive(".new"))
894             splitIdentifier(Operands);
895           Operands.push_back(
896               HexagonOperand::CreateToken(getContext(), RParen, Begin));
897           return false;
898         }
899         if (previousEqual(Operands, 0, "!") &&
900             previousEqual(Operands, 1, "if")) {
901           if (WarnMissingParenthesis)
902             Warning(Begin, "Missing parenthesis around predicate register");
903           static char const *LParen = "(";
904           static char const *RParen = ")";
905           Operands.insert(Operands.end() - 1, HexagonOperand::CreateToken(
906                                                   getContext(), LParen, Begin));
907           Operands.push_back(
908               HexagonOperand::CreateReg(getContext(), Register, Begin, End));
909           const AsmToken &MaybeDotNew = Lexer.getTok();
910           if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
911               MaybeDotNew.getString().equals_insensitive(".new"))
912             splitIdentifier(Operands);
913           Operands.push_back(
914               HexagonOperand::CreateToken(getContext(), RParen, Begin));
915           return false;
916         }
917         break;
918       }
919     Operands.push_back(
920         HexagonOperand::CreateReg(getContext(), Register, Begin, End));
921     return false;
922   }
923   return splitIdentifier(Operands);
924 }
925 
926 bool HexagonAsmParser::isLabel(AsmToken &Token) {
927   MCAsmLexer &Lexer = getLexer();
928   AsmToken const &Second = Lexer.getTok();
929   AsmToken Third = Lexer.peekTok();
930   StringRef String = Token.getString();
931   if (Token.is(AsmToken::TokenKind::LCurly) ||
932       Token.is(AsmToken::TokenKind::RCurly))
933     return false;
934   // special case for parsing vwhist256:sat
935   if (String.lower() == "vwhist256" && Second.is(AsmToken::Colon) &&
936       Third.getString().lower() == "sat")
937     return false;
938   if (!Token.is(AsmToken::TokenKind::Identifier))
939     return true;
940   if (!matchRegister(String.lower()))
941     return true;
942   assert(Second.is(AsmToken::Colon));
943   StringRef Raw(String.data(), Third.getString().data() - String.data() +
944                                    Third.getString().size());
945   std::string Collapsed = std::string(Raw);
946   llvm::erase_if(Collapsed, isSpace);
947   StringRef Whole = Collapsed;
948   std::pair<StringRef, StringRef> DotSplit = Whole.split('.');
949   if (!matchRegister(DotSplit.first.lower()))
950     return true;
951   return false;
952 }
953 
954 bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious,
955                                                    SMLoc &Loc) {
956   if (!Contigious && ErrorNoncontigiousRegister) {
957     Error(Loc, "Register name is not contigious");
958     return true;
959   }
960   if (!Contigious && WarnNoncontigiousRegister)
961     Warning(Loc, "Register name is not contigious");
962   return false;
963 }
964 
965 bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
966                                      SMLoc &EndLoc) {
967   return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success;
968 }
969 
970 OperandMatchResultTy HexagonAsmParser::tryParseRegister(unsigned &RegNo,
971                                                         SMLoc &StartLoc,
972                                                         SMLoc &EndLoc) {
973   MCAsmLexer &Lexer = getLexer();
974   StartLoc = getLexer().getLoc();
975   SmallVector<AsmToken, 5> Lookahead;
976   StringRef RawString(Lexer.getTok().getString().data(), 0);
977   bool Again = Lexer.is(AsmToken::Identifier);
978   bool NeededWorkaround = false;
979   while (Again) {
980     AsmToken const &Token = Lexer.getTok();
981     RawString = StringRef(RawString.data(), Token.getString().data() -
982                                                 RawString.data() +
983                                                 Token.getString().size());
984     Lookahead.push_back(Token);
985     Lexer.Lex();
986     bool Contigious = Lexer.getTok().getString().data() ==
987                       Lookahead.back().getString().data() +
988                           Lookahead.back().getString().size();
989     bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||
990                 Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
991                 Lexer.is(AsmToken::Colon);
992     bool Workaround =
993         Lexer.is(AsmToken::Colon) || Lookahead.back().is(AsmToken::Colon);
994     Again = (Contigious && Type) || (Workaround && Type);
995     NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));
996   }
997   std::string Collapsed = std::string(RawString);
998   llvm::erase_if(Collapsed, isSpace);
999   StringRef FullString = Collapsed;
1000   std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
1001   unsigned DotReg = matchRegister(DotSplit.first.lower());
1002   if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1003     if (DotSplit.second.empty()) {
1004       RegNo = DotReg;
1005       EndLoc = Lexer.getLoc();
1006       if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1007         return MatchOperand_NoMatch;
1008       return MatchOperand_Success;
1009     } else {
1010       RegNo = DotReg;
1011       size_t First = RawString.find('.');
1012       StringRef DotString (RawString.data() + First, RawString.size() - First);
1013       Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString));
1014       EndLoc = Lexer.getLoc();
1015       if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1016         return MatchOperand_NoMatch;
1017       return MatchOperand_Success;
1018     }
1019   }
1020   std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
1021   unsigned ColonReg = matchRegister(ColonSplit.first.lower());
1022   if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1023     do {
1024       Lexer.UnLex(Lookahead.pop_back_val());
1025     } while (!Lookahead.empty() && !Lexer.is(AsmToken::Colon));
1026     RegNo = ColonReg;
1027     EndLoc = Lexer.getLoc();
1028     if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1029       return MatchOperand_NoMatch;
1030     return MatchOperand_Success;
1031   }
1032   while (!Lookahead.empty()) {
1033     Lexer.UnLex(Lookahead.pop_back_val());
1034   }
1035   return MatchOperand_NoMatch;
1036 }
1037 
1038 bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) {
1039   if (previousEqual(Operands, 0, "call"))
1040     return true;
1041   if (previousEqual(Operands, 0, "jump"))
1042     if (!getLexer().getTok().is(AsmToken::Colon))
1043       return true;
1044   if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1))
1045     return true;
1046   if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") &&
1047       (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t")))
1048     return true;
1049   return false;
1050 }
1051 
1052 bool HexagonAsmParser::parseExpression(MCExpr const *&Expr) {
1053   SmallVector<AsmToken, 4> Tokens;
1054   MCAsmLexer &Lexer = getLexer();
1055   bool Done = false;
1056   static char const *Comma = ",";
1057   do {
1058     Tokens.emplace_back(Lexer.getTok());
1059     Lex();
1060     switch (Tokens.back().getKind()) {
1061     case AsmToken::TokenKind::Hash:
1062       if (Tokens.size() > 1)
1063         if ((Tokens.end() - 2)->getKind() == AsmToken::TokenKind::Plus) {
1064           Tokens.insert(Tokens.end() - 2,
1065                         AsmToken(AsmToken::TokenKind::Comma, Comma));
1066           Done = true;
1067         }
1068       break;
1069     case AsmToken::TokenKind::RCurly:
1070     case AsmToken::TokenKind::EndOfStatement:
1071     case AsmToken::TokenKind::Eof:
1072       Done = true;
1073       break;
1074     default:
1075       break;
1076     }
1077   } while (!Done);
1078   while (!Tokens.empty()) {
1079     Lexer.UnLex(Tokens.back());
1080     Tokens.pop_back();
1081   }
1082   SMLoc Loc = Lexer.getLoc();
1083   return getParser().parseExpression(Expr, Loc);
1084 }
1085 
1086 bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
1087   if (implicitExpressionLocation(Operands)) {
1088     MCAsmParser &Parser = getParser();
1089     SMLoc Loc = Parser.getLexer().getLoc();
1090     MCExpr const *Expr = nullptr;
1091     bool Error = parseExpression(Expr);
1092     Expr = HexagonMCExpr::create(Expr, getContext());
1093     if (!Error)
1094       Operands.push_back(
1095           HexagonOperand::CreateImm(getContext(), Expr, Loc, Loc));
1096     return Error;
1097   }
1098   return parseOperand(Operands);
1099 }
1100 
1101 /// Parse an instruction.
1102 bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
1103   MCAsmParser &Parser = getParser();
1104   MCAsmLexer &Lexer = getLexer();
1105   while (true) {
1106     AsmToken const &Token = Parser.getTok();
1107     switch (Token.getKind()) {
1108     case AsmToken::Eof:
1109     case AsmToken::EndOfStatement: {
1110       Lex();
1111       return false;
1112     }
1113     case AsmToken::LCurly: {
1114       if (!Operands.empty())
1115         return true;
1116       Operands.push_back(HexagonOperand::CreateToken(
1117           getContext(), Token.getString(), Token.getLoc()));
1118       Lex();
1119       return false;
1120     }
1121     case AsmToken::RCurly: {
1122       if (Operands.empty()) {
1123         Operands.push_back(HexagonOperand::CreateToken(
1124             getContext(), Token.getString(), Token.getLoc()));
1125         Lex();
1126       }
1127       return false;
1128     }
1129     case AsmToken::Comma: {
1130       Lex();
1131       continue;
1132     }
1133     case AsmToken::EqualEqual:
1134     case AsmToken::ExclaimEqual:
1135     case AsmToken::GreaterEqual:
1136     case AsmToken::GreaterGreater:
1137     case AsmToken::LessEqual:
1138     case AsmToken::LessLess: {
1139       Operands.push_back(HexagonOperand::CreateToken(
1140           getContext(), Token.getString().substr(0, 1), Token.getLoc()));
1141       Operands.push_back(HexagonOperand::CreateToken(
1142           getContext(), Token.getString().substr(1, 1), Token.getLoc()));
1143       Lex();
1144       continue;
1145     }
1146     case AsmToken::Hash: {
1147       bool MustNotExtend = false;
1148       bool ImplicitExpression = implicitExpressionLocation(Operands);
1149       SMLoc ExprLoc = Lexer.getLoc();
1150       if (!ImplicitExpression)
1151         Operands.push_back(HexagonOperand::CreateToken(
1152             getContext(), Token.getString(), Token.getLoc()));
1153       Lex();
1154       bool MustExtend = false;
1155       bool HiOnly = false;
1156       bool LoOnly = false;
1157       if (Lexer.is(AsmToken::Hash)) {
1158         Lex();
1159         MustExtend = true;
1160       } else if (ImplicitExpression)
1161         MustNotExtend = true;
1162       AsmToken const &Token = Parser.getTok();
1163       if (Token.is(AsmToken::Identifier)) {
1164         StringRef String = Token.getString();
1165         if (String.lower() == "hi") {
1166           HiOnly = true;
1167         } else if (String.lower() == "lo") {
1168           LoOnly = true;
1169         }
1170         if (HiOnly || LoOnly) {
1171           AsmToken LParen = Lexer.peekTok();
1172           if (!LParen.is(AsmToken::LParen)) {
1173             HiOnly = false;
1174             LoOnly = false;
1175           } else {
1176             Lex();
1177           }
1178         }
1179       }
1180       MCExpr const *Expr = nullptr;
1181       if (parseExpression(Expr))
1182         return true;
1183       int64_t Value;
1184       MCContext &Context = Parser.getContext();
1185       assert(Expr != nullptr);
1186       if (Expr->evaluateAsAbsolute(Value)) {
1187         if (HiOnly)
1188           Expr = MCBinaryExpr::createLShr(
1189               Expr, MCConstantExpr::create(16, Context), Context);
1190         if (HiOnly || LoOnly)
1191           Expr = MCBinaryExpr::createAnd(
1192               Expr, MCConstantExpr::create(0xffff, Context), Context);
1193       } else {
1194         MCValue Value;
1195         if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) {
1196           if (!Value.isAbsolute()) {
1197             switch (Value.getAccessVariant()) {
1198             case MCSymbolRefExpr::VariantKind::VK_TPREL:
1199             case MCSymbolRefExpr::VariantKind::VK_DTPREL:
1200               // Don't lazy extend these expression variants
1201               MustNotExtend = !MustExtend;
1202               break;
1203             default:
1204               break;
1205             }
1206           }
1207         }
1208       }
1209       Expr = HexagonMCExpr::create(Expr, Context);
1210       HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);
1211       HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
1212       std::unique_ptr<HexagonOperand> Operand =
1213           HexagonOperand::CreateImm(getContext(), Expr, ExprLoc, ExprLoc);
1214       Operands.push_back(std::move(Operand));
1215       continue;
1216     }
1217     default:
1218       break;
1219     }
1220     if (parseExpressionOrOperand(Operands))
1221       return true;
1222   }
1223 }
1224 
1225 bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1226                                         StringRef Name, AsmToken ID,
1227                                         OperandVector &Operands) {
1228   getLexer().UnLex(ID);
1229   return parseInstruction(Operands);
1230 }
1231 
1232 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1,
1233                               MCOperand &MO2) {
1234   MCInst TmpInst;
1235   TmpInst.setOpcode(opCode);
1236   TmpInst.addOperand(Rdd);
1237   TmpInst.addOperand(MO1);
1238   TmpInst.addOperand(MO2);
1239 
1240   return TmpInst;
1241 }
1242 
1243 // Define this matcher function after the auto-generated include so we
1244 // have the match class enum definitions.
1245 unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1246                                                       unsigned Kind) {
1247   HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp);
1248 
1249   switch (Kind) {
1250   case MCK_0: {
1251     int64_t Value;
1252     return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0
1253                ? Match_Success
1254                : Match_InvalidOperand;
1255   }
1256   case MCK_1: {
1257     int64_t Value;
1258     return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1
1259                ? Match_Success
1260                : Match_InvalidOperand;
1261   }
1262   }
1263   if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) {
1264     StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length);
1265     if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind)
1266       return Match_Success;
1267     if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind)
1268       return Match_Success;
1269   }
1270 
1271   LLVM_DEBUG(dbgs() << "Unmatched Operand:");
1272   LLVM_DEBUG(Op->dump());
1273   LLVM_DEBUG(dbgs() << "\n");
1274 
1275   return Match_InvalidOperand;
1276 }
1277 
1278 // FIXME: Calls to OutOfRange shoudl propagate failure up to parseStatement.
1279 bool HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
1280   std::string errStr;
1281   raw_string_ostream ES(errStr);
1282   ES << "value " << Val << "(" << format_hex(Val, 0) << ") out of range: ";
1283   if (Max >= 0)
1284     ES << "0-" << Max;
1285   else
1286     ES << Max << "-" << (-Max - 1);
1287   return Parser.printError(IDLoc, ES.str());
1288 }
1289 
1290 int HexagonAsmParser::processInstruction(MCInst &Inst,
1291                                          OperandVector const &Operands,
1292                                          SMLoc IDLoc) {
1293   MCContext &Context = getParser().getContext();
1294   const MCRegisterInfo *RI = getContext().getRegisterInfo();
1295   const std::string r = "r";
1296   const std::string v = "v";
1297   const std::string Colon = ":";
1298   using RegPairVals = std::pair<unsigned, unsigned>;
1299   auto GetRegPair = [this, r](RegPairVals RegPair) {
1300     const std::string R1 = r + utostr(RegPair.first);
1301     const std::string R2 = r + utostr(RegPair.second);
1302 
1303     return std::make_pair(matchRegister(R1), matchRegister(R2));
1304   };
1305   auto GetScalarRegs = [RI, GetRegPair](unsigned RegPair) {
1306     const unsigned Lower = RI->getEncodingValue(RegPair);
1307     const RegPairVals RegPair_ = std::make_pair(Lower + 1, Lower);
1308 
1309     return GetRegPair(RegPair_);
1310   };
1311   auto GetVecRegs = [GetRegPair](unsigned VecRegPair) {
1312     const RegPairVals RegPair =
1313         HexagonMCInstrInfo::GetVecRegPairIndices(VecRegPair);
1314 
1315     return GetRegPair(RegPair);
1316   };
1317 
1318   bool is32bit = false; // used to distinguish between CONST32 and CONST64
1319   switch (Inst.getOpcode()) {
1320   default:
1321     if (HexagonMCInstrInfo::getDesc(MII, Inst).isPseudo()) {
1322       SMDiagnostic Diag = getSourceManager().GetMessage(
1323           IDLoc, SourceMgr::DK_Error,
1324           "Found pseudo instruction with no expansion");
1325       Diag.print("", errs());
1326       report_fatal_error("Invalid pseudo instruction");
1327     }
1328     break;
1329 
1330   case Hexagon::J2_trap1:
1331     if (!getSTI().getFeatureBits()[Hexagon::ArchV65]) {
1332       MCOperand &Rx = Inst.getOperand(0);
1333       MCOperand &Ry = Inst.getOperand(1);
1334       if (Rx.getReg() != Hexagon::R0 || Ry.getReg() != Hexagon::R0) {
1335         Error(IDLoc, "trap1 can only have register r0 as operand");
1336         return Match_InvalidOperand;
1337       }
1338     }
1339     break;
1340 
1341   case Hexagon::A2_iconst: {
1342     Inst.setOpcode(Hexagon::A2_addi);
1343     MCOperand Reg = Inst.getOperand(0);
1344     MCOperand S27 = Inst.getOperand(1);
1345     HexagonMCInstrInfo::setMustNotExtend(*S27.getExpr());
1346     HexagonMCInstrInfo::setS27_2_reloc(*S27.getExpr());
1347     Inst.clear();
1348     Inst.addOperand(Reg);
1349     Inst.addOperand(MCOperand::createReg(Hexagon::R0));
1350     Inst.addOperand(S27);
1351     break;
1352   }
1353   case Hexagon::M4_mpyrr_addr:
1354   case Hexagon::S4_addi_asl_ri:
1355   case Hexagon::S4_addi_lsr_ri:
1356   case Hexagon::S4_andi_asl_ri:
1357   case Hexagon::S4_andi_lsr_ri:
1358   case Hexagon::S4_ori_asl_ri:
1359   case Hexagon::S4_ori_lsr_ri:
1360   case Hexagon::S4_or_andix:
1361   case Hexagon::S4_subi_asl_ri:
1362   case Hexagon::S4_subi_lsr_ri: {
1363     MCOperand &Ry = Inst.getOperand(0);
1364     MCOperand &src = Inst.getOperand(2);
1365     if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg()))
1366       return Match_InvalidOperand;
1367     break;
1368   }
1369 
1370   case Hexagon::C2_cmpgei: {
1371     MCOperand &MO = Inst.getOperand(2);
1372     MO.setExpr(HexagonMCExpr::create(
1373         MCBinaryExpr::createSub(MO.getExpr(),
1374                                 MCConstantExpr::create(1, Context), Context),
1375         Context));
1376     Inst.setOpcode(Hexagon::C2_cmpgti);
1377     break;
1378   }
1379 
1380   case Hexagon::C2_cmpgeui: {
1381     MCOperand &MO = Inst.getOperand(2);
1382     int64_t Value;
1383     bool Success = MO.getExpr()->evaluateAsAbsolute(Value);
1384     (void)Success;
1385     assert(Success && "Assured by matcher");
1386     if (Value == 0) {
1387       MCInst TmpInst;
1388       MCOperand &Pd = Inst.getOperand(0);
1389       MCOperand &Rt = Inst.getOperand(1);
1390       TmpInst.setOpcode(Hexagon::C2_cmpeq);
1391       TmpInst.addOperand(Pd);
1392       TmpInst.addOperand(Rt);
1393       TmpInst.addOperand(Rt);
1394       Inst = TmpInst;
1395     } else {
1396       MO.setExpr(HexagonMCExpr::create(
1397           MCBinaryExpr::createSub(MO.getExpr(),
1398                                   MCConstantExpr::create(1, Context), Context),
1399           Context));
1400       Inst.setOpcode(Hexagon::C2_cmpgtui);
1401     }
1402     break;
1403   }
1404 
1405   // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1406   case Hexagon::A2_tfrp: {
1407     MCOperand &MO = Inst.getOperand(1);
1408     const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg());
1409     MO.setReg(RegPair.first);
1410     Inst.addOperand(MCOperand::createReg(RegPair.second));
1411     Inst.setOpcode(Hexagon::A2_combinew);
1412     break;
1413   }
1414 
1415   case Hexagon::A2_tfrpt:
1416   case Hexagon::A2_tfrpf: {
1417     MCOperand &MO = Inst.getOperand(2);
1418     const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg());
1419     MO.setReg(RegPair.first);
1420     Inst.addOperand(MCOperand::createReg(RegPair.second));
1421     Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
1422                        ? Hexagon::C2_ccombinewt
1423                        : Hexagon::C2_ccombinewf);
1424     break;
1425   }
1426   case Hexagon::A2_tfrptnew:
1427   case Hexagon::A2_tfrpfnew: {
1428     MCOperand &MO = Inst.getOperand(2);
1429     const std::pair<unsigned, unsigned> RegPair = GetScalarRegs(MO.getReg());
1430     MO.setReg(RegPair.first);
1431     Inst.addOperand(MCOperand::createReg(RegPair.second));
1432     Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
1433                        ? Hexagon::C2_ccombinewnewt
1434                        : Hexagon::C2_ccombinewnewf);
1435     break;
1436   }
1437 
1438   // Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)"
1439   case Hexagon::V6_vassignp: {
1440     MCOperand &MO = Inst.getOperand(1);
1441     const std::pair<unsigned, unsigned> RegPair = GetVecRegs(MO.getReg());
1442     MO.setReg(RegPair.first);
1443     Inst.addOperand(MCOperand::createReg(RegPair.second));
1444     Inst.setOpcode(Hexagon::V6_vcombine);
1445     break;
1446   }
1447 
1448   // Translate a "$Rx =  CONST32(#imm)" to "$Rx = memw(gp+#LABEL) "
1449   case Hexagon::CONST32:
1450     is32bit = true;
1451     [[fallthrough]];
1452   // Translate a "$Rx:y =  CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "
1453   case Hexagon::CONST64:
1454     // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
1455     if (!Parser.getStreamer().hasRawTextSupport()) {
1456       MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
1457       MCOperand &MO_1 = Inst.getOperand(1);
1458       MCOperand &MO_0 = Inst.getOperand(0);
1459 
1460       // push section onto section stack
1461       MES->pushSection();
1462 
1463       std::string myCharStr;
1464       MCSectionELF *mySection;
1465 
1466       // check if this as an immediate or a symbol
1467       int64_t Value;
1468       bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value);
1469       if (Absolute) {
1470         // Create a new section - one for each constant
1471         // Some or all of the zeros are replaced with the given immediate.
1472         if (is32bit) {
1473           std::string myImmStr = utohexstr(static_cast<uint32_t>(Value));
1474           myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000")
1475                           .drop_back(myImmStr.size())
1476                           .str() +
1477                       myImmStr;
1478         } else {
1479           std::string myImmStr = utohexstr(Value);
1480           myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000")
1481                           .drop_back(myImmStr.size())
1482                           .str() +
1483                       myImmStr;
1484         }
1485 
1486         mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1487                                                ELF::SHF_ALLOC | ELF::SHF_WRITE);
1488       } else if (MO_1.isExpr()) {
1489         // .lita - for expressions
1490         myCharStr = ".lita";
1491         mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1492                                                ELF::SHF_ALLOC | ELF::SHF_WRITE);
1493       } else
1494         llvm_unreachable("unexpected type of machine operand!");
1495 
1496       MES->switchSection(mySection);
1497       unsigned byteSize = is32bit ? 4 : 8;
1498       getStreamer().emitCodeAlignment(byteSize, &getSTI(), byteSize);
1499 
1500       MCSymbol *Sym;
1501 
1502       // for symbols, get rid of prepended ".gnu.linkonce.lx."
1503 
1504       // emit symbol if needed
1505       if (Absolute) {
1506         Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16));
1507         if (Sym->isUndefined()) {
1508           getStreamer().emitLabel(Sym);
1509           getStreamer().emitSymbolAttribute(Sym, MCSA_Global);
1510           getStreamer().emitIntValue(Value, byteSize);
1511         }
1512       } else if (MO_1.isExpr()) {
1513         const char *StringStart = nullptr;
1514         const char *StringEnd = nullptr;
1515         if (*Operands[4]->getStartLoc().getPointer() == '#') {
1516           StringStart = Operands[5]->getStartLoc().getPointer();
1517           StringEnd = Operands[6]->getStartLoc().getPointer();
1518         } else { // no pound
1519           StringStart = Operands[4]->getStartLoc().getPointer();
1520           StringEnd = Operands[5]->getStartLoc().getPointer();
1521         }
1522 
1523         unsigned size = StringEnd - StringStart;
1524         std::string DotConst = ".CONST_";
1525         Sym = getContext().getOrCreateSymbol(DotConst +
1526                                              StringRef(StringStart, size));
1527 
1528         if (Sym->isUndefined()) {
1529           // case where symbol is not yet defined: emit symbol
1530           getStreamer().emitLabel(Sym);
1531           getStreamer().emitSymbolAttribute(Sym, MCSA_Local);
1532           getStreamer().emitValue(MO_1.getExpr(), 4);
1533         }
1534       } else
1535         llvm_unreachable("unexpected type of machine operand!");
1536 
1537       MES->popSection();
1538 
1539       if (Sym) {
1540         MCInst TmpInst;
1541         if (is32bit) // 32 bit
1542           TmpInst.setOpcode(Hexagon::L2_loadrigp);
1543         else // 64 bit
1544           TmpInst.setOpcode(Hexagon::L2_loadrdgp);
1545 
1546         TmpInst.addOperand(MO_0);
1547         TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
1548             MCSymbolRefExpr::create(Sym, getContext()), getContext())));
1549         Inst = TmpInst;
1550       }
1551     }
1552     break;
1553 
1554   // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)"
1555   case Hexagon::A2_tfrpi: {
1556     MCOperand &Rdd = Inst.getOperand(0);
1557     MCOperand &MO = Inst.getOperand(1);
1558     int64_t Value;
1559     int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0;
1560     MCOperand imm(MCOperand::createExpr(
1561         HexagonMCExpr::create(MCConstantExpr::create(sVal, Context), Context)));
1562     Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO);
1563     break;
1564   }
1565 
1566   // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)"
1567   case Hexagon::TFRI64_V4: {
1568     MCOperand &Rdd = Inst.getOperand(0);
1569     MCOperand &MO = Inst.getOperand(1);
1570     int64_t Value;
1571     if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1572       int s8 = Hi_32(Value);
1573       if (!isInt<8>(s8))
1574         OutOfRange(IDLoc, s8, -128);
1575       MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1576           MCConstantExpr::create(s8, Context), Context))); // upper 32
1577       auto Expr = HexagonMCExpr::create(
1578           MCConstantExpr::create(Lo_32(Value), Context), Context);
1579       HexagonMCInstrInfo::setMustExtend(
1580           *Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
1581       MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
1582       Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
1583     } else {
1584       MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1585           MCConstantExpr::create(0, Context), Context))); // upper 32
1586       Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO);
1587     }
1588     break;
1589   }
1590 
1591   // Handle $Rdd = combine(##imm, #imm)"
1592   case Hexagon::TFRI64_V2_ext: {
1593     MCOperand &Rdd = Inst.getOperand(0);
1594     MCOperand &MO1 = Inst.getOperand(1);
1595     MCOperand &MO2 = Inst.getOperand(2);
1596     int64_t Value;
1597     if (MO2.getExpr()->evaluateAsAbsolute(Value)) {
1598       int s8 = Value;
1599       if (s8 < -128 || s8 > 127)
1600         OutOfRange(IDLoc, s8, -128);
1601     }
1602     Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);
1603     break;
1604   }
1605 
1606   // Handle $Rdd = combine(#imm, ##imm)"
1607   case Hexagon::A4_combineii: {
1608     MCOperand &Rdd = Inst.getOperand(0);
1609     MCOperand &MO1 = Inst.getOperand(1);
1610     int64_t Value;
1611     if (MO1.getExpr()->evaluateAsAbsolute(Value)) {
1612       int s8 = Value;
1613       if (s8 < -128 || s8 > 127)
1614         OutOfRange(IDLoc, s8, -128);
1615     }
1616     MCOperand &MO2 = Inst.getOperand(2);
1617     Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);
1618     break;
1619   }
1620 
1621   case Hexagon::S2_tableidxb_goodsyntax:
1622     Inst.setOpcode(Hexagon::S2_tableidxb);
1623     break;
1624 
1625   case Hexagon::S2_tableidxh_goodsyntax: {
1626     MCInst TmpInst;
1627     MCOperand &Rx = Inst.getOperand(0);
1628     MCOperand &Rs = Inst.getOperand(2);
1629     MCOperand &Imm4 = Inst.getOperand(3);
1630     MCOperand &Imm6 = Inst.getOperand(4);
1631     Imm6.setExpr(HexagonMCExpr::create(
1632         MCBinaryExpr::createSub(Imm6.getExpr(),
1633                                 MCConstantExpr::create(1, Context), Context),
1634         Context));
1635     TmpInst.setOpcode(Hexagon::S2_tableidxh);
1636     TmpInst.addOperand(Rx);
1637     TmpInst.addOperand(Rx);
1638     TmpInst.addOperand(Rs);
1639     TmpInst.addOperand(Imm4);
1640     TmpInst.addOperand(Imm6);
1641     Inst = TmpInst;
1642     break;
1643   }
1644 
1645   case Hexagon::S2_tableidxw_goodsyntax: {
1646     MCInst TmpInst;
1647     MCOperand &Rx = Inst.getOperand(0);
1648     MCOperand &Rs = Inst.getOperand(2);
1649     MCOperand &Imm4 = Inst.getOperand(3);
1650     MCOperand &Imm6 = Inst.getOperand(4);
1651     Imm6.setExpr(HexagonMCExpr::create(
1652         MCBinaryExpr::createSub(Imm6.getExpr(),
1653                                 MCConstantExpr::create(2, Context), Context),
1654         Context));
1655     TmpInst.setOpcode(Hexagon::S2_tableidxw);
1656     TmpInst.addOperand(Rx);
1657     TmpInst.addOperand(Rx);
1658     TmpInst.addOperand(Rs);
1659     TmpInst.addOperand(Imm4);
1660     TmpInst.addOperand(Imm6);
1661     Inst = TmpInst;
1662     break;
1663   }
1664 
1665   case Hexagon::S2_tableidxd_goodsyntax: {
1666     MCInst TmpInst;
1667     MCOperand &Rx = Inst.getOperand(0);
1668     MCOperand &Rs = Inst.getOperand(2);
1669     MCOperand &Imm4 = Inst.getOperand(3);
1670     MCOperand &Imm6 = Inst.getOperand(4);
1671     Imm6.setExpr(HexagonMCExpr::create(
1672         MCBinaryExpr::createSub(Imm6.getExpr(),
1673                                 MCConstantExpr::create(3, Context), Context),
1674         Context));
1675     TmpInst.setOpcode(Hexagon::S2_tableidxd);
1676     TmpInst.addOperand(Rx);
1677     TmpInst.addOperand(Rx);
1678     TmpInst.addOperand(Rs);
1679     TmpInst.addOperand(Imm4);
1680     TmpInst.addOperand(Imm6);
1681     Inst = TmpInst;
1682     break;
1683   }
1684 
1685   case Hexagon::M2_mpyui:
1686     Inst.setOpcode(Hexagon::M2_mpyi);
1687     break;
1688   case Hexagon::M2_mpysmi: {
1689     MCInst TmpInst;
1690     MCOperand &Rd = Inst.getOperand(0);
1691     MCOperand &Rs = Inst.getOperand(1);
1692     MCOperand &Imm = Inst.getOperand(2);
1693     int64_t Value;
1694     MCExpr const &Expr = *Imm.getExpr();
1695     bool Absolute = Expr.evaluateAsAbsolute(Value);
1696     if (!Absolute)
1697       return Match_InvalidOperand;
1698     if (!HexagonMCInstrInfo::mustExtend(Expr) &&
1699         ((Value <= -256) || Value >= 256))
1700       return Match_InvalidOperand;
1701     if (Value < 0 && Value > -256) {
1702       Imm.setExpr(HexagonMCExpr::create(
1703           MCConstantExpr::create(Value * -1, Context), Context));
1704       TmpInst.setOpcode(Hexagon::M2_mpysin);
1705     } else
1706       TmpInst.setOpcode(Hexagon::M2_mpysip);
1707     TmpInst.addOperand(Rd);
1708     TmpInst.addOperand(Rs);
1709     TmpInst.addOperand(Imm);
1710     Inst = TmpInst;
1711     break;
1712   }
1713 
1714   case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
1715     MCOperand &Imm = Inst.getOperand(2);
1716     MCInst TmpInst;
1717     int64_t Value;
1718     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1719     if (!Absolute)
1720       return Match_InvalidOperand;
1721     if (Value == 0) { // convert to $Rd = $Rs
1722       TmpInst.setOpcode(Hexagon::A2_tfr);
1723       MCOperand &Rd = Inst.getOperand(0);
1724       MCOperand &Rs = Inst.getOperand(1);
1725       TmpInst.addOperand(Rd);
1726       TmpInst.addOperand(Rs);
1727     } else {
1728       Imm.setExpr(HexagonMCExpr::create(
1729           MCBinaryExpr::createSub(Imm.getExpr(),
1730                                   MCConstantExpr::create(1, Context), Context),
1731           Context));
1732       TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
1733       MCOperand &Rd = Inst.getOperand(0);
1734       MCOperand &Rs = Inst.getOperand(1);
1735       TmpInst.addOperand(Rd);
1736       TmpInst.addOperand(Rs);
1737       TmpInst.addOperand(Imm);
1738     }
1739     Inst = TmpInst;
1740     break;
1741   }
1742 
1743   case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
1744     MCOperand &Rdd = Inst.getOperand(0);
1745     MCOperand &Rss = Inst.getOperand(1);
1746     MCOperand &Imm = Inst.getOperand(2);
1747     int64_t Value;
1748     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1749     if (!Absolute)
1750       return Match_InvalidOperand;
1751     if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1])
1752       MCInst TmpInst;
1753       unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1754       std::string R1 = r + utostr(RegPairNum + 1);
1755       StringRef Reg1(R1);
1756       Rss.setReg(matchRegister(Reg1));
1757       // Add a new operand for the second register in the pair.
1758       std::string R2 = r + utostr(RegPairNum);
1759       StringRef Reg2(R2);
1760       TmpInst.setOpcode(Hexagon::A2_combinew);
1761       TmpInst.addOperand(Rdd);
1762       TmpInst.addOperand(Rss);
1763       TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1764       Inst = TmpInst;
1765     } else {
1766       Imm.setExpr(HexagonMCExpr::create(
1767           MCBinaryExpr::createSub(Imm.getExpr(),
1768                                   MCConstantExpr::create(1, Context), Context),
1769           Context));
1770       Inst.setOpcode(Hexagon::S2_asr_i_p_rnd);
1771     }
1772     break;
1773   }
1774 
1775   case Hexagon::A4_boundscheck: {
1776     MCOperand &Rs = Inst.getOperand(1);
1777     unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1778     if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1779       Inst.setOpcode(Hexagon::A4_boundscheck_hi);
1780       std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1781       StringRef RegPair = Name;
1782       Rs.setReg(matchRegister(RegPair));
1783     } else { // raw:lo
1784       Inst.setOpcode(Hexagon::A4_boundscheck_lo);
1785       std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1786       StringRef RegPair = Name;
1787       Rs.setReg(matchRegister(RegPair));
1788     }
1789     break;
1790   }
1791 
1792   case Hexagon::A2_addsp: {
1793     MCOperand &Rs = Inst.getOperand(1);
1794     unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1795     if (RegNum & 1) { // Odd mapped to raw:hi
1796       Inst.setOpcode(Hexagon::A2_addsph);
1797       std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1798       StringRef RegPair = Name;
1799       Rs.setReg(matchRegister(RegPair));
1800     } else { // Even mapped raw:lo
1801       Inst.setOpcode(Hexagon::A2_addspl);
1802       std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1803       StringRef RegPair = Name;
1804       Rs.setReg(matchRegister(RegPair));
1805     }
1806     break;
1807   }
1808 
1809   case Hexagon::M2_vrcmpys_s1: {
1810     MCOperand &Rt = Inst.getOperand(2);
1811     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
1812     if (RegNum & 1) { // Odd mapped to sat:raw:hi
1813       Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
1814       std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1815       StringRef RegPair = Name;
1816       Rt.setReg(matchRegister(RegPair));
1817     } else { // Even mapped sat:raw:lo
1818       Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
1819       std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1820       StringRef RegPair = Name;
1821       Rt.setReg(matchRegister(RegPair));
1822     }
1823     break;
1824   }
1825 
1826   case Hexagon::M2_vrcmpys_acc_s1: {
1827     MCInst TmpInst;
1828     MCOperand &Rxx = Inst.getOperand(0);
1829     MCOperand &Rss = Inst.getOperand(2);
1830     MCOperand &Rt = Inst.getOperand(3);
1831     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
1832     if (RegNum & 1) { // Odd mapped to sat:raw:hi
1833       TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
1834       std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1835       StringRef RegPair = Name;
1836       Rt.setReg(matchRegister(RegPair));
1837     } else { // Even mapped sat:raw:lo
1838       TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
1839       std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1840       StringRef RegPair = Name;
1841       Rt.setReg(matchRegister(RegPair));
1842     }
1843     // Registers are in different positions
1844     TmpInst.addOperand(Rxx);
1845     TmpInst.addOperand(Rxx);
1846     TmpInst.addOperand(Rss);
1847     TmpInst.addOperand(Rt);
1848     Inst = TmpInst;
1849     break;
1850   }
1851 
1852   case Hexagon::M2_vrcmpys_s1rp: {
1853     MCOperand &Rt = Inst.getOperand(2);
1854     unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
1855     if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi
1856       Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
1857       std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1858       StringRef RegPair = Name;
1859       Rt.setReg(matchRegister(RegPair));
1860     } else { // Even mapped rnd:sat:raw:lo
1861       Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
1862       std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1863       StringRef RegPair = Name;
1864       Rt.setReg(matchRegister(RegPair));
1865     }
1866     break;
1867   }
1868 
1869   case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
1870     MCOperand &Imm = Inst.getOperand(2);
1871     int64_t Value;
1872     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1873     if (!Absolute)
1874       return Match_InvalidOperand;
1875     if (Value == 0)
1876       Inst.setOpcode(Hexagon::S2_vsathub);
1877     else {
1878       Imm.setExpr(HexagonMCExpr::create(
1879           MCBinaryExpr::createSub(Imm.getExpr(),
1880                                   MCConstantExpr::create(1, Context), Context),
1881           Context));
1882       Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
1883     }
1884     break;
1885   }
1886 
1887   case Hexagon::S5_vasrhrnd_goodsyntax: {
1888     MCOperand &Rdd = Inst.getOperand(0);
1889     MCOperand &Rss = Inst.getOperand(1);
1890     MCOperand &Imm = Inst.getOperand(2);
1891     int64_t Value;
1892     bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1893     if (!Absolute)
1894       return Match_InvalidOperand;
1895     if (Value == 0) {
1896       MCInst TmpInst;
1897       unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1898       std::string R1 = r + utostr(RegPairNum + 1);
1899       StringRef Reg1(R1);
1900       Rss.setReg(matchRegister(Reg1));
1901       // Add a new operand for the second register in the pair.
1902       std::string R2 = r + utostr(RegPairNum);
1903       StringRef Reg2(R2);
1904       TmpInst.setOpcode(Hexagon::A2_combinew);
1905       TmpInst.addOperand(Rdd);
1906       TmpInst.addOperand(Rss);
1907       TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1908       Inst = TmpInst;
1909     } else {
1910       Imm.setExpr(HexagonMCExpr::create(
1911           MCBinaryExpr::createSub(Imm.getExpr(),
1912                                   MCConstantExpr::create(1, Context), Context),
1913           Context));
1914       Inst.setOpcode(Hexagon::S5_vasrhrnd);
1915     }
1916     break;
1917   }
1918 
1919   case Hexagon::A2_not: {
1920     MCInst TmpInst;
1921     MCOperand &Rd = Inst.getOperand(0);
1922     MCOperand &Rs = Inst.getOperand(1);
1923     TmpInst.setOpcode(Hexagon::A2_subri);
1924     TmpInst.addOperand(Rd);
1925     TmpInst.addOperand(MCOperand::createExpr(
1926         HexagonMCExpr::create(MCConstantExpr::create(-1, Context), Context)));
1927     TmpInst.addOperand(Rs);
1928     Inst = TmpInst;
1929     break;
1930   }
1931   case Hexagon::PS_loadrubabs:
1932     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1933       Inst.setOpcode(Hexagon::L2_loadrubgp);
1934     break;
1935   case Hexagon::PS_loadrbabs:
1936     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1937       Inst.setOpcode(Hexagon::L2_loadrbgp);
1938     break;
1939   case Hexagon::PS_loadruhabs:
1940     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1941       Inst.setOpcode(Hexagon::L2_loadruhgp);
1942     break;
1943   case Hexagon::PS_loadrhabs:
1944     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1945       Inst.setOpcode(Hexagon::L2_loadrhgp);
1946     break;
1947   case Hexagon::PS_loadriabs:
1948     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1949       Inst.setOpcode(Hexagon::L2_loadrigp);
1950     break;
1951   case Hexagon::PS_loadrdabs:
1952     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1953       Inst.setOpcode(Hexagon::L2_loadrdgp);
1954     break;
1955   case Hexagon::PS_storerbabs:
1956     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1957       Inst.setOpcode(Hexagon::S2_storerbgp);
1958     break;
1959   case Hexagon::PS_storerhabs:
1960     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1961       Inst.setOpcode(Hexagon::S2_storerhgp);
1962     break;
1963   case Hexagon::PS_storerfabs:
1964     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1965       Inst.setOpcode(Hexagon::S2_storerfgp);
1966     break;
1967   case Hexagon::PS_storeriabs:
1968     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1969       Inst.setOpcode(Hexagon::S2_storerigp);
1970     break;
1971   case Hexagon::PS_storerdabs:
1972     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1973       Inst.setOpcode(Hexagon::S2_storerdgp);
1974     break;
1975   case Hexagon::PS_storerbnewabs:
1976     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1977       Inst.setOpcode(Hexagon::S2_storerbnewgp);
1978     break;
1979   case Hexagon::PS_storerhnewabs:
1980     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1981       Inst.setOpcode(Hexagon::S2_storerhnewgp);
1982     break;
1983   case Hexagon::PS_storerinewabs:
1984     if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1985       Inst.setOpcode(Hexagon::S2_storerinewgp);
1986     break;
1987   case Hexagon::A2_zxtb: {
1988     Inst.setOpcode(Hexagon::A2_andir);
1989     Inst.addOperand(
1990         MCOperand::createExpr(MCConstantExpr::create(255, Context)));
1991     break;
1992   }
1993   } // switch
1994 
1995   return Match_Success;
1996 }
1997 
1998 unsigned HexagonAsmParser::matchRegister(StringRef Name) {
1999   if (unsigned Reg = MatchRegisterName(Name))
2000     return Reg;
2001   return MatchRegisterAltName(Name);
2002 }
2003