1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides ARM specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMMCTargetDesc.h" 14 #include "ARMAddressingModes.h" 15 #include "ARMBaseInfo.h" 16 #include "ARMInstPrinter.h" 17 #include "ARMMCAsmInfo.h" 18 #include "TargetInfo/ARMTargetInfo.h" 19 #include "llvm/DebugInfo/CodeView/CodeView.h" 20 #include "llvm/MC/MCAsmBackend.h" 21 #include "llvm/MC/MCCodeEmitter.h" 22 #include "llvm/MC/MCELFStreamer.h" 23 #include "llvm/MC/MCInstrAnalysis.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCObjectWriter.h" 26 #include "llvm/MC/MCRegisterInfo.h" 27 #include "llvm/MC/MCStreamer.h" 28 #include "llvm/MC/MCSubtargetInfo.h" 29 #include "llvm/MC/TargetRegistry.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/TargetParser/Triple.h" 32 33 using namespace llvm; 34 35 #define GET_REGINFO_MC_DESC 36 #include "ARMGenRegisterInfo.inc" 37 38 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 39 std::string &Info) { 40 if (STI.hasFeature(llvm::ARM::HasV7Ops) && 41 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && 42 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && 43 // Checks for the deprecated CP15ISB encoding: 44 // mcr p15, #0, rX, c7, c5, #4 45 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { 46 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { 47 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { 48 Info = "deprecated since v7, use 'isb'"; 49 return true; 50 } 51 52 // Checks for the deprecated CP15DSB encoding: 53 // mcr p15, #0, rX, c7, c10, #4 54 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { 55 Info = "deprecated since v7, use 'dsb'"; 56 return true; 57 } 58 } 59 // Checks for the deprecated CP15DMB encoding: 60 // mcr p15, #0, rX, c7, c10, #5 61 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && 62 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { 63 Info = "deprecated since v7, use 'dmb'"; 64 return true; 65 } 66 } 67 if (STI.hasFeature(llvm::ARM::HasV7Ops) && 68 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) || 69 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) { 70 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating " 71 "point instructions"; 72 return true; 73 } 74 return false; 75 } 76 77 static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 78 std::string &Info) { 79 if (STI.hasFeature(llvm::ARM::HasV7Ops) && 80 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) || 81 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) { 82 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating " 83 "point instructions"; 84 return true; 85 } 86 return false; 87 } 88 89 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 90 std::string &Info) { 91 assert(!STI.hasFeature(llvm::ARM::ModeThumb) && 92 "cannot predicate thumb instructions"); 93 94 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); 95 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) { 96 assert(MI.getOperand(OI).isReg() && "expected register"); 97 if (MI.getOperand(OI).getReg() == ARM::PC) { 98 Info = "use of PC in the list is deprecated"; 99 return true; 100 } 101 } 102 return false; 103 } 104 105 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 106 std::string &Info) { 107 assert(!STI.hasFeature(llvm::ARM::ModeThumb) && 108 "cannot predicate thumb instructions"); 109 110 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); 111 bool ListContainsPC = false, ListContainsLR = false; 112 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) { 113 assert(MI.getOperand(OI).isReg() && "expected register"); 114 switch (MI.getOperand(OI).getReg()) { 115 default: 116 break; 117 case ARM::LR: 118 ListContainsLR = true; 119 break; 120 case ARM::PC: 121 ListContainsPC = true; 122 break; 123 } 124 } 125 126 if (ListContainsPC && ListContainsLR) { 127 Info = "use of LR and PC simultaneously in the list is deprecated"; 128 return true; 129 } 130 131 return false; 132 } 133 134 #define GET_INSTRINFO_MC_DESC 135 #define ENABLE_INSTR_PREDICATE_VERIFIER 136 #include "ARMGenInstrInfo.inc" 137 138 #define GET_SUBTARGETINFO_MC_DESC 139 #include "ARMGenSubtargetInfo.inc" 140 141 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { 142 std::string ARMArchFeature; 143 144 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); 145 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic")) 146 ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str(); 147 148 if (TT.isThumb()) { 149 if (!ARMArchFeature.empty()) 150 ARMArchFeature += ","; 151 ARMArchFeature += "+thumb-mode,+v4t"; 152 } 153 154 if (TT.isOSNaCl()) { 155 if (!ARMArchFeature.empty()) 156 ARMArchFeature += ","; 157 ARMArchFeature += "+nacl-trap"; 158 } 159 160 if (TT.isOSWindows()) { 161 if (!ARMArchFeature.empty()) 162 ARMArchFeature += ","; 163 ARMArchFeature += "+noarm"; 164 } 165 166 return ARMArchFeature; 167 } 168 169 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) { 170 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 171 int PredOpIdx = Desc.findFirstPredOperandIdx(); 172 return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL; 173 } 174 175 bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) { 176 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 177 for (unsigned I = 0; I < MI.getNumOperands(); ++I) { 178 const MCOperand &MO = MI.getOperand(I); 179 if (MO.isReg() && MO.getReg() == ARM::CPSR && 180 Desc.operands()[I].isOptionalDef()) 181 return true; 182 } 183 return false; 184 } 185 186 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, 187 uint64_t Addr, int64_t Imm) { 188 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it 189 // is 4 bytes. 190 uint64_t Offset = 191 ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8; 192 193 // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code 194 // which is 32-bit aligned. The target address for the case is calculated as 195 // targetAddress = Align(PC,4) + imm32; 196 // where 197 // Align(x, y) = y * (x DIV y); 198 if (InstDesc.getOpcode() == ARM::tBLXi) 199 Addr &= ~0x3; 200 201 return Addr + Imm + Offset; 202 } 203 204 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT, 205 StringRef CPU, StringRef FS) { 206 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); 207 if (!FS.empty()) { 208 if (!ArchFS.empty()) 209 ArchFS = (Twine(ArchFS) + "," + FS).str(); 210 else 211 ArchFS = std::string(FS); 212 } 213 214 return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS); 215 } 216 217 static MCInstrInfo *createARMMCInstrInfo() { 218 MCInstrInfo *X = new MCInstrInfo(); 219 InitARMMCInstrInfo(X); 220 return X; 221 } 222 223 void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { 224 // Mapping from CodeView to MC register id. 225 static const struct { 226 codeview::RegisterId CVReg; 227 MCPhysReg Reg; 228 } RegMap[] = { 229 {codeview::RegisterId::ARM_R0, ARM::R0}, 230 {codeview::RegisterId::ARM_R1, ARM::R1}, 231 {codeview::RegisterId::ARM_R2, ARM::R2}, 232 {codeview::RegisterId::ARM_R3, ARM::R3}, 233 {codeview::RegisterId::ARM_R4, ARM::R4}, 234 {codeview::RegisterId::ARM_R5, ARM::R5}, 235 {codeview::RegisterId::ARM_R6, ARM::R6}, 236 {codeview::RegisterId::ARM_R7, ARM::R7}, 237 {codeview::RegisterId::ARM_R8, ARM::R8}, 238 {codeview::RegisterId::ARM_R9, ARM::R9}, 239 {codeview::RegisterId::ARM_R10, ARM::R10}, 240 {codeview::RegisterId::ARM_R11, ARM::R11}, 241 {codeview::RegisterId::ARM_R12, ARM::R12}, 242 {codeview::RegisterId::ARM_SP, ARM::SP}, 243 {codeview::RegisterId::ARM_LR, ARM::LR}, 244 {codeview::RegisterId::ARM_PC, ARM::PC}, 245 {codeview::RegisterId::ARM_CPSR, ARM::CPSR}, 246 {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR}, 247 {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC}, 248 {codeview::RegisterId::ARM_FS0, ARM::S0}, 249 {codeview::RegisterId::ARM_FS1, ARM::S1}, 250 {codeview::RegisterId::ARM_FS2, ARM::S2}, 251 {codeview::RegisterId::ARM_FS3, ARM::S3}, 252 {codeview::RegisterId::ARM_FS4, ARM::S4}, 253 {codeview::RegisterId::ARM_FS5, ARM::S5}, 254 {codeview::RegisterId::ARM_FS6, ARM::S6}, 255 {codeview::RegisterId::ARM_FS7, ARM::S7}, 256 {codeview::RegisterId::ARM_FS8, ARM::S8}, 257 {codeview::RegisterId::ARM_FS9, ARM::S9}, 258 {codeview::RegisterId::ARM_FS10, ARM::S10}, 259 {codeview::RegisterId::ARM_FS11, ARM::S11}, 260 {codeview::RegisterId::ARM_FS12, ARM::S12}, 261 {codeview::RegisterId::ARM_FS13, ARM::S13}, 262 {codeview::RegisterId::ARM_FS14, ARM::S14}, 263 {codeview::RegisterId::ARM_FS15, ARM::S15}, 264 {codeview::RegisterId::ARM_FS16, ARM::S16}, 265 {codeview::RegisterId::ARM_FS17, ARM::S17}, 266 {codeview::RegisterId::ARM_FS18, ARM::S18}, 267 {codeview::RegisterId::ARM_FS19, ARM::S19}, 268 {codeview::RegisterId::ARM_FS20, ARM::S20}, 269 {codeview::RegisterId::ARM_FS21, ARM::S21}, 270 {codeview::RegisterId::ARM_FS22, ARM::S22}, 271 {codeview::RegisterId::ARM_FS23, ARM::S23}, 272 {codeview::RegisterId::ARM_FS24, ARM::S24}, 273 {codeview::RegisterId::ARM_FS25, ARM::S25}, 274 {codeview::RegisterId::ARM_FS26, ARM::S26}, 275 {codeview::RegisterId::ARM_FS27, ARM::S27}, 276 {codeview::RegisterId::ARM_FS28, ARM::S28}, 277 {codeview::RegisterId::ARM_FS29, ARM::S29}, 278 {codeview::RegisterId::ARM_FS30, ARM::S30}, 279 {codeview::RegisterId::ARM_FS31, ARM::S31}, 280 {codeview::RegisterId::ARM_ND0, ARM::D0}, 281 {codeview::RegisterId::ARM_ND1, ARM::D1}, 282 {codeview::RegisterId::ARM_ND2, ARM::D2}, 283 {codeview::RegisterId::ARM_ND3, ARM::D3}, 284 {codeview::RegisterId::ARM_ND4, ARM::D4}, 285 {codeview::RegisterId::ARM_ND5, ARM::D5}, 286 {codeview::RegisterId::ARM_ND6, ARM::D6}, 287 {codeview::RegisterId::ARM_ND7, ARM::D7}, 288 {codeview::RegisterId::ARM_ND8, ARM::D8}, 289 {codeview::RegisterId::ARM_ND9, ARM::D9}, 290 {codeview::RegisterId::ARM_ND10, ARM::D10}, 291 {codeview::RegisterId::ARM_ND11, ARM::D11}, 292 {codeview::RegisterId::ARM_ND12, ARM::D12}, 293 {codeview::RegisterId::ARM_ND13, ARM::D13}, 294 {codeview::RegisterId::ARM_ND14, ARM::D14}, 295 {codeview::RegisterId::ARM_ND15, ARM::D15}, 296 {codeview::RegisterId::ARM_ND16, ARM::D16}, 297 {codeview::RegisterId::ARM_ND17, ARM::D17}, 298 {codeview::RegisterId::ARM_ND18, ARM::D18}, 299 {codeview::RegisterId::ARM_ND19, ARM::D19}, 300 {codeview::RegisterId::ARM_ND20, ARM::D20}, 301 {codeview::RegisterId::ARM_ND21, ARM::D21}, 302 {codeview::RegisterId::ARM_ND22, ARM::D22}, 303 {codeview::RegisterId::ARM_ND23, ARM::D23}, 304 {codeview::RegisterId::ARM_ND24, ARM::D24}, 305 {codeview::RegisterId::ARM_ND25, ARM::D25}, 306 {codeview::RegisterId::ARM_ND26, ARM::D26}, 307 {codeview::RegisterId::ARM_ND27, ARM::D27}, 308 {codeview::RegisterId::ARM_ND28, ARM::D28}, 309 {codeview::RegisterId::ARM_ND29, ARM::D29}, 310 {codeview::RegisterId::ARM_ND30, ARM::D30}, 311 {codeview::RegisterId::ARM_ND31, ARM::D31}, 312 {codeview::RegisterId::ARM_NQ0, ARM::Q0}, 313 {codeview::RegisterId::ARM_NQ1, ARM::Q1}, 314 {codeview::RegisterId::ARM_NQ2, ARM::Q2}, 315 {codeview::RegisterId::ARM_NQ3, ARM::Q3}, 316 {codeview::RegisterId::ARM_NQ4, ARM::Q4}, 317 {codeview::RegisterId::ARM_NQ5, ARM::Q5}, 318 {codeview::RegisterId::ARM_NQ6, ARM::Q6}, 319 {codeview::RegisterId::ARM_NQ7, ARM::Q7}, 320 {codeview::RegisterId::ARM_NQ8, ARM::Q8}, 321 {codeview::RegisterId::ARM_NQ9, ARM::Q9}, 322 {codeview::RegisterId::ARM_NQ10, ARM::Q10}, 323 {codeview::RegisterId::ARM_NQ11, ARM::Q11}, 324 {codeview::RegisterId::ARM_NQ12, ARM::Q12}, 325 {codeview::RegisterId::ARM_NQ13, ARM::Q13}, 326 {codeview::RegisterId::ARM_NQ14, ARM::Q14}, 327 {codeview::RegisterId::ARM_NQ15, ARM::Q15}, 328 }; 329 for (const auto &I : RegMap) 330 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); 331 } 332 333 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) { 334 MCRegisterInfo *X = new MCRegisterInfo(); 335 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC); 336 ARM_MC::initLLVMToCVRegMapping(X); 337 return X; 338 } 339 340 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, 341 const Triple &TheTriple, 342 const MCTargetOptions &Options) { 343 MCAsmInfo *MAI; 344 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO()) 345 MAI = new ARMMCAsmInfoDarwin(TheTriple); 346 else if (TheTriple.isWindowsMSVCEnvironment()) 347 MAI = new ARMCOFFMCAsmInfoMicrosoft(); 348 else if (TheTriple.isOSWindows()) 349 MAI = new ARMCOFFMCAsmInfoGNU(); 350 else 351 MAI = new ARMELFMCAsmInfo(TheTriple); 352 353 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); 354 MAI->addInitialFrameState(MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0)); 355 356 return MAI; 357 } 358 359 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, 360 std::unique_ptr<MCAsmBackend> &&MAB, 361 std::unique_ptr<MCObjectWriter> &&OW, 362 std::unique_ptr<MCCodeEmitter> &&Emitter) { 363 return createARMELFStreamer( 364 Ctx, std::move(MAB), std::move(OW), std::move(Emitter), 365 (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb), 366 T.isAndroid()); 367 } 368 369 static MCStreamer * 370 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB, 371 std::unique_ptr<MCObjectWriter> &&OW, 372 std::unique_ptr<MCCodeEmitter> &&Emitter, 373 bool DWARFMustBeAtTheEnd) { 374 return createMachOStreamer(Ctx, std::move(MAB), std::move(OW), 375 std::move(Emitter), DWARFMustBeAtTheEnd); 376 } 377 378 static MCInstPrinter *createARMMCInstPrinter(const Triple &T, 379 unsigned SyntaxVariant, 380 const MCAsmInfo &MAI, 381 const MCInstrInfo &MII, 382 const MCRegisterInfo &MRI) { 383 if (SyntaxVariant == 0) 384 return new ARMInstPrinter(MAI, MII, MRI); 385 return nullptr; 386 } 387 388 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT, 389 MCContext &Ctx) { 390 if (TT.isOSBinFormatMachO()) 391 return createARMMachORelocationInfo(Ctx); 392 // Default to the stock relocation info. 393 return llvm::createMCRelocationInfo(TT, Ctx); 394 } 395 396 namespace { 397 398 class ARMMCInstrAnalysis : public MCInstrAnalysis { 399 public: 400 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 401 402 bool isUnconditionalBranch(const MCInst &Inst) const override { 403 // BCCs with the "always" predicate are unconditional branches. 404 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 405 return true; 406 return MCInstrAnalysis::isUnconditionalBranch(Inst); 407 } 408 409 bool isConditionalBranch(const MCInst &Inst) const override { 410 // BCCs with the "always" predicate are unconditional branches. 411 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 412 return false; 413 return MCInstrAnalysis::isConditionalBranch(Inst); 414 } 415 416 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 417 uint64_t &Target) const override { 418 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 419 420 // Find the PC-relative immediate operand in the instruction. 421 for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) { 422 if (Inst.getOperand(OpNum).isImm() && 423 Desc.operands()[OpNum].OperandType == MCOI::OPERAND_PCREL) { 424 int64_t Imm = Inst.getOperand(OpNum).getImm(); 425 Target = ARM_MC::evaluateBranchTarget(Desc, Addr, Imm); 426 return true; 427 } 428 } 429 return false; 430 } 431 432 std::optional<uint64_t> 433 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, 434 uint64_t Addr, uint64_t Size) const override; 435 }; 436 437 } // namespace 438 439 static std::optional<uint64_t> 440 // NOLINTNEXTLINE(readability-identifier-naming) 441 evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, 442 unsigned MemOpIndex, uint64_t Addr) { 443 if (MemOpIndex + 1 >= Desc.getNumOperands()) 444 return std::nullopt; 445 446 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 447 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); 448 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) 449 return std::nullopt; 450 451 int32_t OffImm = (int32_t)MO2.getImm(); 452 // Special value for #-0. All others are normal. 453 if (OffImm == INT32_MIN) 454 OffImm = 0; 455 return Addr + OffImm; 456 } 457 458 static std::optional<uint64_t> 459 evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, 460 unsigned MemOpIndex, uint64_t Addr) { 461 if (MemOpIndex + 2 >= Desc.getNumOperands()) 462 return std::nullopt; 463 464 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 465 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); 466 const MCOperand &MO3 = Inst.getOperand(MemOpIndex + 2); 467 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm()) 468 return std::nullopt; 469 470 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); 471 ARM_AM::AddrOpc Op = ARM_AM::getAM3Op(MO3.getImm()); 472 473 if (Op == ARM_AM::sub) 474 return Addr - ImmOffs; 475 return Addr + ImmOffs; 476 } 477 478 static std::optional<uint64_t> 479 evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, 480 unsigned MemOpIndex, uint64_t Addr) { 481 if (MemOpIndex + 1 >= Desc.getNumOperands()) 482 return std::nullopt; 483 484 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 485 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); 486 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) 487 return std::nullopt; 488 489 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); 490 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm()); 491 492 if (Op == ARM_AM::sub) 493 return Addr - ImmOffs * 4; 494 return Addr + ImmOffs * 4; 495 } 496 497 static std::optional<uint64_t> 498 evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, 499 unsigned MemOpIndex, uint64_t Addr) { 500 if (MemOpIndex + 1 >= Desc.getNumOperands()) 501 return std::nullopt; 502 503 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 504 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); 505 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) 506 return std::nullopt; 507 508 unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm()); 509 ARM_AM::AddrOpc Op = ARM_AM::getAM5FP16Op(MO2.getImm()); 510 511 if (Op == ARM_AM::sub) 512 return Addr - ImmOffs * 2; 513 return Addr + ImmOffs * 2; 514 } 515 516 static std::optional<uint64_t> 517 // NOLINTNEXTLINE(readability-identifier-naming) 518 evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc, 519 unsigned MemOpIndex, uint64_t Addr) { 520 if (MemOpIndex + 1 >= Desc.getNumOperands()) 521 return std::nullopt; 522 523 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 524 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); 525 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) 526 return std::nullopt; 527 528 int32_t OffImm = (int32_t)MO2.getImm(); 529 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); 530 531 // Special value for #-0. All others are normal. 532 if (OffImm == INT32_MIN) 533 OffImm = 0; 534 return Addr + OffImm; 535 } 536 537 static std::optional<uint64_t> 538 // NOLINTNEXTLINE(readability-identifier-naming) 539 evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, 540 unsigned MemOpIndex, uint64_t Addr) { 541 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 542 if (!MO1.isImm()) 543 return std::nullopt; 544 545 int32_t OffImm = (int32_t)MO1.getImm(); 546 547 // Special value for #-0. All others are normal. 548 if (OffImm == INT32_MIN) 549 OffImm = 0; 550 return Addr + OffImm; 551 } 552 553 static std::optional<uint64_t> 554 // NOLINTNEXTLINE(readability-identifier-naming) 555 evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, 556 unsigned MemOpIndex, uint64_t Addr) { 557 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr); 558 } 559 560 std::optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress( 561 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, 562 uint64_t Size) const { 563 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 564 565 // Only load instructions can have PC-relative memory addressing. 566 if (!Desc.mayLoad()) 567 return std::nullopt; 568 569 // PC-relative addressing does not update the base register. 570 uint64_t TSFlags = Desc.TSFlags; 571 unsigned IndexMode = 572 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; 573 if (IndexMode != ARMII::IndexModeNone) 574 return std::nullopt; 575 576 // Find the memory addressing operand in the instruction. 577 unsigned OpIndex = Desc.NumDefs; 578 while (OpIndex < Desc.getNumOperands() && 579 Desc.operands()[OpIndex].OperandType != MCOI::OPERAND_MEMORY) 580 ++OpIndex; 581 if (OpIndex == Desc.getNumOperands()) 582 return std::nullopt; 583 584 // Base address for PC-relative addressing is always 32-bit aligned. 585 Addr &= ~0x3; 586 587 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it 588 // is 4 bytes. 589 switch (Desc.TSFlags & ARMII::FormMask) { 590 default: 591 Addr += 8; 592 break; 593 case ARMII::ThumbFrm: 594 Addr += 4; 595 break; 596 // VLDR* instructions share the same opcode (and thus the same form) for Arm 597 // and Thumb. Use a bit longer route through STI in that case. 598 case ARMII::VFPLdStFrm: 599 Addr += STI->hasFeature(ARM::ModeThumb) ? 4 : 8; 600 break; 601 } 602 603 // Eveluate the address depending on the addressing mode 604 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 605 switch (AddrMode) { 606 default: 607 return std::nullopt; 608 case ARMII::AddrMode_i12: 609 return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, OpIndex, Addr); 610 case ARMII::AddrMode3: 611 return evaluateMemOpAddrForAddrMode3(Inst, Desc, OpIndex, Addr); 612 case ARMII::AddrMode5: 613 return evaluateMemOpAddrForAddrMode5(Inst, Desc, OpIndex, Addr); 614 case ARMII::AddrMode5FP16: 615 return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, OpIndex, Addr); 616 case ARMII::AddrModeT2_i8s4: 617 return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, OpIndex, Addr); 618 case ARMII::AddrModeT2_pc: 619 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, OpIndex, Addr); 620 case ARMII::AddrModeT1_s: 621 return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, OpIndex, Addr); 622 } 623 } 624 625 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) { 626 return new ARMMCInstrAnalysis(Info); 627 } 628 629 bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) { 630 // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have 631 // to rely on feature bits. 632 if (Coproc >= 8) 633 return false; 634 return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc]; 635 } 636 637 // Force static initialization. 638 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() { 639 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(), 640 &getTheThumbLETarget(), &getTheThumbBETarget()}) { 641 // Register the MC asm info. 642 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo); 643 644 // Register the MC instruction info. 645 TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo); 646 647 // Register the MC register info. 648 TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo); 649 650 // Register the MC subtarget info. 651 TargetRegistry::RegisterMCSubtargetInfo(*T, 652 ARM_MC::createARMMCSubtargetInfo); 653 654 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer); 655 TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer); 656 TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer); 657 658 // Register the obj target streamer. 659 TargetRegistry::RegisterObjectTargetStreamer(*T, 660 createARMObjectTargetStreamer); 661 662 // Register the asm streamer. 663 TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer); 664 665 // Register the null TargetStreamer. 666 TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer); 667 668 // Register the MCInstPrinter. 669 TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter); 670 671 // Register the MC relocation info. 672 TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo); 673 } 674 675 // Register the MC instruction analyzer. 676 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(), 677 &getTheThumbLETarget(), &getTheThumbBETarget()}) 678 TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis); 679 680 for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) { 681 TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter); 682 TargetRegistry::RegisterMCAsmBackend(*T, createARMLEAsmBackend); 683 } 684 for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) { 685 TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter); 686 TargetRegistry::RegisterMCAsmBackend(*T, createARMBEAsmBackend); 687 } 688 } 689