1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &VStream, 141 raw_ostream &CStream) const override; 142 143 private: 144 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 145 ArrayRef<uint8_t> Bytes, uint64_t Address, 146 raw_ostream &VStream, 147 raw_ostream &CStream) const; 148 149 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 150 ArrayRef<uint8_t> Bytes, uint64_t Address, 151 raw_ostream &VStream, 152 raw_ostream &CStream) const; 153 154 mutable ITStatus ITBlock; 155 mutable VPTStatus VPTBlock; 156 157 DecodeStatus AddThumbPredicate(MCInst&) const; 158 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 159 }; 160 161 } // end anonymous namespace 162 163 static bool Check(DecodeStatus &Out, DecodeStatus In) { 164 switch (In) { 165 case MCDisassembler::Success: 166 // Out stays the same. 167 return true; 168 case MCDisassembler::SoftFail: 169 Out = In; 170 return true; 171 case MCDisassembler::Fail: 172 Out = In; 173 return false; 174 } 175 llvm_unreachable("Invalid DecodeStatus!"); 176 } 177 178 // Forward declare these because the autogenerated code will reference them. 179 // Definitions are further down. 180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 216 unsigned RegNo, 217 uint64_t Address, 218 const void *Decoder); 219 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 230 unsigned RegNo, uint64_t Address, 231 const void *Decoder); 232 233 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 244 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 249 unsigned Insn, 250 uint64_t Address, 251 const void *Decoder); 252 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 261 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 262 unsigned Insn, 263 uint64_t Adddress, 264 const void *Decoder); 265 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 386 unsigned Val, 387 uint64_t Address, 388 const void *Decoder); 389 390 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 403 uint64_t Address, const void *Decoder); 404 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 411 uint64_t Address, const void* Decoder); 412 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 413 uint64_t Address, const void* Decoder); 414 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 415 uint64_t Address, const void* Decoder); 416 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 417 uint64_t Address, const void* Decoder); 418 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 419 uint64_t Address, const void *Decoder); 420 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 421 uint64_t Address, const void *Decoder); 422 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 423 uint64_t Address, const void *Decoder); 424 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 425 uint64_t Address, 426 const void *Decoder); 427 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 428 uint64_t Address, const void *Decoder); 429 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 430 uint64_t Address, const void *Decoder); 431 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 432 uint64_t Address, const void *Decoder); 433 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 434 uint64_t Address, const void *Decoder); 435 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 436 uint64_t Address, const void *Decoder); 437 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 438 uint64_t Address, const void *Decoder); 439 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 440 uint64_t Address, const void *Decoder); 441 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 442 uint64_t Address, const void *Decoder); 443 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 444 uint64_t Address, const void *Decoder); 445 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 446 uint64_t Address, const void *Decoder); 447 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 448 uint64_t Address, const void *Decoder); 449 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 450 uint64_t Address, const void *Decoder); 451 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 452 uint64_t Address, const void *Decoder); 453 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 454 uint64_t Address, const void *Decoder); 455 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 456 uint64_t Address, const void *Decoder); 457 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 458 uint64_t Address, const void *Decoder); 459 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 460 uint64_t Address, const void *Decoder); 461 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 462 uint64_t Address, const void *Decoder); 463 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 464 uint64_t Address, const void *Decoder); 465 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 466 uint64_t Address, const void *Decoder); 467 468 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 469 uint64_t Address, const void *Decoder); 470 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 471 uint64_t Address, const void *Decoder); 472 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 473 uint64_t Address, const void *Decoder); 474 475 template <bool isSigned, bool isNeg, int size> 476 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 477 uint64_t Address, const void *Decoder); 478 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 479 uint64_t Address, 480 const void *Decoder); 481 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 482 uint64_t Address, 483 const void *Decoder); 484 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 485 const void *Decoder); 486 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 487 uint64_t Address, 488 const void *Decoder); 489 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 490 const void *Decoder); 491 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 492 uint64_t Address, const void *Decoder); 493 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 494 uint64_t Address, const void *Decoder); 495 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 496 uint64_t Address, 497 const void *Decoder); 498 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 499 uint64_t Address, 500 const void *Decoder); 501 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 502 uint64_t Address, 503 const void *Decoder); 504 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 505 unsigned Val, 506 uint64_t Address, 507 const void *Decoder); 508 template<bool Writeback> 509 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 510 uint64_t Address, 511 const void *Decoder); 512 template<unsigned MinLog, unsigned MaxLog> 513 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 514 uint64_t Address, 515 const void *Decoder); 516 template <int shift> 517 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 518 uint64_t Address, 519 const void *Decoder); 520 template<unsigned start> 521 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 522 uint64_t Address, 523 const void *Decoder); 524 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 525 uint64_t Address, 526 const void *Decoder); 527 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 528 uint64_t Address, 529 const void *Decoder); 530 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 531 uint64_t Address, const void *Decoder); 532 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 533 uint64_t Address, const void *Decoder); 534 template<bool scalar, OperandDecoder predicate_decoder> 535 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 536 uint64_t Address, const void *Decoder); 537 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 538 uint64_t Address, const void *Decoder); 539 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 540 uint64_t Address, 541 const void *Decoder); 542 #include "ARMGenDisassemblerTables.inc" 543 544 static MCDisassembler *createARMDisassembler(const Target &T, 545 const MCSubtargetInfo &STI, 546 MCContext &Ctx) { 547 return new ARMDisassembler(STI, Ctx); 548 } 549 550 // Post-decoding checks 551 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 552 uint64_t Address, raw_ostream &OS, 553 raw_ostream &CS, 554 uint32_t Insn, 555 DecodeStatus Result) { 556 switch (MI.getOpcode()) { 557 case ARM::HVC: { 558 // HVC is undefined if condition = 0xf otherwise upredictable 559 // if condition != 0xe 560 uint32_t Cond = (Insn >> 28) & 0xF; 561 if (Cond == 0xF) 562 return MCDisassembler::Fail; 563 if (Cond != 0xE) 564 return MCDisassembler::SoftFail; 565 return Result; 566 } 567 case ARM::t2ADDri: 568 case ARM::t2ADDri12: 569 case ARM::t2ADDrr: 570 case ARM::t2ADDrs: 571 case ARM::t2SUBri: 572 case ARM::t2SUBri12: 573 case ARM::t2SUBrr: 574 case ARM::t2SUBrs: 575 if (MI.getOperand(0).getReg() == ARM::SP && 576 MI.getOperand(1).getReg() != ARM::SP) 577 return MCDisassembler::SoftFail; 578 return Result; 579 default: return Result; 580 } 581 } 582 583 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 584 ArrayRef<uint8_t> Bytes, 585 uint64_t Address, raw_ostream &OS, 586 raw_ostream &CS) const { 587 if (STI.getFeatureBits()[ARM::ModeThumb]) 588 return getThumbInstruction(MI, Size, Bytes, Address, OS, CS); 589 return getARMInstruction(MI, Size, Bytes, Address, OS, CS); 590 } 591 592 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 593 ArrayRef<uint8_t> Bytes, 594 uint64_t Address, 595 raw_ostream &OS, 596 raw_ostream &CS) const { 597 CommentStream = &CS; 598 599 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 600 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 601 "mode!"); 602 603 // We want to read exactly 4 bytes of data. 604 if (Bytes.size() < 4) { 605 Size = 0; 606 return MCDisassembler::Fail; 607 } 608 609 // Encoded as a small-endian 32-bit word in the stream. 610 uint32_t Insn = 611 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 612 613 // Calling the auto-generated decoder function. 614 DecodeStatus Result = 615 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 616 if (Result != MCDisassembler::Fail) { 617 Size = 4; 618 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 619 } 620 621 struct DecodeTable { 622 const uint8_t *P; 623 bool DecodePred; 624 }; 625 626 const DecodeTable Tables[] = { 627 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 628 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 629 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 630 {DecoderTablev8Crypto32, false}, 631 }; 632 633 for (auto Table : Tables) { 634 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 635 if (Result != MCDisassembler::Fail) { 636 Size = 4; 637 // Add a fake predicate operand, because we share these instruction 638 // definitions with Thumb2 where these instructions are predicable. 639 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 640 return MCDisassembler::Fail; 641 return Result; 642 } 643 } 644 645 Result = 646 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 647 if (Result != MCDisassembler::Fail) { 648 Size = 4; 649 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 650 } 651 652 Size = 4; 653 return MCDisassembler::Fail; 654 } 655 656 namespace llvm { 657 658 extern const MCInstrDesc ARMInsts[]; 659 660 } // end namespace llvm 661 662 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 663 /// immediate Value in the MCInst. The immediate Value has had any PC 664 /// adjustment made by the caller. If the instruction is a branch instruction 665 /// then isBranch is true, else false. If the getOpInfo() function was set as 666 /// part of the setupForSymbolicDisassembly() call then that function is called 667 /// to get any symbolic information at the Address for this instruction. If 668 /// that returns non-zero then the symbolic information it returns is used to 669 /// create an MCExpr and that is added as an operand to the MCInst. If 670 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 671 /// Value is done and if a symbol is found an MCExpr is created with that, else 672 /// an MCExpr with Value is created. This function returns true if it adds an 673 /// operand to the MCInst and false otherwise. 674 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 675 bool isBranch, uint64_t InstSize, 676 MCInst &MI, const void *Decoder) { 677 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 678 // FIXME: Does it make sense for value to be negative? 679 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 680 /* Offset */ 0, InstSize); 681 } 682 683 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 684 /// referenced by a load instruction with the base register that is the Pc. 685 /// These can often be values in a literal pool near the Address of the 686 /// instruction. The Address of the instruction and its immediate Value are 687 /// used as a possible literal pool entry. The SymbolLookUp call back will 688 /// return the name of a symbol referenced by the literal pool's entry if 689 /// the referenced address is that of a symbol. Or it will return a pointer to 690 /// a literal 'C' string if the referenced address of the literal pool's entry 691 /// is an address into a section with 'C' string literals. 692 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 693 const void *Decoder) { 694 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 695 Dis->tryAddingPcLoadReferenceComment(Value, Address); 696 } 697 698 // Thumb1 instructions don't have explicit S bits. Rather, they 699 // implicitly set CPSR. Since it's not represented in the encoding, the 700 // auto-generated decoder won't inject the CPSR operand. We need to fix 701 // that as a post-pass. 702 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 703 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 704 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 705 MCInst::iterator I = MI.begin(); 706 for (unsigned i = 0; i < NumOps; ++i, ++I) { 707 if (I == MI.end()) break; 708 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 709 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 710 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 711 return; 712 } 713 } 714 715 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 716 } 717 718 static bool isVectorPredicable(unsigned Opcode) { 719 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 720 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 721 for (unsigned i = 0; i < NumOps; ++i) { 722 if (ARM::isVpred(OpInfo[i].OperandType)) 723 return true; 724 } 725 return false; 726 } 727 728 // Most Thumb instructions don't have explicit predicates in the 729 // encoding, but rather get their predicates from IT context. We need 730 // to fix up the predicate operands using this context information as a 731 // post-pass. 732 MCDisassembler::DecodeStatus 733 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 734 MCDisassembler::DecodeStatus S = Success; 735 736 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 737 738 // A few instructions actually have predicates encoded in them. Don't 739 // try to overwrite it if we're seeing one of those. 740 switch (MI.getOpcode()) { 741 case ARM::tBcc: 742 case ARM::t2Bcc: 743 case ARM::tCBZ: 744 case ARM::tCBNZ: 745 case ARM::tCPS: 746 case ARM::t2CPS3p: 747 case ARM::t2CPS2p: 748 case ARM::t2CPS1p: 749 case ARM::t2CSEL: 750 case ARM::t2CSINC: 751 case ARM::t2CSINV: 752 case ARM::t2CSNEG: 753 case ARM::tMOVSr: 754 case ARM::tSETEND: 755 // Some instructions (mostly conditional branches) are not 756 // allowed in IT blocks. 757 if (ITBlock.instrInITBlock()) 758 S = SoftFail; 759 else 760 return Success; 761 break; 762 case ARM::t2HINT: 763 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 764 S = SoftFail; 765 break; 766 case ARM::tB: 767 case ARM::t2B: 768 case ARM::t2TBB: 769 case ARM::t2TBH: 770 // Some instructions (mostly unconditional branches) can 771 // only appears at the end of, or outside of, an IT. 772 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 773 S = SoftFail; 774 break; 775 default: 776 break; 777 } 778 779 // Warn on non-VPT predicable instruction in a VPT block and a VPT 780 // predicable instruction in an IT block 781 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 782 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 783 S = SoftFail; 784 785 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 786 // assume a predicate of AL. 787 unsigned CC = ARMCC::AL; 788 unsigned VCC = ARMVCC::None; 789 if (ITBlock.instrInITBlock()) { 790 CC = ITBlock.getITCC(); 791 ITBlock.advanceITState(); 792 } else if (VPTBlock.instrInVPTBlock()) { 793 VCC = VPTBlock.getVPTPred(); 794 VPTBlock.advanceVPTState(); 795 } 796 797 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 798 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 799 800 MCInst::iterator CCI = MI.begin(); 801 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 802 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 803 } 804 805 if (ARMInsts[MI.getOpcode()].isPredicable()) { 806 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 807 ++CCI; 808 if (CC == ARMCC::AL) 809 MI.insert(CCI, MCOperand::createReg(0)); 810 else 811 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 812 } else if (CC != ARMCC::AL) { 813 Check(S, SoftFail); 814 } 815 816 MCInst::iterator VCCI = MI.begin(); 817 unsigned VCCPos; 818 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 819 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 820 } 821 822 if (isVectorPredicable(MI.getOpcode())) { 823 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 824 ++VCCI; 825 if (VCC == ARMVCC::None) 826 MI.insert(VCCI, MCOperand::createReg(0)); 827 else 828 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 829 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 830 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 831 VCCPos + 2, MCOI::TIED_TO); 832 assert(TiedOp >= 0 && 833 "Inactive register in vpred_r is not tied to an output!"); 834 MI.insert(VCCI, MI.getOperand(TiedOp)); 835 } 836 } else if (VCC != ARMVCC::None) { 837 Check(S, SoftFail); 838 } 839 840 return S; 841 } 842 843 // Thumb VFP instructions are a special case. Because we share their 844 // encodings between ARM and Thumb modes, and they are predicable in ARM 845 // mode, the auto-generated decoder will give them an (incorrect) 846 // predicate operand. We need to rewrite these operands based on the IT 847 // context as a post-pass. 848 void ARMDisassembler::UpdateThumbVFPPredicate( 849 DecodeStatus &S, MCInst &MI) const { 850 unsigned CC; 851 CC = ITBlock.getITCC(); 852 if (CC == 0xF) 853 CC = ARMCC::AL; 854 if (ITBlock.instrInITBlock()) 855 ITBlock.advanceITState(); 856 else if (VPTBlock.instrInVPTBlock()) { 857 CC = VPTBlock.getVPTPred(); 858 VPTBlock.advanceVPTState(); 859 } 860 861 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 862 MCInst::iterator I = MI.begin(); 863 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 864 for (unsigned i = 0; i < NumOps; ++i, ++I) { 865 if (OpInfo[i].isPredicate() ) { 866 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 867 Check(S, SoftFail); 868 I->setImm(CC); 869 ++I; 870 if (CC == ARMCC::AL) 871 I->setReg(0); 872 else 873 I->setReg(ARM::CPSR); 874 return; 875 } 876 } 877 } 878 879 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 880 ArrayRef<uint8_t> Bytes, 881 uint64_t Address, 882 raw_ostream &OS, 883 raw_ostream &CS) const { 884 CommentStream = &CS; 885 886 assert(STI.getFeatureBits()[ARM::ModeThumb] && 887 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 888 889 // We want to read exactly 2 bytes of data. 890 if (Bytes.size() < 2) { 891 Size = 0; 892 return MCDisassembler::Fail; 893 } 894 895 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 896 DecodeStatus Result = 897 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 898 if (Result != MCDisassembler::Fail) { 899 Size = 2; 900 Check(Result, AddThumbPredicate(MI)); 901 return Result; 902 } 903 904 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 905 STI); 906 if (Result) { 907 Size = 2; 908 bool InITBlock = ITBlock.instrInITBlock(); 909 Check(Result, AddThumbPredicate(MI)); 910 AddThumb1SBit(MI, InITBlock); 911 return Result; 912 } 913 914 Result = 915 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 916 if (Result != MCDisassembler::Fail) { 917 Size = 2; 918 919 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 920 // the Thumb predicate. 921 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 922 Result = MCDisassembler::SoftFail; 923 924 Check(Result, AddThumbPredicate(MI)); 925 926 // If we find an IT instruction, we need to parse its condition 927 // code and mask operands so that we can apply them correctly 928 // to the subsequent instructions. 929 if (MI.getOpcode() == ARM::t2IT) { 930 unsigned Firstcond = MI.getOperand(0).getImm(); 931 unsigned Mask = MI.getOperand(1).getImm(); 932 ITBlock.setITState(Firstcond, Mask); 933 934 // An IT instruction that would give a 'NV' predicate is unpredictable. 935 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 936 CS << "unpredictable IT predicate sequence"; 937 } 938 939 return Result; 940 } 941 942 // We want to read exactly 4 bytes of data. 943 if (Bytes.size() < 4) { 944 Size = 0; 945 return MCDisassembler::Fail; 946 } 947 948 uint32_t Insn32 = 949 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 950 951 Result = 952 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 953 if (Result != MCDisassembler::Fail) { 954 Size = 4; 955 956 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 957 // the VPT predicate. 958 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 959 Result = MCDisassembler::SoftFail; 960 961 Check(Result, AddThumbPredicate(MI)); 962 963 if (isVPTOpcode(MI.getOpcode())) { 964 unsigned Mask = MI.getOperand(0).getImm(); 965 VPTBlock.setVPTState(Mask); 966 } 967 968 return Result; 969 } 970 971 Result = 972 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 973 if (Result != MCDisassembler::Fail) { 974 Size = 4; 975 bool InITBlock = ITBlock.instrInITBlock(); 976 Check(Result, AddThumbPredicate(MI)); 977 AddThumb1SBit(MI, InITBlock); 978 return Result; 979 } 980 981 Result = 982 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 983 if (Result != MCDisassembler::Fail) { 984 Size = 4; 985 Check(Result, AddThumbPredicate(MI)); 986 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 987 } 988 989 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 990 Result = 991 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 992 if (Result != MCDisassembler::Fail) { 993 Size = 4; 994 UpdateThumbVFPPredicate(Result, MI); 995 return Result; 996 } 997 } 998 999 Result = 1000 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1001 if (Result != MCDisassembler::Fail) { 1002 Size = 4; 1003 return Result; 1004 } 1005 1006 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1007 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1008 STI); 1009 if (Result != MCDisassembler::Fail) { 1010 Size = 4; 1011 Check(Result, AddThumbPredicate(MI)); 1012 return Result; 1013 } 1014 } 1015 1016 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1017 uint32_t NEONLdStInsn = Insn32; 1018 NEONLdStInsn &= 0xF0FFFFFF; 1019 NEONLdStInsn |= 0x04000000; 1020 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1021 Address, this, STI); 1022 if (Result != MCDisassembler::Fail) { 1023 Size = 4; 1024 Check(Result, AddThumbPredicate(MI)); 1025 return Result; 1026 } 1027 } 1028 1029 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1030 uint32_t NEONDataInsn = Insn32; 1031 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1032 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1033 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1034 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1035 Address, this, STI); 1036 if (Result != MCDisassembler::Fail) { 1037 Size = 4; 1038 Check(Result, AddThumbPredicate(MI)); 1039 return Result; 1040 } 1041 1042 uint32_t NEONCryptoInsn = Insn32; 1043 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1044 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1045 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1046 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1047 Address, this, STI); 1048 if (Result != MCDisassembler::Fail) { 1049 Size = 4; 1050 return Result; 1051 } 1052 1053 uint32_t NEONv8Insn = Insn32; 1054 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1055 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1056 this, STI); 1057 if (Result != MCDisassembler::Fail) { 1058 Size = 4; 1059 return Result; 1060 } 1061 } 1062 1063 Result = 1064 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1065 if (Result != MCDisassembler::Fail) { 1066 Size = 4; 1067 Check(Result, AddThumbPredicate(MI)); 1068 return Result; 1069 } 1070 1071 Size = 0; 1072 return MCDisassembler::Fail; 1073 } 1074 1075 extern "C" void LLVMInitializeARMDisassembler() { 1076 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1077 createARMDisassembler); 1078 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1079 createARMDisassembler); 1080 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1081 createARMDisassembler); 1082 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1083 createARMDisassembler); 1084 } 1085 1086 static const uint16_t GPRDecoderTable[] = { 1087 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1088 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1089 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1090 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1091 }; 1092 1093 static const uint16_t CLRMGPRDecoderTable[] = { 1094 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1095 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1096 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1097 ARM::R12, 0, ARM::LR, ARM::APSR 1098 }; 1099 1100 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1101 uint64_t Address, const void *Decoder) { 1102 if (RegNo > 15) 1103 return MCDisassembler::Fail; 1104 1105 unsigned Register = GPRDecoderTable[RegNo]; 1106 Inst.addOperand(MCOperand::createReg(Register)); 1107 return MCDisassembler::Success; 1108 } 1109 1110 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1111 uint64_t Address, 1112 const void *Decoder) { 1113 if (RegNo > 15) 1114 return MCDisassembler::Fail; 1115 1116 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1117 if (Register == 0) 1118 return MCDisassembler::Fail; 1119 1120 Inst.addOperand(MCOperand::createReg(Register)); 1121 return MCDisassembler::Success; 1122 } 1123 1124 static DecodeStatus 1125 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1126 uint64_t Address, const void *Decoder) { 1127 DecodeStatus S = MCDisassembler::Success; 1128 1129 if (RegNo == 15) 1130 S = MCDisassembler::SoftFail; 1131 1132 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1133 1134 return S; 1135 } 1136 1137 static DecodeStatus 1138 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1139 uint64_t Address, const void *Decoder) { 1140 DecodeStatus S = MCDisassembler::Success; 1141 1142 if (RegNo == 15) 1143 { 1144 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1145 return MCDisassembler::Success; 1146 } 1147 1148 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1149 return S; 1150 } 1151 1152 static DecodeStatus 1153 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1154 uint64_t Address, const void *Decoder) { 1155 DecodeStatus S = MCDisassembler::Success; 1156 1157 if (RegNo == 15) 1158 { 1159 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1160 return MCDisassembler::Success; 1161 } 1162 1163 if (RegNo == 13) 1164 S = MCDisassembler::SoftFail; 1165 1166 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1167 return S; 1168 } 1169 1170 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1171 uint64_t Address, const void *Decoder) { 1172 if (RegNo > 7) 1173 return MCDisassembler::Fail; 1174 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1175 } 1176 1177 static const uint16_t GPRPairDecoderTable[] = { 1178 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1179 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1180 }; 1181 1182 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1183 uint64_t Address, const void *Decoder) { 1184 DecodeStatus S = MCDisassembler::Success; 1185 1186 if (RegNo > 13) 1187 return MCDisassembler::Fail; 1188 1189 if ((RegNo & 1) || RegNo == 0xe) 1190 S = MCDisassembler::SoftFail; 1191 1192 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1193 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1194 return S; 1195 } 1196 1197 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1198 uint64_t Address, const void *Decoder) { 1199 unsigned Register = 0; 1200 switch (RegNo) { 1201 case 0: 1202 Register = ARM::R0; 1203 break; 1204 case 1: 1205 Register = ARM::R1; 1206 break; 1207 case 2: 1208 Register = ARM::R2; 1209 break; 1210 case 3: 1211 Register = ARM::R3; 1212 break; 1213 case 9: 1214 Register = ARM::R9; 1215 break; 1216 case 12: 1217 Register = ARM::R12; 1218 break; 1219 default: 1220 return MCDisassembler::Fail; 1221 } 1222 1223 Inst.addOperand(MCOperand::createReg(Register)); 1224 return MCDisassembler::Success; 1225 } 1226 1227 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1228 uint64_t Address, const void *Decoder) { 1229 DecodeStatus S = MCDisassembler::Success; 1230 1231 const FeatureBitset &featureBits = 1232 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1233 1234 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1235 S = MCDisassembler::SoftFail; 1236 1237 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1238 return S; 1239 } 1240 1241 static const uint16_t SPRDecoderTable[] = { 1242 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1243 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1244 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1245 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1246 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1247 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1248 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1249 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1250 }; 1251 1252 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1253 uint64_t Address, const void *Decoder) { 1254 if (RegNo > 31) 1255 return MCDisassembler::Fail; 1256 1257 unsigned Register = SPRDecoderTable[RegNo]; 1258 Inst.addOperand(MCOperand::createReg(Register)); 1259 return MCDisassembler::Success; 1260 } 1261 1262 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1263 uint64_t Address, const void *Decoder) { 1264 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1265 } 1266 1267 static const uint16_t DPRDecoderTable[] = { 1268 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1269 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1270 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1271 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1272 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1273 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1274 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1275 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1276 }; 1277 1278 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1279 uint64_t Address, const void *Decoder) { 1280 const FeatureBitset &featureBits = 1281 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1282 1283 bool hasD32 = featureBits[ARM::FeatureD32]; 1284 1285 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1286 return MCDisassembler::Fail; 1287 1288 unsigned Register = DPRDecoderTable[RegNo]; 1289 Inst.addOperand(MCOperand::createReg(Register)); 1290 return MCDisassembler::Success; 1291 } 1292 1293 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1294 uint64_t Address, const void *Decoder) { 1295 if (RegNo > 7) 1296 return MCDisassembler::Fail; 1297 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1298 } 1299 1300 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1301 uint64_t Address, const void *Decoder) { 1302 if (RegNo > 15) 1303 return MCDisassembler::Fail; 1304 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1305 } 1306 1307 static DecodeStatus 1308 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1309 uint64_t Address, const void *Decoder) { 1310 if (RegNo > 15) 1311 return MCDisassembler::Fail; 1312 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1313 } 1314 1315 static const uint16_t QPRDecoderTable[] = { 1316 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1317 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1318 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1319 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1320 }; 1321 1322 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1323 uint64_t Address, const void *Decoder) { 1324 if (RegNo > 31 || (RegNo & 1) != 0) 1325 return MCDisassembler::Fail; 1326 RegNo >>= 1; 1327 1328 unsigned Register = QPRDecoderTable[RegNo]; 1329 Inst.addOperand(MCOperand::createReg(Register)); 1330 return MCDisassembler::Success; 1331 } 1332 1333 static const uint16_t DPairDecoderTable[] = { 1334 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1335 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1336 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1337 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1338 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1339 ARM::Q15 1340 }; 1341 1342 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1343 uint64_t Address, const void *Decoder) { 1344 if (RegNo > 30) 1345 return MCDisassembler::Fail; 1346 1347 unsigned Register = DPairDecoderTable[RegNo]; 1348 Inst.addOperand(MCOperand::createReg(Register)); 1349 return MCDisassembler::Success; 1350 } 1351 1352 static const uint16_t DPairSpacedDecoderTable[] = { 1353 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1354 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1355 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1356 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1357 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1358 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1359 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1360 ARM::D28_D30, ARM::D29_D31 1361 }; 1362 1363 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1364 unsigned RegNo, 1365 uint64_t Address, 1366 const void *Decoder) { 1367 if (RegNo > 29) 1368 return MCDisassembler::Fail; 1369 1370 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1371 Inst.addOperand(MCOperand::createReg(Register)); 1372 return MCDisassembler::Success; 1373 } 1374 1375 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1376 uint64_t Address, const void *Decoder) { 1377 DecodeStatus S = MCDisassembler::Success; 1378 if (Val == 0xF) return MCDisassembler::Fail; 1379 // AL predicate is not allowed on Thumb1 branches. 1380 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1381 return MCDisassembler::Fail; 1382 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1383 Check(S, MCDisassembler::SoftFail); 1384 Inst.addOperand(MCOperand::createImm(Val)); 1385 if (Val == ARMCC::AL) { 1386 Inst.addOperand(MCOperand::createReg(0)); 1387 } else 1388 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1389 return S; 1390 } 1391 1392 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1393 uint64_t Address, const void *Decoder) { 1394 if (Val) 1395 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1396 else 1397 Inst.addOperand(MCOperand::createReg(0)); 1398 return MCDisassembler::Success; 1399 } 1400 1401 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1402 uint64_t Address, const void *Decoder) { 1403 DecodeStatus S = MCDisassembler::Success; 1404 1405 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1406 unsigned type = fieldFromInstruction(Val, 5, 2); 1407 unsigned imm = fieldFromInstruction(Val, 7, 5); 1408 1409 // Register-immediate 1410 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1411 return MCDisassembler::Fail; 1412 1413 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1414 switch (type) { 1415 case 0: 1416 Shift = ARM_AM::lsl; 1417 break; 1418 case 1: 1419 Shift = ARM_AM::lsr; 1420 break; 1421 case 2: 1422 Shift = ARM_AM::asr; 1423 break; 1424 case 3: 1425 Shift = ARM_AM::ror; 1426 break; 1427 } 1428 1429 if (Shift == ARM_AM::ror && imm == 0) 1430 Shift = ARM_AM::rrx; 1431 1432 unsigned Op = Shift | (imm << 3); 1433 Inst.addOperand(MCOperand::createImm(Op)); 1434 1435 return S; 1436 } 1437 1438 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1439 uint64_t Address, const void *Decoder) { 1440 DecodeStatus S = MCDisassembler::Success; 1441 1442 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1443 unsigned type = fieldFromInstruction(Val, 5, 2); 1444 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1445 1446 // Register-register 1447 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1448 return MCDisassembler::Fail; 1449 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1450 return MCDisassembler::Fail; 1451 1452 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1453 switch (type) { 1454 case 0: 1455 Shift = ARM_AM::lsl; 1456 break; 1457 case 1: 1458 Shift = ARM_AM::lsr; 1459 break; 1460 case 2: 1461 Shift = ARM_AM::asr; 1462 break; 1463 case 3: 1464 Shift = ARM_AM::ror; 1465 break; 1466 } 1467 1468 Inst.addOperand(MCOperand::createImm(Shift)); 1469 1470 return S; 1471 } 1472 1473 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1474 uint64_t Address, const void *Decoder) { 1475 DecodeStatus S = MCDisassembler::Success; 1476 1477 bool NeedDisjointWriteback = false; 1478 unsigned WritebackReg = 0; 1479 bool CLRM = false; 1480 switch (Inst.getOpcode()) { 1481 default: 1482 break; 1483 case ARM::LDMIA_UPD: 1484 case ARM::LDMDB_UPD: 1485 case ARM::LDMIB_UPD: 1486 case ARM::LDMDA_UPD: 1487 case ARM::t2LDMIA_UPD: 1488 case ARM::t2LDMDB_UPD: 1489 case ARM::t2STMIA_UPD: 1490 case ARM::t2STMDB_UPD: 1491 NeedDisjointWriteback = true; 1492 WritebackReg = Inst.getOperand(0).getReg(); 1493 break; 1494 case ARM::t2CLRM: 1495 CLRM = true; 1496 break; 1497 } 1498 1499 // Empty register lists are not allowed. 1500 if (Val == 0) return MCDisassembler::Fail; 1501 for (unsigned i = 0; i < 16; ++i) { 1502 if (Val & (1 << i)) { 1503 if (CLRM) { 1504 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1505 return MCDisassembler::Fail; 1506 } 1507 } else { 1508 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1509 return MCDisassembler::Fail; 1510 // Writeback not allowed if Rn is in the target list. 1511 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1512 Check(S, MCDisassembler::SoftFail); 1513 } 1514 } 1515 } 1516 1517 return S; 1518 } 1519 1520 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1521 uint64_t Address, const void *Decoder) { 1522 DecodeStatus S = MCDisassembler::Success; 1523 1524 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1525 unsigned regs = fieldFromInstruction(Val, 0, 8); 1526 1527 // In case of unpredictable encoding, tweak the operands. 1528 if (regs == 0 || (Vd + regs) > 32) { 1529 regs = Vd + regs > 32 ? 32 - Vd : regs; 1530 regs = std::max( 1u, regs); 1531 S = MCDisassembler::SoftFail; 1532 } 1533 1534 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1535 return MCDisassembler::Fail; 1536 for (unsigned i = 0; i < (regs - 1); ++i) { 1537 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1538 return MCDisassembler::Fail; 1539 } 1540 1541 return S; 1542 } 1543 1544 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1545 uint64_t Address, const void *Decoder) { 1546 DecodeStatus S = MCDisassembler::Success; 1547 1548 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1549 unsigned regs = fieldFromInstruction(Val, 1, 7); 1550 1551 // In case of unpredictable encoding, tweak the operands. 1552 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1553 regs = Vd + regs > 32 ? 32 - Vd : regs; 1554 regs = std::max( 1u, regs); 1555 regs = std::min(16u, regs); 1556 S = MCDisassembler::SoftFail; 1557 } 1558 1559 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1560 return MCDisassembler::Fail; 1561 for (unsigned i = 0; i < (regs - 1); ++i) { 1562 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1563 return MCDisassembler::Fail; 1564 } 1565 1566 return S; 1567 } 1568 1569 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1570 uint64_t Address, const void *Decoder) { 1571 // This operand encodes a mask of contiguous zeros between a specified MSB 1572 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1573 // the mask of all bits LSB-and-lower, and then xor them to create 1574 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1575 // create the final mask. 1576 unsigned msb = fieldFromInstruction(Val, 5, 5); 1577 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1578 1579 DecodeStatus S = MCDisassembler::Success; 1580 if (lsb > msb) { 1581 Check(S, MCDisassembler::SoftFail); 1582 // The check above will cause the warning for the "potentially undefined 1583 // instruction encoding" but we can't build a bad MCOperand value here 1584 // with a lsb > msb or else printing the MCInst will cause a crash. 1585 lsb = msb; 1586 } 1587 1588 uint32_t msb_mask = 0xFFFFFFFF; 1589 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1590 uint32_t lsb_mask = (1U << lsb) - 1; 1591 1592 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1593 return S; 1594 } 1595 1596 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1597 uint64_t Address, const void *Decoder) { 1598 DecodeStatus S = MCDisassembler::Success; 1599 1600 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1601 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1602 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1603 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1604 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1605 unsigned U = fieldFromInstruction(Insn, 23, 1); 1606 const FeatureBitset &featureBits = 1607 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1608 1609 switch (Inst.getOpcode()) { 1610 case ARM::LDC_OFFSET: 1611 case ARM::LDC_PRE: 1612 case ARM::LDC_POST: 1613 case ARM::LDC_OPTION: 1614 case ARM::LDCL_OFFSET: 1615 case ARM::LDCL_PRE: 1616 case ARM::LDCL_POST: 1617 case ARM::LDCL_OPTION: 1618 case ARM::STC_OFFSET: 1619 case ARM::STC_PRE: 1620 case ARM::STC_POST: 1621 case ARM::STC_OPTION: 1622 case ARM::STCL_OFFSET: 1623 case ARM::STCL_PRE: 1624 case ARM::STCL_POST: 1625 case ARM::STCL_OPTION: 1626 case ARM::t2LDC_OFFSET: 1627 case ARM::t2LDC_PRE: 1628 case ARM::t2LDC_POST: 1629 case ARM::t2LDC_OPTION: 1630 case ARM::t2LDCL_OFFSET: 1631 case ARM::t2LDCL_PRE: 1632 case ARM::t2LDCL_POST: 1633 case ARM::t2LDCL_OPTION: 1634 case ARM::t2STC_OFFSET: 1635 case ARM::t2STC_PRE: 1636 case ARM::t2STC_POST: 1637 case ARM::t2STC_OPTION: 1638 case ARM::t2STCL_OFFSET: 1639 case ARM::t2STCL_PRE: 1640 case ARM::t2STCL_POST: 1641 case ARM::t2STCL_OPTION: 1642 case ARM::t2LDC2_OFFSET: 1643 case ARM::t2LDC2L_OFFSET: 1644 case ARM::t2LDC2_PRE: 1645 case ARM::t2LDC2L_PRE: 1646 case ARM::t2STC2_OFFSET: 1647 case ARM::t2STC2L_OFFSET: 1648 case ARM::t2STC2_PRE: 1649 case ARM::t2STC2L_PRE: 1650 case ARM::LDC2_OFFSET: 1651 case ARM::LDC2L_OFFSET: 1652 case ARM::LDC2_PRE: 1653 case ARM::LDC2L_PRE: 1654 case ARM::STC2_OFFSET: 1655 case ARM::STC2L_OFFSET: 1656 case ARM::STC2_PRE: 1657 case ARM::STC2L_PRE: 1658 case ARM::t2LDC2_OPTION: 1659 case ARM::t2STC2_OPTION: 1660 case ARM::t2LDC2_POST: 1661 case ARM::t2LDC2L_POST: 1662 case ARM::t2STC2_POST: 1663 case ARM::t2STC2L_POST: 1664 case ARM::LDC2_POST: 1665 case ARM::LDC2L_POST: 1666 case ARM::STC2_POST: 1667 case ARM::STC2L_POST: 1668 if (coproc == 0xA || coproc == 0xB || 1669 (featureBits[ARM::HasV8_1MMainlineOps] && 1670 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1671 coproc == 0xE || coproc == 0xF))) 1672 return MCDisassembler::Fail; 1673 break; 1674 default: 1675 break; 1676 } 1677 1678 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1679 return MCDisassembler::Fail; 1680 1681 Inst.addOperand(MCOperand::createImm(coproc)); 1682 Inst.addOperand(MCOperand::createImm(CRd)); 1683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1684 return MCDisassembler::Fail; 1685 1686 switch (Inst.getOpcode()) { 1687 case ARM::t2LDC2_OFFSET: 1688 case ARM::t2LDC2L_OFFSET: 1689 case ARM::t2LDC2_PRE: 1690 case ARM::t2LDC2L_PRE: 1691 case ARM::t2STC2_OFFSET: 1692 case ARM::t2STC2L_OFFSET: 1693 case ARM::t2STC2_PRE: 1694 case ARM::t2STC2L_PRE: 1695 case ARM::LDC2_OFFSET: 1696 case ARM::LDC2L_OFFSET: 1697 case ARM::LDC2_PRE: 1698 case ARM::LDC2L_PRE: 1699 case ARM::STC2_OFFSET: 1700 case ARM::STC2L_OFFSET: 1701 case ARM::STC2_PRE: 1702 case ARM::STC2L_PRE: 1703 case ARM::t2LDC_OFFSET: 1704 case ARM::t2LDCL_OFFSET: 1705 case ARM::t2LDC_PRE: 1706 case ARM::t2LDCL_PRE: 1707 case ARM::t2STC_OFFSET: 1708 case ARM::t2STCL_OFFSET: 1709 case ARM::t2STC_PRE: 1710 case ARM::t2STCL_PRE: 1711 case ARM::LDC_OFFSET: 1712 case ARM::LDCL_OFFSET: 1713 case ARM::LDC_PRE: 1714 case ARM::LDCL_PRE: 1715 case ARM::STC_OFFSET: 1716 case ARM::STCL_OFFSET: 1717 case ARM::STC_PRE: 1718 case ARM::STCL_PRE: 1719 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1720 Inst.addOperand(MCOperand::createImm(imm)); 1721 break; 1722 case ARM::t2LDC2_POST: 1723 case ARM::t2LDC2L_POST: 1724 case ARM::t2STC2_POST: 1725 case ARM::t2STC2L_POST: 1726 case ARM::LDC2_POST: 1727 case ARM::LDC2L_POST: 1728 case ARM::STC2_POST: 1729 case ARM::STC2L_POST: 1730 case ARM::t2LDC_POST: 1731 case ARM::t2LDCL_POST: 1732 case ARM::t2STC_POST: 1733 case ARM::t2STCL_POST: 1734 case ARM::LDC_POST: 1735 case ARM::LDCL_POST: 1736 case ARM::STC_POST: 1737 case ARM::STCL_POST: 1738 imm |= U << 8; 1739 LLVM_FALLTHROUGH; 1740 default: 1741 // The 'option' variant doesn't encode 'U' in the immediate since 1742 // the immediate is unsigned [0,255]. 1743 Inst.addOperand(MCOperand::createImm(imm)); 1744 break; 1745 } 1746 1747 switch (Inst.getOpcode()) { 1748 case ARM::LDC_OFFSET: 1749 case ARM::LDC_PRE: 1750 case ARM::LDC_POST: 1751 case ARM::LDC_OPTION: 1752 case ARM::LDCL_OFFSET: 1753 case ARM::LDCL_PRE: 1754 case ARM::LDCL_POST: 1755 case ARM::LDCL_OPTION: 1756 case ARM::STC_OFFSET: 1757 case ARM::STC_PRE: 1758 case ARM::STC_POST: 1759 case ARM::STC_OPTION: 1760 case ARM::STCL_OFFSET: 1761 case ARM::STCL_PRE: 1762 case ARM::STCL_POST: 1763 case ARM::STCL_OPTION: 1764 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1765 return MCDisassembler::Fail; 1766 break; 1767 default: 1768 break; 1769 } 1770 1771 return S; 1772 } 1773 1774 static DecodeStatus 1775 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1776 uint64_t Address, const void *Decoder) { 1777 DecodeStatus S = MCDisassembler::Success; 1778 1779 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1780 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1781 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1782 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1783 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1784 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1785 unsigned P = fieldFromInstruction(Insn, 24, 1); 1786 unsigned W = fieldFromInstruction(Insn, 21, 1); 1787 1788 // On stores, the writeback operand precedes Rt. 1789 switch (Inst.getOpcode()) { 1790 case ARM::STR_POST_IMM: 1791 case ARM::STR_POST_REG: 1792 case ARM::STRB_POST_IMM: 1793 case ARM::STRB_POST_REG: 1794 case ARM::STRT_POST_REG: 1795 case ARM::STRT_POST_IMM: 1796 case ARM::STRBT_POST_REG: 1797 case ARM::STRBT_POST_IMM: 1798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1799 return MCDisassembler::Fail; 1800 break; 1801 default: 1802 break; 1803 } 1804 1805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1806 return MCDisassembler::Fail; 1807 1808 // On loads, the writeback operand comes after Rt. 1809 switch (Inst.getOpcode()) { 1810 case ARM::LDR_POST_IMM: 1811 case ARM::LDR_POST_REG: 1812 case ARM::LDRB_POST_IMM: 1813 case ARM::LDRB_POST_REG: 1814 case ARM::LDRBT_POST_REG: 1815 case ARM::LDRBT_POST_IMM: 1816 case ARM::LDRT_POST_REG: 1817 case ARM::LDRT_POST_IMM: 1818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1819 return MCDisassembler::Fail; 1820 break; 1821 default: 1822 break; 1823 } 1824 1825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1826 return MCDisassembler::Fail; 1827 1828 ARM_AM::AddrOpc Op = ARM_AM::add; 1829 if (!fieldFromInstruction(Insn, 23, 1)) 1830 Op = ARM_AM::sub; 1831 1832 bool writeback = (P == 0) || (W == 1); 1833 unsigned idx_mode = 0; 1834 if (P && writeback) 1835 idx_mode = ARMII::IndexModePre; 1836 else if (!P && writeback) 1837 idx_mode = ARMII::IndexModePost; 1838 1839 if (writeback && (Rn == 15 || Rn == Rt)) 1840 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1841 1842 if (reg) { 1843 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1844 return MCDisassembler::Fail; 1845 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1846 switch( fieldFromInstruction(Insn, 5, 2)) { 1847 case 0: 1848 Opc = ARM_AM::lsl; 1849 break; 1850 case 1: 1851 Opc = ARM_AM::lsr; 1852 break; 1853 case 2: 1854 Opc = ARM_AM::asr; 1855 break; 1856 case 3: 1857 Opc = ARM_AM::ror; 1858 break; 1859 default: 1860 return MCDisassembler::Fail; 1861 } 1862 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1863 if (Opc == ARM_AM::ror && amt == 0) 1864 Opc = ARM_AM::rrx; 1865 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1866 1867 Inst.addOperand(MCOperand::createImm(imm)); 1868 } else { 1869 Inst.addOperand(MCOperand::createReg(0)); 1870 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1871 Inst.addOperand(MCOperand::createImm(tmp)); 1872 } 1873 1874 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1875 return MCDisassembler::Fail; 1876 1877 return S; 1878 } 1879 1880 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1881 uint64_t Address, const void *Decoder) { 1882 DecodeStatus S = MCDisassembler::Success; 1883 1884 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1885 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1886 unsigned type = fieldFromInstruction(Val, 5, 2); 1887 unsigned imm = fieldFromInstruction(Val, 7, 5); 1888 unsigned U = fieldFromInstruction(Val, 12, 1); 1889 1890 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1891 switch (type) { 1892 case 0: 1893 ShOp = ARM_AM::lsl; 1894 break; 1895 case 1: 1896 ShOp = ARM_AM::lsr; 1897 break; 1898 case 2: 1899 ShOp = ARM_AM::asr; 1900 break; 1901 case 3: 1902 ShOp = ARM_AM::ror; 1903 break; 1904 } 1905 1906 if (ShOp == ARM_AM::ror && imm == 0) 1907 ShOp = ARM_AM::rrx; 1908 1909 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1910 return MCDisassembler::Fail; 1911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1912 return MCDisassembler::Fail; 1913 unsigned shift; 1914 if (U) 1915 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1916 else 1917 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1918 Inst.addOperand(MCOperand::createImm(shift)); 1919 1920 return S; 1921 } 1922 1923 static DecodeStatus 1924 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1925 uint64_t Address, const void *Decoder) { 1926 DecodeStatus S = MCDisassembler::Success; 1927 1928 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1929 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1930 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1931 unsigned type = fieldFromInstruction(Insn, 22, 1); 1932 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1933 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1934 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1935 unsigned W = fieldFromInstruction(Insn, 21, 1); 1936 unsigned P = fieldFromInstruction(Insn, 24, 1); 1937 unsigned Rt2 = Rt + 1; 1938 1939 bool writeback = (W == 1) | (P == 0); 1940 1941 // For {LD,ST}RD, Rt must be even, else undefined. 1942 switch (Inst.getOpcode()) { 1943 case ARM::STRD: 1944 case ARM::STRD_PRE: 1945 case ARM::STRD_POST: 1946 case ARM::LDRD: 1947 case ARM::LDRD_PRE: 1948 case ARM::LDRD_POST: 1949 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1950 break; 1951 default: 1952 break; 1953 } 1954 switch (Inst.getOpcode()) { 1955 case ARM::STRD: 1956 case ARM::STRD_PRE: 1957 case ARM::STRD_POST: 1958 if (P == 0 && W == 1) 1959 S = MCDisassembler::SoftFail; 1960 1961 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1962 S = MCDisassembler::SoftFail; 1963 if (type && Rm == 15) 1964 S = MCDisassembler::SoftFail; 1965 if (Rt2 == 15) 1966 S = MCDisassembler::SoftFail; 1967 if (!type && fieldFromInstruction(Insn, 8, 4)) 1968 S = MCDisassembler::SoftFail; 1969 break; 1970 case ARM::STRH: 1971 case ARM::STRH_PRE: 1972 case ARM::STRH_POST: 1973 if (Rt == 15) 1974 S = MCDisassembler::SoftFail; 1975 if (writeback && (Rn == 15 || Rn == Rt)) 1976 S = MCDisassembler::SoftFail; 1977 if (!type && Rm == 15) 1978 S = MCDisassembler::SoftFail; 1979 break; 1980 case ARM::LDRD: 1981 case ARM::LDRD_PRE: 1982 case ARM::LDRD_POST: 1983 if (type && Rn == 15) { 1984 if (Rt2 == 15) 1985 S = MCDisassembler::SoftFail; 1986 break; 1987 } 1988 if (P == 0 && W == 1) 1989 S = MCDisassembler::SoftFail; 1990 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1991 S = MCDisassembler::SoftFail; 1992 if (!type && writeback && Rn == 15) 1993 S = MCDisassembler::SoftFail; 1994 if (writeback && (Rn == Rt || Rn == Rt2)) 1995 S = MCDisassembler::SoftFail; 1996 break; 1997 case ARM::LDRH: 1998 case ARM::LDRH_PRE: 1999 case ARM::LDRH_POST: 2000 if (type && Rn == 15) { 2001 if (Rt == 15) 2002 S = MCDisassembler::SoftFail; 2003 break; 2004 } 2005 if (Rt == 15) 2006 S = MCDisassembler::SoftFail; 2007 if (!type && Rm == 15) 2008 S = MCDisassembler::SoftFail; 2009 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2010 S = MCDisassembler::SoftFail; 2011 break; 2012 case ARM::LDRSH: 2013 case ARM::LDRSH_PRE: 2014 case ARM::LDRSH_POST: 2015 case ARM::LDRSB: 2016 case ARM::LDRSB_PRE: 2017 case ARM::LDRSB_POST: 2018 if (type && Rn == 15) { 2019 if (Rt == 15) 2020 S = MCDisassembler::SoftFail; 2021 break; 2022 } 2023 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2024 S = MCDisassembler::SoftFail; 2025 if (!type && (Rt == 15 || Rm == 15)) 2026 S = MCDisassembler::SoftFail; 2027 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2028 S = MCDisassembler::SoftFail; 2029 break; 2030 default: 2031 break; 2032 } 2033 2034 if (writeback) { // Writeback 2035 if (P) 2036 U |= ARMII::IndexModePre << 9; 2037 else 2038 U |= ARMII::IndexModePost << 9; 2039 2040 // On stores, the writeback operand precedes Rt. 2041 switch (Inst.getOpcode()) { 2042 case ARM::STRD: 2043 case ARM::STRD_PRE: 2044 case ARM::STRD_POST: 2045 case ARM::STRH: 2046 case ARM::STRH_PRE: 2047 case ARM::STRH_POST: 2048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2049 return MCDisassembler::Fail; 2050 break; 2051 default: 2052 break; 2053 } 2054 } 2055 2056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2057 return MCDisassembler::Fail; 2058 switch (Inst.getOpcode()) { 2059 case ARM::STRD: 2060 case ARM::STRD_PRE: 2061 case ARM::STRD_POST: 2062 case ARM::LDRD: 2063 case ARM::LDRD_PRE: 2064 case ARM::LDRD_POST: 2065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2066 return MCDisassembler::Fail; 2067 break; 2068 default: 2069 break; 2070 } 2071 2072 if (writeback) { 2073 // On loads, the writeback operand comes after Rt. 2074 switch (Inst.getOpcode()) { 2075 case ARM::LDRD: 2076 case ARM::LDRD_PRE: 2077 case ARM::LDRD_POST: 2078 case ARM::LDRH: 2079 case ARM::LDRH_PRE: 2080 case ARM::LDRH_POST: 2081 case ARM::LDRSH: 2082 case ARM::LDRSH_PRE: 2083 case ARM::LDRSH_POST: 2084 case ARM::LDRSB: 2085 case ARM::LDRSB_PRE: 2086 case ARM::LDRSB_POST: 2087 case ARM::LDRHTr: 2088 case ARM::LDRSBTr: 2089 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2090 return MCDisassembler::Fail; 2091 break; 2092 default: 2093 break; 2094 } 2095 } 2096 2097 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2098 return MCDisassembler::Fail; 2099 2100 if (type) { 2101 Inst.addOperand(MCOperand::createReg(0)); 2102 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2103 } else { 2104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2105 return MCDisassembler::Fail; 2106 Inst.addOperand(MCOperand::createImm(U)); 2107 } 2108 2109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 2112 return S; 2113 } 2114 2115 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2116 uint64_t Address, const void *Decoder) { 2117 DecodeStatus S = MCDisassembler::Success; 2118 2119 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2120 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2121 2122 switch (mode) { 2123 case 0: 2124 mode = ARM_AM::da; 2125 break; 2126 case 1: 2127 mode = ARM_AM::ia; 2128 break; 2129 case 2: 2130 mode = ARM_AM::db; 2131 break; 2132 case 3: 2133 mode = ARM_AM::ib; 2134 break; 2135 } 2136 2137 Inst.addOperand(MCOperand::createImm(mode)); 2138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2139 return MCDisassembler::Fail; 2140 2141 return S; 2142 } 2143 2144 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2145 uint64_t Address, const void *Decoder) { 2146 DecodeStatus S = MCDisassembler::Success; 2147 2148 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2149 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2150 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2151 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2152 2153 if (pred == 0xF) 2154 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2155 2156 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2157 return MCDisassembler::Fail; 2158 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2159 return MCDisassembler::Fail; 2160 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2161 return MCDisassembler::Fail; 2162 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2163 return MCDisassembler::Fail; 2164 return S; 2165 } 2166 2167 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2168 unsigned Insn, 2169 uint64_t Address, const void *Decoder) { 2170 DecodeStatus S = MCDisassembler::Success; 2171 2172 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2173 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2174 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2175 2176 if (pred == 0xF) { 2177 // Ambiguous with RFE and SRS 2178 switch (Inst.getOpcode()) { 2179 case ARM::LDMDA: 2180 Inst.setOpcode(ARM::RFEDA); 2181 break; 2182 case ARM::LDMDA_UPD: 2183 Inst.setOpcode(ARM::RFEDA_UPD); 2184 break; 2185 case ARM::LDMDB: 2186 Inst.setOpcode(ARM::RFEDB); 2187 break; 2188 case ARM::LDMDB_UPD: 2189 Inst.setOpcode(ARM::RFEDB_UPD); 2190 break; 2191 case ARM::LDMIA: 2192 Inst.setOpcode(ARM::RFEIA); 2193 break; 2194 case ARM::LDMIA_UPD: 2195 Inst.setOpcode(ARM::RFEIA_UPD); 2196 break; 2197 case ARM::LDMIB: 2198 Inst.setOpcode(ARM::RFEIB); 2199 break; 2200 case ARM::LDMIB_UPD: 2201 Inst.setOpcode(ARM::RFEIB_UPD); 2202 break; 2203 case ARM::STMDA: 2204 Inst.setOpcode(ARM::SRSDA); 2205 break; 2206 case ARM::STMDA_UPD: 2207 Inst.setOpcode(ARM::SRSDA_UPD); 2208 break; 2209 case ARM::STMDB: 2210 Inst.setOpcode(ARM::SRSDB); 2211 break; 2212 case ARM::STMDB_UPD: 2213 Inst.setOpcode(ARM::SRSDB_UPD); 2214 break; 2215 case ARM::STMIA: 2216 Inst.setOpcode(ARM::SRSIA); 2217 break; 2218 case ARM::STMIA_UPD: 2219 Inst.setOpcode(ARM::SRSIA_UPD); 2220 break; 2221 case ARM::STMIB: 2222 Inst.setOpcode(ARM::SRSIB); 2223 break; 2224 case ARM::STMIB_UPD: 2225 Inst.setOpcode(ARM::SRSIB_UPD); 2226 break; 2227 default: 2228 return MCDisassembler::Fail; 2229 } 2230 2231 // For stores (which become SRS's, the only operand is the mode. 2232 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2233 // Check SRS encoding constraints 2234 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2235 fieldFromInstruction(Insn, 20, 1) == 0)) 2236 return MCDisassembler::Fail; 2237 2238 Inst.addOperand( 2239 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2240 return S; 2241 } 2242 2243 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2244 } 2245 2246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2247 return MCDisassembler::Fail; 2248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2249 return MCDisassembler::Fail; // Tied 2250 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2251 return MCDisassembler::Fail; 2252 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2253 return MCDisassembler::Fail; 2254 2255 return S; 2256 } 2257 2258 // Check for UNPREDICTABLE predicated ESB instruction 2259 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2260 uint64_t Address, const void *Decoder) { 2261 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2262 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2263 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2264 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2265 2266 DecodeStatus S = MCDisassembler::Success; 2267 2268 Inst.addOperand(MCOperand::createImm(imm8)); 2269 2270 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2271 return MCDisassembler::Fail; 2272 2273 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2274 // so all predicates should be allowed. 2275 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2276 S = MCDisassembler::SoftFail; 2277 2278 return S; 2279 } 2280 2281 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2282 uint64_t Address, const void *Decoder) { 2283 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2284 unsigned M = fieldFromInstruction(Insn, 17, 1); 2285 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2286 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2287 2288 DecodeStatus S = MCDisassembler::Success; 2289 2290 // This decoder is called from multiple location that do not check 2291 // the full encoding is valid before they do. 2292 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2293 fieldFromInstruction(Insn, 16, 1) != 0 || 2294 fieldFromInstruction(Insn, 20, 8) != 0x10) 2295 return MCDisassembler::Fail; 2296 2297 // imod == '01' --> UNPREDICTABLE 2298 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2299 // return failure here. The '01' imod value is unprintable, so there's 2300 // nothing useful we could do even if we returned UNPREDICTABLE. 2301 2302 if (imod == 1) return MCDisassembler::Fail; 2303 2304 if (imod && M) { 2305 Inst.setOpcode(ARM::CPS3p); 2306 Inst.addOperand(MCOperand::createImm(imod)); 2307 Inst.addOperand(MCOperand::createImm(iflags)); 2308 Inst.addOperand(MCOperand::createImm(mode)); 2309 } else if (imod && !M) { 2310 Inst.setOpcode(ARM::CPS2p); 2311 Inst.addOperand(MCOperand::createImm(imod)); 2312 Inst.addOperand(MCOperand::createImm(iflags)); 2313 if (mode) S = MCDisassembler::SoftFail; 2314 } else if (!imod && M) { 2315 Inst.setOpcode(ARM::CPS1p); 2316 Inst.addOperand(MCOperand::createImm(mode)); 2317 if (iflags) S = MCDisassembler::SoftFail; 2318 } else { 2319 // imod == '00' && M == '0' --> UNPREDICTABLE 2320 Inst.setOpcode(ARM::CPS1p); 2321 Inst.addOperand(MCOperand::createImm(mode)); 2322 S = MCDisassembler::SoftFail; 2323 } 2324 2325 return S; 2326 } 2327 2328 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2329 uint64_t Address, const void *Decoder) { 2330 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2331 unsigned M = fieldFromInstruction(Insn, 8, 1); 2332 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2333 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2334 2335 DecodeStatus S = MCDisassembler::Success; 2336 2337 // imod == '01' --> UNPREDICTABLE 2338 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2339 // return failure here. The '01' imod value is unprintable, so there's 2340 // nothing useful we could do even if we returned UNPREDICTABLE. 2341 2342 if (imod == 1) return MCDisassembler::Fail; 2343 2344 if (imod && M) { 2345 Inst.setOpcode(ARM::t2CPS3p); 2346 Inst.addOperand(MCOperand::createImm(imod)); 2347 Inst.addOperand(MCOperand::createImm(iflags)); 2348 Inst.addOperand(MCOperand::createImm(mode)); 2349 } else if (imod && !M) { 2350 Inst.setOpcode(ARM::t2CPS2p); 2351 Inst.addOperand(MCOperand::createImm(imod)); 2352 Inst.addOperand(MCOperand::createImm(iflags)); 2353 if (mode) S = MCDisassembler::SoftFail; 2354 } else if (!imod && M) { 2355 Inst.setOpcode(ARM::t2CPS1p); 2356 Inst.addOperand(MCOperand::createImm(mode)); 2357 if (iflags) S = MCDisassembler::SoftFail; 2358 } else { 2359 // imod == '00' && M == '0' --> this is a HINT instruction 2360 int imm = fieldFromInstruction(Insn, 0, 8); 2361 // HINT are defined only for immediate in [0..4] 2362 if(imm > 4) return MCDisassembler::Fail; 2363 Inst.setOpcode(ARM::t2HINT); 2364 Inst.addOperand(MCOperand::createImm(imm)); 2365 } 2366 2367 return S; 2368 } 2369 2370 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2371 uint64_t Address, const void *Decoder) { 2372 DecodeStatus S = MCDisassembler::Success; 2373 2374 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2375 unsigned imm = 0; 2376 2377 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2378 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2379 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2380 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2381 2382 if (Inst.getOpcode() == ARM::t2MOVTi16) 2383 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2384 return MCDisassembler::Fail; 2385 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2386 return MCDisassembler::Fail; 2387 2388 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2389 Inst.addOperand(MCOperand::createImm(imm)); 2390 2391 return S; 2392 } 2393 2394 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2395 uint64_t Address, const void *Decoder) { 2396 DecodeStatus S = MCDisassembler::Success; 2397 2398 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2399 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2400 unsigned imm = 0; 2401 2402 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2403 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2404 2405 if (Inst.getOpcode() == ARM::MOVTi16) 2406 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2407 return MCDisassembler::Fail; 2408 2409 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2410 return MCDisassembler::Fail; 2411 2412 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2413 Inst.addOperand(MCOperand::createImm(imm)); 2414 2415 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2416 return MCDisassembler::Fail; 2417 2418 return S; 2419 } 2420 2421 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2422 uint64_t Address, const void *Decoder) { 2423 DecodeStatus S = MCDisassembler::Success; 2424 2425 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2426 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2427 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2428 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2429 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2430 2431 if (pred == 0xF) 2432 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2433 2434 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2435 return MCDisassembler::Fail; 2436 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2437 return MCDisassembler::Fail; 2438 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2439 return MCDisassembler::Fail; 2440 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2441 return MCDisassembler::Fail; 2442 2443 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2444 return MCDisassembler::Fail; 2445 2446 return S; 2447 } 2448 2449 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2450 uint64_t Address, const void *Decoder) { 2451 DecodeStatus S = MCDisassembler::Success; 2452 2453 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2454 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2455 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2456 2457 if (Pred == 0xF) 2458 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2459 2460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2461 return MCDisassembler::Fail; 2462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2463 return MCDisassembler::Fail; 2464 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2465 return MCDisassembler::Fail; 2466 2467 return S; 2468 } 2469 2470 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2471 uint64_t Address, const void *Decoder) { 2472 DecodeStatus S = MCDisassembler::Success; 2473 2474 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2475 2476 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2477 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2478 2479 if (!FeatureBits[ARM::HasV8_1aOps] || 2480 !FeatureBits[ARM::HasV8Ops]) 2481 return MCDisassembler::Fail; 2482 2483 // Decoder can be called from DecodeTST, which does not check the full 2484 // encoding is valid. 2485 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2486 fieldFromInstruction(Insn, 4,4) != 0) 2487 return MCDisassembler::Fail; 2488 if (fieldFromInstruction(Insn, 10,10) != 0 || 2489 fieldFromInstruction(Insn, 0,4) != 0) 2490 S = MCDisassembler::SoftFail; 2491 2492 Inst.setOpcode(ARM::SETPAN); 2493 Inst.addOperand(MCOperand::createImm(Imm)); 2494 2495 return S; 2496 } 2497 2498 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2499 uint64_t Address, const void *Decoder) { 2500 DecodeStatus S = MCDisassembler::Success; 2501 2502 unsigned add = fieldFromInstruction(Val, 12, 1); 2503 unsigned imm = fieldFromInstruction(Val, 0, 12); 2504 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2505 2506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2507 return MCDisassembler::Fail; 2508 2509 if (!add) imm *= -1; 2510 if (imm == 0 && !add) imm = INT32_MIN; 2511 Inst.addOperand(MCOperand::createImm(imm)); 2512 if (Rn == 15) 2513 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2514 2515 return S; 2516 } 2517 2518 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2519 uint64_t Address, const void *Decoder) { 2520 DecodeStatus S = MCDisassembler::Success; 2521 2522 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2523 // U == 1 to add imm, 0 to subtract it. 2524 unsigned U = fieldFromInstruction(Val, 8, 1); 2525 unsigned imm = fieldFromInstruction(Val, 0, 8); 2526 2527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2528 return MCDisassembler::Fail; 2529 2530 if (U) 2531 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2532 else 2533 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2534 2535 return S; 2536 } 2537 2538 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2539 uint64_t Address, const void *Decoder) { 2540 DecodeStatus S = MCDisassembler::Success; 2541 2542 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2543 // U == 1 to add imm, 0 to subtract it. 2544 unsigned U = fieldFromInstruction(Val, 8, 1); 2545 unsigned imm = fieldFromInstruction(Val, 0, 8); 2546 2547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2548 return MCDisassembler::Fail; 2549 2550 if (U) 2551 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2552 else 2553 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2554 2555 return S; 2556 } 2557 2558 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2559 uint64_t Address, const void *Decoder) { 2560 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2561 } 2562 2563 static DecodeStatus 2564 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2565 uint64_t Address, const void *Decoder) { 2566 DecodeStatus Status = MCDisassembler::Success; 2567 2568 // Note the J1 and J2 values are from the encoded instruction. So here 2569 // change them to I1 and I2 values via as documented: 2570 // I1 = NOT(J1 EOR S); 2571 // I2 = NOT(J2 EOR S); 2572 // and build the imm32 with one trailing zero as documented: 2573 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2574 unsigned S = fieldFromInstruction(Insn, 26, 1); 2575 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2576 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2577 unsigned I1 = !(J1 ^ S); 2578 unsigned I2 = !(J2 ^ S); 2579 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2580 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2581 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2582 int imm32 = SignExtend32<25>(tmp << 1); 2583 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2584 true, 4, Inst, Decoder)) 2585 Inst.addOperand(MCOperand::createImm(imm32)); 2586 2587 return Status; 2588 } 2589 2590 static DecodeStatus 2591 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2592 uint64_t Address, const void *Decoder) { 2593 DecodeStatus S = MCDisassembler::Success; 2594 2595 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2596 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2597 2598 if (pred == 0xF) { 2599 Inst.setOpcode(ARM::BLXi); 2600 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2601 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2602 true, 4, Inst, Decoder)) 2603 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2604 return S; 2605 } 2606 2607 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2608 true, 4, Inst, Decoder)) 2609 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2610 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2611 return MCDisassembler::Fail; 2612 2613 return S; 2614 } 2615 2616 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2617 uint64_t Address, const void *Decoder) { 2618 DecodeStatus S = MCDisassembler::Success; 2619 2620 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2621 unsigned align = fieldFromInstruction(Val, 4, 2); 2622 2623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2624 return MCDisassembler::Fail; 2625 if (!align) 2626 Inst.addOperand(MCOperand::createImm(0)); 2627 else 2628 Inst.addOperand(MCOperand::createImm(4 << align)); 2629 2630 return S; 2631 } 2632 2633 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2634 uint64_t Address, const void *Decoder) { 2635 DecodeStatus S = MCDisassembler::Success; 2636 2637 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2638 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2639 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2640 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2641 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2642 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2643 2644 // First output register 2645 switch (Inst.getOpcode()) { 2646 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2647 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2648 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2649 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2650 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2651 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2652 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2653 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2654 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2655 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2656 return MCDisassembler::Fail; 2657 break; 2658 case ARM::VLD2b16: 2659 case ARM::VLD2b32: 2660 case ARM::VLD2b8: 2661 case ARM::VLD2b16wb_fixed: 2662 case ARM::VLD2b16wb_register: 2663 case ARM::VLD2b32wb_fixed: 2664 case ARM::VLD2b32wb_register: 2665 case ARM::VLD2b8wb_fixed: 2666 case ARM::VLD2b8wb_register: 2667 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2668 return MCDisassembler::Fail; 2669 break; 2670 default: 2671 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2672 return MCDisassembler::Fail; 2673 } 2674 2675 // Second output register 2676 switch (Inst.getOpcode()) { 2677 case ARM::VLD3d8: 2678 case ARM::VLD3d16: 2679 case ARM::VLD3d32: 2680 case ARM::VLD3d8_UPD: 2681 case ARM::VLD3d16_UPD: 2682 case ARM::VLD3d32_UPD: 2683 case ARM::VLD4d8: 2684 case ARM::VLD4d16: 2685 case ARM::VLD4d32: 2686 case ARM::VLD4d8_UPD: 2687 case ARM::VLD4d16_UPD: 2688 case ARM::VLD4d32_UPD: 2689 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2690 return MCDisassembler::Fail; 2691 break; 2692 case ARM::VLD3q8: 2693 case ARM::VLD3q16: 2694 case ARM::VLD3q32: 2695 case ARM::VLD3q8_UPD: 2696 case ARM::VLD3q16_UPD: 2697 case ARM::VLD3q32_UPD: 2698 case ARM::VLD4q8: 2699 case ARM::VLD4q16: 2700 case ARM::VLD4q32: 2701 case ARM::VLD4q8_UPD: 2702 case ARM::VLD4q16_UPD: 2703 case ARM::VLD4q32_UPD: 2704 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2705 return MCDisassembler::Fail; 2706 break; 2707 default: 2708 break; 2709 } 2710 2711 // Third output register 2712 switch(Inst.getOpcode()) { 2713 case ARM::VLD3d8: 2714 case ARM::VLD3d16: 2715 case ARM::VLD3d32: 2716 case ARM::VLD3d8_UPD: 2717 case ARM::VLD3d16_UPD: 2718 case ARM::VLD3d32_UPD: 2719 case ARM::VLD4d8: 2720 case ARM::VLD4d16: 2721 case ARM::VLD4d32: 2722 case ARM::VLD4d8_UPD: 2723 case ARM::VLD4d16_UPD: 2724 case ARM::VLD4d32_UPD: 2725 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2726 return MCDisassembler::Fail; 2727 break; 2728 case ARM::VLD3q8: 2729 case ARM::VLD3q16: 2730 case ARM::VLD3q32: 2731 case ARM::VLD3q8_UPD: 2732 case ARM::VLD3q16_UPD: 2733 case ARM::VLD3q32_UPD: 2734 case ARM::VLD4q8: 2735 case ARM::VLD4q16: 2736 case ARM::VLD4q32: 2737 case ARM::VLD4q8_UPD: 2738 case ARM::VLD4q16_UPD: 2739 case ARM::VLD4q32_UPD: 2740 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2741 return MCDisassembler::Fail; 2742 break; 2743 default: 2744 break; 2745 } 2746 2747 // Fourth output register 2748 switch (Inst.getOpcode()) { 2749 case ARM::VLD4d8: 2750 case ARM::VLD4d16: 2751 case ARM::VLD4d32: 2752 case ARM::VLD4d8_UPD: 2753 case ARM::VLD4d16_UPD: 2754 case ARM::VLD4d32_UPD: 2755 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2756 return MCDisassembler::Fail; 2757 break; 2758 case ARM::VLD4q8: 2759 case ARM::VLD4q16: 2760 case ARM::VLD4q32: 2761 case ARM::VLD4q8_UPD: 2762 case ARM::VLD4q16_UPD: 2763 case ARM::VLD4q32_UPD: 2764 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2765 return MCDisassembler::Fail; 2766 break; 2767 default: 2768 break; 2769 } 2770 2771 // Writeback operand 2772 switch (Inst.getOpcode()) { 2773 case ARM::VLD1d8wb_fixed: 2774 case ARM::VLD1d16wb_fixed: 2775 case ARM::VLD1d32wb_fixed: 2776 case ARM::VLD1d64wb_fixed: 2777 case ARM::VLD1d8wb_register: 2778 case ARM::VLD1d16wb_register: 2779 case ARM::VLD1d32wb_register: 2780 case ARM::VLD1d64wb_register: 2781 case ARM::VLD1q8wb_fixed: 2782 case ARM::VLD1q16wb_fixed: 2783 case ARM::VLD1q32wb_fixed: 2784 case ARM::VLD1q64wb_fixed: 2785 case ARM::VLD1q8wb_register: 2786 case ARM::VLD1q16wb_register: 2787 case ARM::VLD1q32wb_register: 2788 case ARM::VLD1q64wb_register: 2789 case ARM::VLD1d8Twb_fixed: 2790 case ARM::VLD1d8Twb_register: 2791 case ARM::VLD1d16Twb_fixed: 2792 case ARM::VLD1d16Twb_register: 2793 case ARM::VLD1d32Twb_fixed: 2794 case ARM::VLD1d32Twb_register: 2795 case ARM::VLD1d64Twb_fixed: 2796 case ARM::VLD1d64Twb_register: 2797 case ARM::VLD1d8Qwb_fixed: 2798 case ARM::VLD1d8Qwb_register: 2799 case ARM::VLD1d16Qwb_fixed: 2800 case ARM::VLD1d16Qwb_register: 2801 case ARM::VLD1d32Qwb_fixed: 2802 case ARM::VLD1d32Qwb_register: 2803 case ARM::VLD1d64Qwb_fixed: 2804 case ARM::VLD1d64Qwb_register: 2805 case ARM::VLD2d8wb_fixed: 2806 case ARM::VLD2d16wb_fixed: 2807 case ARM::VLD2d32wb_fixed: 2808 case ARM::VLD2q8wb_fixed: 2809 case ARM::VLD2q16wb_fixed: 2810 case ARM::VLD2q32wb_fixed: 2811 case ARM::VLD2d8wb_register: 2812 case ARM::VLD2d16wb_register: 2813 case ARM::VLD2d32wb_register: 2814 case ARM::VLD2q8wb_register: 2815 case ARM::VLD2q16wb_register: 2816 case ARM::VLD2q32wb_register: 2817 case ARM::VLD2b8wb_fixed: 2818 case ARM::VLD2b16wb_fixed: 2819 case ARM::VLD2b32wb_fixed: 2820 case ARM::VLD2b8wb_register: 2821 case ARM::VLD2b16wb_register: 2822 case ARM::VLD2b32wb_register: 2823 Inst.addOperand(MCOperand::createImm(0)); 2824 break; 2825 case ARM::VLD3d8_UPD: 2826 case ARM::VLD3d16_UPD: 2827 case ARM::VLD3d32_UPD: 2828 case ARM::VLD3q8_UPD: 2829 case ARM::VLD3q16_UPD: 2830 case ARM::VLD3q32_UPD: 2831 case ARM::VLD4d8_UPD: 2832 case ARM::VLD4d16_UPD: 2833 case ARM::VLD4d32_UPD: 2834 case ARM::VLD4q8_UPD: 2835 case ARM::VLD4q16_UPD: 2836 case ARM::VLD4q32_UPD: 2837 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2838 return MCDisassembler::Fail; 2839 break; 2840 default: 2841 break; 2842 } 2843 2844 // AddrMode6 Base (register+alignment) 2845 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2846 return MCDisassembler::Fail; 2847 2848 // AddrMode6 Offset (register) 2849 switch (Inst.getOpcode()) { 2850 default: 2851 // The below have been updated to have explicit am6offset split 2852 // between fixed and register offset. For those instructions not 2853 // yet updated, we need to add an additional reg0 operand for the 2854 // fixed variant. 2855 // 2856 // The fixed offset encodes as Rm == 0xd, so we check for that. 2857 if (Rm == 0xd) { 2858 Inst.addOperand(MCOperand::createReg(0)); 2859 break; 2860 } 2861 // Fall through to handle the register offset variant. 2862 LLVM_FALLTHROUGH; 2863 case ARM::VLD1d8wb_fixed: 2864 case ARM::VLD1d16wb_fixed: 2865 case ARM::VLD1d32wb_fixed: 2866 case ARM::VLD1d64wb_fixed: 2867 case ARM::VLD1d8Twb_fixed: 2868 case ARM::VLD1d16Twb_fixed: 2869 case ARM::VLD1d32Twb_fixed: 2870 case ARM::VLD1d64Twb_fixed: 2871 case ARM::VLD1d8Qwb_fixed: 2872 case ARM::VLD1d16Qwb_fixed: 2873 case ARM::VLD1d32Qwb_fixed: 2874 case ARM::VLD1d64Qwb_fixed: 2875 case ARM::VLD1d8wb_register: 2876 case ARM::VLD1d16wb_register: 2877 case ARM::VLD1d32wb_register: 2878 case ARM::VLD1d64wb_register: 2879 case ARM::VLD1q8wb_fixed: 2880 case ARM::VLD1q16wb_fixed: 2881 case ARM::VLD1q32wb_fixed: 2882 case ARM::VLD1q64wb_fixed: 2883 case ARM::VLD1q8wb_register: 2884 case ARM::VLD1q16wb_register: 2885 case ARM::VLD1q32wb_register: 2886 case ARM::VLD1q64wb_register: 2887 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2888 // variant encodes Rm == 0xf. Anything else is a register offset post- 2889 // increment and we need to add the register operand to the instruction. 2890 if (Rm != 0xD && Rm != 0xF && 2891 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2892 return MCDisassembler::Fail; 2893 break; 2894 case ARM::VLD2d8wb_fixed: 2895 case ARM::VLD2d16wb_fixed: 2896 case ARM::VLD2d32wb_fixed: 2897 case ARM::VLD2b8wb_fixed: 2898 case ARM::VLD2b16wb_fixed: 2899 case ARM::VLD2b32wb_fixed: 2900 case ARM::VLD2q8wb_fixed: 2901 case ARM::VLD2q16wb_fixed: 2902 case ARM::VLD2q32wb_fixed: 2903 break; 2904 } 2905 2906 return S; 2907 } 2908 2909 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2910 uint64_t Address, const void *Decoder) { 2911 unsigned type = fieldFromInstruction(Insn, 8, 4); 2912 unsigned align = fieldFromInstruction(Insn, 4, 2); 2913 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2914 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2915 if (type == 10 && align == 3) return MCDisassembler::Fail; 2916 2917 unsigned load = fieldFromInstruction(Insn, 21, 1); 2918 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2919 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2920 } 2921 2922 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2923 uint64_t Address, const void *Decoder) { 2924 unsigned size = fieldFromInstruction(Insn, 6, 2); 2925 if (size == 3) return MCDisassembler::Fail; 2926 2927 unsigned type = fieldFromInstruction(Insn, 8, 4); 2928 unsigned align = fieldFromInstruction(Insn, 4, 2); 2929 if (type == 8 && align == 3) return MCDisassembler::Fail; 2930 if (type == 9 && align == 3) return MCDisassembler::Fail; 2931 2932 unsigned load = fieldFromInstruction(Insn, 21, 1); 2933 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2934 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2935 } 2936 2937 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2938 uint64_t Address, const void *Decoder) { 2939 unsigned size = fieldFromInstruction(Insn, 6, 2); 2940 if (size == 3) return MCDisassembler::Fail; 2941 2942 unsigned align = fieldFromInstruction(Insn, 4, 2); 2943 if (align & 2) return MCDisassembler::Fail; 2944 2945 unsigned load = fieldFromInstruction(Insn, 21, 1); 2946 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2947 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2948 } 2949 2950 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2951 uint64_t Address, const void *Decoder) { 2952 unsigned size = fieldFromInstruction(Insn, 6, 2); 2953 if (size == 3) return MCDisassembler::Fail; 2954 2955 unsigned load = fieldFromInstruction(Insn, 21, 1); 2956 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2957 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2958 } 2959 2960 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2961 uint64_t Address, const void *Decoder) { 2962 DecodeStatus S = MCDisassembler::Success; 2963 2964 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2965 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2966 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2967 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2968 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2969 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2970 2971 // Writeback Operand 2972 switch (Inst.getOpcode()) { 2973 case ARM::VST1d8wb_fixed: 2974 case ARM::VST1d16wb_fixed: 2975 case ARM::VST1d32wb_fixed: 2976 case ARM::VST1d64wb_fixed: 2977 case ARM::VST1d8wb_register: 2978 case ARM::VST1d16wb_register: 2979 case ARM::VST1d32wb_register: 2980 case ARM::VST1d64wb_register: 2981 case ARM::VST1q8wb_fixed: 2982 case ARM::VST1q16wb_fixed: 2983 case ARM::VST1q32wb_fixed: 2984 case ARM::VST1q64wb_fixed: 2985 case ARM::VST1q8wb_register: 2986 case ARM::VST1q16wb_register: 2987 case ARM::VST1q32wb_register: 2988 case ARM::VST1q64wb_register: 2989 case ARM::VST1d8Twb_fixed: 2990 case ARM::VST1d16Twb_fixed: 2991 case ARM::VST1d32Twb_fixed: 2992 case ARM::VST1d64Twb_fixed: 2993 case ARM::VST1d8Twb_register: 2994 case ARM::VST1d16Twb_register: 2995 case ARM::VST1d32Twb_register: 2996 case ARM::VST1d64Twb_register: 2997 case ARM::VST1d8Qwb_fixed: 2998 case ARM::VST1d16Qwb_fixed: 2999 case ARM::VST1d32Qwb_fixed: 3000 case ARM::VST1d64Qwb_fixed: 3001 case ARM::VST1d8Qwb_register: 3002 case ARM::VST1d16Qwb_register: 3003 case ARM::VST1d32Qwb_register: 3004 case ARM::VST1d64Qwb_register: 3005 case ARM::VST2d8wb_fixed: 3006 case ARM::VST2d16wb_fixed: 3007 case ARM::VST2d32wb_fixed: 3008 case ARM::VST2d8wb_register: 3009 case ARM::VST2d16wb_register: 3010 case ARM::VST2d32wb_register: 3011 case ARM::VST2q8wb_fixed: 3012 case ARM::VST2q16wb_fixed: 3013 case ARM::VST2q32wb_fixed: 3014 case ARM::VST2q8wb_register: 3015 case ARM::VST2q16wb_register: 3016 case ARM::VST2q32wb_register: 3017 case ARM::VST2b8wb_fixed: 3018 case ARM::VST2b16wb_fixed: 3019 case ARM::VST2b32wb_fixed: 3020 case ARM::VST2b8wb_register: 3021 case ARM::VST2b16wb_register: 3022 case ARM::VST2b32wb_register: 3023 if (Rm == 0xF) 3024 return MCDisassembler::Fail; 3025 Inst.addOperand(MCOperand::createImm(0)); 3026 break; 3027 case ARM::VST3d8_UPD: 3028 case ARM::VST3d16_UPD: 3029 case ARM::VST3d32_UPD: 3030 case ARM::VST3q8_UPD: 3031 case ARM::VST3q16_UPD: 3032 case ARM::VST3q32_UPD: 3033 case ARM::VST4d8_UPD: 3034 case ARM::VST4d16_UPD: 3035 case ARM::VST4d32_UPD: 3036 case ARM::VST4q8_UPD: 3037 case ARM::VST4q16_UPD: 3038 case ARM::VST4q32_UPD: 3039 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3040 return MCDisassembler::Fail; 3041 break; 3042 default: 3043 break; 3044 } 3045 3046 // AddrMode6 Base (register+alignment) 3047 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3048 return MCDisassembler::Fail; 3049 3050 // AddrMode6 Offset (register) 3051 switch (Inst.getOpcode()) { 3052 default: 3053 if (Rm == 0xD) 3054 Inst.addOperand(MCOperand::createReg(0)); 3055 else if (Rm != 0xF) { 3056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3057 return MCDisassembler::Fail; 3058 } 3059 break; 3060 case ARM::VST1d8wb_fixed: 3061 case ARM::VST1d16wb_fixed: 3062 case ARM::VST1d32wb_fixed: 3063 case ARM::VST1d64wb_fixed: 3064 case ARM::VST1q8wb_fixed: 3065 case ARM::VST1q16wb_fixed: 3066 case ARM::VST1q32wb_fixed: 3067 case ARM::VST1q64wb_fixed: 3068 case ARM::VST1d8Twb_fixed: 3069 case ARM::VST1d16Twb_fixed: 3070 case ARM::VST1d32Twb_fixed: 3071 case ARM::VST1d64Twb_fixed: 3072 case ARM::VST1d8Qwb_fixed: 3073 case ARM::VST1d16Qwb_fixed: 3074 case ARM::VST1d32Qwb_fixed: 3075 case ARM::VST1d64Qwb_fixed: 3076 case ARM::VST2d8wb_fixed: 3077 case ARM::VST2d16wb_fixed: 3078 case ARM::VST2d32wb_fixed: 3079 case ARM::VST2q8wb_fixed: 3080 case ARM::VST2q16wb_fixed: 3081 case ARM::VST2q32wb_fixed: 3082 case ARM::VST2b8wb_fixed: 3083 case ARM::VST2b16wb_fixed: 3084 case ARM::VST2b32wb_fixed: 3085 break; 3086 } 3087 3088 // First input register 3089 switch (Inst.getOpcode()) { 3090 case ARM::VST1q16: 3091 case ARM::VST1q32: 3092 case ARM::VST1q64: 3093 case ARM::VST1q8: 3094 case ARM::VST1q16wb_fixed: 3095 case ARM::VST1q16wb_register: 3096 case ARM::VST1q32wb_fixed: 3097 case ARM::VST1q32wb_register: 3098 case ARM::VST1q64wb_fixed: 3099 case ARM::VST1q64wb_register: 3100 case ARM::VST1q8wb_fixed: 3101 case ARM::VST1q8wb_register: 3102 case ARM::VST2d16: 3103 case ARM::VST2d32: 3104 case ARM::VST2d8: 3105 case ARM::VST2d16wb_fixed: 3106 case ARM::VST2d16wb_register: 3107 case ARM::VST2d32wb_fixed: 3108 case ARM::VST2d32wb_register: 3109 case ARM::VST2d8wb_fixed: 3110 case ARM::VST2d8wb_register: 3111 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3112 return MCDisassembler::Fail; 3113 break; 3114 case ARM::VST2b16: 3115 case ARM::VST2b32: 3116 case ARM::VST2b8: 3117 case ARM::VST2b16wb_fixed: 3118 case ARM::VST2b16wb_register: 3119 case ARM::VST2b32wb_fixed: 3120 case ARM::VST2b32wb_register: 3121 case ARM::VST2b8wb_fixed: 3122 case ARM::VST2b8wb_register: 3123 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3124 return MCDisassembler::Fail; 3125 break; 3126 default: 3127 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3128 return MCDisassembler::Fail; 3129 } 3130 3131 // Second input register 3132 switch (Inst.getOpcode()) { 3133 case ARM::VST3d8: 3134 case ARM::VST3d16: 3135 case ARM::VST3d32: 3136 case ARM::VST3d8_UPD: 3137 case ARM::VST3d16_UPD: 3138 case ARM::VST3d32_UPD: 3139 case ARM::VST4d8: 3140 case ARM::VST4d16: 3141 case ARM::VST4d32: 3142 case ARM::VST4d8_UPD: 3143 case ARM::VST4d16_UPD: 3144 case ARM::VST4d32_UPD: 3145 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3146 return MCDisassembler::Fail; 3147 break; 3148 case ARM::VST3q8: 3149 case ARM::VST3q16: 3150 case ARM::VST3q32: 3151 case ARM::VST3q8_UPD: 3152 case ARM::VST3q16_UPD: 3153 case ARM::VST3q32_UPD: 3154 case ARM::VST4q8: 3155 case ARM::VST4q16: 3156 case ARM::VST4q32: 3157 case ARM::VST4q8_UPD: 3158 case ARM::VST4q16_UPD: 3159 case ARM::VST4q32_UPD: 3160 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3161 return MCDisassembler::Fail; 3162 break; 3163 default: 3164 break; 3165 } 3166 3167 // Third input register 3168 switch (Inst.getOpcode()) { 3169 case ARM::VST3d8: 3170 case ARM::VST3d16: 3171 case ARM::VST3d32: 3172 case ARM::VST3d8_UPD: 3173 case ARM::VST3d16_UPD: 3174 case ARM::VST3d32_UPD: 3175 case ARM::VST4d8: 3176 case ARM::VST4d16: 3177 case ARM::VST4d32: 3178 case ARM::VST4d8_UPD: 3179 case ARM::VST4d16_UPD: 3180 case ARM::VST4d32_UPD: 3181 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3182 return MCDisassembler::Fail; 3183 break; 3184 case ARM::VST3q8: 3185 case ARM::VST3q16: 3186 case ARM::VST3q32: 3187 case ARM::VST3q8_UPD: 3188 case ARM::VST3q16_UPD: 3189 case ARM::VST3q32_UPD: 3190 case ARM::VST4q8: 3191 case ARM::VST4q16: 3192 case ARM::VST4q32: 3193 case ARM::VST4q8_UPD: 3194 case ARM::VST4q16_UPD: 3195 case ARM::VST4q32_UPD: 3196 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3197 return MCDisassembler::Fail; 3198 break; 3199 default: 3200 break; 3201 } 3202 3203 // Fourth input register 3204 switch (Inst.getOpcode()) { 3205 case ARM::VST4d8: 3206 case ARM::VST4d16: 3207 case ARM::VST4d32: 3208 case ARM::VST4d8_UPD: 3209 case ARM::VST4d16_UPD: 3210 case ARM::VST4d32_UPD: 3211 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3212 return MCDisassembler::Fail; 3213 break; 3214 case ARM::VST4q8: 3215 case ARM::VST4q16: 3216 case ARM::VST4q32: 3217 case ARM::VST4q8_UPD: 3218 case ARM::VST4q16_UPD: 3219 case ARM::VST4q32_UPD: 3220 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3221 return MCDisassembler::Fail; 3222 break; 3223 default: 3224 break; 3225 } 3226 3227 return S; 3228 } 3229 3230 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3231 uint64_t Address, const void *Decoder) { 3232 DecodeStatus S = MCDisassembler::Success; 3233 3234 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3235 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3236 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3237 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3238 unsigned align = fieldFromInstruction(Insn, 4, 1); 3239 unsigned size = fieldFromInstruction(Insn, 6, 2); 3240 3241 if (size == 0 && align == 1) 3242 return MCDisassembler::Fail; 3243 align *= (1 << size); 3244 3245 switch (Inst.getOpcode()) { 3246 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3247 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3248 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3249 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3250 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3251 return MCDisassembler::Fail; 3252 break; 3253 default: 3254 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3255 return MCDisassembler::Fail; 3256 break; 3257 } 3258 if (Rm != 0xF) { 3259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 } 3262 3263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3264 return MCDisassembler::Fail; 3265 Inst.addOperand(MCOperand::createImm(align)); 3266 3267 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3268 // variant encodes Rm == 0xf. Anything else is a register offset post- 3269 // increment and we need to add the register operand to the instruction. 3270 if (Rm != 0xD && Rm != 0xF && 3271 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3272 return MCDisassembler::Fail; 3273 3274 return S; 3275 } 3276 3277 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3278 uint64_t Address, const void *Decoder) { 3279 DecodeStatus S = MCDisassembler::Success; 3280 3281 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3282 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3283 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3284 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3285 unsigned align = fieldFromInstruction(Insn, 4, 1); 3286 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3287 align *= 2*size; 3288 3289 switch (Inst.getOpcode()) { 3290 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3291 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3292 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3293 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3294 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3295 return MCDisassembler::Fail; 3296 break; 3297 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3298 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3299 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3300 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3301 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3302 return MCDisassembler::Fail; 3303 break; 3304 default: 3305 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 break; 3308 } 3309 3310 if (Rm != 0xF) 3311 Inst.addOperand(MCOperand::createImm(0)); 3312 3313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3314 return MCDisassembler::Fail; 3315 Inst.addOperand(MCOperand::createImm(align)); 3316 3317 if (Rm != 0xD && Rm != 0xF) { 3318 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3319 return MCDisassembler::Fail; 3320 } 3321 3322 return S; 3323 } 3324 3325 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3326 uint64_t Address, const void *Decoder) { 3327 DecodeStatus S = MCDisassembler::Success; 3328 3329 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3330 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3331 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3332 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3333 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3334 3335 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3336 return MCDisassembler::Fail; 3337 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3338 return MCDisassembler::Fail; 3339 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3340 return MCDisassembler::Fail; 3341 if (Rm != 0xF) { 3342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3343 return MCDisassembler::Fail; 3344 } 3345 3346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3347 return MCDisassembler::Fail; 3348 Inst.addOperand(MCOperand::createImm(0)); 3349 3350 if (Rm == 0xD) 3351 Inst.addOperand(MCOperand::createReg(0)); 3352 else if (Rm != 0xF) { 3353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3354 return MCDisassembler::Fail; 3355 } 3356 3357 return S; 3358 } 3359 3360 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3361 uint64_t Address, const void *Decoder) { 3362 DecodeStatus S = MCDisassembler::Success; 3363 3364 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3365 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3366 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3367 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3368 unsigned size = fieldFromInstruction(Insn, 6, 2); 3369 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3370 unsigned align = fieldFromInstruction(Insn, 4, 1); 3371 3372 if (size == 0x3) { 3373 if (align == 0) 3374 return MCDisassembler::Fail; 3375 align = 16; 3376 } else { 3377 if (size == 2) { 3378 align *= 8; 3379 } else { 3380 size = 1 << size; 3381 align *= 4*size; 3382 } 3383 } 3384 3385 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3386 return MCDisassembler::Fail; 3387 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3388 return MCDisassembler::Fail; 3389 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3390 return MCDisassembler::Fail; 3391 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3392 return MCDisassembler::Fail; 3393 if (Rm != 0xF) { 3394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3395 return MCDisassembler::Fail; 3396 } 3397 3398 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3399 return MCDisassembler::Fail; 3400 Inst.addOperand(MCOperand::createImm(align)); 3401 3402 if (Rm == 0xD) 3403 Inst.addOperand(MCOperand::createReg(0)); 3404 else if (Rm != 0xF) { 3405 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3406 return MCDisassembler::Fail; 3407 } 3408 3409 return S; 3410 } 3411 3412 static DecodeStatus 3413 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3414 uint64_t Address, const void *Decoder) { 3415 DecodeStatus S = MCDisassembler::Success; 3416 3417 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3418 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3419 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3420 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3421 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3422 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3423 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3424 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3425 3426 if (Q) { 3427 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3428 return MCDisassembler::Fail; 3429 } else { 3430 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3431 return MCDisassembler::Fail; 3432 } 3433 3434 Inst.addOperand(MCOperand::createImm(imm)); 3435 3436 switch (Inst.getOpcode()) { 3437 case ARM::VORRiv4i16: 3438 case ARM::VORRiv2i32: 3439 case ARM::VBICiv4i16: 3440 case ARM::VBICiv2i32: 3441 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 break; 3444 case ARM::VORRiv8i16: 3445 case ARM::VORRiv4i32: 3446 case ARM::VBICiv8i16: 3447 case ARM::VBICiv4i32: 3448 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3449 return MCDisassembler::Fail; 3450 break; 3451 default: 3452 break; 3453 } 3454 3455 return S; 3456 } 3457 3458 static DecodeStatus 3459 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3460 uint64_t Address, const void *Decoder) { 3461 DecodeStatus S = MCDisassembler::Success; 3462 3463 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3464 fieldFromInstruction(Insn, 13, 3)); 3465 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3466 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3467 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3468 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3469 imm |= cmode << 8; 3470 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3471 3472 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3473 return MCDisassembler::Fail; 3474 3475 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3476 return MCDisassembler::Fail; 3477 3478 Inst.addOperand(MCOperand::createImm(imm)); 3479 3480 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3481 Inst.addOperand(MCOperand::createReg(0)); 3482 Inst.addOperand(MCOperand::createImm(0)); 3483 3484 return S; 3485 } 3486 3487 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3488 uint64_t Address, const void *Decoder) { 3489 DecodeStatus S = MCDisassembler::Success; 3490 3491 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3492 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3493 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3494 return MCDisassembler::Fail; 3495 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3496 3497 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3498 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3499 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3502 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3503 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3504 return MCDisassembler::Fail; 3505 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3506 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3507 Inst.addOperand(MCOperand::createImm(Qd)); 3508 3509 return S; 3510 } 3511 3512 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3513 uint64_t Address, const void *Decoder) { 3514 DecodeStatus S = MCDisassembler::Success; 3515 3516 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3517 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3518 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3519 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3520 unsigned size = fieldFromInstruction(Insn, 18, 2); 3521 3522 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3523 return MCDisassembler::Fail; 3524 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3525 return MCDisassembler::Fail; 3526 Inst.addOperand(MCOperand::createImm(8 << size)); 3527 3528 return S; 3529 } 3530 3531 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3532 uint64_t Address, const void *Decoder) { 3533 Inst.addOperand(MCOperand::createImm(8 - Val)); 3534 return MCDisassembler::Success; 3535 } 3536 3537 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3538 uint64_t Address, const void *Decoder) { 3539 Inst.addOperand(MCOperand::createImm(16 - Val)); 3540 return MCDisassembler::Success; 3541 } 3542 3543 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3544 uint64_t Address, const void *Decoder) { 3545 Inst.addOperand(MCOperand::createImm(32 - Val)); 3546 return MCDisassembler::Success; 3547 } 3548 3549 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3550 uint64_t Address, const void *Decoder) { 3551 Inst.addOperand(MCOperand::createImm(64 - Val)); 3552 return MCDisassembler::Success; 3553 } 3554 3555 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3556 uint64_t Address, const void *Decoder) { 3557 DecodeStatus S = MCDisassembler::Success; 3558 3559 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3560 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3561 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3562 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3563 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3564 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3565 unsigned op = fieldFromInstruction(Insn, 6, 1); 3566 3567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3568 return MCDisassembler::Fail; 3569 if (op) { 3570 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3571 return MCDisassembler::Fail; // Writeback 3572 } 3573 3574 switch (Inst.getOpcode()) { 3575 case ARM::VTBL2: 3576 case ARM::VTBX2: 3577 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 break; 3580 default: 3581 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 } 3584 3585 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3586 return MCDisassembler::Fail; 3587 3588 return S; 3589 } 3590 3591 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3592 uint64_t Address, const void *Decoder) { 3593 DecodeStatus S = MCDisassembler::Success; 3594 3595 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3596 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3597 3598 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3599 return MCDisassembler::Fail; 3600 3601 switch(Inst.getOpcode()) { 3602 default: 3603 return MCDisassembler::Fail; 3604 case ARM::tADR: 3605 break; // tADR does not explicitly represent the PC as an operand. 3606 case ARM::tADDrSPi: 3607 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3608 break; 3609 } 3610 3611 Inst.addOperand(MCOperand::createImm(imm)); 3612 return S; 3613 } 3614 3615 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3616 uint64_t Address, const void *Decoder) { 3617 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3618 true, 2, Inst, Decoder)) 3619 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3620 return MCDisassembler::Success; 3621 } 3622 3623 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3624 uint64_t Address, const void *Decoder) { 3625 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3626 true, 4, Inst, Decoder)) 3627 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3628 return MCDisassembler::Success; 3629 } 3630 3631 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3632 uint64_t Address, const void *Decoder) { 3633 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3634 true, 2, Inst, Decoder)) 3635 Inst.addOperand(MCOperand::createImm(Val << 1)); 3636 return MCDisassembler::Success; 3637 } 3638 3639 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3640 uint64_t Address, const void *Decoder) { 3641 DecodeStatus S = MCDisassembler::Success; 3642 3643 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3644 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3645 3646 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3647 return MCDisassembler::Fail; 3648 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3649 return MCDisassembler::Fail; 3650 3651 return S; 3652 } 3653 3654 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3655 uint64_t Address, const void *Decoder) { 3656 DecodeStatus S = MCDisassembler::Success; 3657 3658 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3659 unsigned imm = fieldFromInstruction(Val, 3, 5); 3660 3661 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3662 return MCDisassembler::Fail; 3663 Inst.addOperand(MCOperand::createImm(imm)); 3664 3665 return S; 3666 } 3667 3668 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3669 uint64_t Address, const void *Decoder) { 3670 unsigned imm = Val << 2; 3671 3672 Inst.addOperand(MCOperand::createImm(imm)); 3673 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3674 3675 return MCDisassembler::Success; 3676 } 3677 3678 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3679 uint64_t Address, const void *Decoder) { 3680 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3681 Inst.addOperand(MCOperand::createImm(Val)); 3682 3683 return MCDisassembler::Success; 3684 } 3685 3686 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3687 uint64_t Address, const void *Decoder) { 3688 DecodeStatus S = MCDisassembler::Success; 3689 3690 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3691 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3692 unsigned imm = fieldFromInstruction(Val, 0, 2); 3693 3694 // Thumb stores cannot use PC as dest register. 3695 switch (Inst.getOpcode()) { 3696 case ARM::t2STRHs: 3697 case ARM::t2STRBs: 3698 case ARM::t2STRs: 3699 if (Rn == 15) 3700 return MCDisassembler::Fail; 3701 break; 3702 default: 3703 break; 3704 } 3705 3706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3707 return MCDisassembler::Fail; 3708 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3709 return MCDisassembler::Fail; 3710 Inst.addOperand(MCOperand::createImm(imm)); 3711 3712 return S; 3713 } 3714 3715 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3716 uint64_t Address, const void *Decoder) { 3717 DecodeStatus S = MCDisassembler::Success; 3718 3719 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3720 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3721 3722 const FeatureBitset &featureBits = 3723 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3724 3725 bool hasMP = featureBits[ARM::FeatureMP]; 3726 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3727 3728 if (Rn == 15) { 3729 switch (Inst.getOpcode()) { 3730 case ARM::t2LDRBs: 3731 Inst.setOpcode(ARM::t2LDRBpci); 3732 break; 3733 case ARM::t2LDRHs: 3734 Inst.setOpcode(ARM::t2LDRHpci); 3735 break; 3736 case ARM::t2LDRSHs: 3737 Inst.setOpcode(ARM::t2LDRSHpci); 3738 break; 3739 case ARM::t2LDRSBs: 3740 Inst.setOpcode(ARM::t2LDRSBpci); 3741 break; 3742 case ARM::t2LDRs: 3743 Inst.setOpcode(ARM::t2LDRpci); 3744 break; 3745 case ARM::t2PLDs: 3746 Inst.setOpcode(ARM::t2PLDpci); 3747 break; 3748 case ARM::t2PLIs: 3749 Inst.setOpcode(ARM::t2PLIpci); 3750 break; 3751 default: 3752 return MCDisassembler::Fail; 3753 } 3754 3755 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3756 } 3757 3758 if (Rt == 15) { 3759 switch (Inst.getOpcode()) { 3760 case ARM::t2LDRSHs: 3761 return MCDisassembler::Fail; 3762 case ARM::t2LDRHs: 3763 Inst.setOpcode(ARM::t2PLDWs); 3764 break; 3765 case ARM::t2LDRSBs: 3766 Inst.setOpcode(ARM::t2PLIs); 3767 break; 3768 default: 3769 break; 3770 } 3771 } 3772 3773 switch (Inst.getOpcode()) { 3774 case ARM::t2PLDs: 3775 break; 3776 case ARM::t2PLIs: 3777 if (!hasV7Ops) 3778 return MCDisassembler::Fail; 3779 break; 3780 case ARM::t2PLDWs: 3781 if (!hasV7Ops || !hasMP) 3782 return MCDisassembler::Fail; 3783 break; 3784 default: 3785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3786 return MCDisassembler::Fail; 3787 } 3788 3789 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3790 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3791 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3792 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3793 return MCDisassembler::Fail; 3794 3795 return S; 3796 } 3797 3798 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3799 uint64_t Address, const void* Decoder) { 3800 DecodeStatus S = MCDisassembler::Success; 3801 3802 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3803 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3804 unsigned U = fieldFromInstruction(Insn, 9, 1); 3805 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3806 imm |= (U << 8); 3807 imm |= (Rn << 9); 3808 unsigned add = fieldFromInstruction(Insn, 9, 1); 3809 3810 const FeatureBitset &featureBits = 3811 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3812 3813 bool hasMP = featureBits[ARM::FeatureMP]; 3814 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3815 3816 if (Rn == 15) { 3817 switch (Inst.getOpcode()) { 3818 case ARM::t2LDRi8: 3819 Inst.setOpcode(ARM::t2LDRpci); 3820 break; 3821 case ARM::t2LDRBi8: 3822 Inst.setOpcode(ARM::t2LDRBpci); 3823 break; 3824 case ARM::t2LDRSBi8: 3825 Inst.setOpcode(ARM::t2LDRSBpci); 3826 break; 3827 case ARM::t2LDRHi8: 3828 Inst.setOpcode(ARM::t2LDRHpci); 3829 break; 3830 case ARM::t2LDRSHi8: 3831 Inst.setOpcode(ARM::t2LDRSHpci); 3832 break; 3833 case ARM::t2PLDi8: 3834 Inst.setOpcode(ARM::t2PLDpci); 3835 break; 3836 case ARM::t2PLIi8: 3837 Inst.setOpcode(ARM::t2PLIpci); 3838 break; 3839 default: 3840 return MCDisassembler::Fail; 3841 } 3842 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3843 } 3844 3845 if (Rt == 15) { 3846 switch (Inst.getOpcode()) { 3847 case ARM::t2LDRSHi8: 3848 return MCDisassembler::Fail; 3849 case ARM::t2LDRHi8: 3850 if (!add) 3851 Inst.setOpcode(ARM::t2PLDWi8); 3852 break; 3853 case ARM::t2LDRSBi8: 3854 Inst.setOpcode(ARM::t2PLIi8); 3855 break; 3856 default: 3857 break; 3858 } 3859 } 3860 3861 switch (Inst.getOpcode()) { 3862 case ARM::t2PLDi8: 3863 break; 3864 case ARM::t2PLIi8: 3865 if (!hasV7Ops) 3866 return MCDisassembler::Fail; 3867 break; 3868 case ARM::t2PLDWi8: 3869 if (!hasV7Ops || !hasMP) 3870 return MCDisassembler::Fail; 3871 break; 3872 default: 3873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3874 return MCDisassembler::Fail; 3875 } 3876 3877 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3878 return MCDisassembler::Fail; 3879 return S; 3880 } 3881 3882 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3883 uint64_t Address, const void* Decoder) { 3884 DecodeStatus S = MCDisassembler::Success; 3885 3886 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3887 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3888 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3889 imm |= (Rn << 13); 3890 3891 const FeatureBitset &featureBits = 3892 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3893 3894 bool hasMP = featureBits[ARM::FeatureMP]; 3895 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3896 3897 if (Rn == 15) { 3898 switch (Inst.getOpcode()) { 3899 case ARM::t2LDRi12: 3900 Inst.setOpcode(ARM::t2LDRpci); 3901 break; 3902 case ARM::t2LDRHi12: 3903 Inst.setOpcode(ARM::t2LDRHpci); 3904 break; 3905 case ARM::t2LDRSHi12: 3906 Inst.setOpcode(ARM::t2LDRSHpci); 3907 break; 3908 case ARM::t2LDRBi12: 3909 Inst.setOpcode(ARM::t2LDRBpci); 3910 break; 3911 case ARM::t2LDRSBi12: 3912 Inst.setOpcode(ARM::t2LDRSBpci); 3913 break; 3914 case ARM::t2PLDi12: 3915 Inst.setOpcode(ARM::t2PLDpci); 3916 break; 3917 case ARM::t2PLIi12: 3918 Inst.setOpcode(ARM::t2PLIpci); 3919 break; 3920 default: 3921 return MCDisassembler::Fail; 3922 } 3923 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3924 } 3925 3926 if (Rt == 15) { 3927 switch (Inst.getOpcode()) { 3928 case ARM::t2LDRSHi12: 3929 return MCDisassembler::Fail; 3930 case ARM::t2LDRHi12: 3931 Inst.setOpcode(ARM::t2PLDWi12); 3932 break; 3933 case ARM::t2LDRSBi12: 3934 Inst.setOpcode(ARM::t2PLIi12); 3935 break; 3936 default: 3937 break; 3938 } 3939 } 3940 3941 switch (Inst.getOpcode()) { 3942 case ARM::t2PLDi12: 3943 break; 3944 case ARM::t2PLIi12: 3945 if (!hasV7Ops) 3946 return MCDisassembler::Fail; 3947 break; 3948 case ARM::t2PLDWi12: 3949 if (!hasV7Ops || !hasMP) 3950 return MCDisassembler::Fail; 3951 break; 3952 default: 3953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3954 return MCDisassembler::Fail; 3955 } 3956 3957 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3958 return MCDisassembler::Fail; 3959 return S; 3960 } 3961 3962 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3963 uint64_t Address, const void* Decoder) { 3964 DecodeStatus S = MCDisassembler::Success; 3965 3966 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3967 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3968 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3969 imm |= (Rn << 9); 3970 3971 if (Rn == 15) { 3972 switch (Inst.getOpcode()) { 3973 case ARM::t2LDRT: 3974 Inst.setOpcode(ARM::t2LDRpci); 3975 break; 3976 case ARM::t2LDRBT: 3977 Inst.setOpcode(ARM::t2LDRBpci); 3978 break; 3979 case ARM::t2LDRHT: 3980 Inst.setOpcode(ARM::t2LDRHpci); 3981 break; 3982 case ARM::t2LDRSBT: 3983 Inst.setOpcode(ARM::t2LDRSBpci); 3984 break; 3985 case ARM::t2LDRSHT: 3986 Inst.setOpcode(ARM::t2LDRSHpci); 3987 break; 3988 default: 3989 return MCDisassembler::Fail; 3990 } 3991 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3992 } 3993 3994 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3995 return MCDisassembler::Fail; 3996 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3997 return MCDisassembler::Fail; 3998 return S; 3999 } 4000 4001 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4002 uint64_t Address, const void* Decoder) { 4003 DecodeStatus S = MCDisassembler::Success; 4004 4005 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4006 unsigned U = fieldFromInstruction(Insn, 23, 1); 4007 int imm = fieldFromInstruction(Insn, 0, 12); 4008 4009 const FeatureBitset &featureBits = 4010 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4011 4012 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4013 4014 if (Rt == 15) { 4015 switch (Inst.getOpcode()) { 4016 case ARM::t2LDRBpci: 4017 case ARM::t2LDRHpci: 4018 Inst.setOpcode(ARM::t2PLDpci); 4019 break; 4020 case ARM::t2LDRSBpci: 4021 Inst.setOpcode(ARM::t2PLIpci); 4022 break; 4023 case ARM::t2LDRSHpci: 4024 return MCDisassembler::Fail; 4025 default: 4026 break; 4027 } 4028 } 4029 4030 switch(Inst.getOpcode()) { 4031 case ARM::t2PLDpci: 4032 break; 4033 case ARM::t2PLIpci: 4034 if (!hasV7Ops) 4035 return MCDisassembler::Fail; 4036 break; 4037 default: 4038 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4039 return MCDisassembler::Fail; 4040 } 4041 4042 if (!U) { 4043 // Special case for #-0. 4044 if (imm == 0) 4045 imm = INT32_MIN; 4046 else 4047 imm = -imm; 4048 } 4049 Inst.addOperand(MCOperand::createImm(imm)); 4050 4051 return S; 4052 } 4053 4054 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4055 uint64_t Address, const void *Decoder) { 4056 if (Val == 0) 4057 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4058 else { 4059 int imm = Val & 0xFF; 4060 4061 if (!(Val & 0x100)) imm *= -1; 4062 Inst.addOperand(MCOperand::createImm(imm * 4)); 4063 } 4064 4065 return MCDisassembler::Success; 4066 } 4067 4068 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4069 const void *Decoder) { 4070 if (Val == 0) 4071 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4072 else { 4073 int imm = Val & 0x7F; 4074 4075 if (!(Val & 0x80)) 4076 imm *= -1; 4077 Inst.addOperand(MCOperand::createImm(imm * 4)); 4078 } 4079 4080 return MCDisassembler::Success; 4081 } 4082 4083 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4084 uint64_t Address, const void *Decoder) { 4085 DecodeStatus S = MCDisassembler::Success; 4086 4087 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4088 unsigned imm = fieldFromInstruction(Val, 0, 9); 4089 4090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4091 return MCDisassembler::Fail; 4092 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4093 return MCDisassembler::Fail; 4094 4095 return S; 4096 } 4097 4098 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4099 uint64_t Address, 4100 const void *Decoder) { 4101 DecodeStatus S = MCDisassembler::Success; 4102 4103 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4104 unsigned imm = fieldFromInstruction(Val, 0, 8); 4105 4106 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4107 return MCDisassembler::Fail; 4108 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4109 return MCDisassembler::Fail; 4110 4111 return S; 4112 } 4113 4114 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4115 uint64_t Address, const void *Decoder) { 4116 DecodeStatus S = MCDisassembler::Success; 4117 4118 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4119 unsigned imm = fieldFromInstruction(Val, 0, 8); 4120 4121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4122 return MCDisassembler::Fail; 4123 4124 Inst.addOperand(MCOperand::createImm(imm)); 4125 4126 return S; 4127 } 4128 4129 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4130 uint64_t Address, const void *Decoder) { 4131 int imm = Val & 0xFF; 4132 if (Val == 0) 4133 imm = INT32_MIN; 4134 else if (!(Val & 0x100)) 4135 imm *= -1; 4136 Inst.addOperand(MCOperand::createImm(imm)); 4137 4138 return MCDisassembler::Success; 4139 } 4140 4141 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4142 uint64_t Address, const void *Decoder) { 4143 DecodeStatus S = MCDisassembler::Success; 4144 4145 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4146 unsigned imm = fieldFromInstruction(Val, 0, 9); 4147 4148 // Thumb stores cannot use PC as dest register. 4149 switch (Inst.getOpcode()) { 4150 case ARM::t2STRT: 4151 case ARM::t2STRBT: 4152 case ARM::t2STRHT: 4153 case ARM::t2STRi8: 4154 case ARM::t2STRHi8: 4155 case ARM::t2STRBi8: 4156 if (Rn == 15) 4157 return MCDisassembler::Fail; 4158 break; 4159 default: 4160 break; 4161 } 4162 4163 // Some instructions always use an additive offset. 4164 switch (Inst.getOpcode()) { 4165 case ARM::t2LDRT: 4166 case ARM::t2LDRBT: 4167 case ARM::t2LDRHT: 4168 case ARM::t2LDRSBT: 4169 case ARM::t2LDRSHT: 4170 case ARM::t2STRT: 4171 case ARM::t2STRBT: 4172 case ARM::t2STRHT: 4173 imm |= 0x100; 4174 break; 4175 default: 4176 break; 4177 } 4178 4179 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4180 return MCDisassembler::Fail; 4181 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4182 return MCDisassembler::Fail; 4183 4184 return S; 4185 } 4186 4187 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4188 uint64_t Address, const void *Decoder) { 4189 DecodeStatus S = MCDisassembler::Success; 4190 4191 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4192 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4193 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4194 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4195 addr |= Rn << 9; 4196 unsigned load = fieldFromInstruction(Insn, 20, 1); 4197 4198 if (Rn == 15) { 4199 switch (Inst.getOpcode()) { 4200 case ARM::t2LDR_PRE: 4201 case ARM::t2LDR_POST: 4202 Inst.setOpcode(ARM::t2LDRpci); 4203 break; 4204 case ARM::t2LDRB_PRE: 4205 case ARM::t2LDRB_POST: 4206 Inst.setOpcode(ARM::t2LDRBpci); 4207 break; 4208 case ARM::t2LDRH_PRE: 4209 case ARM::t2LDRH_POST: 4210 Inst.setOpcode(ARM::t2LDRHpci); 4211 break; 4212 case ARM::t2LDRSB_PRE: 4213 case ARM::t2LDRSB_POST: 4214 if (Rt == 15) 4215 Inst.setOpcode(ARM::t2PLIpci); 4216 else 4217 Inst.setOpcode(ARM::t2LDRSBpci); 4218 break; 4219 case ARM::t2LDRSH_PRE: 4220 case ARM::t2LDRSH_POST: 4221 Inst.setOpcode(ARM::t2LDRSHpci); 4222 break; 4223 default: 4224 return MCDisassembler::Fail; 4225 } 4226 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4227 } 4228 4229 if (!load) { 4230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4231 return MCDisassembler::Fail; 4232 } 4233 4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 4237 if (load) { 4238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4239 return MCDisassembler::Fail; 4240 } 4241 4242 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4243 return MCDisassembler::Fail; 4244 4245 return S; 4246 } 4247 4248 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4249 uint64_t Address, const void *Decoder) { 4250 DecodeStatus S = MCDisassembler::Success; 4251 4252 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4253 unsigned imm = fieldFromInstruction(Val, 0, 12); 4254 4255 // Thumb stores cannot use PC as dest register. 4256 switch (Inst.getOpcode()) { 4257 case ARM::t2STRi12: 4258 case ARM::t2STRBi12: 4259 case ARM::t2STRHi12: 4260 if (Rn == 15) 4261 return MCDisassembler::Fail; 4262 break; 4263 default: 4264 break; 4265 } 4266 4267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 Inst.addOperand(MCOperand::createImm(imm)); 4270 4271 return S; 4272 } 4273 4274 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4275 uint64_t Address, const void *Decoder) { 4276 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4277 4278 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4279 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4280 Inst.addOperand(MCOperand::createImm(imm)); 4281 4282 return MCDisassembler::Success; 4283 } 4284 4285 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4286 uint64_t Address, const void *Decoder) { 4287 DecodeStatus S = MCDisassembler::Success; 4288 4289 if (Inst.getOpcode() == ARM::tADDrSP) { 4290 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4291 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4292 4293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4294 return MCDisassembler::Fail; 4295 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4297 return MCDisassembler::Fail; 4298 } else if (Inst.getOpcode() == ARM::tADDspr) { 4299 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4300 4301 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4302 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 } 4306 4307 return S; 4308 } 4309 4310 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4311 uint64_t Address, const void *Decoder) { 4312 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4313 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4314 4315 Inst.addOperand(MCOperand::createImm(imod)); 4316 Inst.addOperand(MCOperand::createImm(flags)); 4317 4318 return MCDisassembler::Success; 4319 } 4320 4321 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4322 uint64_t Address, const void *Decoder) { 4323 DecodeStatus S = MCDisassembler::Success; 4324 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4325 unsigned add = fieldFromInstruction(Insn, 4, 1); 4326 4327 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4328 return MCDisassembler::Fail; 4329 Inst.addOperand(MCOperand::createImm(add)); 4330 4331 return S; 4332 } 4333 4334 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4335 uint64_t Address, const void *Decoder) { 4336 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4337 // Note only one trailing zero not two. Also the J1 and J2 values are from 4338 // the encoded instruction. So here change to I1 and I2 values via: 4339 // I1 = NOT(J1 EOR S); 4340 // I2 = NOT(J2 EOR S); 4341 // and build the imm32 with two trailing zeros as documented: 4342 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4343 unsigned S = (Val >> 23) & 1; 4344 unsigned J1 = (Val >> 22) & 1; 4345 unsigned J2 = (Val >> 21) & 1; 4346 unsigned I1 = !(J1 ^ S); 4347 unsigned I2 = !(J2 ^ S); 4348 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4349 int imm32 = SignExtend32<25>(tmp << 1); 4350 4351 if (!tryAddingSymbolicOperand(Address, 4352 (Address & ~2u) + imm32 + 4, 4353 true, 4, Inst, Decoder)) 4354 Inst.addOperand(MCOperand::createImm(imm32)); 4355 return MCDisassembler::Success; 4356 } 4357 4358 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4359 uint64_t Address, const void *Decoder) { 4360 if (Val == 0xA || Val == 0xB) 4361 return MCDisassembler::Fail; 4362 4363 const FeatureBitset &featureBits = 4364 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4365 4366 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4367 return MCDisassembler::Fail; 4368 4369 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should 4370 // decode as VFP/MVE instructions. 4371 if (featureBits[ARM::HasV8_1MMainlineOps] && 4372 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || 4373 (Val & 0xE) == 0xE)) 4374 return MCDisassembler::Fail; 4375 4376 Inst.addOperand(MCOperand::createImm(Val)); 4377 return MCDisassembler::Success; 4378 } 4379 4380 static DecodeStatus 4381 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4382 uint64_t Address, const void *Decoder) { 4383 DecodeStatus S = MCDisassembler::Success; 4384 4385 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4386 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4387 4388 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4390 return MCDisassembler::Fail; 4391 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4392 return MCDisassembler::Fail; 4393 return S; 4394 } 4395 4396 static DecodeStatus 4397 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4398 uint64_t Address, const void *Decoder) { 4399 DecodeStatus S = MCDisassembler::Success; 4400 4401 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4402 if (pred == 0xE || pred == 0xF) { 4403 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4404 switch (opc) { 4405 default: 4406 return MCDisassembler::Fail; 4407 case 0xf3bf8f4: 4408 Inst.setOpcode(ARM::t2DSB); 4409 break; 4410 case 0xf3bf8f5: 4411 Inst.setOpcode(ARM::t2DMB); 4412 break; 4413 case 0xf3bf8f6: 4414 Inst.setOpcode(ARM::t2ISB); 4415 break; 4416 } 4417 4418 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4419 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4420 } 4421 4422 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4423 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4424 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4425 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4426 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4427 4428 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4429 return MCDisassembler::Fail; 4430 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4431 return MCDisassembler::Fail; 4432 4433 return S; 4434 } 4435 4436 // Decode a shifted immediate operand. These basically consist 4437 // of an 8-bit value, and a 4-bit directive that specifies either 4438 // a splat operation or a rotation. 4439 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4440 uint64_t Address, const void *Decoder) { 4441 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4442 if (ctrl == 0) { 4443 unsigned byte = fieldFromInstruction(Val, 8, 2); 4444 unsigned imm = fieldFromInstruction(Val, 0, 8); 4445 switch (byte) { 4446 case 0: 4447 Inst.addOperand(MCOperand::createImm(imm)); 4448 break; 4449 case 1: 4450 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4451 break; 4452 case 2: 4453 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4454 break; 4455 case 3: 4456 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4457 (imm << 8) | imm)); 4458 break; 4459 } 4460 } else { 4461 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4462 unsigned rot = fieldFromInstruction(Val, 7, 5); 4463 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4464 Inst.addOperand(MCOperand::createImm(imm)); 4465 } 4466 4467 return MCDisassembler::Success; 4468 } 4469 4470 static DecodeStatus 4471 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4472 uint64_t Address, const void *Decoder) { 4473 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4474 true, 2, Inst, Decoder)) 4475 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4476 return MCDisassembler::Success; 4477 } 4478 4479 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4480 uint64_t Address, 4481 const void *Decoder) { 4482 // Val is passed in as S:J1:J2:imm10:imm11 4483 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4484 // the encoded instruction. So here change to I1 and I2 values via: 4485 // I1 = NOT(J1 EOR S); 4486 // I2 = NOT(J2 EOR S); 4487 // and build the imm32 with one trailing zero as documented: 4488 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4489 unsigned S = (Val >> 23) & 1; 4490 unsigned J1 = (Val >> 22) & 1; 4491 unsigned J2 = (Val >> 21) & 1; 4492 unsigned I1 = !(J1 ^ S); 4493 unsigned I2 = !(J2 ^ S); 4494 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4495 int imm32 = SignExtend32<25>(tmp << 1); 4496 4497 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4498 true, 4, Inst, Decoder)) 4499 Inst.addOperand(MCOperand::createImm(imm32)); 4500 return MCDisassembler::Success; 4501 } 4502 4503 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4504 uint64_t Address, const void *Decoder) { 4505 if (Val & ~0xf) 4506 return MCDisassembler::Fail; 4507 4508 Inst.addOperand(MCOperand::createImm(Val)); 4509 return MCDisassembler::Success; 4510 } 4511 4512 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4513 uint64_t Address, const void *Decoder) { 4514 if (Val & ~0xf) 4515 return MCDisassembler::Fail; 4516 4517 Inst.addOperand(MCOperand::createImm(Val)); 4518 return MCDisassembler::Success; 4519 } 4520 4521 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4522 uint64_t Address, const void *Decoder) { 4523 DecodeStatus S = MCDisassembler::Success; 4524 const FeatureBitset &FeatureBits = 4525 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4526 4527 if (FeatureBits[ARM::FeatureMClass]) { 4528 unsigned ValLow = Val & 0xff; 4529 4530 // Validate the SYSm value first. 4531 switch (ValLow) { 4532 case 0: // apsr 4533 case 1: // iapsr 4534 case 2: // eapsr 4535 case 3: // xpsr 4536 case 5: // ipsr 4537 case 6: // epsr 4538 case 7: // iepsr 4539 case 8: // msp 4540 case 9: // psp 4541 case 16: // primask 4542 case 20: // control 4543 break; 4544 case 17: // basepri 4545 case 18: // basepri_max 4546 case 19: // faultmask 4547 if (!(FeatureBits[ARM::HasV7Ops])) 4548 // Values basepri, basepri_max and faultmask are only valid for v7m. 4549 return MCDisassembler::Fail; 4550 break; 4551 case 0x8a: // msplim_ns 4552 case 0x8b: // psplim_ns 4553 case 0x91: // basepri_ns 4554 case 0x93: // faultmask_ns 4555 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4556 return MCDisassembler::Fail; 4557 LLVM_FALLTHROUGH; 4558 case 10: // msplim 4559 case 11: // psplim 4560 case 0x88: // msp_ns 4561 case 0x89: // psp_ns 4562 case 0x90: // primask_ns 4563 case 0x94: // control_ns 4564 case 0x98: // sp_ns 4565 if (!(FeatureBits[ARM::Feature8MSecExt])) 4566 return MCDisassembler::Fail; 4567 break; 4568 default: 4569 // Architecturally defined as unpredictable 4570 S = MCDisassembler::SoftFail; 4571 break; 4572 } 4573 4574 if (Inst.getOpcode() == ARM::t2MSR_M) { 4575 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4576 if (!(FeatureBits[ARM::HasV7Ops])) { 4577 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4578 // unpredictable. 4579 if (Mask != 2) 4580 S = MCDisassembler::SoftFail; 4581 } 4582 else { 4583 // The ARMv7-M architecture stores an additional 2-bit mask value in 4584 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4585 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4586 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4587 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4588 // only if the processor includes the DSP extension. 4589 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4590 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4591 S = MCDisassembler::SoftFail; 4592 } 4593 } 4594 } else { 4595 // A/R class 4596 if (Val == 0) 4597 return MCDisassembler::Fail; 4598 } 4599 Inst.addOperand(MCOperand::createImm(Val)); 4600 return S; 4601 } 4602 4603 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4604 uint64_t Address, const void *Decoder) { 4605 unsigned R = fieldFromInstruction(Val, 5, 1); 4606 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4607 4608 // The table of encodings for these banked registers comes from B9.2.3 of the 4609 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4610 // neater. So by fiat, these values are UNPREDICTABLE: 4611 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4612 return MCDisassembler::Fail; 4613 4614 Inst.addOperand(MCOperand::createImm(Val)); 4615 return MCDisassembler::Success; 4616 } 4617 4618 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4619 uint64_t Address, const void *Decoder) { 4620 DecodeStatus S = MCDisassembler::Success; 4621 4622 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4623 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4624 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4625 4626 if (Rn == 0xF) 4627 S = MCDisassembler::SoftFail; 4628 4629 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4630 return MCDisassembler::Fail; 4631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4632 return MCDisassembler::Fail; 4633 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4634 return MCDisassembler::Fail; 4635 4636 return S; 4637 } 4638 4639 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4640 uint64_t Address, 4641 const void *Decoder) { 4642 DecodeStatus S = MCDisassembler::Success; 4643 4644 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4645 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4646 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4647 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4648 4649 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4650 return MCDisassembler::Fail; 4651 4652 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4653 S = MCDisassembler::SoftFail; 4654 4655 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4656 return MCDisassembler::Fail; 4657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4658 return MCDisassembler::Fail; 4659 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4660 return MCDisassembler::Fail; 4661 4662 return S; 4663 } 4664 4665 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4666 uint64_t Address, const void *Decoder) { 4667 DecodeStatus S = MCDisassembler::Success; 4668 4669 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4670 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4671 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4672 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4673 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4674 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4675 4676 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4677 4678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4681 return MCDisassembler::Fail; 4682 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4683 return MCDisassembler::Fail; 4684 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4685 return MCDisassembler::Fail; 4686 4687 return S; 4688 } 4689 4690 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4691 uint64_t Address, const void *Decoder) { 4692 DecodeStatus S = MCDisassembler::Success; 4693 4694 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4695 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4696 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4697 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4698 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4699 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4700 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4701 4702 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4703 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4704 4705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4706 return MCDisassembler::Fail; 4707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4708 return MCDisassembler::Fail; 4709 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4710 return MCDisassembler::Fail; 4711 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4712 return MCDisassembler::Fail; 4713 4714 return S; 4715 } 4716 4717 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4718 uint64_t Address, const void *Decoder) { 4719 DecodeStatus S = MCDisassembler::Success; 4720 4721 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4722 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4723 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4724 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4725 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4726 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4727 4728 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4729 4730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4731 return MCDisassembler::Fail; 4732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4733 return MCDisassembler::Fail; 4734 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4735 return MCDisassembler::Fail; 4736 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4737 return MCDisassembler::Fail; 4738 4739 return S; 4740 } 4741 4742 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4743 uint64_t Address, const void *Decoder) { 4744 DecodeStatus S = MCDisassembler::Success; 4745 4746 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4747 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4748 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4749 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4750 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4751 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4752 4753 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4754 4755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4756 return MCDisassembler::Fail; 4757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4758 return MCDisassembler::Fail; 4759 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4760 return MCDisassembler::Fail; 4761 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4762 return MCDisassembler::Fail; 4763 4764 return S; 4765 } 4766 4767 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4768 uint64_t Address, const void *Decoder) { 4769 DecodeStatus S = MCDisassembler::Success; 4770 4771 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4772 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4773 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4774 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4775 unsigned size = fieldFromInstruction(Insn, 10, 2); 4776 4777 unsigned align = 0; 4778 unsigned index = 0; 4779 switch (size) { 4780 default: 4781 return MCDisassembler::Fail; 4782 case 0: 4783 if (fieldFromInstruction(Insn, 4, 1)) 4784 return MCDisassembler::Fail; // UNDEFINED 4785 index = fieldFromInstruction(Insn, 5, 3); 4786 break; 4787 case 1: 4788 if (fieldFromInstruction(Insn, 5, 1)) 4789 return MCDisassembler::Fail; // UNDEFINED 4790 index = fieldFromInstruction(Insn, 6, 2); 4791 if (fieldFromInstruction(Insn, 4, 1)) 4792 align = 2; 4793 break; 4794 case 2: 4795 if (fieldFromInstruction(Insn, 6, 1)) 4796 return MCDisassembler::Fail; // UNDEFINED 4797 index = fieldFromInstruction(Insn, 7, 1); 4798 4799 switch (fieldFromInstruction(Insn, 4, 2)) { 4800 case 0 : 4801 align = 0; break; 4802 case 3: 4803 align = 4; break; 4804 default: 4805 return MCDisassembler::Fail; 4806 } 4807 break; 4808 } 4809 4810 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4811 return MCDisassembler::Fail; 4812 if (Rm != 0xF) { // Writeback 4813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4814 return MCDisassembler::Fail; 4815 } 4816 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4817 return MCDisassembler::Fail; 4818 Inst.addOperand(MCOperand::createImm(align)); 4819 if (Rm != 0xF) { 4820 if (Rm != 0xD) { 4821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4822 return MCDisassembler::Fail; 4823 } else 4824 Inst.addOperand(MCOperand::createReg(0)); 4825 } 4826 4827 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4828 return MCDisassembler::Fail; 4829 Inst.addOperand(MCOperand::createImm(index)); 4830 4831 return S; 4832 } 4833 4834 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4835 uint64_t Address, const void *Decoder) { 4836 DecodeStatus S = MCDisassembler::Success; 4837 4838 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4839 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4840 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4841 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4842 unsigned size = fieldFromInstruction(Insn, 10, 2); 4843 4844 unsigned align = 0; 4845 unsigned index = 0; 4846 switch (size) { 4847 default: 4848 return MCDisassembler::Fail; 4849 case 0: 4850 if (fieldFromInstruction(Insn, 4, 1)) 4851 return MCDisassembler::Fail; // UNDEFINED 4852 index = fieldFromInstruction(Insn, 5, 3); 4853 break; 4854 case 1: 4855 if (fieldFromInstruction(Insn, 5, 1)) 4856 return MCDisassembler::Fail; // UNDEFINED 4857 index = fieldFromInstruction(Insn, 6, 2); 4858 if (fieldFromInstruction(Insn, 4, 1)) 4859 align = 2; 4860 break; 4861 case 2: 4862 if (fieldFromInstruction(Insn, 6, 1)) 4863 return MCDisassembler::Fail; // UNDEFINED 4864 index = fieldFromInstruction(Insn, 7, 1); 4865 4866 switch (fieldFromInstruction(Insn, 4, 2)) { 4867 case 0: 4868 align = 0; break; 4869 case 3: 4870 align = 4; break; 4871 default: 4872 return MCDisassembler::Fail; 4873 } 4874 break; 4875 } 4876 4877 if (Rm != 0xF) { // Writeback 4878 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4879 return MCDisassembler::Fail; 4880 } 4881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4882 return MCDisassembler::Fail; 4883 Inst.addOperand(MCOperand::createImm(align)); 4884 if (Rm != 0xF) { 4885 if (Rm != 0xD) { 4886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4887 return MCDisassembler::Fail; 4888 } else 4889 Inst.addOperand(MCOperand::createReg(0)); 4890 } 4891 4892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4893 return MCDisassembler::Fail; 4894 Inst.addOperand(MCOperand::createImm(index)); 4895 4896 return S; 4897 } 4898 4899 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4900 uint64_t Address, const void *Decoder) { 4901 DecodeStatus S = MCDisassembler::Success; 4902 4903 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4904 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4905 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4906 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4907 unsigned size = fieldFromInstruction(Insn, 10, 2); 4908 4909 unsigned align = 0; 4910 unsigned index = 0; 4911 unsigned inc = 1; 4912 switch (size) { 4913 default: 4914 return MCDisassembler::Fail; 4915 case 0: 4916 index = fieldFromInstruction(Insn, 5, 3); 4917 if (fieldFromInstruction(Insn, 4, 1)) 4918 align = 2; 4919 break; 4920 case 1: 4921 index = fieldFromInstruction(Insn, 6, 2); 4922 if (fieldFromInstruction(Insn, 4, 1)) 4923 align = 4; 4924 if (fieldFromInstruction(Insn, 5, 1)) 4925 inc = 2; 4926 break; 4927 case 2: 4928 if (fieldFromInstruction(Insn, 5, 1)) 4929 return MCDisassembler::Fail; // UNDEFINED 4930 index = fieldFromInstruction(Insn, 7, 1); 4931 if (fieldFromInstruction(Insn, 4, 1) != 0) 4932 align = 8; 4933 if (fieldFromInstruction(Insn, 6, 1)) 4934 inc = 2; 4935 break; 4936 } 4937 4938 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4939 return MCDisassembler::Fail; 4940 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4941 return MCDisassembler::Fail; 4942 if (Rm != 0xF) { // Writeback 4943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4944 return MCDisassembler::Fail; 4945 } 4946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4947 return MCDisassembler::Fail; 4948 Inst.addOperand(MCOperand::createImm(align)); 4949 if (Rm != 0xF) { 4950 if (Rm != 0xD) { 4951 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4952 return MCDisassembler::Fail; 4953 } else 4954 Inst.addOperand(MCOperand::createReg(0)); 4955 } 4956 4957 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4958 return MCDisassembler::Fail; 4959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4960 return MCDisassembler::Fail; 4961 Inst.addOperand(MCOperand::createImm(index)); 4962 4963 return S; 4964 } 4965 4966 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4967 uint64_t Address, const void *Decoder) { 4968 DecodeStatus S = MCDisassembler::Success; 4969 4970 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4971 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4972 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4973 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4974 unsigned size = fieldFromInstruction(Insn, 10, 2); 4975 4976 unsigned align = 0; 4977 unsigned index = 0; 4978 unsigned inc = 1; 4979 switch (size) { 4980 default: 4981 return MCDisassembler::Fail; 4982 case 0: 4983 index = fieldFromInstruction(Insn, 5, 3); 4984 if (fieldFromInstruction(Insn, 4, 1)) 4985 align = 2; 4986 break; 4987 case 1: 4988 index = fieldFromInstruction(Insn, 6, 2); 4989 if (fieldFromInstruction(Insn, 4, 1)) 4990 align = 4; 4991 if (fieldFromInstruction(Insn, 5, 1)) 4992 inc = 2; 4993 break; 4994 case 2: 4995 if (fieldFromInstruction(Insn, 5, 1)) 4996 return MCDisassembler::Fail; // UNDEFINED 4997 index = fieldFromInstruction(Insn, 7, 1); 4998 if (fieldFromInstruction(Insn, 4, 1) != 0) 4999 align = 8; 5000 if (fieldFromInstruction(Insn, 6, 1)) 5001 inc = 2; 5002 break; 5003 } 5004 5005 if (Rm != 0xF) { // Writeback 5006 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5007 return MCDisassembler::Fail; 5008 } 5009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5010 return MCDisassembler::Fail; 5011 Inst.addOperand(MCOperand::createImm(align)); 5012 if (Rm != 0xF) { 5013 if (Rm != 0xD) { 5014 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5015 return MCDisassembler::Fail; 5016 } else 5017 Inst.addOperand(MCOperand::createReg(0)); 5018 } 5019 5020 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5021 return MCDisassembler::Fail; 5022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5023 return MCDisassembler::Fail; 5024 Inst.addOperand(MCOperand::createImm(index)); 5025 5026 return S; 5027 } 5028 5029 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5030 uint64_t Address, const void *Decoder) { 5031 DecodeStatus S = MCDisassembler::Success; 5032 5033 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5034 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5035 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5036 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5037 unsigned size = fieldFromInstruction(Insn, 10, 2); 5038 5039 unsigned align = 0; 5040 unsigned index = 0; 5041 unsigned inc = 1; 5042 switch (size) { 5043 default: 5044 return MCDisassembler::Fail; 5045 case 0: 5046 if (fieldFromInstruction(Insn, 4, 1)) 5047 return MCDisassembler::Fail; // UNDEFINED 5048 index = fieldFromInstruction(Insn, 5, 3); 5049 break; 5050 case 1: 5051 if (fieldFromInstruction(Insn, 4, 1)) 5052 return MCDisassembler::Fail; // UNDEFINED 5053 index = fieldFromInstruction(Insn, 6, 2); 5054 if (fieldFromInstruction(Insn, 5, 1)) 5055 inc = 2; 5056 break; 5057 case 2: 5058 if (fieldFromInstruction(Insn, 4, 2)) 5059 return MCDisassembler::Fail; // UNDEFINED 5060 index = fieldFromInstruction(Insn, 7, 1); 5061 if (fieldFromInstruction(Insn, 6, 1)) 5062 inc = 2; 5063 break; 5064 } 5065 5066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5067 return MCDisassembler::Fail; 5068 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5069 return MCDisassembler::Fail; 5070 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5071 return MCDisassembler::Fail; 5072 5073 if (Rm != 0xF) { // Writeback 5074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5075 return MCDisassembler::Fail; 5076 } 5077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5078 return MCDisassembler::Fail; 5079 Inst.addOperand(MCOperand::createImm(align)); 5080 if (Rm != 0xF) { 5081 if (Rm != 0xD) { 5082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5083 return MCDisassembler::Fail; 5084 } else 5085 Inst.addOperand(MCOperand::createReg(0)); 5086 } 5087 5088 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5089 return MCDisassembler::Fail; 5090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5091 return MCDisassembler::Fail; 5092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5093 return MCDisassembler::Fail; 5094 Inst.addOperand(MCOperand::createImm(index)); 5095 5096 return S; 5097 } 5098 5099 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5100 uint64_t Address, const void *Decoder) { 5101 DecodeStatus S = MCDisassembler::Success; 5102 5103 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5104 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5105 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5106 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5107 unsigned size = fieldFromInstruction(Insn, 10, 2); 5108 5109 unsigned align = 0; 5110 unsigned index = 0; 5111 unsigned inc = 1; 5112 switch (size) { 5113 default: 5114 return MCDisassembler::Fail; 5115 case 0: 5116 if (fieldFromInstruction(Insn, 4, 1)) 5117 return MCDisassembler::Fail; // UNDEFINED 5118 index = fieldFromInstruction(Insn, 5, 3); 5119 break; 5120 case 1: 5121 if (fieldFromInstruction(Insn, 4, 1)) 5122 return MCDisassembler::Fail; // UNDEFINED 5123 index = fieldFromInstruction(Insn, 6, 2); 5124 if (fieldFromInstruction(Insn, 5, 1)) 5125 inc = 2; 5126 break; 5127 case 2: 5128 if (fieldFromInstruction(Insn, 4, 2)) 5129 return MCDisassembler::Fail; // UNDEFINED 5130 index = fieldFromInstruction(Insn, 7, 1); 5131 if (fieldFromInstruction(Insn, 6, 1)) 5132 inc = 2; 5133 break; 5134 } 5135 5136 if (Rm != 0xF) { // Writeback 5137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5138 return MCDisassembler::Fail; 5139 } 5140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5141 return MCDisassembler::Fail; 5142 Inst.addOperand(MCOperand::createImm(align)); 5143 if (Rm != 0xF) { 5144 if (Rm != 0xD) { 5145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5146 return MCDisassembler::Fail; 5147 } else 5148 Inst.addOperand(MCOperand::createReg(0)); 5149 } 5150 5151 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5152 return MCDisassembler::Fail; 5153 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5154 return MCDisassembler::Fail; 5155 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5156 return MCDisassembler::Fail; 5157 Inst.addOperand(MCOperand::createImm(index)); 5158 5159 return S; 5160 } 5161 5162 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5163 uint64_t Address, const void *Decoder) { 5164 DecodeStatus S = MCDisassembler::Success; 5165 5166 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5167 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5168 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5169 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5170 unsigned size = fieldFromInstruction(Insn, 10, 2); 5171 5172 unsigned align = 0; 5173 unsigned index = 0; 5174 unsigned inc = 1; 5175 switch (size) { 5176 default: 5177 return MCDisassembler::Fail; 5178 case 0: 5179 if (fieldFromInstruction(Insn, 4, 1)) 5180 align = 4; 5181 index = fieldFromInstruction(Insn, 5, 3); 5182 break; 5183 case 1: 5184 if (fieldFromInstruction(Insn, 4, 1)) 5185 align = 8; 5186 index = fieldFromInstruction(Insn, 6, 2); 5187 if (fieldFromInstruction(Insn, 5, 1)) 5188 inc = 2; 5189 break; 5190 case 2: 5191 switch (fieldFromInstruction(Insn, 4, 2)) { 5192 case 0: 5193 align = 0; break; 5194 case 3: 5195 return MCDisassembler::Fail; 5196 default: 5197 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5198 } 5199 5200 index = fieldFromInstruction(Insn, 7, 1); 5201 if (fieldFromInstruction(Insn, 6, 1)) 5202 inc = 2; 5203 break; 5204 } 5205 5206 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5207 return MCDisassembler::Fail; 5208 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5209 return MCDisassembler::Fail; 5210 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5211 return MCDisassembler::Fail; 5212 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5213 return MCDisassembler::Fail; 5214 5215 if (Rm != 0xF) { // Writeback 5216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5217 return MCDisassembler::Fail; 5218 } 5219 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5220 return MCDisassembler::Fail; 5221 Inst.addOperand(MCOperand::createImm(align)); 5222 if (Rm != 0xF) { 5223 if (Rm != 0xD) { 5224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5225 return MCDisassembler::Fail; 5226 } else 5227 Inst.addOperand(MCOperand::createReg(0)); 5228 } 5229 5230 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5231 return MCDisassembler::Fail; 5232 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5233 return MCDisassembler::Fail; 5234 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5235 return MCDisassembler::Fail; 5236 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5237 return MCDisassembler::Fail; 5238 Inst.addOperand(MCOperand::createImm(index)); 5239 5240 return S; 5241 } 5242 5243 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5244 uint64_t Address, const void *Decoder) { 5245 DecodeStatus S = MCDisassembler::Success; 5246 5247 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5248 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5249 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5250 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5251 unsigned size = fieldFromInstruction(Insn, 10, 2); 5252 5253 unsigned align = 0; 5254 unsigned index = 0; 5255 unsigned inc = 1; 5256 switch (size) { 5257 default: 5258 return MCDisassembler::Fail; 5259 case 0: 5260 if (fieldFromInstruction(Insn, 4, 1)) 5261 align = 4; 5262 index = fieldFromInstruction(Insn, 5, 3); 5263 break; 5264 case 1: 5265 if (fieldFromInstruction(Insn, 4, 1)) 5266 align = 8; 5267 index = fieldFromInstruction(Insn, 6, 2); 5268 if (fieldFromInstruction(Insn, 5, 1)) 5269 inc = 2; 5270 break; 5271 case 2: 5272 switch (fieldFromInstruction(Insn, 4, 2)) { 5273 case 0: 5274 align = 0; break; 5275 case 3: 5276 return MCDisassembler::Fail; 5277 default: 5278 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5279 } 5280 5281 index = fieldFromInstruction(Insn, 7, 1); 5282 if (fieldFromInstruction(Insn, 6, 1)) 5283 inc = 2; 5284 break; 5285 } 5286 5287 if (Rm != 0xF) { // Writeback 5288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5289 return MCDisassembler::Fail; 5290 } 5291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5292 return MCDisassembler::Fail; 5293 Inst.addOperand(MCOperand::createImm(align)); 5294 if (Rm != 0xF) { 5295 if (Rm != 0xD) { 5296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5297 return MCDisassembler::Fail; 5298 } else 5299 Inst.addOperand(MCOperand::createReg(0)); 5300 } 5301 5302 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5303 return MCDisassembler::Fail; 5304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5305 return MCDisassembler::Fail; 5306 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5307 return MCDisassembler::Fail; 5308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5309 return MCDisassembler::Fail; 5310 Inst.addOperand(MCOperand::createImm(index)); 5311 5312 return S; 5313 } 5314 5315 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5316 uint64_t Address, const void *Decoder) { 5317 DecodeStatus S = MCDisassembler::Success; 5318 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5319 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5320 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5321 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5322 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5323 5324 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5325 S = MCDisassembler::SoftFail; 5326 5327 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5328 return MCDisassembler::Fail; 5329 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5330 return MCDisassembler::Fail; 5331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5332 return MCDisassembler::Fail; 5333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5334 return MCDisassembler::Fail; 5335 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5336 return MCDisassembler::Fail; 5337 5338 return S; 5339 } 5340 5341 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5342 uint64_t Address, const void *Decoder) { 5343 DecodeStatus S = MCDisassembler::Success; 5344 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5345 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5346 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5347 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5348 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5349 5350 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5351 S = MCDisassembler::SoftFail; 5352 5353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5354 return MCDisassembler::Fail; 5355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5356 return MCDisassembler::Fail; 5357 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5358 return MCDisassembler::Fail; 5359 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5360 return MCDisassembler::Fail; 5361 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5362 return MCDisassembler::Fail; 5363 5364 return S; 5365 } 5366 5367 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5368 uint64_t Address, const void *Decoder) { 5369 DecodeStatus S = MCDisassembler::Success; 5370 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5371 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5372 5373 if (pred == 0xF) { 5374 pred = 0xE; 5375 S = MCDisassembler::SoftFail; 5376 } 5377 5378 if (mask == 0x0) 5379 return MCDisassembler::Fail; 5380 5381 // IT masks are encoded as a sequence of replacement low-order bits 5382 // for the condition code. So if the low bit of the starting 5383 // condition code is 1, then we have to flip all the bits above the 5384 // terminating bit (which is the lowest 1 bit). 5385 if (pred & 1) { 5386 unsigned LowBit = mask & -mask; 5387 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5388 mask ^= BitsAboveLowBit; 5389 } 5390 5391 Inst.addOperand(MCOperand::createImm(pred)); 5392 Inst.addOperand(MCOperand::createImm(mask)); 5393 return S; 5394 } 5395 5396 static DecodeStatus 5397 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5398 uint64_t Address, const void *Decoder) { 5399 DecodeStatus S = MCDisassembler::Success; 5400 5401 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5402 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5403 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5404 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5405 unsigned W = fieldFromInstruction(Insn, 21, 1); 5406 unsigned U = fieldFromInstruction(Insn, 23, 1); 5407 unsigned P = fieldFromInstruction(Insn, 24, 1); 5408 bool writeback = (W == 1) | (P == 0); 5409 5410 addr |= (U << 8) | (Rn << 9); 5411 5412 if (writeback && (Rn == Rt || Rn == Rt2)) 5413 Check(S, MCDisassembler::SoftFail); 5414 if (Rt == Rt2) 5415 Check(S, MCDisassembler::SoftFail); 5416 5417 // Rt 5418 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5419 return MCDisassembler::Fail; 5420 // Rt2 5421 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5422 return MCDisassembler::Fail; 5423 // Writeback operand 5424 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5425 return MCDisassembler::Fail; 5426 // addr 5427 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5428 return MCDisassembler::Fail; 5429 5430 return S; 5431 } 5432 5433 static DecodeStatus 5434 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5435 uint64_t Address, const void *Decoder) { 5436 DecodeStatus S = MCDisassembler::Success; 5437 5438 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5439 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5440 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5441 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5442 unsigned W = fieldFromInstruction(Insn, 21, 1); 5443 unsigned U = fieldFromInstruction(Insn, 23, 1); 5444 unsigned P = fieldFromInstruction(Insn, 24, 1); 5445 bool writeback = (W == 1) | (P == 0); 5446 5447 addr |= (U << 8) | (Rn << 9); 5448 5449 if (writeback && (Rn == Rt || Rn == Rt2)) 5450 Check(S, MCDisassembler::SoftFail); 5451 5452 // Writeback operand 5453 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5454 return MCDisassembler::Fail; 5455 // Rt 5456 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5457 return MCDisassembler::Fail; 5458 // Rt2 5459 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5460 return MCDisassembler::Fail; 5461 // addr 5462 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5463 return MCDisassembler::Fail; 5464 5465 return S; 5466 } 5467 5468 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5469 uint64_t Address, const void *Decoder) { 5470 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5471 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5472 if (sign1 != sign2) return MCDisassembler::Fail; 5473 5474 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5475 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5476 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5477 Val |= sign1 << 12; 5478 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5479 5480 return MCDisassembler::Success; 5481 } 5482 5483 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5484 uint64_t Address, 5485 const void *Decoder) { 5486 DecodeStatus S = MCDisassembler::Success; 5487 5488 // Shift of "asr #32" is not allowed in Thumb2 mode. 5489 if (Val == 0x20) S = MCDisassembler::Fail; 5490 Inst.addOperand(MCOperand::createImm(Val)); 5491 return S; 5492 } 5493 5494 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5495 uint64_t Address, const void *Decoder) { 5496 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5497 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5498 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5499 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5500 5501 if (pred == 0xF) 5502 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5503 5504 DecodeStatus S = MCDisassembler::Success; 5505 5506 if (Rt == Rn || Rn == Rt2) 5507 S = MCDisassembler::SoftFail; 5508 5509 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5510 return MCDisassembler::Fail; 5511 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5512 return MCDisassembler::Fail; 5513 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5514 return MCDisassembler::Fail; 5515 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5516 return MCDisassembler::Fail; 5517 5518 return S; 5519 } 5520 5521 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5522 uint64_t Address, const void *Decoder) { 5523 const FeatureBitset &featureBits = 5524 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5525 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5526 5527 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5528 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5529 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5530 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5531 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5532 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5533 unsigned op = fieldFromInstruction(Insn, 5, 1); 5534 5535 DecodeStatus S = MCDisassembler::Success; 5536 5537 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5538 if (!(imm & 0x38)) { 5539 if (cmode == 0xF) { 5540 if (op == 1) return MCDisassembler::Fail; 5541 Inst.setOpcode(ARM::VMOVv2f32); 5542 } 5543 if (hasFullFP16) { 5544 if (cmode == 0xE) { 5545 if (op == 1) { 5546 Inst.setOpcode(ARM::VMOVv1i64); 5547 } else { 5548 Inst.setOpcode(ARM::VMOVv8i8); 5549 } 5550 } 5551 if (cmode == 0xD) { 5552 if (op == 1) { 5553 Inst.setOpcode(ARM::VMVNv2i32); 5554 } else { 5555 Inst.setOpcode(ARM::VMOVv2i32); 5556 } 5557 } 5558 if (cmode == 0xC) { 5559 if (op == 1) { 5560 Inst.setOpcode(ARM::VMVNv2i32); 5561 } else { 5562 Inst.setOpcode(ARM::VMOVv2i32); 5563 } 5564 } 5565 } 5566 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5567 } 5568 5569 if (!(imm & 0x20)) return MCDisassembler::Fail; 5570 5571 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5572 return MCDisassembler::Fail; 5573 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5574 return MCDisassembler::Fail; 5575 Inst.addOperand(MCOperand::createImm(64 - imm)); 5576 5577 return S; 5578 } 5579 5580 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5581 uint64_t Address, const void *Decoder) { 5582 const FeatureBitset &featureBits = 5583 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5584 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5585 5586 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5587 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5588 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5589 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5590 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5591 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5592 unsigned op = fieldFromInstruction(Insn, 5, 1); 5593 5594 DecodeStatus S = MCDisassembler::Success; 5595 5596 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5597 if (!(imm & 0x38)) { 5598 if (cmode == 0xF) { 5599 if (op == 1) return MCDisassembler::Fail; 5600 Inst.setOpcode(ARM::VMOVv4f32); 5601 } 5602 if (hasFullFP16) { 5603 if (cmode == 0xE) { 5604 if (op == 1) { 5605 Inst.setOpcode(ARM::VMOVv2i64); 5606 } else { 5607 Inst.setOpcode(ARM::VMOVv16i8); 5608 } 5609 } 5610 if (cmode == 0xD) { 5611 if (op == 1) { 5612 Inst.setOpcode(ARM::VMVNv4i32); 5613 } else { 5614 Inst.setOpcode(ARM::VMOVv4i32); 5615 } 5616 } 5617 if (cmode == 0xC) { 5618 if (op == 1) { 5619 Inst.setOpcode(ARM::VMVNv4i32); 5620 } else { 5621 Inst.setOpcode(ARM::VMOVv4i32); 5622 } 5623 } 5624 } 5625 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5626 } 5627 5628 if (!(imm & 0x20)) return MCDisassembler::Fail; 5629 5630 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5631 return MCDisassembler::Fail; 5632 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5633 return MCDisassembler::Fail; 5634 Inst.addOperand(MCOperand::createImm(64 - imm)); 5635 5636 return S; 5637 } 5638 5639 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5640 unsigned Insn, 5641 uint64_t Address, 5642 const void *Decoder) { 5643 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5644 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5645 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5646 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5647 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5648 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5649 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5650 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5651 5652 DecodeStatus S = MCDisassembler::Success; 5653 5654 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5655 5656 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5657 return MCDisassembler::Fail; 5658 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5659 return MCDisassembler::Fail; 5660 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5661 return MCDisassembler::Fail; 5662 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5663 return MCDisassembler::Fail; 5664 // The lane index does not have any bits in the encoding, because it can only 5665 // be 0. 5666 Inst.addOperand(MCOperand::createImm(0)); 5667 Inst.addOperand(MCOperand::createImm(rotate)); 5668 5669 return S; 5670 } 5671 5672 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5673 uint64_t Address, const void *Decoder) { 5674 DecodeStatus S = MCDisassembler::Success; 5675 5676 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5677 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5678 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5679 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5680 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5681 5682 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5683 S = MCDisassembler::SoftFail; 5684 5685 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5686 return MCDisassembler::Fail; 5687 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5688 return MCDisassembler::Fail; 5689 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5690 return MCDisassembler::Fail; 5691 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5692 return MCDisassembler::Fail; 5693 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5694 return MCDisassembler::Fail; 5695 5696 return S; 5697 } 5698 5699 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5700 uint64_t Address, const void *Decoder) { 5701 DecodeStatus S = MCDisassembler::Success; 5702 5703 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5704 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5705 unsigned cop = fieldFromInstruction(Val, 8, 4); 5706 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5707 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5708 5709 if ((cop & ~0x1) == 0xa) 5710 return MCDisassembler::Fail; 5711 5712 if (Rt == Rt2) 5713 S = MCDisassembler::SoftFail; 5714 5715 // We have to check if the instruction is MRRC2 5716 // or MCRR2 when constructing the operands for 5717 // Inst. Reason is because MRRC2 stores to two 5718 // registers so it's tablegen desc has has two 5719 // outputs whereas MCRR doesn't store to any 5720 // registers so all of it's operands are listed 5721 // as inputs, therefore the operand order for 5722 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5723 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5724 5725 if (Inst.getOpcode() == ARM::MRRC2) { 5726 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5727 return MCDisassembler::Fail; 5728 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5729 return MCDisassembler::Fail; 5730 } 5731 Inst.addOperand(MCOperand::createImm(cop)); 5732 Inst.addOperand(MCOperand::createImm(opc1)); 5733 if (Inst.getOpcode() == ARM::MCRR2) { 5734 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5735 return MCDisassembler::Fail; 5736 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5737 return MCDisassembler::Fail; 5738 } 5739 Inst.addOperand(MCOperand::createImm(CRm)); 5740 5741 return S; 5742 } 5743 5744 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5745 uint64_t Address, 5746 const void *Decoder) { 5747 const FeatureBitset &featureBits = 5748 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5749 DecodeStatus S = MCDisassembler::Success; 5750 5751 // Add explicit operand for the destination sysreg, for cases where 5752 // we have to model it for code generation purposes. 5753 switch (Inst.getOpcode()) { 5754 case ARM::VMSR_FPSCR_NZCVQC: 5755 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5756 break; 5757 case ARM::VMSR_P0: 5758 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5759 break; 5760 } 5761 5762 if (Inst.getOpcode() != ARM::FMSTAT) { 5763 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5764 5765 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5766 if (Rt == 13 || Rt == 15) 5767 S = MCDisassembler::SoftFail; 5768 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5769 } else 5770 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5771 } 5772 5773 // Add explicit operand for the source sysreg, similarly to above. 5774 switch (Inst.getOpcode()) { 5775 case ARM::VMRS_FPSCR_NZCVQC: 5776 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5777 break; 5778 case ARM::VMRS_P0: 5779 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5780 break; 5781 } 5782 5783 if (featureBits[ARM::ModeThumb]) { 5784 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5785 Inst.addOperand(MCOperand::createReg(0)); 5786 } else { 5787 unsigned pred = fieldFromInstruction(Val, 28, 4); 5788 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5789 return MCDisassembler::Fail; 5790 } 5791 5792 return S; 5793 } 5794 5795 template <bool isSigned, bool isNeg, int size> 5796 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5797 uint64_t Address, 5798 const void *Decoder) { 5799 DecodeStatus S = MCDisassembler::Success; 5800 if (Val == 0) 5801 S = MCDisassembler::SoftFail; 5802 5803 uint64_t DecVal; 5804 if (isSigned) 5805 DecVal = SignExtend32<size + 1>(Val << 1); 5806 else 5807 DecVal = (Val << 1); 5808 5809 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5810 Decoder)) 5811 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5812 return S; 5813 } 5814 5815 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5816 uint64_t Address, 5817 const void *Decoder) { 5818 5819 uint64_t LocImm = Inst.getOperand(0).getImm(); 5820 Val = LocImm + (2 << Val); 5821 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5822 Decoder)) 5823 Inst.addOperand(MCOperand::createImm(Val)); 5824 return MCDisassembler::Success; 5825 } 5826 5827 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5828 uint64_t Address, 5829 const void *Decoder) { 5830 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5831 return MCDisassembler::Fail; 5832 Inst.addOperand(MCOperand::createImm(Val)); 5833 return MCDisassembler::Success; 5834 } 5835 5836 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5837 const void *Decoder) { 5838 DecodeStatus S = MCDisassembler::Success; 5839 5840 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5841 fieldFromInstruction(Insn, 1, 10) << 1; 5842 switch (Inst.getOpcode()) { 5843 case ARM::t2LEUpdate: 5844 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5845 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5846 LLVM_FALLTHROUGH; 5847 case ARM::t2LE: 5848 if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address, 5849 Decoder))) 5850 return MCDisassembler::Fail; 5851 break; 5852 case ARM::t2WLS: 5853 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5854 if (!Check(S, 5855 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5856 Address, Decoder)) || 5857 !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address, 5858 Decoder))) 5859 return MCDisassembler::Fail; 5860 break; 5861 case ARM::t2DLS: 5862 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5863 if (Rn == 0xF) { 5864 return MCDisassembler::Fail; 5865 } else { 5866 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5867 if (!Check(S, DecoderGPRRegisterClass(Inst, 5868 fieldFromInstruction(Insn, 16, 4), 5869 Address, Decoder))) 5870 return MCDisassembler::Fail; 5871 } 5872 break; 5873 } 5874 return S; 5875 } 5876 5877 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 5878 uint64_t Address, 5879 const void *Decoder) { 5880 DecodeStatus S = MCDisassembler::Success; 5881 5882 if (Val == 0) 5883 Val = 32; 5884 5885 Inst.addOperand(MCOperand::createImm(Val)); 5886 5887 return S; 5888 } 5889 5890 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 5891 uint64_t Address, const void *Decoder) { 5892 if ((RegNo) + 1 > 11) 5893 return MCDisassembler::Fail; 5894 5895 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 5896 Inst.addOperand(MCOperand::createReg(Register)); 5897 return MCDisassembler::Success; 5898 } 5899 5900 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 5901 uint64_t Address, const void *Decoder) { 5902 if ((RegNo) > 14) 5903 return MCDisassembler::Fail; 5904 5905 unsigned Register = GPRDecoderTable[(RegNo)]; 5906 Inst.addOperand(MCOperand::createReg(Register)); 5907 return MCDisassembler::Success; 5908 } 5909 5910 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 5911 const void *Decoder) { 5912 DecodeStatus S = MCDisassembler::Success; 5913 5914 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5915 Inst.addOperand(MCOperand::createReg(0)); 5916 if (Inst.getOpcode() == ARM::VSCCLRMD) { 5917 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 5918 (fieldFromInstruction(Insn, 12, 4) << 8) | 5919 (fieldFromInstruction(Insn, 22, 1) << 12); 5920 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 5921 return MCDisassembler::Fail; 5922 } 5923 } else { 5924 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 5925 (fieldFromInstruction(Insn, 22, 1) << 8) | 5926 (fieldFromInstruction(Insn, 12, 4) << 9); 5927 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 5928 return MCDisassembler::Fail; 5929 } 5930 } 5931 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5932 5933 return S; 5934 } 5935 5936 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 5937 uint64_t Address, 5938 const void *Decoder) { 5939 if (RegNo > 7) 5940 return MCDisassembler::Fail; 5941 5942 unsigned Register = QPRDecoderTable[RegNo]; 5943 Inst.addOperand(MCOperand::createReg(Register)); 5944 return MCDisassembler::Success; 5945 } 5946 5947 static const uint16_t QQPRDecoderTable[] = { 5948 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 5949 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 5950 }; 5951 5952 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 5953 uint64_t Address, 5954 const void *Decoder) { 5955 if (RegNo > 6) 5956 return MCDisassembler::Fail; 5957 5958 unsigned Register = QQPRDecoderTable[RegNo]; 5959 Inst.addOperand(MCOperand::createReg(Register)); 5960 return MCDisassembler::Success; 5961 } 5962 5963 static const uint16_t QQQQPRDecoderTable[] = { 5964 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 5965 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 5966 }; 5967 5968 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 5969 uint64_t Address, 5970 const void *Decoder) { 5971 if (RegNo > 4) 5972 return MCDisassembler::Fail; 5973 5974 unsigned Register = QQQQPRDecoderTable[RegNo]; 5975 Inst.addOperand(MCOperand::createReg(Register)); 5976 return MCDisassembler::Success; 5977 } 5978 5979 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 5980 uint64_t Address, 5981 const void *Decoder) { 5982 DecodeStatus S = MCDisassembler::Success; 5983 5984 // Parse VPT mask and encode it in the MCInst as an immediate with the same 5985 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 5986 // 't' as 0 and finish with a 1. 5987 unsigned Imm = 0; 5988 // We always start with a 't'. 5989 unsigned CurBit = 0; 5990 for (int i = 3; i >= 0; --i) { 5991 // If the bit we are looking at is not the same as last one, invert the 5992 // CurBit, if it is the same leave it as is. 5993 CurBit ^= (Val >> i) & 1U; 5994 5995 // Encode the CurBit at the right place in the immediate. 5996 Imm |= (CurBit << i); 5997 5998 // If we are done, finish the encoding with a 1. 5999 if ((Val & ~(~0U << i)) == 0) { 6000 Imm |= 1U << i; 6001 break; 6002 } 6003 } 6004 6005 Inst.addOperand(MCOperand::createImm(Imm)); 6006 6007 return S; 6008 } 6009 6010 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6011 uint64_t Address, const void *Decoder) { 6012 // The vpred_r operand type includes an MQPR register field derived 6013 // from the encoding. But we don't actually want to add an operand 6014 // to the MCInst at this stage, because AddThumbPredicate will do it 6015 // later, and will infer the register number from the TIED_TO 6016 // constraint. So this is a deliberately empty decoder method that 6017 // will inhibit the auto-generated disassembly code from adding an 6018 // operand at all. 6019 return MCDisassembler::Success; 6020 } 6021 6022 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6023 unsigned Val, 6024 uint64_t Address, 6025 const void *Decoder) { 6026 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6027 return MCDisassembler::Success; 6028 } 6029 6030 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6031 unsigned Val, 6032 uint64_t Address, 6033 const void *Decoder) { 6034 unsigned Code; 6035 switch (Val & 0x3) { 6036 case 0: 6037 Code = ARMCC::GE; 6038 break; 6039 case 1: 6040 Code = ARMCC::LT; 6041 break; 6042 case 2: 6043 Code = ARMCC::GT; 6044 break; 6045 case 3: 6046 Code = ARMCC::LE; 6047 break; 6048 } 6049 Inst.addOperand(MCOperand::createImm(Code)); 6050 return MCDisassembler::Success; 6051 } 6052 6053 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6054 unsigned Val, 6055 uint64_t Address, 6056 const void *Decoder) { 6057 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6058 return MCDisassembler::Success; 6059 } 6060 6061 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6062 uint64_t Address, 6063 const void *Decoder) { 6064 unsigned Code; 6065 switch (Val) { 6066 default: 6067 return MCDisassembler::Fail; 6068 case 0: 6069 Code = ARMCC::EQ; 6070 break; 6071 case 1: 6072 Code = ARMCC::NE; 6073 break; 6074 case 4: 6075 Code = ARMCC::GE; 6076 break; 6077 case 5: 6078 Code = ARMCC::LT; 6079 break; 6080 case 6: 6081 Code = ARMCC::GT; 6082 break; 6083 case 7: 6084 Code = ARMCC::LE; 6085 break; 6086 } 6087 6088 Inst.addOperand(MCOperand::createImm(Code)); 6089 return MCDisassembler::Success; 6090 } 6091 6092 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6093 uint64_t Address, const void *Decoder) { 6094 DecodeStatus S = MCDisassembler::Success; 6095 6096 unsigned DecodedVal = 64 - Val; 6097 6098 switch (Inst.getOpcode()) { 6099 case ARM::MVE_VCVTf16s16_fix: 6100 case ARM::MVE_VCVTs16f16_fix: 6101 case ARM::MVE_VCVTf16u16_fix: 6102 case ARM::MVE_VCVTu16f16_fix: 6103 if (DecodedVal > 16) 6104 return MCDisassembler::Fail; 6105 break; 6106 case ARM::MVE_VCVTf32s32_fix: 6107 case ARM::MVE_VCVTs32f32_fix: 6108 case ARM::MVE_VCVTf32u32_fix: 6109 case ARM::MVE_VCVTu32f32_fix: 6110 if (DecodedVal > 32) 6111 return MCDisassembler::Fail; 6112 break; 6113 } 6114 6115 Inst.addOperand(MCOperand::createImm(64 - Val)); 6116 6117 return S; 6118 } 6119 6120 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6121 switch (Opcode) { 6122 case ARM::VSTR_P0_off: 6123 case ARM::VSTR_P0_pre: 6124 case ARM::VSTR_P0_post: 6125 case ARM::VLDR_P0_off: 6126 case ARM::VLDR_P0_pre: 6127 case ARM::VLDR_P0_post: 6128 return ARM::P0; 6129 default: 6130 return 0; 6131 } 6132 } 6133 6134 template<bool Writeback> 6135 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6136 uint64_t Address, 6137 const void *Decoder) { 6138 switch (Inst.getOpcode()) { 6139 case ARM::VSTR_FPSCR_pre: 6140 case ARM::VSTR_FPSCR_NZCVQC_pre: 6141 case ARM::VLDR_FPSCR_pre: 6142 case ARM::VLDR_FPSCR_NZCVQC_pre: 6143 case ARM::VSTR_FPSCR_off: 6144 case ARM::VSTR_FPSCR_NZCVQC_off: 6145 case ARM::VLDR_FPSCR_off: 6146 case ARM::VLDR_FPSCR_NZCVQC_off: 6147 case ARM::VSTR_FPSCR_post: 6148 case ARM::VSTR_FPSCR_NZCVQC_post: 6149 case ARM::VLDR_FPSCR_post: 6150 case ARM::VLDR_FPSCR_NZCVQC_post: 6151 const FeatureBitset &featureBits = 6152 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6153 6154 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6155 return MCDisassembler::Fail; 6156 } 6157 6158 DecodeStatus S = MCDisassembler::Success; 6159 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6160 Inst.addOperand(MCOperand::createReg(Sysreg)); 6161 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6162 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6163 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6164 6165 if (Writeback) { 6166 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6167 return MCDisassembler::Fail; 6168 } 6169 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6170 return MCDisassembler::Fail; 6171 6172 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6173 Inst.addOperand(MCOperand::createReg(0)); 6174 6175 return S; 6176 } 6177 6178 template<unsigned MinLog, unsigned MaxLog> 6179 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6180 uint64_t Address, 6181 const void *Decoder) { 6182 DecodeStatus S = MCDisassembler::Success; 6183 6184 if (Val < MinLog || Val > MaxLog) 6185 return MCDisassembler::Fail; 6186 6187 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6188 return S; 6189 } 6190 6191 template <int shift> 6192 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6193 uint64_t Address, 6194 const void *Decoder) { 6195 Val <<= shift; 6196 6197 Inst.addOperand(MCOperand::createImm(Val)); 6198 return MCDisassembler::Success; 6199 } 6200 6201 template<unsigned start> 6202 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6203 uint64_t Address, 6204 const void *Decoder) { 6205 DecodeStatus S = MCDisassembler::Success; 6206 6207 Inst.addOperand(MCOperand::createImm(start + Val)); 6208 6209 return S; 6210 } 6211 6212 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6213 uint64_t Address, const void *Decoder) { 6214 DecodeStatus S = MCDisassembler::Success; 6215 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6216 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6217 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6218 fieldFromInstruction(Insn, 13, 3)); 6219 unsigned index = fieldFromInstruction(Insn, 4, 1); 6220 6221 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6222 return MCDisassembler::Fail; 6223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6224 return MCDisassembler::Fail; 6225 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6226 return MCDisassembler::Fail; 6227 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6228 return MCDisassembler::Fail; 6229 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6230 return MCDisassembler::Fail; 6231 6232 return S; 6233 } 6234 6235 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6236 uint64_t Address, const void *Decoder) { 6237 DecodeStatus S = MCDisassembler::Success; 6238 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6239 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6240 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6241 fieldFromInstruction(Insn, 13, 3)); 6242 unsigned index = fieldFromInstruction(Insn, 4, 1); 6243 6244 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6245 return MCDisassembler::Fail; 6246 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6247 return MCDisassembler::Fail; 6248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6249 return MCDisassembler::Fail; 6250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6251 return MCDisassembler::Fail; 6252 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6253 return MCDisassembler::Fail; 6254 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6255 return MCDisassembler::Fail; 6256 6257 return S; 6258 } 6259 6260 static DecodeStatus DecodeMVEOverlappingLongShift( 6261 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6262 DecodeStatus S = MCDisassembler::Success; 6263 6264 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6265 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6266 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6267 6268 if (RdaHi == 14) { 6269 // This value of RdaHi (really indicating pc, because RdaHi has to 6270 // be an odd-numbered register, so the low bit will be set by the 6271 // decode function below) indicates that we must decode as SQRSHR 6272 // or UQRSHL, which both have a single Rda register field with all 6273 // four bits. 6274 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6275 6276 switch (Inst.getOpcode()) { 6277 case ARM::MVE_ASRLr: 6278 case ARM::MVE_SQRSHRL: 6279 Inst.setOpcode(ARM::MVE_SQRSHR); 6280 break; 6281 case ARM::MVE_LSLLr: 6282 case ARM::MVE_UQRSHLL: 6283 Inst.setOpcode(ARM::MVE_UQRSHL); 6284 break; 6285 default: 6286 llvm_unreachable("Unexpected starting opcode!"); 6287 } 6288 6289 // Rda as output parameter 6290 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6291 return MCDisassembler::Fail; 6292 6293 // Rda again as input parameter 6294 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6295 return MCDisassembler::Fail; 6296 6297 // Rm, the amount to shift by 6298 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6299 return MCDisassembler::Fail; 6300 6301 return S; 6302 } 6303 6304 // Otherwise, we decode as whichever opcode our caller has already 6305 // put into Inst. Those all look the same: 6306 6307 // RdaLo,RdaHi as output parameters 6308 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6309 return MCDisassembler::Fail; 6310 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6311 return MCDisassembler::Fail; 6312 6313 // RdaLo,RdaHi again as input parameters 6314 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6315 return MCDisassembler::Fail; 6316 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6317 return MCDisassembler::Fail; 6318 6319 // Rm, the amount to shift by 6320 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6321 return MCDisassembler::Fail; 6322 6323 return S; 6324 } 6325 6326 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6327 const void *Decoder) { 6328 DecodeStatus S = MCDisassembler::Success; 6329 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6330 fieldFromInstruction(Insn, 13, 3)); 6331 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6332 fieldFromInstruction(Insn, 1, 3)); 6333 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6334 6335 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6336 return MCDisassembler::Fail; 6337 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6338 return MCDisassembler::Fail; 6339 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6340 return MCDisassembler::Fail; 6341 6342 return S; 6343 } 6344 6345 template<bool scalar, OperandDecoder predicate_decoder> 6346 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6347 const void *Decoder) { 6348 DecodeStatus S = MCDisassembler::Success; 6349 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6350 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6351 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6352 return MCDisassembler::Fail; 6353 6354 unsigned fc; 6355 6356 if (scalar) { 6357 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6358 fieldFromInstruction(Insn, 7, 1) | 6359 fieldFromInstruction(Insn, 5, 1) << 1; 6360 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6361 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6362 return MCDisassembler::Fail; 6363 } else { 6364 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6365 fieldFromInstruction(Insn, 7, 1) | 6366 fieldFromInstruction(Insn, 0, 1) << 1; 6367 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6368 fieldFromInstruction(Insn, 1, 3); 6369 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6370 return MCDisassembler::Fail; 6371 } 6372 6373 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6374 return MCDisassembler::Fail; 6375 6376 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6377 Inst.addOperand(MCOperand::createReg(0)); 6378 Inst.addOperand(MCOperand::createImm(0)); 6379 6380 return S; 6381 } 6382 6383 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6384 const void *Decoder) { 6385 DecodeStatus S = MCDisassembler::Success; 6386 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6387 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6388 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6389 return MCDisassembler::Fail; 6390 return S; 6391 } 6392