1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/MC/TargetRegistry.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142 private: 143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 144 ArrayRef<uint8_t> Bytes, uint64_t Address, 145 raw_ostream &CStream) const; 146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 148 ArrayRef<uint8_t> Bytes, uint64_t Address, 149 raw_ostream &CStream) const; 150 151 mutable ITStatus ITBlock; 152 mutable VPTStatus VPTBlock; 153 154 DecodeStatus AddThumbPredicate(MCInst&) const; 155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 156 }; 157 158 } // end anonymous namespace 159 160 static bool Check(DecodeStatus &Out, DecodeStatus In) { 161 switch (In) { 162 case MCDisassembler::Success: 163 // Out stays the same. 164 return true; 165 case MCDisassembler::SoftFail: 166 Out = In; 167 return true; 168 case MCDisassembler::Fail: 169 Out = In; 170 return false; 171 } 172 llvm_unreachable("Invalid DecodeStatus!"); 173 } 174 175 // Forward declare these because the autogenerated code will reference them. 176 // Definitions are further down. 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus 186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 192 uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 198 unsigned RegNo, uint64_t Address, 199 const void *Decoder); 200 static DecodeStatus DecodeGPRwithZRnospRegisterClass( 201 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 213 uint64_t Address, 214 const void *Decoder); 215 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 226 unsigned RegNo, 227 uint64_t Address, 228 const void *Decoder); 229 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 234 uint64_t Address, 235 const void *Decoder); 236 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 237 uint64_t Address, 238 const void *Decoder); 239 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 242 unsigned RegNo, uint64_t Address, 243 const void *Decoder); 244 245 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 256 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 261 unsigned Insn, 262 uint64_t Address, 263 const void *Decoder); 264 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 275 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 276 unsigned Insn, 277 uint64_t Adddress, 278 const void *Decoder); 279 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, 296 uint64_t Address, 297 const void *Decoder); 298 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void *Decoder); 354 template<int shift> 355 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 404 uint64_t Address, const void *Decoder); 405 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 406 uint64_t Address, const void *Decoder); 407 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 408 unsigned Val, 409 uint64_t Address, 410 const void *Decoder); 411 412 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 417 uint64_t Address, const void *Decoder); 418 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 419 uint64_t Address, const void *Decoder); 420 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 421 uint64_t Address, const void *Decoder); 422 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 423 uint64_t Address, const void *Decoder); 424 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 425 uint64_t Address, const void *Decoder); 426 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 427 uint64_t Address, const void *Decoder); 428 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 429 uint64_t Address, const void *Decoder); 430 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 431 uint64_t Address, const void *Decoder); 432 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 433 uint64_t Address, const void* Decoder); 434 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 435 uint64_t Address, const void* Decoder); 436 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 437 uint64_t Address, const void* Decoder); 438 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 439 uint64_t Address, const void* Decoder); 440 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 441 uint64_t Address, const void *Decoder); 442 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 443 uint64_t Address, const void *Decoder); 444 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 447 uint64_t Address, 448 const void *Decoder); 449 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 450 uint64_t Address, const void *Decoder); 451 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 452 uint64_t Address, const void *Decoder); 453 template<int shift> 454 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 455 uint64_t Address, const void *Decoder); 456 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 457 uint64_t Address, const void *Decoder); 458 template<int shift> 459 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 460 uint64_t Address, const void *Decoder); 461 template<int shift, int WriteBack> 462 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 463 uint64_t Address, const void *Decoder); 464 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 465 uint64_t Address, const void *Decoder); 466 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 467 uint64_t Address, const void *Decoder); 468 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 469 uint64_t Address, const void *Decoder); 470 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 471 uint64_t Address, const void *Decoder); 472 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 473 uint64_t Address, const void *Decoder); 474 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 475 uint64_t Address, const void *Decoder); 476 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 477 uint64_t Address, const void *Decoder); 478 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 479 uint64_t Address, const void *Decoder); 480 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 481 uint64_t Address, const void *Decoder); 482 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 483 uint64_t Address, const void *Decoder); 484 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 489 uint64_t Address, const void *Decoder); 490 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 491 uint64_t Address, const void *Decoder); 492 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 493 uint64_t Address, const void *Decoder); 494 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 495 uint64_t Address, const void *Decoder); 496 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 497 uint64_t Address, const void *Decoder); 498 499 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 500 uint64_t Address, const void *Decoder); 501 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 502 uint64_t Address, const void *Decoder); 503 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 504 uint64_t Address, const void *Decoder); 505 506 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 507 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 508 uint64_t Address, const void *Decoder); 509 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 510 uint64_t Address, 511 const void *Decoder); 512 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 513 uint64_t Address, 514 const void *Decoder); 515 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 516 const void *Decoder); 517 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 518 uint64_t Address, 519 const void *Decoder); 520 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 521 const void *Decoder); 522 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 523 uint64_t Address, const void *Decoder); 524 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 525 uint64_t Address, const void *Decoder); 526 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 527 uint64_t Address, 528 const void *Decoder); 529 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 530 uint64_t Address, 531 const void *Decoder); 532 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 533 uint64_t Address, 534 const void *Decoder); 535 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 536 unsigned Val, 537 uint64_t Address, 538 const void *Decoder); 539 template<bool Writeback> 540 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 541 uint64_t Address, 542 const void *Decoder); 543 template<int shift> 544 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 545 uint64_t Address, const void *Decoder); 546 template<int shift> 547 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 548 uint64_t Address, const void *Decoder); 549 template<int shift> 550 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 551 uint64_t Address, const void *Decoder); 552 template<unsigned MinLog, unsigned MaxLog> 553 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 554 uint64_t Address, 555 const void *Decoder); 556 template<unsigned start> 557 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 558 uint64_t Address, 559 const void *Decoder); 560 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 561 uint64_t Address, 562 const void *Decoder); 563 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 564 uint64_t Address, 565 const void *Decoder); 566 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 567 uint64_t Address, const void *Decoder); 568 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 569 uint64_t Address, const void *Decoder); 570 template<bool scalar, OperandDecoder predicate_decoder> 571 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 572 uint64_t Address, const void *Decoder); 573 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 574 uint64_t Address, const void *Decoder); 575 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 576 uint64_t Address, const void *Decoder); 577 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 578 uint64_t Address, 579 const void *Decoder); 580 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 581 uint64_t Address, const void *Decoder); 582 583 #include "ARMGenDisassemblerTables.inc" 584 585 static MCDisassembler *createARMDisassembler(const Target &T, 586 const MCSubtargetInfo &STI, 587 MCContext &Ctx) { 588 return new ARMDisassembler(STI, Ctx); 589 } 590 591 // Post-decoding checks 592 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 593 uint64_t Address, raw_ostream &CS, 594 uint32_t Insn, 595 DecodeStatus Result) { 596 switch (MI.getOpcode()) { 597 case ARM::HVC: { 598 // HVC is undefined if condition = 0xf otherwise upredictable 599 // if condition != 0xe 600 uint32_t Cond = (Insn >> 28) & 0xF; 601 if (Cond == 0xF) 602 return MCDisassembler::Fail; 603 if (Cond != 0xE) 604 return MCDisassembler::SoftFail; 605 return Result; 606 } 607 case ARM::t2ADDri: 608 case ARM::t2ADDri12: 609 case ARM::t2ADDrr: 610 case ARM::t2ADDrs: 611 case ARM::t2SUBri: 612 case ARM::t2SUBri12: 613 case ARM::t2SUBrr: 614 case ARM::t2SUBrs: 615 if (MI.getOperand(0).getReg() == ARM::SP && 616 MI.getOperand(1).getReg() != ARM::SP) 617 return MCDisassembler::SoftFail; 618 return Result; 619 default: return Result; 620 } 621 } 622 623 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 624 ArrayRef<uint8_t> Bytes, 625 uint64_t Address, 626 raw_ostream &CS) const { 627 if (STI.getFeatureBits()[ARM::ModeThumb]) 628 return getThumbInstruction(MI, Size, Bytes, Address, CS); 629 return getARMInstruction(MI, Size, Bytes, Address, CS); 630 } 631 632 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 633 ArrayRef<uint8_t> Bytes, 634 uint64_t Address, 635 raw_ostream &CS) const { 636 CommentStream = &CS; 637 638 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 639 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 640 "mode!"); 641 642 // We want to read exactly 4 bytes of data. 643 if (Bytes.size() < 4) { 644 Size = 0; 645 return MCDisassembler::Fail; 646 } 647 648 // Encoded as a small-endian 32-bit word in the stream. 649 uint32_t Insn = 650 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 651 652 // Calling the auto-generated decoder function. 653 DecodeStatus Result = 654 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 655 if (Result != MCDisassembler::Fail) { 656 Size = 4; 657 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 658 } 659 660 struct DecodeTable { 661 const uint8_t *P; 662 bool DecodePred; 663 }; 664 665 const DecodeTable Tables[] = { 666 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 667 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 668 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 669 {DecoderTablev8Crypto32, false}, 670 }; 671 672 for (auto Table : Tables) { 673 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 674 if (Result != MCDisassembler::Fail) { 675 Size = 4; 676 // Add a fake predicate operand, because we share these instruction 677 // definitions with Thumb2 where these instructions are predicable. 678 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 679 return MCDisassembler::Fail; 680 return Result; 681 } 682 } 683 684 Result = 685 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 686 if (Result != MCDisassembler::Fail) { 687 Size = 4; 688 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 689 } 690 691 Size = 4; 692 return MCDisassembler::Fail; 693 } 694 695 namespace llvm { 696 697 extern const MCInstrDesc ARMInsts[]; 698 699 } // end namespace llvm 700 701 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 702 /// immediate Value in the MCInst. The immediate Value has had any PC 703 /// adjustment made by the caller. If the instruction is a branch instruction 704 /// then isBranch is true, else false. If the getOpInfo() function was set as 705 /// part of the setupForSymbolicDisassembly() call then that function is called 706 /// to get any symbolic information at the Address for this instruction. If 707 /// that returns non-zero then the symbolic information it returns is used to 708 /// create an MCExpr and that is added as an operand to the MCInst. If 709 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 710 /// Value is done and if a symbol is found an MCExpr is created with that, else 711 /// an MCExpr with Value is created. This function returns true if it adds an 712 /// operand to the MCInst and false otherwise. 713 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 714 bool isBranch, uint64_t InstSize, 715 MCInst &MI, const void *Decoder) { 716 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 717 // FIXME: Does it make sense for value to be negative? 718 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 719 /* Offset */ 0, InstSize); 720 } 721 722 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 723 /// referenced by a load instruction with the base register that is the Pc. 724 /// These can often be values in a literal pool near the Address of the 725 /// instruction. The Address of the instruction and its immediate Value are 726 /// used as a possible literal pool entry. The SymbolLookUp call back will 727 /// return the name of a symbol referenced by the literal pool's entry if 728 /// the referenced address is that of a symbol. Or it will return a pointer to 729 /// a literal 'C' string if the referenced address of the literal pool's entry 730 /// is an address into a section with 'C' string literals. 731 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 732 const void *Decoder) { 733 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 734 Dis->tryAddingPcLoadReferenceComment(Value, Address); 735 } 736 737 // Thumb1 instructions don't have explicit S bits. Rather, they 738 // implicitly set CPSR. Since it's not represented in the encoding, the 739 // auto-generated decoder won't inject the CPSR operand. We need to fix 740 // that as a post-pass. 741 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 742 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 743 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 744 MCInst::iterator I = MI.begin(); 745 for (unsigned i = 0; i < NumOps; ++i, ++I) { 746 if (I == MI.end()) break; 747 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 748 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 749 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 750 return; 751 } 752 } 753 754 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 755 } 756 757 static bool isVectorPredicable(unsigned Opcode) { 758 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 759 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 760 for (unsigned i = 0; i < NumOps; ++i) { 761 if (ARM::isVpred(OpInfo[i].OperandType)) 762 return true; 763 } 764 return false; 765 } 766 767 // Most Thumb instructions don't have explicit predicates in the 768 // encoding, but rather get their predicates from IT context. We need 769 // to fix up the predicate operands using this context information as a 770 // post-pass. 771 MCDisassembler::DecodeStatus 772 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 773 MCDisassembler::DecodeStatus S = Success; 774 775 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 776 777 // A few instructions actually have predicates encoded in them. Don't 778 // try to overwrite it if we're seeing one of those. 779 switch (MI.getOpcode()) { 780 case ARM::tBcc: 781 case ARM::t2Bcc: 782 case ARM::tCBZ: 783 case ARM::tCBNZ: 784 case ARM::tCPS: 785 case ARM::t2CPS3p: 786 case ARM::t2CPS2p: 787 case ARM::t2CPS1p: 788 case ARM::t2CSEL: 789 case ARM::t2CSINC: 790 case ARM::t2CSINV: 791 case ARM::t2CSNEG: 792 case ARM::tMOVSr: 793 case ARM::tSETEND: 794 // Some instructions (mostly conditional branches) are not 795 // allowed in IT blocks. 796 if (ITBlock.instrInITBlock()) 797 S = SoftFail; 798 else 799 return Success; 800 break; 801 case ARM::t2HINT: 802 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 803 S = SoftFail; 804 break; 805 case ARM::tB: 806 case ARM::t2B: 807 case ARM::t2TBB: 808 case ARM::t2TBH: 809 // Some instructions (mostly unconditional branches) can 810 // only appears at the end of, or outside of, an IT. 811 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 812 S = SoftFail; 813 break; 814 default: 815 break; 816 } 817 818 // Warn on non-VPT predicable instruction in a VPT block and a VPT 819 // predicable instruction in an IT block 820 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 821 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 822 S = SoftFail; 823 824 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 825 // assume a predicate of AL. 826 unsigned CC = ARMCC::AL; 827 unsigned VCC = ARMVCC::None; 828 if (ITBlock.instrInITBlock()) { 829 CC = ITBlock.getITCC(); 830 ITBlock.advanceITState(); 831 } else if (VPTBlock.instrInVPTBlock()) { 832 VCC = VPTBlock.getVPTPred(); 833 VPTBlock.advanceVPTState(); 834 } 835 836 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 837 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 838 839 MCInst::iterator CCI = MI.begin(); 840 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 841 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 842 } 843 844 if (ARMInsts[MI.getOpcode()].isPredicable()) { 845 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 846 ++CCI; 847 if (CC == ARMCC::AL) 848 MI.insert(CCI, MCOperand::createReg(0)); 849 else 850 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 851 } else if (CC != ARMCC::AL) { 852 Check(S, SoftFail); 853 } 854 855 MCInst::iterator VCCI = MI.begin(); 856 unsigned VCCPos; 857 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 858 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 859 } 860 861 if (isVectorPredicable(MI.getOpcode())) { 862 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 863 ++VCCI; 864 if (VCC == ARMVCC::None) 865 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 866 else 867 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 868 ++VCCI; 869 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 870 ++VCCI; 871 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 872 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 873 VCCPos + 3, MCOI::TIED_TO); 874 assert(TiedOp >= 0 && 875 "Inactive register in vpred_r is not tied to an output!"); 876 // Copy the operand to ensure it's not invalidated when MI grows. 877 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 878 } 879 } else if (VCC != ARMVCC::None) { 880 Check(S, SoftFail); 881 } 882 883 return S; 884 } 885 886 // Thumb VFP instructions are a special case. Because we share their 887 // encodings between ARM and Thumb modes, and they are predicable in ARM 888 // mode, the auto-generated decoder will give them an (incorrect) 889 // predicate operand. We need to rewrite these operands based on the IT 890 // context as a post-pass. 891 void ARMDisassembler::UpdateThumbVFPPredicate( 892 DecodeStatus &S, MCInst &MI) const { 893 unsigned CC; 894 CC = ITBlock.getITCC(); 895 if (CC == 0xF) 896 CC = ARMCC::AL; 897 if (ITBlock.instrInITBlock()) 898 ITBlock.advanceITState(); 899 else if (VPTBlock.instrInVPTBlock()) { 900 CC = VPTBlock.getVPTPred(); 901 VPTBlock.advanceVPTState(); 902 } 903 904 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 905 MCInst::iterator I = MI.begin(); 906 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 907 for (unsigned i = 0; i < NumOps; ++i, ++I) { 908 if (OpInfo[i].isPredicate() ) { 909 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 910 Check(S, SoftFail); 911 I->setImm(CC); 912 ++I; 913 if (CC == ARMCC::AL) 914 I->setReg(0); 915 else 916 I->setReg(ARM::CPSR); 917 return; 918 } 919 } 920 } 921 922 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 923 ArrayRef<uint8_t> Bytes, 924 uint64_t Address, 925 raw_ostream &CS) const { 926 CommentStream = &CS; 927 928 assert(STI.getFeatureBits()[ARM::ModeThumb] && 929 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 930 931 // We want to read exactly 2 bytes of data. 932 if (Bytes.size() < 2) { 933 Size = 0; 934 return MCDisassembler::Fail; 935 } 936 937 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 938 DecodeStatus Result = 939 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 940 if (Result != MCDisassembler::Fail) { 941 Size = 2; 942 Check(Result, AddThumbPredicate(MI)); 943 return Result; 944 } 945 946 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 947 STI); 948 if (Result) { 949 Size = 2; 950 bool InITBlock = ITBlock.instrInITBlock(); 951 Check(Result, AddThumbPredicate(MI)); 952 AddThumb1SBit(MI, InITBlock); 953 return Result; 954 } 955 956 Result = 957 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 958 if (Result != MCDisassembler::Fail) { 959 Size = 2; 960 961 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 962 // the Thumb predicate. 963 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 964 Result = MCDisassembler::SoftFail; 965 966 Check(Result, AddThumbPredicate(MI)); 967 968 // If we find an IT instruction, we need to parse its condition 969 // code and mask operands so that we can apply them correctly 970 // to the subsequent instructions. 971 if (MI.getOpcode() == ARM::t2IT) { 972 unsigned Firstcond = MI.getOperand(0).getImm(); 973 unsigned Mask = MI.getOperand(1).getImm(); 974 ITBlock.setITState(Firstcond, Mask); 975 976 // An IT instruction that would give a 'NV' predicate is unpredictable. 977 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 978 CS << "unpredictable IT predicate sequence"; 979 } 980 981 return Result; 982 } 983 984 // We want to read exactly 4 bytes of data. 985 if (Bytes.size() < 4) { 986 Size = 0; 987 return MCDisassembler::Fail; 988 } 989 990 uint32_t Insn32 = 991 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 992 993 Result = 994 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 995 if (Result != MCDisassembler::Fail) { 996 Size = 4; 997 998 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 999 // the VPT predicate. 1000 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 1001 Result = MCDisassembler::SoftFail; 1002 1003 Check(Result, AddThumbPredicate(MI)); 1004 1005 if (isVPTOpcode(MI.getOpcode())) { 1006 unsigned Mask = MI.getOperand(0).getImm(); 1007 VPTBlock.setVPTState(Mask); 1008 } 1009 1010 return Result; 1011 } 1012 1013 Result = 1014 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1015 if (Result != MCDisassembler::Fail) { 1016 Size = 4; 1017 bool InITBlock = ITBlock.instrInITBlock(); 1018 Check(Result, AddThumbPredicate(MI)); 1019 AddThumb1SBit(MI, InITBlock); 1020 return Result; 1021 } 1022 1023 Result = 1024 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1025 if (Result != MCDisassembler::Fail) { 1026 Size = 4; 1027 Check(Result, AddThumbPredicate(MI)); 1028 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1029 } 1030 1031 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1032 Result = 1033 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1034 if (Result != MCDisassembler::Fail) { 1035 Size = 4; 1036 UpdateThumbVFPPredicate(Result, MI); 1037 return Result; 1038 } 1039 } 1040 1041 Result = 1042 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1043 if (Result != MCDisassembler::Fail) { 1044 Size = 4; 1045 return Result; 1046 } 1047 1048 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1049 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1050 STI); 1051 if (Result != MCDisassembler::Fail) { 1052 Size = 4; 1053 Check(Result, AddThumbPredicate(MI)); 1054 return Result; 1055 } 1056 } 1057 1058 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1059 uint32_t NEONLdStInsn = Insn32; 1060 NEONLdStInsn &= 0xF0FFFFFF; 1061 NEONLdStInsn |= 0x04000000; 1062 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1063 Address, this, STI); 1064 if (Result != MCDisassembler::Fail) { 1065 Size = 4; 1066 Check(Result, AddThumbPredicate(MI)); 1067 return Result; 1068 } 1069 } 1070 1071 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1072 uint32_t NEONDataInsn = Insn32; 1073 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1074 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1075 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1076 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1077 Address, this, STI); 1078 if (Result != MCDisassembler::Fail) { 1079 Size = 4; 1080 Check(Result, AddThumbPredicate(MI)); 1081 return Result; 1082 } 1083 1084 uint32_t NEONCryptoInsn = Insn32; 1085 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1086 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1087 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1088 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1089 Address, this, STI); 1090 if (Result != MCDisassembler::Fail) { 1091 Size = 4; 1092 return Result; 1093 } 1094 1095 uint32_t NEONv8Insn = Insn32; 1096 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1097 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1098 this, STI); 1099 if (Result != MCDisassembler::Fail) { 1100 Size = 4; 1101 return Result; 1102 } 1103 } 1104 1105 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1106 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1107 ? DecoderTableThumb2CDE32 1108 : DecoderTableThumb2CoProc32; 1109 Result = 1110 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1111 if (Result != MCDisassembler::Fail) { 1112 Size = 4; 1113 Check(Result, AddThumbPredicate(MI)); 1114 return Result; 1115 } 1116 1117 Size = 0; 1118 return MCDisassembler::Fail; 1119 } 1120 1121 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1122 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1123 createARMDisassembler); 1124 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1125 createARMDisassembler); 1126 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1127 createARMDisassembler); 1128 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1129 createARMDisassembler); 1130 } 1131 1132 static const uint16_t GPRDecoderTable[] = { 1133 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1134 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1135 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1136 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1137 }; 1138 1139 static const uint16_t CLRMGPRDecoderTable[] = { 1140 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1141 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1142 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1143 ARM::R12, 0, ARM::LR, ARM::APSR 1144 }; 1145 1146 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1147 uint64_t Address, const void *Decoder) { 1148 if (RegNo > 15) 1149 return MCDisassembler::Fail; 1150 1151 unsigned Register = GPRDecoderTable[RegNo]; 1152 Inst.addOperand(MCOperand::createReg(Register)); 1153 return MCDisassembler::Success; 1154 } 1155 1156 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1157 uint64_t Address, 1158 const void *Decoder) { 1159 if (RegNo > 15) 1160 return MCDisassembler::Fail; 1161 1162 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1163 if (Register == 0) 1164 return MCDisassembler::Fail; 1165 1166 Inst.addOperand(MCOperand::createReg(Register)); 1167 return MCDisassembler::Success; 1168 } 1169 1170 static DecodeStatus 1171 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1172 uint64_t Address, const void *Decoder) { 1173 DecodeStatus S = MCDisassembler::Success; 1174 1175 if (RegNo == 15) 1176 S = MCDisassembler::SoftFail; 1177 1178 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1179 1180 return S; 1181 } 1182 1183 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1184 uint64_t Address, 1185 const void *Decoder) { 1186 DecodeStatus S = MCDisassembler::Success; 1187 1188 if (RegNo == 13) 1189 S = MCDisassembler::SoftFail; 1190 1191 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1192 1193 return S; 1194 } 1195 1196 static DecodeStatus 1197 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1198 uint64_t Address, const void *Decoder) { 1199 DecodeStatus S = MCDisassembler::Success; 1200 1201 if (RegNo == 15) 1202 { 1203 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1204 return MCDisassembler::Success; 1205 } 1206 1207 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1208 return S; 1209 } 1210 1211 static DecodeStatus 1212 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1213 uint64_t Address, const void *Decoder) { 1214 DecodeStatus S = MCDisassembler::Success; 1215 1216 if (RegNo == 15) 1217 { 1218 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1219 return MCDisassembler::Success; 1220 } 1221 1222 if (RegNo == 13) 1223 Check(S, MCDisassembler::SoftFail); 1224 1225 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1226 return S; 1227 } 1228 1229 static DecodeStatus 1230 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1231 uint64_t Address, const void *Decoder) { 1232 DecodeStatus S = MCDisassembler::Success; 1233 if (RegNo == 13) 1234 return MCDisassembler::Fail; 1235 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1236 return S; 1237 } 1238 1239 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1240 uint64_t Address, const void *Decoder) { 1241 if (RegNo > 7) 1242 return MCDisassembler::Fail; 1243 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1244 } 1245 1246 static const uint16_t GPRPairDecoderTable[] = { 1247 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1248 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1249 }; 1250 1251 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1252 uint64_t Address, const void *Decoder) { 1253 DecodeStatus S = MCDisassembler::Success; 1254 1255 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1256 // rather than SoftFail as there is no GPRPair table entry for index 7. 1257 if (RegNo > 13) 1258 return MCDisassembler::Fail; 1259 1260 if (RegNo & 1) 1261 S = MCDisassembler::SoftFail; 1262 1263 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1264 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1265 return S; 1266 } 1267 1268 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 1269 uint64_t Address, const void *Decoder) { 1270 if (RegNo > 13) 1271 return MCDisassembler::Fail; 1272 1273 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1274 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1275 1276 if ((RegNo & 1) || RegNo > 10) 1277 return MCDisassembler::SoftFail; 1278 return MCDisassembler::Success; 1279 } 1280 1281 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1282 uint64_t Address, 1283 const void *Decoder) { 1284 if (RegNo != 13) 1285 return MCDisassembler::Fail; 1286 1287 unsigned Register = GPRDecoderTable[RegNo]; 1288 Inst.addOperand(MCOperand::createReg(Register)); 1289 return MCDisassembler::Success; 1290 } 1291 1292 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1293 uint64_t Address, const void *Decoder) { 1294 unsigned Register = 0; 1295 switch (RegNo) { 1296 case 0: 1297 Register = ARM::R0; 1298 break; 1299 case 1: 1300 Register = ARM::R1; 1301 break; 1302 case 2: 1303 Register = ARM::R2; 1304 break; 1305 case 3: 1306 Register = ARM::R3; 1307 break; 1308 case 9: 1309 Register = ARM::R9; 1310 break; 1311 case 12: 1312 Register = ARM::R12; 1313 break; 1314 default: 1315 return MCDisassembler::Fail; 1316 } 1317 1318 Inst.addOperand(MCOperand::createReg(Register)); 1319 return MCDisassembler::Success; 1320 } 1321 1322 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1323 uint64_t Address, const void *Decoder) { 1324 DecodeStatus S = MCDisassembler::Success; 1325 1326 const FeatureBitset &featureBits = 1327 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1328 1329 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1330 S = MCDisassembler::SoftFail; 1331 1332 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1333 return S; 1334 } 1335 1336 static const uint16_t SPRDecoderTable[] = { 1337 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1338 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1339 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1340 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1341 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1342 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1343 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1344 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1345 }; 1346 1347 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1348 uint64_t Address, const void *Decoder) { 1349 if (RegNo > 31) 1350 return MCDisassembler::Fail; 1351 1352 unsigned Register = SPRDecoderTable[RegNo]; 1353 Inst.addOperand(MCOperand::createReg(Register)); 1354 return MCDisassembler::Success; 1355 } 1356 1357 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1358 uint64_t Address, const void *Decoder) { 1359 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1360 } 1361 1362 static const uint16_t DPRDecoderTable[] = { 1363 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1364 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1365 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1366 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1367 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1368 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1369 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1370 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1371 }; 1372 1373 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1374 uint64_t Address, const void *Decoder) { 1375 const FeatureBitset &featureBits = 1376 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1377 1378 bool hasD32 = featureBits[ARM::FeatureD32]; 1379 1380 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1381 return MCDisassembler::Fail; 1382 1383 unsigned Register = DPRDecoderTable[RegNo]; 1384 Inst.addOperand(MCOperand::createReg(Register)); 1385 return MCDisassembler::Success; 1386 } 1387 1388 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1389 uint64_t Address, const void *Decoder) { 1390 if (RegNo > 7) 1391 return MCDisassembler::Fail; 1392 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1393 } 1394 1395 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1396 uint64_t Address, const void *Decoder) { 1397 if (RegNo > 15) 1398 return MCDisassembler::Fail; 1399 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1400 } 1401 1402 static DecodeStatus 1403 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1404 uint64_t Address, const void *Decoder) { 1405 if (RegNo > 15) 1406 return MCDisassembler::Fail; 1407 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1408 } 1409 1410 static const uint16_t QPRDecoderTable[] = { 1411 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1412 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1413 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1414 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1415 }; 1416 1417 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1418 uint64_t Address, const void *Decoder) { 1419 if (RegNo > 31 || (RegNo & 1) != 0) 1420 return MCDisassembler::Fail; 1421 RegNo >>= 1; 1422 1423 unsigned Register = QPRDecoderTable[RegNo]; 1424 Inst.addOperand(MCOperand::createReg(Register)); 1425 return MCDisassembler::Success; 1426 } 1427 1428 static const uint16_t DPairDecoderTable[] = { 1429 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1430 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1431 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1432 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1433 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1434 ARM::Q15 1435 }; 1436 1437 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1438 uint64_t Address, const void *Decoder) { 1439 if (RegNo > 30) 1440 return MCDisassembler::Fail; 1441 1442 unsigned Register = DPairDecoderTable[RegNo]; 1443 Inst.addOperand(MCOperand::createReg(Register)); 1444 return MCDisassembler::Success; 1445 } 1446 1447 static const uint16_t DPairSpacedDecoderTable[] = { 1448 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1449 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1450 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1451 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1452 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1453 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1454 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1455 ARM::D28_D30, ARM::D29_D31 1456 }; 1457 1458 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1459 unsigned RegNo, 1460 uint64_t Address, 1461 const void *Decoder) { 1462 if (RegNo > 29) 1463 return MCDisassembler::Fail; 1464 1465 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1466 Inst.addOperand(MCOperand::createReg(Register)); 1467 return MCDisassembler::Success; 1468 } 1469 1470 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1471 uint64_t Address, const void *Decoder) { 1472 DecodeStatus S = MCDisassembler::Success; 1473 if (Val == 0xF) return MCDisassembler::Fail; 1474 // AL predicate is not allowed on Thumb1 branches. 1475 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1476 return MCDisassembler::Fail; 1477 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1478 Check(S, MCDisassembler::SoftFail); 1479 Inst.addOperand(MCOperand::createImm(Val)); 1480 if (Val == ARMCC::AL) { 1481 Inst.addOperand(MCOperand::createReg(0)); 1482 } else 1483 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1484 return S; 1485 } 1486 1487 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1488 uint64_t Address, const void *Decoder) { 1489 if (Val) 1490 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1491 else 1492 Inst.addOperand(MCOperand::createReg(0)); 1493 return MCDisassembler::Success; 1494 } 1495 1496 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1497 uint64_t Address, const void *Decoder) { 1498 DecodeStatus S = MCDisassembler::Success; 1499 1500 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1501 unsigned type = fieldFromInstruction(Val, 5, 2); 1502 unsigned imm = fieldFromInstruction(Val, 7, 5); 1503 1504 // Register-immediate 1505 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1506 return MCDisassembler::Fail; 1507 1508 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1509 switch (type) { 1510 case 0: 1511 Shift = ARM_AM::lsl; 1512 break; 1513 case 1: 1514 Shift = ARM_AM::lsr; 1515 break; 1516 case 2: 1517 Shift = ARM_AM::asr; 1518 break; 1519 case 3: 1520 Shift = ARM_AM::ror; 1521 break; 1522 } 1523 1524 if (Shift == ARM_AM::ror && imm == 0) 1525 Shift = ARM_AM::rrx; 1526 1527 unsigned Op = Shift | (imm << 3); 1528 Inst.addOperand(MCOperand::createImm(Op)); 1529 1530 return S; 1531 } 1532 1533 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1534 uint64_t Address, const void *Decoder) { 1535 DecodeStatus S = MCDisassembler::Success; 1536 1537 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1538 unsigned type = fieldFromInstruction(Val, 5, 2); 1539 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1540 1541 // Register-register 1542 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1543 return MCDisassembler::Fail; 1544 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1545 return MCDisassembler::Fail; 1546 1547 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1548 switch (type) { 1549 case 0: 1550 Shift = ARM_AM::lsl; 1551 break; 1552 case 1: 1553 Shift = ARM_AM::lsr; 1554 break; 1555 case 2: 1556 Shift = ARM_AM::asr; 1557 break; 1558 case 3: 1559 Shift = ARM_AM::ror; 1560 break; 1561 } 1562 1563 Inst.addOperand(MCOperand::createImm(Shift)); 1564 1565 return S; 1566 } 1567 1568 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1569 uint64_t Address, const void *Decoder) { 1570 DecodeStatus S = MCDisassembler::Success; 1571 1572 bool NeedDisjointWriteback = false; 1573 unsigned WritebackReg = 0; 1574 bool CLRM = false; 1575 switch (Inst.getOpcode()) { 1576 default: 1577 break; 1578 case ARM::LDMIA_UPD: 1579 case ARM::LDMDB_UPD: 1580 case ARM::LDMIB_UPD: 1581 case ARM::LDMDA_UPD: 1582 case ARM::t2LDMIA_UPD: 1583 case ARM::t2LDMDB_UPD: 1584 case ARM::t2STMIA_UPD: 1585 case ARM::t2STMDB_UPD: 1586 NeedDisjointWriteback = true; 1587 WritebackReg = Inst.getOperand(0).getReg(); 1588 break; 1589 case ARM::t2CLRM: 1590 CLRM = true; 1591 break; 1592 } 1593 1594 // Empty register lists are not allowed. 1595 if (Val == 0) return MCDisassembler::Fail; 1596 for (unsigned i = 0; i < 16; ++i) { 1597 if (Val & (1 << i)) { 1598 if (CLRM) { 1599 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1600 return MCDisassembler::Fail; 1601 } 1602 } else { 1603 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1604 return MCDisassembler::Fail; 1605 // Writeback not allowed if Rn is in the target list. 1606 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1607 Check(S, MCDisassembler::SoftFail); 1608 } 1609 } 1610 } 1611 1612 return S; 1613 } 1614 1615 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1616 uint64_t Address, const void *Decoder) { 1617 DecodeStatus S = MCDisassembler::Success; 1618 1619 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1620 unsigned regs = fieldFromInstruction(Val, 0, 8); 1621 1622 // In case of unpredictable encoding, tweak the operands. 1623 if (regs == 0 || (Vd + regs) > 32) { 1624 regs = Vd + regs > 32 ? 32 - Vd : regs; 1625 regs = std::max( 1u, regs); 1626 S = MCDisassembler::SoftFail; 1627 } 1628 1629 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1630 return MCDisassembler::Fail; 1631 for (unsigned i = 0; i < (regs - 1); ++i) { 1632 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1633 return MCDisassembler::Fail; 1634 } 1635 1636 return S; 1637 } 1638 1639 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1640 uint64_t Address, const void *Decoder) { 1641 DecodeStatus S = MCDisassembler::Success; 1642 1643 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1644 unsigned regs = fieldFromInstruction(Val, 1, 7); 1645 1646 // In case of unpredictable encoding, tweak the operands. 1647 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1648 regs = Vd + regs > 32 ? 32 - Vd : regs; 1649 regs = std::max( 1u, regs); 1650 regs = std::min(16u, regs); 1651 S = MCDisassembler::SoftFail; 1652 } 1653 1654 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1655 return MCDisassembler::Fail; 1656 for (unsigned i = 0; i < (regs - 1); ++i) { 1657 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1658 return MCDisassembler::Fail; 1659 } 1660 1661 return S; 1662 } 1663 1664 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1665 uint64_t Address, const void *Decoder) { 1666 // This operand encodes a mask of contiguous zeros between a specified MSB 1667 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1668 // the mask of all bits LSB-and-lower, and then xor them to create 1669 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1670 // create the final mask. 1671 unsigned msb = fieldFromInstruction(Val, 5, 5); 1672 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1673 1674 DecodeStatus S = MCDisassembler::Success; 1675 if (lsb > msb) { 1676 Check(S, MCDisassembler::SoftFail); 1677 // The check above will cause the warning for the "potentially undefined 1678 // instruction encoding" but we can't build a bad MCOperand value here 1679 // with a lsb > msb or else printing the MCInst will cause a crash. 1680 lsb = msb; 1681 } 1682 1683 uint32_t msb_mask = 0xFFFFFFFF; 1684 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1685 uint32_t lsb_mask = (1U << lsb) - 1; 1686 1687 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1688 return S; 1689 } 1690 1691 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1692 uint64_t Address, const void *Decoder) { 1693 DecodeStatus S = MCDisassembler::Success; 1694 1695 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1696 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1697 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1698 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1699 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1700 unsigned U = fieldFromInstruction(Insn, 23, 1); 1701 const FeatureBitset &featureBits = 1702 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1703 1704 switch (Inst.getOpcode()) { 1705 case ARM::LDC_OFFSET: 1706 case ARM::LDC_PRE: 1707 case ARM::LDC_POST: 1708 case ARM::LDC_OPTION: 1709 case ARM::LDCL_OFFSET: 1710 case ARM::LDCL_PRE: 1711 case ARM::LDCL_POST: 1712 case ARM::LDCL_OPTION: 1713 case ARM::STC_OFFSET: 1714 case ARM::STC_PRE: 1715 case ARM::STC_POST: 1716 case ARM::STC_OPTION: 1717 case ARM::STCL_OFFSET: 1718 case ARM::STCL_PRE: 1719 case ARM::STCL_POST: 1720 case ARM::STCL_OPTION: 1721 case ARM::t2LDC_OFFSET: 1722 case ARM::t2LDC_PRE: 1723 case ARM::t2LDC_POST: 1724 case ARM::t2LDC_OPTION: 1725 case ARM::t2LDCL_OFFSET: 1726 case ARM::t2LDCL_PRE: 1727 case ARM::t2LDCL_POST: 1728 case ARM::t2LDCL_OPTION: 1729 case ARM::t2STC_OFFSET: 1730 case ARM::t2STC_PRE: 1731 case ARM::t2STC_POST: 1732 case ARM::t2STC_OPTION: 1733 case ARM::t2STCL_OFFSET: 1734 case ARM::t2STCL_PRE: 1735 case ARM::t2STCL_POST: 1736 case ARM::t2STCL_OPTION: 1737 case ARM::t2LDC2_OFFSET: 1738 case ARM::t2LDC2L_OFFSET: 1739 case ARM::t2LDC2_PRE: 1740 case ARM::t2LDC2L_PRE: 1741 case ARM::t2STC2_OFFSET: 1742 case ARM::t2STC2L_OFFSET: 1743 case ARM::t2STC2_PRE: 1744 case ARM::t2STC2L_PRE: 1745 case ARM::LDC2_OFFSET: 1746 case ARM::LDC2L_OFFSET: 1747 case ARM::LDC2_PRE: 1748 case ARM::LDC2L_PRE: 1749 case ARM::STC2_OFFSET: 1750 case ARM::STC2L_OFFSET: 1751 case ARM::STC2_PRE: 1752 case ARM::STC2L_PRE: 1753 case ARM::t2LDC2_OPTION: 1754 case ARM::t2STC2_OPTION: 1755 case ARM::t2LDC2_POST: 1756 case ARM::t2LDC2L_POST: 1757 case ARM::t2STC2_POST: 1758 case ARM::t2STC2L_POST: 1759 case ARM::LDC2_POST: 1760 case ARM::LDC2L_POST: 1761 case ARM::STC2_POST: 1762 case ARM::STC2L_POST: 1763 if (coproc == 0xA || coproc == 0xB || 1764 (featureBits[ARM::HasV8_1MMainlineOps] && 1765 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1766 coproc == 0xE || coproc == 0xF))) 1767 return MCDisassembler::Fail; 1768 break; 1769 default: 1770 break; 1771 } 1772 1773 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1774 return MCDisassembler::Fail; 1775 1776 Inst.addOperand(MCOperand::createImm(coproc)); 1777 Inst.addOperand(MCOperand::createImm(CRd)); 1778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1779 return MCDisassembler::Fail; 1780 1781 switch (Inst.getOpcode()) { 1782 case ARM::t2LDC2_OFFSET: 1783 case ARM::t2LDC2L_OFFSET: 1784 case ARM::t2LDC2_PRE: 1785 case ARM::t2LDC2L_PRE: 1786 case ARM::t2STC2_OFFSET: 1787 case ARM::t2STC2L_OFFSET: 1788 case ARM::t2STC2_PRE: 1789 case ARM::t2STC2L_PRE: 1790 case ARM::LDC2_OFFSET: 1791 case ARM::LDC2L_OFFSET: 1792 case ARM::LDC2_PRE: 1793 case ARM::LDC2L_PRE: 1794 case ARM::STC2_OFFSET: 1795 case ARM::STC2L_OFFSET: 1796 case ARM::STC2_PRE: 1797 case ARM::STC2L_PRE: 1798 case ARM::t2LDC_OFFSET: 1799 case ARM::t2LDCL_OFFSET: 1800 case ARM::t2LDC_PRE: 1801 case ARM::t2LDCL_PRE: 1802 case ARM::t2STC_OFFSET: 1803 case ARM::t2STCL_OFFSET: 1804 case ARM::t2STC_PRE: 1805 case ARM::t2STCL_PRE: 1806 case ARM::LDC_OFFSET: 1807 case ARM::LDCL_OFFSET: 1808 case ARM::LDC_PRE: 1809 case ARM::LDCL_PRE: 1810 case ARM::STC_OFFSET: 1811 case ARM::STCL_OFFSET: 1812 case ARM::STC_PRE: 1813 case ARM::STCL_PRE: 1814 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1815 Inst.addOperand(MCOperand::createImm(imm)); 1816 break; 1817 case ARM::t2LDC2_POST: 1818 case ARM::t2LDC2L_POST: 1819 case ARM::t2STC2_POST: 1820 case ARM::t2STC2L_POST: 1821 case ARM::LDC2_POST: 1822 case ARM::LDC2L_POST: 1823 case ARM::STC2_POST: 1824 case ARM::STC2L_POST: 1825 case ARM::t2LDC_POST: 1826 case ARM::t2LDCL_POST: 1827 case ARM::t2STC_POST: 1828 case ARM::t2STCL_POST: 1829 case ARM::LDC_POST: 1830 case ARM::LDCL_POST: 1831 case ARM::STC_POST: 1832 case ARM::STCL_POST: 1833 imm |= U << 8; 1834 LLVM_FALLTHROUGH; 1835 default: 1836 // The 'option' variant doesn't encode 'U' in the immediate since 1837 // the immediate is unsigned [0,255]. 1838 Inst.addOperand(MCOperand::createImm(imm)); 1839 break; 1840 } 1841 1842 switch (Inst.getOpcode()) { 1843 case ARM::LDC_OFFSET: 1844 case ARM::LDC_PRE: 1845 case ARM::LDC_POST: 1846 case ARM::LDC_OPTION: 1847 case ARM::LDCL_OFFSET: 1848 case ARM::LDCL_PRE: 1849 case ARM::LDCL_POST: 1850 case ARM::LDCL_OPTION: 1851 case ARM::STC_OFFSET: 1852 case ARM::STC_PRE: 1853 case ARM::STC_POST: 1854 case ARM::STC_OPTION: 1855 case ARM::STCL_OFFSET: 1856 case ARM::STCL_PRE: 1857 case ARM::STCL_POST: 1858 case ARM::STCL_OPTION: 1859 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1860 return MCDisassembler::Fail; 1861 break; 1862 default: 1863 break; 1864 } 1865 1866 return S; 1867 } 1868 1869 static DecodeStatus 1870 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1871 uint64_t Address, const void *Decoder) { 1872 DecodeStatus S = MCDisassembler::Success; 1873 1874 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1875 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1876 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1877 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1878 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1879 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1880 unsigned P = fieldFromInstruction(Insn, 24, 1); 1881 unsigned W = fieldFromInstruction(Insn, 21, 1); 1882 1883 // On stores, the writeback operand precedes Rt. 1884 switch (Inst.getOpcode()) { 1885 case ARM::STR_POST_IMM: 1886 case ARM::STR_POST_REG: 1887 case ARM::STRB_POST_IMM: 1888 case ARM::STRB_POST_REG: 1889 case ARM::STRT_POST_REG: 1890 case ARM::STRT_POST_IMM: 1891 case ARM::STRBT_POST_REG: 1892 case ARM::STRBT_POST_IMM: 1893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1894 return MCDisassembler::Fail; 1895 break; 1896 default: 1897 break; 1898 } 1899 1900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1901 return MCDisassembler::Fail; 1902 1903 // On loads, the writeback operand comes after Rt. 1904 switch (Inst.getOpcode()) { 1905 case ARM::LDR_POST_IMM: 1906 case ARM::LDR_POST_REG: 1907 case ARM::LDRB_POST_IMM: 1908 case ARM::LDRB_POST_REG: 1909 case ARM::LDRBT_POST_REG: 1910 case ARM::LDRBT_POST_IMM: 1911 case ARM::LDRT_POST_REG: 1912 case ARM::LDRT_POST_IMM: 1913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1914 return MCDisassembler::Fail; 1915 break; 1916 default: 1917 break; 1918 } 1919 1920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1921 return MCDisassembler::Fail; 1922 1923 ARM_AM::AddrOpc Op = ARM_AM::add; 1924 if (!fieldFromInstruction(Insn, 23, 1)) 1925 Op = ARM_AM::sub; 1926 1927 bool writeback = (P == 0) || (W == 1); 1928 unsigned idx_mode = 0; 1929 if (P && writeback) 1930 idx_mode = ARMII::IndexModePre; 1931 else if (!P && writeback) 1932 idx_mode = ARMII::IndexModePost; 1933 1934 if (writeback && (Rn == 15 || Rn == Rt)) 1935 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1936 1937 if (reg) { 1938 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1939 return MCDisassembler::Fail; 1940 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1941 switch( fieldFromInstruction(Insn, 5, 2)) { 1942 case 0: 1943 Opc = ARM_AM::lsl; 1944 break; 1945 case 1: 1946 Opc = ARM_AM::lsr; 1947 break; 1948 case 2: 1949 Opc = ARM_AM::asr; 1950 break; 1951 case 3: 1952 Opc = ARM_AM::ror; 1953 break; 1954 default: 1955 return MCDisassembler::Fail; 1956 } 1957 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1958 if (Opc == ARM_AM::ror && amt == 0) 1959 Opc = ARM_AM::rrx; 1960 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1961 1962 Inst.addOperand(MCOperand::createImm(imm)); 1963 } else { 1964 Inst.addOperand(MCOperand::createReg(0)); 1965 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1966 Inst.addOperand(MCOperand::createImm(tmp)); 1967 } 1968 1969 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1970 return MCDisassembler::Fail; 1971 1972 return S; 1973 } 1974 1975 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1976 uint64_t Address, const void *Decoder) { 1977 DecodeStatus S = MCDisassembler::Success; 1978 1979 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1980 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1981 unsigned type = fieldFromInstruction(Val, 5, 2); 1982 unsigned imm = fieldFromInstruction(Val, 7, 5); 1983 unsigned U = fieldFromInstruction(Val, 12, 1); 1984 1985 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1986 switch (type) { 1987 case 0: 1988 ShOp = ARM_AM::lsl; 1989 break; 1990 case 1: 1991 ShOp = ARM_AM::lsr; 1992 break; 1993 case 2: 1994 ShOp = ARM_AM::asr; 1995 break; 1996 case 3: 1997 ShOp = ARM_AM::ror; 1998 break; 1999 } 2000 2001 if (ShOp == ARM_AM::ror && imm == 0) 2002 ShOp = ARM_AM::rrx; 2003 2004 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2005 return MCDisassembler::Fail; 2006 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2007 return MCDisassembler::Fail; 2008 unsigned shift; 2009 if (U) 2010 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 2011 else 2012 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 2013 Inst.addOperand(MCOperand::createImm(shift)); 2014 2015 return S; 2016 } 2017 2018 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 2019 uint64_t Address, 2020 const void *Decoder) { 2021 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) 2022 return MCDisassembler::Fail; 2023 2024 // The "csync" operand is not encoded into the "tsb" instruction (as this is 2025 // the only available operand), but LLVM expects the instruction to have one 2026 // operand, so we need to add the csync when decoding. 2027 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC)); 2028 return MCDisassembler::Success; 2029 } 2030 2031 static DecodeStatus 2032 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 2033 uint64_t Address, const void *Decoder) { 2034 DecodeStatus S = MCDisassembler::Success; 2035 2036 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2037 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2038 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2039 unsigned type = fieldFromInstruction(Insn, 22, 1); 2040 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2041 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2042 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2043 unsigned W = fieldFromInstruction(Insn, 21, 1); 2044 unsigned P = fieldFromInstruction(Insn, 24, 1); 2045 unsigned Rt2 = Rt + 1; 2046 2047 bool writeback = (W == 1) | (P == 0); 2048 2049 // For {LD,ST}RD, Rt must be even, else undefined. 2050 switch (Inst.getOpcode()) { 2051 case ARM::STRD: 2052 case ARM::STRD_PRE: 2053 case ARM::STRD_POST: 2054 case ARM::LDRD: 2055 case ARM::LDRD_PRE: 2056 case ARM::LDRD_POST: 2057 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2058 break; 2059 default: 2060 break; 2061 } 2062 switch (Inst.getOpcode()) { 2063 case ARM::STRD: 2064 case ARM::STRD_PRE: 2065 case ARM::STRD_POST: 2066 if (P == 0 && W == 1) 2067 S = MCDisassembler::SoftFail; 2068 2069 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2070 S = MCDisassembler::SoftFail; 2071 if (type && Rm == 15) 2072 S = MCDisassembler::SoftFail; 2073 if (Rt2 == 15) 2074 S = MCDisassembler::SoftFail; 2075 if (!type && fieldFromInstruction(Insn, 8, 4)) 2076 S = MCDisassembler::SoftFail; 2077 break; 2078 case ARM::STRH: 2079 case ARM::STRH_PRE: 2080 case ARM::STRH_POST: 2081 if (Rt == 15) 2082 S = MCDisassembler::SoftFail; 2083 if (writeback && (Rn == 15 || Rn == Rt)) 2084 S = MCDisassembler::SoftFail; 2085 if (!type && Rm == 15) 2086 S = MCDisassembler::SoftFail; 2087 break; 2088 case ARM::LDRD: 2089 case ARM::LDRD_PRE: 2090 case ARM::LDRD_POST: 2091 if (type && Rn == 15) { 2092 if (Rt2 == 15) 2093 S = MCDisassembler::SoftFail; 2094 break; 2095 } 2096 if (P == 0 && W == 1) 2097 S = MCDisassembler::SoftFail; 2098 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2099 S = MCDisassembler::SoftFail; 2100 if (!type && writeback && Rn == 15) 2101 S = MCDisassembler::SoftFail; 2102 if (writeback && (Rn == Rt || Rn == Rt2)) 2103 S = MCDisassembler::SoftFail; 2104 break; 2105 case ARM::LDRH: 2106 case ARM::LDRH_PRE: 2107 case ARM::LDRH_POST: 2108 if (type && Rn == 15) { 2109 if (Rt == 15) 2110 S = MCDisassembler::SoftFail; 2111 break; 2112 } 2113 if (Rt == 15) 2114 S = MCDisassembler::SoftFail; 2115 if (!type && Rm == 15) 2116 S = MCDisassembler::SoftFail; 2117 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2118 S = MCDisassembler::SoftFail; 2119 break; 2120 case ARM::LDRSH: 2121 case ARM::LDRSH_PRE: 2122 case ARM::LDRSH_POST: 2123 case ARM::LDRSB: 2124 case ARM::LDRSB_PRE: 2125 case ARM::LDRSB_POST: 2126 if (type && Rn == 15) { 2127 if (Rt == 15) 2128 S = MCDisassembler::SoftFail; 2129 break; 2130 } 2131 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2132 S = MCDisassembler::SoftFail; 2133 if (!type && (Rt == 15 || Rm == 15)) 2134 S = MCDisassembler::SoftFail; 2135 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2136 S = MCDisassembler::SoftFail; 2137 break; 2138 default: 2139 break; 2140 } 2141 2142 if (writeback) { // Writeback 2143 if (P) 2144 U |= ARMII::IndexModePre << 9; 2145 else 2146 U |= ARMII::IndexModePost << 9; 2147 2148 // On stores, the writeback operand precedes Rt. 2149 switch (Inst.getOpcode()) { 2150 case ARM::STRD: 2151 case ARM::STRD_PRE: 2152 case ARM::STRD_POST: 2153 case ARM::STRH: 2154 case ARM::STRH_PRE: 2155 case ARM::STRH_POST: 2156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2157 return MCDisassembler::Fail; 2158 break; 2159 default: 2160 break; 2161 } 2162 } 2163 2164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2165 return MCDisassembler::Fail; 2166 switch (Inst.getOpcode()) { 2167 case ARM::STRD: 2168 case ARM::STRD_PRE: 2169 case ARM::STRD_POST: 2170 case ARM::LDRD: 2171 case ARM::LDRD_PRE: 2172 case ARM::LDRD_POST: 2173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2174 return MCDisassembler::Fail; 2175 break; 2176 default: 2177 break; 2178 } 2179 2180 if (writeback) { 2181 // On loads, the writeback operand comes after Rt. 2182 switch (Inst.getOpcode()) { 2183 case ARM::LDRD: 2184 case ARM::LDRD_PRE: 2185 case ARM::LDRD_POST: 2186 case ARM::LDRH: 2187 case ARM::LDRH_PRE: 2188 case ARM::LDRH_POST: 2189 case ARM::LDRSH: 2190 case ARM::LDRSH_PRE: 2191 case ARM::LDRSH_POST: 2192 case ARM::LDRSB: 2193 case ARM::LDRSB_PRE: 2194 case ARM::LDRSB_POST: 2195 case ARM::LDRHTr: 2196 case ARM::LDRSBTr: 2197 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2198 return MCDisassembler::Fail; 2199 break; 2200 default: 2201 break; 2202 } 2203 } 2204 2205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2206 return MCDisassembler::Fail; 2207 2208 if (type) { 2209 Inst.addOperand(MCOperand::createReg(0)); 2210 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2211 } else { 2212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2213 return MCDisassembler::Fail; 2214 Inst.addOperand(MCOperand::createImm(U)); 2215 } 2216 2217 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2218 return MCDisassembler::Fail; 2219 2220 return S; 2221 } 2222 2223 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2224 uint64_t Address, const void *Decoder) { 2225 DecodeStatus S = MCDisassembler::Success; 2226 2227 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2228 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2229 2230 switch (mode) { 2231 case 0: 2232 mode = ARM_AM::da; 2233 break; 2234 case 1: 2235 mode = ARM_AM::ia; 2236 break; 2237 case 2: 2238 mode = ARM_AM::db; 2239 break; 2240 case 3: 2241 mode = ARM_AM::ib; 2242 break; 2243 } 2244 2245 Inst.addOperand(MCOperand::createImm(mode)); 2246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2247 return MCDisassembler::Fail; 2248 2249 return S; 2250 } 2251 2252 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2253 uint64_t Address, const void *Decoder) { 2254 DecodeStatus S = MCDisassembler::Success; 2255 2256 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2257 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2258 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2259 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2260 2261 if (pred == 0xF) 2262 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2263 2264 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2265 return MCDisassembler::Fail; 2266 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2267 return MCDisassembler::Fail; 2268 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2269 return MCDisassembler::Fail; 2270 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2271 return MCDisassembler::Fail; 2272 return S; 2273 } 2274 2275 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2276 unsigned Insn, 2277 uint64_t Address, const void *Decoder) { 2278 DecodeStatus S = MCDisassembler::Success; 2279 2280 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2281 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2282 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2283 2284 if (pred == 0xF) { 2285 // Ambiguous with RFE and SRS 2286 switch (Inst.getOpcode()) { 2287 case ARM::LDMDA: 2288 Inst.setOpcode(ARM::RFEDA); 2289 break; 2290 case ARM::LDMDA_UPD: 2291 Inst.setOpcode(ARM::RFEDA_UPD); 2292 break; 2293 case ARM::LDMDB: 2294 Inst.setOpcode(ARM::RFEDB); 2295 break; 2296 case ARM::LDMDB_UPD: 2297 Inst.setOpcode(ARM::RFEDB_UPD); 2298 break; 2299 case ARM::LDMIA: 2300 Inst.setOpcode(ARM::RFEIA); 2301 break; 2302 case ARM::LDMIA_UPD: 2303 Inst.setOpcode(ARM::RFEIA_UPD); 2304 break; 2305 case ARM::LDMIB: 2306 Inst.setOpcode(ARM::RFEIB); 2307 break; 2308 case ARM::LDMIB_UPD: 2309 Inst.setOpcode(ARM::RFEIB_UPD); 2310 break; 2311 case ARM::STMDA: 2312 Inst.setOpcode(ARM::SRSDA); 2313 break; 2314 case ARM::STMDA_UPD: 2315 Inst.setOpcode(ARM::SRSDA_UPD); 2316 break; 2317 case ARM::STMDB: 2318 Inst.setOpcode(ARM::SRSDB); 2319 break; 2320 case ARM::STMDB_UPD: 2321 Inst.setOpcode(ARM::SRSDB_UPD); 2322 break; 2323 case ARM::STMIA: 2324 Inst.setOpcode(ARM::SRSIA); 2325 break; 2326 case ARM::STMIA_UPD: 2327 Inst.setOpcode(ARM::SRSIA_UPD); 2328 break; 2329 case ARM::STMIB: 2330 Inst.setOpcode(ARM::SRSIB); 2331 break; 2332 case ARM::STMIB_UPD: 2333 Inst.setOpcode(ARM::SRSIB_UPD); 2334 break; 2335 default: 2336 return MCDisassembler::Fail; 2337 } 2338 2339 // For stores (which become SRS's, the only operand is the mode. 2340 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2341 // Check SRS encoding constraints 2342 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2343 fieldFromInstruction(Insn, 20, 1) == 0)) 2344 return MCDisassembler::Fail; 2345 2346 Inst.addOperand( 2347 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2348 return S; 2349 } 2350 2351 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2352 } 2353 2354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2355 return MCDisassembler::Fail; 2356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2357 return MCDisassembler::Fail; // Tied 2358 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2359 return MCDisassembler::Fail; 2360 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2361 return MCDisassembler::Fail; 2362 2363 return S; 2364 } 2365 2366 // Check for UNPREDICTABLE predicated ESB instruction 2367 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2368 uint64_t Address, const void *Decoder) { 2369 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2370 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2371 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2372 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2373 2374 DecodeStatus S = MCDisassembler::Success; 2375 2376 Inst.addOperand(MCOperand::createImm(imm8)); 2377 2378 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2379 return MCDisassembler::Fail; 2380 2381 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2382 // so all predicates should be allowed. 2383 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2384 S = MCDisassembler::SoftFail; 2385 2386 return S; 2387 } 2388 2389 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2390 uint64_t Address, const void *Decoder) { 2391 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2392 unsigned M = fieldFromInstruction(Insn, 17, 1); 2393 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2394 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2395 2396 DecodeStatus S = MCDisassembler::Success; 2397 2398 // This decoder is called from multiple location that do not check 2399 // the full encoding is valid before they do. 2400 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2401 fieldFromInstruction(Insn, 16, 1) != 0 || 2402 fieldFromInstruction(Insn, 20, 8) != 0x10) 2403 return MCDisassembler::Fail; 2404 2405 // imod == '01' --> UNPREDICTABLE 2406 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2407 // return failure here. The '01' imod value is unprintable, so there's 2408 // nothing useful we could do even if we returned UNPREDICTABLE. 2409 2410 if (imod == 1) return MCDisassembler::Fail; 2411 2412 if (imod && M) { 2413 Inst.setOpcode(ARM::CPS3p); 2414 Inst.addOperand(MCOperand::createImm(imod)); 2415 Inst.addOperand(MCOperand::createImm(iflags)); 2416 Inst.addOperand(MCOperand::createImm(mode)); 2417 } else if (imod && !M) { 2418 Inst.setOpcode(ARM::CPS2p); 2419 Inst.addOperand(MCOperand::createImm(imod)); 2420 Inst.addOperand(MCOperand::createImm(iflags)); 2421 if (mode) S = MCDisassembler::SoftFail; 2422 } else if (!imod && M) { 2423 Inst.setOpcode(ARM::CPS1p); 2424 Inst.addOperand(MCOperand::createImm(mode)); 2425 if (iflags) S = MCDisassembler::SoftFail; 2426 } else { 2427 // imod == '00' && M == '0' --> UNPREDICTABLE 2428 Inst.setOpcode(ARM::CPS1p); 2429 Inst.addOperand(MCOperand::createImm(mode)); 2430 S = MCDisassembler::SoftFail; 2431 } 2432 2433 return S; 2434 } 2435 2436 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2437 uint64_t Address, const void *Decoder) { 2438 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2439 unsigned M = fieldFromInstruction(Insn, 8, 1); 2440 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2441 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2442 2443 DecodeStatus S = MCDisassembler::Success; 2444 2445 // imod == '01' --> UNPREDICTABLE 2446 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2447 // return failure here. The '01' imod value is unprintable, so there's 2448 // nothing useful we could do even if we returned UNPREDICTABLE. 2449 2450 if (imod == 1) return MCDisassembler::Fail; 2451 2452 if (imod && M) { 2453 Inst.setOpcode(ARM::t2CPS3p); 2454 Inst.addOperand(MCOperand::createImm(imod)); 2455 Inst.addOperand(MCOperand::createImm(iflags)); 2456 Inst.addOperand(MCOperand::createImm(mode)); 2457 } else if (imod && !M) { 2458 Inst.setOpcode(ARM::t2CPS2p); 2459 Inst.addOperand(MCOperand::createImm(imod)); 2460 Inst.addOperand(MCOperand::createImm(iflags)); 2461 if (mode) S = MCDisassembler::SoftFail; 2462 } else if (!imod && M) { 2463 Inst.setOpcode(ARM::t2CPS1p); 2464 Inst.addOperand(MCOperand::createImm(mode)); 2465 if (iflags) S = MCDisassembler::SoftFail; 2466 } else { 2467 // imod == '00' && M == '0' --> this is a HINT instruction 2468 int imm = fieldFromInstruction(Insn, 0, 8); 2469 // HINT are defined only for immediate in [0..4] 2470 if(imm > 4) return MCDisassembler::Fail; 2471 Inst.setOpcode(ARM::t2HINT); 2472 Inst.addOperand(MCOperand::createImm(imm)); 2473 } 2474 2475 return S; 2476 } 2477 2478 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, 2479 uint64_t Address, 2480 const void *Decoder) { 2481 unsigned imm = fieldFromInstruction(Insn, 0, 8); 2482 2483 unsigned Opcode = ARM::t2HINT; 2484 2485 if (imm == 0x0D) { 2486 Opcode = ARM::t2PACBTI; 2487 } else if (imm == 0x1D) { 2488 Opcode = ARM::t2PAC; 2489 } else if (imm == 0x2D) { 2490 Opcode = ARM::t2AUT; 2491 } else if (imm == 0x0F) { 2492 Opcode = ARM::t2BTI; 2493 } 2494 2495 Inst.setOpcode(Opcode); 2496 if (Opcode == ARM::t2HINT) { 2497 Inst.addOperand(MCOperand::createImm(imm)); 2498 } 2499 2500 return MCDisassembler::Success; 2501 } 2502 2503 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2504 uint64_t Address, const void *Decoder) { 2505 DecodeStatus S = MCDisassembler::Success; 2506 2507 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2508 unsigned imm = 0; 2509 2510 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2511 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2512 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2513 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2514 2515 if (Inst.getOpcode() == ARM::t2MOVTi16) 2516 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2517 return MCDisassembler::Fail; 2518 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2519 return MCDisassembler::Fail; 2520 2521 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2522 Inst.addOperand(MCOperand::createImm(imm)); 2523 2524 return S; 2525 } 2526 2527 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2528 uint64_t Address, const void *Decoder) { 2529 DecodeStatus S = MCDisassembler::Success; 2530 2531 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2532 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2533 unsigned imm = 0; 2534 2535 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2536 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2537 2538 if (Inst.getOpcode() == ARM::MOVTi16) 2539 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2540 return MCDisassembler::Fail; 2541 2542 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2543 return MCDisassembler::Fail; 2544 2545 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2546 Inst.addOperand(MCOperand::createImm(imm)); 2547 2548 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2549 return MCDisassembler::Fail; 2550 2551 return S; 2552 } 2553 2554 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2555 uint64_t Address, const void *Decoder) { 2556 DecodeStatus S = MCDisassembler::Success; 2557 2558 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2559 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2560 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2561 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2562 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2563 2564 if (pred == 0xF) 2565 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2566 2567 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2568 return MCDisassembler::Fail; 2569 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2570 return MCDisassembler::Fail; 2571 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2572 return MCDisassembler::Fail; 2573 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2574 return MCDisassembler::Fail; 2575 2576 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2577 return MCDisassembler::Fail; 2578 2579 return S; 2580 } 2581 2582 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2583 uint64_t Address, const void *Decoder) { 2584 DecodeStatus S = MCDisassembler::Success; 2585 2586 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2587 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2588 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2589 2590 if (Pred == 0xF) 2591 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2592 2593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2594 return MCDisassembler::Fail; 2595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2596 return MCDisassembler::Fail; 2597 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2598 return MCDisassembler::Fail; 2599 2600 return S; 2601 } 2602 2603 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2604 uint64_t Address, const void *Decoder) { 2605 DecodeStatus S = MCDisassembler::Success; 2606 2607 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2608 2609 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2610 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2611 2612 if (!FeatureBits[ARM::HasV8_1aOps] || 2613 !FeatureBits[ARM::HasV8Ops]) 2614 return MCDisassembler::Fail; 2615 2616 // Decoder can be called from DecodeTST, which does not check the full 2617 // encoding is valid. 2618 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2619 fieldFromInstruction(Insn, 4,4) != 0) 2620 return MCDisassembler::Fail; 2621 if (fieldFromInstruction(Insn, 10,10) != 0 || 2622 fieldFromInstruction(Insn, 0,4) != 0) 2623 S = MCDisassembler::SoftFail; 2624 2625 Inst.setOpcode(ARM::SETPAN); 2626 Inst.addOperand(MCOperand::createImm(Imm)); 2627 2628 return S; 2629 } 2630 2631 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2632 uint64_t Address, const void *Decoder) { 2633 DecodeStatus S = MCDisassembler::Success; 2634 2635 unsigned add = fieldFromInstruction(Val, 12, 1); 2636 unsigned imm = fieldFromInstruction(Val, 0, 12); 2637 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2638 2639 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2640 return MCDisassembler::Fail; 2641 2642 if (!add) imm *= -1; 2643 if (imm == 0 && !add) imm = INT32_MIN; 2644 Inst.addOperand(MCOperand::createImm(imm)); 2645 if (Rn == 15) 2646 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2647 2648 return S; 2649 } 2650 2651 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2652 uint64_t Address, const void *Decoder) { 2653 DecodeStatus S = MCDisassembler::Success; 2654 2655 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2656 // U == 1 to add imm, 0 to subtract it. 2657 unsigned U = fieldFromInstruction(Val, 8, 1); 2658 unsigned imm = fieldFromInstruction(Val, 0, 8); 2659 2660 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2661 return MCDisassembler::Fail; 2662 2663 if (U) 2664 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2665 else 2666 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2667 2668 return S; 2669 } 2670 2671 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2672 uint64_t Address, const void *Decoder) { 2673 DecodeStatus S = MCDisassembler::Success; 2674 2675 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2676 // U == 1 to add imm, 0 to subtract it. 2677 unsigned U = fieldFromInstruction(Val, 8, 1); 2678 unsigned imm = fieldFromInstruction(Val, 0, 8); 2679 2680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2681 return MCDisassembler::Fail; 2682 2683 if (U) 2684 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2685 else 2686 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2687 2688 return S; 2689 } 2690 2691 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2692 uint64_t Address, const void *Decoder) { 2693 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2694 } 2695 2696 static DecodeStatus 2697 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2698 uint64_t Address, const void *Decoder) { 2699 DecodeStatus Status = MCDisassembler::Success; 2700 2701 // Note the J1 and J2 values are from the encoded instruction. So here 2702 // change them to I1 and I2 values via as documented: 2703 // I1 = NOT(J1 EOR S); 2704 // I2 = NOT(J2 EOR S); 2705 // and build the imm32 with one trailing zero as documented: 2706 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2707 unsigned S = fieldFromInstruction(Insn, 26, 1); 2708 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2709 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2710 unsigned I1 = !(J1 ^ S); 2711 unsigned I2 = !(J2 ^ S); 2712 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2713 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2714 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2715 int imm32 = SignExtend32<25>(tmp << 1); 2716 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2717 true, 4, Inst, Decoder)) 2718 Inst.addOperand(MCOperand::createImm(imm32)); 2719 2720 return Status; 2721 } 2722 2723 static DecodeStatus 2724 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2725 uint64_t Address, const void *Decoder) { 2726 DecodeStatus S = MCDisassembler::Success; 2727 2728 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2729 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2730 2731 if (pred == 0xF) { 2732 Inst.setOpcode(ARM::BLXi); 2733 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2734 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2735 true, 4, Inst, Decoder)) 2736 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2737 return S; 2738 } 2739 2740 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2741 true, 4, Inst, Decoder)) 2742 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2743 2744 // We already have BL_pred for BL w/ predicate, no need to add addition 2745 // predicate opreands for BL 2746 if (Inst.getOpcode() != ARM::BL) 2747 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2748 return MCDisassembler::Fail; 2749 2750 return S; 2751 } 2752 2753 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2754 uint64_t Address, const void *Decoder) { 2755 DecodeStatus S = MCDisassembler::Success; 2756 2757 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2758 unsigned align = fieldFromInstruction(Val, 4, 2); 2759 2760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2761 return MCDisassembler::Fail; 2762 if (!align) 2763 Inst.addOperand(MCOperand::createImm(0)); 2764 else 2765 Inst.addOperand(MCOperand::createImm(4 << align)); 2766 2767 return S; 2768 } 2769 2770 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2771 uint64_t Address, const void *Decoder) { 2772 DecodeStatus S = MCDisassembler::Success; 2773 2774 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2775 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2776 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2777 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2778 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2779 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2780 2781 // First output register 2782 switch (Inst.getOpcode()) { 2783 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2784 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2785 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2786 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2787 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2788 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2789 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2790 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2791 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2792 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 break; 2795 case ARM::VLD2b16: 2796 case ARM::VLD2b32: 2797 case ARM::VLD2b8: 2798 case ARM::VLD2b16wb_fixed: 2799 case ARM::VLD2b16wb_register: 2800 case ARM::VLD2b32wb_fixed: 2801 case ARM::VLD2b32wb_register: 2802 case ARM::VLD2b8wb_fixed: 2803 case ARM::VLD2b8wb_register: 2804 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2805 return MCDisassembler::Fail; 2806 break; 2807 default: 2808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2809 return MCDisassembler::Fail; 2810 } 2811 2812 // Second output register 2813 switch (Inst.getOpcode()) { 2814 case ARM::VLD3d8: 2815 case ARM::VLD3d16: 2816 case ARM::VLD3d32: 2817 case ARM::VLD3d8_UPD: 2818 case ARM::VLD3d16_UPD: 2819 case ARM::VLD3d32_UPD: 2820 case ARM::VLD4d8: 2821 case ARM::VLD4d16: 2822 case ARM::VLD4d32: 2823 case ARM::VLD4d8_UPD: 2824 case ARM::VLD4d16_UPD: 2825 case ARM::VLD4d32_UPD: 2826 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2827 return MCDisassembler::Fail; 2828 break; 2829 case ARM::VLD3q8: 2830 case ARM::VLD3q16: 2831 case ARM::VLD3q32: 2832 case ARM::VLD3q8_UPD: 2833 case ARM::VLD3q16_UPD: 2834 case ARM::VLD3q32_UPD: 2835 case ARM::VLD4q8: 2836 case ARM::VLD4q16: 2837 case ARM::VLD4q32: 2838 case ARM::VLD4q8_UPD: 2839 case ARM::VLD4q16_UPD: 2840 case ARM::VLD4q32_UPD: 2841 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2842 return MCDisassembler::Fail; 2843 break; 2844 default: 2845 break; 2846 } 2847 2848 // Third output register 2849 switch(Inst.getOpcode()) { 2850 case ARM::VLD3d8: 2851 case ARM::VLD3d16: 2852 case ARM::VLD3d32: 2853 case ARM::VLD3d8_UPD: 2854 case ARM::VLD3d16_UPD: 2855 case ARM::VLD3d32_UPD: 2856 case ARM::VLD4d8: 2857 case ARM::VLD4d16: 2858 case ARM::VLD4d32: 2859 case ARM::VLD4d8_UPD: 2860 case ARM::VLD4d16_UPD: 2861 case ARM::VLD4d32_UPD: 2862 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2863 return MCDisassembler::Fail; 2864 break; 2865 case ARM::VLD3q8: 2866 case ARM::VLD3q16: 2867 case ARM::VLD3q32: 2868 case ARM::VLD3q8_UPD: 2869 case ARM::VLD3q16_UPD: 2870 case ARM::VLD3q32_UPD: 2871 case ARM::VLD4q8: 2872 case ARM::VLD4q16: 2873 case ARM::VLD4q32: 2874 case ARM::VLD4q8_UPD: 2875 case ARM::VLD4q16_UPD: 2876 case ARM::VLD4q32_UPD: 2877 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2878 return MCDisassembler::Fail; 2879 break; 2880 default: 2881 break; 2882 } 2883 2884 // Fourth output register 2885 switch (Inst.getOpcode()) { 2886 case ARM::VLD4d8: 2887 case ARM::VLD4d16: 2888 case ARM::VLD4d32: 2889 case ARM::VLD4d8_UPD: 2890 case ARM::VLD4d16_UPD: 2891 case ARM::VLD4d32_UPD: 2892 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2893 return MCDisassembler::Fail; 2894 break; 2895 case ARM::VLD4q8: 2896 case ARM::VLD4q16: 2897 case ARM::VLD4q32: 2898 case ARM::VLD4q8_UPD: 2899 case ARM::VLD4q16_UPD: 2900 case ARM::VLD4q32_UPD: 2901 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2902 return MCDisassembler::Fail; 2903 break; 2904 default: 2905 break; 2906 } 2907 2908 // Writeback operand 2909 switch (Inst.getOpcode()) { 2910 case ARM::VLD1d8wb_fixed: 2911 case ARM::VLD1d16wb_fixed: 2912 case ARM::VLD1d32wb_fixed: 2913 case ARM::VLD1d64wb_fixed: 2914 case ARM::VLD1d8wb_register: 2915 case ARM::VLD1d16wb_register: 2916 case ARM::VLD1d32wb_register: 2917 case ARM::VLD1d64wb_register: 2918 case ARM::VLD1q8wb_fixed: 2919 case ARM::VLD1q16wb_fixed: 2920 case ARM::VLD1q32wb_fixed: 2921 case ARM::VLD1q64wb_fixed: 2922 case ARM::VLD1q8wb_register: 2923 case ARM::VLD1q16wb_register: 2924 case ARM::VLD1q32wb_register: 2925 case ARM::VLD1q64wb_register: 2926 case ARM::VLD1d8Twb_fixed: 2927 case ARM::VLD1d8Twb_register: 2928 case ARM::VLD1d16Twb_fixed: 2929 case ARM::VLD1d16Twb_register: 2930 case ARM::VLD1d32Twb_fixed: 2931 case ARM::VLD1d32Twb_register: 2932 case ARM::VLD1d64Twb_fixed: 2933 case ARM::VLD1d64Twb_register: 2934 case ARM::VLD1d8Qwb_fixed: 2935 case ARM::VLD1d8Qwb_register: 2936 case ARM::VLD1d16Qwb_fixed: 2937 case ARM::VLD1d16Qwb_register: 2938 case ARM::VLD1d32Qwb_fixed: 2939 case ARM::VLD1d32Qwb_register: 2940 case ARM::VLD1d64Qwb_fixed: 2941 case ARM::VLD1d64Qwb_register: 2942 case ARM::VLD2d8wb_fixed: 2943 case ARM::VLD2d16wb_fixed: 2944 case ARM::VLD2d32wb_fixed: 2945 case ARM::VLD2q8wb_fixed: 2946 case ARM::VLD2q16wb_fixed: 2947 case ARM::VLD2q32wb_fixed: 2948 case ARM::VLD2d8wb_register: 2949 case ARM::VLD2d16wb_register: 2950 case ARM::VLD2d32wb_register: 2951 case ARM::VLD2q8wb_register: 2952 case ARM::VLD2q16wb_register: 2953 case ARM::VLD2q32wb_register: 2954 case ARM::VLD2b8wb_fixed: 2955 case ARM::VLD2b16wb_fixed: 2956 case ARM::VLD2b32wb_fixed: 2957 case ARM::VLD2b8wb_register: 2958 case ARM::VLD2b16wb_register: 2959 case ARM::VLD2b32wb_register: 2960 Inst.addOperand(MCOperand::createImm(0)); 2961 break; 2962 case ARM::VLD3d8_UPD: 2963 case ARM::VLD3d16_UPD: 2964 case ARM::VLD3d32_UPD: 2965 case ARM::VLD3q8_UPD: 2966 case ARM::VLD3q16_UPD: 2967 case ARM::VLD3q32_UPD: 2968 case ARM::VLD4d8_UPD: 2969 case ARM::VLD4d16_UPD: 2970 case ARM::VLD4d32_UPD: 2971 case ARM::VLD4q8_UPD: 2972 case ARM::VLD4q16_UPD: 2973 case ARM::VLD4q32_UPD: 2974 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2975 return MCDisassembler::Fail; 2976 break; 2977 default: 2978 break; 2979 } 2980 2981 // AddrMode6 Base (register+alignment) 2982 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2983 return MCDisassembler::Fail; 2984 2985 // AddrMode6 Offset (register) 2986 switch (Inst.getOpcode()) { 2987 default: 2988 // The below have been updated to have explicit am6offset split 2989 // between fixed and register offset. For those instructions not 2990 // yet updated, we need to add an additional reg0 operand for the 2991 // fixed variant. 2992 // 2993 // The fixed offset encodes as Rm == 0xd, so we check for that. 2994 if (Rm == 0xd) { 2995 Inst.addOperand(MCOperand::createReg(0)); 2996 break; 2997 } 2998 // Fall through to handle the register offset variant. 2999 LLVM_FALLTHROUGH; 3000 case ARM::VLD1d8wb_fixed: 3001 case ARM::VLD1d16wb_fixed: 3002 case ARM::VLD1d32wb_fixed: 3003 case ARM::VLD1d64wb_fixed: 3004 case ARM::VLD1d8Twb_fixed: 3005 case ARM::VLD1d16Twb_fixed: 3006 case ARM::VLD1d32Twb_fixed: 3007 case ARM::VLD1d64Twb_fixed: 3008 case ARM::VLD1d8Qwb_fixed: 3009 case ARM::VLD1d16Qwb_fixed: 3010 case ARM::VLD1d32Qwb_fixed: 3011 case ARM::VLD1d64Qwb_fixed: 3012 case ARM::VLD1d8wb_register: 3013 case ARM::VLD1d16wb_register: 3014 case ARM::VLD1d32wb_register: 3015 case ARM::VLD1d64wb_register: 3016 case ARM::VLD1q8wb_fixed: 3017 case ARM::VLD1q16wb_fixed: 3018 case ARM::VLD1q32wb_fixed: 3019 case ARM::VLD1q64wb_fixed: 3020 case ARM::VLD1q8wb_register: 3021 case ARM::VLD1q16wb_register: 3022 case ARM::VLD1q32wb_register: 3023 case ARM::VLD1q64wb_register: 3024 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3025 // variant encodes Rm == 0xf. Anything else is a register offset post- 3026 // increment and we need to add the register operand to the instruction. 3027 if (Rm != 0xD && Rm != 0xF && 3028 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3029 return MCDisassembler::Fail; 3030 break; 3031 case ARM::VLD2d8wb_fixed: 3032 case ARM::VLD2d16wb_fixed: 3033 case ARM::VLD2d32wb_fixed: 3034 case ARM::VLD2b8wb_fixed: 3035 case ARM::VLD2b16wb_fixed: 3036 case ARM::VLD2b32wb_fixed: 3037 case ARM::VLD2q8wb_fixed: 3038 case ARM::VLD2q16wb_fixed: 3039 case ARM::VLD2q32wb_fixed: 3040 break; 3041 } 3042 3043 return S; 3044 } 3045 3046 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 3047 uint64_t Address, const void *Decoder) { 3048 unsigned type = fieldFromInstruction(Insn, 8, 4); 3049 unsigned align = fieldFromInstruction(Insn, 4, 2); 3050 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 3051 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 3052 if (type == 10 && align == 3) return MCDisassembler::Fail; 3053 3054 unsigned load = fieldFromInstruction(Insn, 21, 1); 3055 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3056 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3057 } 3058 3059 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 3060 uint64_t Address, const void *Decoder) { 3061 unsigned size = fieldFromInstruction(Insn, 6, 2); 3062 if (size == 3) return MCDisassembler::Fail; 3063 3064 unsigned type = fieldFromInstruction(Insn, 8, 4); 3065 unsigned align = fieldFromInstruction(Insn, 4, 2); 3066 if (type == 8 && align == 3) return MCDisassembler::Fail; 3067 if (type == 9 && align == 3) return MCDisassembler::Fail; 3068 3069 unsigned load = fieldFromInstruction(Insn, 21, 1); 3070 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3071 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3072 } 3073 3074 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3075 uint64_t Address, const void *Decoder) { 3076 unsigned size = fieldFromInstruction(Insn, 6, 2); 3077 if (size == 3) return MCDisassembler::Fail; 3078 3079 unsigned align = fieldFromInstruction(Insn, 4, 2); 3080 if (align & 2) return MCDisassembler::Fail; 3081 3082 unsigned load = fieldFromInstruction(Insn, 21, 1); 3083 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3084 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3085 } 3086 3087 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3088 uint64_t Address, const void *Decoder) { 3089 unsigned size = fieldFromInstruction(Insn, 6, 2); 3090 if (size == 3) return MCDisassembler::Fail; 3091 3092 unsigned load = fieldFromInstruction(Insn, 21, 1); 3093 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3094 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3095 } 3096 3097 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3098 uint64_t Address, const void *Decoder) { 3099 DecodeStatus S = MCDisassembler::Success; 3100 3101 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3102 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3103 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3104 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3105 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3106 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3107 3108 // Writeback Operand 3109 switch (Inst.getOpcode()) { 3110 case ARM::VST1d8wb_fixed: 3111 case ARM::VST1d16wb_fixed: 3112 case ARM::VST1d32wb_fixed: 3113 case ARM::VST1d64wb_fixed: 3114 case ARM::VST1d8wb_register: 3115 case ARM::VST1d16wb_register: 3116 case ARM::VST1d32wb_register: 3117 case ARM::VST1d64wb_register: 3118 case ARM::VST1q8wb_fixed: 3119 case ARM::VST1q16wb_fixed: 3120 case ARM::VST1q32wb_fixed: 3121 case ARM::VST1q64wb_fixed: 3122 case ARM::VST1q8wb_register: 3123 case ARM::VST1q16wb_register: 3124 case ARM::VST1q32wb_register: 3125 case ARM::VST1q64wb_register: 3126 case ARM::VST1d8Twb_fixed: 3127 case ARM::VST1d16Twb_fixed: 3128 case ARM::VST1d32Twb_fixed: 3129 case ARM::VST1d64Twb_fixed: 3130 case ARM::VST1d8Twb_register: 3131 case ARM::VST1d16Twb_register: 3132 case ARM::VST1d32Twb_register: 3133 case ARM::VST1d64Twb_register: 3134 case ARM::VST1d8Qwb_fixed: 3135 case ARM::VST1d16Qwb_fixed: 3136 case ARM::VST1d32Qwb_fixed: 3137 case ARM::VST1d64Qwb_fixed: 3138 case ARM::VST1d8Qwb_register: 3139 case ARM::VST1d16Qwb_register: 3140 case ARM::VST1d32Qwb_register: 3141 case ARM::VST1d64Qwb_register: 3142 case ARM::VST2d8wb_fixed: 3143 case ARM::VST2d16wb_fixed: 3144 case ARM::VST2d32wb_fixed: 3145 case ARM::VST2d8wb_register: 3146 case ARM::VST2d16wb_register: 3147 case ARM::VST2d32wb_register: 3148 case ARM::VST2q8wb_fixed: 3149 case ARM::VST2q16wb_fixed: 3150 case ARM::VST2q32wb_fixed: 3151 case ARM::VST2q8wb_register: 3152 case ARM::VST2q16wb_register: 3153 case ARM::VST2q32wb_register: 3154 case ARM::VST2b8wb_fixed: 3155 case ARM::VST2b16wb_fixed: 3156 case ARM::VST2b32wb_fixed: 3157 case ARM::VST2b8wb_register: 3158 case ARM::VST2b16wb_register: 3159 case ARM::VST2b32wb_register: 3160 if (Rm == 0xF) 3161 return MCDisassembler::Fail; 3162 Inst.addOperand(MCOperand::createImm(0)); 3163 break; 3164 case ARM::VST3d8_UPD: 3165 case ARM::VST3d16_UPD: 3166 case ARM::VST3d32_UPD: 3167 case ARM::VST3q8_UPD: 3168 case ARM::VST3q16_UPD: 3169 case ARM::VST3q32_UPD: 3170 case ARM::VST4d8_UPD: 3171 case ARM::VST4d16_UPD: 3172 case ARM::VST4d32_UPD: 3173 case ARM::VST4q8_UPD: 3174 case ARM::VST4q16_UPD: 3175 case ARM::VST4q32_UPD: 3176 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3177 return MCDisassembler::Fail; 3178 break; 3179 default: 3180 break; 3181 } 3182 3183 // AddrMode6 Base (register+alignment) 3184 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3185 return MCDisassembler::Fail; 3186 3187 // AddrMode6 Offset (register) 3188 switch (Inst.getOpcode()) { 3189 default: 3190 if (Rm == 0xD) 3191 Inst.addOperand(MCOperand::createReg(0)); 3192 else if (Rm != 0xF) { 3193 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3194 return MCDisassembler::Fail; 3195 } 3196 break; 3197 case ARM::VST1d8wb_fixed: 3198 case ARM::VST1d16wb_fixed: 3199 case ARM::VST1d32wb_fixed: 3200 case ARM::VST1d64wb_fixed: 3201 case ARM::VST1q8wb_fixed: 3202 case ARM::VST1q16wb_fixed: 3203 case ARM::VST1q32wb_fixed: 3204 case ARM::VST1q64wb_fixed: 3205 case ARM::VST1d8Twb_fixed: 3206 case ARM::VST1d16Twb_fixed: 3207 case ARM::VST1d32Twb_fixed: 3208 case ARM::VST1d64Twb_fixed: 3209 case ARM::VST1d8Qwb_fixed: 3210 case ARM::VST1d16Qwb_fixed: 3211 case ARM::VST1d32Qwb_fixed: 3212 case ARM::VST1d64Qwb_fixed: 3213 case ARM::VST2d8wb_fixed: 3214 case ARM::VST2d16wb_fixed: 3215 case ARM::VST2d32wb_fixed: 3216 case ARM::VST2q8wb_fixed: 3217 case ARM::VST2q16wb_fixed: 3218 case ARM::VST2q32wb_fixed: 3219 case ARM::VST2b8wb_fixed: 3220 case ARM::VST2b16wb_fixed: 3221 case ARM::VST2b32wb_fixed: 3222 break; 3223 } 3224 3225 // First input register 3226 switch (Inst.getOpcode()) { 3227 case ARM::VST1q16: 3228 case ARM::VST1q32: 3229 case ARM::VST1q64: 3230 case ARM::VST1q8: 3231 case ARM::VST1q16wb_fixed: 3232 case ARM::VST1q16wb_register: 3233 case ARM::VST1q32wb_fixed: 3234 case ARM::VST1q32wb_register: 3235 case ARM::VST1q64wb_fixed: 3236 case ARM::VST1q64wb_register: 3237 case ARM::VST1q8wb_fixed: 3238 case ARM::VST1q8wb_register: 3239 case ARM::VST2d16: 3240 case ARM::VST2d32: 3241 case ARM::VST2d8: 3242 case ARM::VST2d16wb_fixed: 3243 case ARM::VST2d16wb_register: 3244 case ARM::VST2d32wb_fixed: 3245 case ARM::VST2d32wb_register: 3246 case ARM::VST2d8wb_fixed: 3247 case ARM::VST2d8wb_register: 3248 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3249 return MCDisassembler::Fail; 3250 break; 3251 case ARM::VST2b16: 3252 case ARM::VST2b32: 3253 case ARM::VST2b8: 3254 case ARM::VST2b16wb_fixed: 3255 case ARM::VST2b16wb_register: 3256 case ARM::VST2b32wb_fixed: 3257 case ARM::VST2b32wb_register: 3258 case ARM::VST2b8wb_fixed: 3259 case ARM::VST2b8wb_register: 3260 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3261 return MCDisassembler::Fail; 3262 break; 3263 default: 3264 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3265 return MCDisassembler::Fail; 3266 } 3267 3268 // Second input register 3269 switch (Inst.getOpcode()) { 3270 case ARM::VST3d8: 3271 case ARM::VST3d16: 3272 case ARM::VST3d32: 3273 case ARM::VST3d8_UPD: 3274 case ARM::VST3d16_UPD: 3275 case ARM::VST3d32_UPD: 3276 case ARM::VST4d8: 3277 case ARM::VST4d16: 3278 case ARM::VST4d32: 3279 case ARM::VST4d8_UPD: 3280 case ARM::VST4d16_UPD: 3281 case ARM::VST4d32_UPD: 3282 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3283 return MCDisassembler::Fail; 3284 break; 3285 case ARM::VST3q8: 3286 case ARM::VST3q16: 3287 case ARM::VST3q32: 3288 case ARM::VST3q8_UPD: 3289 case ARM::VST3q16_UPD: 3290 case ARM::VST3q32_UPD: 3291 case ARM::VST4q8: 3292 case ARM::VST4q16: 3293 case ARM::VST4q32: 3294 case ARM::VST4q8_UPD: 3295 case ARM::VST4q16_UPD: 3296 case ARM::VST4q32_UPD: 3297 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3298 return MCDisassembler::Fail; 3299 break; 3300 default: 3301 break; 3302 } 3303 3304 // Third input register 3305 switch (Inst.getOpcode()) { 3306 case ARM::VST3d8: 3307 case ARM::VST3d16: 3308 case ARM::VST3d32: 3309 case ARM::VST3d8_UPD: 3310 case ARM::VST3d16_UPD: 3311 case ARM::VST3d32_UPD: 3312 case ARM::VST4d8: 3313 case ARM::VST4d16: 3314 case ARM::VST4d32: 3315 case ARM::VST4d8_UPD: 3316 case ARM::VST4d16_UPD: 3317 case ARM::VST4d32_UPD: 3318 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3319 return MCDisassembler::Fail; 3320 break; 3321 case ARM::VST3q8: 3322 case ARM::VST3q16: 3323 case ARM::VST3q32: 3324 case ARM::VST3q8_UPD: 3325 case ARM::VST3q16_UPD: 3326 case ARM::VST3q32_UPD: 3327 case ARM::VST4q8: 3328 case ARM::VST4q16: 3329 case ARM::VST4q32: 3330 case ARM::VST4q8_UPD: 3331 case ARM::VST4q16_UPD: 3332 case ARM::VST4q32_UPD: 3333 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3334 return MCDisassembler::Fail; 3335 break; 3336 default: 3337 break; 3338 } 3339 3340 // Fourth input register 3341 switch (Inst.getOpcode()) { 3342 case ARM::VST4d8: 3343 case ARM::VST4d16: 3344 case ARM::VST4d32: 3345 case ARM::VST4d8_UPD: 3346 case ARM::VST4d16_UPD: 3347 case ARM::VST4d32_UPD: 3348 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3349 return MCDisassembler::Fail; 3350 break; 3351 case ARM::VST4q8: 3352 case ARM::VST4q16: 3353 case ARM::VST4q32: 3354 case ARM::VST4q8_UPD: 3355 case ARM::VST4q16_UPD: 3356 case ARM::VST4q32_UPD: 3357 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3358 return MCDisassembler::Fail; 3359 break; 3360 default: 3361 break; 3362 } 3363 3364 return S; 3365 } 3366 3367 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3368 uint64_t Address, const void *Decoder) { 3369 DecodeStatus S = MCDisassembler::Success; 3370 3371 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3372 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3373 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3374 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3375 unsigned align = fieldFromInstruction(Insn, 4, 1); 3376 unsigned size = fieldFromInstruction(Insn, 6, 2); 3377 3378 if (size == 0 && align == 1) 3379 return MCDisassembler::Fail; 3380 align *= (1 << size); 3381 3382 switch (Inst.getOpcode()) { 3383 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3384 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3385 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3386 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3387 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3388 return MCDisassembler::Fail; 3389 break; 3390 default: 3391 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3392 return MCDisassembler::Fail; 3393 break; 3394 } 3395 if (Rm != 0xF) { 3396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3397 return MCDisassembler::Fail; 3398 } 3399 3400 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3401 return MCDisassembler::Fail; 3402 Inst.addOperand(MCOperand::createImm(align)); 3403 3404 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3405 // variant encodes Rm == 0xf. Anything else is a register offset post- 3406 // increment and we need to add the register operand to the instruction. 3407 if (Rm != 0xD && Rm != 0xF && 3408 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 3411 return S; 3412 } 3413 3414 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3415 uint64_t Address, const void *Decoder) { 3416 DecodeStatus S = MCDisassembler::Success; 3417 3418 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3419 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3420 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3421 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3422 unsigned align = fieldFromInstruction(Insn, 4, 1); 3423 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3424 align *= 2*size; 3425 3426 switch (Inst.getOpcode()) { 3427 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3428 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3429 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3430 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3431 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3432 return MCDisassembler::Fail; 3433 break; 3434 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3435 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3436 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3437 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3438 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3439 return MCDisassembler::Fail; 3440 break; 3441 default: 3442 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3443 return MCDisassembler::Fail; 3444 break; 3445 } 3446 3447 if (Rm != 0xF) 3448 Inst.addOperand(MCOperand::createImm(0)); 3449 3450 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3451 return MCDisassembler::Fail; 3452 Inst.addOperand(MCOperand::createImm(align)); 3453 3454 if (Rm != 0xD && Rm != 0xF) { 3455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3456 return MCDisassembler::Fail; 3457 } 3458 3459 return S; 3460 } 3461 3462 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3463 uint64_t Address, const void *Decoder) { 3464 DecodeStatus S = MCDisassembler::Success; 3465 3466 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3467 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3468 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3469 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3470 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3471 3472 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3473 return MCDisassembler::Fail; 3474 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3475 return MCDisassembler::Fail; 3476 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3477 return MCDisassembler::Fail; 3478 if (Rm != 0xF) { 3479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3480 return MCDisassembler::Fail; 3481 } 3482 3483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3484 return MCDisassembler::Fail; 3485 Inst.addOperand(MCOperand::createImm(0)); 3486 3487 if (Rm == 0xD) 3488 Inst.addOperand(MCOperand::createReg(0)); 3489 else if (Rm != 0xF) { 3490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3491 return MCDisassembler::Fail; 3492 } 3493 3494 return S; 3495 } 3496 3497 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3498 uint64_t Address, const void *Decoder) { 3499 DecodeStatus S = MCDisassembler::Success; 3500 3501 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3502 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3503 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3504 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3505 unsigned size = fieldFromInstruction(Insn, 6, 2); 3506 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3507 unsigned align = fieldFromInstruction(Insn, 4, 1); 3508 3509 if (size == 0x3) { 3510 if (align == 0) 3511 return MCDisassembler::Fail; 3512 align = 16; 3513 } else { 3514 if (size == 2) { 3515 align *= 8; 3516 } else { 3517 size = 1 << size; 3518 align *= 4*size; 3519 } 3520 } 3521 3522 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3523 return MCDisassembler::Fail; 3524 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3525 return MCDisassembler::Fail; 3526 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3527 return MCDisassembler::Fail; 3528 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3529 return MCDisassembler::Fail; 3530 if (Rm != 0xF) { 3531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3532 return MCDisassembler::Fail; 3533 } 3534 3535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3536 return MCDisassembler::Fail; 3537 Inst.addOperand(MCOperand::createImm(align)); 3538 3539 if (Rm == 0xD) 3540 Inst.addOperand(MCOperand::createReg(0)); 3541 else if (Rm != 0xF) { 3542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3543 return MCDisassembler::Fail; 3544 } 3545 3546 return S; 3547 } 3548 3549 static DecodeStatus 3550 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3551 uint64_t Address, const void *Decoder) { 3552 DecodeStatus S = MCDisassembler::Success; 3553 3554 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3555 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3556 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3557 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3558 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3559 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3560 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3561 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3562 3563 if (Q) { 3564 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3565 return MCDisassembler::Fail; 3566 } else { 3567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3568 return MCDisassembler::Fail; 3569 } 3570 3571 Inst.addOperand(MCOperand::createImm(imm)); 3572 3573 switch (Inst.getOpcode()) { 3574 case ARM::VORRiv4i16: 3575 case ARM::VORRiv2i32: 3576 case ARM::VBICiv4i16: 3577 case ARM::VBICiv2i32: 3578 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3579 return MCDisassembler::Fail; 3580 break; 3581 case ARM::VORRiv8i16: 3582 case ARM::VORRiv4i32: 3583 case ARM::VBICiv8i16: 3584 case ARM::VBICiv4i32: 3585 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3586 return MCDisassembler::Fail; 3587 break; 3588 default: 3589 break; 3590 } 3591 3592 return S; 3593 } 3594 3595 static DecodeStatus 3596 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3597 uint64_t Address, const void *Decoder) { 3598 DecodeStatus S = MCDisassembler::Success; 3599 3600 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3601 fieldFromInstruction(Insn, 13, 3)); 3602 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3603 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3604 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3605 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3606 imm |= cmode << 8; 3607 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3608 3609 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3610 return MCDisassembler::Fail; 3611 3612 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3613 return MCDisassembler::Fail; 3614 3615 Inst.addOperand(MCOperand::createImm(imm)); 3616 3617 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3618 Inst.addOperand(MCOperand::createReg(0)); 3619 Inst.addOperand(MCOperand::createImm(0)); 3620 3621 return S; 3622 } 3623 3624 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3625 uint64_t Address, const void *Decoder) { 3626 DecodeStatus S = MCDisassembler::Success; 3627 3628 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3629 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3630 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3631 return MCDisassembler::Fail; 3632 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3633 3634 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3635 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3636 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3637 return MCDisassembler::Fail; 3638 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3639 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3640 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3641 return MCDisassembler::Fail; 3642 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3643 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3644 Inst.addOperand(MCOperand::createImm(Qd)); 3645 3646 return S; 3647 } 3648 3649 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3650 uint64_t Address, const void *Decoder) { 3651 DecodeStatus S = MCDisassembler::Success; 3652 3653 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3654 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3655 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3656 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3657 unsigned size = fieldFromInstruction(Insn, 18, 2); 3658 3659 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3660 return MCDisassembler::Fail; 3661 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3662 return MCDisassembler::Fail; 3663 Inst.addOperand(MCOperand::createImm(8 << size)); 3664 3665 return S; 3666 } 3667 3668 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3669 uint64_t Address, const void *Decoder) { 3670 Inst.addOperand(MCOperand::createImm(8 - Val)); 3671 return MCDisassembler::Success; 3672 } 3673 3674 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3675 uint64_t Address, const void *Decoder) { 3676 Inst.addOperand(MCOperand::createImm(16 - Val)); 3677 return MCDisassembler::Success; 3678 } 3679 3680 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3681 uint64_t Address, const void *Decoder) { 3682 Inst.addOperand(MCOperand::createImm(32 - Val)); 3683 return MCDisassembler::Success; 3684 } 3685 3686 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3687 uint64_t Address, const void *Decoder) { 3688 Inst.addOperand(MCOperand::createImm(64 - Val)); 3689 return MCDisassembler::Success; 3690 } 3691 3692 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3693 uint64_t Address, const void *Decoder) { 3694 DecodeStatus S = MCDisassembler::Success; 3695 3696 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3697 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3698 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3699 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3700 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3701 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3702 unsigned op = fieldFromInstruction(Insn, 6, 1); 3703 3704 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3705 return MCDisassembler::Fail; 3706 if (op) { 3707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3708 return MCDisassembler::Fail; // Writeback 3709 } 3710 3711 switch (Inst.getOpcode()) { 3712 case ARM::VTBL2: 3713 case ARM::VTBX2: 3714 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3715 return MCDisassembler::Fail; 3716 break; 3717 default: 3718 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3719 return MCDisassembler::Fail; 3720 } 3721 3722 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3723 return MCDisassembler::Fail; 3724 3725 return S; 3726 } 3727 3728 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3729 uint64_t Address, const void *Decoder) { 3730 DecodeStatus S = MCDisassembler::Success; 3731 3732 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3733 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3734 3735 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3736 return MCDisassembler::Fail; 3737 3738 switch(Inst.getOpcode()) { 3739 default: 3740 return MCDisassembler::Fail; 3741 case ARM::tADR: 3742 break; // tADR does not explicitly represent the PC as an operand. 3743 case ARM::tADDrSPi: 3744 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3745 break; 3746 } 3747 3748 Inst.addOperand(MCOperand::createImm(imm)); 3749 return S; 3750 } 3751 3752 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3753 uint64_t Address, const void *Decoder) { 3754 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3755 true, 2, Inst, Decoder)) 3756 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3757 return MCDisassembler::Success; 3758 } 3759 3760 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3761 uint64_t Address, const void *Decoder) { 3762 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3763 true, 4, Inst, Decoder)) 3764 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3765 return MCDisassembler::Success; 3766 } 3767 3768 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3769 uint64_t Address, const void *Decoder) { 3770 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3771 true, 2, Inst, Decoder)) 3772 Inst.addOperand(MCOperand::createImm(Val << 1)); 3773 return MCDisassembler::Success; 3774 } 3775 3776 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3777 uint64_t Address, const void *Decoder) { 3778 DecodeStatus S = MCDisassembler::Success; 3779 3780 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3781 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3782 3783 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3784 return MCDisassembler::Fail; 3785 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3786 return MCDisassembler::Fail; 3787 3788 return S; 3789 } 3790 3791 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3792 uint64_t Address, const void *Decoder) { 3793 DecodeStatus S = MCDisassembler::Success; 3794 3795 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3796 unsigned imm = fieldFromInstruction(Val, 3, 5); 3797 3798 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3799 return MCDisassembler::Fail; 3800 Inst.addOperand(MCOperand::createImm(imm)); 3801 3802 return S; 3803 } 3804 3805 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3806 uint64_t Address, const void *Decoder) { 3807 unsigned imm = Val << 2; 3808 3809 Inst.addOperand(MCOperand::createImm(imm)); 3810 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3811 3812 return MCDisassembler::Success; 3813 } 3814 3815 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3816 uint64_t Address, const void *Decoder) { 3817 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3818 Inst.addOperand(MCOperand::createImm(Val)); 3819 3820 return MCDisassembler::Success; 3821 } 3822 3823 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3824 uint64_t Address, const void *Decoder) { 3825 DecodeStatus S = MCDisassembler::Success; 3826 3827 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3828 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3829 unsigned imm = fieldFromInstruction(Val, 0, 2); 3830 3831 // Thumb stores cannot use PC as dest register. 3832 switch (Inst.getOpcode()) { 3833 case ARM::t2STRHs: 3834 case ARM::t2STRBs: 3835 case ARM::t2STRs: 3836 if (Rn == 15) 3837 return MCDisassembler::Fail; 3838 break; 3839 default: 3840 break; 3841 } 3842 3843 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3844 return MCDisassembler::Fail; 3845 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3846 return MCDisassembler::Fail; 3847 Inst.addOperand(MCOperand::createImm(imm)); 3848 3849 return S; 3850 } 3851 3852 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3853 uint64_t Address, const void *Decoder) { 3854 DecodeStatus S = MCDisassembler::Success; 3855 3856 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3857 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3858 3859 const FeatureBitset &featureBits = 3860 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3861 3862 bool hasMP = featureBits[ARM::FeatureMP]; 3863 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3864 3865 if (Rn == 15) { 3866 switch (Inst.getOpcode()) { 3867 case ARM::t2LDRBs: 3868 Inst.setOpcode(ARM::t2LDRBpci); 3869 break; 3870 case ARM::t2LDRHs: 3871 Inst.setOpcode(ARM::t2LDRHpci); 3872 break; 3873 case ARM::t2LDRSHs: 3874 Inst.setOpcode(ARM::t2LDRSHpci); 3875 break; 3876 case ARM::t2LDRSBs: 3877 Inst.setOpcode(ARM::t2LDRSBpci); 3878 break; 3879 case ARM::t2LDRs: 3880 Inst.setOpcode(ARM::t2LDRpci); 3881 break; 3882 case ARM::t2PLDs: 3883 Inst.setOpcode(ARM::t2PLDpci); 3884 break; 3885 case ARM::t2PLIs: 3886 Inst.setOpcode(ARM::t2PLIpci); 3887 break; 3888 default: 3889 return MCDisassembler::Fail; 3890 } 3891 3892 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3893 } 3894 3895 if (Rt == 15) { 3896 switch (Inst.getOpcode()) { 3897 case ARM::t2LDRSHs: 3898 return MCDisassembler::Fail; 3899 case ARM::t2LDRHs: 3900 Inst.setOpcode(ARM::t2PLDWs); 3901 break; 3902 case ARM::t2LDRSBs: 3903 Inst.setOpcode(ARM::t2PLIs); 3904 break; 3905 default: 3906 break; 3907 } 3908 } 3909 3910 switch (Inst.getOpcode()) { 3911 case ARM::t2PLDs: 3912 break; 3913 case ARM::t2PLIs: 3914 if (!hasV7Ops) 3915 return MCDisassembler::Fail; 3916 break; 3917 case ARM::t2PLDWs: 3918 if (!hasV7Ops || !hasMP) 3919 return MCDisassembler::Fail; 3920 break; 3921 default: 3922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3923 return MCDisassembler::Fail; 3924 } 3925 3926 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3927 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3928 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3929 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3930 return MCDisassembler::Fail; 3931 3932 return S; 3933 } 3934 3935 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3936 uint64_t Address, const void* Decoder) { 3937 DecodeStatus S = MCDisassembler::Success; 3938 3939 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3940 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3941 unsigned U = fieldFromInstruction(Insn, 9, 1); 3942 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3943 imm |= (U << 8); 3944 imm |= (Rn << 9); 3945 unsigned add = fieldFromInstruction(Insn, 9, 1); 3946 3947 const FeatureBitset &featureBits = 3948 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3949 3950 bool hasMP = featureBits[ARM::FeatureMP]; 3951 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3952 3953 if (Rn == 15) { 3954 switch (Inst.getOpcode()) { 3955 case ARM::t2LDRi8: 3956 Inst.setOpcode(ARM::t2LDRpci); 3957 break; 3958 case ARM::t2LDRBi8: 3959 Inst.setOpcode(ARM::t2LDRBpci); 3960 break; 3961 case ARM::t2LDRSBi8: 3962 Inst.setOpcode(ARM::t2LDRSBpci); 3963 break; 3964 case ARM::t2LDRHi8: 3965 Inst.setOpcode(ARM::t2LDRHpci); 3966 break; 3967 case ARM::t2LDRSHi8: 3968 Inst.setOpcode(ARM::t2LDRSHpci); 3969 break; 3970 case ARM::t2PLDi8: 3971 Inst.setOpcode(ARM::t2PLDpci); 3972 break; 3973 case ARM::t2PLIi8: 3974 Inst.setOpcode(ARM::t2PLIpci); 3975 break; 3976 default: 3977 return MCDisassembler::Fail; 3978 } 3979 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3980 } 3981 3982 if (Rt == 15) { 3983 switch (Inst.getOpcode()) { 3984 case ARM::t2LDRSHi8: 3985 return MCDisassembler::Fail; 3986 case ARM::t2LDRHi8: 3987 if (!add) 3988 Inst.setOpcode(ARM::t2PLDWi8); 3989 break; 3990 case ARM::t2LDRSBi8: 3991 Inst.setOpcode(ARM::t2PLIi8); 3992 break; 3993 default: 3994 break; 3995 } 3996 } 3997 3998 switch (Inst.getOpcode()) { 3999 case ARM::t2PLDi8: 4000 break; 4001 case ARM::t2PLIi8: 4002 if (!hasV7Ops) 4003 return MCDisassembler::Fail; 4004 break; 4005 case ARM::t2PLDWi8: 4006 if (!hasV7Ops || !hasMP) 4007 return MCDisassembler::Fail; 4008 break; 4009 default: 4010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4011 return MCDisassembler::Fail; 4012 } 4013 4014 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4015 return MCDisassembler::Fail; 4016 return S; 4017 } 4018 4019 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 4020 uint64_t Address, const void* Decoder) { 4021 DecodeStatus S = MCDisassembler::Success; 4022 4023 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4024 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4025 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4026 imm |= (Rn << 13); 4027 4028 const FeatureBitset &featureBits = 4029 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4030 4031 bool hasMP = featureBits[ARM::FeatureMP]; 4032 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4033 4034 if (Rn == 15) { 4035 switch (Inst.getOpcode()) { 4036 case ARM::t2LDRi12: 4037 Inst.setOpcode(ARM::t2LDRpci); 4038 break; 4039 case ARM::t2LDRHi12: 4040 Inst.setOpcode(ARM::t2LDRHpci); 4041 break; 4042 case ARM::t2LDRSHi12: 4043 Inst.setOpcode(ARM::t2LDRSHpci); 4044 break; 4045 case ARM::t2LDRBi12: 4046 Inst.setOpcode(ARM::t2LDRBpci); 4047 break; 4048 case ARM::t2LDRSBi12: 4049 Inst.setOpcode(ARM::t2LDRSBpci); 4050 break; 4051 case ARM::t2PLDi12: 4052 Inst.setOpcode(ARM::t2PLDpci); 4053 break; 4054 case ARM::t2PLIi12: 4055 Inst.setOpcode(ARM::t2PLIpci); 4056 break; 4057 default: 4058 return MCDisassembler::Fail; 4059 } 4060 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4061 } 4062 4063 if (Rt == 15) { 4064 switch (Inst.getOpcode()) { 4065 case ARM::t2LDRSHi12: 4066 return MCDisassembler::Fail; 4067 case ARM::t2LDRHi12: 4068 Inst.setOpcode(ARM::t2PLDWi12); 4069 break; 4070 case ARM::t2LDRSBi12: 4071 Inst.setOpcode(ARM::t2PLIi12); 4072 break; 4073 default: 4074 break; 4075 } 4076 } 4077 4078 switch (Inst.getOpcode()) { 4079 case ARM::t2PLDi12: 4080 break; 4081 case ARM::t2PLIi12: 4082 if (!hasV7Ops) 4083 return MCDisassembler::Fail; 4084 break; 4085 case ARM::t2PLDWi12: 4086 if (!hasV7Ops || !hasMP) 4087 return MCDisassembler::Fail; 4088 break; 4089 default: 4090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4091 return MCDisassembler::Fail; 4092 } 4093 4094 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4095 return MCDisassembler::Fail; 4096 return S; 4097 } 4098 4099 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 4100 uint64_t Address, const void* Decoder) { 4101 DecodeStatus S = MCDisassembler::Success; 4102 4103 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4104 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4105 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4106 imm |= (Rn << 9); 4107 4108 if (Rn == 15) { 4109 switch (Inst.getOpcode()) { 4110 case ARM::t2LDRT: 4111 Inst.setOpcode(ARM::t2LDRpci); 4112 break; 4113 case ARM::t2LDRBT: 4114 Inst.setOpcode(ARM::t2LDRBpci); 4115 break; 4116 case ARM::t2LDRHT: 4117 Inst.setOpcode(ARM::t2LDRHpci); 4118 break; 4119 case ARM::t2LDRSBT: 4120 Inst.setOpcode(ARM::t2LDRSBpci); 4121 break; 4122 case ARM::t2LDRSHT: 4123 Inst.setOpcode(ARM::t2LDRSHpci); 4124 break; 4125 default: 4126 return MCDisassembler::Fail; 4127 } 4128 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4129 } 4130 4131 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4132 return MCDisassembler::Fail; 4133 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4134 return MCDisassembler::Fail; 4135 return S; 4136 } 4137 4138 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4139 uint64_t Address, const void* Decoder) { 4140 DecodeStatus S = MCDisassembler::Success; 4141 4142 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4143 unsigned U = fieldFromInstruction(Insn, 23, 1); 4144 int imm = fieldFromInstruction(Insn, 0, 12); 4145 4146 const FeatureBitset &featureBits = 4147 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4148 4149 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4150 4151 if (Rt == 15) { 4152 switch (Inst.getOpcode()) { 4153 case ARM::t2LDRBpci: 4154 case ARM::t2LDRHpci: 4155 Inst.setOpcode(ARM::t2PLDpci); 4156 break; 4157 case ARM::t2LDRSBpci: 4158 Inst.setOpcode(ARM::t2PLIpci); 4159 break; 4160 case ARM::t2LDRSHpci: 4161 return MCDisassembler::Fail; 4162 default: 4163 break; 4164 } 4165 } 4166 4167 switch(Inst.getOpcode()) { 4168 case ARM::t2PLDpci: 4169 break; 4170 case ARM::t2PLIpci: 4171 if (!hasV7Ops) 4172 return MCDisassembler::Fail; 4173 break; 4174 default: 4175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4176 return MCDisassembler::Fail; 4177 } 4178 4179 if (!U) { 4180 // Special case for #-0. 4181 if (imm == 0) 4182 imm = INT32_MIN; 4183 else 4184 imm = -imm; 4185 } 4186 Inst.addOperand(MCOperand::createImm(imm)); 4187 4188 return S; 4189 } 4190 4191 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4192 uint64_t Address, const void *Decoder) { 4193 if (Val == 0) 4194 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4195 else { 4196 int imm = Val & 0xFF; 4197 4198 if (!(Val & 0x100)) imm *= -1; 4199 Inst.addOperand(MCOperand::createImm(imm * 4)); 4200 } 4201 4202 return MCDisassembler::Success; 4203 } 4204 4205 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4206 const void *Decoder) { 4207 if (Val == 0) 4208 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4209 else { 4210 int imm = Val & 0x7F; 4211 4212 if (!(Val & 0x80)) 4213 imm *= -1; 4214 Inst.addOperand(MCOperand::createImm(imm * 4)); 4215 } 4216 4217 return MCDisassembler::Success; 4218 } 4219 4220 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4221 uint64_t Address, const void *Decoder) { 4222 DecodeStatus S = MCDisassembler::Success; 4223 4224 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4225 unsigned imm = fieldFromInstruction(Val, 0, 9); 4226 4227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4228 return MCDisassembler::Fail; 4229 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4230 return MCDisassembler::Fail; 4231 4232 return S; 4233 } 4234 4235 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4236 uint64_t Address, 4237 const void *Decoder) { 4238 DecodeStatus S = MCDisassembler::Success; 4239 4240 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4241 unsigned imm = fieldFromInstruction(Val, 0, 8); 4242 4243 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4244 return MCDisassembler::Fail; 4245 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4246 return MCDisassembler::Fail; 4247 4248 return S; 4249 } 4250 4251 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4252 uint64_t Address, const void *Decoder) { 4253 DecodeStatus S = MCDisassembler::Success; 4254 4255 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4256 unsigned imm = fieldFromInstruction(Val, 0, 8); 4257 4258 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4259 return MCDisassembler::Fail; 4260 4261 Inst.addOperand(MCOperand::createImm(imm)); 4262 4263 return S; 4264 } 4265 4266 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4267 uint64_t Address, const void *Decoder) { 4268 int imm = Val & 0xFF; 4269 if (Val == 0) 4270 imm = INT32_MIN; 4271 else if (!(Val & 0x100)) 4272 imm *= -1; 4273 Inst.addOperand(MCOperand::createImm(imm)); 4274 4275 return MCDisassembler::Success; 4276 } 4277 4278 template<int shift> 4279 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4280 uint64_t Address, const void *Decoder) { 4281 int imm = Val & 0x7F; 4282 if (Val == 0) 4283 imm = INT32_MIN; 4284 else if (!(Val & 0x80)) 4285 imm *= -1; 4286 if (imm != INT32_MIN) 4287 imm *= (1U << shift); 4288 Inst.addOperand(MCOperand::createImm(imm)); 4289 4290 return MCDisassembler::Success; 4291 } 4292 4293 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4294 uint64_t Address, const void *Decoder) { 4295 DecodeStatus S = MCDisassembler::Success; 4296 4297 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4298 unsigned imm = fieldFromInstruction(Val, 0, 9); 4299 4300 // Thumb stores cannot use PC as dest register. 4301 switch (Inst.getOpcode()) { 4302 case ARM::t2STRT: 4303 case ARM::t2STRBT: 4304 case ARM::t2STRHT: 4305 case ARM::t2STRi8: 4306 case ARM::t2STRHi8: 4307 case ARM::t2STRBi8: 4308 if (Rn == 15) 4309 return MCDisassembler::Fail; 4310 break; 4311 default: 4312 break; 4313 } 4314 4315 // Some instructions always use an additive offset. 4316 switch (Inst.getOpcode()) { 4317 case ARM::t2LDRT: 4318 case ARM::t2LDRBT: 4319 case ARM::t2LDRHT: 4320 case ARM::t2LDRSBT: 4321 case ARM::t2LDRSHT: 4322 case ARM::t2STRT: 4323 case ARM::t2STRBT: 4324 case ARM::t2STRHT: 4325 imm |= 0x100; 4326 break; 4327 default: 4328 break; 4329 } 4330 4331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4332 return MCDisassembler::Fail; 4333 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4334 return MCDisassembler::Fail; 4335 4336 return S; 4337 } 4338 4339 template<int shift> 4340 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4341 uint64_t Address, 4342 const void *Decoder) { 4343 DecodeStatus S = MCDisassembler::Success; 4344 4345 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4346 unsigned imm = fieldFromInstruction(Val, 0, 8); 4347 4348 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4349 return MCDisassembler::Fail; 4350 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4351 return MCDisassembler::Fail; 4352 4353 return S; 4354 } 4355 4356 template<int shift, int WriteBack> 4357 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4358 uint64_t Address, 4359 const void *Decoder) { 4360 DecodeStatus S = MCDisassembler::Success; 4361 4362 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4363 unsigned imm = fieldFromInstruction(Val, 0, 8); 4364 if (WriteBack) { 4365 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4368 return MCDisassembler::Fail; 4369 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4370 return MCDisassembler::Fail; 4371 4372 return S; 4373 } 4374 4375 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4376 uint64_t Address, const void *Decoder) { 4377 DecodeStatus S = MCDisassembler::Success; 4378 4379 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4380 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4381 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4382 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4383 addr |= Rn << 9; 4384 unsigned load = fieldFromInstruction(Insn, 20, 1); 4385 4386 if (Rn == 15) { 4387 switch (Inst.getOpcode()) { 4388 case ARM::t2LDR_PRE: 4389 case ARM::t2LDR_POST: 4390 Inst.setOpcode(ARM::t2LDRpci); 4391 break; 4392 case ARM::t2LDRB_PRE: 4393 case ARM::t2LDRB_POST: 4394 Inst.setOpcode(ARM::t2LDRBpci); 4395 break; 4396 case ARM::t2LDRH_PRE: 4397 case ARM::t2LDRH_POST: 4398 Inst.setOpcode(ARM::t2LDRHpci); 4399 break; 4400 case ARM::t2LDRSB_PRE: 4401 case ARM::t2LDRSB_POST: 4402 if (Rt == 15) 4403 Inst.setOpcode(ARM::t2PLIpci); 4404 else 4405 Inst.setOpcode(ARM::t2LDRSBpci); 4406 break; 4407 case ARM::t2LDRSH_PRE: 4408 case ARM::t2LDRSH_POST: 4409 Inst.setOpcode(ARM::t2LDRSHpci); 4410 break; 4411 default: 4412 return MCDisassembler::Fail; 4413 } 4414 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4415 } 4416 4417 if (!load) { 4418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4419 return MCDisassembler::Fail; 4420 } 4421 4422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4423 return MCDisassembler::Fail; 4424 4425 if (load) { 4426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4427 return MCDisassembler::Fail; 4428 } 4429 4430 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4431 return MCDisassembler::Fail; 4432 4433 return S; 4434 } 4435 4436 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4437 uint64_t Address, const void *Decoder) { 4438 DecodeStatus S = MCDisassembler::Success; 4439 4440 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4441 unsigned imm = fieldFromInstruction(Val, 0, 12); 4442 4443 // Thumb stores cannot use PC as dest register. 4444 switch (Inst.getOpcode()) { 4445 case ARM::t2STRi12: 4446 case ARM::t2STRBi12: 4447 case ARM::t2STRHi12: 4448 if (Rn == 15) 4449 return MCDisassembler::Fail; 4450 break; 4451 default: 4452 break; 4453 } 4454 4455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4456 return MCDisassembler::Fail; 4457 Inst.addOperand(MCOperand::createImm(imm)); 4458 4459 return S; 4460 } 4461 4462 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4463 uint64_t Address, const void *Decoder) { 4464 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4465 4466 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4467 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4468 Inst.addOperand(MCOperand::createImm(imm)); 4469 4470 return MCDisassembler::Success; 4471 } 4472 4473 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4474 uint64_t Address, const void *Decoder) { 4475 DecodeStatus S = MCDisassembler::Success; 4476 4477 if (Inst.getOpcode() == ARM::tADDrSP) { 4478 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4479 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4480 4481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4482 return MCDisassembler::Fail; 4483 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4485 return MCDisassembler::Fail; 4486 } else if (Inst.getOpcode() == ARM::tADDspr) { 4487 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4488 4489 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4490 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4492 return MCDisassembler::Fail; 4493 } 4494 4495 return S; 4496 } 4497 4498 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4499 uint64_t Address, const void *Decoder) { 4500 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4501 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4502 4503 Inst.addOperand(MCOperand::createImm(imod)); 4504 Inst.addOperand(MCOperand::createImm(flags)); 4505 4506 return MCDisassembler::Success; 4507 } 4508 4509 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4510 uint64_t Address, const void *Decoder) { 4511 DecodeStatus S = MCDisassembler::Success; 4512 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4513 unsigned add = fieldFromInstruction(Insn, 4, 1); 4514 4515 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4516 return MCDisassembler::Fail; 4517 Inst.addOperand(MCOperand::createImm(add)); 4518 4519 return S; 4520 } 4521 4522 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4523 uint64_t Address, const void *Decoder) { 4524 DecodeStatus S = MCDisassembler::Success; 4525 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4526 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4527 4528 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4529 return MCDisassembler::Fail; 4530 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4531 return MCDisassembler::Fail; 4532 4533 return S; 4534 } 4535 4536 template<int shift> 4537 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4538 uint64_t Address, const void *Decoder) { 4539 DecodeStatus S = MCDisassembler::Success; 4540 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4541 int imm = fieldFromInstruction(Insn, 0, 7); 4542 4543 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4544 return MCDisassembler::Fail; 4545 4546 if(!fieldFromInstruction(Insn, 7, 1)) { 4547 if (imm == 0) 4548 imm = INT32_MIN; // indicate -0 4549 else 4550 imm *= -1; 4551 } 4552 if (imm != INT32_MIN) 4553 imm *= (1U << shift); 4554 Inst.addOperand(MCOperand::createImm(imm)); 4555 4556 return S; 4557 } 4558 4559 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4560 uint64_t Address, const void *Decoder) { 4561 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4562 // Note only one trailing zero not two. Also the J1 and J2 values are from 4563 // the encoded instruction. So here change to I1 and I2 values via: 4564 // I1 = NOT(J1 EOR S); 4565 // I2 = NOT(J2 EOR S); 4566 // and build the imm32 with two trailing zeros as documented: 4567 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4568 unsigned S = (Val >> 23) & 1; 4569 unsigned J1 = (Val >> 22) & 1; 4570 unsigned J2 = (Val >> 21) & 1; 4571 unsigned I1 = !(J1 ^ S); 4572 unsigned I2 = !(J2 ^ S); 4573 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4574 int imm32 = SignExtend32<25>(tmp << 1); 4575 4576 if (!tryAddingSymbolicOperand(Address, 4577 (Address & ~2u) + imm32 + 4, 4578 true, 4, Inst, Decoder)) 4579 Inst.addOperand(MCOperand::createImm(imm32)); 4580 return MCDisassembler::Success; 4581 } 4582 4583 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4584 uint64_t Address, const void *Decoder) { 4585 if (Val == 0xA || Val == 0xB) 4586 return MCDisassembler::Fail; 4587 4588 const FeatureBitset &featureBits = 4589 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4590 4591 if (!isValidCoprocessorNumber(Val, featureBits)) 4592 return MCDisassembler::Fail; 4593 4594 Inst.addOperand(MCOperand::createImm(Val)); 4595 return MCDisassembler::Success; 4596 } 4597 4598 static DecodeStatus 4599 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4600 uint64_t Address, const void *Decoder) { 4601 const FeatureBitset &FeatureBits = 4602 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4603 DecodeStatus S = MCDisassembler::Success; 4604 4605 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4606 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4607 4608 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4610 return MCDisassembler::Fail; 4611 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4612 return MCDisassembler::Fail; 4613 return S; 4614 } 4615 4616 static DecodeStatus 4617 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4618 uint64_t Address, const void *Decoder) { 4619 DecodeStatus S = MCDisassembler::Success; 4620 4621 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4622 if (pred == 0xE || pred == 0xF) { 4623 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4624 switch (opc) { 4625 default: 4626 return MCDisassembler::Fail; 4627 case 0xf3bf8f4: 4628 Inst.setOpcode(ARM::t2DSB); 4629 break; 4630 case 0xf3bf8f5: 4631 Inst.setOpcode(ARM::t2DMB); 4632 break; 4633 case 0xf3bf8f6: 4634 Inst.setOpcode(ARM::t2ISB); 4635 break; 4636 } 4637 4638 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4639 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4640 } 4641 4642 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4643 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4644 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4645 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4646 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4647 4648 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4649 return MCDisassembler::Fail; 4650 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4651 return MCDisassembler::Fail; 4652 4653 return S; 4654 } 4655 4656 // Decode a shifted immediate operand. These basically consist 4657 // of an 8-bit value, and a 4-bit directive that specifies either 4658 // a splat operation or a rotation. 4659 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4660 uint64_t Address, const void *Decoder) { 4661 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4662 if (ctrl == 0) { 4663 unsigned byte = fieldFromInstruction(Val, 8, 2); 4664 unsigned imm = fieldFromInstruction(Val, 0, 8); 4665 switch (byte) { 4666 case 0: 4667 Inst.addOperand(MCOperand::createImm(imm)); 4668 break; 4669 case 1: 4670 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4671 break; 4672 case 2: 4673 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4674 break; 4675 case 3: 4676 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4677 (imm << 8) | imm)); 4678 break; 4679 } 4680 } else { 4681 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4682 unsigned rot = fieldFromInstruction(Val, 7, 5); 4683 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4684 Inst.addOperand(MCOperand::createImm(imm)); 4685 } 4686 4687 return MCDisassembler::Success; 4688 } 4689 4690 static DecodeStatus 4691 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4692 uint64_t Address, const void *Decoder) { 4693 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4694 true, 2, Inst, Decoder)) 4695 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4696 return MCDisassembler::Success; 4697 } 4698 4699 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4700 uint64_t Address, 4701 const void *Decoder) { 4702 // Val is passed in as S:J1:J2:imm10:imm11 4703 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4704 // the encoded instruction. So here change to I1 and I2 values via: 4705 // I1 = NOT(J1 EOR S); 4706 // I2 = NOT(J2 EOR S); 4707 // and build the imm32 with one trailing zero as documented: 4708 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4709 unsigned S = (Val >> 23) & 1; 4710 unsigned J1 = (Val >> 22) & 1; 4711 unsigned J2 = (Val >> 21) & 1; 4712 unsigned I1 = !(J1 ^ S); 4713 unsigned I2 = !(J2 ^ S); 4714 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4715 int imm32 = SignExtend32<25>(tmp << 1); 4716 4717 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4718 true, 4, Inst, Decoder)) 4719 Inst.addOperand(MCOperand::createImm(imm32)); 4720 return MCDisassembler::Success; 4721 } 4722 4723 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4724 uint64_t Address, const void *Decoder) { 4725 if (Val & ~0xf) 4726 return MCDisassembler::Fail; 4727 4728 Inst.addOperand(MCOperand::createImm(Val)); 4729 return MCDisassembler::Success; 4730 } 4731 4732 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4733 uint64_t Address, const void *Decoder) { 4734 if (Val & ~0xf) 4735 return MCDisassembler::Fail; 4736 4737 Inst.addOperand(MCOperand::createImm(Val)); 4738 return MCDisassembler::Success; 4739 } 4740 4741 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4742 uint64_t Address, const void *Decoder) { 4743 DecodeStatus S = MCDisassembler::Success; 4744 const FeatureBitset &FeatureBits = 4745 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4746 4747 if (FeatureBits[ARM::FeatureMClass]) { 4748 unsigned ValLow = Val & 0xff; 4749 4750 // Validate the SYSm value first. 4751 switch (ValLow) { 4752 case 0: // apsr 4753 case 1: // iapsr 4754 case 2: // eapsr 4755 case 3: // xpsr 4756 case 5: // ipsr 4757 case 6: // epsr 4758 case 7: // iepsr 4759 case 8: // msp 4760 case 9: // psp 4761 case 16: // primask 4762 case 20: // control 4763 break; 4764 case 17: // basepri 4765 case 18: // basepri_max 4766 case 19: // faultmask 4767 if (!(FeatureBits[ARM::HasV7Ops])) 4768 // Values basepri, basepri_max and faultmask are only valid for v7m. 4769 return MCDisassembler::Fail; 4770 break; 4771 case 0x8a: // msplim_ns 4772 case 0x8b: // psplim_ns 4773 case 0x91: // basepri_ns 4774 case 0x93: // faultmask_ns 4775 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4776 return MCDisassembler::Fail; 4777 LLVM_FALLTHROUGH; 4778 case 10: // msplim 4779 case 11: // psplim 4780 case 0x88: // msp_ns 4781 case 0x89: // psp_ns 4782 case 0x90: // primask_ns 4783 case 0x94: // control_ns 4784 case 0x98: // sp_ns 4785 if (!(FeatureBits[ARM::Feature8MSecExt])) 4786 return MCDisassembler::Fail; 4787 break; 4788 case 0x20: // pac_key_p_0 4789 case 0x21: // pac_key_p_1 4790 case 0x22: // pac_key_p_2 4791 case 0x23: // pac_key_p_3 4792 case 0x24: // pac_key_u_0 4793 case 0x25: // pac_key_u_1 4794 case 0x26: // pac_key_u_2 4795 case 0x27: // pac_key_u_3 4796 case 0xa0: // pac_key_p_0_ns 4797 case 0xa1: // pac_key_p_1_ns 4798 case 0xa2: // pac_key_p_2_ns 4799 case 0xa3: // pac_key_p_3_ns 4800 case 0xa4: // pac_key_u_0_ns 4801 case 0xa5: // pac_key_u_1_ns 4802 case 0xa6: // pac_key_u_2_ns 4803 case 0xa7: // pac_key_u_3_ns 4804 if (!(FeatureBits[ARM::FeaturePACBTI])) 4805 return MCDisassembler::Fail; 4806 break; 4807 default: 4808 // Architecturally defined as unpredictable 4809 S = MCDisassembler::SoftFail; 4810 break; 4811 } 4812 4813 if (Inst.getOpcode() == ARM::t2MSR_M) { 4814 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4815 if (!(FeatureBits[ARM::HasV7Ops])) { 4816 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4817 // unpredictable. 4818 if (Mask != 2) 4819 S = MCDisassembler::SoftFail; 4820 } 4821 else { 4822 // The ARMv7-M architecture stores an additional 2-bit mask value in 4823 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4824 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4825 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4826 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4827 // only if the processor includes the DSP extension. 4828 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4829 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4830 S = MCDisassembler::SoftFail; 4831 } 4832 } 4833 } else { 4834 // A/R class 4835 if (Val == 0) 4836 return MCDisassembler::Fail; 4837 } 4838 Inst.addOperand(MCOperand::createImm(Val)); 4839 return S; 4840 } 4841 4842 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4843 uint64_t Address, const void *Decoder) { 4844 unsigned R = fieldFromInstruction(Val, 5, 1); 4845 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4846 4847 // The table of encodings for these banked registers comes from B9.2.3 of the 4848 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4849 // neater. So by fiat, these values are UNPREDICTABLE: 4850 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4851 return MCDisassembler::Fail; 4852 4853 Inst.addOperand(MCOperand::createImm(Val)); 4854 return MCDisassembler::Success; 4855 } 4856 4857 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4858 uint64_t Address, const void *Decoder) { 4859 DecodeStatus S = MCDisassembler::Success; 4860 4861 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4862 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4863 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4864 4865 if (Rn == 0xF) 4866 S = MCDisassembler::SoftFail; 4867 4868 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4869 return MCDisassembler::Fail; 4870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4871 return MCDisassembler::Fail; 4872 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4873 return MCDisassembler::Fail; 4874 4875 return S; 4876 } 4877 4878 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4879 uint64_t Address, 4880 const void *Decoder) { 4881 DecodeStatus S = MCDisassembler::Success; 4882 4883 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4884 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4885 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4886 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4887 4888 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4889 return MCDisassembler::Fail; 4890 4891 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4892 S = MCDisassembler::SoftFail; 4893 4894 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4895 return MCDisassembler::Fail; 4896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4897 return MCDisassembler::Fail; 4898 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4899 return MCDisassembler::Fail; 4900 4901 return S; 4902 } 4903 4904 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4905 uint64_t Address, const void *Decoder) { 4906 DecodeStatus S = MCDisassembler::Success; 4907 4908 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4909 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4910 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4911 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4912 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4913 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4914 4915 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4916 4917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4918 return MCDisassembler::Fail; 4919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4920 return MCDisassembler::Fail; 4921 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4922 return MCDisassembler::Fail; 4923 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4924 return MCDisassembler::Fail; 4925 4926 return S; 4927 } 4928 4929 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4930 uint64_t Address, const void *Decoder) { 4931 DecodeStatus S = MCDisassembler::Success; 4932 4933 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4934 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4935 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4936 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4937 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4938 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4939 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4940 4941 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4942 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4943 4944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4945 return MCDisassembler::Fail; 4946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4947 return MCDisassembler::Fail; 4948 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4949 return MCDisassembler::Fail; 4950 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4951 return MCDisassembler::Fail; 4952 4953 return S; 4954 } 4955 4956 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4957 uint64_t Address, const void *Decoder) { 4958 DecodeStatus S = MCDisassembler::Success; 4959 4960 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4961 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4962 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4963 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4964 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4965 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4966 4967 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4968 4969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4970 return MCDisassembler::Fail; 4971 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4972 return MCDisassembler::Fail; 4973 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4974 return MCDisassembler::Fail; 4975 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4976 return MCDisassembler::Fail; 4977 4978 return S; 4979 } 4980 4981 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4982 uint64_t Address, const void *Decoder) { 4983 DecodeStatus S = MCDisassembler::Success; 4984 4985 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4986 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4987 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4988 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4989 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4990 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4991 4992 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4993 4994 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4995 return MCDisassembler::Fail; 4996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4997 return MCDisassembler::Fail; 4998 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4999 return MCDisassembler::Fail; 5000 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5001 return MCDisassembler::Fail; 5002 5003 return S; 5004 } 5005 5006 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 5007 uint64_t Address, const void *Decoder) { 5008 DecodeStatus S = MCDisassembler::Success; 5009 5010 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5011 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5012 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5013 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5014 unsigned size = fieldFromInstruction(Insn, 10, 2); 5015 5016 unsigned align = 0; 5017 unsigned index = 0; 5018 switch (size) { 5019 default: 5020 return MCDisassembler::Fail; 5021 case 0: 5022 if (fieldFromInstruction(Insn, 4, 1)) 5023 return MCDisassembler::Fail; // UNDEFINED 5024 index = fieldFromInstruction(Insn, 5, 3); 5025 break; 5026 case 1: 5027 if (fieldFromInstruction(Insn, 5, 1)) 5028 return MCDisassembler::Fail; // UNDEFINED 5029 index = fieldFromInstruction(Insn, 6, 2); 5030 if (fieldFromInstruction(Insn, 4, 1)) 5031 align = 2; 5032 break; 5033 case 2: 5034 if (fieldFromInstruction(Insn, 6, 1)) 5035 return MCDisassembler::Fail; // UNDEFINED 5036 index = fieldFromInstruction(Insn, 7, 1); 5037 5038 switch (fieldFromInstruction(Insn, 4, 2)) { 5039 case 0 : 5040 align = 0; break; 5041 case 3: 5042 align = 4; break; 5043 default: 5044 return MCDisassembler::Fail; 5045 } 5046 break; 5047 } 5048 5049 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5050 return MCDisassembler::Fail; 5051 if (Rm != 0xF) { // Writeback 5052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5053 return MCDisassembler::Fail; 5054 } 5055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5056 return MCDisassembler::Fail; 5057 Inst.addOperand(MCOperand::createImm(align)); 5058 if (Rm != 0xF) { 5059 if (Rm != 0xD) { 5060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5061 return MCDisassembler::Fail; 5062 } else 5063 Inst.addOperand(MCOperand::createReg(0)); 5064 } 5065 5066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5067 return MCDisassembler::Fail; 5068 Inst.addOperand(MCOperand::createImm(index)); 5069 5070 return S; 5071 } 5072 5073 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 5074 uint64_t Address, const void *Decoder) { 5075 DecodeStatus S = MCDisassembler::Success; 5076 5077 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5078 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5079 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5080 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5081 unsigned size = fieldFromInstruction(Insn, 10, 2); 5082 5083 unsigned align = 0; 5084 unsigned index = 0; 5085 switch (size) { 5086 default: 5087 return MCDisassembler::Fail; 5088 case 0: 5089 if (fieldFromInstruction(Insn, 4, 1)) 5090 return MCDisassembler::Fail; // UNDEFINED 5091 index = fieldFromInstruction(Insn, 5, 3); 5092 break; 5093 case 1: 5094 if (fieldFromInstruction(Insn, 5, 1)) 5095 return MCDisassembler::Fail; // UNDEFINED 5096 index = fieldFromInstruction(Insn, 6, 2); 5097 if (fieldFromInstruction(Insn, 4, 1)) 5098 align = 2; 5099 break; 5100 case 2: 5101 if (fieldFromInstruction(Insn, 6, 1)) 5102 return MCDisassembler::Fail; // UNDEFINED 5103 index = fieldFromInstruction(Insn, 7, 1); 5104 5105 switch (fieldFromInstruction(Insn, 4, 2)) { 5106 case 0: 5107 align = 0; break; 5108 case 3: 5109 align = 4; break; 5110 default: 5111 return MCDisassembler::Fail; 5112 } 5113 break; 5114 } 5115 5116 if (Rm != 0xF) { // Writeback 5117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5118 return MCDisassembler::Fail; 5119 } 5120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5121 return MCDisassembler::Fail; 5122 Inst.addOperand(MCOperand::createImm(align)); 5123 if (Rm != 0xF) { 5124 if (Rm != 0xD) { 5125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5126 return MCDisassembler::Fail; 5127 } else 5128 Inst.addOperand(MCOperand::createReg(0)); 5129 } 5130 5131 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5132 return MCDisassembler::Fail; 5133 Inst.addOperand(MCOperand::createImm(index)); 5134 5135 return S; 5136 } 5137 5138 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5139 uint64_t Address, const void *Decoder) { 5140 DecodeStatus S = MCDisassembler::Success; 5141 5142 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5143 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5144 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5145 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5146 unsigned size = fieldFromInstruction(Insn, 10, 2); 5147 5148 unsigned align = 0; 5149 unsigned index = 0; 5150 unsigned inc = 1; 5151 switch (size) { 5152 default: 5153 return MCDisassembler::Fail; 5154 case 0: 5155 index = fieldFromInstruction(Insn, 5, 3); 5156 if (fieldFromInstruction(Insn, 4, 1)) 5157 align = 2; 5158 break; 5159 case 1: 5160 index = fieldFromInstruction(Insn, 6, 2); 5161 if (fieldFromInstruction(Insn, 4, 1)) 5162 align = 4; 5163 if (fieldFromInstruction(Insn, 5, 1)) 5164 inc = 2; 5165 break; 5166 case 2: 5167 if (fieldFromInstruction(Insn, 5, 1)) 5168 return MCDisassembler::Fail; // UNDEFINED 5169 index = fieldFromInstruction(Insn, 7, 1); 5170 if (fieldFromInstruction(Insn, 4, 1) != 0) 5171 align = 8; 5172 if (fieldFromInstruction(Insn, 6, 1)) 5173 inc = 2; 5174 break; 5175 } 5176 5177 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5178 return MCDisassembler::Fail; 5179 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5180 return MCDisassembler::Fail; 5181 if (Rm != 0xF) { // Writeback 5182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5183 return MCDisassembler::Fail; 5184 } 5185 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5186 return MCDisassembler::Fail; 5187 Inst.addOperand(MCOperand::createImm(align)); 5188 if (Rm != 0xF) { 5189 if (Rm != 0xD) { 5190 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5191 return MCDisassembler::Fail; 5192 } else 5193 Inst.addOperand(MCOperand::createReg(0)); 5194 } 5195 5196 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5197 return MCDisassembler::Fail; 5198 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5199 return MCDisassembler::Fail; 5200 Inst.addOperand(MCOperand::createImm(index)); 5201 5202 return S; 5203 } 5204 5205 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5206 uint64_t Address, const void *Decoder) { 5207 DecodeStatus S = MCDisassembler::Success; 5208 5209 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5210 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5211 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5212 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5213 unsigned size = fieldFromInstruction(Insn, 10, 2); 5214 5215 unsigned align = 0; 5216 unsigned index = 0; 5217 unsigned inc = 1; 5218 switch (size) { 5219 default: 5220 return MCDisassembler::Fail; 5221 case 0: 5222 index = fieldFromInstruction(Insn, 5, 3); 5223 if (fieldFromInstruction(Insn, 4, 1)) 5224 align = 2; 5225 break; 5226 case 1: 5227 index = fieldFromInstruction(Insn, 6, 2); 5228 if (fieldFromInstruction(Insn, 4, 1)) 5229 align = 4; 5230 if (fieldFromInstruction(Insn, 5, 1)) 5231 inc = 2; 5232 break; 5233 case 2: 5234 if (fieldFromInstruction(Insn, 5, 1)) 5235 return MCDisassembler::Fail; // UNDEFINED 5236 index = fieldFromInstruction(Insn, 7, 1); 5237 if (fieldFromInstruction(Insn, 4, 1) != 0) 5238 align = 8; 5239 if (fieldFromInstruction(Insn, 6, 1)) 5240 inc = 2; 5241 break; 5242 } 5243 5244 if (Rm != 0xF) { // Writeback 5245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5246 return MCDisassembler::Fail; 5247 } 5248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5249 return MCDisassembler::Fail; 5250 Inst.addOperand(MCOperand::createImm(align)); 5251 if (Rm != 0xF) { 5252 if (Rm != 0xD) { 5253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5254 return MCDisassembler::Fail; 5255 } else 5256 Inst.addOperand(MCOperand::createReg(0)); 5257 } 5258 5259 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5260 return MCDisassembler::Fail; 5261 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5262 return MCDisassembler::Fail; 5263 Inst.addOperand(MCOperand::createImm(index)); 5264 5265 return S; 5266 } 5267 5268 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5269 uint64_t Address, const void *Decoder) { 5270 DecodeStatus S = MCDisassembler::Success; 5271 5272 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5273 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5274 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5275 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5276 unsigned size = fieldFromInstruction(Insn, 10, 2); 5277 5278 unsigned align = 0; 5279 unsigned index = 0; 5280 unsigned inc = 1; 5281 switch (size) { 5282 default: 5283 return MCDisassembler::Fail; 5284 case 0: 5285 if (fieldFromInstruction(Insn, 4, 1)) 5286 return MCDisassembler::Fail; // UNDEFINED 5287 index = fieldFromInstruction(Insn, 5, 3); 5288 break; 5289 case 1: 5290 if (fieldFromInstruction(Insn, 4, 1)) 5291 return MCDisassembler::Fail; // UNDEFINED 5292 index = fieldFromInstruction(Insn, 6, 2); 5293 if (fieldFromInstruction(Insn, 5, 1)) 5294 inc = 2; 5295 break; 5296 case 2: 5297 if (fieldFromInstruction(Insn, 4, 2)) 5298 return MCDisassembler::Fail; // UNDEFINED 5299 index = fieldFromInstruction(Insn, 7, 1); 5300 if (fieldFromInstruction(Insn, 6, 1)) 5301 inc = 2; 5302 break; 5303 } 5304 5305 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5306 return MCDisassembler::Fail; 5307 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5308 return MCDisassembler::Fail; 5309 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5310 return MCDisassembler::Fail; 5311 5312 if (Rm != 0xF) { // Writeback 5313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5314 return MCDisassembler::Fail; 5315 } 5316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5317 return MCDisassembler::Fail; 5318 Inst.addOperand(MCOperand::createImm(align)); 5319 if (Rm != 0xF) { 5320 if (Rm != 0xD) { 5321 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5322 return MCDisassembler::Fail; 5323 } else 5324 Inst.addOperand(MCOperand::createReg(0)); 5325 } 5326 5327 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5328 return MCDisassembler::Fail; 5329 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5330 return MCDisassembler::Fail; 5331 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5332 return MCDisassembler::Fail; 5333 Inst.addOperand(MCOperand::createImm(index)); 5334 5335 return S; 5336 } 5337 5338 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5339 uint64_t Address, const void *Decoder) { 5340 DecodeStatus S = MCDisassembler::Success; 5341 5342 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5343 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5344 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5345 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5346 unsigned size = fieldFromInstruction(Insn, 10, 2); 5347 5348 unsigned align = 0; 5349 unsigned index = 0; 5350 unsigned inc = 1; 5351 switch (size) { 5352 default: 5353 return MCDisassembler::Fail; 5354 case 0: 5355 if (fieldFromInstruction(Insn, 4, 1)) 5356 return MCDisassembler::Fail; // UNDEFINED 5357 index = fieldFromInstruction(Insn, 5, 3); 5358 break; 5359 case 1: 5360 if (fieldFromInstruction(Insn, 4, 1)) 5361 return MCDisassembler::Fail; // UNDEFINED 5362 index = fieldFromInstruction(Insn, 6, 2); 5363 if (fieldFromInstruction(Insn, 5, 1)) 5364 inc = 2; 5365 break; 5366 case 2: 5367 if (fieldFromInstruction(Insn, 4, 2)) 5368 return MCDisassembler::Fail; // UNDEFINED 5369 index = fieldFromInstruction(Insn, 7, 1); 5370 if (fieldFromInstruction(Insn, 6, 1)) 5371 inc = 2; 5372 break; 5373 } 5374 5375 if (Rm != 0xF) { // Writeback 5376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5377 return MCDisassembler::Fail; 5378 } 5379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5380 return MCDisassembler::Fail; 5381 Inst.addOperand(MCOperand::createImm(align)); 5382 if (Rm != 0xF) { 5383 if (Rm != 0xD) { 5384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5385 return MCDisassembler::Fail; 5386 } else 5387 Inst.addOperand(MCOperand::createReg(0)); 5388 } 5389 5390 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5391 return MCDisassembler::Fail; 5392 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5393 return MCDisassembler::Fail; 5394 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5395 return MCDisassembler::Fail; 5396 Inst.addOperand(MCOperand::createImm(index)); 5397 5398 return S; 5399 } 5400 5401 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5402 uint64_t Address, const void *Decoder) { 5403 DecodeStatus S = MCDisassembler::Success; 5404 5405 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5406 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5407 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5408 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5409 unsigned size = fieldFromInstruction(Insn, 10, 2); 5410 5411 unsigned align = 0; 5412 unsigned index = 0; 5413 unsigned inc = 1; 5414 switch (size) { 5415 default: 5416 return MCDisassembler::Fail; 5417 case 0: 5418 if (fieldFromInstruction(Insn, 4, 1)) 5419 align = 4; 5420 index = fieldFromInstruction(Insn, 5, 3); 5421 break; 5422 case 1: 5423 if (fieldFromInstruction(Insn, 4, 1)) 5424 align = 8; 5425 index = fieldFromInstruction(Insn, 6, 2); 5426 if (fieldFromInstruction(Insn, 5, 1)) 5427 inc = 2; 5428 break; 5429 case 2: 5430 switch (fieldFromInstruction(Insn, 4, 2)) { 5431 case 0: 5432 align = 0; break; 5433 case 3: 5434 return MCDisassembler::Fail; 5435 default: 5436 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5437 } 5438 5439 index = fieldFromInstruction(Insn, 7, 1); 5440 if (fieldFromInstruction(Insn, 6, 1)) 5441 inc = 2; 5442 break; 5443 } 5444 5445 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5446 return MCDisassembler::Fail; 5447 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5448 return MCDisassembler::Fail; 5449 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5450 return MCDisassembler::Fail; 5451 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5452 return MCDisassembler::Fail; 5453 5454 if (Rm != 0xF) { // Writeback 5455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5456 return MCDisassembler::Fail; 5457 } 5458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5459 return MCDisassembler::Fail; 5460 Inst.addOperand(MCOperand::createImm(align)); 5461 if (Rm != 0xF) { 5462 if (Rm != 0xD) { 5463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5464 return MCDisassembler::Fail; 5465 } else 5466 Inst.addOperand(MCOperand::createReg(0)); 5467 } 5468 5469 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5470 return MCDisassembler::Fail; 5471 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5472 return MCDisassembler::Fail; 5473 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5474 return MCDisassembler::Fail; 5475 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5476 return MCDisassembler::Fail; 5477 Inst.addOperand(MCOperand::createImm(index)); 5478 5479 return S; 5480 } 5481 5482 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5483 uint64_t Address, const void *Decoder) { 5484 DecodeStatus S = MCDisassembler::Success; 5485 5486 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5487 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5488 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5489 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5490 unsigned size = fieldFromInstruction(Insn, 10, 2); 5491 5492 unsigned align = 0; 5493 unsigned index = 0; 5494 unsigned inc = 1; 5495 switch (size) { 5496 default: 5497 return MCDisassembler::Fail; 5498 case 0: 5499 if (fieldFromInstruction(Insn, 4, 1)) 5500 align = 4; 5501 index = fieldFromInstruction(Insn, 5, 3); 5502 break; 5503 case 1: 5504 if (fieldFromInstruction(Insn, 4, 1)) 5505 align = 8; 5506 index = fieldFromInstruction(Insn, 6, 2); 5507 if (fieldFromInstruction(Insn, 5, 1)) 5508 inc = 2; 5509 break; 5510 case 2: 5511 switch (fieldFromInstruction(Insn, 4, 2)) { 5512 case 0: 5513 align = 0; break; 5514 case 3: 5515 return MCDisassembler::Fail; 5516 default: 5517 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5518 } 5519 5520 index = fieldFromInstruction(Insn, 7, 1); 5521 if (fieldFromInstruction(Insn, 6, 1)) 5522 inc = 2; 5523 break; 5524 } 5525 5526 if (Rm != 0xF) { // Writeback 5527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5528 return MCDisassembler::Fail; 5529 } 5530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5531 return MCDisassembler::Fail; 5532 Inst.addOperand(MCOperand::createImm(align)); 5533 if (Rm != 0xF) { 5534 if (Rm != 0xD) { 5535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5536 return MCDisassembler::Fail; 5537 } else 5538 Inst.addOperand(MCOperand::createReg(0)); 5539 } 5540 5541 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5542 return MCDisassembler::Fail; 5543 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5544 return MCDisassembler::Fail; 5545 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5546 return MCDisassembler::Fail; 5547 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5548 return MCDisassembler::Fail; 5549 Inst.addOperand(MCOperand::createImm(index)); 5550 5551 return S; 5552 } 5553 5554 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5555 uint64_t Address, const void *Decoder) { 5556 DecodeStatus S = MCDisassembler::Success; 5557 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5558 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5559 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5560 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5561 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5562 5563 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5564 S = MCDisassembler::SoftFail; 5565 5566 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5567 return MCDisassembler::Fail; 5568 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5569 return MCDisassembler::Fail; 5570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5571 return MCDisassembler::Fail; 5572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5573 return MCDisassembler::Fail; 5574 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5575 return MCDisassembler::Fail; 5576 5577 return S; 5578 } 5579 5580 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5581 uint64_t Address, const void *Decoder) { 5582 DecodeStatus S = MCDisassembler::Success; 5583 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5584 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5585 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5586 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5587 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5588 5589 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5590 S = MCDisassembler::SoftFail; 5591 5592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5593 return MCDisassembler::Fail; 5594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5595 return MCDisassembler::Fail; 5596 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5597 return MCDisassembler::Fail; 5598 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5599 return MCDisassembler::Fail; 5600 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5601 return MCDisassembler::Fail; 5602 5603 return S; 5604 } 5605 5606 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5607 uint64_t Address, const void *Decoder) { 5608 DecodeStatus S = MCDisassembler::Success; 5609 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5610 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5611 5612 if (pred == 0xF) { 5613 pred = 0xE; 5614 S = MCDisassembler::SoftFail; 5615 } 5616 5617 if (mask == 0x0) 5618 return MCDisassembler::Fail; 5619 5620 // IT masks are encoded as a sequence of replacement low-order bits 5621 // for the condition code. So if the low bit of the starting 5622 // condition code is 1, then we have to flip all the bits above the 5623 // terminating bit (which is the lowest 1 bit). 5624 if (pred & 1) { 5625 unsigned LowBit = mask & -mask; 5626 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5627 mask ^= BitsAboveLowBit; 5628 } 5629 5630 Inst.addOperand(MCOperand::createImm(pred)); 5631 Inst.addOperand(MCOperand::createImm(mask)); 5632 return S; 5633 } 5634 5635 static DecodeStatus 5636 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5637 uint64_t Address, const void *Decoder) { 5638 DecodeStatus S = MCDisassembler::Success; 5639 5640 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5641 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5642 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5643 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5644 unsigned W = fieldFromInstruction(Insn, 21, 1); 5645 unsigned U = fieldFromInstruction(Insn, 23, 1); 5646 unsigned P = fieldFromInstruction(Insn, 24, 1); 5647 bool writeback = (W == 1) | (P == 0); 5648 5649 addr |= (U << 8) | (Rn << 9); 5650 5651 if (writeback && (Rn == Rt || Rn == Rt2)) 5652 Check(S, MCDisassembler::SoftFail); 5653 if (Rt == Rt2) 5654 Check(S, MCDisassembler::SoftFail); 5655 5656 // Rt 5657 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5658 return MCDisassembler::Fail; 5659 // Rt2 5660 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5661 return MCDisassembler::Fail; 5662 // Writeback operand 5663 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5664 return MCDisassembler::Fail; 5665 // addr 5666 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5667 return MCDisassembler::Fail; 5668 5669 return S; 5670 } 5671 5672 static DecodeStatus 5673 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5674 uint64_t Address, const void *Decoder) { 5675 DecodeStatus S = MCDisassembler::Success; 5676 5677 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5678 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5679 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5680 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5681 unsigned W = fieldFromInstruction(Insn, 21, 1); 5682 unsigned U = fieldFromInstruction(Insn, 23, 1); 5683 unsigned P = fieldFromInstruction(Insn, 24, 1); 5684 bool writeback = (W == 1) | (P == 0); 5685 5686 addr |= (U << 8) | (Rn << 9); 5687 5688 if (writeback && (Rn == Rt || Rn == Rt2)) 5689 Check(S, MCDisassembler::SoftFail); 5690 5691 // Writeback operand 5692 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5693 return MCDisassembler::Fail; 5694 // Rt 5695 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5696 return MCDisassembler::Fail; 5697 // Rt2 5698 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5699 return MCDisassembler::Fail; 5700 // addr 5701 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5702 return MCDisassembler::Fail; 5703 5704 return S; 5705 } 5706 5707 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5708 uint64_t Address, const void *Decoder) { 5709 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5710 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5711 if (sign1 != sign2) return MCDisassembler::Fail; 5712 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5713 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5714 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5715 5716 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5717 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5718 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5719 // If sign, then it is decreasing the address. 5720 if (sign1) { 5721 // Following ARMv7 Architecture Manual, when the offset 5722 // is zero, it is decoded as a subw, not as a adr.w 5723 if (!Val) { 5724 Inst.setOpcode(ARM::t2SUBri12); 5725 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5726 } else 5727 Val = -Val; 5728 } 5729 Inst.addOperand(MCOperand::createImm(Val)); 5730 return S; 5731 } 5732 5733 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5734 uint64_t Address, 5735 const void *Decoder) { 5736 DecodeStatus S = MCDisassembler::Success; 5737 5738 // Shift of "asr #32" is not allowed in Thumb2 mode. 5739 if (Val == 0x20) S = MCDisassembler::Fail; 5740 Inst.addOperand(MCOperand::createImm(Val)); 5741 return S; 5742 } 5743 5744 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5745 uint64_t Address, const void *Decoder) { 5746 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5747 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5748 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5749 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5750 5751 if (pred == 0xF) 5752 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5753 5754 DecodeStatus S = MCDisassembler::Success; 5755 5756 if (Rt == Rn || Rn == Rt2) 5757 S = MCDisassembler::SoftFail; 5758 5759 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5760 return MCDisassembler::Fail; 5761 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5762 return MCDisassembler::Fail; 5763 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5764 return MCDisassembler::Fail; 5765 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5766 return MCDisassembler::Fail; 5767 5768 return S; 5769 } 5770 5771 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5772 uint64_t Address, const void *Decoder) { 5773 const FeatureBitset &featureBits = 5774 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5775 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5776 5777 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5778 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5779 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5780 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5781 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5782 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5783 unsigned op = fieldFromInstruction(Insn, 5, 1); 5784 5785 DecodeStatus S = MCDisassembler::Success; 5786 5787 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5788 if (!(imm & 0x38)) { 5789 if (cmode == 0xF) { 5790 if (op == 1) return MCDisassembler::Fail; 5791 Inst.setOpcode(ARM::VMOVv2f32); 5792 } 5793 if (hasFullFP16) { 5794 if (cmode == 0xE) { 5795 if (op == 1) { 5796 Inst.setOpcode(ARM::VMOVv1i64); 5797 } else { 5798 Inst.setOpcode(ARM::VMOVv8i8); 5799 } 5800 } 5801 if (cmode == 0xD) { 5802 if (op == 1) { 5803 Inst.setOpcode(ARM::VMVNv2i32); 5804 } else { 5805 Inst.setOpcode(ARM::VMOVv2i32); 5806 } 5807 } 5808 if (cmode == 0xC) { 5809 if (op == 1) { 5810 Inst.setOpcode(ARM::VMVNv2i32); 5811 } else { 5812 Inst.setOpcode(ARM::VMOVv2i32); 5813 } 5814 } 5815 } 5816 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5817 } 5818 5819 if (!(imm & 0x20)) return MCDisassembler::Fail; 5820 5821 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5822 return MCDisassembler::Fail; 5823 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5824 return MCDisassembler::Fail; 5825 Inst.addOperand(MCOperand::createImm(64 - imm)); 5826 5827 return S; 5828 } 5829 5830 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5831 uint64_t Address, const void *Decoder) { 5832 const FeatureBitset &featureBits = 5833 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5834 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5835 5836 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5837 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5838 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5839 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5840 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5841 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5842 unsigned op = fieldFromInstruction(Insn, 5, 1); 5843 5844 DecodeStatus S = MCDisassembler::Success; 5845 5846 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5847 if (!(imm & 0x38)) { 5848 if (cmode == 0xF) { 5849 if (op == 1) return MCDisassembler::Fail; 5850 Inst.setOpcode(ARM::VMOVv4f32); 5851 } 5852 if (hasFullFP16) { 5853 if (cmode == 0xE) { 5854 if (op == 1) { 5855 Inst.setOpcode(ARM::VMOVv2i64); 5856 } else { 5857 Inst.setOpcode(ARM::VMOVv16i8); 5858 } 5859 } 5860 if (cmode == 0xD) { 5861 if (op == 1) { 5862 Inst.setOpcode(ARM::VMVNv4i32); 5863 } else { 5864 Inst.setOpcode(ARM::VMOVv4i32); 5865 } 5866 } 5867 if (cmode == 0xC) { 5868 if (op == 1) { 5869 Inst.setOpcode(ARM::VMVNv4i32); 5870 } else { 5871 Inst.setOpcode(ARM::VMOVv4i32); 5872 } 5873 } 5874 } 5875 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5876 } 5877 5878 if (!(imm & 0x20)) return MCDisassembler::Fail; 5879 5880 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5881 return MCDisassembler::Fail; 5882 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5883 return MCDisassembler::Fail; 5884 Inst.addOperand(MCOperand::createImm(64 - imm)); 5885 5886 return S; 5887 } 5888 5889 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5890 unsigned Insn, 5891 uint64_t Address, 5892 const void *Decoder) { 5893 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5894 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5895 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5896 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5897 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5898 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5899 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5900 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5901 5902 DecodeStatus S = MCDisassembler::Success; 5903 5904 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5905 5906 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5907 return MCDisassembler::Fail; 5908 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5909 return MCDisassembler::Fail; 5910 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5911 return MCDisassembler::Fail; 5912 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5913 return MCDisassembler::Fail; 5914 // The lane index does not have any bits in the encoding, because it can only 5915 // be 0. 5916 Inst.addOperand(MCOperand::createImm(0)); 5917 Inst.addOperand(MCOperand::createImm(rotate)); 5918 5919 return S; 5920 } 5921 5922 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5923 uint64_t Address, const void *Decoder) { 5924 DecodeStatus S = MCDisassembler::Success; 5925 5926 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5927 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5928 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5929 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5930 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5931 5932 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5933 S = MCDisassembler::SoftFail; 5934 5935 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5936 return MCDisassembler::Fail; 5937 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5938 return MCDisassembler::Fail; 5939 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5940 return MCDisassembler::Fail; 5941 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5942 return MCDisassembler::Fail; 5943 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5944 return MCDisassembler::Fail; 5945 5946 return S; 5947 } 5948 5949 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5950 uint64_t Address, const void *Decoder) { 5951 DecodeStatus S = MCDisassembler::Success; 5952 5953 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5954 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5955 unsigned cop = fieldFromInstruction(Val, 8, 4); 5956 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5957 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5958 5959 if ((cop & ~0x1) == 0xa) 5960 return MCDisassembler::Fail; 5961 5962 if (Rt == Rt2) 5963 S = MCDisassembler::SoftFail; 5964 5965 // We have to check if the instruction is MRRC2 5966 // or MCRR2 when constructing the operands for 5967 // Inst. Reason is because MRRC2 stores to two 5968 // registers so it's tablegen desc has has two 5969 // outputs whereas MCRR doesn't store to any 5970 // registers so all of it's operands are listed 5971 // as inputs, therefore the operand order for 5972 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5973 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5974 5975 if (Inst.getOpcode() == ARM::MRRC2) { 5976 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5977 return MCDisassembler::Fail; 5978 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5979 return MCDisassembler::Fail; 5980 } 5981 Inst.addOperand(MCOperand::createImm(cop)); 5982 Inst.addOperand(MCOperand::createImm(opc1)); 5983 if (Inst.getOpcode() == ARM::MCRR2) { 5984 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5985 return MCDisassembler::Fail; 5986 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5987 return MCDisassembler::Fail; 5988 } 5989 Inst.addOperand(MCOperand::createImm(CRm)); 5990 5991 return S; 5992 } 5993 5994 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5995 uint64_t Address, 5996 const void *Decoder) { 5997 const FeatureBitset &featureBits = 5998 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5999 DecodeStatus S = MCDisassembler::Success; 6000 6001 // Add explicit operand for the destination sysreg, for cases where 6002 // we have to model it for code generation purposes. 6003 switch (Inst.getOpcode()) { 6004 case ARM::VMSR_FPSCR_NZCVQC: 6005 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6006 break; 6007 case ARM::VMSR_P0: 6008 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6009 break; 6010 } 6011 6012 if (Inst.getOpcode() != ARM::FMSTAT) { 6013 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6014 6015 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 6016 if (Rt == 13 || Rt == 15) 6017 S = MCDisassembler::SoftFail; 6018 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 6019 } else 6020 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 6021 } 6022 6023 // Add explicit operand for the source sysreg, similarly to above. 6024 switch (Inst.getOpcode()) { 6025 case ARM::VMRS_FPSCR_NZCVQC: 6026 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6027 break; 6028 case ARM::VMRS_P0: 6029 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6030 break; 6031 } 6032 6033 if (featureBits[ARM::ModeThumb]) { 6034 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6035 Inst.addOperand(MCOperand::createReg(0)); 6036 } else { 6037 unsigned pred = fieldFromInstruction(Val, 28, 4); 6038 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6039 return MCDisassembler::Fail; 6040 } 6041 6042 return S; 6043 } 6044 6045 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 6046 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 6047 uint64_t Address, 6048 const void *Decoder) { 6049 DecodeStatus S = MCDisassembler::Success; 6050 if (Val == 0 && !zeroPermitted) 6051 S = MCDisassembler::Fail; 6052 6053 uint64_t DecVal; 6054 if (isSigned) 6055 DecVal = SignExtend32<size + 1>(Val << 1); 6056 else 6057 DecVal = (Val << 1); 6058 6059 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 6060 Decoder)) 6061 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 6062 return S; 6063 } 6064 6065 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 6066 uint64_t Address, 6067 const void *Decoder) { 6068 6069 uint64_t LocImm = Inst.getOperand(0).getImm(); 6070 Val = LocImm + (2 << Val); 6071 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 6072 Decoder)) 6073 Inst.addOperand(MCOperand::createImm(Val)); 6074 return MCDisassembler::Success; 6075 } 6076 6077 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 6078 uint64_t Address, 6079 const void *Decoder) { 6080 if (Val >= ARMCC::AL) // also exclude the non-condition NV 6081 return MCDisassembler::Fail; 6082 Inst.addOperand(MCOperand::createImm(Val)); 6083 return MCDisassembler::Success; 6084 } 6085 6086 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6087 const void *Decoder) { 6088 DecodeStatus S = MCDisassembler::Success; 6089 6090 if (Inst.getOpcode() == ARM::MVE_LCTP) 6091 return S; 6092 6093 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6094 fieldFromInstruction(Insn, 1, 10) << 1; 6095 switch (Inst.getOpcode()) { 6096 case ARM::t2LEUpdate: 6097 case ARM::MVE_LETP: 6098 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6099 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6100 LLVM_FALLTHROUGH; 6101 case ARM::t2LE: 6102 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6103 Inst, Imm, Address, Decoder))) 6104 return MCDisassembler::Fail; 6105 break; 6106 case ARM::t2WLS: 6107 case ARM::MVE_WLSTP_8: 6108 case ARM::MVE_WLSTP_16: 6109 case ARM::MVE_WLSTP_32: 6110 case ARM::MVE_WLSTP_64: 6111 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6112 if (!Check(S, 6113 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6114 Address, Decoder)) || 6115 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6116 Inst, Imm, Address, Decoder))) 6117 return MCDisassembler::Fail; 6118 break; 6119 case ARM::t2DLS: 6120 case ARM::MVE_DLSTP_8: 6121 case ARM::MVE_DLSTP_16: 6122 case ARM::MVE_DLSTP_32: 6123 case ARM::MVE_DLSTP_64: 6124 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6125 if (Rn == 0xF) { 6126 // Enforce all the rest of the instruction bits in LCTP, which 6127 // won't have been reliably checked based on LCTP's own tablegen 6128 // record, because we came to this decode by a roundabout route. 6129 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6130 if ((Insn & ~SBZMask) != CanonicalLCTP) 6131 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6132 if (Insn != CanonicalLCTP) 6133 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6134 6135 Inst.setOpcode(ARM::MVE_LCTP); 6136 } else { 6137 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6138 if (!Check(S, DecoderGPRRegisterClass(Inst, 6139 fieldFromInstruction(Insn, 16, 4), 6140 Address, Decoder))) 6141 return MCDisassembler::Fail; 6142 } 6143 break; 6144 } 6145 return S; 6146 } 6147 6148 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6149 uint64_t Address, 6150 const void *Decoder) { 6151 DecodeStatus S = MCDisassembler::Success; 6152 6153 if (Val == 0) 6154 Val = 32; 6155 6156 Inst.addOperand(MCOperand::createImm(Val)); 6157 6158 return S; 6159 } 6160 6161 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6162 uint64_t Address, const void *Decoder) { 6163 if ((RegNo) + 1 > 11) 6164 return MCDisassembler::Fail; 6165 6166 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6167 Inst.addOperand(MCOperand::createReg(Register)); 6168 return MCDisassembler::Success; 6169 } 6170 6171 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6172 uint64_t Address, const void *Decoder) { 6173 if ((RegNo) > 14) 6174 return MCDisassembler::Fail; 6175 6176 unsigned Register = GPRDecoderTable[(RegNo)]; 6177 Inst.addOperand(MCOperand::createReg(Register)); 6178 return MCDisassembler::Success; 6179 } 6180 6181 static DecodeStatus 6182 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6183 uint64_t Address, const void *Decoder) { 6184 if (RegNo == 15) { 6185 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6186 return MCDisassembler::Success; 6187 } 6188 6189 unsigned Register = GPRDecoderTable[RegNo]; 6190 Inst.addOperand(MCOperand::createReg(Register)); 6191 6192 if (RegNo == 13) 6193 return MCDisassembler::SoftFail; 6194 6195 return MCDisassembler::Success; 6196 } 6197 6198 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6199 const void *Decoder) { 6200 DecodeStatus S = MCDisassembler::Success; 6201 6202 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6203 Inst.addOperand(MCOperand::createReg(0)); 6204 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6205 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6206 (fieldFromInstruction(Insn, 12, 4) << 8) | 6207 (fieldFromInstruction(Insn, 22, 1) << 12); 6208 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6209 return MCDisassembler::Fail; 6210 } 6211 } else { 6212 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6213 (fieldFromInstruction(Insn, 22, 1) << 8) | 6214 (fieldFromInstruction(Insn, 12, 4) << 9); 6215 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6216 return MCDisassembler::Fail; 6217 } 6218 } 6219 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6220 6221 return S; 6222 } 6223 6224 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6225 uint64_t Address, 6226 const void *Decoder) { 6227 if (RegNo > 7) 6228 return MCDisassembler::Fail; 6229 6230 unsigned Register = QPRDecoderTable[RegNo]; 6231 Inst.addOperand(MCOperand::createReg(Register)); 6232 return MCDisassembler::Success; 6233 } 6234 6235 static const uint16_t QQPRDecoderTable[] = { 6236 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6237 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6238 }; 6239 6240 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6241 uint64_t Address, 6242 const void *Decoder) { 6243 if (RegNo > 6) 6244 return MCDisassembler::Fail; 6245 6246 unsigned Register = QQPRDecoderTable[RegNo]; 6247 Inst.addOperand(MCOperand::createReg(Register)); 6248 return MCDisassembler::Success; 6249 } 6250 6251 static const uint16_t QQQQPRDecoderTable[] = { 6252 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6253 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6254 }; 6255 6256 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6257 uint64_t Address, 6258 const void *Decoder) { 6259 if (RegNo > 4) 6260 return MCDisassembler::Fail; 6261 6262 unsigned Register = QQQQPRDecoderTable[RegNo]; 6263 Inst.addOperand(MCOperand::createReg(Register)); 6264 return MCDisassembler::Success; 6265 } 6266 6267 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6268 uint64_t Address, 6269 const void *Decoder) { 6270 DecodeStatus S = MCDisassembler::Success; 6271 6272 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6273 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6274 // 't' as 0 and finish with a 1. 6275 unsigned Imm = 0; 6276 // We always start with a 't'. 6277 unsigned CurBit = 0; 6278 for (int i = 3; i >= 0; --i) { 6279 // If the bit we are looking at is not the same as last one, invert the 6280 // CurBit, if it is the same leave it as is. 6281 CurBit ^= (Val >> i) & 1U; 6282 6283 // Encode the CurBit at the right place in the immediate. 6284 Imm |= (CurBit << i); 6285 6286 // If we are done, finish the encoding with a 1. 6287 if ((Val & ~(~0U << i)) == 0) { 6288 Imm |= 1U << i; 6289 break; 6290 } 6291 } 6292 6293 Inst.addOperand(MCOperand::createImm(Imm)); 6294 6295 return S; 6296 } 6297 6298 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6299 uint64_t Address, const void *Decoder) { 6300 // The vpred_r operand type includes an MQPR register field derived 6301 // from the encoding. But we don't actually want to add an operand 6302 // to the MCInst at this stage, because AddThumbPredicate will do it 6303 // later, and will infer the register number from the TIED_TO 6304 // constraint. So this is a deliberately empty decoder method that 6305 // will inhibit the auto-generated disassembly code from adding an 6306 // operand at all. 6307 return MCDisassembler::Success; 6308 } 6309 6310 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6311 unsigned Val, 6312 uint64_t Address, 6313 const void *Decoder) { 6314 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6315 return MCDisassembler::Success; 6316 } 6317 6318 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6319 unsigned Val, 6320 uint64_t Address, 6321 const void *Decoder) { 6322 unsigned Code; 6323 switch (Val & 0x3) { 6324 case 0: 6325 Code = ARMCC::GE; 6326 break; 6327 case 1: 6328 Code = ARMCC::LT; 6329 break; 6330 case 2: 6331 Code = ARMCC::GT; 6332 break; 6333 case 3: 6334 Code = ARMCC::LE; 6335 break; 6336 } 6337 Inst.addOperand(MCOperand::createImm(Code)); 6338 return MCDisassembler::Success; 6339 } 6340 6341 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6342 unsigned Val, 6343 uint64_t Address, 6344 const void *Decoder) { 6345 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6346 return MCDisassembler::Success; 6347 } 6348 6349 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6350 uint64_t Address, 6351 const void *Decoder) { 6352 unsigned Code; 6353 switch (Val) { 6354 default: 6355 return MCDisassembler::Fail; 6356 case 0: 6357 Code = ARMCC::EQ; 6358 break; 6359 case 1: 6360 Code = ARMCC::NE; 6361 break; 6362 case 4: 6363 Code = ARMCC::GE; 6364 break; 6365 case 5: 6366 Code = ARMCC::LT; 6367 break; 6368 case 6: 6369 Code = ARMCC::GT; 6370 break; 6371 case 7: 6372 Code = ARMCC::LE; 6373 break; 6374 } 6375 6376 Inst.addOperand(MCOperand::createImm(Code)); 6377 return MCDisassembler::Success; 6378 } 6379 6380 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6381 uint64_t Address, const void *Decoder) { 6382 DecodeStatus S = MCDisassembler::Success; 6383 6384 unsigned DecodedVal = 64 - Val; 6385 6386 switch (Inst.getOpcode()) { 6387 case ARM::MVE_VCVTf16s16_fix: 6388 case ARM::MVE_VCVTs16f16_fix: 6389 case ARM::MVE_VCVTf16u16_fix: 6390 case ARM::MVE_VCVTu16f16_fix: 6391 if (DecodedVal > 16) 6392 return MCDisassembler::Fail; 6393 break; 6394 case ARM::MVE_VCVTf32s32_fix: 6395 case ARM::MVE_VCVTs32f32_fix: 6396 case ARM::MVE_VCVTf32u32_fix: 6397 case ARM::MVE_VCVTu32f32_fix: 6398 if (DecodedVal > 32) 6399 return MCDisassembler::Fail; 6400 break; 6401 } 6402 6403 Inst.addOperand(MCOperand::createImm(64 - Val)); 6404 6405 return S; 6406 } 6407 6408 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6409 switch (Opcode) { 6410 case ARM::VSTR_P0_off: 6411 case ARM::VSTR_P0_pre: 6412 case ARM::VSTR_P0_post: 6413 case ARM::VLDR_P0_off: 6414 case ARM::VLDR_P0_pre: 6415 case ARM::VLDR_P0_post: 6416 return ARM::P0; 6417 default: 6418 return 0; 6419 } 6420 } 6421 6422 template<bool Writeback> 6423 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6424 uint64_t Address, 6425 const void *Decoder) { 6426 switch (Inst.getOpcode()) { 6427 case ARM::VSTR_FPSCR_pre: 6428 case ARM::VSTR_FPSCR_NZCVQC_pre: 6429 case ARM::VLDR_FPSCR_pre: 6430 case ARM::VLDR_FPSCR_NZCVQC_pre: 6431 case ARM::VSTR_FPSCR_off: 6432 case ARM::VSTR_FPSCR_NZCVQC_off: 6433 case ARM::VLDR_FPSCR_off: 6434 case ARM::VLDR_FPSCR_NZCVQC_off: 6435 case ARM::VSTR_FPSCR_post: 6436 case ARM::VSTR_FPSCR_NZCVQC_post: 6437 case ARM::VLDR_FPSCR_post: 6438 case ARM::VLDR_FPSCR_NZCVQC_post: 6439 const FeatureBitset &featureBits = 6440 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6441 6442 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6443 return MCDisassembler::Fail; 6444 } 6445 6446 DecodeStatus S = MCDisassembler::Success; 6447 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6448 Inst.addOperand(MCOperand::createReg(Sysreg)); 6449 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6450 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6451 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6452 6453 if (Writeback) { 6454 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6455 return MCDisassembler::Fail; 6456 } 6457 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6458 return MCDisassembler::Fail; 6459 6460 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6461 Inst.addOperand(MCOperand::createReg(0)); 6462 6463 return S; 6464 } 6465 6466 static inline DecodeStatus DecodeMVE_MEM_pre( 6467 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6468 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6469 DecodeStatus S = MCDisassembler::Success; 6470 6471 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6472 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6473 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6474 6475 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6476 return MCDisassembler::Fail; 6477 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6478 return MCDisassembler::Fail; 6479 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6480 return MCDisassembler::Fail; 6481 6482 return S; 6483 } 6484 6485 template <int shift> 6486 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6487 uint64_t Address, const void *Decoder) { 6488 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6489 fieldFromInstruction(Val, 16, 3), 6490 DecodetGPRRegisterClass, 6491 DecodeTAddrModeImm7<shift>); 6492 } 6493 6494 template <int shift> 6495 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6496 uint64_t Address, const void *Decoder) { 6497 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6498 fieldFromInstruction(Val, 16, 4), 6499 DecoderGPRRegisterClass, 6500 DecodeT2AddrModeImm7<shift,1>); 6501 } 6502 6503 template <int shift> 6504 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6505 uint64_t Address, const void *Decoder) { 6506 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6507 fieldFromInstruction(Val, 17, 3), 6508 DecodeMQPRRegisterClass, 6509 DecodeMveAddrModeQ<shift>); 6510 } 6511 6512 template<unsigned MinLog, unsigned MaxLog> 6513 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6514 uint64_t Address, 6515 const void *Decoder) { 6516 DecodeStatus S = MCDisassembler::Success; 6517 6518 if (Val < MinLog || Val > MaxLog) 6519 return MCDisassembler::Fail; 6520 6521 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6522 return S; 6523 } 6524 6525 template<unsigned start> 6526 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6527 uint64_t Address, 6528 const void *Decoder) { 6529 DecodeStatus S = MCDisassembler::Success; 6530 6531 Inst.addOperand(MCOperand::createImm(start + Val)); 6532 6533 return S; 6534 } 6535 6536 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6537 uint64_t Address, const void *Decoder) { 6538 DecodeStatus S = MCDisassembler::Success; 6539 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6540 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6541 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6542 fieldFromInstruction(Insn, 13, 3)); 6543 unsigned index = fieldFromInstruction(Insn, 4, 1); 6544 6545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6546 return MCDisassembler::Fail; 6547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6548 return MCDisassembler::Fail; 6549 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6550 return MCDisassembler::Fail; 6551 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6552 return MCDisassembler::Fail; 6553 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6554 return MCDisassembler::Fail; 6555 6556 return S; 6557 } 6558 6559 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6560 uint64_t Address, const void *Decoder) { 6561 DecodeStatus S = MCDisassembler::Success; 6562 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6563 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6564 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6565 fieldFromInstruction(Insn, 13, 3)); 6566 unsigned index = fieldFromInstruction(Insn, 4, 1); 6567 6568 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6569 return MCDisassembler::Fail; 6570 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6571 return MCDisassembler::Fail; 6572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6573 return MCDisassembler::Fail; 6574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6575 return MCDisassembler::Fail; 6576 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6577 return MCDisassembler::Fail; 6578 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6579 return MCDisassembler::Fail; 6580 6581 return S; 6582 } 6583 6584 static DecodeStatus DecodeMVEOverlappingLongShift( 6585 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6586 DecodeStatus S = MCDisassembler::Success; 6587 6588 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6589 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6590 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6591 6592 if (RdaHi == 14) { 6593 // This value of RdaHi (really indicating pc, because RdaHi has to 6594 // be an odd-numbered register, so the low bit will be set by the 6595 // decode function below) indicates that we must decode as SQRSHR 6596 // or UQRSHL, which both have a single Rda register field with all 6597 // four bits. 6598 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6599 6600 switch (Inst.getOpcode()) { 6601 case ARM::MVE_ASRLr: 6602 case ARM::MVE_SQRSHRL: 6603 Inst.setOpcode(ARM::MVE_SQRSHR); 6604 break; 6605 case ARM::MVE_LSLLr: 6606 case ARM::MVE_UQRSHLL: 6607 Inst.setOpcode(ARM::MVE_UQRSHL); 6608 break; 6609 default: 6610 llvm_unreachable("Unexpected starting opcode!"); 6611 } 6612 6613 // Rda as output parameter 6614 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6615 return MCDisassembler::Fail; 6616 6617 // Rda again as input parameter 6618 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6619 return MCDisassembler::Fail; 6620 6621 // Rm, the amount to shift by 6622 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6623 return MCDisassembler::Fail; 6624 6625 if (fieldFromInstruction (Insn, 6, 3) != 4) 6626 return MCDisassembler::SoftFail; 6627 6628 if (Rda == Rm) 6629 return MCDisassembler::SoftFail; 6630 6631 return S; 6632 } 6633 6634 // Otherwise, we decode as whichever opcode our caller has already 6635 // put into Inst. Those all look the same: 6636 6637 // RdaLo,RdaHi as output parameters 6638 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6639 return MCDisassembler::Fail; 6640 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6641 return MCDisassembler::Fail; 6642 6643 // RdaLo,RdaHi again as input parameters 6644 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6645 return MCDisassembler::Fail; 6646 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6647 return MCDisassembler::Fail; 6648 6649 // Rm, the amount to shift by 6650 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6651 return MCDisassembler::Fail; 6652 6653 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6654 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6655 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6656 // Saturate, the bit position for saturation 6657 Inst.addOperand(MCOperand::createImm(Saturate)); 6658 } 6659 6660 return S; 6661 } 6662 6663 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6664 const void *Decoder) { 6665 DecodeStatus S = MCDisassembler::Success; 6666 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6667 fieldFromInstruction(Insn, 13, 3)); 6668 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6669 fieldFromInstruction(Insn, 1, 3)); 6670 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6671 6672 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6673 return MCDisassembler::Fail; 6674 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6675 return MCDisassembler::Fail; 6676 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6677 return MCDisassembler::Fail; 6678 6679 return S; 6680 } 6681 6682 template<bool scalar, OperandDecoder predicate_decoder> 6683 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6684 const void *Decoder) { 6685 DecodeStatus S = MCDisassembler::Success; 6686 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6687 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6688 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6689 return MCDisassembler::Fail; 6690 6691 unsigned fc; 6692 6693 if (scalar) { 6694 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6695 fieldFromInstruction(Insn, 7, 1) | 6696 fieldFromInstruction(Insn, 5, 1) << 1; 6697 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6698 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6699 return MCDisassembler::Fail; 6700 } else { 6701 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6702 fieldFromInstruction(Insn, 7, 1) | 6703 fieldFromInstruction(Insn, 0, 1) << 1; 6704 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6705 fieldFromInstruction(Insn, 1, 3); 6706 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6707 return MCDisassembler::Fail; 6708 } 6709 6710 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6711 return MCDisassembler::Fail; 6712 6713 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6714 Inst.addOperand(MCOperand::createReg(0)); 6715 Inst.addOperand(MCOperand::createImm(0)); 6716 6717 return S; 6718 } 6719 6720 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6721 const void *Decoder) { 6722 DecodeStatus S = MCDisassembler::Success; 6723 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6724 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6725 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6726 return MCDisassembler::Fail; 6727 return S; 6728 } 6729 6730 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6731 const void *Decoder) { 6732 DecodeStatus S = MCDisassembler::Success; 6733 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6734 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6735 return S; 6736 } 6737 6738 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6739 uint64_t Address, const void *Decoder) { 6740 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6741 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6742 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6743 fieldFromInstruction(Insn, 12, 3) << 8 | 6744 fieldFromInstruction(Insn, 0, 8); 6745 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6746 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6747 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 6748 unsigned S = fieldFromInstruction(Insn, 20, 1); 6749 if (sign1 != sign2) 6750 return MCDisassembler::Fail; 6751 6752 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 6753 DecodeStatus DS = MCDisassembler::Success; 6754 if ((!Check(DS, 6755 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 6756 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 6757 return MCDisassembler::Fail; 6758 if (TypeT3) { 6759 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 6760 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 6761 } else { 6762 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 6763 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 6764 return MCDisassembler::Fail; 6765 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 6766 return MCDisassembler::Fail; 6767 } 6768 6769 return DS; 6770 } 6771