1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCDisassembler.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCFixedLenDisassembler.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/LEB128.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <vector> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "arm-disassembler" 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 // Handles the condition code status of instructions in IT blocks 35 class ITStatus 36 { 37 public: 38 // Returns the condition code for instruction in IT block 39 unsigned getITCC() { 40 unsigned CC = ARMCC::AL; 41 if (instrInITBlock()) 42 CC = ITStates.back(); 43 return CC; 44 } 45 46 // Advances the IT block state to the next T or E 47 void advanceITState() { 48 ITStates.pop_back(); 49 } 50 51 // Returns true if the current instruction is in an IT block 52 bool instrInITBlock() { 53 return !ITStates.empty(); 54 } 55 56 // Returns true if current instruction is the last instruction in an IT block 57 bool instrLastInITBlock() { 58 return ITStates.size() == 1; 59 } 60 61 // Called when decoding an IT instruction. Sets the IT state for the following 62 // instructions that for the IT block. Firstcond and Mask correspond to the 63 // fields in the IT instruction encoding. 64 void setITState(char Firstcond, char Mask) { 65 // (3 - the number of trailing zeros) is the number of then / else. 66 unsigned CondBit0 = Firstcond & 1; 67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 69 assert(NumTZ <= 3 && "Invalid IT mask!"); 70 // push condition codes onto the stack the correct order for the pops 71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 72 bool T = ((Mask >> Pos) & 1) == CondBit0; 73 if (T) 74 ITStates.push_back(CCBits); 75 else 76 ITStates.push_back(CCBits ^ 1); 77 } 78 ITStates.push_back(CCBits); 79 } 80 81 private: 82 std::vector<unsigned char> ITStates; 83 }; 84 } 85 86 namespace { 87 /// ARM disassembler for all ARM platforms. 88 class ARMDisassembler : public MCDisassembler { 89 public: 90 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 91 MCDisassembler(STI, Ctx) { 92 } 93 94 ~ARMDisassembler() override {} 95 96 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 97 ArrayRef<uint8_t> Bytes, uint64_t Address, 98 raw_ostream &VStream, 99 raw_ostream &CStream) const override; 100 }; 101 102 /// Thumb disassembler for all Thumb platforms. 103 class ThumbDisassembler : public MCDisassembler { 104 public: 105 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 106 MCDisassembler(STI, Ctx) { 107 } 108 109 ~ThumbDisassembler() override {} 110 111 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 112 ArrayRef<uint8_t> Bytes, uint64_t Address, 113 raw_ostream &VStream, 114 raw_ostream &CStream) const override; 115 116 private: 117 mutable ITStatus ITBlock; 118 DecodeStatus AddThumbPredicate(MCInst&) const; 119 void UpdateThumbVFPPredicate(MCInst&) const; 120 }; 121 } 122 123 static bool Check(DecodeStatus &Out, DecodeStatus In) { 124 switch (In) { 125 case MCDisassembler::Success: 126 // Out stays the same. 127 return true; 128 case MCDisassembler::SoftFail: 129 Out = In; 130 return true; 131 case MCDisassembler::Fail: 132 Out = In; 133 return false; 134 } 135 llvm_unreachable("Invalid DecodeStatus!"); 136 } 137 138 139 // Forward declare these because the autogenerated code will reference them. 140 // Definitions are further down. 141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, const void *Decoder); 143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 144 unsigned RegNo, uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 147 unsigned RegNo, uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 150 uint64_t Address, const void *Decoder); 151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 164 unsigned RegNo, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 172 unsigned RegNo, uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 191 unsigned Insn, 192 uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 201 uint64_t Address, const void *Decoder); 202 203 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 204 unsigned Insn, 205 uint64_t Adddress, 206 const void *Decoder); 207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 318 uint64_t Address, const void *Decoder); 319 320 321 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 342 uint64_t Address, const void* Decoder); 343 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void* Decoder); 345 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void* Decoder); 347 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void* Decoder); 349 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 392 uint64_t Address, const void *Decoder); 393 394 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 #include "ARMGenDisassemblerTables.inc" 399 400 static MCDisassembler *createARMDisassembler(const Target &T, 401 const MCSubtargetInfo &STI, 402 MCContext &Ctx) { 403 return new ARMDisassembler(STI, Ctx); 404 } 405 406 static MCDisassembler *createThumbDisassembler(const Target &T, 407 const MCSubtargetInfo &STI, 408 MCContext &Ctx) { 409 return new ThumbDisassembler(STI, Ctx); 410 } 411 412 // Post-decoding checks 413 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 414 uint64_t Address, raw_ostream &OS, 415 raw_ostream &CS, 416 uint32_t Insn, 417 DecodeStatus Result) 418 { 419 switch (MI.getOpcode()) { 420 case ARM::HVC: { 421 // HVC is undefined if condition = 0xf otherwise upredictable 422 // if condition != 0xe 423 uint32_t Cond = (Insn >> 28) & 0xF; 424 if (Cond == 0xF) 425 return MCDisassembler::Fail; 426 if (Cond != 0xE) 427 return MCDisassembler::SoftFail; 428 return Result; 429 } 430 default: return Result; 431 } 432 } 433 434 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 435 ArrayRef<uint8_t> Bytes, 436 uint64_t Address, raw_ostream &OS, 437 raw_ostream &CS) const { 438 CommentStream = &CS; 439 440 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 441 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 442 "mode!"); 443 444 // We want to read exactly 4 bytes of data. 445 if (Bytes.size() < 4) { 446 Size = 0; 447 return MCDisassembler::Fail; 448 } 449 450 // Encoded as a small-endian 32-bit word in the stream. 451 uint32_t Insn = 452 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 453 454 // Calling the auto-generated decoder function. 455 DecodeStatus Result = 456 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 457 if (Result != MCDisassembler::Fail) { 458 Size = 4; 459 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 460 } 461 462 // VFP and NEON instructions, similarly, are shared between ARM 463 // and Thumb modes. 464 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI); 465 if (Result != MCDisassembler::Fail) { 466 Size = 4; 467 return Result; 468 } 469 470 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI); 471 if (Result != MCDisassembler::Fail) { 472 Size = 4; 473 return Result; 474 } 475 476 Result = 477 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI); 478 if (Result != MCDisassembler::Fail) { 479 Size = 4; 480 // Add a fake predicate operand, because we share these instruction 481 // definitions with Thumb2 where these instructions are predicable. 482 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 483 return MCDisassembler::Fail; 484 return Result; 485 } 486 487 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address, 488 this, STI); 489 if (Result != MCDisassembler::Fail) { 490 Size = 4; 491 // Add a fake predicate operand, because we share these instruction 492 // definitions with Thumb2 where these instructions are predicable. 493 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 494 return MCDisassembler::Fail; 495 return Result; 496 } 497 498 Result = 499 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI); 500 if (Result != MCDisassembler::Fail) { 501 Size = 4; 502 // Add a fake predicate operand, because we share these instruction 503 // definitions with Thumb2 where these instructions are predicable. 504 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 505 return MCDisassembler::Fail; 506 return Result; 507 } 508 509 Result = 510 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI); 511 if (Result != MCDisassembler::Fail) { 512 Size = 4; 513 return Result; 514 } 515 516 Result = 517 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI); 518 if (Result != MCDisassembler::Fail) { 519 Size = 4; 520 return Result; 521 } 522 523 Size = 0; 524 return MCDisassembler::Fail; 525 } 526 527 namespace llvm { 528 extern const MCInstrDesc ARMInsts[]; 529 } 530 531 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 532 /// immediate Value in the MCInst. The immediate Value has had any PC 533 /// adjustment made by the caller. If the instruction is a branch instruction 534 /// then isBranch is true, else false. If the getOpInfo() function was set as 535 /// part of the setupForSymbolicDisassembly() call then that function is called 536 /// to get any symbolic information at the Address for this instruction. If 537 /// that returns non-zero then the symbolic information it returns is used to 538 /// create an MCExpr and that is added as an operand to the MCInst. If 539 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 540 /// Value is done and if a symbol is found an MCExpr is created with that, else 541 /// an MCExpr with Value is created. This function returns true if it adds an 542 /// operand to the MCInst and false otherwise. 543 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 544 bool isBranch, uint64_t InstSize, 545 MCInst &MI, const void *Decoder) { 546 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 547 // FIXME: Does it make sense for value to be negative? 548 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 549 /* Offset */ 0, InstSize); 550 } 551 552 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 553 /// referenced by a load instruction with the base register that is the Pc. 554 /// These can often be values in a literal pool near the Address of the 555 /// instruction. The Address of the instruction and its immediate Value are 556 /// used as a possible literal pool entry. The SymbolLookUp call back will 557 /// return the name of a symbol referenced by the literal pool's entry if 558 /// the referenced address is that of a symbol. Or it will return a pointer to 559 /// a literal 'C' string if the referenced address of the literal pool's entry 560 /// is an address into a section with 'C' string literals. 561 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 562 const void *Decoder) { 563 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 564 Dis->tryAddingPcLoadReferenceComment(Value, Address); 565 } 566 567 // Thumb1 instructions don't have explicit S bits. Rather, they 568 // implicitly set CPSR. Since it's not represented in the encoding, the 569 // auto-generated decoder won't inject the CPSR operand. We need to fix 570 // that as a post-pass. 571 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 572 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 573 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 574 MCInst::iterator I = MI.begin(); 575 for (unsigned i = 0; i < NumOps; ++i, ++I) { 576 if (I == MI.end()) break; 577 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 578 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 579 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 580 return; 581 } 582 } 583 584 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 585 } 586 587 // Most Thumb instructions don't have explicit predicates in the 588 // encoding, but rather get their predicates from IT context. We need 589 // to fix up the predicate operands using this context information as a 590 // post-pass. 591 MCDisassembler::DecodeStatus 592 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 593 MCDisassembler::DecodeStatus S = Success; 594 595 // A few instructions actually have predicates encoded in them. Don't 596 // try to overwrite it if we're seeing one of those. 597 switch (MI.getOpcode()) { 598 case ARM::tBcc: 599 case ARM::t2Bcc: 600 case ARM::tCBZ: 601 case ARM::tCBNZ: 602 case ARM::tCPS: 603 case ARM::t2CPS3p: 604 case ARM::t2CPS2p: 605 case ARM::t2CPS1p: 606 case ARM::tMOVSr: 607 case ARM::tSETEND: 608 // Some instructions (mostly conditional branches) are not 609 // allowed in IT blocks. 610 if (ITBlock.instrInITBlock()) 611 S = SoftFail; 612 else 613 return Success; 614 break; 615 case ARM::tB: 616 case ARM::t2B: 617 case ARM::t2TBB: 618 case ARM::t2TBH: 619 // Some instructions (mostly unconditional branches) can 620 // only appears at the end of, or outside of, an IT. 621 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 622 S = SoftFail; 623 break; 624 default: 625 break; 626 } 627 628 // If we're in an IT block, base the predicate on that. Otherwise, 629 // assume a predicate of AL. 630 unsigned CC; 631 CC = ITBlock.getITCC(); 632 if (CC == 0xF) 633 CC = ARMCC::AL; 634 if (ITBlock.instrInITBlock()) 635 ITBlock.advanceITState(); 636 637 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 638 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 639 MCInst::iterator I = MI.begin(); 640 for (unsigned i = 0; i < NumOps; ++i, ++I) { 641 if (I == MI.end()) break; 642 if (OpInfo[i].isPredicate()) { 643 I = MI.insert(I, MCOperand::createImm(CC)); 644 ++I; 645 if (CC == ARMCC::AL) 646 MI.insert(I, MCOperand::createReg(0)); 647 else 648 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 649 return S; 650 } 651 } 652 653 I = MI.insert(I, MCOperand::createImm(CC)); 654 ++I; 655 if (CC == ARMCC::AL) 656 MI.insert(I, MCOperand::createReg(0)); 657 else 658 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 659 660 return S; 661 } 662 663 // Thumb VFP instructions are a special case. Because we share their 664 // encodings between ARM and Thumb modes, and they are predicable in ARM 665 // mode, the auto-generated decoder will give them an (incorrect) 666 // predicate operand. We need to rewrite these operands based on the IT 667 // context as a post-pass. 668 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 669 unsigned CC; 670 CC = ITBlock.getITCC(); 671 if (ITBlock.instrInITBlock()) 672 ITBlock.advanceITState(); 673 674 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 675 MCInst::iterator I = MI.begin(); 676 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 677 for (unsigned i = 0; i < NumOps; ++i, ++I) { 678 if (OpInfo[i].isPredicate() ) { 679 I->setImm(CC); 680 ++I; 681 if (CC == ARMCC::AL) 682 I->setReg(0); 683 else 684 I->setReg(ARM::CPSR); 685 return; 686 } 687 } 688 } 689 690 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 691 ArrayRef<uint8_t> Bytes, 692 uint64_t Address, 693 raw_ostream &OS, 694 raw_ostream &CS) const { 695 CommentStream = &CS; 696 697 assert(STI.getFeatureBits()[ARM::ModeThumb] && 698 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 699 700 // We want to read exactly 2 bytes of data. 701 if (Bytes.size() < 2) { 702 Size = 0; 703 return MCDisassembler::Fail; 704 } 705 706 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 707 DecodeStatus Result = 708 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 709 if (Result != MCDisassembler::Fail) { 710 Size = 2; 711 Check(Result, AddThumbPredicate(MI)); 712 return Result; 713 } 714 715 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 716 STI); 717 if (Result) { 718 Size = 2; 719 bool InITBlock = ITBlock.instrInITBlock(); 720 Check(Result, AddThumbPredicate(MI)); 721 AddThumb1SBit(MI, InITBlock); 722 return Result; 723 } 724 725 Result = 726 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 727 if (Result != MCDisassembler::Fail) { 728 Size = 2; 729 730 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 731 // the Thumb predicate. 732 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 733 Result = MCDisassembler::SoftFail; 734 735 Check(Result, AddThumbPredicate(MI)); 736 737 // If we find an IT instruction, we need to parse its condition 738 // code and mask operands so that we can apply them correctly 739 // to the subsequent instructions. 740 if (MI.getOpcode() == ARM::t2IT) { 741 742 unsigned Firstcond = MI.getOperand(0).getImm(); 743 unsigned Mask = MI.getOperand(1).getImm(); 744 ITBlock.setITState(Firstcond, Mask); 745 } 746 747 return Result; 748 } 749 750 // We want to read exactly 4 bytes of data. 751 if (Bytes.size() < 4) { 752 Size = 0; 753 return MCDisassembler::Fail; 754 } 755 756 uint32_t Insn32 = 757 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 758 Result = 759 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 760 if (Result != MCDisassembler::Fail) { 761 Size = 4; 762 bool InITBlock = ITBlock.instrInITBlock(); 763 Check(Result, AddThumbPredicate(MI)); 764 AddThumb1SBit(MI, InITBlock); 765 return Result; 766 } 767 768 Result = 769 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 770 if (Result != MCDisassembler::Fail) { 771 Size = 4; 772 Check(Result, AddThumbPredicate(MI)); 773 return Result; 774 } 775 776 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 777 Result = 778 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 779 if (Result != MCDisassembler::Fail) { 780 Size = 4; 781 UpdateThumbVFPPredicate(MI); 782 return Result; 783 } 784 } 785 786 Result = 787 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 788 if (Result != MCDisassembler::Fail) { 789 Size = 4; 790 return Result; 791 } 792 793 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 794 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 795 STI); 796 if (Result != MCDisassembler::Fail) { 797 Size = 4; 798 Check(Result, AddThumbPredicate(MI)); 799 return Result; 800 } 801 } 802 803 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 804 uint32_t NEONLdStInsn = Insn32; 805 NEONLdStInsn &= 0xF0FFFFFF; 806 NEONLdStInsn |= 0x04000000; 807 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 808 Address, this, STI); 809 if (Result != MCDisassembler::Fail) { 810 Size = 4; 811 Check(Result, AddThumbPredicate(MI)); 812 return Result; 813 } 814 } 815 816 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 817 uint32_t NEONDataInsn = Insn32; 818 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 819 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 820 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 821 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 822 Address, this, STI); 823 if (Result != MCDisassembler::Fail) { 824 Size = 4; 825 Check(Result, AddThumbPredicate(MI)); 826 return Result; 827 } 828 829 uint32_t NEONCryptoInsn = Insn32; 830 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 831 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 832 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 833 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 834 Address, this, STI); 835 if (Result != MCDisassembler::Fail) { 836 Size = 4; 837 return Result; 838 } 839 840 uint32_t NEONv8Insn = Insn32; 841 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 842 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 843 this, STI); 844 if (Result != MCDisassembler::Fail) { 845 Size = 4; 846 return Result; 847 } 848 } 849 850 Size = 0; 851 return MCDisassembler::Fail; 852 } 853 854 855 extern "C" void LLVMInitializeARMDisassembler() { 856 TargetRegistry::RegisterMCDisassembler(TheARMLETarget, 857 createARMDisassembler); 858 TargetRegistry::RegisterMCDisassembler(TheARMBETarget, 859 createARMDisassembler); 860 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget, 861 createThumbDisassembler); 862 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget, 863 createThumbDisassembler); 864 } 865 866 static const uint16_t GPRDecoderTable[] = { 867 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 868 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 869 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 870 ARM::R12, ARM::SP, ARM::LR, ARM::PC 871 }; 872 873 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 874 uint64_t Address, const void *Decoder) { 875 if (RegNo > 15) 876 return MCDisassembler::Fail; 877 878 unsigned Register = GPRDecoderTable[RegNo]; 879 Inst.addOperand(MCOperand::createReg(Register)); 880 return MCDisassembler::Success; 881 } 882 883 static DecodeStatus 884 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 885 uint64_t Address, const void *Decoder) { 886 DecodeStatus S = MCDisassembler::Success; 887 888 if (RegNo == 15) 889 S = MCDisassembler::SoftFail; 890 891 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 892 893 return S; 894 } 895 896 static DecodeStatus 897 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 898 uint64_t Address, const void *Decoder) { 899 DecodeStatus S = MCDisassembler::Success; 900 901 if (RegNo == 15) 902 { 903 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 904 return MCDisassembler::Success; 905 } 906 907 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 908 return S; 909 } 910 911 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 912 uint64_t Address, const void *Decoder) { 913 if (RegNo > 7) 914 return MCDisassembler::Fail; 915 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 916 } 917 918 static const uint16_t GPRPairDecoderTable[] = { 919 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 920 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 921 }; 922 923 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 924 uint64_t Address, const void *Decoder) { 925 DecodeStatus S = MCDisassembler::Success; 926 927 if (RegNo > 13) 928 return MCDisassembler::Fail; 929 930 if ((RegNo & 1) || RegNo == 0xe) 931 S = MCDisassembler::SoftFail; 932 933 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 934 Inst.addOperand(MCOperand::createReg(RegisterPair)); 935 return S; 936 } 937 938 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 939 uint64_t Address, const void *Decoder) { 940 unsigned Register = 0; 941 switch (RegNo) { 942 case 0: 943 Register = ARM::R0; 944 break; 945 case 1: 946 Register = ARM::R1; 947 break; 948 case 2: 949 Register = ARM::R2; 950 break; 951 case 3: 952 Register = ARM::R3; 953 break; 954 case 9: 955 Register = ARM::R9; 956 break; 957 case 12: 958 Register = ARM::R12; 959 break; 960 default: 961 return MCDisassembler::Fail; 962 } 963 964 Inst.addOperand(MCOperand::createReg(Register)); 965 return MCDisassembler::Success; 966 } 967 968 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 969 uint64_t Address, const void *Decoder) { 970 DecodeStatus S = MCDisassembler::Success; 971 972 const FeatureBitset &featureBits = 973 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 974 975 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 976 S = MCDisassembler::SoftFail; 977 978 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 979 return S; 980 } 981 982 static const uint16_t SPRDecoderTable[] = { 983 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 984 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 985 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 986 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 987 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 988 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 989 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 990 ARM::S28, ARM::S29, ARM::S30, ARM::S31 991 }; 992 993 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 994 uint64_t Address, const void *Decoder) { 995 if (RegNo > 31) 996 return MCDisassembler::Fail; 997 998 unsigned Register = SPRDecoderTable[RegNo]; 999 Inst.addOperand(MCOperand::createReg(Register)); 1000 return MCDisassembler::Success; 1001 } 1002 1003 static const uint16_t DPRDecoderTable[] = { 1004 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1005 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1006 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1007 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1008 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1009 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1010 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1011 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1012 }; 1013 1014 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1015 uint64_t Address, const void *Decoder) { 1016 const FeatureBitset &featureBits = 1017 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1018 1019 bool hasD16 = featureBits[ARM::FeatureD16]; 1020 1021 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1022 return MCDisassembler::Fail; 1023 1024 unsigned Register = DPRDecoderTable[RegNo]; 1025 Inst.addOperand(MCOperand::createReg(Register)); 1026 return MCDisassembler::Success; 1027 } 1028 1029 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1030 uint64_t Address, const void *Decoder) { 1031 if (RegNo > 7) 1032 return MCDisassembler::Fail; 1033 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1034 } 1035 1036 static DecodeStatus 1037 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1038 uint64_t Address, const void *Decoder) { 1039 if (RegNo > 15) 1040 return MCDisassembler::Fail; 1041 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1042 } 1043 1044 static const uint16_t QPRDecoderTable[] = { 1045 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1046 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1047 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1048 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1049 }; 1050 1051 1052 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1053 uint64_t Address, const void *Decoder) { 1054 if (RegNo > 31 || (RegNo & 1) != 0) 1055 return MCDisassembler::Fail; 1056 RegNo >>= 1; 1057 1058 unsigned Register = QPRDecoderTable[RegNo]; 1059 Inst.addOperand(MCOperand::createReg(Register)); 1060 return MCDisassembler::Success; 1061 } 1062 1063 static const uint16_t DPairDecoderTable[] = { 1064 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1065 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1066 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1067 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1068 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1069 ARM::Q15 1070 }; 1071 1072 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1073 uint64_t Address, const void *Decoder) { 1074 if (RegNo > 30) 1075 return MCDisassembler::Fail; 1076 1077 unsigned Register = DPairDecoderTable[RegNo]; 1078 Inst.addOperand(MCOperand::createReg(Register)); 1079 return MCDisassembler::Success; 1080 } 1081 1082 static const uint16_t DPairSpacedDecoderTable[] = { 1083 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1084 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1085 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1086 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1087 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1088 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1089 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1090 ARM::D28_D30, ARM::D29_D31 1091 }; 1092 1093 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1094 unsigned RegNo, 1095 uint64_t Address, 1096 const void *Decoder) { 1097 if (RegNo > 29) 1098 return MCDisassembler::Fail; 1099 1100 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1101 Inst.addOperand(MCOperand::createReg(Register)); 1102 return MCDisassembler::Success; 1103 } 1104 1105 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1106 uint64_t Address, const void *Decoder) { 1107 if (Val == 0xF) return MCDisassembler::Fail; 1108 // AL predicate is not allowed on Thumb1 branches. 1109 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1110 return MCDisassembler::Fail; 1111 Inst.addOperand(MCOperand::createImm(Val)); 1112 if (Val == ARMCC::AL) { 1113 Inst.addOperand(MCOperand::createReg(0)); 1114 } else 1115 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1116 return MCDisassembler::Success; 1117 } 1118 1119 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1120 uint64_t Address, const void *Decoder) { 1121 if (Val) 1122 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1123 else 1124 Inst.addOperand(MCOperand::createReg(0)); 1125 return MCDisassembler::Success; 1126 } 1127 1128 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1129 uint64_t Address, const void *Decoder) { 1130 DecodeStatus S = MCDisassembler::Success; 1131 1132 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1133 unsigned type = fieldFromInstruction(Val, 5, 2); 1134 unsigned imm = fieldFromInstruction(Val, 7, 5); 1135 1136 // Register-immediate 1137 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1138 return MCDisassembler::Fail; 1139 1140 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1141 switch (type) { 1142 case 0: 1143 Shift = ARM_AM::lsl; 1144 break; 1145 case 1: 1146 Shift = ARM_AM::lsr; 1147 break; 1148 case 2: 1149 Shift = ARM_AM::asr; 1150 break; 1151 case 3: 1152 Shift = ARM_AM::ror; 1153 break; 1154 } 1155 1156 if (Shift == ARM_AM::ror && imm == 0) 1157 Shift = ARM_AM::rrx; 1158 1159 unsigned Op = Shift | (imm << 3); 1160 Inst.addOperand(MCOperand::createImm(Op)); 1161 1162 return S; 1163 } 1164 1165 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1166 uint64_t Address, const void *Decoder) { 1167 DecodeStatus S = MCDisassembler::Success; 1168 1169 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1170 unsigned type = fieldFromInstruction(Val, 5, 2); 1171 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1172 1173 // Register-register 1174 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1175 return MCDisassembler::Fail; 1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1177 return MCDisassembler::Fail; 1178 1179 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1180 switch (type) { 1181 case 0: 1182 Shift = ARM_AM::lsl; 1183 break; 1184 case 1: 1185 Shift = ARM_AM::lsr; 1186 break; 1187 case 2: 1188 Shift = ARM_AM::asr; 1189 break; 1190 case 3: 1191 Shift = ARM_AM::ror; 1192 break; 1193 } 1194 1195 Inst.addOperand(MCOperand::createImm(Shift)); 1196 1197 return S; 1198 } 1199 1200 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1201 uint64_t Address, const void *Decoder) { 1202 DecodeStatus S = MCDisassembler::Success; 1203 1204 bool NeedDisjointWriteback = false; 1205 unsigned WritebackReg = 0; 1206 switch (Inst.getOpcode()) { 1207 default: 1208 break; 1209 case ARM::LDMIA_UPD: 1210 case ARM::LDMDB_UPD: 1211 case ARM::LDMIB_UPD: 1212 case ARM::LDMDA_UPD: 1213 case ARM::t2LDMIA_UPD: 1214 case ARM::t2LDMDB_UPD: 1215 case ARM::t2STMIA_UPD: 1216 case ARM::t2STMDB_UPD: 1217 NeedDisjointWriteback = true; 1218 WritebackReg = Inst.getOperand(0).getReg(); 1219 break; 1220 } 1221 1222 // Empty register lists are not allowed. 1223 if (Val == 0) return MCDisassembler::Fail; 1224 for (unsigned i = 0; i < 16; ++i) { 1225 if (Val & (1 << i)) { 1226 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1227 return MCDisassembler::Fail; 1228 // Writeback not allowed if Rn is in the target list. 1229 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1230 Check(S, MCDisassembler::SoftFail); 1231 } 1232 } 1233 1234 return S; 1235 } 1236 1237 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1238 uint64_t Address, const void *Decoder) { 1239 DecodeStatus S = MCDisassembler::Success; 1240 1241 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1242 unsigned regs = fieldFromInstruction(Val, 0, 8); 1243 1244 // In case of unpredictable encoding, tweak the operands. 1245 if (regs == 0 || (Vd + regs) > 32) { 1246 regs = Vd + regs > 32 ? 32 - Vd : regs; 1247 regs = std::max( 1u, regs); 1248 S = MCDisassembler::SoftFail; 1249 } 1250 1251 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1252 return MCDisassembler::Fail; 1253 for (unsigned i = 0; i < (regs - 1); ++i) { 1254 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1255 return MCDisassembler::Fail; 1256 } 1257 1258 return S; 1259 } 1260 1261 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1262 uint64_t Address, const void *Decoder) { 1263 DecodeStatus S = MCDisassembler::Success; 1264 1265 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1266 unsigned regs = fieldFromInstruction(Val, 1, 7); 1267 1268 // In case of unpredictable encoding, tweak the operands. 1269 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1270 regs = Vd + regs > 32 ? 32 - Vd : regs; 1271 regs = std::max( 1u, regs); 1272 regs = std::min(16u, regs); 1273 S = MCDisassembler::SoftFail; 1274 } 1275 1276 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1277 return MCDisassembler::Fail; 1278 for (unsigned i = 0; i < (regs - 1); ++i) { 1279 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1280 return MCDisassembler::Fail; 1281 } 1282 1283 return S; 1284 } 1285 1286 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1287 uint64_t Address, const void *Decoder) { 1288 // This operand encodes a mask of contiguous zeros between a specified MSB 1289 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1290 // the mask of all bits LSB-and-lower, and then xor them to create 1291 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1292 // create the final mask. 1293 unsigned msb = fieldFromInstruction(Val, 5, 5); 1294 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1295 1296 DecodeStatus S = MCDisassembler::Success; 1297 if (lsb > msb) { 1298 Check(S, MCDisassembler::SoftFail); 1299 // The check above will cause the warning for the "potentially undefined 1300 // instruction encoding" but we can't build a bad MCOperand value here 1301 // with a lsb > msb or else printing the MCInst will cause a crash. 1302 lsb = msb; 1303 } 1304 1305 uint32_t msb_mask = 0xFFFFFFFF; 1306 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1307 uint32_t lsb_mask = (1U << lsb) - 1; 1308 1309 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1310 return S; 1311 } 1312 1313 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1314 uint64_t Address, const void *Decoder) { 1315 DecodeStatus S = MCDisassembler::Success; 1316 1317 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1318 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1319 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1320 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1321 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1322 unsigned U = fieldFromInstruction(Insn, 23, 1); 1323 1324 switch (Inst.getOpcode()) { 1325 case ARM::LDC_OFFSET: 1326 case ARM::LDC_PRE: 1327 case ARM::LDC_POST: 1328 case ARM::LDC_OPTION: 1329 case ARM::LDCL_OFFSET: 1330 case ARM::LDCL_PRE: 1331 case ARM::LDCL_POST: 1332 case ARM::LDCL_OPTION: 1333 case ARM::STC_OFFSET: 1334 case ARM::STC_PRE: 1335 case ARM::STC_POST: 1336 case ARM::STC_OPTION: 1337 case ARM::STCL_OFFSET: 1338 case ARM::STCL_PRE: 1339 case ARM::STCL_POST: 1340 case ARM::STCL_OPTION: 1341 case ARM::t2LDC_OFFSET: 1342 case ARM::t2LDC_PRE: 1343 case ARM::t2LDC_POST: 1344 case ARM::t2LDC_OPTION: 1345 case ARM::t2LDCL_OFFSET: 1346 case ARM::t2LDCL_PRE: 1347 case ARM::t2LDCL_POST: 1348 case ARM::t2LDCL_OPTION: 1349 case ARM::t2STC_OFFSET: 1350 case ARM::t2STC_PRE: 1351 case ARM::t2STC_POST: 1352 case ARM::t2STC_OPTION: 1353 case ARM::t2STCL_OFFSET: 1354 case ARM::t2STCL_PRE: 1355 case ARM::t2STCL_POST: 1356 case ARM::t2STCL_OPTION: 1357 if (coproc == 0xA || coproc == 0xB) 1358 return MCDisassembler::Fail; 1359 break; 1360 default: 1361 break; 1362 } 1363 1364 const FeatureBitset &featureBits = 1365 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1366 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1367 return MCDisassembler::Fail; 1368 1369 Inst.addOperand(MCOperand::createImm(coproc)); 1370 Inst.addOperand(MCOperand::createImm(CRd)); 1371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1372 return MCDisassembler::Fail; 1373 1374 switch (Inst.getOpcode()) { 1375 case ARM::t2LDC2_OFFSET: 1376 case ARM::t2LDC2L_OFFSET: 1377 case ARM::t2LDC2_PRE: 1378 case ARM::t2LDC2L_PRE: 1379 case ARM::t2STC2_OFFSET: 1380 case ARM::t2STC2L_OFFSET: 1381 case ARM::t2STC2_PRE: 1382 case ARM::t2STC2L_PRE: 1383 case ARM::LDC2_OFFSET: 1384 case ARM::LDC2L_OFFSET: 1385 case ARM::LDC2_PRE: 1386 case ARM::LDC2L_PRE: 1387 case ARM::STC2_OFFSET: 1388 case ARM::STC2L_OFFSET: 1389 case ARM::STC2_PRE: 1390 case ARM::STC2L_PRE: 1391 case ARM::t2LDC_OFFSET: 1392 case ARM::t2LDCL_OFFSET: 1393 case ARM::t2LDC_PRE: 1394 case ARM::t2LDCL_PRE: 1395 case ARM::t2STC_OFFSET: 1396 case ARM::t2STCL_OFFSET: 1397 case ARM::t2STC_PRE: 1398 case ARM::t2STCL_PRE: 1399 case ARM::LDC_OFFSET: 1400 case ARM::LDCL_OFFSET: 1401 case ARM::LDC_PRE: 1402 case ARM::LDCL_PRE: 1403 case ARM::STC_OFFSET: 1404 case ARM::STCL_OFFSET: 1405 case ARM::STC_PRE: 1406 case ARM::STCL_PRE: 1407 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1408 Inst.addOperand(MCOperand::createImm(imm)); 1409 break; 1410 case ARM::t2LDC2_POST: 1411 case ARM::t2LDC2L_POST: 1412 case ARM::t2STC2_POST: 1413 case ARM::t2STC2L_POST: 1414 case ARM::LDC2_POST: 1415 case ARM::LDC2L_POST: 1416 case ARM::STC2_POST: 1417 case ARM::STC2L_POST: 1418 case ARM::t2LDC_POST: 1419 case ARM::t2LDCL_POST: 1420 case ARM::t2STC_POST: 1421 case ARM::t2STCL_POST: 1422 case ARM::LDC_POST: 1423 case ARM::LDCL_POST: 1424 case ARM::STC_POST: 1425 case ARM::STCL_POST: 1426 imm |= U << 8; 1427 // fall through. 1428 default: 1429 // The 'option' variant doesn't encode 'U' in the immediate since 1430 // the immediate is unsigned [0,255]. 1431 Inst.addOperand(MCOperand::createImm(imm)); 1432 break; 1433 } 1434 1435 switch (Inst.getOpcode()) { 1436 case ARM::LDC_OFFSET: 1437 case ARM::LDC_PRE: 1438 case ARM::LDC_POST: 1439 case ARM::LDC_OPTION: 1440 case ARM::LDCL_OFFSET: 1441 case ARM::LDCL_PRE: 1442 case ARM::LDCL_POST: 1443 case ARM::LDCL_OPTION: 1444 case ARM::STC_OFFSET: 1445 case ARM::STC_PRE: 1446 case ARM::STC_POST: 1447 case ARM::STC_OPTION: 1448 case ARM::STCL_OFFSET: 1449 case ARM::STCL_PRE: 1450 case ARM::STCL_POST: 1451 case ARM::STCL_OPTION: 1452 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1453 return MCDisassembler::Fail; 1454 break; 1455 default: 1456 break; 1457 } 1458 1459 return S; 1460 } 1461 1462 static DecodeStatus 1463 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1464 uint64_t Address, const void *Decoder) { 1465 DecodeStatus S = MCDisassembler::Success; 1466 1467 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1468 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1469 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1470 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1471 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1472 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1473 unsigned P = fieldFromInstruction(Insn, 24, 1); 1474 unsigned W = fieldFromInstruction(Insn, 21, 1); 1475 1476 // On stores, the writeback operand precedes Rt. 1477 switch (Inst.getOpcode()) { 1478 case ARM::STR_POST_IMM: 1479 case ARM::STR_POST_REG: 1480 case ARM::STRB_POST_IMM: 1481 case ARM::STRB_POST_REG: 1482 case ARM::STRT_POST_REG: 1483 case ARM::STRT_POST_IMM: 1484 case ARM::STRBT_POST_REG: 1485 case ARM::STRBT_POST_IMM: 1486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1487 return MCDisassembler::Fail; 1488 break; 1489 default: 1490 break; 1491 } 1492 1493 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1494 return MCDisassembler::Fail; 1495 1496 // On loads, the writeback operand comes after Rt. 1497 switch (Inst.getOpcode()) { 1498 case ARM::LDR_POST_IMM: 1499 case ARM::LDR_POST_REG: 1500 case ARM::LDRB_POST_IMM: 1501 case ARM::LDRB_POST_REG: 1502 case ARM::LDRBT_POST_REG: 1503 case ARM::LDRBT_POST_IMM: 1504 case ARM::LDRT_POST_REG: 1505 case ARM::LDRT_POST_IMM: 1506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1507 return MCDisassembler::Fail; 1508 break; 1509 default: 1510 break; 1511 } 1512 1513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1514 return MCDisassembler::Fail; 1515 1516 ARM_AM::AddrOpc Op = ARM_AM::add; 1517 if (!fieldFromInstruction(Insn, 23, 1)) 1518 Op = ARM_AM::sub; 1519 1520 bool writeback = (P == 0) || (W == 1); 1521 unsigned idx_mode = 0; 1522 if (P && writeback) 1523 idx_mode = ARMII::IndexModePre; 1524 else if (!P && writeback) 1525 idx_mode = ARMII::IndexModePost; 1526 1527 if (writeback && (Rn == 15 || Rn == Rt)) 1528 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1529 1530 if (reg) { 1531 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1532 return MCDisassembler::Fail; 1533 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1534 switch( fieldFromInstruction(Insn, 5, 2)) { 1535 case 0: 1536 Opc = ARM_AM::lsl; 1537 break; 1538 case 1: 1539 Opc = ARM_AM::lsr; 1540 break; 1541 case 2: 1542 Opc = ARM_AM::asr; 1543 break; 1544 case 3: 1545 Opc = ARM_AM::ror; 1546 break; 1547 default: 1548 return MCDisassembler::Fail; 1549 } 1550 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1551 if (Opc == ARM_AM::ror && amt == 0) 1552 Opc = ARM_AM::rrx; 1553 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1554 1555 Inst.addOperand(MCOperand::createImm(imm)); 1556 } else { 1557 Inst.addOperand(MCOperand::createReg(0)); 1558 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1559 Inst.addOperand(MCOperand::createImm(tmp)); 1560 } 1561 1562 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1563 return MCDisassembler::Fail; 1564 1565 return S; 1566 } 1567 1568 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1569 uint64_t Address, const void *Decoder) { 1570 DecodeStatus S = MCDisassembler::Success; 1571 1572 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1573 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1574 unsigned type = fieldFromInstruction(Val, 5, 2); 1575 unsigned imm = fieldFromInstruction(Val, 7, 5); 1576 unsigned U = fieldFromInstruction(Val, 12, 1); 1577 1578 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1579 switch (type) { 1580 case 0: 1581 ShOp = ARM_AM::lsl; 1582 break; 1583 case 1: 1584 ShOp = ARM_AM::lsr; 1585 break; 1586 case 2: 1587 ShOp = ARM_AM::asr; 1588 break; 1589 case 3: 1590 ShOp = ARM_AM::ror; 1591 break; 1592 } 1593 1594 if (ShOp == ARM_AM::ror && imm == 0) 1595 ShOp = ARM_AM::rrx; 1596 1597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1598 return MCDisassembler::Fail; 1599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1600 return MCDisassembler::Fail; 1601 unsigned shift; 1602 if (U) 1603 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1604 else 1605 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1606 Inst.addOperand(MCOperand::createImm(shift)); 1607 1608 return S; 1609 } 1610 1611 static DecodeStatus 1612 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1613 uint64_t Address, const void *Decoder) { 1614 DecodeStatus S = MCDisassembler::Success; 1615 1616 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1617 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1618 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1619 unsigned type = fieldFromInstruction(Insn, 22, 1); 1620 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1621 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1622 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1623 unsigned W = fieldFromInstruction(Insn, 21, 1); 1624 unsigned P = fieldFromInstruction(Insn, 24, 1); 1625 unsigned Rt2 = Rt + 1; 1626 1627 bool writeback = (W == 1) | (P == 0); 1628 1629 // For {LD,ST}RD, Rt must be even, else undefined. 1630 switch (Inst.getOpcode()) { 1631 case ARM::STRD: 1632 case ARM::STRD_PRE: 1633 case ARM::STRD_POST: 1634 case ARM::LDRD: 1635 case ARM::LDRD_PRE: 1636 case ARM::LDRD_POST: 1637 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1638 break; 1639 default: 1640 break; 1641 } 1642 switch (Inst.getOpcode()) { 1643 case ARM::STRD: 1644 case ARM::STRD_PRE: 1645 case ARM::STRD_POST: 1646 if (P == 0 && W == 1) 1647 S = MCDisassembler::SoftFail; 1648 1649 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1650 S = MCDisassembler::SoftFail; 1651 if (type && Rm == 15) 1652 S = MCDisassembler::SoftFail; 1653 if (Rt2 == 15) 1654 S = MCDisassembler::SoftFail; 1655 if (!type && fieldFromInstruction(Insn, 8, 4)) 1656 S = MCDisassembler::SoftFail; 1657 break; 1658 case ARM::STRH: 1659 case ARM::STRH_PRE: 1660 case ARM::STRH_POST: 1661 if (Rt == 15) 1662 S = MCDisassembler::SoftFail; 1663 if (writeback && (Rn == 15 || Rn == Rt)) 1664 S = MCDisassembler::SoftFail; 1665 if (!type && Rm == 15) 1666 S = MCDisassembler::SoftFail; 1667 break; 1668 case ARM::LDRD: 1669 case ARM::LDRD_PRE: 1670 case ARM::LDRD_POST: 1671 if (type && Rn == 15){ 1672 if (Rt2 == 15) 1673 S = MCDisassembler::SoftFail; 1674 break; 1675 } 1676 if (P == 0 && W == 1) 1677 S = MCDisassembler::SoftFail; 1678 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1679 S = MCDisassembler::SoftFail; 1680 if (!type && writeback && Rn == 15) 1681 S = MCDisassembler::SoftFail; 1682 if (writeback && (Rn == Rt || Rn == Rt2)) 1683 S = MCDisassembler::SoftFail; 1684 break; 1685 case ARM::LDRH: 1686 case ARM::LDRH_PRE: 1687 case ARM::LDRH_POST: 1688 if (type && Rn == 15){ 1689 if (Rt == 15) 1690 S = MCDisassembler::SoftFail; 1691 break; 1692 } 1693 if (Rt == 15) 1694 S = MCDisassembler::SoftFail; 1695 if (!type && Rm == 15) 1696 S = MCDisassembler::SoftFail; 1697 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1698 S = MCDisassembler::SoftFail; 1699 break; 1700 case ARM::LDRSH: 1701 case ARM::LDRSH_PRE: 1702 case ARM::LDRSH_POST: 1703 case ARM::LDRSB: 1704 case ARM::LDRSB_PRE: 1705 case ARM::LDRSB_POST: 1706 if (type && Rn == 15){ 1707 if (Rt == 15) 1708 S = MCDisassembler::SoftFail; 1709 break; 1710 } 1711 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1712 S = MCDisassembler::SoftFail; 1713 if (!type && (Rt == 15 || Rm == 15)) 1714 S = MCDisassembler::SoftFail; 1715 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1716 S = MCDisassembler::SoftFail; 1717 break; 1718 default: 1719 break; 1720 } 1721 1722 if (writeback) { // Writeback 1723 if (P) 1724 U |= ARMII::IndexModePre << 9; 1725 else 1726 U |= ARMII::IndexModePost << 9; 1727 1728 // On stores, the writeback operand precedes Rt. 1729 switch (Inst.getOpcode()) { 1730 case ARM::STRD: 1731 case ARM::STRD_PRE: 1732 case ARM::STRD_POST: 1733 case ARM::STRH: 1734 case ARM::STRH_PRE: 1735 case ARM::STRH_POST: 1736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1737 return MCDisassembler::Fail; 1738 break; 1739 default: 1740 break; 1741 } 1742 } 1743 1744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1745 return MCDisassembler::Fail; 1746 switch (Inst.getOpcode()) { 1747 case ARM::STRD: 1748 case ARM::STRD_PRE: 1749 case ARM::STRD_POST: 1750 case ARM::LDRD: 1751 case ARM::LDRD_PRE: 1752 case ARM::LDRD_POST: 1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1754 return MCDisassembler::Fail; 1755 break; 1756 default: 1757 break; 1758 } 1759 1760 if (writeback) { 1761 // On loads, the writeback operand comes after Rt. 1762 switch (Inst.getOpcode()) { 1763 case ARM::LDRD: 1764 case ARM::LDRD_PRE: 1765 case ARM::LDRD_POST: 1766 case ARM::LDRH: 1767 case ARM::LDRH_PRE: 1768 case ARM::LDRH_POST: 1769 case ARM::LDRSH: 1770 case ARM::LDRSH_PRE: 1771 case ARM::LDRSH_POST: 1772 case ARM::LDRSB: 1773 case ARM::LDRSB_PRE: 1774 case ARM::LDRSB_POST: 1775 case ARM::LDRHTr: 1776 case ARM::LDRSBTr: 1777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1778 return MCDisassembler::Fail; 1779 break; 1780 default: 1781 break; 1782 } 1783 } 1784 1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1786 return MCDisassembler::Fail; 1787 1788 if (type) { 1789 Inst.addOperand(MCOperand::createReg(0)); 1790 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1791 } else { 1792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1793 return MCDisassembler::Fail; 1794 Inst.addOperand(MCOperand::createImm(U)); 1795 } 1796 1797 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1798 return MCDisassembler::Fail; 1799 1800 return S; 1801 } 1802 1803 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1804 uint64_t Address, const void *Decoder) { 1805 DecodeStatus S = MCDisassembler::Success; 1806 1807 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1808 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1809 1810 switch (mode) { 1811 case 0: 1812 mode = ARM_AM::da; 1813 break; 1814 case 1: 1815 mode = ARM_AM::ia; 1816 break; 1817 case 2: 1818 mode = ARM_AM::db; 1819 break; 1820 case 3: 1821 mode = ARM_AM::ib; 1822 break; 1823 } 1824 1825 Inst.addOperand(MCOperand::createImm(mode)); 1826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1827 return MCDisassembler::Fail; 1828 1829 return S; 1830 } 1831 1832 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1833 uint64_t Address, const void *Decoder) { 1834 DecodeStatus S = MCDisassembler::Success; 1835 1836 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1837 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1838 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1839 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1840 1841 if (pred == 0xF) 1842 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1843 1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1845 return MCDisassembler::Fail; 1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1847 return MCDisassembler::Fail; 1848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1849 return MCDisassembler::Fail; 1850 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1851 return MCDisassembler::Fail; 1852 return S; 1853 } 1854 1855 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1856 unsigned Insn, 1857 uint64_t Address, const void *Decoder) { 1858 DecodeStatus S = MCDisassembler::Success; 1859 1860 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1861 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1862 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1863 1864 if (pred == 0xF) { 1865 // Ambiguous with RFE and SRS 1866 switch (Inst.getOpcode()) { 1867 case ARM::LDMDA: 1868 Inst.setOpcode(ARM::RFEDA); 1869 break; 1870 case ARM::LDMDA_UPD: 1871 Inst.setOpcode(ARM::RFEDA_UPD); 1872 break; 1873 case ARM::LDMDB: 1874 Inst.setOpcode(ARM::RFEDB); 1875 break; 1876 case ARM::LDMDB_UPD: 1877 Inst.setOpcode(ARM::RFEDB_UPD); 1878 break; 1879 case ARM::LDMIA: 1880 Inst.setOpcode(ARM::RFEIA); 1881 break; 1882 case ARM::LDMIA_UPD: 1883 Inst.setOpcode(ARM::RFEIA_UPD); 1884 break; 1885 case ARM::LDMIB: 1886 Inst.setOpcode(ARM::RFEIB); 1887 break; 1888 case ARM::LDMIB_UPD: 1889 Inst.setOpcode(ARM::RFEIB_UPD); 1890 break; 1891 case ARM::STMDA: 1892 Inst.setOpcode(ARM::SRSDA); 1893 break; 1894 case ARM::STMDA_UPD: 1895 Inst.setOpcode(ARM::SRSDA_UPD); 1896 break; 1897 case ARM::STMDB: 1898 Inst.setOpcode(ARM::SRSDB); 1899 break; 1900 case ARM::STMDB_UPD: 1901 Inst.setOpcode(ARM::SRSDB_UPD); 1902 break; 1903 case ARM::STMIA: 1904 Inst.setOpcode(ARM::SRSIA); 1905 break; 1906 case ARM::STMIA_UPD: 1907 Inst.setOpcode(ARM::SRSIA_UPD); 1908 break; 1909 case ARM::STMIB: 1910 Inst.setOpcode(ARM::SRSIB); 1911 break; 1912 case ARM::STMIB_UPD: 1913 Inst.setOpcode(ARM::SRSIB_UPD); 1914 break; 1915 default: 1916 return MCDisassembler::Fail; 1917 } 1918 1919 // For stores (which become SRS's, the only operand is the mode. 1920 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1921 // Check SRS encoding constraints 1922 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1923 fieldFromInstruction(Insn, 20, 1) == 0)) 1924 return MCDisassembler::Fail; 1925 1926 Inst.addOperand( 1927 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 1928 return S; 1929 } 1930 1931 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1932 } 1933 1934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1935 return MCDisassembler::Fail; 1936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1937 return MCDisassembler::Fail; // Tied 1938 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1939 return MCDisassembler::Fail; 1940 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1941 return MCDisassembler::Fail; 1942 1943 return S; 1944 } 1945 1946 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1947 uint64_t Address, const void *Decoder) { 1948 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1949 unsigned M = fieldFromInstruction(Insn, 17, 1); 1950 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1951 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1952 1953 DecodeStatus S = MCDisassembler::Success; 1954 1955 // This decoder is called from multiple location that do not check 1956 // the full encoding is valid before they do. 1957 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1958 fieldFromInstruction(Insn, 16, 1) != 0 || 1959 fieldFromInstruction(Insn, 20, 8) != 0x10) 1960 return MCDisassembler::Fail; 1961 1962 // imod == '01' --> UNPREDICTABLE 1963 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1964 // return failure here. The '01' imod value is unprintable, so there's 1965 // nothing useful we could do even if we returned UNPREDICTABLE. 1966 1967 if (imod == 1) return MCDisassembler::Fail; 1968 1969 if (imod && M) { 1970 Inst.setOpcode(ARM::CPS3p); 1971 Inst.addOperand(MCOperand::createImm(imod)); 1972 Inst.addOperand(MCOperand::createImm(iflags)); 1973 Inst.addOperand(MCOperand::createImm(mode)); 1974 } else if (imod && !M) { 1975 Inst.setOpcode(ARM::CPS2p); 1976 Inst.addOperand(MCOperand::createImm(imod)); 1977 Inst.addOperand(MCOperand::createImm(iflags)); 1978 if (mode) S = MCDisassembler::SoftFail; 1979 } else if (!imod && M) { 1980 Inst.setOpcode(ARM::CPS1p); 1981 Inst.addOperand(MCOperand::createImm(mode)); 1982 if (iflags) S = MCDisassembler::SoftFail; 1983 } else { 1984 // imod == '00' && M == '0' --> UNPREDICTABLE 1985 Inst.setOpcode(ARM::CPS1p); 1986 Inst.addOperand(MCOperand::createImm(mode)); 1987 S = MCDisassembler::SoftFail; 1988 } 1989 1990 return S; 1991 } 1992 1993 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1994 uint64_t Address, const void *Decoder) { 1995 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1996 unsigned M = fieldFromInstruction(Insn, 8, 1); 1997 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1998 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1999 2000 DecodeStatus S = MCDisassembler::Success; 2001 2002 // imod == '01' --> UNPREDICTABLE 2003 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2004 // return failure here. The '01' imod value is unprintable, so there's 2005 // nothing useful we could do even if we returned UNPREDICTABLE. 2006 2007 if (imod == 1) return MCDisassembler::Fail; 2008 2009 if (imod && M) { 2010 Inst.setOpcode(ARM::t2CPS3p); 2011 Inst.addOperand(MCOperand::createImm(imod)); 2012 Inst.addOperand(MCOperand::createImm(iflags)); 2013 Inst.addOperand(MCOperand::createImm(mode)); 2014 } else if (imod && !M) { 2015 Inst.setOpcode(ARM::t2CPS2p); 2016 Inst.addOperand(MCOperand::createImm(imod)); 2017 Inst.addOperand(MCOperand::createImm(iflags)); 2018 if (mode) S = MCDisassembler::SoftFail; 2019 } else if (!imod && M) { 2020 Inst.setOpcode(ARM::t2CPS1p); 2021 Inst.addOperand(MCOperand::createImm(mode)); 2022 if (iflags) S = MCDisassembler::SoftFail; 2023 } else { 2024 // imod == '00' && M == '0' --> this is a HINT instruction 2025 int imm = fieldFromInstruction(Insn, 0, 8); 2026 // HINT are defined only for immediate in [0..4] 2027 if(imm > 4) return MCDisassembler::Fail; 2028 Inst.setOpcode(ARM::t2HINT); 2029 Inst.addOperand(MCOperand::createImm(imm)); 2030 } 2031 2032 return S; 2033 } 2034 2035 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2036 uint64_t Address, const void *Decoder) { 2037 DecodeStatus S = MCDisassembler::Success; 2038 2039 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2040 unsigned imm = 0; 2041 2042 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2043 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2044 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2045 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2046 2047 if (Inst.getOpcode() == ARM::t2MOVTi16) 2048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2049 return MCDisassembler::Fail; 2050 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2051 return MCDisassembler::Fail; 2052 2053 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2054 Inst.addOperand(MCOperand::createImm(imm)); 2055 2056 return S; 2057 } 2058 2059 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2060 uint64_t Address, const void *Decoder) { 2061 DecodeStatus S = MCDisassembler::Success; 2062 2063 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2064 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2065 unsigned imm = 0; 2066 2067 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2068 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2069 2070 if (Inst.getOpcode() == ARM::MOVTi16) 2071 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2072 return MCDisassembler::Fail; 2073 2074 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2075 return MCDisassembler::Fail; 2076 2077 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2078 Inst.addOperand(MCOperand::createImm(imm)); 2079 2080 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2081 return MCDisassembler::Fail; 2082 2083 return S; 2084 } 2085 2086 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2087 uint64_t Address, const void *Decoder) { 2088 DecodeStatus S = MCDisassembler::Success; 2089 2090 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2091 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2092 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2093 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2094 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2095 2096 if (pred == 0xF) 2097 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2098 2099 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2100 return MCDisassembler::Fail; 2101 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2102 return MCDisassembler::Fail; 2103 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2104 return MCDisassembler::Fail; 2105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2106 return MCDisassembler::Fail; 2107 2108 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2109 return MCDisassembler::Fail; 2110 2111 return S; 2112 } 2113 2114 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2115 uint64_t Address, const void *Decoder) { 2116 DecodeStatus S = MCDisassembler::Success; 2117 2118 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2119 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2120 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2121 2122 if (Pred == 0xF) 2123 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2124 2125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2126 return MCDisassembler::Fail; 2127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2128 return MCDisassembler::Fail; 2129 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2130 return MCDisassembler::Fail; 2131 2132 return S; 2133 } 2134 2135 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2136 uint64_t Address, const void *Decoder) { 2137 DecodeStatus S = MCDisassembler::Success; 2138 2139 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2140 2141 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2142 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2143 2144 if (!FeatureBits[ARM::HasV8_1aOps] || 2145 !FeatureBits[ARM::HasV8Ops]) 2146 return MCDisassembler::Fail; 2147 2148 // Decoder can be called from DecodeTST, which does not check the full 2149 // encoding is valid. 2150 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2151 fieldFromInstruction(Insn, 4,4) != 0) 2152 return MCDisassembler::Fail; 2153 if (fieldFromInstruction(Insn, 10,10) != 0 || 2154 fieldFromInstruction(Insn, 0,4) != 0) 2155 S = MCDisassembler::SoftFail; 2156 2157 Inst.setOpcode(ARM::SETPAN); 2158 Inst.addOperand(MCOperand::createImm(Imm)); 2159 2160 return S; 2161 } 2162 2163 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2164 uint64_t Address, const void *Decoder) { 2165 DecodeStatus S = MCDisassembler::Success; 2166 2167 unsigned add = fieldFromInstruction(Val, 12, 1); 2168 unsigned imm = fieldFromInstruction(Val, 0, 12); 2169 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2170 2171 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2172 return MCDisassembler::Fail; 2173 2174 if (!add) imm *= -1; 2175 if (imm == 0 && !add) imm = INT32_MIN; 2176 Inst.addOperand(MCOperand::createImm(imm)); 2177 if (Rn == 15) 2178 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2179 2180 return S; 2181 } 2182 2183 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2184 uint64_t Address, const void *Decoder) { 2185 DecodeStatus S = MCDisassembler::Success; 2186 2187 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2188 // U == 1 to add imm, 0 to subtract it. 2189 unsigned U = fieldFromInstruction(Val, 8, 1); 2190 unsigned imm = fieldFromInstruction(Val, 0, 8); 2191 2192 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2193 return MCDisassembler::Fail; 2194 2195 if (U) 2196 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2197 else 2198 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2199 2200 return S; 2201 } 2202 2203 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2204 uint64_t Address, const void *Decoder) { 2205 DecodeStatus S = MCDisassembler::Success; 2206 2207 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2208 // U == 1 to add imm, 0 to subtract it. 2209 unsigned U = fieldFromInstruction(Val, 8, 1); 2210 unsigned imm = fieldFromInstruction(Val, 0, 8); 2211 2212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2213 return MCDisassembler::Fail; 2214 2215 if (U) 2216 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2217 else 2218 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2219 2220 return S; 2221 } 2222 2223 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2224 uint64_t Address, const void *Decoder) { 2225 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2226 } 2227 2228 static DecodeStatus 2229 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2230 uint64_t Address, const void *Decoder) { 2231 DecodeStatus Status = MCDisassembler::Success; 2232 2233 // Note the J1 and J2 values are from the encoded instruction. So here 2234 // change them to I1 and I2 values via as documented: 2235 // I1 = NOT(J1 EOR S); 2236 // I2 = NOT(J2 EOR S); 2237 // and build the imm32 with one trailing zero as documented: 2238 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2239 unsigned S = fieldFromInstruction(Insn, 26, 1); 2240 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2241 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2242 unsigned I1 = !(J1 ^ S); 2243 unsigned I2 = !(J2 ^ S); 2244 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2245 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2246 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2247 int imm32 = SignExtend32<25>(tmp << 1); 2248 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2249 true, 4, Inst, Decoder)) 2250 Inst.addOperand(MCOperand::createImm(imm32)); 2251 2252 return Status; 2253 } 2254 2255 static DecodeStatus 2256 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2257 uint64_t Address, const void *Decoder) { 2258 DecodeStatus S = MCDisassembler::Success; 2259 2260 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2261 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2262 2263 if (pred == 0xF) { 2264 Inst.setOpcode(ARM::BLXi); 2265 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2266 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2267 true, 4, Inst, Decoder)) 2268 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2269 return S; 2270 } 2271 2272 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2273 true, 4, Inst, Decoder)) 2274 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2275 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2276 return MCDisassembler::Fail; 2277 2278 return S; 2279 } 2280 2281 2282 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2283 uint64_t Address, const void *Decoder) { 2284 DecodeStatus S = MCDisassembler::Success; 2285 2286 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2287 unsigned align = fieldFromInstruction(Val, 4, 2); 2288 2289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2290 return MCDisassembler::Fail; 2291 if (!align) 2292 Inst.addOperand(MCOperand::createImm(0)); 2293 else 2294 Inst.addOperand(MCOperand::createImm(4 << align)); 2295 2296 return S; 2297 } 2298 2299 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2300 uint64_t Address, const void *Decoder) { 2301 DecodeStatus S = MCDisassembler::Success; 2302 2303 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2304 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2305 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2306 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2307 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2308 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2309 2310 // First output register 2311 switch (Inst.getOpcode()) { 2312 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2313 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2314 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2315 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2316 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2317 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2318 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2319 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2320 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2321 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2322 return MCDisassembler::Fail; 2323 break; 2324 case ARM::VLD2b16: 2325 case ARM::VLD2b32: 2326 case ARM::VLD2b8: 2327 case ARM::VLD2b16wb_fixed: 2328 case ARM::VLD2b16wb_register: 2329 case ARM::VLD2b32wb_fixed: 2330 case ARM::VLD2b32wb_register: 2331 case ARM::VLD2b8wb_fixed: 2332 case ARM::VLD2b8wb_register: 2333 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2334 return MCDisassembler::Fail; 2335 break; 2336 default: 2337 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2338 return MCDisassembler::Fail; 2339 } 2340 2341 // Second output register 2342 switch (Inst.getOpcode()) { 2343 case ARM::VLD3d8: 2344 case ARM::VLD3d16: 2345 case ARM::VLD3d32: 2346 case ARM::VLD3d8_UPD: 2347 case ARM::VLD3d16_UPD: 2348 case ARM::VLD3d32_UPD: 2349 case ARM::VLD4d8: 2350 case ARM::VLD4d16: 2351 case ARM::VLD4d32: 2352 case ARM::VLD4d8_UPD: 2353 case ARM::VLD4d16_UPD: 2354 case ARM::VLD4d32_UPD: 2355 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2356 return MCDisassembler::Fail; 2357 break; 2358 case ARM::VLD3q8: 2359 case ARM::VLD3q16: 2360 case ARM::VLD3q32: 2361 case ARM::VLD3q8_UPD: 2362 case ARM::VLD3q16_UPD: 2363 case ARM::VLD3q32_UPD: 2364 case ARM::VLD4q8: 2365 case ARM::VLD4q16: 2366 case ARM::VLD4q32: 2367 case ARM::VLD4q8_UPD: 2368 case ARM::VLD4q16_UPD: 2369 case ARM::VLD4q32_UPD: 2370 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2371 return MCDisassembler::Fail; 2372 default: 2373 break; 2374 } 2375 2376 // Third output register 2377 switch(Inst.getOpcode()) { 2378 case ARM::VLD3d8: 2379 case ARM::VLD3d16: 2380 case ARM::VLD3d32: 2381 case ARM::VLD3d8_UPD: 2382 case ARM::VLD3d16_UPD: 2383 case ARM::VLD3d32_UPD: 2384 case ARM::VLD4d8: 2385 case ARM::VLD4d16: 2386 case ARM::VLD4d32: 2387 case ARM::VLD4d8_UPD: 2388 case ARM::VLD4d16_UPD: 2389 case ARM::VLD4d32_UPD: 2390 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2391 return MCDisassembler::Fail; 2392 break; 2393 case ARM::VLD3q8: 2394 case ARM::VLD3q16: 2395 case ARM::VLD3q32: 2396 case ARM::VLD3q8_UPD: 2397 case ARM::VLD3q16_UPD: 2398 case ARM::VLD3q32_UPD: 2399 case ARM::VLD4q8: 2400 case ARM::VLD4q16: 2401 case ARM::VLD4q32: 2402 case ARM::VLD4q8_UPD: 2403 case ARM::VLD4q16_UPD: 2404 case ARM::VLD4q32_UPD: 2405 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2406 return MCDisassembler::Fail; 2407 break; 2408 default: 2409 break; 2410 } 2411 2412 // Fourth output register 2413 switch (Inst.getOpcode()) { 2414 case ARM::VLD4d8: 2415 case ARM::VLD4d16: 2416 case ARM::VLD4d32: 2417 case ARM::VLD4d8_UPD: 2418 case ARM::VLD4d16_UPD: 2419 case ARM::VLD4d32_UPD: 2420 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2421 return MCDisassembler::Fail; 2422 break; 2423 case ARM::VLD4q8: 2424 case ARM::VLD4q16: 2425 case ARM::VLD4q32: 2426 case ARM::VLD4q8_UPD: 2427 case ARM::VLD4q16_UPD: 2428 case ARM::VLD4q32_UPD: 2429 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2430 return MCDisassembler::Fail; 2431 break; 2432 default: 2433 break; 2434 } 2435 2436 // Writeback operand 2437 switch (Inst.getOpcode()) { 2438 case ARM::VLD1d8wb_fixed: 2439 case ARM::VLD1d16wb_fixed: 2440 case ARM::VLD1d32wb_fixed: 2441 case ARM::VLD1d64wb_fixed: 2442 case ARM::VLD1d8wb_register: 2443 case ARM::VLD1d16wb_register: 2444 case ARM::VLD1d32wb_register: 2445 case ARM::VLD1d64wb_register: 2446 case ARM::VLD1q8wb_fixed: 2447 case ARM::VLD1q16wb_fixed: 2448 case ARM::VLD1q32wb_fixed: 2449 case ARM::VLD1q64wb_fixed: 2450 case ARM::VLD1q8wb_register: 2451 case ARM::VLD1q16wb_register: 2452 case ARM::VLD1q32wb_register: 2453 case ARM::VLD1q64wb_register: 2454 case ARM::VLD1d8Twb_fixed: 2455 case ARM::VLD1d8Twb_register: 2456 case ARM::VLD1d16Twb_fixed: 2457 case ARM::VLD1d16Twb_register: 2458 case ARM::VLD1d32Twb_fixed: 2459 case ARM::VLD1d32Twb_register: 2460 case ARM::VLD1d64Twb_fixed: 2461 case ARM::VLD1d64Twb_register: 2462 case ARM::VLD1d8Qwb_fixed: 2463 case ARM::VLD1d8Qwb_register: 2464 case ARM::VLD1d16Qwb_fixed: 2465 case ARM::VLD1d16Qwb_register: 2466 case ARM::VLD1d32Qwb_fixed: 2467 case ARM::VLD1d32Qwb_register: 2468 case ARM::VLD1d64Qwb_fixed: 2469 case ARM::VLD1d64Qwb_register: 2470 case ARM::VLD2d8wb_fixed: 2471 case ARM::VLD2d16wb_fixed: 2472 case ARM::VLD2d32wb_fixed: 2473 case ARM::VLD2q8wb_fixed: 2474 case ARM::VLD2q16wb_fixed: 2475 case ARM::VLD2q32wb_fixed: 2476 case ARM::VLD2d8wb_register: 2477 case ARM::VLD2d16wb_register: 2478 case ARM::VLD2d32wb_register: 2479 case ARM::VLD2q8wb_register: 2480 case ARM::VLD2q16wb_register: 2481 case ARM::VLD2q32wb_register: 2482 case ARM::VLD2b8wb_fixed: 2483 case ARM::VLD2b16wb_fixed: 2484 case ARM::VLD2b32wb_fixed: 2485 case ARM::VLD2b8wb_register: 2486 case ARM::VLD2b16wb_register: 2487 case ARM::VLD2b32wb_register: 2488 Inst.addOperand(MCOperand::createImm(0)); 2489 break; 2490 case ARM::VLD3d8_UPD: 2491 case ARM::VLD3d16_UPD: 2492 case ARM::VLD3d32_UPD: 2493 case ARM::VLD3q8_UPD: 2494 case ARM::VLD3q16_UPD: 2495 case ARM::VLD3q32_UPD: 2496 case ARM::VLD4d8_UPD: 2497 case ARM::VLD4d16_UPD: 2498 case ARM::VLD4d32_UPD: 2499 case ARM::VLD4q8_UPD: 2500 case ARM::VLD4q16_UPD: 2501 case ARM::VLD4q32_UPD: 2502 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2503 return MCDisassembler::Fail; 2504 break; 2505 default: 2506 break; 2507 } 2508 2509 // AddrMode6 Base (register+alignment) 2510 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2511 return MCDisassembler::Fail; 2512 2513 // AddrMode6 Offset (register) 2514 switch (Inst.getOpcode()) { 2515 default: 2516 // The below have been updated to have explicit am6offset split 2517 // between fixed and register offset. For those instructions not 2518 // yet updated, we need to add an additional reg0 operand for the 2519 // fixed variant. 2520 // 2521 // The fixed offset encodes as Rm == 0xd, so we check for that. 2522 if (Rm == 0xd) { 2523 Inst.addOperand(MCOperand::createReg(0)); 2524 break; 2525 } 2526 // Fall through to handle the register offset variant. 2527 case ARM::VLD1d8wb_fixed: 2528 case ARM::VLD1d16wb_fixed: 2529 case ARM::VLD1d32wb_fixed: 2530 case ARM::VLD1d64wb_fixed: 2531 case ARM::VLD1d8Twb_fixed: 2532 case ARM::VLD1d16Twb_fixed: 2533 case ARM::VLD1d32Twb_fixed: 2534 case ARM::VLD1d64Twb_fixed: 2535 case ARM::VLD1d8Qwb_fixed: 2536 case ARM::VLD1d16Qwb_fixed: 2537 case ARM::VLD1d32Qwb_fixed: 2538 case ARM::VLD1d64Qwb_fixed: 2539 case ARM::VLD1d8wb_register: 2540 case ARM::VLD1d16wb_register: 2541 case ARM::VLD1d32wb_register: 2542 case ARM::VLD1d64wb_register: 2543 case ARM::VLD1q8wb_fixed: 2544 case ARM::VLD1q16wb_fixed: 2545 case ARM::VLD1q32wb_fixed: 2546 case ARM::VLD1q64wb_fixed: 2547 case ARM::VLD1q8wb_register: 2548 case ARM::VLD1q16wb_register: 2549 case ARM::VLD1q32wb_register: 2550 case ARM::VLD1q64wb_register: 2551 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2552 // variant encodes Rm == 0xf. Anything else is a register offset post- 2553 // increment and we need to add the register operand to the instruction. 2554 if (Rm != 0xD && Rm != 0xF && 2555 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2556 return MCDisassembler::Fail; 2557 break; 2558 case ARM::VLD2d8wb_fixed: 2559 case ARM::VLD2d16wb_fixed: 2560 case ARM::VLD2d32wb_fixed: 2561 case ARM::VLD2b8wb_fixed: 2562 case ARM::VLD2b16wb_fixed: 2563 case ARM::VLD2b32wb_fixed: 2564 case ARM::VLD2q8wb_fixed: 2565 case ARM::VLD2q16wb_fixed: 2566 case ARM::VLD2q32wb_fixed: 2567 break; 2568 } 2569 2570 return S; 2571 } 2572 2573 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2574 uint64_t Address, const void *Decoder) { 2575 unsigned type = fieldFromInstruction(Insn, 8, 4); 2576 unsigned align = fieldFromInstruction(Insn, 4, 2); 2577 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2578 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2579 if (type == 10 && align == 3) return MCDisassembler::Fail; 2580 2581 unsigned load = fieldFromInstruction(Insn, 21, 1); 2582 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2583 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2584 } 2585 2586 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2587 uint64_t Address, const void *Decoder) { 2588 unsigned size = fieldFromInstruction(Insn, 6, 2); 2589 if (size == 3) return MCDisassembler::Fail; 2590 2591 unsigned type = fieldFromInstruction(Insn, 8, 4); 2592 unsigned align = fieldFromInstruction(Insn, 4, 2); 2593 if (type == 8 && align == 3) return MCDisassembler::Fail; 2594 if (type == 9 && align == 3) return MCDisassembler::Fail; 2595 2596 unsigned load = fieldFromInstruction(Insn, 21, 1); 2597 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2598 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2599 } 2600 2601 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2602 uint64_t Address, const void *Decoder) { 2603 unsigned size = fieldFromInstruction(Insn, 6, 2); 2604 if (size == 3) return MCDisassembler::Fail; 2605 2606 unsigned align = fieldFromInstruction(Insn, 4, 2); 2607 if (align & 2) return MCDisassembler::Fail; 2608 2609 unsigned load = fieldFromInstruction(Insn, 21, 1); 2610 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2611 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2612 } 2613 2614 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2615 uint64_t Address, const void *Decoder) { 2616 unsigned size = fieldFromInstruction(Insn, 6, 2); 2617 if (size == 3) return MCDisassembler::Fail; 2618 2619 unsigned load = fieldFromInstruction(Insn, 21, 1); 2620 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2621 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2622 } 2623 2624 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2625 uint64_t Address, const void *Decoder) { 2626 DecodeStatus S = MCDisassembler::Success; 2627 2628 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2629 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2630 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2631 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2632 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2633 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2634 2635 // Writeback Operand 2636 switch (Inst.getOpcode()) { 2637 case ARM::VST1d8wb_fixed: 2638 case ARM::VST1d16wb_fixed: 2639 case ARM::VST1d32wb_fixed: 2640 case ARM::VST1d64wb_fixed: 2641 case ARM::VST1d8wb_register: 2642 case ARM::VST1d16wb_register: 2643 case ARM::VST1d32wb_register: 2644 case ARM::VST1d64wb_register: 2645 case ARM::VST1q8wb_fixed: 2646 case ARM::VST1q16wb_fixed: 2647 case ARM::VST1q32wb_fixed: 2648 case ARM::VST1q64wb_fixed: 2649 case ARM::VST1q8wb_register: 2650 case ARM::VST1q16wb_register: 2651 case ARM::VST1q32wb_register: 2652 case ARM::VST1q64wb_register: 2653 case ARM::VST1d8Twb_fixed: 2654 case ARM::VST1d16Twb_fixed: 2655 case ARM::VST1d32Twb_fixed: 2656 case ARM::VST1d64Twb_fixed: 2657 case ARM::VST1d8Twb_register: 2658 case ARM::VST1d16Twb_register: 2659 case ARM::VST1d32Twb_register: 2660 case ARM::VST1d64Twb_register: 2661 case ARM::VST1d8Qwb_fixed: 2662 case ARM::VST1d16Qwb_fixed: 2663 case ARM::VST1d32Qwb_fixed: 2664 case ARM::VST1d64Qwb_fixed: 2665 case ARM::VST1d8Qwb_register: 2666 case ARM::VST1d16Qwb_register: 2667 case ARM::VST1d32Qwb_register: 2668 case ARM::VST1d64Qwb_register: 2669 case ARM::VST2d8wb_fixed: 2670 case ARM::VST2d16wb_fixed: 2671 case ARM::VST2d32wb_fixed: 2672 case ARM::VST2d8wb_register: 2673 case ARM::VST2d16wb_register: 2674 case ARM::VST2d32wb_register: 2675 case ARM::VST2q8wb_fixed: 2676 case ARM::VST2q16wb_fixed: 2677 case ARM::VST2q32wb_fixed: 2678 case ARM::VST2q8wb_register: 2679 case ARM::VST2q16wb_register: 2680 case ARM::VST2q32wb_register: 2681 case ARM::VST2b8wb_fixed: 2682 case ARM::VST2b16wb_fixed: 2683 case ARM::VST2b32wb_fixed: 2684 case ARM::VST2b8wb_register: 2685 case ARM::VST2b16wb_register: 2686 case ARM::VST2b32wb_register: 2687 if (Rm == 0xF) 2688 return MCDisassembler::Fail; 2689 Inst.addOperand(MCOperand::createImm(0)); 2690 break; 2691 case ARM::VST3d8_UPD: 2692 case ARM::VST3d16_UPD: 2693 case ARM::VST3d32_UPD: 2694 case ARM::VST3q8_UPD: 2695 case ARM::VST3q16_UPD: 2696 case ARM::VST3q32_UPD: 2697 case ARM::VST4d8_UPD: 2698 case ARM::VST4d16_UPD: 2699 case ARM::VST4d32_UPD: 2700 case ARM::VST4q8_UPD: 2701 case ARM::VST4q16_UPD: 2702 case ARM::VST4q32_UPD: 2703 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2704 return MCDisassembler::Fail; 2705 break; 2706 default: 2707 break; 2708 } 2709 2710 // AddrMode6 Base (register+alignment) 2711 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2712 return MCDisassembler::Fail; 2713 2714 // AddrMode6 Offset (register) 2715 switch (Inst.getOpcode()) { 2716 default: 2717 if (Rm == 0xD) 2718 Inst.addOperand(MCOperand::createReg(0)); 2719 else if (Rm != 0xF) { 2720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2721 return MCDisassembler::Fail; 2722 } 2723 break; 2724 case ARM::VST1d8wb_fixed: 2725 case ARM::VST1d16wb_fixed: 2726 case ARM::VST1d32wb_fixed: 2727 case ARM::VST1d64wb_fixed: 2728 case ARM::VST1q8wb_fixed: 2729 case ARM::VST1q16wb_fixed: 2730 case ARM::VST1q32wb_fixed: 2731 case ARM::VST1q64wb_fixed: 2732 case ARM::VST1d8Twb_fixed: 2733 case ARM::VST1d16Twb_fixed: 2734 case ARM::VST1d32Twb_fixed: 2735 case ARM::VST1d64Twb_fixed: 2736 case ARM::VST1d8Qwb_fixed: 2737 case ARM::VST1d16Qwb_fixed: 2738 case ARM::VST1d32Qwb_fixed: 2739 case ARM::VST1d64Qwb_fixed: 2740 case ARM::VST2d8wb_fixed: 2741 case ARM::VST2d16wb_fixed: 2742 case ARM::VST2d32wb_fixed: 2743 case ARM::VST2q8wb_fixed: 2744 case ARM::VST2q16wb_fixed: 2745 case ARM::VST2q32wb_fixed: 2746 case ARM::VST2b8wb_fixed: 2747 case ARM::VST2b16wb_fixed: 2748 case ARM::VST2b32wb_fixed: 2749 break; 2750 } 2751 2752 2753 // First input register 2754 switch (Inst.getOpcode()) { 2755 case ARM::VST1q16: 2756 case ARM::VST1q32: 2757 case ARM::VST1q64: 2758 case ARM::VST1q8: 2759 case ARM::VST1q16wb_fixed: 2760 case ARM::VST1q16wb_register: 2761 case ARM::VST1q32wb_fixed: 2762 case ARM::VST1q32wb_register: 2763 case ARM::VST1q64wb_fixed: 2764 case ARM::VST1q64wb_register: 2765 case ARM::VST1q8wb_fixed: 2766 case ARM::VST1q8wb_register: 2767 case ARM::VST2d16: 2768 case ARM::VST2d32: 2769 case ARM::VST2d8: 2770 case ARM::VST2d16wb_fixed: 2771 case ARM::VST2d16wb_register: 2772 case ARM::VST2d32wb_fixed: 2773 case ARM::VST2d32wb_register: 2774 case ARM::VST2d8wb_fixed: 2775 case ARM::VST2d8wb_register: 2776 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2777 return MCDisassembler::Fail; 2778 break; 2779 case ARM::VST2b16: 2780 case ARM::VST2b32: 2781 case ARM::VST2b8: 2782 case ARM::VST2b16wb_fixed: 2783 case ARM::VST2b16wb_register: 2784 case ARM::VST2b32wb_fixed: 2785 case ARM::VST2b32wb_register: 2786 case ARM::VST2b8wb_fixed: 2787 case ARM::VST2b8wb_register: 2788 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2789 return MCDisassembler::Fail; 2790 break; 2791 default: 2792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 } 2795 2796 // Second input register 2797 switch (Inst.getOpcode()) { 2798 case ARM::VST3d8: 2799 case ARM::VST3d16: 2800 case ARM::VST3d32: 2801 case ARM::VST3d8_UPD: 2802 case ARM::VST3d16_UPD: 2803 case ARM::VST3d32_UPD: 2804 case ARM::VST4d8: 2805 case ARM::VST4d16: 2806 case ARM::VST4d32: 2807 case ARM::VST4d8_UPD: 2808 case ARM::VST4d16_UPD: 2809 case ARM::VST4d32_UPD: 2810 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2811 return MCDisassembler::Fail; 2812 break; 2813 case ARM::VST3q8: 2814 case ARM::VST3q16: 2815 case ARM::VST3q32: 2816 case ARM::VST3q8_UPD: 2817 case ARM::VST3q16_UPD: 2818 case ARM::VST3q32_UPD: 2819 case ARM::VST4q8: 2820 case ARM::VST4q16: 2821 case ARM::VST4q32: 2822 case ARM::VST4q8_UPD: 2823 case ARM::VST4q16_UPD: 2824 case ARM::VST4q32_UPD: 2825 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2826 return MCDisassembler::Fail; 2827 break; 2828 default: 2829 break; 2830 } 2831 2832 // Third input register 2833 switch (Inst.getOpcode()) { 2834 case ARM::VST3d8: 2835 case ARM::VST3d16: 2836 case ARM::VST3d32: 2837 case ARM::VST3d8_UPD: 2838 case ARM::VST3d16_UPD: 2839 case ARM::VST3d32_UPD: 2840 case ARM::VST4d8: 2841 case ARM::VST4d16: 2842 case ARM::VST4d32: 2843 case ARM::VST4d8_UPD: 2844 case ARM::VST4d16_UPD: 2845 case ARM::VST4d32_UPD: 2846 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2847 return MCDisassembler::Fail; 2848 break; 2849 case ARM::VST3q8: 2850 case ARM::VST3q16: 2851 case ARM::VST3q32: 2852 case ARM::VST3q8_UPD: 2853 case ARM::VST3q16_UPD: 2854 case ARM::VST3q32_UPD: 2855 case ARM::VST4q8: 2856 case ARM::VST4q16: 2857 case ARM::VST4q32: 2858 case ARM::VST4q8_UPD: 2859 case ARM::VST4q16_UPD: 2860 case ARM::VST4q32_UPD: 2861 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2862 return MCDisassembler::Fail; 2863 break; 2864 default: 2865 break; 2866 } 2867 2868 // Fourth input register 2869 switch (Inst.getOpcode()) { 2870 case ARM::VST4d8: 2871 case ARM::VST4d16: 2872 case ARM::VST4d32: 2873 case ARM::VST4d8_UPD: 2874 case ARM::VST4d16_UPD: 2875 case ARM::VST4d32_UPD: 2876 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2877 return MCDisassembler::Fail; 2878 break; 2879 case ARM::VST4q8: 2880 case ARM::VST4q16: 2881 case ARM::VST4q32: 2882 case ARM::VST4q8_UPD: 2883 case ARM::VST4q16_UPD: 2884 case ARM::VST4q32_UPD: 2885 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2886 return MCDisassembler::Fail; 2887 break; 2888 default: 2889 break; 2890 } 2891 2892 return S; 2893 } 2894 2895 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2896 uint64_t Address, const void *Decoder) { 2897 DecodeStatus S = MCDisassembler::Success; 2898 2899 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2900 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2901 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2902 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2903 unsigned align = fieldFromInstruction(Insn, 4, 1); 2904 unsigned size = fieldFromInstruction(Insn, 6, 2); 2905 2906 if (size == 0 && align == 1) 2907 return MCDisassembler::Fail; 2908 align *= (1 << size); 2909 2910 switch (Inst.getOpcode()) { 2911 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2912 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2913 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2914 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2915 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2916 return MCDisassembler::Fail; 2917 break; 2918 default: 2919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2920 return MCDisassembler::Fail; 2921 break; 2922 } 2923 if (Rm != 0xF) { 2924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2925 return MCDisassembler::Fail; 2926 } 2927 2928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2929 return MCDisassembler::Fail; 2930 Inst.addOperand(MCOperand::createImm(align)); 2931 2932 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2933 // variant encodes Rm == 0xf. Anything else is a register offset post- 2934 // increment and we need to add the register operand to the instruction. 2935 if (Rm != 0xD && Rm != 0xF && 2936 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2937 return MCDisassembler::Fail; 2938 2939 return S; 2940 } 2941 2942 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2943 uint64_t Address, const void *Decoder) { 2944 DecodeStatus S = MCDisassembler::Success; 2945 2946 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2947 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2948 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2949 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2950 unsigned align = fieldFromInstruction(Insn, 4, 1); 2951 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2952 align *= 2*size; 2953 2954 switch (Inst.getOpcode()) { 2955 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2956 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2957 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2958 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2959 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2960 return MCDisassembler::Fail; 2961 break; 2962 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2963 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2964 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2965 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2966 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2967 return MCDisassembler::Fail; 2968 break; 2969 default: 2970 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2971 return MCDisassembler::Fail; 2972 break; 2973 } 2974 2975 if (Rm != 0xF) 2976 Inst.addOperand(MCOperand::createImm(0)); 2977 2978 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2979 return MCDisassembler::Fail; 2980 Inst.addOperand(MCOperand::createImm(align)); 2981 2982 if (Rm != 0xD && Rm != 0xF) { 2983 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 } 2986 2987 return S; 2988 } 2989 2990 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2991 uint64_t Address, const void *Decoder) { 2992 DecodeStatus S = MCDisassembler::Success; 2993 2994 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2995 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2996 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2997 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2998 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2999 3000 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3001 return MCDisassembler::Fail; 3002 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3003 return MCDisassembler::Fail; 3004 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3005 return MCDisassembler::Fail; 3006 if (Rm != 0xF) { 3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3008 return MCDisassembler::Fail; 3009 } 3010 3011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3012 return MCDisassembler::Fail; 3013 Inst.addOperand(MCOperand::createImm(0)); 3014 3015 if (Rm == 0xD) 3016 Inst.addOperand(MCOperand::createReg(0)); 3017 else if (Rm != 0xF) { 3018 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3019 return MCDisassembler::Fail; 3020 } 3021 3022 return S; 3023 } 3024 3025 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3026 uint64_t Address, const void *Decoder) { 3027 DecodeStatus S = MCDisassembler::Success; 3028 3029 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3030 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3031 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3032 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3033 unsigned size = fieldFromInstruction(Insn, 6, 2); 3034 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3035 unsigned align = fieldFromInstruction(Insn, 4, 1); 3036 3037 if (size == 0x3) { 3038 if (align == 0) 3039 return MCDisassembler::Fail; 3040 align = 16; 3041 } else { 3042 if (size == 2) { 3043 align *= 8; 3044 } else { 3045 size = 1 << size; 3046 align *= 4*size; 3047 } 3048 } 3049 3050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3053 return MCDisassembler::Fail; 3054 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3055 return MCDisassembler::Fail; 3056 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3057 return MCDisassembler::Fail; 3058 if (Rm != 0xF) { 3059 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3060 return MCDisassembler::Fail; 3061 } 3062 3063 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3064 return MCDisassembler::Fail; 3065 Inst.addOperand(MCOperand::createImm(align)); 3066 3067 if (Rm == 0xD) 3068 Inst.addOperand(MCOperand::createReg(0)); 3069 else if (Rm != 0xF) { 3070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3071 return MCDisassembler::Fail; 3072 } 3073 3074 return S; 3075 } 3076 3077 static DecodeStatus 3078 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3079 uint64_t Address, const void *Decoder) { 3080 DecodeStatus S = MCDisassembler::Success; 3081 3082 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3083 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3084 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3085 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3086 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3087 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3088 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3089 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3090 3091 if (Q) { 3092 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3093 return MCDisassembler::Fail; 3094 } else { 3095 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3096 return MCDisassembler::Fail; 3097 } 3098 3099 Inst.addOperand(MCOperand::createImm(imm)); 3100 3101 switch (Inst.getOpcode()) { 3102 case ARM::VORRiv4i16: 3103 case ARM::VORRiv2i32: 3104 case ARM::VBICiv4i16: 3105 case ARM::VBICiv2i32: 3106 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3107 return MCDisassembler::Fail; 3108 break; 3109 case ARM::VORRiv8i16: 3110 case ARM::VORRiv4i32: 3111 case ARM::VBICiv8i16: 3112 case ARM::VBICiv4i32: 3113 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3114 return MCDisassembler::Fail; 3115 break; 3116 default: 3117 break; 3118 } 3119 3120 return S; 3121 } 3122 3123 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3124 uint64_t Address, const void *Decoder) { 3125 DecodeStatus S = MCDisassembler::Success; 3126 3127 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3128 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3129 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3130 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3131 unsigned size = fieldFromInstruction(Insn, 18, 2); 3132 3133 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3134 return MCDisassembler::Fail; 3135 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3136 return MCDisassembler::Fail; 3137 Inst.addOperand(MCOperand::createImm(8 << size)); 3138 3139 return S; 3140 } 3141 3142 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3143 uint64_t Address, const void *Decoder) { 3144 Inst.addOperand(MCOperand::createImm(8 - Val)); 3145 return MCDisassembler::Success; 3146 } 3147 3148 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3149 uint64_t Address, const void *Decoder) { 3150 Inst.addOperand(MCOperand::createImm(16 - Val)); 3151 return MCDisassembler::Success; 3152 } 3153 3154 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3155 uint64_t Address, const void *Decoder) { 3156 Inst.addOperand(MCOperand::createImm(32 - Val)); 3157 return MCDisassembler::Success; 3158 } 3159 3160 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3161 uint64_t Address, const void *Decoder) { 3162 Inst.addOperand(MCOperand::createImm(64 - Val)); 3163 return MCDisassembler::Success; 3164 } 3165 3166 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3167 uint64_t Address, const void *Decoder) { 3168 DecodeStatus S = MCDisassembler::Success; 3169 3170 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3171 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3172 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3173 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3174 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3175 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3176 unsigned op = fieldFromInstruction(Insn, 6, 1); 3177 3178 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3179 return MCDisassembler::Fail; 3180 if (op) { 3181 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3182 return MCDisassembler::Fail; // Writeback 3183 } 3184 3185 switch (Inst.getOpcode()) { 3186 case ARM::VTBL2: 3187 case ARM::VTBX2: 3188 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3189 return MCDisassembler::Fail; 3190 break; 3191 default: 3192 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3193 return MCDisassembler::Fail; 3194 } 3195 3196 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3197 return MCDisassembler::Fail; 3198 3199 return S; 3200 } 3201 3202 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3203 uint64_t Address, const void *Decoder) { 3204 DecodeStatus S = MCDisassembler::Success; 3205 3206 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3207 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3208 3209 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3210 return MCDisassembler::Fail; 3211 3212 switch(Inst.getOpcode()) { 3213 default: 3214 return MCDisassembler::Fail; 3215 case ARM::tADR: 3216 break; // tADR does not explicitly represent the PC as an operand. 3217 case ARM::tADDrSPi: 3218 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3219 break; 3220 } 3221 3222 Inst.addOperand(MCOperand::createImm(imm)); 3223 return S; 3224 } 3225 3226 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3227 uint64_t Address, const void *Decoder) { 3228 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3229 true, 2, Inst, Decoder)) 3230 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3231 return MCDisassembler::Success; 3232 } 3233 3234 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3235 uint64_t Address, const void *Decoder) { 3236 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3237 true, 4, Inst, Decoder)) 3238 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3239 return MCDisassembler::Success; 3240 } 3241 3242 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3243 uint64_t Address, const void *Decoder) { 3244 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3245 true, 2, Inst, Decoder)) 3246 Inst.addOperand(MCOperand::createImm(Val << 1)); 3247 return MCDisassembler::Success; 3248 } 3249 3250 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3251 uint64_t Address, const void *Decoder) { 3252 DecodeStatus S = MCDisassembler::Success; 3253 3254 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3255 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3256 3257 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3258 return MCDisassembler::Fail; 3259 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 3262 return S; 3263 } 3264 3265 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3266 uint64_t Address, const void *Decoder) { 3267 DecodeStatus S = MCDisassembler::Success; 3268 3269 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3270 unsigned imm = fieldFromInstruction(Val, 3, 5); 3271 3272 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3273 return MCDisassembler::Fail; 3274 Inst.addOperand(MCOperand::createImm(imm)); 3275 3276 return S; 3277 } 3278 3279 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3280 uint64_t Address, const void *Decoder) { 3281 unsigned imm = Val << 2; 3282 3283 Inst.addOperand(MCOperand::createImm(imm)); 3284 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3285 3286 return MCDisassembler::Success; 3287 } 3288 3289 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3290 uint64_t Address, const void *Decoder) { 3291 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3292 Inst.addOperand(MCOperand::createImm(Val)); 3293 3294 return MCDisassembler::Success; 3295 } 3296 3297 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3298 uint64_t Address, const void *Decoder) { 3299 DecodeStatus S = MCDisassembler::Success; 3300 3301 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3302 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3303 unsigned imm = fieldFromInstruction(Val, 0, 2); 3304 3305 // Thumb stores cannot use PC as dest register. 3306 switch (Inst.getOpcode()) { 3307 case ARM::t2STRHs: 3308 case ARM::t2STRBs: 3309 case ARM::t2STRs: 3310 if (Rn == 15) 3311 return MCDisassembler::Fail; 3312 default: 3313 break; 3314 } 3315 3316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3317 return MCDisassembler::Fail; 3318 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3319 return MCDisassembler::Fail; 3320 Inst.addOperand(MCOperand::createImm(imm)); 3321 3322 return S; 3323 } 3324 3325 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3326 uint64_t Address, const void *Decoder) { 3327 DecodeStatus S = MCDisassembler::Success; 3328 3329 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3330 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3331 3332 const FeatureBitset &featureBits = 3333 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3334 3335 bool hasMP = featureBits[ARM::FeatureMP]; 3336 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3337 3338 if (Rn == 15) { 3339 switch (Inst.getOpcode()) { 3340 case ARM::t2LDRBs: 3341 Inst.setOpcode(ARM::t2LDRBpci); 3342 break; 3343 case ARM::t2LDRHs: 3344 Inst.setOpcode(ARM::t2LDRHpci); 3345 break; 3346 case ARM::t2LDRSHs: 3347 Inst.setOpcode(ARM::t2LDRSHpci); 3348 break; 3349 case ARM::t2LDRSBs: 3350 Inst.setOpcode(ARM::t2LDRSBpci); 3351 break; 3352 case ARM::t2LDRs: 3353 Inst.setOpcode(ARM::t2LDRpci); 3354 break; 3355 case ARM::t2PLDs: 3356 Inst.setOpcode(ARM::t2PLDpci); 3357 break; 3358 case ARM::t2PLIs: 3359 Inst.setOpcode(ARM::t2PLIpci); 3360 break; 3361 default: 3362 return MCDisassembler::Fail; 3363 } 3364 3365 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3366 } 3367 3368 if (Rt == 15) { 3369 switch (Inst.getOpcode()) { 3370 case ARM::t2LDRSHs: 3371 return MCDisassembler::Fail; 3372 case ARM::t2LDRHs: 3373 Inst.setOpcode(ARM::t2PLDWs); 3374 break; 3375 case ARM::t2LDRSBs: 3376 Inst.setOpcode(ARM::t2PLIs); 3377 default: 3378 break; 3379 } 3380 } 3381 3382 switch (Inst.getOpcode()) { 3383 case ARM::t2PLDs: 3384 break; 3385 case ARM::t2PLIs: 3386 if (!hasV7Ops) 3387 return MCDisassembler::Fail; 3388 break; 3389 case ARM::t2PLDWs: 3390 if (!hasV7Ops || !hasMP) 3391 return MCDisassembler::Fail; 3392 break; 3393 default: 3394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3395 return MCDisassembler::Fail; 3396 } 3397 3398 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3399 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3400 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3401 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3402 return MCDisassembler::Fail; 3403 3404 return S; 3405 } 3406 3407 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3408 uint64_t Address, const void* Decoder) { 3409 DecodeStatus S = MCDisassembler::Success; 3410 3411 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3412 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3413 unsigned U = fieldFromInstruction(Insn, 9, 1); 3414 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3415 imm |= (U << 8); 3416 imm |= (Rn << 9); 3417 unsigned add = fieldFromInstruction(Insn, 9, 1); 3418 3419 const FeatureBitset &featureBits = 3420 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3421 3422 bool hasMP = featureBits[ARM::FeatureMP]; 3423 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3424 3425 if (Rn == 15) { 3426 switch (Inst.getOpcode()) { 3427 case ARM::t2LDRi8: 3428 Inst.setOpcode(ARM::t2LDRpci); 3429 break; 3430 case ARM::t2LDRBi8: 3431 Inst.setOpcode(ARM::t2LDRBpci); 3432 break; 3433 case ARM::t2LDRSBi8: 3434 Inst.setOpcode(ARM::t2LDRSBpci); 3435 break; 3436 case ARM::t2LDRHi8: 3437 Inst.setOpcode(ARM::t2LDRHpci); 3438 break; 3439 case ARM::t2LDRSHi8: 3440 Inst.setOpcode(ARM::t2LDRSHpci); 3441 break; 3442 case ARM::t2PLDi8: 3443 Inst.setOpcode(ARM::t2PLDpci); 3444 break; 3445 case ARM::t2PLIi8: 3446 Inst.setOpcode(ARM::t2PLIpci); 3447 break; 3448 default: 3449 return MCDisassembler::Fail; 3450 } 3451 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3452 } 3453 3454 if (Rt == 15) { 3455 switch (Inst.getOpcode()) { 3456 case ARM::t2LDRSHi8: 3457 return MCDisassembler::Fail; 3458 case ARM::t2LDRHi8: 3459 if (!add) 3460 Inst.setOpcode(ARM::t2PLDWi8); 3461 break; 3462 case ARM::t2LDRSBi8: 3463 Inst.setOpcode(ARM::t2PLIi8); 3464 break; 3465 default: 3466 break; 3467 } 3468 } 3469 3470 switch (Inst.getOpcode()) { 3471 case ARM::t2PLDi8: 3472 break; 3473 case ARM::t2PLIi8: 3474 if (!hasV7Ops) 3475 return MCDisassembler::Fail; 3476 break; 3477 case ARM::t2PLDWi8: 3478 if (!hasV7Ops || !hasMP) 3479 return MCDisassembler::Fail; 3480 break; 3481 default: 3482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3483 return MCDisassembler::Fail; 3484 } 3485 3486 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3487 return MCDisassembler::Fail; 3488 return S; 3489 } 3490 3491 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3492 uint64_t Address, const void* Decoder) { 3493 DecodeStatus S = MCDisassembler::Success; 3494 3495 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3496 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3497 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3498 imm |= (Rn << 13); 3499 3500 const FeatureBitset &featureBits = 3501 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3502 3503 bool hasMP = featureBits[ARM::FeatureMP]; 3504 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3505 3506 if (Rn == 15) { 3507 switch (Inst.getOpcode()) { 3508 case ARM::t2LDRi12: 3509 Inst.setOpcode(ARM::t2LDRpci); 3510 break; 3511 case ARM::t2LDRHi12: 3512 Inst.setOpcode(ARM::t2LDRHpci); 3513 break; 3514 case ARM::t2LDRSHi12: 3515 Inst.setOpcode(ARM::t2LDRSHpci); 3516 break; 3517 case ARM::t2LDRBi12: 3518 Inst.setOpcode(ARM::t2LDRBpci); 3519 break; 3520 case ARM::t2LDRSBi12: 3521 Inst.setOpcode(ARM::t2LDRSBpci); 3522 break; 3523 case ARM::t2PLDi12: 3524 Inst.setOpcode(ARM::t2PLDpci); 3525 break; 3526 case ARM::t2PLIi12: 3527 Inst.setOpcode(ARM::t2PLIpci); 3528 break; 3529 default: 3530 return MCDisassembler::Fail; 3531 } 3532 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3533 } 3534 3535 if (Rt == 15) { 3536 switch (Inst.getOpcode()) { 3537 case ARM::t2LDRSHi12: 3538 return MCDisassembler::Fail; 3539 case ARM::t2LDRHi12: 3540 Inst.setOpcode(ARM::t2PLDWi12); 3541 break; 3542 case ARM::t2LDRSBi12: 3543 Inst.setOpcode(ARM::t2PLIi12); 3544 break; 3545 default: 3546 break; 3547 } 3548 } 3549 3550 switch (Inst.getOpcode()) { 3551 case ARM::t2PLDi12: 3552 break; 3553 case ARM::t2PLIi12: 3554 if (!hasV7Ops) 3555 return MCDisassembler::Fail; 3556 break; 3557 case ARM::t2PLDWi12: 3558 if (!hasV7Ops || !hasMP) 3559 return MCDisassembler::Fail; 3560 break; 3561 default: 3562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 } 3565 3566 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3567 return MCDisassembler::Fail; 3568 return S; 3569 } 3570 3571 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3572 uint64_t Address, const void* Decoder) { 3573 DecodeStatus S = MCDisassembler::Success; 3574 3575 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3576 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3577 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3578 imm |= (Rn << 9); 3579 3580 if (Rn == 15) { 3581 switch (Inst.getOpcode()) { 3582 case ARM::t2LDRT: 3583 Inst.setOpcode(ARM::t2LDRpci); 3584 break; 3585 case ARM::t2LDRBT: 3586 Inst.setOpcode(ARM::t2LDRBpci); 3587 break; 3588 case ARM::t2LDRHT: 3589 Inst.setOpcode(ARM::t2LDRHpci); 3590 break; 3591 case ARM::t2LDRSBT: 3592 Inst.setOpcode(ARM::t2LDRSBpci); 3593 break; 3594 case ARM::t2LDRSHT: 3595 Inst.setOpcode(ARM::t2LDRSHpci); 3596 break; 3597 default: 3598 return MCDisassembler::Fail; 3599 } 3600 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3601 } 3602 3603 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3604 return MCDisassembler::Fail; 3605 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3606 return MCDisassembler::Fail; 3607 return S; 3608 } 3609 3610 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3611 uint64_t Address, const void* Decoder) { 3612 DecodeStatus S = MCDisassembler::Success; 3613 3614 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3615 unsigned U = fieldFromInstruction(Insn, 23, 1); 3616 int imm = fieldFromInstruction(Insn, 0, 12); 3617 3618 const FeatureBitset &featureBits = 3619 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3620 3621 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3622 3623 if (Rt == 15) { 3624 switch (Inst.getOpcode()) { 3625 case ARM::t2LDRBpci: 3626 case ARM::t2LDRHpci: 3627 Inst.setOpcode(ARM::t2PLDpci); 3628 break; 3629 case ARM::t2LDRSBpci: 3630 Inst.setOpcode(ARM::t2PLIpci); 3631 break; 3632 case ARM::t2LDRSHpci: 3633 return MCDisassembler::Fail; 3634 default: 3635 break; 3636 } 3637 } 3638 3639 switch(Inst.getOpcode()) { 3640 case ARM::t2PLDpci: 3641 break; 3642 case ARM::t2PLIpci: 3643 if (!hasV7Ops) 3644 return MCDisassembler::Fail; 3645 break; 3646 default: 3647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3648 return MCDisassembler::Fail; 3649 } 3650 3651 if (!U) { 3652 // Special case for #-0. 3653 if (imm == 0) 3654 imm = INT32_MIN; 3655 else 3656 imm = -imm; 3657 } 3658 Inst.addOperand(MCOperand::createImm(imm)); 3659 3660 return S; 3661 } 3662 3663 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3664 uint64_t Address, const void *Decoder) { 3665 if (Val == 0) 3666 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3667 else { 3668 int imm = Val & 0xFF; 3669 3670 if (!(Val & 0x100)) imm *= -1; 3671 Inst.addOperand(MCOperand::createImm(imm * 4)); 3672 } 3673 3674 return MCDisassembler::Success; 3675 } 3676 3677 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3678 uint64_t Address, const void *Decoder) { 3679 DecodeStatus S = MCDisassembler::Success; 3680 3681 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3682 unsigned imm = fieldFromInstruction(Val, 0, 9); 3683 3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3685 return MCDisassembler::Fail; 3686 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 3689 return S; 3690 } 3691 3692 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3693 uint64_t Address, const void *Decoder) { 3694 DecodeStatus S = MCDisassembler::Success; 3695 3696 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3697 unsigned imm = fieldFromInstruction(Val, 0, 8); 3698 3699 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3700 return MCDisassembler::Fail; 3701 3702 Inst.addOperand(MCOperand::createImm(imm)); 3703 3704 return S; 3705 } 3706 3707 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3708 uint64_t Address, const void *Decoder) { 3709 int imm = Val & 0xFF; 3710 if (Val == 0) 3711 imm = INT32_MIN; 3712 else if (!(Val & 0x100)) 3713 imm *= -1; 3714 Inst.addOperand(MCOperand::createImm(imm)); 3715 3716 return MCDisassembler::Success; 3717 } 3718 3719 3720 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3721 uint64_t Address, const void *Decoder) { 3722 DecodeStatus S = MCDisassembler::Success; 3723 3724 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3725 unsigned imm = fieldFromInstruction(Val, 0, 9); 3726 3727 // Thumb stores cannot use PC as dest register. 3728 switch (Inst.getOpcode()) { 3729 case ARM::t2STRT: 3730 case ARM::t2STRBT: 3731 case ARM::t2STRHT: 3732 case ARM::t2STRi8: 3733 case ARM::t2STRHi8: 3734 case ARM::t2STRBi8: 3735 if (Rn == 15) 3736 return MCDisassembler::Fail; 3737 break; 3738 default: 3739 break; 3740 } 3741 3742 // Some instructions always use an additive offset. 3743 switch (Inst.getOpcode()) { 3744 case ARM::t2LDRT: 3745 case ARM::t2LDRBT: 3746 case ARM::t2LDRHT: 3747 case ARM::t2LDRSBT: 3748 case ARM::t2LDRSHT: 3749 case ARM::t2STRT: 3750 case ARM::t2STRBT: 3751 case ARM::t2STRHT: 3752 imm |= 0x100; 3753 break; 3754 default: 3755 break; 3756 } 3757 3758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3759 return MCDisassembler::Fail; 3760 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3761 return MCDisassembler::Fail; 3762 3763 return S; 3764 } 3765 3766 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3767 uint64_t Address, const void *Decoder) { 3768 DecodeStatus S = MCDisassembler::Success; 3769 3770 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3771 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3772 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3773 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3774 addr |= Rn << 9; 3775 unsigned load = fieldFromInstruction(Insn, 20, 1); 3776 3777 if (Rn == 15) { 3778 switch (Inst.getOpcode()) { 3779 case ARM::t2LDR_PRE: 3780 case ARM::t2LDR_POST: 3781 Inst.setOpcode(ARM::t2LDRpci); 3782 break; 3783 case ARM::t2LDRB_PRE: 3784 case ARM::t2LDRB_POST: 3785 Inst.setOpcode(ARM::t2LDRBpci); 3786 break; 3787 case ARM::t2LDRH_PRE: 3788 case ARM::t2LDRH_POST: 3789 Inst.setOpcode(ARM::t2LDRHpci); 3790 break; 3791 case ARM::t2LDRSB_PRE: 3792 case ARM::t2LDRSB_POST: 3793 if (Rt == 15) 3794 Inst.setOpcode(ARM::t2PLIpci); 3795 else 3796 Inst.setOpcode(ARM::t2LDRSBpci); 3797 break; 3798 case ARM::t2LDRSH_PRE: 3799 case ARM::t2LDRSH_POST: 3800 Inst.setOpcode(ARM::t2LDRSHpci); 3801 break; 3802 default: 3803 return MCDisassembler::Fail; 3804 } 3805 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3806 } 3807 3808 if (!load) { 3809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3810 return MCDisassembler::Fail; 3811 } 3812 3813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3814 return MCDisassembler::Fail; 3815 3816 if (load) { 3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3818 return MCDisassembler::Fail; 3819 } 3820 3821 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3822 return MCDisassembler::Fail; 3823 3824 return S; 3825 } 3826 3827 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3828 uint64_t Address, const void *Decoder) { 3829 DecodeStatus S = MCDisassembler::Success; 3830 3831 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3832 unsigned imm = fieldFromInstruction(Val, 0, 12); 3833 3834 // Thumb stores cannot use PC as dest register. 3835 switch (Inst.getOpcode()) { 3836 case ARM::t2STRi12: 3837 case ARM::t2STRBi12: 3838 case ARM::t2STRHi12: 3839 if (Rn == 15) 3840 return MCDisassembler::Fail; 3841 default: 3842 break; 3843 } 3844 3845 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3846 return MCDisassembler::Fail; 3847 Inst.addOperand(MCOperand::createImm(imm)); 3848 3849 return S; 3850 } 3851 3852 3853 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3854 uint64_t Address, const void *Decoder) { 3855 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3856 3857 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3858 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3859 Inst.addOperand(MCOperand::createImm(imm)); 3860 3861 return MCDisassembler::Success; 3862 } 3863 3864 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3865 uint64_t Address, const void *Decoder) { 3866 DecodeStatus S = MCDisassembler::Success; 3867 3868 if (Inst.getOpcode() == ARM::tADDrSP) { 3869 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3870 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3871 3872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3873 return MCDisassembler::Fail; 3874 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3876 return MCDisassembler::Fail; 3877 } else if (Inst.getOpcode() == ARM::tADDspr) { 3878 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3879 3880 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3881 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3883 return MCDisassembler::Fail; 3884 } 3885 3886 return S; 3887 } 3888 3889 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3890 uint64_t Address, const void *Decoder) { 3891 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3892 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3893 3894 Inst.addOperand(MCOperand::createImm(imod)); 3895 Inst.addOperand(MCOperand::createImm(flags)); 3896 3897 return MCDisassembler::Success; 3898 } 3899 3900 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3901 uint64_t Address, const void *Decoder) { 3902 DecodeStatus S = MCDisassembler::Success; 3903 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3904 unsigned add = fieldFromInstruction(Insn, 4, 1); 3905 3906 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3907 return MCDisassembler::Fail; 3908 Inst.addOperand(MCOperand::createImm(add)); 3909 3910 return S; 3911 } 3912 3913 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3914 uint64_t Address, const void *Decoder) { 3915 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3916 // Note only one trailing zero not two. Also the J1 and J2 values are from 3917 // the encoded instruction. So here change to I1 and I2 values via: 3918 // I1 = NOT(J1 EOR S); 3919 // I2 = NOT(J2 EOR S); 3920 // and build the imm32 with two trailing zeros as documented: 3921 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3922 unsigned S = (Val >> 23) & 1; 3923 unsigned J1 = (Val >> 22) & 1; 3924 unsigned J2 = (Val >> 21) & 1; 3925 unsigned I1 = !(J1 ^ S); 3926 unsigned I2 = !(J2 ^ S); 3927 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3928 int imm32 = SignExtend32<25>(tmp << 1); 3929 3930 if (!tryAddingSymbolicOperand(Address, 3931 (Address & ~2u) + imm32 + 4, 3932 true, 4, Inst, Decoder)) 3933 Inst.addOperand(MCOperand::createImm(imm32)); 3934 return MCDisassembler::Success; 3935 } 3936 3937 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3938 uint64_t Address, const void *Decoder) { 3939 if (Val == 0xA || Val == 0xB) 3940 return MCDisassembler::Fail; 3941 3942 const FeatureBitset &featureBits = 3943 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3944 3945 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 3946 return MCDisassembler::Fail; 3947 3948 Inst.addOperand(MCOperand::createImm(Val)); 3949 return MCDisassembler::Success; 3950 } 3951 3952 static DecodeStatus 3953 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3954 uint64_t Address, const void *Decoder) { 3955 DecodeStatus S = MCDisassembler::Success; 3956 3957 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3958 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3959 3960 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3961 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3962 return MCDisassembler::Fail; 3963 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3964 return MCDisassembler::Fail; 3965 return S; 3966 } 3967 3968 static DecodeStatus 3969 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3970 uint64_t Address, const void *Decoder) { 3971 DecodeStatus S = MCDisassembler::Success; 3972 3973 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3974 if (pred == 0xE || pred == 0xF) { 3975 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3976 switch (opc) { 3977 default: 3978 return MCDisassembler::Fail; 3979 case 0xf3bf8f4: 3980 Inst.setOpcode(ARM::t2DSB); 3981 break; 3982 case 0xf3bf8f5: 3983 Inst.setOpcode(ARM::t2DMB); 3984 break; 3985 case 0xf3bf8f6: 3986 Inst.setOpcode(ARM::t2ISB); 3987 break; 3988 } 3989 3990 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3991 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3992 } 3993 3994 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3995 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3996 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3997 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3998 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3999 4000 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4001 return MCDisassembler::Fail; 4002 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4003 return MCDisassembler::Fail; 4004 4005 return S; 4006 } 4007 4008 // Decode a shifted immediate operand. These basically consist 4009 // of an 8-bit value, and a 4-bit directive that specifies either 4010 // a splat operation or a rotation. 4011 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4012 uint64_t Address, const void *Decoder) { 4013 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4014 if (ctrl == 0) { 4015 unsigned byte = fieldFromInstruction(Val, 8, 2); 4016 unsigned imm = fieldFromInstruction(Val, 0, 8); 4017 switch (byte) { 4018 case 0: 4019 Inst.addOperand(MCOperand::createImm(imm)); 4020 break; 4021 case 1: 4022 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4023 break; 4024 case 2: 4025 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4026 break; 4027 case 3: 4028 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4029 (imm << 8) | imm)); 4030 break; 4031 } 4032 } else { 4033 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4034 unsigned rot = fieldFromInstruction(Val, 7, 5); 4035 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4036 Inst.addOperand(MCOperand::createImm(imm)); 4037 } 4038 4039 return MCDisassembler::Success; 4040 } 4041 4042 static DecodeStatus 4043 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4044 uint64_t Address, const void *Decoder){ 4045 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4046 true, 2, Inst, Decoder)) 4047 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4048 return MCDisassembler::Success; 4049 } 4050 4051 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4052 uint64_t Address, const void *Decoder){ 4053 // Val is passed in as S:J1:J2:imm10:imm11 4054 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4055 // the encoded instruction. So here change to I1 and I2 values via: 4056 // I1 = NOT(J1 EOR S); 4057 // I2 = NOT(J2 EOR S); 4058 // and build the imm32 with one trailing zero as documented: 4059 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4060 unsigned S = (Val >> 23) & 1; 4061 unsigned J1 = (Val >> 22) & 1; 4062 unsigned J2 = (Val >> 21) & 1; 4063 unsigned I1 = !(J1 ^ S); 4064 unsigned I2 = !(J2 ^ S); 4065 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4066 int imm32 = SignExtend32<25>(tmp << 1); 4067 4068 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4069 true, 4, Inst, Decoder)) 4070 Inst.addOperand(MCOperand::createImm(imm32)); 4071 return MCDisassembler::Success; 4072 } 4073 4074 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4075 uint64_t Address, const void *Decoder) { 4076 if (Val & ~0xf) 4077 return MCDisassembler::Fail; 4078 4079 Inst.addOperand(MCOperand::createImm(Val)); 4080 return MCDisassembler::Success; 4081 } 4082 4083 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4084 uint64_t Address, const void *Decoder) { 4085 if (Val & ~0xf) 4086 return MCDisassembler::Fail; 4087 4088 Inst.addOperand(MCOperand::createImm(Val)); 4089 return MCDisassembler::Success; 4090 } 4091 4092 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4093 uint64_t Address, const void *Decoder) { 4094 DecodeStatus S = MCDisassembler::Success; 4095 const FeatureBitset &FeatureBits = 4096 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4097 4098 if (FeatureBits[ARM::FeatureMClass]) { 4099 unsigned ValLow = Val & 0xff; 4100 4101 // Validate the SYSm value first. 4102 switch (ValLow) { 4103 case 0: // apsr 4104 case 1: // iapsr 4105 case 2: // eapsr 4106 case 3: // xpsr 4107 case 5: // ipsr 4108 case 6: // epsr 4109 case 7: // iepsr 4110 case 8: // msp 4111 case 9: // psp 4112 case 16: // primask 4113 case 20: // control 4114 break; 4115 case 17: // basepri 4116 case 18: // basepri_max 4117 case 19: // faultmask 4118 if (!(FeatureBits[ARM::HasV7Ops])) 4119 // Values basepri, basepri_max and faultmask are only valid for v7m. 4120 return MCDisassembler::Fail; 4121 break; 4122 case 0x8a: // msplim_ns 4123 case 0x8b: // psplim_ns 4124 case 0x91: // basepri_ns 4125 case 0x92: // basepri_max_ns 4126 case 0x93: // faultmask_ns 4127 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4128 return MCDisassembler::Fail; 4129 // fall through 4130 case 10: // msplim 4131 case 11: // psplim 4132 case 0x88: // msp_ns 4133 case 0x89: // psp_ns 4134 case 0x90: // primask_ns 4135 case 0x94: // control_ns 4136 case 0x98: // sp_ns 4137 if (!(FeatureBits[ARM::Feature8MSecExt])) 4138 return MCDisassembler::Fail; 4139 break; 4140 default: 4141 return MCDisassembler::Fail; 4142 } 4143 4144 if (Inst.getOpcode() == ARM::t2MSR_M) { 4145 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4146 if (!(FeatureBits[ARM::HasV7Ops])) { 4147 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4148 // unpredictable. 4149 if (Mask != 2) 4150 S = MCDisassembler::SoftFail; 4151 } 4152 else { 4153 // The ARMv7-M architecture stores an additional 2-bit mask value in 4154 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4155 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4156 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4157 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4158 // only if the processor includes the DSP extension. 4159 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4160 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4161 S = MCDisassembler::SoftFail; 4162 } 4163 } 4164 } else { 4165 // A/R class 4166 if (Val == 0) 4167 return MCDisassembler::Fail; 4168 } 4169 Inst.addOperand(MCOperand::createImm(Val)); 4170 return S; 4171 } 4172 4173 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4174 uint64_t Address, const void *Decoder) { 4175 4176 unsigned R = fieldFromInstruction(Val, 5, 1); 4177 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4178 4179 // The table of encodings for these banked registers comes from B9.2.3 of the 4180 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4181 // neater. So by fiat, these values are UNPREDICTABLE: 4182 if (!R) { 4183 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || 4184 SysM == 0x1a || SysM == 0x1b) 4185 return MCDisassembler::SoftFail; 4186 } else { 4187 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && 4188 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) 4189 return MCDisassembler::SoftFail; 4190 } 4191 4192 Inst.addOperand(MCOperand::createImm(Val)); 4193 return MCDisassembler::Success; 4194 } 4195 4196 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4197 uint64_t Address, const void *Decoder) { 4198 DecodeStatus S = MCDisassembler::Success; 4199 4200 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4201 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4202 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4203 4204 if (Rn == 0xF) 4205 S = MCDisassembler::SoftFail; 4206 4207 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4208 return MCDisassembler::Fail; 4209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4210 return MCDisassembler::Fail; 4211 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4212 return MCDisassembler::Fail; 4213 4214 return S; 4215 } 4216 4217 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4218 uint64_t Address, const void *Decoder){ 4219 DecodeStatus S = MCDisassembler::Success; 4220 4221 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4222 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4223 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4224 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4225 4226 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4227 return MCDisassembler::Fail; 4228 4229 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4230 S = MCDisassembler::SoftFail; 4231 4232 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4233 return MCDisassembler::Fail; 4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4237 return MCDisassembler::Fail; 4238 4239 return S; 4240 } 4241 4242 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4243 uint64_t Address, const void *Decoder) { 4244 DecodeStatus S = MCDisassembler::Success; 4245 4246 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4247 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4248 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4249 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4250 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4251 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4252 4253 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4254 4255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4256 return MCDisassembler::Fail; 4257 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4258 return MCDisassembler::Fail; 4259 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4260 return MCDisassembler::Fail; 4261 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4262 return MCDisassembler::Fail; 4263 4264 return S; 4265 } 4266 4267 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4268 uint64_t Address, const void *Decoder) { 4269 DecodeStatus S = MCDisassembler::Success; 4270 4271 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4272 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4273 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4274 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4275 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4276 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4277 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4278 4279 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4280 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4281 4282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4283 return MCDisassembler::Fail; 4284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4285 return MCDisassembler::Fail; 4286 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4287 return MCDisassembler::Fail; 4288 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4289 return MCDisassembler::Fail; 4290 4291 return S; 4292 } 4293 4294 4295 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4296 uint64_t Address, const void *Decoder) { 4297 DecodeStatus S = MCDisassembler::Success; 4298 4299 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4300 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4301 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4302 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4303 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4304 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4305 4306 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4307 4308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4309 return MCDisassembler::Fail; 4310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4313 return MCDisassembler::Fail; 4314 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4315 return MCDisassembler::Fail; 4316 4317 return S; 4318 } 4319 4320 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4321 uint64_t Address, const void *Decoder) { 4322 DecodeStatus S = MCDisassembler::Success; 4323 4324 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4325 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4326 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4327 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4328 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4329 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4330 4331 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4332 4333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4334 return MCDisassembler::Fail; 4335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4336 return MCDisassembler::Fail; 4337 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4338 return MCDisassembler::Fail; 4339 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4340 return MCDisassembler::Fail; 4341 4342 return S; 4343 } 4344 4345 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4346 uint64_t Address, const void *Decoder) { 4347 DecodeStatus S = MCDisassembler::Success; 4348 4349 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4350 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4351 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4352 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4353 unsigned size = fieldFromInstruction(Insn, 10, 2); 4354 4355 unsigned align = 0; 4356 unsigned index = 0; 4357 switch (size) { 4358 default: 4359 return MCDisassembler::Fail; 4360 case 0: 4361 if (fieldFromInstruction(Insn, 4, 1)) 4362 return MCDisassembler::Fail; // UNDEFINED 4363 index = fieldFromInstruction(Insn, 5, 3); 4364 break; 4365 case 1: 4366 if (fieldFromInstruction(Insn, 5, 1)) 4367 return MCDisassembler::Fail; // UNDEFINED 4368 index = fieldFromInstruction(Insn, 6, 2); 4369 if (fieldFromInstruction(Insn, 4, 1)) 4370 align = 2; 4371 break; 4372 case 2: 4373 if (fieldFromInstruction(Insn, 6, 1)) 4374 return MCDisassembler::Fail; // UNDEFINED 4375 index = fieldFromInstruction(Insn, 7, 1); 4376 4377 switch (fieldFromInstruction(Insn, 4, 2)) { 4378 case 0 : 4379 align = 0; break; 4380 case 3: 4381 align = 4; break; 4382 default: 4383 return MCDisassembler::Fail; 4384 } 4385 break; 4386 } 4387 4388 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4389 return MCDisassembler::Fail; 4390 if (Rm != 0xF) { // Writeback 4391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4392 return MCDisassembler::Fail; 4393 } 4394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4395 return MCDisassembler::Fail; 4396 Inst.addOperand(MCOperand::createImm(align)); 4397 if (Rm != 0xF) { 4398 if (Rm != 0xD) { 4399 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4400 return MCDisassembler::Fail; 4401 } else 4402 Inst.addOperand(MCOperand::createReg(0)); 4403 } 4404 4405 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4406 return MCDisassembler::Fail; 4407 Inst.addOperand(MCOperand::createImm(index)); 4408 4409 return S; 4410 } 4411 4412 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4413 uint64_t Address, const void *Decoder) { 4414 DecodeStatus S = MCDisassembler::Success; 4415 4416 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4417 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4418 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4419 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4420 unsigned size = fieldFromInstruction(Insn, 10, 2); 4421 4422 unsigned align = 0; 4423 unsigned index = 0; 4424 switch (size) { 4425 default: 4426 return MCDisassembler::Fail; 4427 case 0: 4428 if (fieldFromInstruction(Insn, 4, 1)) 4429 return MCDisassembler::Fail; // UNDEFINED 4430 index = fieldFromInstruction(Insn, 5, 3); 4431 break; 4432 case 1: 4433 if (fieldFromInstruction(Insn, 5, 1)) 4434 return MCDisassembler::Fail; // UNDEFINED 4435 index = fieldFromInstruction(Insn, 6, 2); 4436 if (fieldFromInstruction(Insn, 4, 1)) 4437 align = 2; 4438 break; 4439 case 2: 4440 if (fieldFromInstruction(Insn, 6, 1)) 4441 return MCDisassembler::Fail; // UNDEFINED 4442 index = fieldFromInstruction(Insn, 7, 1); 4443 4444 switch (fieldFromInstruction(Insn, 4, 2)) { 4445 case 0: 4446 align = 0; break; 4447 case 3: 4448 align = 4; break; 4449 default: 4450 return MCDisassembler::Fail; 4451 } 4452 break; 4453 } 4454 4455 if (Rm != 0xF) { // Writeback 4456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4457 return MCDisassembler::Fail; 4458 } 4459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4460 return MCDisassembler::Fail; 4461 Inst.addOperand(MCOperand::createImm(align)); 4462 if (Rm != 0xF) { 4463 if (Rm != 0xD) { 4464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4465 return MCDisassembler::Fail; 4466 } else 4467 Inst.addOperand(MCOperand::createReg(0)); 4468 } 4469 4470 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4471 return MCDisassembler::Fail; 4472 Inst.addOperand(MCOperand::createImm(index)); 4473 4474 return S; 4475 } 4476 4477 4478 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4479 uint64_t Address, const void *Decoder) { 4480 DecodeStatus S = MCDisassembler::Success; 4481 4482 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4483 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4484 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4485 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4486 unsigned size = fieldFromInstruction(Insn, 10, 2); 4487 4488 unsigned align = 0; 4489 unsigned index = 0; 4490 unsigned inc = 1; 4491 switch (size) { 4492 default: 4493 return MCDisassembler::Fail; 4494 case 0: 4495 index = fieldFromInstruction(Insn, 5, 3); 4496 if (fieldFromInstruction(Insn, 4, 1)) 4497 align = 2; 4498 break; 4499 case 1: 4500 index = fieldFromInstruction(Insn, 6, 2); 4501 if (fieldFromInstruction(Insn, 4, 1)) 4502 align = 4; 4503 if (fieldFromInstruction(Insn, 5, 1)) 4504 inc = 2; 4505 break; 4506 case 2: 4507 if (fieldFromInstruction(Insn, 5, 1)) 4508 return MCDisassembler::Fail; // UNDEFINED 4509 index = fieldFromInstruction(Insn, 7, 1); 4510 if (fieldFromInstruction(Insn, 4, 1) != 0) 4511 align = 8; 4512 if (fieldFromInstruction(Insn, 6, 1)) 4513 inc = 2; 4514 break; 4515 } 4516 4517 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4518 return MCDisassembler::Fail; 4519 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4520 return MCDisassembler::Fail; 4521 if (Rm != 0xF) { // Writeback 4522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4523 return MCDisassembler::Fail; 4524 } 4525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4526 return MCDisassembler::Fail; 4527 Inst.addOperand(MCOperand::createImm(align)); 4528 if (Rm != 0xF) { 4529 if (Rm != 0xD) { 4530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4531 return MCDisassembler::Fail; 4532 } else 4533 Inst.addOperand(MCOperand::createReg(0)); 4534 } 4535 4536 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4537 return MCDisassembler::Fail; 4538 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4539 return MCDisassembler::Fail; 4540 Inst.addOperand(MCOperand::createImm(index)); 4541 4542 return S; 4543 } 4544 4545 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4546 uint64_t Address, const void *Decoder) { 4547 DecodeStatus S = MCDisassembler::Success; 4548 4549 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4550 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4551 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4552 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4553 unsigned size = fieldFromInstruction(Insn, 10, 2); 4554 4555 unsigned align = 0; 4556 unsigned index = 0; 4557 unsigned inc = 1; 4558 switch (size) { 4559 default: 4560 return MCDisassembler::Fail; 4561 case 0: 4562 index = fieldFromInstruction(Insn, 5, 3); 4563 if (fieldFromInstruction(Insn, 4, 1)) 4564 align = 2; 4565 break; 4566 case 1: 4567 index = fieldFromInstruction(Insn, 6, 2); 4568 if (fieldFromInstruction(Insn, 4, 1)) 4569 align = 4; 4570 if (fieldFromInstruction(Insn, 5, 1)) 4571 inc = 2; 4572 break; 4573 case 2: 4574 if (fieldFromInstruction(Insn, 5, 1)) 4575 return MCDisassembler::Fail; // UNDEFINED 4576 index = fieldFromInstruction(Insn, 7, 1); 4577 if (fieldFromInstruction(Insn, 4, 1) != 0) 4578 align = 8; 4579 if (fieldFromInstruction(Insn, 6, 1)) 4580 inc = 2; 4581 break; 4582 } 4583 4584 if (Rm != 0xF) { // Writeback 4585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4586 return MCDisassembler::Fail; 4587 } 4588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4589 return MCDisassembler::Fail; 4590 Inst.addOperand(MCOperand::createImm(align)); 4591 if (Rm != 0xF) { 4592 if (Rm != 0xD) { 4593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4594 return MCDisassembler::Fail; 4595 } else 4596 Inst.addOperand(MCOperand::createReg(0)); 4597 } 4598 4599 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4600 return MCDisassembler::Fail; 4601 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4602 return MCDisassembler::Fail; 4603 Inst.addOperand(MCOperand::createImm(index)); 4604 4605 return S; 4606 } 4607 4608 4609 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4610 uint64_t Address, const void *Decoder) { 4611 DecodeStatus S = MCDisassembler::Success; 4612 4613 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4614 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4615 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4616 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4617 unsigned size = fieldFromInstruction(Insn, 10, 2); 4618 4619 unsigned align = 0; 4620 unsigned index = 0; 4621 unsigned inc = 1; 4622 switch (size) { 4623 default: 4624 return MCDisassembler::Fail; 4625 case 0: 4626 if (fieldFromInstruction(Insn, 4, 1)) 4627 return MCDisassembler::Fail; // UNDEFINED 4628 index = fieldFromInstruction(Insn, 5, 3); 4629 break; 4630 case 1: 4631 if (fieldFromInstruction(Insn, 4, 1)) 4632 return MCDisassembler::Fail; // UNDEFINED 4633 index = fieldFromInstruction(Insn, 6, 2); 4634 if (fieldFromInstruction(Insn, 5, 1)) 4635 inc = 2; 4636 break; 4637 case 2: 4638 if (fieldFromInstruction(Insn, 4, 2)) 4639 return MCDisassembler::Fail; // UNDEFINED 4640 index = fieldFromInstruction(Insn, 7, 1); 4641 if (fieldFromInstruction(Insn, 6, 1)) 4642 inc = 2; 4643 break; 4644 } 4645 4646 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4647 return MCDisassembler::Fail; 4648 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4649 return MCDisassembler::Fail; 4650 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4651 return MCDisassembler::Fail; 4652 4653 if (Rm != 0xF) { // Writeback 4654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4655 return MCDisassembler::Fail; 4656 } 4657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4658 return MCDisassembler::Fail; 4659 Inst.addOperand(MCOperand::createImm(align)); 4660 if (Rm != 0xF) { 4661 if (Rm != 0xD) { 4662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4663 return MCDisassembler::Fail; 4664 } else 4665 Inst.addOperand(MCOperand::createReg(0)); 4666 } 4667 4668 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4669 return MCDisassembler::Fail; 4670 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4671 return MCDisassembler::Fail; 4672 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4673 return MCDisassembler::Fail; 4674 Inst.addOperand(MCOperand::createImm(index)); 4675 4676 return S; 4677 } 4678 4679 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4680 uint64_t Address, const void *Decoder) { 4681 DecodeStatus S = MCDisassembler::Success; 4682 4683 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4684 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4685 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4686 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4687 unsigned size = fieldFromInstruction(Insn, 10, 2); 4688 4689 unsigned align = 0; 4690 unsigned index = 0; 4691 unsigned inc = 1; 4692 switch (size) { 4693 default: 4694 return MCDisassembler::Fail; 4695 case 0: 4696 if (fieldFromInstruction(Insn, 4, 1)) 4697 return MCDisassembler::Fail; // UNDEFINED 4698 index = fieldFromInstruction(Insn, 5, 3); 4699 break; 4700 case 1: 4701 if (fieldFromInstruction(Insn, 4, 1)) 4702 return MCDisassembler::Fail; // UNDEFINED 4703 index = fieldFromInstruction(Insn, 6, 2); 4704 if (fieldFromInstruction(Insn, 5, 1)) 4705 inc = 2; 4706 break; 4707 case 2: 4708 if (fieldFromInstruction(Insn, 4, 2)) 4709 return MCDisassembler::Fail; // UNDEFINED 4710 index = fieldFromInstruction(Insn, 7, 1); 4711 if (fieldFromInstruction(Insn, 6, 1)) 4712 inc = 2; 4713 break; 4714 } 4715 4716 if (Rm != 0xF) { // Writeback 4717 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4718 return MCDisassembler::Fail; 4719 } 4720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4721 return MCDisassembler::Fail; 4722 Inst.addOperand(MCOperand::createImm(align)); 4723 if (Rm != 0xF) { 4724 if (Rm != 0xD) { 4725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4726 return MCDisassembler::Fail; 4727 } else 4728 Inst.addOperand(MCOperand::createReg(0)); 4729 } 4730 4731 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4732 return MCDisassembler::Fail; 4733 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4734 return MCDisassembler::Fail; 4735 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4736 return MCDisassembler::Fail; 4737 Inst.addOperand(MCOperand::createImm(index)); 4738 4739 return S; 4740 } 4741 4742 4743 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4744 uint64_t Address, const void *Decoder) { 4745 DecodeStatus S = MCDisassembler::Success; 4746 4747 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4748 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4749 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4750 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4751 unsigned size = fieldFromInstruction(Insn, 10, 2); 4752 4753 unsigned align = 0; 4754 unsigned index = 0; 4755 unsigned inc = 1; 4756 switch (size) { 4757 default: 4758 return MCDisassembler::Fail; 4759 case 0: 4760 if (fieldFromInstruction(Insn, 4, 1)) 4761 align = 4; 4762 index = fieldFromInstruction(Insn, 5, 3); 4763 break; 4764 case 1: 4765 if (fieldFromInstruction(Insn, 4, 1)) 4766 align = 8; 4767 index = fieldFromInstruction(Insn, 6, 2); 4768 if (fieldFromInstruction(Insn, 5, 1)) 4769 inc = 2; 4770 break; 4771 case 2: 4772 switch (fieldFromInstruction(Insn, 4, 2)) { 4773 case 0: 4774 align = 0; break; 4775 case 3: 4776 return MCDisassembler::Fail; 4777 default: 4778 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4779 } 4780 4781 index = fieldFromInstruction(Insn, 7, 1); 4782 if (fieldFromInstruction(Insn, 6, 1)) 4783 inc = 2; 4784 break; 4785 } 4786 4787 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4788 return MCDisassembler::Fail; 4789 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4790 return MCDisassembler::Fail; 4791 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4792 return MCDisassembler::Fail; 4793 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4794 return MCDisassembler::Fail; 4795 4796 if (Rm != 0xF) { // Writeback 4797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4798 return MCDisassembler::Fail; 4799 } 4800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4801 return MCDisassembler::Fail; 4802 Inst.addOperand(MCOperand::createImm(align)); 4803 if (Rm != 0xF) { 4804 if (Rm != 0xD) { 4805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4806 return MCDisassembler::Fail; 4807 } else 4808 Inst.addOperand(MCOperand::createReg(0)); 4809 } 4810 4811 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4812 return MCDisassembler::Fail; 4813 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4814 return MCDisassembler::Fail; 4815 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4816 return MCDisassembler::Fail; 4817 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4818 return MCDisassembler::Fail; 4819 Inst.addOperand(MCOperand::createImm(index)); 4820 4821 return S; 4822 } 4823 4824 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4825 uint64_t Address, const void *Decoder) { 4826 DecodeStatus S = MCDisassembler::Success; 4827 4828 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4829 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4830 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4831 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4832 unsigned size = fieldFromInstruction(Insn, 10, 2); 4833 4834 unsigned align = 0; 4835 unsigned index = 0; 4836 unsigned inc = 1; 4837 switch (size) { 4838 default: 4839 return MCDisassembler::Fail; 4840 case 0: 4841 if (fieldFromInstruction(Insn, 4, 1)) 4842 align = 4; 4843 index = fieldFromInstruction(Insn, 5, 3); 4844 break; 4845 case 1: 4846 if (fieldFromInstruction(Insn, 4, 1)) 4847 align = 8; 4848 index = fieldFromInstruction(Insn, 6, 2); 4849 if (fieldFromInstruction(Insn, 5, 1)) 4850 inc = 2; 4851 break; 4852 case 2: 4853 switch (fieldFromInstruction(Insn, 4, 2)) { 4854 case 0: 4855 align = 0; break; 4856 case 3: 4857 return MCDisassembler::Fail; 4858 default: 4859 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4860 } 4861 4862 index = fieldFromInstruction(Insn, 7, 1); 4863 if (fieldFromInstruction(Insn, 6, 1)) 4864 inc = 2; 4865 break; 4866 } 4867 4868 if (Rm != 0xF) { // Writeback 4869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4870 return MCDisassembler::Fail; 4871 } 4872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4873 return MCDisassembler::Fail; 4874 Inst.addOperand(MCOperand::createImm(align)); 4875 if (Rm != 0xF) { 4876 if (Rm != 0xD) { 4877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4878 return MCDisassembler::Fail; 4879 } else 4880 Inst.addOperand(MCOperand::createReg(0)); 4881 } 4882 4883 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4884 return MCDisassembler::Fail; 4885 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4886 return MCDisassembler::Fail; 4887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4888 return MCDisassembler::Fail; 4889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4890 return MCDisassembler::Fail; 4891 Inst.addOperand(MCOperand::createImm(index)); 4892 4893 return S; 4894 } 4895 4896 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4897 uint64_t Address, const void *Decoder) { 4898 DecodeStatus S = MCDisassembler::Success; 4899 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4900 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4901 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4902 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4903 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4904 4905 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4906 S = MCDisassembler::SoftFail; 4907 4908 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4909 return MCDisassembler::Fail; 4910 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4911 return MCDisassembler::Fail; 4912 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4913 return MCDisassembler::Fail; 4914 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4915 return MCDisassembler::Fail; 4916 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4917 return MCDisassembler::Fail; 4918 4919 return S; 4920 } 4921 4922 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4923 uint64_t Address, const void *Decoder) { 4924 DecodeStatus S = MCDisassembler::Success; 4925 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4926 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4927 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4928 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4929 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4930 4931 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4932 S = MCDisassembler::SoftFail; 4933 4934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4935 return MCDisassembler::Fail; 4936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4937 return MCDisassembler::Fail; 4938 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4939 return MCDisassembler::Fail; 4940 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4941 return MCDisassembler::Fail; 4942 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4943 return MCDisassembler::Fail; 4944 4945 return S; 4946 } 4947 4948 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4949 uint64_t Address, const void *Decoder) { 4950 DecodeStatus S = MCDisassembler::Success; 4951 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4952 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4953 4954 if (pred == 0xF) { 4955 pred = 0xE; 4956 S = MCDisassembler::SoftFail; 4957 } 4958 4959 if (mask == 0x0) 4960 return MCDisassembler::Fail; 4961 4962 Inst.addOperand(MCOperand::createImm(pred)); 4963 Inst.addOperand(MCOperand::createImm(mask)); 4964 return S; 4965 } 4966 4967 static DecodeStatus 4968 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4969 uint64_t Address, const void *Decoder) { 4970 DecodeStatus S = MCDisassembler::Success; 4971 4972 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4973 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4974 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4975 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4976 unsigned W = fieldFromInstruction(Insn, 21, 1); 4977 unsigned U = fieldFromInstruction(Insn, 23, 1); 4978 unsigned P = fieldFromInstruction(Insn, 24, 1); 4979 bool writeback = (W == 1) | (P == 0); 4980 4981 addr |= (U << 8) | (Rn << 9); 4982 4983 if (writeback && (Rn == Rt || Rn == Rt2)) 4984 Check(S, MCDisassembler::SoftFail); 4985 if (Rt == Rt2) 4986 Check(S, MCDisassembler::SoftFail); 4987 4988 // Rt 4989 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4990 return MCDisassembler::Fail; 4991 // Rt2 4992 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4993 return MCDisassembler::Fail; 4994 // Writeback operand 4995 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4996 return MCDisassembler::Fail; 4997 // addr 4998 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4999 return MCDisassembler::Fail; 5000 5001 return S; 5002 } 5003 5004 static DecodeStatus 5005 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5006 uint64_t Address, const void *Decoder) { 5007 DecodeStatus S = MCDisassembler::Success; 5008 5009 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5010 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5011 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5012 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5013 unsigned W = fieldFromInstruction(Insn, 21, 1); 5014 unsigned U = fieldFromInstruction(Insn, 23, 1); 5015 unsigned P = fieldFromInstruction(Insn, 24, 1); 5016 bool writeback = (W == 1) | (P == 0); 5017 5018 addr |= (U << 8) | (Rn << 9); 5019 5020 if (writeback && (Rn == Rt || Rn == Rt2)) 5021 Check(S, MCDisassembler::SoftFail); 5022 5023 // Writeback operand 5024 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5025 return MCDisassembler::Fail; 5026 // Rt 5027 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5028 return MCDisassembler::Fail; 5029 // Rt2 5030 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5031 return MCDisassembler::Fail; 5032 // addr 5033 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5034 return MCDisassembler::Fail; 5035 5036 return S; 5037 } 5038 5039 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5040 uint64_t Address, const void *Decoder) { 5041 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5042 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5043 if (sign1 != sign2) return MCDisassembler::Fail; 5044 5045 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5046 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5047 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5048 Val |= sign1 << 12; 5049 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5050 5051 return MCDisassembler::Success; 5052 } 5053 5054 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5055 uint64_t Address, 5056 const void *Decoder) { 5057 DecodeStatus S = MCDisassembler::Success; 5058 5059 // Shift of "asr #32" is not allowed in Thumb2 mode. 5060 if (Val == 0x20) S = MCDisassembler::Fail; 5061 Inst.addOperand(MCOperand::createImm(Val)); 5062 return S; 5063 } 5064 5065 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5066 uint64_t Address, const void *Decoder) { 5067 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5068 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5069 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5070 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5071 5072 if (pred == 0xF) 5073 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5074 5075 DecodeStatus S = MCDisassembler::Success; 5076 5077 if (Rt == Rn || Rn == Rt2) 5078 S = MCDisassembler::SoftFail; 5079 5080 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5081 return MCDisassembler::Fail; 5082 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5083 return MCDisassembler::Fail; 5084 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5085 return MCDisassembler::Fail; 5086 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5087 return MCDisassembler::Fail; 5088 5089 return S; 5090 } 5091 5092 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5093 uint64_t Address, const void *Decoder) { 5094 const FeatureBitset &featureBits = 5095 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5096 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5097 5098 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5099 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5100 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5101 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5102 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5103 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5104 unsigned op = fieldFromInstruction(Insn, 5, 1); 5105 5106 DecodeStatus S = MCDisassembler::Success; 5107 5108 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5109 if (!(imm & 0x38)) { 5110 if (cmode == 0xF) { 5111 if (op == 1) return MCDisassembler::Fail; 5112 Inst.setOpcode(ARM::VMOVv2f32); 5113 } 5114 if (hasFullFP16) { 5115 if (cmode == 0xE) { 5116 if (op == 1) { 5117 Inst.setOpcode(ARM::VMOVv1i64); 5118 } else { 5119 Inst.setOpcode(ARM::VMOVv8i8); 5120 } 5121 } 5122 if (cmode == 0xD) { 5123 if (op == 1) { 5124 Inst.setOpcode(ARM::VMVNv2i32); 5125 } else { 5126 Inst.setOpcode(ARM::VMOVv2i32); 5127 } 5128 } 5129 if (cmode == 0xC) { 5130 if (op == 1) { 5131 Inst.setOpcode(ARM::VMVNv2i32); 5132 } else { 5133 Inst.setOpcode(ARM::VMOVv2i32); 5134 } 5135 } 5136 } 5137 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5138 } 5139 5140 if (!(imm & 0x20)) return MCDisassembler::Fail; 5141 5142 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5143 return MCDisassembler::Fail; 5144 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5145 return MCDisassembler::Fail; 5146 Inst.addOperand(MCOperand::createImm(64 - imm)); 5147 5148 return S; 5149 } 5150 5151 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5152 uint64_t Address, const void *Decoder) { 5153 const FeatureBitset &featureBits = 5154 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5155 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5156 5157 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5158 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5159 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5160 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5161 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5162 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5163 unsigned op = fieldFromInstruction(Insn, 5, 1); 5164 5165 DecodeStatus S = MCDisassembler::Success; 5166 5167 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5168 if (!(imm & 0x38)) { 5169 if (cmode == 0xF) { 5170 if (op == 1) return MCDisassembler::Fail; 5171 Inst.setOpcode(ARM::VMOVv4f32); 5172 } 5173 if (hasFullFP16) { 5174 if (cmode == 0xE) { 5175 if (op == 1) { 5176 Inst.setOpcode(ARM::VMOVv2i64); 5177 } else { 5178 Inst.setOpcode(ARM::VMOVv16i8); 5179 } 5180 } 5181 if (cmode == 0xD) { 5182 if (op == 1) { 5183 Inst.setOpcode(ARM::VMVNv4i32); 5184 } else { 5185 Inst.setOpcode(ARM::VMOVv4i32); 5186 } 5187 } 5188 if (cmode == 0xC) { 5189 if (op == 1) { 5190 Inst.setOpcode(ARM::VMVNv4i32); 5191 } else { 5192 Inst.setOpcode(ARM::VMOVv4i32); 5193 } 5194 } 5195 } 5196 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5197 } 5198 5199 if (!(imm & 0x20)) return MCDisassembler::Fail; 5200 5201 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5202 return MCDisassembler::Fail; 5203 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5204 return MCDisassembler::Fail; 5205 Inst.addOperand(MCOperand::createImm(64 - imm)); 5206 5207 return S; 5208 } 5209 5210 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5211 uint64_t Address, const void *Decoder) { 5212 DecodeStatus S = MCDisassembler::Success; 5213 5214 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5215 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5216 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5217 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5218 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5219 5220 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5221 S = MCDisassembler::SoftFail; 5222 5223 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5224 return MCDisassembler::Fail; 5225 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5226 return MCDisassembler::Fail; 5227 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5228 return MCDisassembler::Fail; 5229 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5230 return MCDisassembler::Fail; 5231 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5232 return MCDisassembler::Fail; 5233 5234 return S; 5235 } 5236 5237 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 5238 uint64_t Address, const void *Decoder) { 5239 5240 DecodeStatus S = MCDisassembler::Success; 5241 5242 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5243 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5244 unsigned cop = fieldFromInstruction(Val, 8, 4); 5245 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5246 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5247 5248 if ((cop & ~0x1) == 0xa) 5249 return MCDisassembler::Fail; 5250 5251 if (Rt == Rt2) 5252 S = MCDisassembler::SoftFail; 5253 5254 Inst.addOperand(MCOperand::createImm(cop)); 5255 Inst.addOperand(MCOperand::createImm(opc1)); 5256 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5257 return MCDisassembler::Fail; 5258 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5259 return MCDisassembler::Fail; 5260 Inst.addOperand(MCOperand::createImm(CRm)); 5261 5262 return S; 5263 } 5264 5265