1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDecoderOps.h" 17 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/MC/TargetRegistry.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include "llvm/TargetParser/SubtargetFeature.h" 28 #include <algorithm> 29 #include <cassert> 30 #include <cstdint> 31 #include <vector> 32 33 using namespace llvm; 34 35 #define DEBUG_TYPE "arm-disassembler" 36 37 using DecodeStatus = MCDisassembler::DecodeStatus; 38 39 namespace { 40 41 // Handles the condition code status of instructions in IT blocks 42 class ITStatus 43 { 44 public: 45 // Returns the condition code for instruction in IT block 46 unsigned getITCC() { 47 unsigned CC = ARMCC::AL; 48 if (instrInITBlock()) 49 CC = ITStates.back(); 50 return CC; 51 } 52 53 // Advances the IT block state to the next T or E 54 void advanceITState() { 55 ITStates.pop_back(); 56 } 57 58 // Returns true if the current instruction is in an IT block 59 bool instrInITBlock() { 60 return !ITStates.empty(); 61 } 62 63 // Returns true if current instruction is the last instruction in an IT block 64 bool instrLastInITBlock() { 65 return ITStates.size() == 1; 66 } 67 68 // Called when decoding an IT instruction. Sets the IT state for 69 // the following instructions that for the IT block. Firstcond 70 // corresponds to the field in the IT instruction encoding; Mask 71 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 72 void setITState(char Firstcond, char Mask) { 73 // (3 - the number of trailing zeros) is the number of then / else. 74 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask); 75 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 76 assert(NumTZ <= 3 && "Invalid IT mask!"); 77 // push condition codes onto the stack the correct order for the pops 78 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 79 unsigned Else = (Mask >> Pos) & 1; 80 ITStates.push_back(CCBits ^ Else); 81 } 82 ITStates.push_back(CCBits); 83 } 84 85 private: 86 std::vector<unsigned char> ITStates; 87 }; 88 89 class VPTStatus 90 { 91 public: 92 unsigned getVPTPred() { 93 unsigned Pred = ARMVCC::None; 94 if (instrInVPTBlock()) 95 Pred = VPTStates.back(); 96 return Pred; 97 } 98 99 void advanceVPTState() { 100 VPTStates.pop_back(); 101 } 102 103 bool instrInVPTBlock() { 104 return !VPTStates.empty(); 105 } 106 107 bool instrLastInVPTBlock() { 108 return VPTStates.size() == 1; 109 } 110 111 void setVPTState(char Mask) { 112 // (3 - the number of trailing zeros) is the number of then / else. 113 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask); 114 assert(NumTZ <= 3 && "Invalid VPT mask!"); 115 // push predicates onto the stack the correct order for the pops 116 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 117 bool T = ((Mask >> Pos) & 1) == 0; 118 if (T) 119 VPTStates.push_back(ARMVCC::Then); 120 else 121 VPTStates.push_back(ARMVCC::Else); 122 } 123 VPTStates.push_back(ARMVCC::Then); 124 } 125 126 private: 127 SmallVector<unsigned char, 4> VPTStates; 128 }; 129 130 /// ARM disassembler for all ARM platforms. 131 class ARMDisassembler : public MCDisassembler { 132 public: 133 std::unique_ptr<const MCInstrInfo> MCII; 134 135 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 136 const MCInstrInfo *MCII) 137 : MCDisassembler(STI, Ctx), MCII(MCII) { 138 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions) 139 ? llvm::endianness::big 140 : llvm::endianness::little; 141 } 142 143 ~ARMDisassembler() override = default; 144 145 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 146 ArrayRef<uint8_t> Bytes, uint64_t Address, 147 raw_ostream &CStream) const override; 148 149 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 150 uint64_t Address) const override; 151 152 private: 153 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 154 ArrayRef<uint8_t> Bytes, uint64_t Address, 155 raw_ostream &CStream) const; 156 157 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 158 ArrayRef<uint8_t> Bytes, uint64_t Address, 159 raw_ostream &CStream) const; 160 161 mutable ITStatus ITBlock; 162 mutable VPTStatus VPTBlock; 163 164 void AddThumb1SBit(MCInst &MI, bool InITBlock) const; 165 bool isVectorPredicable(const MCInst &MI) const; 166 DecodeStatus AddThumbPredicate(MCInst&) const; 167 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 168 169 llvm::endianness InstructionEndianness; 170 }; 171 172 } // end anonymous namespace 173 174 // Forward declare these because the autogenerated code will reference them. 175 // Definitions are further down. 176 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, 178 const MCDisassembler *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, 181 const MCDisassembler *Decoder); 182 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, 184 const MCDisassembler *Decoder); 185 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 186 uint64_t Address, 187 const MCDisassembler *Decoder); 188 static DecodeStatus 189 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 190 uint64_t Address, 191 const MCDisassembler *Decoder); 192 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 193 uint64_t Address, 194 const MCDisassembler *Decoder); 195 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 196 uint64_t Address, 197 const MCDisassembler *Decoder); 198 static DecodeStatus 199 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 200 const MCDisassembler *Decoder); 201 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, 203 const MCDisassembler *Decoder); 204 static DecodeStatus 205 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 206 const MCDisassembler *Decoder); 207 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, 209 const MCDisassembler *Decoder); 210 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 211 uint64_t Address, 212 const MCDisassembler *Decoder); 213 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, 215 const MCDisassembler *Decoder); 216 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, 218 const MCDisassembler *Decoder); 219 static DecodeStatus 220 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 221 const MCDisassembler *Decoder); 222 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 223 uint64_t Address, 224 const MCDisassembler *Decoder); 225 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 226 uint64_t Address, 227 const MCDisassembler *Decoder); 228 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, 230 const MCDisassembler *Decoder); 231 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 232 uint64_t Address, 233 const MCDisassembler *Decoder); 234 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 235 uint64_t Address, 236 const MCDisassembler *Decoder); 237 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 238 uint64_t Address, 239 const MCDisassembler *Decoder); 240 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 241 uint64_t Address, 242 const MCDisassembler *Decoder); 243 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 244 uint64_t Address, 245 const MCDisassembler *Decoder); 246 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 247 uint64_t Address, 248 const MCDisassembler *Decoder); 249 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 250 uint64_t Address, 251 const MCDisassembler *Decoder); 252 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 253 uint64_t Address, 254 const MCDisassembler *Decoder); 255 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 256 uint64_t Address, 257 const MCDisassembler *Decoder); 258 static DecodeStatus 259 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 260 const MCDisassembler *Decoder); 261 262 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 263 uint64_t Address, 264 const MCDisassembler *Decoder); 265 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 266 uint64_t Address, 267 const MCDisassembler *Decoder); 268 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 269 uint64_t Address, 270 const MCDisassembler *Decoder); 271 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 272 uint64_t Address, 273 const MCDisassembler *Decoder); 274 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 275 uint64_t Address, 276 const MCDisassembler *Decoder); 277 278 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 279 uint64_t Address, 280 const MCDisassembler *Decoder); 281 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 282 uint64_t Address, 283 const MCDisassembler *Decoder); 284 static DecodeStatus 285 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 286 const MCDisassembler *Decoder); 287 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 288 uint64_t Address, 289 const MCDisassembler *Decoder); 290 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 291 uint64_t Address, 292 const MCDisassembler *Decoder); 293 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 294 uint64_t Address, 295 const MCDisassembler *Decoder); 296 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 297 uint64_t Address, 298 const MCDisassembler *Decoder); 299 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 300 uint64_t Address, 301 const MCDisassembler *Decoder); 302 303 static DecodeStatus 304 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 305 uint64_t Adddress, 306 const MCDisassembler *Decoder); 307 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 308 uint64_t Address, 309 const MCDisassembler *Decoder); 310 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 311 uint64_t Address, 312 const MCDisassembler *Decoder); 313 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 314 uint64_t Address, 315 const MCDisassembler *Decoder); 316 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 317 uint64_t Address, 318 const MCDisassembler *Decoder); 319 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 320 uint64_t Address, 321 const MCDisassembler *Decoder); 322 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 323 uint64_t Address, 324 const MCDisassembler *Decoder); 325 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 326 uint64_t Address, 327 const MCDisassembler *Decoder); 328 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 329 uint64_t Address, 330 const MCDisassembler *Decoder); 331 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, 332 uint64_t Address, 333 const MCDisassembler *Decoder); 334 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 335 uint64_t Address, 336 const MCDisassembler *Decoder); 337 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 338 uint64_t Address, 339 const MCDisassembler *Decoder); 340 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 341 uint64_t Address, 342 const MCDisassembler *Decoder); 343 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 344 uint64_t Address, 345 const MCDisassembler *Decoder); 346 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 347 uint64_t Address, 348 const MCDisassembler *Decoder); 349 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 350 uint64_t Address, 351 const MCDisassembler *Decoder); 352 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 353 uint64_t Address, 354 const MCDisassembler *Decoder); 355 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 356 uint64_t Address, 357 const MCDisassembler *Decoder); 358 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 359 uint64_t Address, 360 const MCDisassembler *Decoder); 361 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 362 uint64_t Address, 363 const MCDisassembler *Decoder); 364 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 365 uint64_t Address, 366 const MCDisassembler *Decoder); 367 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 368 uint64_t Address, 369 const MCDisassembler *Decoder); 370 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 371 uint64_t Address, 372 const MCDisassembler *Decoder); 373 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 374 uint64_t Address, 375 const MCDisassembler *Decoder); 376 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 377 uint64_t Address, 378 const MCDisassembler *Decoder); 379 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 380 uint64_t Address, 381 const MCDisassembler *Decoder); 382 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 383 uint64_t Address, 384 const MCDisassembler *Decoder); 385 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val, 386 uint64_t Address, 387 const MCDisassembler *Decoder); 388 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val, 389 uint64_t Address, 390 const MCDisassembler *Decoder); 391 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 392 uint64_t Address, 393 const MCDisassembler *Decoder); 394 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 395 uint64_t Address, 396 const MCDisassembler *Decoder); 397 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 398 uint64_t Address, 399 const MCDisassembler *Decoder); 400 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 401 uint64_t Address, 402 const MCDisassembler *Decoder); 403 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 404 uint64_t Address, 405 const MCDisassembler *Decoder); 406 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 407 uint64_t Address, 408 const MCDisassembler *Decoder); 409 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 410 uint64_t Address, 411 const MCDisassembler *Decoder); 412 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 413 uint64_t Address, 414 const MCDisassembler *Decoder); 415 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 416 uint64_t Address, 417 const MCDisassembler *Decoder); 418 template <int shift> 419 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 420 uint64_t Address, 421 const MCDisassembler *Decoder); 422 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 423 uint64_t Address, 424 const MCDisassembler *Decoder); 425 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 426 uint64_t Address, 427 const MCDisassembler *Decoder); 428 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 429 uint64_t Address, 430 const MCDisassembler *Decoder); 431 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, 432 const MCDisassembler *Decoder); 433 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 434 uint64_t Address, 435 const MCDisassembler *Decoder); 436 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 437 uint64_t Address, 438 const MCDisassembler *Decoder); 439 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 440 uint64_t Address, 441 const MCDisassembler *Decoder); 442 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 443 uint64_t Address, 444 const MCDisassembler *Decoder); 445 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 446 uint64_t Address, 447 const MCDisassembler *Decoder); 448 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 449 uint64_t Address, 450 const MCDisassembler *Decoder); 451 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 452 uint64_t Address, 453 const MCDisassembler *Decoder); 454 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 455 const MCDisassembler *Decoder); 456 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 457 const MCDisassembler *Decoder); 458 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 459 const MCDisassembler *Decoder); 460 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 461 const MCDisassembler *Decoder); 462 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 463 const MCDisassembler *Decoder); 464 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 465 const MCDisassembler *Decoder); 466 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 467 const MCDisassembler *Decoder); 468 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 469 const MCDisassembler *Decoder); 470 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 471 const MCDisassembler *Decoder); 472 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 473 const MCDisassembler *Decoder); 474 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 475 const MCDisassembler *Decoder); 476 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 477 const MCDisassembler *Decoder); 478 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 479 const MCDisassembler *Decoder); 480 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 481 uint64_t Address, 482 const MCDisassembler *Decoder); 483 static DecodeStatus 484 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, 485 const MCDisassembler *Decoder); 486 487 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 488 uint64_t Address, 489 const MCDisassembler *Decoder); 490 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 491 uint64_t Address, 492 const MCDisassembler *Decoder); 493 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 494 uint64_t Address, 495 const MCDisassembler *Decoder); 496 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 497 uint64_t Address, 498 const MCDisassembler *Decoder); 499 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 500 uint64_t Address, 501 const MCDisassembler *Decoder); 502 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const MCDisassembler *Decoder); 505 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 506 uint64_t Address, 507 const MCDisassembler *Decoder); 508 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 509 uint64_t Address, 510 const MCDisassembler *Decoder); 511 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 512 uint64_t Address, 513 const MCDisassembler *Decoder); 514 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 515 uint64_t Address, 516 const MCDisassembler *Decoder); 517 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 518 uint64_t Address, 519 const MCDisassembler *Decoder); 520 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 521 uint64_t Address, 522 const MCDisassembler *Decoder); 523 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 524 const MCDisassembler *Decoder); 525 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 526 uint64_t Address, 527 const MCDisassembler *Decoder); 528 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 529 const MCDisassembler *Decoder); 530 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 531 const MCDisassembler *Decoder); 532 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 533 uint64_t Address, 534 const MCDisassembler *Decoder); 535 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 536 uint64_t Address, 537 const MCDisassembler *Decoder); 538 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 539 uint64_t Address, 540 const MCDisassembler *Decoder); 541 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 542 const MCDisassembler *Decoder); 543 template <int shift> 544 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 545 const MCDisassembler *Decoder); 546 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 547 uint64_t Address, 548 const MCDisassembler *Decoder); 549 template <int shift> 550 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 551 uint64_t Address, 552 const MCDisassembler *Decoder); 553 template <int shift, int WriteBack> 554 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 555 uint64_t Address, 556 const MCDisassembler *Decoder); 557 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 558 uint64_t Address, 559 const MCDisassembler *Decoder); 560 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 561 uint64_t Address, 562 const MCDisassembler *Decoder); 563 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 564 uint64_t Address, 565 const MCDisassembler *Decoder); 566 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 567 uint64_t Address, 568 const MCDisassembler *Decoder); 569 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 570 uint64_t Address, 571 const MCDisassembler *Decoder); 572 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 573 uint64_t Address, 574 const MCDisassembler *Decoder); 575 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 576 uint64_t Address, 577 const MCDisassembler *Decoder); 578 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 579 uint64_t Address, 580 const MCDisassembler *Decoder); 581 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 582 const MCDisassembler *Decoder); 583 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 584 uint64_t Address, 585 const MCDisassembler *Decoder); 586 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 587 uint64_t Address, 588 const MCDisassembler *Decoder); 589 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, 590 const MCDisassembler *Decoder); 591 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 592 uint64_t Address, 593 const MCDisassembler *Decoder); 594 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 595 uint64_t Address, 596 const MCDisassembler *Decoder); 597 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, 598 const MCDisassembler *Decoder); 599 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 600 uint64_t Address, 601 const MCDisassembler *Decoder); 602 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 603 uint64_t Address, 604 const MCDisassembler *Decoder); 605 606 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 607 const MCDisassembler *Decoder); 608 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 609 uint64_t Address, 610 const MCDisassembler *Decoder); 611 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 612 uint64_t Address, 613 const MCDisassembler *Decoder); 614 615 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 616 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 617 uint64_t Address, 618 const MCDisassembler *Decoder); 619 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 620 uint64_t Address, 621 const MCDisassembler *Decoder); 622 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 623 uint64_t Address, 624 const MCDisassembler *Decoder); 625 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 626 const MCDisassembler *Decoder); 627 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 628 uint64_t Address, 629 const MCDisassembler *Decoder); 630 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 631 const MCDisassembler *Decoder); 632 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 633 uint64_t Address, 634 const MCDisassembler *Decoder); 635 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 636 uint64_t Address, 637 const MCDisassembler *Decoder); 638 static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val, 639 uint64_t Address, 640 const MCDisassembler *Decoder); 641 static DecodeStatus 642 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 643 const MCDisassembler *Decoder); 644 static DecodeStatus 645 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 646 const MCDisassembler *Decoder); 647 static DecodeStatus 648 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 649 const MCDisassembler *Decoder); 650 static DecodeStatus 651 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 652 const MCDisassembler *Decoder); 653 template <bool Writeback> 654 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 655 uint64_t Address, 656 const MCDisassembler *Decoder); 657 template <int shift> 658 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 659 uint64_t Address, 660 const MCDisassembler *Decoder); 661 template <int shift> 662 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 663 uint64_t Address, 664 const MCDisassembler *Decoder); 665 template <int shift> 666 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 667 uint64_t Address, 668 const MCDisassembler *Decoder); 669 template <unsigned MinLog, unsigned MaxLog> 670 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 671 uint64_t Address, 672 const MCDisassembler *Decoder); 673 template <unsigned start> 674 static DecodeStatus 675 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 676 const MCDisassembler *Decoder); 677 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 678 uint64_t Address, 679 const MCDisassembler *Decoder); 680 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 681 uint64_t Address, 682 const MCDisassembler *Decoder); 683 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 684 uint64_t Address, 685 const MCDisassembler *Decoder); 686 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 687 uint64_t Address, 688 const MCDisassembler *Decoder); 689 template <bool scalar, OperandDecoder predicate_decoder> 690 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 691 const MCDisassembler *Decoder); 692 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 693 const MCDisassembler *Decoder); 694 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 695 uint64_t Address, 696 const MCDisassembler *Decoder); 697 static DecodeStatus 698 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 699 const MCDisassembler *Decoder); 700 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 701 uint64_t Address, 702 const MCDisassembler *Decoder); 703 static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, 704 uint64_t Address, 705 const MCDisassembler *Decoder); 706 707 #include "ARMGenDisassemblerTables.inc" 708 709 static MCDisassembler *createARMDisassembler(const Target &T, 710 const MCSubtargetInfo &STI, 711 MCContext &Ctx) { 712 return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo()); 713 } 714 715 // Post-decoding checks 716 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 717 uint64_t Address, raw_ostream &CS, 718 uint32_t Insn, 719 DecodeStatus Result) { 720 switch (MI.getOpcode()) { 721 case ARM::HVC: { 722 // HVC is undefined if condition = 0xf otherwise upredictable 723 // if condition != 0xe 724 uint32_t Cond = (Insn >> 28) & 0xF; 725 if (Cond == 0xF) 726 return MCDisassembler::Fail; 727 if (Cond != 0xE) 728 return MCDisassembler::SoftFail; 729 return Result; 730 } 731 case ARM::t2ADDri: 732 case ARM::t2ADDri12: 733 case ARM::t2ADDrr: 734 case ARM::t2ADDrs: 735 case ARM::t2SUBri: 736 case ARM::t2SUBri12: 737 case ARM::t2SUBrr: 738 case ARM::t2SUBrs: 739 if (MI.getOperand(0).getReg() == ARM::SP && 740 MI.getOperand(1).getReg() != ARM::SP) 741 return MCDisassembler::SoftFail; 742 return Result; 743 default: return Result; 744 } 745 } 746 747 uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 748 uint64_t Address) const { 749 // In Arm state, instructions are always 4 bytes wide, so there's no 750 // point in skipping any smaller number of bytes if an instruction 751 // can't be decoded. 752 if (!STI.hasFeature(ARM::ModeThumb)) 753 return 4; 754 755 // In a Thumb instruction stream, a halfword is a standalone 2-byte 756 // instruction if and only if its value is less than 0xE800. 757 // Otherwise, it's the first halfword of a 4-byte instruction. 758 // 759 // So, if we can see the upcoming halfword, we can judge on that 760 // basis, and maybe skip a whole 4-byte instruction that we don't 761 // know how to decode, without accidentally trying to interpret its 762 // second half as something else. 763 // 764 // If we don't have the instruction data available, we just have to 765 // recommend skipping the minimum sensible distance, which is 2 766 // bytes. 767 if (Bytes.size() < 2) 768 return 2; 769 770 uint16_t Insn16 = llvm::support::endian::read<uint16_t>( 771 Bytes.data(), InstructionEndianness); 772 return Insn16 < 0xE800 ? 2 : 4; 773 } 774 775 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 776 ArrayRef<uint8_t> Bytes, 777 uint64_t Address, 778 raw_ostream &CS) const { 779 if (STI.hasFeature(ARM::ModeThumb)) 780 return getThumbInstruction(MI, Size, Bytes, Address, CS); 781 return getARMInstruction(MI, Size, Bytes, Address, CS); 782 } 783 784 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 785 ArrayRef<uint8_t> Bytes, 786 uint64_t Address, 787 raw_ostream &CS) const { 788 CommentStream = &CS; 789 790 assert(!STI.hasFeature(ARM::ModeThumb) && 791 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 792 "mode!"); 793 794 // We want to read exactly 4 bytes of data. 795 if (Bytes.size() < 4) { 796 Size = 0; 797 return MCDisassembler::Fail; 798 } 799 800 // Encoded as a 32-bit word in the stream. 801 uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(), 802 InstructionEndianness); 803 804 // Calling the auto-generated decoder function. 805 DecodeStatus Result = 806 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 807 if (Result != MCDisassembler::Fail) { 808 Size = 4; 809 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 810 } 811 812 struct DecodeTable { 813 const uint8_t *P; 814 bool DecodePred; 815 }; 816 817 const DecodeTable Tables[] = { 818 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 819 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 820 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 821 {DecoderTablev8Crypto32, false}, 822 }; 823 824 for (auto Table : Tables) { 825 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 826 if (Result != MCDisassembler::Fail) { 827 Size = 4; 828 // Add a fake predicate operand, because we share these instruction 829 // definitions with Thumb2 where these instructions are predicable. 830 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 831 return MCDisassembler::Fail; 832 return Result; 833 } 834 } 835 836 Result = 837 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 838 if (Result != MCDisassembler::Fail) { 839 Size = 4; 840 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 841 } 842 843 Size = 4; 844 return MCDisassembler::Fail; 845 } 846 847 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 848 /// immediate Value in the MCInst. The immediate Value has had any PC 849 /// adjustment made by the caller. If the instruction is a branch instruction 850 /// then isBranch is true, else false. If the getOpInfo() function was set as 851 /// part of the setupForSymbolicDisassembly() call then that function is called 852 /// to get any symbolic information at the Address for this instruction. If 853 /// that returns non-zero then the symbolic information it returns is used to 854 /// create an MCExpr and that is added as an operand to the MCInst. If 855 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 856 /// Value is done and if a symbol is found an MCExpr is created with that, else 857 /// an MCExpr with Value is created. This function returns true if it adds an 858 /// operand to the MCInst and false otherwise. 859 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 860 bool isBranch, uint64_t InstSize, 861 MCInst &MI, 862 const MCDisassembler *Decoder) { 863 // FIXME: Does it make sense for value to be negative? 864 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, 865 isBranch, /*Offset=*/0, /*OpSize=*/0, 866 InstSize); 867 } 868 869 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 870 /// referenced by a load instruction with the base register that is the Pc. 871 /// These can often be values in a literal pool near the Address of the 872 /// instruction. The Address of the instruction and its immediate Value are 873 /// used as a possible literal pool entry. The SymbolLookUp call back will 874 /// return the name of a symbol referenced by the literal pool's entry if 875 /// the referenced address is that of a symbol. Or it will return a pointer to 876 /// a literal 'C' string if the referenced address of the literal pool's entry 877 /// is an address into a section with 'C' string literals. 878 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 879 const MCDisassembler *Decoder) { 880 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 881 Dis->tryAddingPcLoadReferenceComment(Value, Address); 882 } 883 884 // Thumb1 instructions don't have explicit S bits. Rather, they 885 // implicitly set CPSR. Since it's not represented in the encoding, the 886 // auto-generated decoder won't inject the CPSR operand. We need to fix 887 // that as a post-pass. 888 void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const { 889 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 890 MCInst::iterator I = MI.begin(); 891 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) { 892 if (I == MI.end()) break; 893 if (MCID.operands()[i].isOptionalDef() && 894 MCID.operands()[i].RegClass == ARM::CCRRegClassID) { 895 if (i > 0 && MCID.operands()[i - 1].isPredicate()) 896 continue; 897 MI.insert(I, 898 MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR)); 899 return; 900 } 901 } 902 903 MI.insert(I, MCOperand::createReg(InITBlock ? ARM::NoRegister : ARM::CPSR)); 904 } 905 906 bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const { 907 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 908 for (unsigned i = 0; i < MCID.NumOperands; ++i) { 909 if (ARM::isVpred(MCID.operands()[i].OperandType)) 910 return true; 911 } 912 return false; 913 } 914 915 // Most Thumb instructions don't have explicit predicates in the 916 // encoding, but rather get their predicates from IT context. We need 917 // to fix up the predicate operands using this context information as a 918 // post-pass. 919 MCDisassembler::DecodeStatus 920 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 921 MCDisassembler::DecodeStatus S = Success; 922 923 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 924 925 // A few instructions actually have predicates encoded in them. Don't 926 // try to overwrite it if we're seeing one of those. 927 switch (MI.getOpcode()) { 928 case ARM::tBcc: 929 case ARM::t2Bcc: 930 case ARM::tCBZ: 931 case ARM::tCBNZ: 932 case ARM::tCPS: 933 case ARM::t2CPS3p: 934 case ARM::t2CPS2p: 935 case ARM::t2CPS1p: 936 case ARM::t2CSEL: 937 case ARM::t2CSINC: 938 case ARM::t2CSINV: 939 case ARM::t2CSNEG: 940 case ARM::tMOVSr: 941 case ARM::tSETEND: 942 // Some instructions (mostly conditional branches) are not 943 // allowed in IT blocks. 944 if (ITBlock.instrInITBlock()) 945 S = SoftFail; 946 else 947 return Success; 948 break; 949 case ARM::t2HINT: 950 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 951 S = SoftFail; 952 break; 953 case ARM::tB: 954 case ARM::t2B: 955 case ARM::t2TBB: 956 case ARM::t2TBH: 957 // Some instructions (mostly unconditional branches) can 958 // only appears at the end of, or outside of, an IT. 959 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 960 S = SoftFail; 961 break; 962 default: 963 break; 964 } 965 966 // Warn on non-VPT predicable instruction in a VPT block and a VPT 967 // predicable instruction in an IT block 968 if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) || 969 (isVectorPredicable(MI) && ITBlock.instrInITBlock())) 970 S = SoftFail; 971 972 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 973 // assume a predicate of AL. 974 unsigned CC = ARMCC::AL; 975 unsigned VCC = ARMVCC::None; 976 if (ITBlock.instrInITBlock()) { 977 CC = ITBlock.getITCC(); 978 ITBlock.advanceITState(); 979 } else if (VPTBlock.instrInVPTBlock()) { 980 VCC = VPTBlock.getVPTPred(); 981 VPTBlock.advanceVPTState(); 982 } 983 984 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 985 986 MCInst::iterator CCI = MI.begin(); 987 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) { 988 if (MCID.operands()[i].isPredicate() || CCI == MI.end()) 989 break; 990 } 991 992 if (MCID.isPredicable()) { 993 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 994 ++CCI; 995 if (CC == ARMCC::AL) 996 MI.insert(CCI, MCOperand::createReg(0)); 997 else 998 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 999 } else if (CC != ARMCC::AL) { 1000 Check(S, SoftFail); 1001 } 1002 1003 MCInst::iterator VCCI = MI.begin(); 1004 unsigned VCCPos; 1005 for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) { 1006 if (ARM::isVpred(MCID.operands()[VCCPos].OperandType) || VCCI == MI.end()) 1007 break; 1008 } 1009 1010 if (isVectorPredicable(MI)) { 1011 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 1012 ++VCCI; 1013 if (VCC == ARMVCC::None) 1014 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1015 else 1016 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 1017 ++VCCI; 1018 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1019 ++VCCI; 1020 if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 1021 int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO); 1022 assert(TiedOp >= 0 && 1023 "Inactive register in vpred_r is not tied to an output!"); 1024 // Copy the operand to ensure it's not invalidated when MI grows. 1025 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 1026 } 1027 } else if (VCC != ARMVCC::None) { 1028 Check(S, SoftFail); 1029 } 1030 1031 return S; 1032 } 1033 1034 // Thumb VFP instructions are a special case. Because we share their 1035 // encodings between ARM and Thumb modes, and they are predicable in ARM 1036 // mode, the auto-generated decoder will give them an (incorrect) 1037 // predicate operand. We need to rewrite these operands based on the IT 1038 // context as a post-pass. 1039 void ARMDisassembler::UpdateThumbVFPPredicate( 1040 DecodeStatus &S, MCInst &MI) const { 1041 unsigned CC; 1042 CC = ITBlock.getITCC(); 1043 if (CC == 0xF) 1044 CC = ARMCC::AL; 1045 if (ITBlock.instrInITBlock()) 1046 ITBlock.advanceITState(); 1047 else if (VPTBlock.instrInVPTBlock()) { 1048 CC = VPTBlock.getVPTPred(); 1049 VPTBlock.advanceVPTState(); 1050 } 1051 1052 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 1053 ArrayRef<MCOperandInfo> OpInfo = MCID.operands(); 1054 MCInst::iterator I = MI.begin(); 1055 unsigned short NumOps = MCID.NumOperands; 1056 for (unsigned i = 0; i < NumOps; ++i, ++I) { 1057 if (OpInfo[i].isPredicate() ) { 1058 if (CC != ARMCC::AL && !MCID.isPredicable()) 1059 Check(S, SoftFail); 1060 I->setImm(CC); 1061 ++I; 1062 if (CC == ARMCC::AL) 1063 I->setReg(0); 1064 else 1065 I->setReg(ARM::CPSR); 1066 return; 1067 } 1068 } 1069 } 1070 1071 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 1072 ArrayRef<uint8_t> Bytes, 1073 uint64_t Address, 1074 raw_ostream &CS) const { 1075 CommentStream = &CS; 1076 1077 assert(STI.hasFeature(ARM::ModeThumb) && 1078 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 1079 1080 // We want to read exactly 2 bytes of data. 1081 if (Bytes.size() < 2) { 1082 Size = 0; 1083 return MCDisassembler::Fail; 1084 } 1085 1086 uint16_t Insn16 = llvm::support::endian::read<uint16_t>( 1087 Bytes.data(), InstructionEndianness); 1088 DecodeStatus Result = 1089 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 1090 if (Result != MCDisassembler::Fail) { 1091 Size = 2; 1092 Check(Result, AddThumbPredicate(MI)); 1093 return Result; 1094 } 1095 1096 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 1097 STI); 1098 if (Result) { 1099 Size = 2; 1100 bool InITBlock = ITBlock.instrInITBlock(); 1101 Check(Result, AddThumbPredicate(MI)); 1102 AddThumb1SBit(MI, InITBlock); 1103 return Result; 1104 } 1105 1106 Result = 1107 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 1108 if (Result != MCDisassembler::Fail) { 1109 Size = 2; 1110 1111 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 1112 // the Thumb predicate. 1113 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 1114 Result = MCDisassembler::SoftFail; 1115 1116 Check(Result, AddThumbPredicate(MI)); 1117 1118 // If we find an IT instruction, we need to parse its condition 1119 // code and mask operands so that we can apply them correctly 1120 // to the subsequent instructions. 1121 if (MI.getOpcode() == ARM::t2IT) { 1122 unsigned Firstcond = MI.getOperand(0).getImm(); 1123 unsigned Mask = MI.getOperand(1).getImm(); 1124 ITBlock.setITState(Firstcond, Mask); 1125 1126 // An IT instruction that would give a 'NV' predicate is unpredictable. 1127 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 1128 CS << "unpredictable IT predicate sequence"; 1129 } 1130 1131 return Result; 1132 } 1133 1134 // We want to read exactly 4 bytes of data. 1135 if (Bytes.size() < 4) { 1136 Size = 0; 1137 return MCDisassembler::Fail; 1138 } 1139 1140 uint32_t Insn32 = 1141 (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>( 1142 Bytes.data() + 2, InstructionEndianness); 1143 1144 Result = 1145 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 1146 if (Result != MCDisassembler::Fail) { 1147 Size = 4; 1148 1149 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 1150 // the VPT predicate. 1151 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 1152 Result = MCDisassembler::SoftFail; 1153 1154 Check(Result, AddThumbPredicate(MI)); 1155 1156 if (isVPTOpcode(MI.getOpcode())) { 1157 unsigned Mask = MI.getOperand(0).getImm(); 1158 VPTBlock.setVPTState(Mask); 1159 } 1160 1161 return Result; 1162 } 1163 1164 Result = 1165 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1166 if (Result != MCDisassembler::Fail) { 1167 Size = 4; 1168 bool InITBlock = ITBlock.instrInITBlock(); 1169 Check(Result, AddThumbPredicate(MI)); 1170 AddThumb1SBit(MI, InITBlock); 1171 return Result; 1172 } 1173 1174 Result = 1175 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1176 if (Result != MCDisassembler::Fail) { 1177 Size = 4; 1178 Check(Result, AddThumbPredicate(MI)); 1179 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1180 } 1181 1182 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1183 Result = 1184 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1185 if (Result != MCDisassembler::Fail) { 1186 Size = 4; 1187 UpdateThumbVFPPredicate(Result, MI); 1188 return Result; 1189 } 1190 } 1191 1192 Result = 1193 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1194 if (Result != MCDisassembler::Fail) { 1195 Size = 4; 1196 return Result; 1197 } 1198 1199 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1200 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1201 STI); 1202 if (Result != MCDisassembler::Fail) { 1203 Size = 4; 1204 Check(Result, AddThumbPredicate(MI)); 1205 return Result; 1206 } 1207 } 1208 1209 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1210 uint32_t NEONLdStInsn = Insn32; 1211 NEONLdStInsn &= 0xF0FFFFFF; 1212 NEONLdStInsn |= 0x04000000; 1213 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1214 Address, this, STI); 1215 if (Result != MCDisassembler::Fail) { 1216 Size = 4; 1217 Check(Result, AddThumbPredicate(MI)); 1218 return Result; 1219 } 1220 } 1221 1222 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1223 uint32_t NEONDataInsn = Insn32; 1224 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1225 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1226 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1227 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1228 Address, this, STI); 1229 if (Result != MCDisassembler::Fail) { 1230 Size = 4; 1231 Check(Result, AddThumbPredicate(MI)); 1232 return Result; 1233 } 1234 1235 uint32_t NEONCryptoInsn = Insn32; 1236 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1237 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1238 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1239 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1240 Address, this, STI); 1241 if (Result != MCDisassembler::Fail) { 1242 Size = 4; 1243 return Result; 1244 } 1245 1246 uint32_t NEONv8Insn = Insn32; 1247 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1248 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1249 this, STI); 1250 if (Result != MCDisassembler::Fail) { 1251 Size = 4; 1252 return Result; 1253 } 1254 } 1255 1256 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1257 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1258 ? DecoderTableThumb2CDE32 1259 : DecoderTableThumb2CoProc32; 1260 Result = 1261 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1262 if (Result != MCDisassembler::Fail) { 1263 Size = 4; 1264 Check(Result, AddThumbPredicate(MI)); 1265 return Result; 1266 } 1267 1268 Size = 0; 1269 return MCDisassembler::Fail; 1270 } 1271 1272 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1273 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1274 createARMDisassembler); 1275 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1276 createARMDisassembler); 1277 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1278 createARMDisassembler); 1279 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1280 createARMDisassembler); 1281 } 1282 1283 static const uint16_t GPRDecoderTable[] = { 1284 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1285 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1286 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1287 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1288 }; 1289 1290 static const uint16_t CLRMGPRDecoderTable[] = { 1291 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1292 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1293 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1294 ARM::R12, 0, ARM::LR, ARM::APSR 1295 }; 1296 1297 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1298 uint64_t Address, 1299 const MCDisassembler *Decoder) { 1300 if (RegNo > 15) 1301 return MCDisassembler::Fail; 1302 1303 unsigned Register = GPRDecoderTable[RegNo]; 1304 Inst.addOperand(MCOperand::createReg(Register)); 1305 return MCDisassembler::Success; 1306 } 1307 1308 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1309 uint64_t Address, 1310 const MCDisassembler *Decoder) { 1311 if (RegNo > 15) 1312 return MCDisassembler::Fail; 1313 1314 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1315 if (Register == 0) 1316 return MCDisassembler::Fail; 1317 1318 Inst.addOperand(MCOperand::createReg(Register)); 1319 return MCDisassembler::Success; 1320 } 1321 1322 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1323 uint64_t Address, 1324 const MCDisassembler *Decoder) { 1325 DecodeStatus S = MCDisassembler::Success; 1326 1327 if (RegNo == 15) 1328 S = MCDisassembler::SoftFail; 1329 1330 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1331 1332 return S; 1333 } 1334 1335 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1336 uint64_t Address, 1337 const MCDisassembler *Decoder) { 1338 DecodeStatus S = MCDisassembler::Success; 1339 1340 if (RegNo == 13) 1341 S = MCDisassembler::SoftFail; 1342 1343 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1344 1345 return S; 1346 } 1347 1348 static DecodeStatus 1349 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1350 const MCDisassembler *Decoder) { 1351 DecodeStatus S = MCDisassembler::Success; 1352 1353 if (RegNo == 15) 1354 { 1355 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1356 return MCDisassembler::Success; 1357 } 1358 1359 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1360 return S; 1361 } 1362 1363 static DecodeStatus 1364 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1365 const MCDisassembler *Decoder) { 1366 DecodeStatus S = MCDisassembler::Success; 1367 1368 if (RegNo == 15) 1369 { 1370 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1371 return MCDisassembler::Success; 1372 } 1373 1374 if (RegNo == 13) 1375 Check(S, MCDisassembler::SoftFail); 1376 1377 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1378 return S; 1379 } 1380 1381 static DecodeStatus 1382 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1383 const MCDisassembler *Decoder) { 1384 DecodeStatus S = MCDisassembler::Success; 1385 if (RegNo == 13) 1386 return MCDisassembler::Fail; 1387 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1388 return S; 1389 } 1390 1391 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1392 uint64_t Address, 1393 const MCDisassembler *Decoder) { 1394 if (RegNo > 7) 1395 return MCDisassembler::Fail; 1396 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1397 } 1398 1399 static const uint16_t GPRPairDecoderTable[] = { 1400 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1401 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1402 }; 1403 1404 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1405 uint64_t Address, 1406 const MCDisassembler *Decoder) { 1407 DecodeStatus S = MCDisassembler::Success; 1408 1409 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1410 // rather than SoftFail as there is no GPRPair table entry for index 7. 1411 if (RegNo > 13) 1412 return MCDisassembler::Fail; 1413 1414 if (RegNo & 1) 1415 S = MCDisassembler::SoftFail; 1416 1417 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1418 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1419 return S; 1420 } 1421 1422 static DecodeStatus 1423 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1424 const MCDisassembler *Decoder) { 1425 if (RegNo > 13) 1426 return MCDisassembler::Fail; 1427 1428 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1429 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1430 1431 if ((RegNo & 1) || RegNo > 10) 1432 return MCDisassembler::SoftFail; 1433 return MCDisassembler::Success; 1434 } 1435 1436 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1437 uint64_t Address, 1438 const MCDisassembler *Decoder) { 1439 if (RegNo != 13) 1440 return MCDisassembler::Fail; 1441 1442 unsigned Register = GPRDecoderTable[RegNo]; 1443 Inst.addOperand(MCOperand::createReg(Register)); 1444 return MCDisassembler::Success; 1445 } 1446 1447 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1448 uint64_t Address, 1449 const MCDisassembler *Decoder) { 1450 unsigned Register = 0; 1451 switch (RegNo) { 1452 case 0: 1453 Register = ARM::R0; 1454 break; 1455 case 1: 1456 Register = ARM::R1; 1457 break; 1458 case 2: 1459 Register = ARM::R2; 1460 break; 1461 case 3: 1462 Register = ARM::R3; 1463 break; 1464 case 9: 1465 Register = ARM::R9; 1466 break; 1467 case 12: 1468 Register = ARM::R12; 1469 break; 1470 default: 1471 return MCDisassembler::Fail; 1472 } 1473 1474 Inst.addOperand(MCOperand::createReg(Register)); 1475 return MCDisassembler::Success; 1476 } 1477 1478 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1479 uint64_t Address, 1480 const MCDisassembler *Decoder) { 1481 DecodeStatus S = MCDisassembler::Success; 1482 1483 const FeatureBitset &featureBits = 1484 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1485 1486 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1487 S = MCDisassembler::SoftFail; 1488 1489 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1490 return S; 1491 } 1492 1493 static const uint16_t SPRDecoderTable[] = { 1494 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1495 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1496 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1497 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1498 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1499 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1500 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1501 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1502 }; 1503 1504 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1505 uint64_t Address, 1506 const MCDisassembler *Decoder) { 1507 if (RegNo > 31) 1508 return MCDisassembler::Fail; 1509 1510 unsigned Register = SPRDecoderTable[RegNo]; 1511 Inst.addOperand(MCOperand::createReg(Register)); 1512 return MCDisassembler::Success; 1513 } 1514 1515 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1516 uint64_t Address, 1517 const MCDisassembler *Decoder) { 1518 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1519 } 1520 1521 static const uint16_t DPRDecoderTable[] = { 1522 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1523 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1524 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1525 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1526 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1527 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1528 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1529 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1530 }; 1531 1532 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1533 uint64_t Address, 1534 const MCDisassembler *Decoder) { 1535 const FeatureBitset &featureBits = 1536 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1537 1538 bool hasD32 = featureBits[ARM::FeatureD32]; 1539 1540 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1541 return MCDisassembler::Fail; 1542 1543 unsigned Register = DPRDecoderTable[RegNo]; 1544 Inst.addOperand(MCOperand::createReg(Register)); 1545 return MCDisassembler::Success; 1546 } 1547 1548 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1549 uint64_t Address, 1550 const MCDisassembler *Decoder) { 1551 if (RegNo > 7) 1552 return MCDisassembler::Fail; 1553 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1554 } 1555 1556 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1557 uint64_t Address, 1558 const MCDisassembler *Decoder) { 1559 if (RegNo > 15) 1560 return MCDisassembler::Fail; 1561 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1562 } 1563 1564 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1565 uint64_t Address, 1566 const MCDisassembler *Decoder) { 1567 if (RegNo > 15) 1568 return MCDisassembler::Fail; 1569 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1570 } 1571 1572 static const uint16_t QPRDecoderTable[] = { 1573 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1574 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1575 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1576 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1577 }; 1578 1579 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1580 uint64_t Address, 1581 const MCDisassembler *Decoder) { 1582 if (RegNo > 31 || (RegNo & 1) != 0) 1583 return MCDisassembler::Fail; 1584 RegNo >>= 1; 1585 1586 unsigned Register = QPRDecoderTable[RegNo]; 1587 Inst.addOperand(MCOperand::createReg(Register)); 1588 return MCDisassembler::Success; 1589 } 1590 1591 static const uint16_t DPairDecoderTable[] = { 1592 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1593 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1594 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1595 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1596 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1597 ARM::Q15 1598 }; 1599 1600 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1601 uint64_t Address, 1602 const MCDisassembler *Decoder) { 1603 if (RegNo > 30) 1604 return MCDisassembler::Fail; 1605 1606 unsigned Register = DPairDecoderTable[RegNo]; 1607 Inst.addOperand(MCOperand::createReg(Register)); 1608 return MCDisassembler::Success; 1609 } 1610 1611 static const uint16_t DPairSpacedDecoderTable[] = { 1612 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1613 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1614 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1615 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1616 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1617 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1618 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1619 ARM::D28_D30, ARM::D29_D31 1620 }; 1621 1622 static DecodeStatus 1623 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1624 const MCDisassembler *Decoder) { 1625 if (RegNo > 29) 1626 return MCDisassembler::Fail; 1627 1628 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1629 Inst.addOperand(MCOperand::createReg(Register)); 1630 return MCDisassembler::Success; 1631 } 1632 1633 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1634 uint64_t Address, 1635 const MCDisassembler *Decoder) { 1636 DecodeStatus S = MCDisassembler::Success; 1637 if (Val == 0xF) return MCDisassembler::Fail; 1638 // AL predicate is not allowed on Thumb1 branches. 1639 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1640 return MCDisassembler::Fail; 1641 const MCInstrInfo *MCII = 1642 static_cast<const ARMDisassembler *>(Decoder)->MCII.get(); 1643 if (Val != ARMCC::AL && !MCII->get(Inst.getOpcode()).isPredicable()) 1644 Check(S, MCDisassembler::SoftFail); 1645 Inst.addOperand(MCOperand::createImm(Val)); 1646 if (Val == ARMCC::AL) { 1647 Inst.addOperand(MCOperand::createReg(0)); 1648 } else 1649 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1650 return S; 1651 } 1652 1653 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1654 uint64_t Address, 1655 const MCDisassembler *Decoder) { 1656 if (Val) 1657 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1658 else 1659 Inst.addOperand(MCOperand::createReg(0)); 1660 return MCDisassembler::Success; 1661 } 1662 1663 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1664 uint64_t Address, 1665 const MCDisassembler *Decoder) { 1666 DecodeStatus S = MCDisassembler::Success; 1667 1668 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1669 unsigned type = fieldFromInstruction(Val, 5, 2); 1670 unsigned imm = fieldFromInstruction(Val, 7, 5); 1671 1672 // Register-immediate 1673 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1674 return MCDisassembler::Fail; 1675 1676 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1677 switch (type) { 1678 case 0: 1679 Shift = ARM_AM::lsl; 1680 break; 1681 case 1: 1682 Shift = ARM_AM::lsr; 1683 break; 1684 case 2: 1685 Shift = ARM_AM::asr; 1686 break; 1687 case 3: 1688 Shift = ARM_AM::ror; 1689 break; 1690 } 1691 1692 if (Shift == ARM_AM::ror && imm == 0) 1693 Shift = ARM_AM::rrx; 1694 1695 unsigned Op = Shift | (imm << 3); 1696 Inst.addOperand(MCOperand::createImm(Op)); 1697 1698 return S; 1699 } 1700 1701 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1702 uint64_t Address, 1703 const MCDisassembler *Decoder) { 1704 DecodeStatus S = MCDisassembler::Success; 1705 1706 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1707 unsigned type = fieldFromInstruction(Val, 5, 2); 1708 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1709 1710 // Register-register 1711 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1712 return MCDisassembler::Fail; 1713 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1714 return MCDisassembler::Fail; 1715 1716 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1717 switch (type) { 1718 case 0: 1719 Shift = ARM_AM::lsl; 1720 break; 1721 case 1: 1722 Shift = ARM_AM::lsr; 1723 break; 1724 case 2: 1725 Shift = ARM_AM::asr; 1726 break; 1727 case 3: 1728 Shift = ARM_AM::ror; 1729 break; 1730 } 1731 1732 Inst.addOperand(MCOperand::createImm(Shift)); 1733 1734 return S; 1735 } 1736 1737 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1738 uint64_t Address, 1739 const MCDisassembler *Decoder) { 1740 DecodeStatus S = MCDisassembler::Success; 1741 1742 bool NeedDisjointWriteback = false; 1743 MCRegister WritebackReg; 1744 bool CLRM = false; 1745 switch (Inst.getOpcode()) { 1746 default: 1747 break; 1748 case ARM::LDMIA_UPD: 1749 case ARM::LDMDB_UPD: 1750 case ARM::LDMIB_UPD: 1751 case ARM::LDMDA_UPD: 1752 case ARM::t2LDMIA_UPD: 1753 case ARM::t2LDMDB_UPD: 1754 case ARM::t2STMIA_UPD: 1755 case ARM::t2STMDB_UPD: 1756 NeedDisjointWriteback = true; 1757 WritebackReg = Inst.getOperand(0).getReg(); 1758 break; 1759 case ARM::t2CLRM: 1760 CLRM = true; 1761 break; 1762 } 1763 1764 // Empty register lists are not allowed. 1765 if (Val == 0) return MCDisassembler::Fail; 1766 for (unsigned i = 0; i < 16; ++i) { 1767 if (Val & (1 << i)) { 1768 if (CLRM) { 1769 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1770 return MCDisassembler::Fail; 1771 } 1772 } else { 1773 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1774 return MCDisassembler::Fail; 1775 // Writeback not allowed if Rn is in the target list. 1776 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1777 Check(S, MCDisassembler::SoftFail); 1778 } 1779 } 1780 } 1781 1782 return S; 1783 } 1784 1785 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1786 uint64_t Address, 1787 const MCDisassembler *Decoder) { 1788 DecodeStatus S = MCDisassembler::Success; 1789 1790 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1791 unsigned regs = fieldFromInstruction(Val, 0, 8); 1792 1793 // In case of unpredictable encoding, tweak the operands. 1794 if (regs == 0 || (Vd + regs) > 32) { 1795 regs = Vd + regs > 32 ? 32 - Vd : regs; 1796 regs = std::max( 1u, regs); 1797 S = MCDisassembler::SoftFail; 1798 } 1799 1800 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1801 return MCDisassembler::Fail; 1802 for (unsigned i = 0; i < (regs - 1); ++i) { 1803 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1804 return MCDisassembler::Fail; 1805 } 1806 1807 return S; 1808 } 1809 1810 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1811 uint64_t Address, 1812 const MCDisassembler *Decoder) { 1813 DecodeStatus S = MCDisassembler::Success; 1814 1815 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1816 unsigned regs = fieldFromInstruction(Val, 1, 7); 1817 1818 // In case of unpredictable encoding, tweak the operands. 1819 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1820 regs = Vd + regs > 32 ? 32 - Vd : regs; 1821 regs = std::max( 1u, regs); 1822 regs = std::min(16u, regs); 1823 S = MCDisassembler::SoftFail; 1824 } 1825 1826 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1827 return MCDisassembler::Fail; 1828 for (unsigned i = 0; i < (regs - 1); ++i) { 1829 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1830 return MCDisassembler::Fail; 1831 } 1832 1833 return S; 1834 } 1835 1836 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1837 uint64_t Address, 1838 const MCDisassembler *Decoder) { 1839 // This operand encodes a mask of contiguous zeros between a specified MSB 1840 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1841 // the mask of all bits LSB-and-lower, and then xor them to create 1842 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1843 // create the final mask. 1844 unsigned msb = fieldFromInstruction(Val, 5, 5); 1845 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1846 1847 DecodeStatus S = MCDisassembler::Success; 1848 if (lsb > msb) { 1849 Check(S, MCDisassembler::SoftFail); 1850 // The check above will cause the warning for the "potentially undefined 1851 // instruction encoding" but we can't build a bad MCOperand value here 1852 // with a lsb > msb or else printing the MCInst will cause a crash. 1853 lsb = msb; 1854 } 1855 1856 uint32_t msb_mask = 0xFFFFFFFF; 1857 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1858 uint32_t lsb_mask = (1U << lsb) - 1; 1859 1860 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1861 return S; 1862 } 1863 1864 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1865 uint64_t Address, 1866 const MCDisassembler *Decoder) { 1867 DecodeStatus S = MCDisassembler::Success; 1868 1869 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1870 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1871 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1872 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1873 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1874 unsigned U = fieldFromInstruction(Insn, 23, 1); 1875 const FeatureBitset &featureBits = 1876 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1877 1878 switch (Inst.getOpcode()) { 1879 case ARM::LDC_OFFSET: 1880 case ARM::LDC_PRE: 1881 case ARM::LDC_POST: 1882 case ARM::LDC_OPTION: 1883 case ARM::LDCL_OFFSET: 1884 case ARM::LDCL_PRE: 1885 case ARM::LDCL_POST: 1886 case ARM::LDCL_OPTION: 1887 case ARM::STC_OFFSET: 1888 case ARM::STC_PRE: 1889 case ARM::STC_POST: 1890 case ARM::STC_OPTION: 1891 case ARM::STCL_OFFSET: 1892 case ARM::STCL_PRE: 1893 case ARM::STCL_POST: 1894 case ARM::STCL_OPTION: 1895 case ARM::t2LDC_OFFSET: 1896 case ARM::t2LDC_PRE: 1897 case ARM::t2LDC_POST: 1898 case ARM::t2LDC_OPTION: 1899 case ARM::t2LDCL_OFFSET: 1900 case ARM::t2LDCL_PRE: 1901 case ARM::t2LDCL_POST: 1902 case ARM::t2LDCL_OPTION: 1903 case ARM::t2STC_OFFSET: 1904 case ARM::t2STC_PRE: 1905 case ARM::t2STC_POST: 1906 case ARM::t2STC_OPTION: 1907 case ARM::t2STCL_OFFSET: 1908 case ARM::t2STCL_PRE: 1909 case ARM::t2STCL_POST: 1910 case ARM::t2STCL_OPTION: 1911 case ARM::t2LDC2_OFFSET: 1912 case ARM::t2LDC2L_OFFSET: 1913 case ARM::t2LDC2_PRE: 1914 case ARM::t2LDC2L_PRE: 1915 case ARM::t2STC2_OFFSET: 1916 case ARM::t2STC2L_OFFSET: 1917 case ARM::t2STC2_PRE: 1918 case ARM::t2STC2L_PRE: 1919 case ARM::LDC2_OFFSET: 1920 case ARM::LDC2L_OFFSET: 1921 case ARM::LDC2_PRE: 1922 case ARM::LDC2L_PRE: 1923 case ARM::STC2_OFFSET: 1924 case ARM::STC2L_OFFSET: 1925 case ARM::STC2_PRE: 1926 case ARM::STC2L_PRE: 1927 case ARM::t2LDC2_OPTION: 1928 case ARM::t2STC2_OPTION: 1929 case ARM::t2LDC2_POST: 1930 case ARM::t2LDC2L_POST: 1931 case ARM::t2STC2_POST: 1932 case ARM::t2STC2L_POST: 1933 case ARM::LDC2_POST: 1934 case ARM::LDC2L_POST: 1935 case ARM::STC2_POST: 1936 case ARM::STC2L_POST: 1937 if (coproc == 0xA || coproc == 0xB || 1938 (featureBits[ARM::HasV8_1MMainlineOps] && 1939 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1940 coproc == 0xE || coproc == 0xF))) 1941 return MCDisassembler::Fail; 1942 break; 1943 default: 1944 break; 1945 } 1946 1947 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1948 return MCDisassembler::Fail; 1949 1950 Inst.addOperand(MCOperand::createImm(coproc)); 1951 Inst.addOperand(MCOperand::createImm(CRd)); 1952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1953 return MCDisassembler::Fail; 1954 1955 switch (Inst.getOpcode()) { 1956 case ARM::t2LDC2_OFFSET: 1957 case ARM::t2LDC2L_OFFSET: 1958 case ARM::t2LDC2_PRE: 1959 case ARM::t2LDC2L_PRE: 1960 case ARM::t2STC2_OFFSET: 1961 case ARM::t2STC2L_OFFSET: 1962 case ARM::t2STC2_PRE: 1963 case ARM::t2STC2L_PRE: 1964 case ARM::LDC2_OFFSET: 1965 case ARM::LDC2L_OFFSET: 1966 case ARM::LDC2_PRE: 1967 case ARM::LDC2L_PRE: 1968 case ARM::STC2_OFFSET: 1969 case ARM::STC2L_OFFSET: 1970 case ARM::STC2_PRE: 1971 case ARM::STC2L_PRE: 1972 case ARM::t2LDC_OFFSET: 1973 case ARM::t2LDCL_OFFSET: 1974 case ARM::t2LDC_PRE: 1975 case ARM::t2LDCL_PRE: 1976 case ARM::t2STC_OFFSET: 1977 case ARM::t2STCL_OFFSET: 1978 case ARM::t2STC_PRE: 1979 case ARM::t2STCL_PRE: 1980 case ARM::LDC_OFFSET: 1981 case ARM::LDCL_OFFSET: 1982 case ARM::LDC_PRE: 1983 case ARM::LDCL_PRE: 1984 case ARM::STC_OFFSET: 1985 case ARM::STCL_OFFSET: 1986 case ARM::STC_PRE: 1987 case ARM::STCL_PRE: 1988 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1989 Inst.addOperand(MCOperand::createImm(imm)); 1990 break; 1991 case ARM::t2LDC2_POST: 1992 case ARM::t2LDC2L_POST: 1993 case ARM::t2STC2_POST: 1994 case ARM::t2STC2L_POST: 1995 case ARM::LDC2_POST: 1996 case ARM::LDC2L_POST: 1997 case ARM::STC2_POST: 1998 case ARM::STC2L_POST: 1999 case ARM::t2LDC_POST: 2000 case ARM::t2LDCL_POST: 2001 case ARM::t2STC_POST: 2002 case ARM::t2STCL_POST: 2003 case ARM::LDC_POST: 2004 case ARM::LDCL_POST: 2005 case ARM::STC_POST: 2006 case ARM::STCL_POST: 2007 imm |= U << 8; 2008 [[fallthrough]]; 2009 default: 2010 // The 'option' variant doesn't encode 'U' in the immediate since 2011 // the immediate is unsigned [0,255]. 2012 Inst.addOperand(MCOperand::createImm(imm)); 2013 break; 2014 } 2015 2016 switch (Inst.getOpcode()) { 2017 case ARM::LDC_OFFSET: 2018 case ARM::LDC_PRE: 2019 case ARM::LDC_POST: 2020 case ARM::LDC_OPTION: 2021 case ARM::LDCL_OFFSET: 2022 case ARM::LDCL_PRE: 2023 case ARM::LDCL_POST: 2024 case ARM::LDCL_OPTION: 2025 case ARM::STC_OFFSET: 2026 case ARM::STC_PRE: 2027 case ARM::STC_POST: 2028 case ARM::STC_OPTION: 2029 case ARM::STCL_OFFSET: 2030 case ARM::STCL_PRE: 2031 case ARM::STCL_POST: 2032 case ARM::STCL_OPTION: 2033 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2034 return MCDisassembler::Fail; 2035 break; 2036 default: 2037 break; 2038 } 2039 2040 return S; 2041 } 2042 2043 static DecodeStatus 2044 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2045 const MCDisassembler *Decoder) { 2046 DecodeStatus S = MCDisassembler::Success; 2047 2048 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2049 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2050 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2051 unsigned imm = fieldFromInstruction(Insn, 0, 12); 2052 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2053 unsigned reg = fieldFromInstruction(Insn, 25, 1); 2054 unsigned P = fieldFromInstruction(Insn, 24, 1); 2055 unsigned W = fieldFromInstruction(Insn, 21, 1); 2056 2057 // On stores, the writeback operand precedes Rt. 2058 switch (Inst.getOpcode()) { 2059 case ARM::STR_POST_IMM: 2060 case ARM::STR_POST_REG: 2061 case ARM::STRB_POST_IMM: 2062 case ARM::STRB_POST_REG: 2063 case ARM::STRT_POST_REG: 2064 case ARM::STRT_POST_IMM: 2065 case ARM::STRBT_POST_REG: 2066 case ARM::STRBT_POST_IMM: 2067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2068 return MCDisassembler::Fail; 2069 break; 2070 default: 2071 break; 2072 } 2073 2074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2075 return MCDisassembler::Fail; 2076 2077 // On loads, the writeback operand comes after Rt. 2078 switch (Inst.getOpcode()) { 2079 case ARM::LDR_POST_IMM: 2080 case ARM::LDR_POST_REG: 2081 case ARM::LDRB_POST_IMM: 2082 case ARM::LDRB_POST_REG: 2083 case ARM::LDRBT_POST_REG: 2084 case ARM::LDRBT_POST_IMM: 2085 case ARM::LDRT_POST_REG: 2086 case ARM::LDRT_POST_IMM: 2087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2088 return MCDisassembler::Fail; 2089 break; 2090 default: 2091 break; 2092 } 2093 2094 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2095 return MCDisassembler::Fail; 2096 2097 ARM_AM::AddrOpc Op = ARM_AM::add; 2098 if (!fieldFromInstruction(Insn, 23, 1)) 2099 Op = ARM_AM::sub; 2100 2101 bool writeback = (P == 0) || (W == 1); 2102 unsigned idx_mode = 0; 2103 if (P && writeback) 2104 idx_mode = ARMII::IndexModePre; 2105 else if (!P && writeback) 2106 idx_mode = ARMII::IndexModePost; 2107 2108 if (writeback && (Rn == 15 || Rn == Rt)) 2109 S = MCDisassembler::SoftFail; // UNPREDICTABLE 2110 2111 if (reg) { 2112 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2113 return MCDisassembler::Fail; 2114 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 2115 switch( fieldFromInstruction(Insn, 5, 2)) { 2116 case 0: 2117 Opc = ARM_AM::lsl; 2118 break; 2119 case 1: 2120 Opc = ARM_AM::lsr; 2121 break; 2122 case 2: 2123 Opc = ARM_AM::asr; 2124 break; 2125 case 3: 2126 Opc = ARM_AM::ror; 2127 break; 2128 default: 2129 return MCDisassembler::Fail; 2130 } 2131 unsigned amt = fieldFromInstruction(Insn, 7, 5); 2132 if (Opc == ARM_AM::ror && amt == 0) 2133 Opc = ARM_AM::rrx; 2134 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 2135 2136 Inst.addOperand(MCOperand::createImm(imm)); 2137 } else { 2138 Inst.addOperand(MCOperand::createReg(0)); 2139 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 2140 Inst.addOperand(MCOperand::createImm(tmp)); 2141 } 2142 2143 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2144 return MCDisassembler::Fail; 2145 2146 return S; 2147 } 2148 2149 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 2150 uint64_t Address, 2151 const MCDisassembler *Decoder) { 2152 DecodeStatus S = MCDisassembler::Success; 2153 2154 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2155 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2156 unsigned type = fieldFromInstruction(Val, 5, 2); 2157 unsigned imm = fieldFromInstruction(Val, 7, 5); 2158 unsigned U = fieldFromInstruction(Val, 12, 1); 2159 2160 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 2161 switch (type) { 2162 case 0: 2163 ShOp = ARM_AM::lsl; 2164 break; 2165 case 1: 2166 ShOp = ARM_AM::lsr; 2167 break; 2168 case 2: 2169 ShOp = ARM_AM::asr; 2170 break; 2171 case 3: 2172 ShOp = ARM_AM::ror; 2173 break; 2174 } 2175 2176 if (ShOp == ARM_AM::ror && imm == 0) 2177 ShOp = ARM_AM::rrx; 2178 2179 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2180 return MCDisassembler::Fail; 2181 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2182 return MCDisassembler::Fail; 2183 unsigned shift; 2184 if (U) 2185 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 2186 else 2187 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 2188 Inst.addOperand(MCOperand::createImm(shift)); 2189 2190 return S; 2191 } 2192 2193 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 2194 uint64_t Address, 2195 const MCDisassembler *Decoder) { 2196 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) 2197 return MCDisassembler::Fail; 2198 2199 // The "csync" operand is not encoded into the "tsb" instruction (as this is 2200 // the only available operand), but LLVM expects the instruction to have one 2201 // operand, so we need to add the csync when decoding. 2202 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC)); 2203 return MCDisassembler::Success; 2204 } 2205 2206 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 2207 uint64_t Address, 2208 const MCDisassembler *Decoder) { 2209 DecodeStatus S = MCDisassembler::Success; 2210 2211 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2212 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2213 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2214 unsigned type = fieldFromInstruction(Insn, 22, 1); 2215 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2216 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2217 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2218 unsigned W = fieldFromInstruction(Insn, 21, 1); 2219 unsigned P = fieldFromInstruction(Insn, 24, 1); 2220 unsigned Rt2 = Rt + 1; 2221 2222 bool writeback = (W == 1) | (P == 0); 2223 2224 // For {LD,ST}RD, Rt must be even, else undefined. 2225 switch (Inst.getOpcode()) { 2226 case ARM::STRD: 2227 case ARM::STRD_PRE: 2228 case ARM::STRD_POST: 2229 case ARM::LDRD: 2230 case ARM::LDRD_PRE: 2231 case ARM::LDRD_POST: 2232 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2233 break; 2234 default: 2235 break; 2236 } 2237 switch (Inst.getOpcode()) { 2238 case ARM::STRD: 2239 case ARM::STRD_PRE: 2240 case ARM::STRD_POST: 2241 if (P == 0 && W == 1) 2242 S = MCDisassembler::SoftFail; 2243 2244 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2245 S = MCDisassembler::SoftFail; 2246 if (type && Rm == 15) 2247 S = MCDisassembler::SoftFail; 2248 if (Rt2 == 15) 2249 S = MCDisassembler::SoftFail; 2250 if (!type && fieldFromInstruction(Insn, 8, 4)) 2251 S = MCDisassembler::SoftFail; 2252 break; 2253 case ARM::STRH: 2254 case ARM::STRH_PRE: 2255 case ARM::STRH_POST: 2256 if (Rt == 15) 2257 S = MCDisassembler::SoftFail; 2258 if (writeback && (Rn == 15 || Rn == Rt)) 2259 S = MCDisassembler::SoftFail; 2260 if (!type && Rm == 15) 2261 S = MCDisassembler::SoftFail; 2262 break; 2263 case ARM::LDRD: 2264 case ARM::LDRD_PRE: 2265 case ARM::LDRD_POST: 2266 if (type && Rn == 15) { 2267 if (Rt2 == 15) 2268 S = MCDisassembler::SoftFail; 2269 break; 2270 } 2271 if (P == 0 && W == 1) 2272 S = MCDisassembler::SoftFail; 2273 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2274 S = MCDisassembler::SoftFail; 2275 if (!type && writeback && Rn == 15) 2276 S = MCDisassembler::SoftFail; 2277 if (writeback && (Rn == Rt || Rn == Rt2)) 2278 S = MCDisassembler::SoftFail; 2279 break; 2280 case ARM::LDRH: 2281 case ARM::LDRH_PRE: 2282 case ARM::LDRH_POST: 2283 if (type && Rn == 15) { 2284 if (Rt == 15) 2285 S = MCDisassembler::SoftFail; 2286 break; 2287 } 2288 if (Rt == 15) 2289 S = MCDisassembler::SoftFail; 2290 if (!type && Rm == 15) 2291 S = MCDisassembler::SoftFail; 2292 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2293 S = MCDisassembler::SoftFail; 2294 break; 2295 case ARM::LDRSH: 2296 case ARM::LDRSH_PRE: 2297 case ARM::LDRSH_POST: 2298 case ARM::LDRSB: 2299 case ARM::LDRSB_PRE: 2300 case ARM::LDRSB_POST: 2301 if (type && Rn == 15) { 2302 if (Rt == 15) 2303 S = MCDisassembler::SoftFail; 2304 break; 2305 } 2306 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2307 S = MCDisassembler::SoftFail; 2308 if (!type && (Rt == 15 || Rm == 15)) 2309 S = MCDisassembler::SoftFail; 2310 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2311 S = MCDisassembler::SoftFail; 2312 break; 2313 default: 2314 break; 2315 } 2316 2317 if (writeback) { // Writeback 2318 if (P) 2319 U |= ARMII::IndexModePre << 9; 2320 else 2321 U |= ARMII::IndexModePost << 9; 2322 2323 // On stores, the writeback operand precedes Rt. 2324 switch (Inst.getOpcode()) { 2325 case ARM::STRD: 2326 case ARM::STRD_PRE: 2327 case ARM::STRD_POST: 2328 case ARM::STRH: 2329 case ARM::STRH_PRE: 2330 case ARM::STRH_POST: 2331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2332 return MCDisassembler::Fail; 2333 break; 2334 default: 2335 break; 2336 } 2337 } 2338 2339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2340 return MCDisassembler::Fail; 2341 switch (Inst.getOpcode()) { 2342 case ARM::STRD: 2343 case ARM::STRD_PRE: 2344 case ARM::STRD_POST: 2345 case ARM::LDRD: 2346 case ARM::LDRD_PRE: 2347 case ARM::LDRD_POST: 2348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2349 return MCDisassembler::Fail; 2350 break; 2351 default: 2352 break; 2353 } 2354 2355 if (writeback) { 2356 // On loads, the writeback operand comes after Rt. 2357 switch (Inst.getOpcode()) { 2358 case ARM::LDRD: 2359 case ARM::LDRD_PRE: 2360 case ARM::LDRD_POST: 2361 case ARM::LDRH: 2362 case ARM::LDRH_PRE: 2363 case ARM::LDRH_POST: 2364 case ARM::LDRSH: 2365 case ARM::LDRSH_PRE: 2366 case ARM::LDRSH_POST: 2367 case ARM::LDRSB: 2368 case ARM::LDRSB_PRE: 2369 case ARM::LDRSB_POST: 2370 case ARM::LDRHTr: 2371 case ARM::LDRSBTr: 2372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2373 return MCDisassembler::Fail; 2374 break; 2375 default: 2376 break; 2377 } 2378 } 2379 2380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2381 return MCDisassembler::Fail; 2382 2383 if (type) { 2384 Inst.addOperand(MCOperand::createReg(0)); 2385 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2386 } else { 2387 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2388 return MCDisassembler::Fail; 2389 Inst.addOperand(MCOperand::createImm(U)); 2390 } 2391 2392 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2393 return MCDisassembler::Fail; 2394 2395 return S; 2396 } 2397 2398 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2399 uint64_t Address, 2400 const MCDisassembler *Decoder) { 2401 DecodeStatus S = MCDisassembler::Success; 2402 2403 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2404 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2405 2406 switch (mode) { 2407 case 0: 2408 mode = ARM_AM::da; 2409 break; 2410 case 1: 2411 mode = ARM_AM::ia; 2412 break; 2413 case 2: 2414 mode = ARM_AM::db; 2415 break; 2416 case 3: 2417 mode = ARM_AM::ib; 2418 break; 2419 } 2420 2421 Inst.addOperand(MCOperand::createImm(mode)); 2422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2423 return MCDisassembler::Fail; 2424 2425 return S; 2426 } 2427 2428 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2429 uint64_t Address, 2430 const MCDisassembler *Decoder) { 2431 DecodeStatus S = MCDisassembler::Success; 2432 2433 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2434 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2435 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2436 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2437 2438 if (pred == 0xF) 2439 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2440 2441 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2442 return MCDisassembler::Fail; 2443 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2444 return MCDisassembler::Fail; 2445 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2446 return MCDisassembler::Fail; 2447 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2448 return MCDisassembler::Fail; 2449 return S; 2450 } 2451 2452 static DecodeStatus 2453 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 2454 uint64_t Address, 2455 const MCDisassembler *Decoder) { 2456 DecodeStatus S = MCDisassembler::Success; 2457 2458 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2459 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2460 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2461 2462 if (pred == 0xF) { 2463 // Ambiguous with RFE and SRS 2464 switch (Inst.getOpcode()) { 2465 case ARM::LDMDA: 2466 Inst.setOpcode(ARM::RFEDA); 2467 break; 2468 case ARM::LDMDA_UPD: 2469 Inst.setOpcode(ARM::RFEDA_UPD); 2470 break; 2471 case ARM::LDMDB: 2472 Inst.setOpcode(ARM::RFEDB); 2473 break; 2474 case ARM::LDMDB_UPD: 2475 Inst.setOpcode(ARM::RFEDB_UPD); 2476 break; 2477 case ARM::LDMIA: 2478 Inst.setOpcode(ARM::RFEIA); 2479 break; 2480 case ARM::LDMIA_UPD: 2481 Inst.setOpcode(ARM::RFEIA_UPD); 2482 break; 2483 case ARM::LDMIB: 2484 Inst.setOpcode(ARM::RFEIB); 2485 break; 2486 case ARM::LDMIB_UPD: 2487 Inst.setOpcode(ARM::RFEIB_UPD); 2488 break; 2489 case ARM::STMDA: 2490 Inst.setOpcode(ARM::SRSDA); 2491 break; 2492 case ARM::STMDA_UPD: 2493 Inst.setOpcode(ARM::SRSDA_UPD); 2494 break; 2495 case ARM::STMDB: 2496 Inst.setOpcode(ARM::SRSDB); 2497 break; 2498 case ARM::STMDB_UPD: 2499 Inst.setOpcode(ARM::SRSDB_UPD); 2500 break; 2501 case ARM::STMIA: 2502 Inst.setOpcode(ARM::SRSIA); 2503 break; 2504 case ARM::STMIA_UPD: 2505 Inst.setOpcode(ARM::SRSIA_UPD); 2506 break; 2507 case ARM::STMIB: 2508 Inst.setOpcode(ARM::SRSIB); 2509 break; 2510 case ARM::STMIB_UPD: 2511 Inst.setOpcode(ARM::SRSIB_UPD); 2512 break; 2513 default: 2514 return MCDisassembler::Fail; 2515 } 2516 2517 // For stores (which become SRS's, the only operand is the mode. 2518 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2519 // Check SRS encoding constraints 2520 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2521 fieldFromInstruction(Insn, 20, 1) == 0)) 2522 return MCDisassembler::Fail; 2523 2524 Inst.addOperand( 2525 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2526 return S; 2527 } 2528 2529 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2530 } 2531 2532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2533 return MCDisassembler::Fail; 2534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2535 return MCDisassembler::Fail; // Tied 2536 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2537 return MCDisassembler::Fail; 2538 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2539 return MCDisassembler::Fail; 2540 2541 return S; 2542 } 2543 2544 // Check for UNPREDICTABLE predicated ESB instruction 2545 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2546 uint64_t Address, 2547 const MCDisassembler *Decoder) { 2548 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2549 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2550 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2551 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2552 2553 DecodeStatus S = MCDisassembler::Success; 2554 2555 Inst.addOperand(MCOperand::createImm(imm8)); 2556 2557 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2558 return MCDisassembler::Fail; 2559 2560 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2561 // so all predicates should be allowed. 2562 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2563 S = MCDisassembler::SoftFail; 2564 2565 return S; 2566 } 2567 2568 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2569 uint64_t Address, 2570 const MCDisassembler *Decoder) { 2571 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2572 unsigned M = fieldFromInstruction(Insn, 17, 1); 2573 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2574 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2575 2576 DecodeStatus S = MCDisassembler::Success; 2577 2578 // This decoder is called from multiple location that do not check 2579 // the full encoding is valid before they do. 2580 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2581 fieldFromInstruction(Insn, 16, 1) != 0 || 2582 fieldFromInstruction(Insn, 20, 8) != 0x10) 2583 return MCDisassembler::Fail; 2584 2585 // imod == '01' --> UNPREDICTABLE 2586 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2587 // return failure here. The '01' imod value is unprintable, so there's 2588 // nothing useful we could do even if we returned UNPREDICTABLE. 2589 2590 if (imod == 1) return MCDisassembler::Fail; 2591 2592 if (imod && M) { 2593 Inst.setOpcode(ARM::CPS3p); 2594 Inst.addOperand(MCOperand::createImm(imod)); 2595 Inst.addOperand(MCOperand::createImm(iflags)); 2596 Inst.addOperand(MCOperand::createImm(mode)); 2597 } else if (imod && !M) { 2598 Inst.setOpcode(ARM::CPS2p); 2599 Inst.addOperand(MCOperand::createImm(imod)); 2600 Inst.addOperand(MCOperand::createImm(iflags)); 2601 if (mode) S = MCDisassembler::SoftFail; 2602 } else if (!imod && M) { 2603 Inst.setOpcode(ARM::CPS1p); 2604 Inst.addOperand(MCOperand::createImm(mode)); 2605 if (iflags) S = MCDisassembler::SoftFail; 2606 } else { 2607 // imod == '00' && M == '0' --> UNPREDICTABLE 2608 Inst.setOpcode(ARM::CPS1p); 2609 Inst.addOperand(MCOperand::createImm(mode)); 2610 S = MCDisassembler::SoftFail; 2611 } 2612 2613 return S; 2614 } 2615 2616 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2617 uint64_t Address, 2618 const MCDisassembler *Decoder) { 2619 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2620 unsigned M = fieldFromInstruction(Insn, 8, 1); 2621 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2622 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2623 2624 DecodeStatus S = MCDisassembler::Success; 2625 2626 // imod == '01' --> UNPREDICTABLE 2627 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2628 // return failure here. The '01' imod value is unprintable, so there's 2629 // nothing useful we could do even if we returned UNPREDICTABLE. 2630 2631 if (imod == 1) return MCDisassembler::Fail; 2632 2633 if (imod && M) { 2634 Inst.setOpcode(ARM::t2CPS3p); 2635 Inst.addOperand(MCOperand::createImm(imod)); 2636 Inst.addOperand(MCOperand::createImm(iflags)); 2637 Inst.addOperand(MCOperand::createImm(mode)); 2638 } else if (imod && !M) { 2639 Inst.setOpcode(ARM::t2CPS2p); 2640 Inst.addOperand(MCOperand::createImm(imod)); 2641 Inst.addOperand(MCOperand::createImm(iflags)); 2642 if (mode) S = MCDisassembler::SoftFail; 2643 } else if (!imod && M) { 2644 Inst.setOpcode(ARM::t2CPS1p); 2645 Inst.addOperand(MCOperand::createImm(mode)); 2646 if (iflags) S = MCDisassembler::SoftFail; 2647 } else { 2648 // imod == '00' && M == '0' --> this is a HINT instruction 2649 int imm = fieldFromInstruction(Insn, 0, 8); 2650 // HINT are defined only for immediate in [0..4] 2651 if(imm > 4) return MCDisassembler::Fail; 2652 Inst.setOpcode(ARM::t2HINT); 2653 Inst.addOperand(MCOperand::createImm(imm)); 2654 } 2655 2656 return S; 2657 } 2658 2659 static DecodeStatus 2660 DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2661 const MCDisassembler *Decoder) { 2662 unsigned imm = fieldFromInstruction(Insn, 0, 8); 2663 2664 unsigned Opcode = ARM::t2HINT; 2665 2666 if (imm == 0x0D) { 2667 Opcode = ARM::t2PACBTI; 2668 } else if (imm == 0x1D) { 2669 Opcode = ARM::t2PAC; 2670 } else if (imm == 0x2D) { 2671 Opcode = ARM::t2AUT; 2672 } else if (imm == 0x0F) { 2673 Opcode = ARM::t2BTI; 2674 } 2675 2676 Inst.setOpcode(Opcode); 2677 if (Opcode == ARM::t2HINT) { 2678 Inst.addOperand(MCOperand::createImm(imm)); 2679 } 2680 2681 return MCDisassembler::Success; 2682 } 2683 2684 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2685 uint64_t Address, 2686 const MCDisassembler *Decoder) { 2687 DecodeStatus S = MCDisassembler::Success; 2688 2689 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2690 unsigned imm = 0; 2691 2692 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2693 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2694 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2695 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2696 2697 if (Inst.getOpcode() == ARM::t2MOVTi16) 2698 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2699 return MCDisassembler::Fail; 2700 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2701 return MCDisassembler::Fail; 2702 2703 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2704 Inst.addOperand(MCOperand::createImm(imm)); 2705 2706 return S; 2707 } 2708 2709 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2710 uint64_t Address, 2711 const MCDisassembler *Decoder) { 2712 DecodeStatus S = MCDisassembler::Success; 2713 2714 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2715 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2716 unsigned imm = 0; 2717 2718 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2719 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2720 2721 if (Inst.getOpcode() == ARM::MOVTi16) 2722 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2723 return MCDisassembler::Fail; 2724 2725 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2726 return MCDisassembler::Fail; 2727 2728 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2729 Inst.addOperand(MCOperand::createImm(imm)); 2730 2731 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2732 return MCDisassembler::Fail; 2733 2734 return S; 2735 } 2736 2737 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2738 uint64_t Address, 2739 const MCDisassembler *Decoder) { 2740 DecodeStatus S = MCDisassembler::Success; 2741 2742 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2743 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2744 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2745 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2746 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2747 2748 if (pred == 0xF) 2749 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2750 2751 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2752 return MCDisassembler::Fail; 2753 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2754 return MCDisassembler::Fail; 2755 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2756 return MCDisassembler::Fail; 2757 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2758 return MCDisassembler::Fail; 2759 2760 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2761 return MCDisassembler::Fail; 2762 2763 return S; 2764 } 2765 2766 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2767 uint64_t Address, 2768 const MCDisassembler *Decoder) { 2769 DecodeStatus S = MCDisassembler::Success; 2770 2771 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2772 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2773 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2774 2775 if (Pred == 0xF) 2776 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2777 2778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2779 return MCDisassembler::Fail; 2780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2781 return MCDisassembler::Fail; 2782 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2783 return MCDisassembler::Fail; 2784 2785 return S; 2786 } 2787 2788 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2789 uint64_t Address, 2790 const MCDisassembler *Decoder) { 2791 DecodeStatus S = MCDisassembler::Success; 2792 2793 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2794 2795 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2796 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2797 2798 if (!FeatureBits[ARM::HasV8_1aOps] || 2799 !FeatureBits[ARM::HasV8Ops]) 2800 return MCDisassembler::Fail; 2801 2802 // Decoder can be called from DecodeTST, which does not check the full 2803 // encoding is valid. 2804 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2805 fieldFromInstruction(Insn, 4,4) != 0) 2806 return MCDisassembler::Fail; 2807 if (fieldFromInstruction(Insn, 10,10) != 0 || 2808 fieldFromInstruction(Insn, 0,4) != 0) 2809 S = MCDisassembler::SoftFail; 2810 2811 Inst.setOpcode(ARM::SETPAN); 2812 Inst.addOperand(MCOperand::createImm(Imm)); 2813 2814 return S; 2815 } 2816 2817 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2818 uint64_t Address, 2819 const MCDisassembler *Decoder) { 2820 DecodeStatus S = MCDisassembler::Success; 2821 2822 unsigned add = fieldFromInstruction(Val, 12, 1); 2823 unsigned imm = fieldFromInstruction(Val, 0, 12); 2824 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2825 2826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2827 return MCDisassembler::Fail; 2828 2829 if (!add) imm *= -1; 2830 if (imm == 0 && !add) imm = INT32_MIN; 2831 Inst.addOperand(MCOperand::createImm(imm)); 2832 if (Rn == 15) 2833 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2834 2835 return S; 2836 } 2837 2838 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2839 uint64_t Address, 2840 const MCDisassembler *Decoder) { 2841 DecodeStatus S = MCDisassembler::Success; 2842 2843 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2844 // U == 1 to add imm, 0 to subtract it. 2845 unsigned U = fieldFromInstruction(Val, 8, 1); 2846 unsigned imm = fieldFromInstruction(Val, 0, 8); 2847 2848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2849 return MCDisassembler::Fail; 2850 2851 if (U) 2852 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2853 else 2854 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2855 2856 return S; 2857 } 2858 2859 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2860 uint64_t Address, 2861 const MCDisassembler *Decoder) { 2862 DecodeStatus S = MCDisassembler::Success; 2863 2864 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2865 // U == 1 to add imm, 0 to subtract it. 2866 unsigned U = fieldFromInstruction(Val, 8, 1); 2867 unsigned imm = fieldFromInstruction(Val, 0, 8); 2868 2869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2870 return MCDisassembler::Fail; 2871 2872 if (U) 2873 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2874 else 2875 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2876 2877 return S; 2878 } 2879 2880 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2881 uint64_t Address, 2882 const MCDisassembler *Decoder) { 2883 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2884 } 2885 2886 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2887 uint64_t Address, 2888 const MCDisassembler *Decoder) { 2889 DecodeStatus Status = MCDisassembler::Success; 2890 2891 // Note the J1 and J2 values are from the encoded instruction. So here 2892 // change them to I1 and I2 values via as documented: 2893 // I1 = NOT(J1 EOR S); 2894 // I2 = NOT(J2 EOR S); 2895 // and build the imm32 with one trailing zero as documented: 2896 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2897 unsigned S = fieldFromInstruction(Insn, 26, 1); 2898 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2899 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2900 unsigned I1 = !(J1 ^ S); 2901 unsigned I2 = !(J2 ^ S); 2902 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2903 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2904 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2905 int imm32 = SignExtend32<25>(tmp << 1); 2906 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2907 true, 4, Inst, Decoder)) 2908 Inst.addOperand(MCOperand::createImm(imm32)); 2909 2910 return Status; 2911 } 2912 2913 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2914 uint64_t Address, 2915 const MCDisassembler *Decoder) { 2916 DecodeStatus S = MCDisassembler::Success; 2917 2918 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2919 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2920 2921 if (pred == 0xF) { 2922 Inst.setOpcode(ARM::BLXi); 2923 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2924 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2925 true, 4, Inst, Decoder)) 2926 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2927 return S; 2928 } 2929 2930 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2931 true, 4, Inst, Decoder)) 2932 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2933 2934 // We already have BL_pred for BL w/ predicate, no need to add addition 2935 // predicate opreands for BL 2936 if (Inst.getOpcode() != ARM::BL) 2937 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2938 return MCDisassembler::Fail; 2939 2940 return S; 2941 } 2942 2943 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2944 uint64_t Address, 2945 const MCDisassembler *Decoder) { 2946 DecodeStatus S = MCDisassembler::Success; 2947 2948 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2949 unsigned align = fieldFromInstruction(Val, 4, 2); 2950 2951 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2952 return MCDisassembler::Fail; 2953 if (!align) 2954 Inst.addOperand(MCOperand::createImm(0)); 2955 else 2956 Inst.addOperand(MCOperand::createImm(4 << align)); 2957 2958 return S; 2959 } 2960 2961 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2962 uint64_t Address, 2963 const MCDisassembler *Decoder) { 2964 DecodeStatus S = MCDisassembler::Success; 2965 2966 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2967 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2968 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2969 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2970 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2971 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2972 2973 // First output register 2974 switch (Inst.getOpcode()) { 2975 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2976 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2977 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2978 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2979 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2980 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2981 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2982 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2983 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2984 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2985 return MCDisassembler::Fail; 2986 break; 2987 case ARM::VLD2b16: 2988 case ARM::VLD2b32: 2989 case ARM::VLD2b8: 2990 case ARM::VLD2b16wb_fixed: 2991 case ARM::VLD2b16wb_register: 2992 case ARM::VLD2b32wb_fixed: 2993 case ARM::VLD2b32wb_register: 2994 case ARM::VLD2b8wb_fixed: 2995 case ARM::VLD2b8wb_register: 2996 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2997 return MCDisassembler::Fail; 2998 break; 2999 default: 3000 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3001 return MCDisassembler::Fail; 3002 } 3003 3004 // Second output register 3005 switch (Inst.getOpcode()) { 3006 case ARM::VLD3d8: 3007 case ARM::VLD3d16: 3008 case ARM::VLD3d32: 3009 case ARM::VLD3d8_UPD: 3010 case ARM::VLD3d16_UPD: 3011 case ARM::VLD3d32_UPD: 3012 case ARM::VLD4d8: 3013 case ARM::VLD4d16: 3014 case ARM::VLD4d32: 3015 case ARM::VLD4d8_UPD: 3016 case ARM::VLD4d16_UPD: 3017 case ARM::VLD4d32_UPD: 3018 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3019 return MCDisassembler::Fail; 3020 break; 3021 case ARM::VLD3q8: 3022 case ARM::VLD3q16: 3023 case ARM::VLD3q32: 3024 case ARM::VLD3q8_UPD: 3025 case ARM::VLD3q16_UPD: 3026 case ARM::VLD3q32_UPD: 3027 case ARM::VLD4q8: 3028 case ARM::VLD4q16: 3029 case ARM::VLD4q32: 3030 case ARM::VLD4q8_UPD: 3031 case ARM::VLD4q16_UPD: 3032 case ARM::VLD4q32_UPD: 3033 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3034 return MCDisassembler::Fail; 3035 break; 3036 default: 3037 break; 3038 } 3039 3040 // Third output register 3041 switch(Inst.getOpcode()) { 3042 case ARM::VLD3d8: 3043 case ARM::VLD3d16: 3044 case ARM::VLD3d32: 3045 case ARM::VLD3d8_UPD: 3046 case ARM::VLD3d16_UPD: 3047 case ARM::VLD3d32_UPD: 3048 case ARM::VLD4d8: 3049 case ARM::VLD4d16: 3050 case ARM::VLD4d32: 3051 case ARM::VLD4d8_UPD: 3052 case ARM::VLD4d16_UPD: 3053 case ARM::VLD4d32_UPD: 3054 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3055 return MCDisassembler::Fail; 3056 break; 3057 case ARM::VLD3q8: 3058 case ARM::VLD3q16: 3059 case ARM::VLD3q32: 3060 case ARM::VLD3q8_UPD: 3061 case ARM::VLD3q16_UPD: 3062 case ARM::VLD3q32_UPD: 3063 case ARM::VLD4q8: 3064 case ARM::VLD4q16: 3065 case ARM::VLD4q32: 3066 case ARM::VLD4q8_UPD: 3067 case ARM::VLD4q16_UPD: 3068 case ARM::VLD4q32_UPD: 3069 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3070 return MCDisassembler::Fail; 3071 break; 3072 default: 3073 break; 3074 } 3075 3076 // Fourth output register 3077 switch (Inst.getOpcode()) { 3078 case ARM::VLD4d8: 3079 case ARM::VLD4d16: 3080 case ARM::VLD4d32: 3081 case ARM::VLD4d8_UPD: 3082 case ARM::VLD4d16_UPD: 3083 case ARM::VLD4d32_UPD: 3084 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3085 return MCDisassembler::Fail; 3086 break; 3087 case ARM::VLD4q8: 3088 case ARM::VLD4q16: 3089 case ARM::VLD4q32: 3090 case ARM::VLD4q8_UPD: 3091 case ARM::VLD4q16_UPD: 3092 case ARM::VLD4q32_UPD: 3093 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3094 return MCDisassembler::Fail; 3095 break; 3096 default: 3097 break; 3098 } 3099 3100 // Writeback operand 3101 switch (Inst.getOpcode()) { 3102 case ARM::VLD1d8wb_fixed: 3103 case ARM::VLD1d16wb_fixed: 3104 case ARM::VLD1d32wb_fixed: 3105 case ARM::VLD1d64wb_fixed: 3106 case ARM::VLD1d8wb_register: 3107 case ARM::VLD1d16wb_register: 3108 case ARM::VLD1d32wb_register: 3109 case ARM::VLD1d64wb_register: 3110 case ARM::VLD1q8wb_fixed: 3111 case ARM::VLD1q16wb_fixed: 3112 case ARM::VLD1q32wb_fixed: 3113 case ARM::VLD1q64wb_fixed: 3114 case ARM::VLD1q8wb_register: 3115 case ARM::VLD1q16wb_register: 3116 case ARM::VLD1q32wb_register: 3117 case ARM::VLD1q64wb_register: 3118 case ARM::VLD1d8Twb_fixed: 3119 case ARM::VLD1d8Twb_register: 3120 case ARM::VLD1d16Twb_fixed: 3121 case ARM::VLD1d16Twb_register: 3122 case ARM::VLD1d32Twb_fixed: 3123 case ARM::VLD1d32Twb_register: 3124 case ARM::VLD1d64Twb_fixed: 3125 case ARM::VLD1d64Twb_register: 3126 case ARM::VLD1d8Qwb_fixed: 3127 case ARM::VLD1d8Qwb_register: 3128 case ARM::VLD1d16Qwb_fixed: 3129 case ARM::VLD1d16Qwb_register: 3130 case ARM::VLD1d32Qwb_fixed: 3131 case ARM::VLD1d32Qwb_register: 3132 case ARM::VLD1d64Qwb_fixed: 3133 case ARM::VLD1d64Qwb_register: 3134 case ARM::VLD2d8wb_fixed: 3135 case ARM::VLD2d16wb_fixed: 3136 case ARM::VLD2d32wb_fixed: 3137 case ARM::VLD2q8wb_fixed: 3138 case ARM::VLD2q16wb_fixed: 3139 case ARM::VLD2q32wb_fixed: 3140 case ARM::VLD2d8wb_register: 3141 case ARM::VLD2d16wb_register: 3142 case ARM::VLD2d32wb_register: 3143 case ARM::VLD2q8wb_register: 3144 case ARM::VLD2q16wb_register: 3145 case ARM::VLD2q32wb_register: 3146 case ARM::VLD2b8wb_fixed: 3147 case ARM::VLD2b16wb_fixed: 3148 case ARM::VLD2b32wb_fixed: 3149 case ARM::VLD2b8wb_register: 3150 case ARM::VLD2b16wb_register: 3151 case ARM::VLD2b32wb_register: 3152 Inst.addOperand(MCOperand::createImm(0)); 3153 break; 3154 case ARM::VLD3d8_UPD: 3155 case ARM::VLD3d16_UPD: 3156 case ARM::VLD3d32_UPD: 3157 case ARM::VLD3q8_UPD: 3158 case ARM::VLD3q16_UPD: 3159 case ARM::VLD3q32_UPD: 3160 case ARM::VLD4d8_UPD: 3161 case ARM::VLD4d16_UPD: 3162 case ARM::VLD4d32_UPD: 3163 case ARM::VLD4q8_UPD: 3164 case ARM::VLD4q16_UPD: 3165 case ARM::VLD4q32_UPD: 3166 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3167 return MCDisassembler::Fail; 3168 break; 3169 default: 3170 break; 3171 } 3172 3173 // AddrMode6 Base (register+alignment) 3174 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3175 return MCDisassembler::Fail; 3176 3177 // AddrMode6 Offset (register) 3178 switch (Inst.getOpcode()) { 3179 default: 3180 // The below have been updated to have explicit am6offset split 3181 // between fixed and register offset. For those instructions not 3182 // yet updated, we need to add an additional reg0 operand for the 3183 // fixed variant. 3184 // 3185 // The fixed offset encodes as Rm == 0xd, so we check for that. 3186 if (Rm == 0xd) { 3187 Inst.addOperand(MCOperand::createReg(0)); 3188 break; 3189 } 3190 // Fall through to handle the register offset variant. 3191 [[fallthrough]]; 3192 case ARM::VLD1d8wb_fixed: 3193 case ARM::VLD1d16wb_fixed: 3194 case ARM::VLD1d32wb_fixed: 3195 case ARM::VLD1d64wb_fixed: 3196 case ARM::VLD1d8Twb_fixed: 3197 case ARM::VLD1d16Twb_fixed: 3198 case ARM::VLD1d32Twb_fixed: 3199 case ARM::VLD1d64Twb_fixed: 3200 case ARM::VLD1d8Qwb_fixed: 3201 case ARM::VLD1d16Qwb_fixed: 3202 case ARM::VLD1d32Qwb_fixed: 3203 case ARM::VLD1d64Qwb_fixed: 3204 case ARM::VLD1d8wb_register: 3205 case ARM::VLD1d16wb_register: 3206 case ARM::VLD1d32wb_register: 3207 case ARM::VLD1d64wb_register: 3208 case ARM::VLD1q8wb_fixed: 3209 case ARM::VLD1q16wb_fixed: 3210 case ARM::VLD1q32wb_fixed: 3211 case ARM::VLD1q64wb_fixed: 3212 case ARM::VLD1q8wb_register: 3213 case ARM::VLD1q16wb_register: 3214 case ARM::VLD1q32wb_register: 3215 case ARM::VLD1q64wb_register: 3216 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3217 // variant encodes Rm == 0xf. Anything else is a register offset post- 3218 // increment and we need to add the register operand to the instruction. 3219 if (Rm != 0xD && Rm != 0xF && 3220 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3221 return MCDisassembler::Fail; 3222 break; 3223 case ARM::VLD2d8wb_fixed: 3224 case ARM::VLD2d16wb_fixed: 3225 case ARM::VLD2d32wb_fixed: 3226 case ARM::VLD2b8wb_fixed: 3227 case ARM::VLD2b16wb_fixed: 3228 case ARM::VLD2b32wb_fixed: 3229 case ARM::VLD2q8wb_fixed: 3230 case ARM::VLD2q16wb_fixed: 3231 case ARM::VLD2q32wb_fixed: 3232 break; 3233 } 3234 3235 return S; 3236 } 3237 3238 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 3239 uint64_t Address, 3240 const MCDisassembler *Decoder) { 3241 unsigned type = fieldFromInstruction(Insn, 8, 4); 3242 unsigned align = fieldFromInstruction(Insn, 4, 2); 3243 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 3244 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 3245 if (type == 10 && align == 3) return MCDisassembler::Fail; 3246 3247 unsigned load = fieldFromInstruction(Insn, 21, 1); 3248 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3249 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3250 } 3251 3252 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 3253 uint64_t Address, 3254 const MCDisassembler *Decoder) { 3255 unsigned size = fieldFromInstruction(Insn, 6, 2); 3256 if (size == 3) return MCDisassembler::Fail; 3257 3258 unsigned type = fieldFromInstruction(Insn, 8, 4); 3259 unsigned align = fieldFromInstruction(Insn, 4, 2); 3260 if (type == 8 && align == 3) return MCDisassembler::Fail; 3261 if (type == 9 && align == 3) return MCDisassembler::Fail; 3262 3263 unsigned load = fieldFromInstruction(Insn, 21, 1); 3264 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3265 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3266 } 3267 3268 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3269 uint64_t Address, 3270 const MCDisassembler *Decoder) { 3271 unsigned size = fieldFromInstruction(Insn, 6, 2); 3272 if (size == 3) return MCDisassembler::Fail; 3273 3274 unsigned align = fieldFromInstruction(Insn, 4, 2); 3275 if (align & 2) return MCDisassembler::Fail; 3276 3277 unsigned load = fieldFromInstruction(Insn, 21, 1); 3278 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3279 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3280 } 3281 3282 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3283 uint64_t Address, 3284 const MCDisassembler *Decoder) { 3285 unsigned size = fieldFromInstruction(Insn, 6, 2); 3286 if (size == 3) return MCDisassembler::Fail; 3287 3288 unsigned load = fieldFromInstruction(Insn, 21, 1); 3289 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3290 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3291 } 3292 3293 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3294 uint64_t Address, 3295 const MCDisassembler *Decoder) { 3296 DecodeStatus S = MCDisassembler::Success; 3297 3298 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3299 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3300 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3301 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3302 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3303 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3304 3305 // Writeback Operand 3306 switch (Inst.getOpcode()) { 3307 case ARM::VST1d8wb_fixed: 3308 case ARM::VST1d16wb_fixed: 3309 case ARM::VST1d32wb_fixed: 3310 case ARM::VST1d64wb_fixed: 3311 case ARM::VST1d8wb_register: 3312 case ARM::VST1d16wb_register: 3313 case ARM::VST1d32wb_register: 3314 case ARM::VST1d64wb_register: 3315 case ARM::VST1q8wb_fixed: 3316 case ARM::VST1q16wb_fixed: 3317 case ARM::VST1q32wb_fixed: 3318 case ARM::VST1q64wb_fixed: 3319 case ARM::VST1q8wb_register: 3320 case ARM::VST1q16wb_register: 3321 case ARM::VST1q32wb_register: 3322 case ARM::VST1q64wb_register: 3323 case ARM::VST1d8Twb_fixed: 3324 case ARM::VST1d16Twb_fixed: 3325 case ARM::VST1d32Twb_fixed: 3326 case ARM::VST1d64Twb_fixed: 3327 case ARM::VST1d8Twb_register: 3328 case ARM::VST1d16Twb_register: 3329 case ARM::VST1d32Twb_register: 3330 case ARM::VST1d64Twb_register: 3331 case ARM::VST1d8Qwb_fixed: 3332 case ARM::VST1d16Qwb_fixed: 3333 case ARM::VST1d32Qwb_fixed: 3334 case ARM::VST1d64Qwb_fixed: 3335 case ARM::VST1d8Qwb_register: 3336 case ARM::VST1d16Qwb_register: 3337 case ARM::VST1d32Qwb_register: 3338 case ARM::VST1d64Qwb_register: 3339 case ARM::VST2d8wb_fixed: 3340 case ARM::VST2d16wb_fixed: 3341 case ARM::VST2d32wb_fixed: 3342 case ARM::VST2d8wb_register: 3343 case ARM::VST2d16wb_register: 3344 case ARM::VST2d32wb_register: 3345 case ARM::VST2q8wb_fixed: 3346 case ARM::VST2q16wb_fixed: 3347 case ARM::VST2q32wb_fixed: 3348 case ARM::VST2q8wb_register: 3349 case ARM::VST2q16wb_register: 3350 case ARM::VST2q32wb_register: 3351 case ARM::VST2b8wb_fixed: 3352 case ARM::VST2b16wb_fixed: 3353 case ARM::VST2b32wb_fixed: 3354 case ARM::VST2b8wb_register: 3355 case ARM::VST2b16wb_register: 3356 case ARM::VST2b32wb_register: 3357 if (Rm == 0xF) 3358 return MCDisassembler::Fail; 3359 Inst.addOperand(MCOperand::createImm(0)); 3360 break; 3361 case ARM::VST3d8_UPD: 3362 case ARM::VST3d16_UPD: 3363 case ARM::VST3d32_UPD: 3364 case ARM::VST3q8_UPD: 3365 case ARM::VST3q16_UPD: 3366 case ARM::VST3q32_UPD: 3367 case ARM::VST4d8_UPD: 3368 case ARM::VST4d16_UPD: 3369 case ARM::VST4d32_UPD: 3370 case ARM::VST4q8_UPD: 3371 case ARM::VST4q16_UPD: 3372 case ARM::VST4q32_UPD: 3373 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3374 return MCDisassembler::Fail; 3375 break; 3376 default: 3377 break; 3378 } 3379 3380 // AddrMode6 Base (register+alignment) 3381 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3382 return MCDisassembler::Fail; 3383 3384 // AddrMode6 Offset (register) 3385 switch (Inst.getOpcode()) { 3386 default: 3387 if (Rm == 0xD) 3388 Inst.addOperand(MCOperand::createReg(0)); 3389 else if (Rm != 0xF) { 3390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3391 return MCDisassembler::Fail; 3392 } 3393 break; 3394 case ARM::VST1d8wb_fixed: 3395 case ARM::VST1d16wb_fixed: 3396 case ARM::VST1d32wb_fixed: 3397 case ARM::VST1d64wb_fixed: 3398 case ARM::VST1q8wb_fixed: 3399 case ARM::VST1q16wb_fixed: 3400 case ARM::VST1q32wb_fixed: 3401 case ARM::VST1q64wb_fixed: 3402 case ARM::VST1d8Twb_fixed: 3403 case ARM::VST1d16Twb_fixed: 3404 case ARM::VST1d32Twb_fixed: 3405 case ARM::VST1d64Twb_fixed: 3406 case ARM::VST1d8Qwb_fixed: 3407 case ARM::VST1d16Qwb_fixed: 3408 case ARM::VST1d32Qwb_fixed: 3409 case ARM::VST1d64Qwb_fixed: 3410 case ARM::VST2d8wb_fixed: 3411 case ARM::VST2d16wb_fixed: 3412 case ARM::VST2d32wb_fixed: 3413 case ARM::VST2q8wb_fixed: 3414 case ARM::VST2q16wb_fixed: 3415 case ARM::VST2q32wb_fixed: 3416 case ARM::VST2b8wb_fixed: 3417 case ARM::VST2b16wb_fixed: 3418 case ARM::VST2b32wb_fixed: 3419 break; 3420 } 3421 3422 // First input register 3423 switch (Inst.getOpcode()) { 3424 case ARM::VST1q16: 3425 case ARM::VST1q32: 3426 case ARM::VST1q64: 3427 case ARM::VST1q8: 3428 case ARM::VST1q16wb_fixed: 3429 case ARM::VST1q16wb_register: 3430 case ARM::VST1q32wb_fixed: 3431 case ARM::VST1q32wb_register: 3432 case ARM::VST1q64wb_fixed: 3433 case ARM::VST1q64wb_register: 3434 case ARM::VST1q8wb_fixed: 3435 case ARM::VST1q8wb_register: 3436 case ARM::VST2d16: 3437 case ARM::VST2d32: 3438 case ARM::VST2d8: 3439 case ARM::VST2d16wb_fixed: 3440 case ARM::VST2d16wb_register: 3441 case ARM::VST2d32wb_fixed: 3442 case ARM::VST2d32wb_register: 3443 case ARM::VST2d8wb_fixed: 3444 case ARM::VST2d8wb_register: 3445 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3446 return MCDisassembler::Fail; 3447 break; 3448 case ARM::VST2b16: 3449 case ARM::VST2b32: 3450 case ARM::VST2b8: 3451 case ARM::VST2b16wb_fixed: 3452 case ARM::VST2b16wb_register: 3453 case ARM::VST2b32wb_fixed: 3454 case ARM::VST2b32wb_register: 3455 case ARM::VST2b8wb_fixed: 3456 case ARM::VST2b8wb_register: 3457 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3458 return MCDisassembler::Fail; 3459 break; 3460 default: 3461 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3462 return MCDisassembler::Fail; 3463 } 3464 3465 // Second input register 3466 switch (Inst.getOpcode()) { 3467 case ARM::VST3d8: 3468 case ARM::VST3d16: 3469 case ARM::VST3d32: 3470 case ARM::VST3d8_UPD: 3471 case ARM::VST3d16_UPD: 3472 case ARM::VST3d32_UPD: 3473 case ARM::VST4d8: 3474 case ARM::VST4d16: 3475 case ARM::VST4d32: 3476 case ARM::VST4d8_UPD: 3477 case ARM::VST4d16_UPD: 3478 case ARM::VST4d32_UPD: 3479 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3480 return MCDisassembler::Fail; 3481 break; 3482 case ARM::VST3q8: 3483 case ARM::VST3q16: 3484 case ARM::VST3q32: 3485 case ARM::VST3q8_UPD: 3486 case ARM::VST3q16_UPD: 3487 case ARM::VST3q32_UPD: 3488 case ARM::VST4q8: 3489 case ARM::VST4q16: 3490 case ARM::VST4q32: 3491 case ARM::VST4q8_UPD: 3492 case ARM::VST4q16_UPD: 3493 case ARM::VST4q32_UPD: 3494 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3495 return MCDisassembler::Fail; 3496 break; 3497 default: 3498 break; 3499 } 3500 3501 // Third input register 3502 switch (Inst.getOpcode()) { 3503 case ARM::VST3d8: 3504 case ARM::VST3d16: 3505 case ARM::VST3d32: 3506 case ARM::VST3d8_UPD: 3507 case ARM::VST3d16_UPD: 3508 case ARM::VST3d32_UPD: 3509 case ARM::VST4d8: 3510 case ARM::VST4d16: 3511 case ARM::VST4d32: 3512 case ARM::VST4d8_UPD: 3513 case ARM::VST4d16_UPD: 3514 case ARM::VST4d32_UPD: 3515 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3516 return MCDisassembler::Fail; 3517 break; 3518 case ARM::VST3q8: 3519 case ARM::VST3q16: 3520 case ARM::VST3q32: 3521 case ARM::VST3q8_UPD: 3522 case ARM::VST3q16_UPD: 3523 case ARM::VST3q32_UPD: 3524 case ARM::VST4q8: 3525 case ARM::VST4q16: 3526 case ARM::VST4q32: 3527 case ARM::VST4q8_UPD: 3528 case ARM::VST4q16_UPD: 3529 case ARM::VST4q32_UPD: 3530 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 break; 3533 default: 3534 break; 3535 } 3536 3537 // Fourth input register 3538 switch (Inst.getOpcode()) { 3539 case ARM::VST4d8: 3540 case ARM::VST4d16: 3541 case ARM::VST4d32: 3542 case ARM::VST4d8_UPD: 3543 case ARM::VST4d16_UPD: 3544 case ARM::VST4d32_UPD: 3545 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3546 return MCDisassembler::Fail; 3547 break; 3548 case ARM::VST4q8: 3549 case ARM::VST4q16: 3550 case ARM::VST4q32: 3551 case ARM::VST4q8_UPD: 3552 case ARM::VST4q16_UPD: 3553 case ARM::VST4q32_UPD: 3554 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3555 return MCDisassembler::Fail; 3556 break; 3557 default: 3558 break; 3559 } 3560 3561 return S; 3562 } 3563 3564 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3565 uint64_t Address, 3566 const MCDisassembler *Decoder) { 3567 DecodeStatus S = MCDisassembler::Success; 3568 3569 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3570 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3571 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3572 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3573 unsigned align = fieldFromInstruction(Insn, 4, 1); 3574 unsigned size = fieldFromInstruction(Insn, 6, 2); 3575 3576 if (size == 0 && align == 1) 3577 return MCDisassembler::Fail; 3578 align *= (1 << size); 3579 3580 switch (Inst.getOpcode()) { 3581 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3582 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3583 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3584 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3585 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3586 return MCDisassembler::Fail; 3587 break; 3588 default: 3589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3590 return MCDisassembler::Fail; 3591 break; 3592 } 3593 if (Rm != 0xF) { 3594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3595 return MCDisassembler::Fail; 3596 } 3597 3598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3599 return MCDisassembler::Fail; 3600 Inst.addOperand(MCOperand::createImm(align)); 3601 3602 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3603 // variant encodes Rm == 0xf. Anything else is a register offset post- 3604 // increment and we need to add the register operand to the instruction. 3605 if (Rm != 0xD && Rm != 0xF && 3606 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3607 return MCDisassembler::Fail; 3608 3609 return S; 3610 } 3611 3612 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3613 uint64_t Address, 3614 const MCDisassembler *Decoder) { 3615 DecodeStatus S = MCDisassembler::Success; 3616 3617 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3618 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3619 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3620 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3621 unsigned align = fieldFromInstruction(Insn, 4, 1); 3622 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3623 align *= 2*size; 3624 3625 switch (Inst.getOpcode()) { 3626 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3627 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3628 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3629 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3630 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3631 return MCDisassembler::Fail; 3632 break; 3633 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3634 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3635 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3636 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3637 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3638 return MCDisassembler::Fail; 3639 break; 3640 default: 3641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3642 return MCDisassembler::Fail; 3643 break; 3644 } 3645 3646 if (Rm != 0xF) 3647 Inst.addOperand(MCOperand::createImm(0)); 3648 3649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3650 return MCDisassembler::Fail; 3651 Inst.addOperand(MCOperand::createImm(align)); 3652 3653 if (Rm != 0xD && Rm != 0xF) { 3654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3655 return MCDisassembler::Fail; 3656 } 3657 3658 return S; 3659 } 3660 3661 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3662 uint64_t Address, 3663 const MCDisassembler *Decoder) { 3664 DecodeStatus S = MCDisassembler::Success; 3665 3666 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3667 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3668 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3669 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3670 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3671 3672 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3673 return MCDisassembler::Fail; 3674 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3675 return MCDisassembler::Fail; 3676 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3677 return MCDisassembler::Fail; 3678 if (Rm != 0xF) { 3679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 } 3682 3683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3684 return MCDisassembler::Fail; 3685 Inst.addOperand(MCOperand::createImm(0)); 3686 3687 if (Rm == 0xD) 3688 Inst.addOperand(MCOperand::createReg(0)); 3689 else if (Rm != 0xF) { 3690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3691 return MCDisassembler::Fail; 3692 } 3693 3694 return S; 3695 } 3696 3697 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3698 uint64_t Address, 3699 const MCDisassembler *Decoder) { 3700 DecodeStatus S = MCDisassembler::Success; 3701 3702 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3703 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3704 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3705 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3706 unsigned size = fieldFromInstruction(Insn, 6, 2); 3707 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3708 unsigned align = fieldFromInstruction(Insn, 4, 1); 3709 3710 if (size == 0x3) { 3711 if (align == 0) 3712 return MCDisassembler::Fail; 3713 align = 16; 3714 } else { 3715 if (size == 2) { 3716 align *= 8; 3717 } else { 3718 size = 1 << size; 3719 align *= 4*size; 3720 } 3721 } 3722 3723 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3724 return MCDisassembler::Fail; 3725 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3726 return MCDisassembler::Fail; 3727 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3728 return MCDisassembler::Fail; 3729 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3730 return MCDisassembler::Fail; 3731 if (Rm != 0xF) { 3732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3733 return MCDisassembler::Fail; 3734 } 3735 3736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3737 return MCDisassembler::Fail; 3738 Inst.addOperand(MCOperand::createImm(align)); 3739 3740 if (Rm == 0xD) 3741 Inst.addOperand(MCOperand::createReg(0)); 3742 else if (Rm != 0xF) { 3743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3744 return MCDisassembler::Fail; 3745 } 3746 3747 return S; 3748 } 3749 3750 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3751 uint64_t Address, 3752 const MCDisassembler *Decoder) { 3753 DecodeStatus S = MCDisassembler::Success; 3754 3755 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3756 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3757 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3758 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3759 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3760 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3761 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3762 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3763 3764 if (Q) { 3765 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3766 return MCDisassembler::Fail; 3767 } else { 3768 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3769 return MCDisassembler::Fail; 3770 } 3771 3772 Inst.addOperand(MCOperand::createImm(imm)); 3773 3774 switch (Inst.getOpcode()) { 3775 case ARM::VORRiv4i16: 3776 case ARM::VORRiv2i32: 3777 case ARM::VBICiv4i16: 3778 case ARM::VBICiv2i32: 3779 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3780 return MCDisassembler::Fail; 3781 break; 3782 case ARM::VORRiv8i16: 3783 case ARM::VORRiv4i32: 3784 case ARM::VBICiv8i16: 3785 case ARM::VBICiv4i32: 3786 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3787 return MCDisassembler::Fail; 3788 break; 3789 default: 3790 break; 3791 } 3792 3793 return S; 3794 } 3795 3796 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3797 uint64_t Address, 3798 const MCDisassembler *Decoder) { 3799 DecodeStatus S = MCDisassembler::Success; 3800 3801 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3802 fieldFromInstruction(Insn, 13, 3)); 3803 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3804 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3805 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3806 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3807 imm |= cmode << 8; 3808 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3809 3810 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3811 return MCDisassembler::Fail; 3812 3813 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3814 return MCDisassembler::Fail; 3815 3816 Inst.addOperand(MCOperand::createImm(imm)); 3817 3818 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3819 Inst.addOperand(MCOperand::createReg(0)); 3820 Inst.addOperand(MCOperand::createImm(0)); 3821 3822 return S; 3823 } 3824 3825 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3826 uint64_t Address, 3827 const MCDisassembler *Decoder) { 3828 DecodeStatus S = MCDisassembler::Success; 3829 3830 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3831 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3832 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3833 return MCDisassembler::Fail; 3834 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3835 3836 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3837 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3838 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3839 return MCDisassembler::Fail; 3840 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3841 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3842 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3843 return MCDisassembler::Fail; 3844 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3845 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3846 Inst.addOperand(MCOperand::createImm(Qd)); 3847 3848 return S; 3849 } 3850 3851 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3852 uint64_t Address, 3853 const MCDisassembler *Decoder) { 3854 DecodeStatus S = MCDisassembler::Success; 3855 3856 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3857 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3858 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3859 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3860 unsigned size = fieldFromInstruction(Insn, 18, 2); 3861 3862 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3863 return MCDisassembler::Fail; 3864 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3865 return MCDisassembler::Fail; 3866 Inst.addOperand(MCOperand::createImm(8 << size)); 3867 3868 return S; 3869 } 3870 3871 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3872 uint64_t Address, 3873 const MCDisassembler *Decoder) { 3874 Inst.addOperand(MCOperand::createImm(8 - Val)); 3875 return MCDisassembler::Success; 3876 } 3877 3878 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3879 uint64_t Address, 3880 const MCDisassembler *Decoder) { 3881 Inst.addOperand(MCOperand::createImm(16 - Val)); 3882 return MCDisassembler::Success; 3883 } 3884 3885 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3886 uint64_t Address, 3887 const MCDisassembler *Decoder) { 3888 Inst.addOperand(MCOperand::createImm(32 - Val)); 3889 return MCDisassembler::Success; 3890 } 3891 3892 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3893 uint64_t Address, 3894 const MCDisassembler *Decoder) { 3895 Inst.addOperand(MCOperand::createImm(64 - Val)); 3896 return MCDisassembler::Success; 3897 } 3898 3899 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3900 uint64_t Address, 3901 const MCDisassembler *Decoder) { 3902 DecodeStatus S = MCDisassembler::Success; 3903 3904 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3905 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3906 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3907 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3908 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3909 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3910 unsigned op = fieldFromInstruction(Insn, 6, 1); 3911 3912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3913 return MCDisassembler::Fail; 3914 if (op) { 3915 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3916 return MCDisassembler::Fail; // Writeback 3917 } 3918 3919 switch (Inst.getOpcode()) { 3920 case ARM::VTBL2: 3921 case ARM::VTBX2: 3922 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3923 return MCDisassembler::Fail; 3924 break; 3925 default: 3926 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3927 return MCDisassembler::Fail; 3928 } 3929 3930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3931 return MCDisassembler::Fail; 3932 3933 return S; 3934 } 3935 3936 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3937 uint64_t Address, 3938 const MCDisassembler *Decoder) { 3939 DecodeStatus S = MCDisassembler::Success; 3940 3941 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3942 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3943 3944 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3945 return MCDisassembler::Fail; 3946 3947 switch(Inst.getOpcode()) { 3948 default: 3949 return MCDisassembler::Fail; 3950 case ARM::tADR: 3951 break; // tADR does not explicitly represent the PC as an operand. 3952 case ARM::tADDrSPi: 3953 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3954 break; 3955 } 3956 3957 Inst.addOperand(MCOperand::createImm(imm)); 3958 return S; 3959 } 3960 3961 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3962 uint64_t Address, 3963 const MCDisassembler *Decoder) { 3964 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3965 true, 2, Inst, Decoder)) 3966 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3967 return MCDisassembler::Success; 3968 } 3969 3970 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3971 uint64_t Address, 3972 const MCDisassembler *Decoder) { 3973 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3974 true, 4, Inst, Decoder)) 3975 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3976 return MCDisassembler::Success; 3977 } 3978 3979 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3980 uint64_t Address, 3981 const MCDisassembler *Decoder) { 3982 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3983 true, 2, Inst, Decoder)) 3984 Inst.addOperand(MCOperand::createImm(Val << 1)); 3985 return MCDisassembler::Success; 3986 } 3987 3988 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3989 uint64_t Address, 3990 const MCDisassembler *Decoder) { 3991 DecodeStatus S = MCDisassembler::Success; 3992 3993 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3994 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3995 3996 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3997 return MCDisassembler::Fail; 3998 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3999 return MCDisassembler::Fail; 4000 4001 return S; 4002 } 4003 4004 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 4005 uint64_t Address, 4006 const MCDisassembler *Decoder) { 4007 DecodeStatus S = MCDisassembler::Success; 4008 4009 unsigned Rn = fieldFromInstruction(Val, 0, 3); 4010 unsigned imm = fieldFromInstruction(Val, 3, 5); 4011 4012 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4013 return MCDisassembler::Fail; 4014 Inst.addOperand(MCOperand::createImm(imm)); 4015 4016 return S; 4017 } 4018 4019 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 4020 uint64_t Address, 4021 const MCDisassembler *Decoder) { 4022 unsigned imm = Val << 2; 4023 4024 Inst.addOperand(MCOperand::createImm(imm)); 4025 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 4026 4027 return MCDisassembler::Success; 4028 } 4029 4030 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 4031 uint64_t Address, 4032 const MCDisassembler *Decoder) { 4033 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4034 Inst.addOperand(MCOperand::createImm(Val)); 4035 4036 return MCDisassembler::Success; 4037 } 4038 4039 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 4040 uint64_t Address, 4041 const MCDisassembler *Decoder) { 4042 DecodeStatus S = MCDisassembler::Success; 4043 4044 unsigned Rn = fieldFromInstruction(Val, 6, 4); 4045 unsigned Rm = fieldFromInstruction(Val, 2, 4); 4046 unsigned imm = fieldFromInstruction(Val, 0, 2); 4047 4048 // Thumb stores cannot use PC as dest register. 4049 switch (Inst.getOpcode()) { 4050 case ARM::t2STRHs: 4051 case ARM::t2STRBs: 4052 case ARM::t2STRs: 4053 if (Rn == 15) 4054 return MCDisassembler::Fail; 4055 break; 4056 default: 4057 break; 4058 } 4059 4060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4061 return MCDisassembler::Fail; 4062 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4063 return MCDisassembler::Fail; 4064 Inst.addOperand(MCOperand::createImm(imm)); 4065 4066 return S; 4067 } 4068 4069 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 4070 uint64_t Address, 4071 const MCDisassembler *Decoder) { 4072 DecodeStatus S = MCDisassembler::Success; 4073 4074 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4075 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4076 4077 const FeatureBitset &featureBits = 4078 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4079 4080 bool hasMP = featureBits[ARM::FeatureMP]; 4081 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4082 4083 if (Rn == 15) { 4084 switch (Inst.getOpcode()) { 4085 case ARM::t2LDRBs: 4086 Inst.setOpcode(ARM::t2LDRBpci); 4087 break; 4088 case ARM::t2LDRHs: 4089 Inst.setOpcode(ARM::t2LDRHpci); 4090 break; 4091 case ARM::t2LDRSHs: 4092 Inst.setOpcode(ARM::t2LDRSHpci); 4093 break; 4094 case ARM::t2LDRSBs: 4095 Inst.setOpcode(ARM::t2LDRSBpci); 4096 break; 4097 case ARM::t2LDRs: 4098 Inst.setOpcode(ARM::t2LDRpci); 4099 break; 4100 case ARM::t2PLDs: 4101 Inst.setOpcode(ARM::t2PLDpci); 4102 break; 4103 case ARM::t2PLIs: 4104 Inst.setOpcode(ARM::t2PLIpci); 4105 break; 4106 default: 4107 return MCDisassembler::Fail; 4108 } 4109 4110 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4111 } 4112 4113 if (Rt == 15) { 4114 switch (Inst.getOpcode()) { 4115 case ARM::t2LDRSHs: 4116 return MCDisassembler::Fail; 4117 case ARM::t2LDRHs: 4118 Inst.setOpcode(ARM::t2PLDWs); 4119 break; 4120 case ARM::t2LDRSBs: 4121 Inst.setOpcode(ARM::t2PLIs); 4122 break; 4123 default: 4124 break; 4125 } 4126 } 4127 4128 switch (Inst.getOpcode()) { 4129 case ARM::t2PLDs: 4130 break; 4131 case ARM::t2PLIs: 4132 if (!hasV7Ops) 4133 return MCDisassembler::Fail; 4134 break; 4135 case ARM::t2PLDWs: 4136 if (!hasV7Ops || !hasMP) 4137 return MCDisassembler::Fail; 4138 break; 4139 default: 4140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4141 return MCDisassembler::Fail; 4142 } 4143 4144 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 4145 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 4146 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 4147 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 4148 return MCDisassembler::Fail; 4149 4150 return S; 4151 } 4152 4153 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 4154 uint64_t Address, 4155 const MCDisassembler *Decoder) { 4156 DecodeStatus S = MCDisassembler::Success; 4157 4158 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4159 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4160 unsigned U = fieldFromInstruction(Insn, 9, 1); 4161 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4162 imm |= (U << 8); 4163 imm |= (Rn << 9); 4164 unsigned add = fieldFromInstruction(Insn, 9, 1); 4165 4166 const FeatureBitset &featureBits = 4167 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4168 4169 bool hasMP = featureBits[ARM::FeatureMP]; 4170 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4171 4172 if (Rn == 15) { 4173 switch (Inst.getOpcode()) { 4174 case ARM::t2LDRi8: 4175 Inst.setOpcode(ARM::t2LDRpci); 4176 break; 4177 case ARM::t2LDRBi8: 4178 Inst.setOpcode(ARM::t2LDRBpci); 4179 break; 4180 case ARM::t2LDRSBi8: 4181 Inst.setOpcode(ARM::t2LDRSBpci); 4182 break; 4183 case ARM::t2LDRHi8: 4184 Inst.setOpcode(ARM::t2LDRHpci); 4185 break; 4186 case ARM::t2LDRSHi8: 4187 Inst.setOpcode(ARM::t2LDRSHpci); 4188 break; 4189 case ARM::t2PLDi8: 4190 Inst.setOpcode(ARM::t2PLDpci); 4191 break; 4192 case ARM::t2PLIi8: 4193 Inst.setOpcode(ARM::t2PLIpci); 4194 break; 4195 default: 4196 return MCDisassembler::Fail; 4197 } 4198 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4199 } 4200 4201 if (Rt == 15) { 4202 switch (Inst.getOpcode()) { 4203 case ARM::t2LDRSHi8: 4204 return MCDisassembler::Fail; 4205 case ARM::t2LDRHi8: 4206 if (!add) 4207 Inst.setOpcode(ARM::t2PLDWi8); 4208 break; 4209 case ARM::t2LDRSBi8: 4210 Inst.setOpcode(ARM::t2PLIi8); 4211 break; 4212 default: 4213 break; 4214 } 4215 } 4216 4217 switch (Inst.getOpcode()) { 4218 case ARM::t2PLDi8: 4219 break; 4220 case ARM::t2PLIi8: 4221 if (!hasV7Ops) 4222 return MCDisassembler::Fail; 4223 break; 4224 case ARM::t2PLDWi8: 4225 if (!hasV7Ops || !hasMP) 4226 return MCDisassembler::Fail; 4227 break; 4228 default: 4229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4230 return MCDisassembler::Fail; 4231 } 4232 4233 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4234 return MCDisassembler::Fail; 4235 return S; 4236 } 4237 4238 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 4239 uint64_t Address, 4240 const MCDisassembler *Decoder) { 4241 DecodeStatus S = MCDisassembler::Success; 4242 4243 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4244 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4245 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4246 imm |= (Rn << 13); 4247 4248 const FeatureBitset &featureBits = 4249 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4250 4251 bool hasMP = featureBits[ARM::FeatureMP]; 4252 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4253 4254 if (Rn == 15) { 4255 switch (Inst.getOpcode()) { 4256 case ARM::t2LDRi12: 4257 Inst.setOpcode(ARM::t2LDRpci); 4258 break; 4259 case ARM::t2LDRHi12: 4260 Inst.setOpcode(ARM::t2LDRHpci); 4261 break; 4262 case ARM::t2LDRSHi12: 4263 Inst.setOpcode(ARM::t2LDRSHpci); 4264 break; 4265 case ARM::t2LDRBi12: 4266 Inst.setOpcode(ARM::t2LDRBpci); 4267 break; 4268 case ARM::t2LDRSBi12: 4269 Inst.setOpcode(ARM::t2LDRSBpci); 4270 break; 4271 case ARM::t2PLDi12: 4272 Inst.setOpcode(ARM::t2PLDpci); 4273 break; 4274 case ARM::t2PLIi12: 4275 Inst.setOpcode(ARM::t2PLIpci); 4276 break; 4277 default: 4278 return MCDisassembler::Fail; 4279 } 4280 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4281 } 4282 4283 if (Rt == 15) { 4284 switch (Inst.getOpcode()) { 4285 case ARM::t2LDRSHi12: 4286 return MCDisassembler::Fail; 4287 case ARM::t2LDRHi12: 4288 Inst.setOpcode(ARM::t2PLDWi12); 4289 break; 4290 case ARM::t2LDRSBi12: 4291 Inst.setOpcode(ARM::t2PLIi12); 4292 break; 4293 default: 4294 break; 4295 } 4296 } 4297 4298 switch (Inst.getOpcode()) { 4299 case ARM::t2PLDi12: 4300 break; 4301 case ARM::t2PLIi12: 4302 if (!hasV7Ops) 4303 return MCDisassembler::Fail; 4304 break; 4305 case ARM::t2PLDWi12: 4306 if (!hasV7Ops || !hasMP) 4307 return MCDisassembler::Fail; 4308 break; 4309 default: 4310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 } 4313 4314 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4315 return MCDisassembler::Fail; 4316 return S; 4317 } 4318 4319 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 4320 const MCDisassembler *Decoder) { 4321 DecodeStatus S = MCDisassembler::Success; 4322 4323 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4324 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4325 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4326 imm |= (Rn << 9); 4327 4328 if (Rn == 15) { 4329 switch (Inst.getOpcode()) { 4330 case ARM::t2LDRT: 4331 Inst.setOpcode(ARM::t2LDRpci); 4332 break; 4333 case ARM::t2LDRBT: 4334 Inst.setOpcode(ARM::t2LDRBpci); 4335 break; 4336 case ARM::t2LDRHT: 4337 Inst.setOpcode(ARM::t2LDRHpci); 4338 break; 4339 case ARM::t2LDRSBT: 4340 Inst.setOpcode(ARM::t2LDRSBpci); 4341 break; 4342 case ARM::t2LDRSHT: 4343 Inst.setOpcode(ARM::t2LDRSHpci); 4344 break; 4345 default: 4346 return MCDisassembler::Fail; 4347 } 4348 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4349 } 4350 4351 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4352 return MCDisassembler::Fail; 4353 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4354 return MCDisassembler::Fail; 4355 return S; 4356 } 4357 4358 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4359 uint64_t Address, 4360 const MCDisassembler *Decoder) { 4361 DecodeStatus S = MCDisassembler::Success; 4362 4363 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4364 unsigned U = fieldFromInstruction(Insn, 23, 1); 4365 int imm = fieldFromInstruction(Insn, 0, 12); 4366 4367 const FeatureBitset &featureBits = 4368 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4369 4370 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4371 4372 if (Rt == 15) { 4373 switch (Inst.getOpcode()) { 4374 case ARM::t2LDRBpci: 4375 case ARM::t2LDRHpci: 4376 Inst.setOpcode(ARM::t2PLDpci); 4377 break; 4378 case ARM::t2LDRSBpci: 4379 Inst.setOpcode(ARM::t2PLIpci); 4380 break; 4381 case ARM::t2LDRSHpci: 4382 return MCDisassembler::Fail; 4383 default: 4384 break; 4385 } 4386 } 4387 4388 switch(Inst.getOpcode()) { 4389 case ARM::t2PLDpci: 4390 break; 4391 case ARM::t2PLIpci: 4392 if (!hasV7Ops) 4393 return MCDisassembler::Fail; 4394 break; 4395 default: 4396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4397 return MCDisassembler::Fail; 4398 } 4399 4400 if (!U) { 4401 // Special case for #-0. 4402 if (imm == 0) 4403 imm = INT32_MIN; 4404 else 4405 imm = -imm; 4406 } 4407 Inst.addOperand(MCOperand::createImm(imm)); 4408 4409 return S; 4410 } 4411 4412 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 4413 const MCDisassembler *Decoder) { 4414 if (Val == 0) 4415 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4416 else { 4417 int imm = Val & 0xFF; 4418 4419 if (!(Val & 0x100)) imm *= -1; 4420 Inst.addOperand(MCOperand::createImm(imm * 4)); 4421 } 4422 4423 return MCDisassembler::Success; 4424 } 4425 4426 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4427 const MCDisassembler *Decoder) { 4428 if (Val == 0) 4429 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4430 else { 4431 int imm = Val & 0x7F; 4432 4433 if (!(Val & 0x80)) 4434 imm *= -1; 4435 Inst.addOperand(MCOperand::createImm(imm * 4)); 4436 } 4437 4438 return MCDisassembler::Success; 4439 } 4440 4441 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4442 uint64_t Address, 4443 const MCDisassembler *Decoder) { 4444 DecodeStatus S = MCDisassembler::Success; 4445 4446 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4447 unsigned imm = fieldFromInstruction(Val, 0, 9); 4448 4449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4450 return MCDisassembler::Fail; 4451 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4452 return MCDisassembler::Fail; 4453 4454 return S; 4455 } 4456 4457 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4458 uint64_t Address, 4459 const MCDisassembler *Decoder) { 4460 DecodeStatus S = MCDisassembler::Success; 4461 4462 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4463 unsigned imm = fieldFromInstruction(Val, 0, 8); 4464 4465 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4466 return MCDisassembler::Fail; 4467 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4468 return MCDisassembler::Fail; 4469 4470 return S; 4471 } 4472 4473 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 4474 uint64_t Address, 4475 const MCDisassembler *Decoder) { 4476 DecodeStatus S = MCDisassembler::Success; 4477 4478 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4479 unsigned imm = fieldFromInstruction(Val, 0, 8); 4480 4481 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4482 return MCDisassembler::Fail; 4483 4484 Inst.addOperand(MCOperand::createImm(imm)); 4485 4486 return S; 4487 } 4488 4489 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 4490 const MCDisassembler *Decoder) { 4491 int imm = Val & 0xFF; 4492 if (Val == 0) 4493 imm = INT32_MIN; 4494 else if (!(Val & 0x100)) 4495 imm *= -1; 4496 Inst.addOperand(MCOperand::createImm(imm)); 4497 4498 return MCDisassembler::Success; 4499 } 4500 4501 template <int shift> 4502 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 4503 const MCDisassembler *Decoder) { 4504 int imm = Val & 0x7F; 4505 if (Val == 0) 4506 imm = INT32_MIN; 4507 else if (!(Val & 0x80)) 4508 imm *= -1; 4509 if (imm != INT32_MIN) 4510 imm *= (1U << shift); 4511 Inst.addOperand(MCOperand::createImm(imm)); 4512 4513 return MCDisassembler::Success; 4514 } 4515 4516 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4517 uint64_t Address, 4518 const MCDisassembler *Decoder) { 4519 DecodeStatus S = MCDisassembler::Success; 4520 4521 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4522 unsigned imm = fieldFromInstruction(Val, 0, 9); 4523 4524 // Thumb stores cannot use PC as dest register. 4525 switch (Inst.getOpcode()) { 4526 case ARM::t2STRT: 4527 case ARM::t2STRBT: 4528 case ARM::t2STRHT: 4529 case ARM::t2STRi8: 4530 case ARM::t2STRHi8: 4531 case ARM::t2STRBi8: 4532 if (Rn == 15) 4533 return MCDisassembler::Fail; 4534 break; 4535 default: 4536 break; 4537 } 4538 4539 // Some instructions always use an additive offset. 4540 switch (Inst.getOpcode()) { 4541 case ARM::t2LDRT: 4542 case ARM::t2LDRBT: 4543 case ARM::t2LDRHT: 4544 case ARM::t2LDRSBT: 4545 case ARM::t2LDRSHT: 4546 case ARM::t2STRT: 4547 case ARM::t2STRBT: 4548 case ARM::t2STRHT: 4549 imm |= 0x100; 4550 break; 4551 default: 4552 break; 4553 } 4554 4555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4556 return MCDisassembler::Fail; 4557 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4558 return MCDisassembler::Fail; 4559 4560 return S; 4561 } 4562 4563 template <int shift> 4564 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4565 uint64_t Address, 4566 const MCDisassembler *Decoder) { 4567 DecodeStatus S = MCDisassembler::Success; 4568 4569 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4570 unsigned imm = fieldFromInstruction(Val, 0, 8); 4571 4572 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4573 return MCDisassembler::Fail; 4574 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4575 return MCDisassembler::Fail; 4576 4577 return S; 4578 } 4579 4580 template <int shift, int WriteBack> 4581 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4582 uint64_t Address, 4583 const MCDisassembler *Decoder) { 4584 DecodeStatus S = MCDisassembler::Success; 4585 4586 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4587 unsigned imm = fieldFromInstruction(Val, 0, 8); 4588 if (WriteBack) { 4589 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4590 return MCDisassembler::Fail; 4591 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4592 return MCDisassembler::Fail; 4593 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4594 return MCDisassembler::Fail; 4595 4596 return S; 4597 } 4598 4599 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4600 uint64_t Address, 4601 const MCDisassembler *Decoder) { 4602 DecodeStatus S = MCDisassembler::Success; 4603 4604 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4605 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4606 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4607 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4608 addr |= Rn << 9; 4609 unsigned load = fieldFromInstruction(Insn, 20, 1); 4610 4611 if (Rn == 15) { 4612 switch (Inst.getOpcode()) { 4613 case ARM::t2LDR_PRE: 4614 case ARM::t2LDR_POST: 4615 Inst.setOpcode(ARM::t2LDRpci); 4616 break; 4617 case ARM::t2LDRB_PRE: 4618 case ARM::t2LDRB_POST: 4619 Inst.setOpcode(ARM::t2LDRBpci); 4620 break; 4621 case ARM::t2LDRH_PRE: 4622 case ARM::t2LDRH_POST: 4623 Inst.setOpcode(ARM::t2LDRHpci); 4624 break; 4625 case ARM::t2LDRSB_PRE: 4626 case ARM::t2LDRSB_POST: 4627 if (Rt == 15) 4628 Inst.setOpcode(ARM::t2PLIpci); 4629 else 4630 Inst.setOpcode(ARM::t2LDRSBpci); 4631 break; 4632 case ARM::t2LDRSH_PRE: 4633 case ARM::t2LDRSH_POST: 4634 Inst.setOpcode(ARM::t2LDRSHpci); 4635 break; 4636 default: 4637 return MCDisassembler::Fail; 4638 } 4639 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4640 } 4641 4642 if (!load) { 4643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4644 return MCDisassembler::Fail; 4645 } 4646 4647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4648 return MCDisassembler::Fail; 4649 4650 if (load) { 4651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4652 return MCDisassembler::Fail; 4653 } 4654 4655 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4656 return MCDisassembler::Fail; 4657 4658 return S; 4659 } 4660 4661 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4662 uint64_t Address, 4663 const MCDisassembler *Decoder) { 4664 DecodeStatus S = MCDisassembler::Success; 4665 4666 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4667 unsigned imm = fieldFromInstruction(Val, 0, 12); 4668 4669 // Thumb stores cannot use PC as dest register. 4670 switch (Inst.getOpcode()) { 4671 case ARM::t2STRi12: 4672 case ARM::t2STRBi12: 4673 case ARM::t2STRHi12: 4674 if (Rn == 15) 4675 return MCDisassembler::Fail; 4676 break; 4677 default: 4678 break; 4679 } 4680 4681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4682 return MCDisassembler::Fail; 4683 Inst.addOperand(MCOperand::createImm(imm)); 4684 4685 return S; 4686 } 4687 4688 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4689 uint64_t Address, 4690 const MCDisassembler *Decoder) { 4691 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4692 4693 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4694 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4695 Inst.addOperand(MCOperand::createImm(imm)); 4696 4697 return MCDisassembler::Success; 4698 } 4699 4700 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4701 uint64_t Address, 4702 const MCDisassembler *Decoder) { 4703 DecodeStatus S = MCDisassembler::Success; 4704 4705 if (Inst.getOpcode() == ARM::tADDrSP) { 4706 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4707 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4708 4709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4710 return MCDisassembler::Fail; 4711 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4713 return MCDisassembler::Fail; 4714 } else if (Inst.getOpcode() == ARM::tADDspr) { 4715 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4716 4717 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4718 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4719 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4720 return MCDisassembler::Fail; 4721 } 4722 4723 return S; 4724 } 4725 4726 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4727 uint64_t Address, 4728 const MCDisassembler *Decoder) { 4729 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4730 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4731 4732 Inst.addOperand(MCOperand::createImm(imod)); 4733 Inst.addOperand(MCOperand::createImm(flags)); 4734 4735 return MCDisassembler::Success; 4736 } 4737 4738 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4739 uint64_t Address, 4740 const MCDisassembler *Decoder) { 4741 DecodeStatus S = MCDisassembler::Success; 4742 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4743 unsigned add = fieldFromInstruction(Insn, 4, 1); 4744 4745 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4746 return MCDisassembler::Fail; 4747 Inst.addOperand(MCOperand::createImm(add)); 4748 4749 return S; 4750 } 4751 4752 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4753 uint64_t Address, 4754 const MCDisassembler *Decoder) { 4755 DecodeStatus S = MCDisassembler::Success; 4756 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4757 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4758 4759 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4760 return MCDisassembler::Fail; 4761 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4762 return MCDisassembler::Fail; 4763 4764 return S; 4765 } 4766 4767 template <int shift> 4768 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4769 uint64_t Address, 4770 const MCDisassembler *Decoder) { 4771 DecodeStatus S = MCDisassembler::Success; 4772 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4773 int imm = fieldFromInstruction(Insn, 0, 7); 4774 4775 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4776 return MCDisassembler::Fail; 4777 4778 if(!fieldFromInstruction(Insn, 7, 1)) { 4779 if (imm == 0) 4780 imm = INT32_MIN; // indicate -0 4781 else 4782 imm *= -1; 4783 } 4784 if (imm != INT32_MIN) 4785 imm *= (1U << shift); 4786 Inst.addOperand(MCOperand::createImm(imm)); 4787 4788 return S; 4789 } 4790 4791 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4792 uint64_t Address, 4793 const MCDisassembler *Decoder) { 4794 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4795 // Note only one trailing zero not two. Also the J1 and J2 values are from 4796 // the encoded instruction. So here change to I1 and I2 values via: 4797 // I1 = NOT(J1 EOR S); 4798 // I2 = NOT(J2 EOR S); 4799 // and build the imm32 with two trailing zeros as documented: 4800 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4801 unsigned S = (Val >> 23) & 1; 4802 unsigned J1 = (Val >> 22) & 1; 4803 unsigned J2 = (Val >> 21) & 1; 4804 unsigned I1 = !(J1 ^ S); 4805 unsigned I2 = !(J2 ^ S); 4806 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4807 int imm32 = SignExtend32<25>(tmp << 1); 4808 4809 if (!tryAddingSymbolicOperand(Address, 4810 (Address & ~2u) + imm32 + 4, 4811 true, 4, Inst, Decoder)) 4812 Inst.addOperand(MCOperand::createImm(imm32)); 4813 return MCDisassembler::Success; 4814 } 4815 4816 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4817 uint64_t Address, 4818 const MCDisassembler *Decoder) { 4819 if (Val == 0xA || Val == 0xB) 4820 return MCDisassembler::Fail; 4821 4822 const FeatureBitset &featureBits = 4823 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4824 4825 if (!isValidCoprocessorNumber(Val, featureBits)) 4826 return MCDisassembler::Fail; 4827 4828 Inst.addOperand(MCOperand::createImm(Val)); 4829 return MCDisassembler::Success; 4830 } 4831 4832 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4833 uint64_t Address, 4834 const MCDisassembler *Decoder) { 4835 const FeatureBitset &FeatureBits = 4836 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4837 DecodeStatus S = MCDisassembler::Success; 4838 4839 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4840 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4841 4842 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4843 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4844 return MCDisassembler::Fail; 4845 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4846 return MCDisassembler::Fail; 4847 return S; 4848 } 4849 4850 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4851 uint64_t Address, 4852 const MCDisassembler *Decoder) { 4853 DecodeStatus S = MCDisassembler::Success; 4854 4855 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4856 if (pred == 0xE || pred == 0xF) { 4857 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4858 switch (opc) { 4859 default: 4860 return MCDisassembler::Fail; 4861 case 0xf3bf8f4: 4862 Inst.setOpcode(ARM::t2DSB); 4863 break; 4864 case 0xf3bf8f5: 4865 Inst.setOpcode(ARM::t2DMB); 4866 break; 4867 case 0xf3bf8f6: 4868 Inst.setOpcode(ARM::t2ISB); 4869 break; 4870 } 4871 4872 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4873 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4874 } 4875 4876 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4877 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4878 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4879 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4880 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4881 4882 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4883 return MCDisassembler::Fail; 4884 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4885 return MCDisassembler::Fail; 4886 4887 return S; 4888 } 4889 4890 // Decode a shifted immediate operand. These basically consist 4891 // of an 8-bit value, and a 4-bit directive that specifies either 4892 // a splat operation or a rotation. 4893 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 4894 const MCDisassembler *Decoder) { 4895 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4896 if (ctrl == 0) { 4897 unsigned byte = fieldFromInstruction(Val, 8, 2); 4898 unsigned imm = fieldFromInstruction(Val, 0, 8); 4899 switch (byte) { 4900 case 0: 4901 Inst.addOperand(MCOperand::createImm(imm)); 4902 break; 4903 case 1: 4904 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4905 break; 4906 case 2: 4907 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4908 break; 4909 case 3: 4910 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4911 (imm << 8) | imm)); 4912 break; 4913 } 4914 } else { 4915 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4916 unsigned rot = fieldFromInstruction(Val, 7, 5); 4917 unsigned imm = llvm::rotr<uint32_t>(unrot, rot); 4918 Inst.addOperand(MCOperand::createImm(imm)); 4919 } 4920 4921 return MCDisassembler::Success; 4922 } 4923 4924 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4925 uint64_t Address, 4926 const MCDisassembler *Decoder) { 4927 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4928 true, 2, Inst, Decoder)) 4929 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4930 return MCDisassembler::Success; 4931 } 4932 4933 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4934 uint64_t Address, 4935 const MCDisassembler *Decoder) { 4936 // Val is passed in as S:J1:J2:imm10:imm11 4937 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4938 // the encoded instruction. So here change to I1 and I2 values via: 4939 // I1 = NOT(J1 EOR S); 4940 // I2 = NOT(J2 EOR S); 4941 // and build the imm32 with one trailing zero as documented: 4942 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4943 unsigned S = (Val >> 23) & 1; 4944 unsigned J1 = (Val >> 22) & 1; 4945 unsigned J2 = (Val >> 21) & 1; 4946 unsigned I1 = !(J1 ^ S); 4947 unsigned I2 = !(J2 ^ S); 4948 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4949 int imm32 = SignExtend32<25>(tmp << 1); 4950 4951 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4952 true, 4, Inst, Decoder)) 4953 Inst.addOperand(MCOperand::createImm(imm32)); 4954 return MCDisassembler::Success; 4955 } 4956 4957 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4958 uint64_t Address, 4959 const MCDisassembler *Decoder) { 4960 if (Val & ~0xf) 4961 return MCDisassembler::Fail; 4962 4963 Inst.addOperand(MCOperand::createImm(Val)); 4964 return MCDisassembler::Success; 4965 } 4966 4967 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4968 uint64_t Address, 4969 const MCDisassembler *Decoder) { 4970 if (Val & ~0xf) 4971 return MCDisassembler::Fail; 4972 4973 Inst.addOperand(MCOperand::createImm(Val)); 4974 return MCDisassembler::Success; 4975 } 4976 4977 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, 4978 const MCDisassembler *Decoder) { 4979 DecodeStatus S = MCDisassembler::Success; 4980 const FeatureBitset &FeatureBits = 4981 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4982 4983 if (FeatureBits[ARM::FeatureMClass]) { 4984 unsigned ValLow = Val & 0xff; 4985 4986 // Validate the SYSm value first. 4987 switch (ValLow) { 4988 case 0: // apsr 4989 case 1: // iapsr 4990 case 2: // eapsr 4991 case 3: // xpsr 4992 case 5: // ipsr 4993 case 6: // epsr 4994 case 7: // iepsr 4995 case 8: // msp 4996 case 9: // psp 4997 case 16: // primask 4998 case 20: // control 4999 break; 5000 case 17: // basepri 5001 case 18: // basepri_max 5002 case 19: // faultmask 5003 if (!(FeatureBits[ARM::HasV7Ops])) 5004 // Values basepri, basepri_max and faultmask are only valid for v7m. 5005 return MCDisassembler::Fail; 5006 break; 5007 case 0x8a: // msplim_ns 5008 case 0x8b: // psplim_ns 5009 case 0x91: // basepri_ns 5010 case 0x93: // faultmask_ns 5011 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 5012 return MCDisassembler::Fail; 5013 [[fallthrough]]; 5014 case 10: // msplim 5015 case 11: // psplim 5016 case 0x88: // msp_ns 5017 case 0x89: // psp_ns 5018 case 0x90: // primask_ns 5019 case 0x94: // control_ns 5020 case 0x98: // sp_ns 5021 if (!(FeatureBits[ARM::Feature8MSecExt])) 5022 return MCDisassembler::Fail; 5023 break; 5024 case 0x20: // pac_key_p_0 5025 case 0x21: // pac_key_p_1 5026 case 0x22: // pac_key_p_2 5027 case 0x23: // pac_key_p_3 5028 case 0x24: // pac_key_u_0 5029 case 0x25: // pac_key_u_1 5030 case 0x26: // pac_key_u_2 5031 case 0x27: // pac_key_u_3 5032 case 0xa0: // pac_key_p_0_ns 5033 case 0xa1: // pac_key_p_1_ns 5034 case 0xa2: // pac_key_p_2_ns 5035 case 0xa3: // pac_key_p_3_ns 5036 case 0xa4: // pac_key_u_0_ns 5037 case 0xa5: // pac_key_u_1_ns 5038 case 0xa6: // pac_key_u_2_ns 5039 case 0xa7: // pac_key_u_3_ns 5040 if (!(FeatureBits[ARM::FeaturePACBTI])) 5041 return MCDisassembler::Fail; 5042 break; 5043 default: 5044 // Architecturally defined as unpredictable 5045 S = MCDisassembler::SoftFail; 5046 break; 5047 } 5048 5049 if (Inst.getOpcode() == ARM::t2MSR_M) { 5050 unsigned Mask = fieldFromInstruction(Val, 10, 2); 5051 if (!(FeatureBits[ARM::HasV7Ops])) { 5052 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 5053 // unpredictable. 5054 if (Mask != 2) 5055 S = MCDisassembler::SoftFail; 5056 } 5057 else { 5058 // The ARMv7-M architecture stores an additional 2-bit mask value in 5059 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 5060 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 5061 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 5062 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 5063 // only if the processor includes the DSP extension. 5064 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 5065 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 5066 S = MCDisassembler::SoftFail; 5067 } 5068 } 5069 } else { 5070 // A/R class 5071 if (Val == 0) 5072 return MCDisassembler::Fail; 5073 } 5074 Inst.addOperand(MCOperand::createImm(Val)); 5075 return S; 5076 } 5077 5078 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 5079 uint64_t Address, 5080 const MCDisassembler *Decoder) { 5081 unsigned R = fieldFromInstruction(Val, 5, 1); 5082 unsigned SysM = fieldFromInstruction(Val, 0, 5); 5083 5084 // The table of encodings for these banked registers comes from B9.2.3 of the 5085 // ARM ARM. There are patterns, but nothing regular enough to make this logic 5086 // neater. So by fiat, these values are UNPREDICTABLE: 5087 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 5088 return MCDisassembler::Fail; 5089 5090 Inst.addOperand(MCOperand::createImm(Val)); 5091 return MCDisassembler::Success; 5092 } 5093 5094 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 5095 uint64_t Address, 5096 const MCDisassembler *Decoder) { 5097 DecodeStatus S = MCDisassembler::Success; 5098 5099 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5100 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5101 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5102 5103 if (Rn == 0xF) 5104 S = MCDisassembler::SoftFail; 5105 5106 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5107 return MCDisassembler::Fail; 5108 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5109 return MCDisassembler::Fail; 5110 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5111 return MCDisassembler::Fail; 5112 5113 return S; 5114 } 5115 5116 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 5117 uint64_t Address, 5118 const MCDisassembler *Decoder) { 5119 DecodeStatus S = MCDisassembler::Success; 5120 5121 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5122 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 5123 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5124 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5125 5126 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 5127 return MCDisassembler::Fail; 5128 5129 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 5130 S = MCDisassembler::SoftFail; 5131 5132 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5133 return MCDisassembler::Fail; 5134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5135 return MCDisassembler::Fail; 5136 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5137 return MCDisassembler::Fail; 5138 5139 return S; 5140 } 5141 5142 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 5143 uint64_t Address, 5144 const MCDisassembler *Decoder) { 5145 DecodeStatus S = MCDisassembler::Success; 5146 5147 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5148 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5149 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5150 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5151 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5152 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5153 5154 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5155 5156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5157 return MCDisassembler::Fail; 5158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5159 return MCDisassembler::Fail; 5160 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5161 return MCDisassembler::Fail; 5162 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5163 return MCDisassembler::Fail; 5164 5165 return S; 5166 } 5167 5168 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 5169 uint64_t Address, 5170 const MCDisassembler *Decoder) { 5171 DecodeStatus S = MCDisassembler::Success; 5172 5173 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5174 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5175 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5176 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5177 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5178 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5179 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5180 5181 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5182 if (Rm == 0xF) S = MCDisassembler::SoftFail; 5183 5184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5185 return MCDisassembler::Fail; 5186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5187 return MCDisassembler::Fail; 5188 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5189 return MCDisassembler::Fail; 5190 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5191 return MCDisassembler::Fail; 5192 5193 return S; 5194 } 5195 5196 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 5197 uint64_t Address, 5198 const MCDisassembler *Decoder) { 5199 DecodeStatus S = MCDisassembler::Success; 5200 5201 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5202 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5203 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5204 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5205 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5206 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5207 5208 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5209 5210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5211 return MCDisassembler::Fail; 5212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5213 return MCDisassembler::Fail; 5214 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5215 return MCDisassembler::Fail; 5216 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5217 return MCDisassembler::Fail; 5218 5219 return S; 5220 } 5221 5222 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 5223 uint64_t Address, 5224 const MCDisassembler *Decoder) { 5225 DecodeStatus S = MCDisassembler::Success; 5226 5227 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5228 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5229 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5230 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5231 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5232 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5233 5234 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5235 5236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5237 return MCDisassembler::Fail; 5238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5239 return MCDisassembler::Fail; 5240 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5241 return MCDisassembler::Fail; 5242 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5243 return MCDisassembler::Fail; 5244 5245 return S; 5246 } 5247 5248 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5249 const MCDisassembler *Decoder) { 5250 DecodeStatus S = MCDisassembler::Success; 5251 5252 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5253 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5254 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5255 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5256 unsigned size = fieldFromInstruction(Insn, 10, 2); 5257 5258 unsigned align = 0; 5259 unsigned index = 0; 5260 switch (size) { 5261 default: 5262 return MCDisassembler::Fail; 5263 case 0: 5264 if (fieldFromInstruction(Insn, 4, 1)) 5265 return MCDisassembler::Fail; // UNDEFINED 5266 index = fieldFromInstruction(Insn, 5, 3); 5267 break; 5268 case 1: 5269 if (fieldFromInstruction(Insn, 5, 1)) 5270 return MCDisassembler::Fail; // UNDEFINED 5271 index = fieldFromInstruction(Insn, 6, 2); 5272 if (fieldFromInstruction(Insn, 4, 1)) 5273 align = 2; 5274 break; 5275 case 2: 5276 if (fieldFromInstruction(Insn, 6, 1)) 5277 return MCDisassembler::Fail; // UNDEFINED 5278 index = fieldFromInstruction(Insn, 7, 1); 5279 5280 switch (fieldFromInstruction(Insn, 4, 2)) { 5281 case 0 : 5282 align = 0; break; 5283 case 3: 5284 align = 4; break; 5285 default: 5286 return MCDisassembler::Fail; 5287 } 5288 break; 5289 } 5290 5291 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5292 return MCDisassembler::Fail; 5293 if (Rm != 0xF) { // Writeback 5294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5295 return MCDisassembler::Fail; 5296 } 5297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5298 return MCDisassembler::Fail; 5299 Inst.addOperand(MCOperand::createImm(align)); 5300 if (Rm != 0xF) { 5301 if (Rm != 0xD) { 5302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5303 return MCDisassembler::Fail; 5304 } else 5305 Inst.addOperand(MCOperand::createReg(0)); 5306 } 5307 5308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5309 return MCDisassembler::Fail; 5310 Inst.addOperand(MCOperand::createImm(index)); 5311 5312 return S; 5313 } 5314 5315 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5316 const MCDisassembler *Decoder) { 5317 DecodeStatus S = MCDisassembler::Success; 5318 5319 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5320 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5321 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5322 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5323 unsigned size = fieldFromInstruction(Insn, 10, 2); 5324 5325 unsigned align = 0; 5326 unsigned index = 0; 5327 switch (size) { 5328 default: 5329 return MCDisassembler::Fail; 5330 case 0: 5331 if (fieldFromInstruction(Insn, 4, 1)) 5332 return MCDisassembler::Fail; // UNDEFINED 5333 index = fieldFromInstruction(Insn, 5, 3); 5334 break; 5335 case 1: 5336 if (fieldFromInstruction(Insn, 5, 1)) 5337 return MCDisassembler::Fail; // UNDEFINED 5338 index = fieldFromInstruction(Insn, 6, 2); 5339 if (fieldFromInstruction(Insn, 4, 1)) 5340 align = 2; 5341 break; 5342 case 2: 5343 if (fieldFromInstruction(Insn, 6, 1)) 5344 return MCDisassembler::Fail; // UNDEFINED 5345 index = fieldFromInstruction(Insn, 7, 1); 5346 5347 switch (fieldFromInstruction(Insn, 4, 2)) { 5348 case 0: 5349 align = 0; break; 5350 case 3: 5351 align = 4; break; 5352 default: 5353 return MCDisassembler::Fail; 5354 } 5355 break; 5356 } 5357 5358 if (Rm != 0xF) { // Writeback 5359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5360 return MCDisassembler::Fail; 5361 } 5362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5363 return MCDisassembler::Fail; 5364 Inst.addOperand(MCOperand::createImm(align)); 5365 if (Rm != 0xF) { 5366 if (Rm != 0xD) { 5367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5368 return MCDisassembler::Fail; 5369 } else 5370 Inst.addOperand(MCOperand::createReg(0)); 5371 } 5372 5373 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5374 return MCDisassembler::Fail; 5375 Inst.addOperand(MCOperand::createImm(index)); 5376 5377 return S; 5378 } 5379 5380 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5381 const MCDisassembler *Decoder) { 5382 DecodeStatus S = MCDisassembler::Success; 5383 5384 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5385 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5386 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5387 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5388 unsigned size = fieldFromInstruction(Insn, 10, 2); 5389 5390 unsigned align = 0; 5391 unsigned index = 0; 5392 unsigned inc = 1; 5393 switch (size) { 5394 default: 5395 return MCDisassembler::Fail; 5396 case 0: 5397 index = fieldFromInstruction(Insn, 5, 3); 5398 if (fieldFromInstruction(Insn, 4, 1)) 5399 align = 2; 5400 break; 5401 case 1: 5402 index = fieldFromInstruction(Insn, 6, 2); 5403 if (fieldFromInstruction(Insn, 4, 1)) 5404 align = 4; 5405 if (fieldFromInstruction(Insn, 5, 1)) 5406 inc = 2; 5407 break; 5408 case 2: 5409 if (fieldFromInstruction(Insn, 5, 1)) 5410 return MCDisassembler::Fail; // UNDEFINED 5411 index = fieldFromInstruction(Insn, 7, 1); 5412 if (fieldFromInstruction(Insn, 4, 1) != 0) 5413 align = 8; 5414 if (fieldFromInstruction(Insn, 6, 1)) 5415 inc = 2; 5416 break; 5417 } 5418 5419 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5420 return MCDisassembler::Fail; 5421 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5422 return MCDisassembler::Fail; 5423 if (Rm != 0xF) { // Writeback 5424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5425 return MCDisassembler::Fail; 5426 } 5427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5428 return MCDisassembler::Fail; 5429 Inst.addOperand(MCOperand::createImm(align)); 5430 if (Rm != 0xF) { 5431 if (Rm != 0xD) { 5432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5433 return MCDisassembler::Fail; 5434 } else 5435 Inst.addOperand(MCOperand::createReg(0)); 5436 } 5437 5438 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5439 return MCDisassembler::Fail; 5440 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5441 return MCDisassembler::Fail; 5442 Inst.addOperand(MCOperand::createImm(index)); 5443 5444 return S; 5445 } 5446 5447 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5448 const MCDisassembler *Decoder) { 5449 DecodeStatus S = MCDisassembler::Success; 5450 5451 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5452 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5453 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5454 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5455 unsigned size = fieldFromInstruction(Insn, 10, 2); 5456 5457 unsigned align = 0; 5458 unsigned index = 0; 5459 unsigned inc = 1; 5460 switch (size) { 5461 default: 5462 return MCDisassembler::Fail; 5463 case 0: 5464 index = fieldFromInstruction(Insn, 5, 3); 5465 if (fieldFromInstruction(Insn, 4, 1)) 5466 align = 2; 5467 break; 5468 case 1: 5469 index = fieldFromInstruction(Insn, 6, 2); 5470 if (fieldFromInstruction(Insn, 4, 1)) 5471 align = 4; 5472 if (fieldFromInstruction(Insn, 5, 1)) 5473 inc = 2; 5474 break; 5475 case 2: 5476 if (fieldFromInstruction(Insn, 5, 1)) 5477 return MCDisassembler::Fail; // UNDEFINED 5478 index = fieldFromInstruction(Insn, 7, 1); 5479 if (fieldFromInstruction(Insn, 4, 1) != 0) 5480 align = 8; 5481 if (fieldFromInstruction(Insn, 6, 1)) 5482 inc = 2; 5483 break; 5484 } 5485 5486 if (Rm != 0xF) { // Writeback 5487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5488 return MCDisassembler::Fail; 5489 } 5490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5491 return MCDisassembler::Fail; 5492 Inst.addOperand(MCOperand::createImm(align)); 5493 if (Rm != 0xF) { 5494 if (Rm != 0xD) { 5495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5496 return MCDisassembler::Fail; 5497 } else 5498 Inst.addOperand(MCOperand::createReg(0)); 5499 } 5500 5501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5502 return MCDisassembler::Fail; 5503 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5504 return MCDisassembler::Fail; 5505 Inst.addOperand(MCOperand::createImm(index)); 5506 5507 return S; 5508 } 5509 5510 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5511 const MCDisassembler *Decoder) { 5512 DecodeStatus S = MCDisassembler::Success; 5513 5514 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5515 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5516 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5517 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5518 unsigned size = fieldFromInstruction(Insn, 10, 2); 5519 5520 unsigned align = 0; 5521 unsigned index = 0; 5522 unsigned inc = 1; 5523 switch (size) { 5524 default: 5525 return MCDisassembler::Fail; 5526 case 0: 5527 if (fieldFromInstruction(Insn, 4, 1)) 5528 return MCDisassembler::Fail; // UNDEFINED 5529 index = fieldFromInstruction(Insn, 5, 3); 5530 break; 5531 case 1: 5532 if (fieldFromInstruction(Insn, 4, 1)) 5533 return MCDisassembler::Fail; // UNDEFINED 5534 index = fieldFromInstruction(Insn, 6, 2); 5535 if (fieldFromInstruction(Insn, 5, 1)) 5536 inc = 2; 5537 break; 5538 case 2: 5539 if (fieldFromInstruction(Insn, 4, 2)) 5540 return MCDisassembler::Fail; // UNDEFINED 5541 index = fieldFromInstruction(Insn, 7, 1); 5542 if (fieldFromInstruction(Insn, 6, 1)) 5543 inc = 2; 5544 break; 5545 } 5546 5547 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5548 return MCDisassembler::Fail; 5549 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5550 return MCDisassembler::Fail; 5551 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5552 return MCDisassembler::Fail; 5553 5554 if (Rm != 0xF) { // Writeback 5555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5556 return MCDisassembler::Fail; 5557 } 5558 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5559 return MCDisassembler::Fail; 5560 Inst.addOperand(MCOperand::createImm(align)); 5561 if (Rm != 0xF) { 5562 if (Rm != 0xD) { 5563 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5564 return MCDisassembler::Fail; 5565 } else 5566 Inst.addOperand(MCOperand::createReg(0)); 5567 } 5568 5569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5570 return MCDisassembler::Fail; 5571 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5572 return MCDisassembler::Fail; 5573 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5574 return MCDisassembler::Fail; 5575 Inst.addOperand(MCOperand::createImm(index)); 5576 5577 return S; 5578 } 5579 5580 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5581 const MCDisassembler *Decoder) { 5582 DecodeStatus S = MCDisassembler::Success; 5583 5584 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5585 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5586 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5587 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5588 unsigned size = fieldFromInstruction(Insn, 10, 2); 5589 5590 unsigned align = 0; 5591 unsigned index = 0; 5592 unsigned inc = 1; 5593 switch (size) { 5594 default: 5595 return MCDisassembler::Fail; 5596 case 0: 5597 if (fieldFromInstruction(Insn, 4, 1)) 5598 return MCDisassembler::Fail; // UNDEFINED 5599 index = fieldFromInstruction(Insn, 5, 3); 5600 break; 5601 case 1: 5602 if (fieldFromInstruction(Insn, 4, 1)) 5603 return MCDisassembler::Fail; // UNDEFINED 5604 index = fieldFromInstruction(Insn, 6, 2); 5605 if (fieldFromInstruction(Insn, 5, 1)) 5606 inc = 2; 5607 break; 5608 case 2: 5609 if (fieldFromInstruction(Insn, 4, 2)) 5610 return MCDisassembler::Fail; // UNDEFINED 5611 index = fieldFromInstruction(Insn, 7, 1); 5612 if (fieldFromInstruction(Insn, 6, 1)) 5613 inc = 2; 5614 break; 5615 } 5616 5617 if (Rm != 0xF) { // Writeback 5618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5619 return MCDisassembler::Fail; 5620 } 5621 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5622 return MCDisassembler::Fail; 5623 Inst.addOperand(MCOperand::createImm(align)); 5624 if (Rm != 0xF) { 5625 if (Rm != 0xD) { 5626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5627 return MCDisassembler::Fail; 5628 } else 5629 Inst.addOperand(MCOperand::createReg(0)); 5630 } 5631 5632 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5633 return MCDisassembler::Fail; 5634 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5635 return MCDisassembler::Fail; 5636 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5637 return MCDisassembler::Fail; 5638 Inst.addOperand(MCOperand::createImm(index)); 5639 5640 return S; 5641 } 5642 5643 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5644 const MCDisassembler *Decoder) { 5645 DecodeStatus S = MCDisassembler::Success; 5646 5647 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5648 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5649 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5650 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5651 unsigned size = fieldFromInstruction(Insn, 10, 2); 5652 5653 unsigned align = 0; 5654 unsigned index = 0; 5655 unsigned inc = 1; 5656 switch (size) { 5657 default: 5658 return MCDisassembler::Fail; 5659 case 0: 5660 if (fieldFromInstruction(Insn, 4, 1)) 5661 align = 4; 5662 index = fieldFromInstruction(Insn, 5, 3); 5663 break; 5664 case 1: 5665 if (fieldFromInstruction(Insn, 4, 1)) 5666 align = 8; 5667 index = fieldFromInstruction(Insn, 6, 2); 5668 if (fieldFromInstruction(Insn, 5, 1)) 5669 inc = 2; 5670 break; 5671 case 2: 5672 switch (fieldFromInstruction(Insn, 4, 2)) { 5673 case 0: 5674 align = 0; break; 5675 case 3: 5676 return MCDisassembler::Fail; 5677 default: 5678 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5679 } 5680 5681 index = fieldFromInstruction(Insn, 7, 1); 5682 if (fieldFromInstruction(Insn, 6, 1)) 5683 inc = 2; 5684 break; 5685 } 5686 5687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5688 return MCDisassembler::Fail; 5689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5690 return MCDisassembler::Fail; 5691 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5692 return MCDisassembler::Fail; 5693 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5694 return MCDisassembler::Fail; 5695 5696 if (Rm != 0xF) { // Writeback 5697 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5698 return MCDisassembler::Fail; 5699 } 5700 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5701 return MCDisassembler::Fail; 5702 Inst.addOperand(MCOperand::createImm(align)); 5703 if (Rm != 0xF) { 5704 if (Rm != 0xD) { 5705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5706 return MCDisassembler::Fail; 5707 } else 5708 Inst.addOperand(MCOperand::createReg(0)); 5709 } 5710 5711 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5712 return MCDisassembler::Fail; 5713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5714 return MCDisassembler::Fail; 5715 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5716 return MCDisassembler::Fail; 5717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5718 return MCDisassembler::Fail; 5719 Inst.addOperand(MCOperand::createImm(index)); 5720 5721 return S; 5722 } 5723 5724 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5725 const MCDisassembler *Decoder) { 5726 DecodeStatus S = MCDisassembler::Success; 5727 5728 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5729 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5730 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5731 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5732 unsigned size = fieldFromInstruction(Insn, 10, 2); 5733 5734 unsigned align = 0; 5735 unsigned index = 0; 5736 unsigned inc = 1; 5737 switch (size) { 5738 default: 5739 return MCDisassembler::Fail; 5740 case 0: 5741 if (fieldFromInstruction(Insn, 4, 1)) 5742 align = 4; 5743 index = fieldFromInstruction(Insn, 5, 3); 5744 break; 5745 case 1: 5746 if (fieldFromInstruction(Insn, 4, 1)) 5747 align = 8; 5748 index = fieldFromInstruction(Insn, 6, 2); 5749 if (fieldFromInstruction(Insn, 5, 1)) 5750 inc = 2; 5751 break; 5752 case 2: 5753 switch (fieldFromInstruction(Insn, 4, 2)) { 5754 case 0: 5755 align = 0; break; 5756 case 3: 5757 return MCDisassembler::Fail; 5758 default: 5759 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5760 } 5761 5762 index = fieldFromInstruction(Insn, 7, 1); 5763 if (fieldFromInstruction(Insn, 6, 1)) 5764 inc = 2; 5765 break; 5766 } 5767 5768 if (Rm != 0xF) { // Writeback 5769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5770 return MCDisassembler::Fail; 5771 } 5772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5773 return MCDisassembler::Fail; 5774 Inst.addOperand(MCOperand::createImm(align)); 5775 if (Rm != 0xF) { 5776 if (Rm != 0xD) { 5777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5778 return MCDisassembler::Fail; 5779 } else 5780 Inst.addOperand(MCOperand::createReg(0)); 5781 } 5782 5783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5784 return MCDisassembler::Fail; 5785 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5786 return MCDisassembler::Fail; 5787 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5788 return MCDisassembler::Fail; 5789 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5790 return MCDisassembler::Fail; 5791 Inst.addOperand(MCOperand::createImm(index)); 5792 5793 return S; 5794 } 5795 5796 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 5797 const MCDisassembler *Decoder) { 5798 DecodeStatus S = MCDisassembler::Success; 5799 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5800 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5801 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5802 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5803 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5804 5805 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5806 S = MCDisassembler::SoftFail; 5807 5808 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5809 return MCDisassembler::Fail; 5810 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5811 return MCDisassembler::Fail; 5812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5813 return MCDisassembler::Fail; 5814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5815 return MCDisassembler::Fail; 5816 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5817 return MCDisassembler::Fail; 5818 5819 return S; 5820 } 5821 5822 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 5823 const MCDisassembler *Decoder) { 5824 DecodeStatus S = MCDisassembler::Success; 5825 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5826 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5827 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5828 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5829 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5830 5831 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5832 S = MCDisassembler::SoftFail; 5833 5834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5835 return MCDisassembler::Fail; 5836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5837 return MCDisassembler::Fail; 5838 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5839 return MCDisassembler::Fail; 5840 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5841 return MCDisassembler::Fail; 5842 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5843 return MCDisassembler::Fail; 5844 5845 return S; 5846 } 5847 5848 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, 5849 const MCDisassembler *Decoder) { 5850 DecodeStatus S = MCDisassembler::Success; 5851 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5852 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5853 5854 if (pred == 0xF) { 5855 pred = 0xE; 5856 S = MCDisassembler::SoftFail; 5857 } 5858 5859 if (mask == 0x0) 5860 return MCDisassembler::Fail; 5861 5862 // IT masks are encoded as a sequence of replacement low-order bits 5863 // for the condition code. So if the low bit of the starting 5864 // condition code is 1, then we have to flip all the bits above the 5865 // terminating bit (which is the lowest 1 bit). 5866 if (pred & 1) { 5867 unsigned LowBit = mask & -mask; 5868 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5869 mask ^= BitsAboveLowBit; 5870 } 5871 5872 Inst.addOperand(MCOperand::createImm(pred)); 5873 Inst.addOperand(MCOperand::createImm(mask)); 5874 return S; 5875 } 5876 5877 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5878 uint64_t Address, 5879 const MCDisassembler *Decoder) { 5880 DecodeStatus S = MCDisassembler::Success; 5881 5882 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5883 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5884 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5885 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5886 unsigned W = fieldFromInstruction(Insn, 21, 1); 5887 unsigned U = fieldFromInstruction(Insn, 23, 1); 5888 unsigned P = fieldFromInstruction(Insn, 24, 1); 5889 bool writeback = (W == 1) | (P == 0); 5890 5891 addr |= (U << 8) | (Rn << 9); 5892 5893 if (writeback && (Rn == Rt || Rn == Rt2)) 5894 Check(S, MCDisassembler::SoftFail); 5895 if (Rt == Rt2) 5896 Check(S, MCDisassembler::SoftFail); 5897 5898 // Rt 5899 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5900 return MCDisassembler::Fail; 5901 // Rt2 5902 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5903 return MCDisassembler::Fail; 5904 // Writeback operand 5905 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5906 return MCDisassembler::Fail; 5907 // addr 5908 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5909 return MCDisassembler::Fail; 5910 5911 return S; 5912 } 5913 5914 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5915 uint64_t Address, 5916 const MCDisassembler *Decoder) { 5917 DecodeStatus S = MCDisassembler::Success; 5918 5919 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5920 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5921 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5922 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5923 unsigned W = fieldFromInstruction(Insn, 21, 1); 5924 unsigned U = fieldFromInstruction(Insn, 23, 1); 5925 unsigned P = fieldFromInstruction(Insn, 24, 1); 5926 bool writeback = (W == 1) | (P == 0); 5927 5928 addr |= (U << 8) | (Rn << 9); 5929 5930 if (writeback && (Rn == Rt || Rn == Rt2)) 5931 Check(S, MCDisassembler::SoftFail); 5932 5933 // Writeback operand 5934 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5935 return MCDisassembler::Fail; 5936 // Rt 5937 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5938 return MCDisassembler::Fail; 5939 // Rt2 5940 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5941 return MCDisassembler::Fail; 5942 // addr 5943 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5944 return MCDisassembler::Fail; 5945 5946 return S; 5947 } 5948 5949 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, 5950 const MCDisassembler *Decoder) { 5951 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5952 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5953 if (sign1 != sign2) return MCDisassembler::Fail; 5954 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5955 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5956 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5957 5958 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5959 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5960 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5961 // If sign, then it is decreasing the address. 5962 if (sign1) { 5963 // Following ARMv7 Architecture Manual, when the offset 5964 // is zero, it is decoded as a subw, not as a adr.w 5965 if (!Val) { 5966 Inst.setOpcode(ARM::t2SUBri12); 5967 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5968 } else 5969 Val = -Val; 5970 } 5971 Inst.addOperand(MCOperand::createImm(Val)); 5972 return S; 5973 } 5974 5975 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5976 uint64_t Address, 5977 const MCDisassembler *Decoder) { 5978 DecodeStatus S = MCDisassembler::Success; 5979 5980 // Shift of "asr #32" is not allowed in Thumb2 mode. 5981 if (Val == 0x20) S = MCDisassembler::Fail; 5982 Inst.addOperand(MCOperand::createImm(Val)); 5983 return S; 5984 } 5985 5986 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 5987 const MCDisassembler *Decoder) { 5988 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5989 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5990 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5991 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5992 5993 if (pred == 0xF) 5994 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5995 5996 DecodeStatus S = MCDisassembler::Success; 5997 5998 if (Rt == Rn || Rn == Rt2) 5999 S = MCDisassembler::SoftFail; 6000 6001 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6002 return MCDisassembler::Fail; 6003 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6004 return MCDisassembler::Fail; 6005 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6006 return MCDisassembler::Fail; 6007 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6008 return MCDisassembler::Fail; 6009 6010 return S; 6011 } 6012 6013 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 6014 const MCDisassembler *Decoder) { 6015 const FeatureBitset &featureBits = 6016 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6017 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6018 6019 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6020 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6021 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6022 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6023 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6024 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6025 unsigned op = fieldFromInstruction(Insn, 5, 1); 6026 6027 DecodeStatus S = MCDisassembler::Success; 6028 6029 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6030 if (!(imm & 0x38)) { 6031 if (cmode == 0xF) { 6032 if (op == 1) return MCDisassembler::Fail; 6033 Inst.setOpcode(ARM::VMOVv2f32); 6034 } 6035 if (hasFullFP16) { 6036 if (cmode == 0xE) { 6037 if (op == 1) { 6038 Inst.setOpcode(ARM::VMOVv1i64); 6039 } else { 6040 Inst.setOpcode(ARM::VMOVv8i8); 6041 } 6042 } 6043 if (cmode == 0xD) { 6044 if (op == 1) { 6045 Inst.setOpcode(ARM::VMVNv2i32); 6046 } else { 6047 Inst.setOpcode(ARM::VMOVv2i32); 6048 } 6049 } 6050 if (cmode == 0xC) { 6051 if (op == 1) { 6052 Inst.setOpcode(ARM::VMVNv2i32); 6053 } else { 6054 Inst.setOpcode(ARM::VMOVv2i32); 6055 } 6056 } 6057 } 6058 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6059 } 6060 6061 if (!(imm & 0x20)) return MCDisassembler::Fail; 6062 6063 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 6064 return MCDisassembler::Fail; 6065 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6066 return MCDisassembler::Fail; 6067 Inst.addOperand(MCOperand::createImm(64 - imm)); 6068 6069 return S; 6070 } 6071 6072 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 6073 const MCDisassembler *Decoder) { 6074 const FeatureBitset &featureBits = 6075 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6076 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6077 6078 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6079 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6080 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6081 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6082 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6083 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6084 unsigned op = fieldFromInstruction(Insn, 5, 1); 6085 6086 DecodeStatus S = MCDisassembler::Success; 6087 6088 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6089 if (!(imm & 0x38)) { 6090 if (cmode == 0xF) { 6091 if (op == 1) return MCDisassembler::Fail; 6092 Inst.setOpcode(ARM::VMOVv4f32); 6093 } 6094 if (hasFullFP16) { 6095 if (cmode == 0xE) { 6096 if (op == 1) { 6097 Inst.setOpcode(ARM::VMOVv2i64); 6098 } else { 6099 Inst.setOpcode(ARM::VMOVv16i8); 6100 } 6101 } 6102 if (cmode == 0xD) { 6103 if (op == 1) { 6104 Inst.setOpcode(ARM::VMVNv4i32); 6105 } else { 6106 Inst.setOpcode(ARM::VMOVv4i32); 6107 } 6108 } 6109 if (cmode == 0xC) { 6110 if (op == 1) { 6111 Inst.setOpcode(ARM::VMVNv4i32); 6112 } else { 6113 Inst.setOpcode(ARM::VMOVv4i32); 6114 } 6115 } 6116 } 6117 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6118 } 6119 6120 if (!(imm & 0x20)) return MCDisassembler::Fail; 6121 6122 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 6123 return MCDisassembler::Fail; 6124 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 6125 return MCDisassembler::Fail; 6126 Inst.addOperand(MCOperand::createImm(64 - imm)); 6127 6128 return S; 6129 } 6130 6131 static DecodeStatus 6132 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, 6133 uint64_t Address, 6134 const MCDisassembler *Decoder) { 6135 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6136 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6137 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 6138 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 6139 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6140 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6141 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 6142 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 6143 6144 DecodeStatus S = MCDisassembler::Success; 6145 6146 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 6147 6148 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6149 return MCDisassembler::Fail; 6150 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6151 return MCDisassembler::Fail; 6152 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 6153 return MCDisassembler::Fail; 6154 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6155 return MCDisassembler::Fail; 6156 // The lane index does not have any bits in the encoding, because it can only 6157 // be 0. 6158 Inst.addOperand(MCOperand::createImm(0)); 6159 Inst.addOperand(MCOperand::createImm(rotate)); 6160 6161 return S; 6162 } 6163 6164 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 6165 const MCDisassembler *Decoder) { 6166 DecodeStatus S = MCDisassembler::Success; 6167 6168 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6169 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6170 unsigned Rm = fieldFromInstruction(Val, 0, 4); 6171 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 6172 unsigned Cond = fieldFromInstruction(Val, 28, 4); 6173 6174 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 6175 S = MCDisassembler::SoftFail; 6176 6177 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6178 return MCDisassembler::Fail; 6179 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6180 return MCDisassembler::Fail; 6181 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 6182 return MCDisassembler::Fail; 6183 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 6184 return MCDisassembler::Fail; 6185 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 6186 return MCDisassembler::Fail; 6187 6188 return S; 6189 } 6190 6191 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 6192 uint64_t Address, 6193 const MCDisassembler *Decoder) { 6194 DecodeStatus S = MCDisassembler::Success; 6195 6196 unsigned CRm = fieldFromInstruction(Val, 0, 4); 6197 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 6198 unsigned cop = fieldFromInstruction(Val, 8, 4); 6199 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6200 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 6201 6202 if ((cop & ~0x1) == 0xa) 6203 return MCDisassembler::Fail; 6204 6205 if (Rt == Rt2) 6206 S = MCDisassembler::SoftFail; 6207 6208 // We have to check if the instruction is MRRC2 6209 // or MCRR2 when constructing the operands for 6210 // Inst. Reason is because MRRC2 stores to two 6211 // registers so it's tablegen desc has two 6212 // outputs whereas MCRR doesn't store to any 6213 // registers so all of it's operands are listed 6214 // as inputs, therefore the operand order for 6215 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 6216 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 6217 6218 if (Inst.getOpcode() == ARM::MRRC2) { 6219 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6220 return MCDisassembler::Fail; 6221 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6222 return MCDisassembler::Fail; 6223 } 6224 Inst.addOperand(MCOperand::createImm(cop)); 6225 Inst.addOperand(MCOperand::createImm(opc1)); 6226 if (Inst.getOpcode() == ARM::MCRR2) { 6227 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6228 return MCDisassembler::Fail; 6229 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6230 return MCDisassembler::Fail; 6231 } 6232 Inst.addOperand(MCOperand::createImm(CRm)); 6233 6234 return S; 6235 } 6236 6237 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 6238 uint64_t Address, 6239 const MCDisassembler *Decoder) { 6240 const FeatureBitset &featureBits = 6241 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6242 DecodeStatus S = MCDisassembler::Success; 6243 6244 // Add explicit operand for the destination sysreg, for cases where 6245 // we have to model it for code generation purposes. 6246 switch (Inst.getOpcode()) { 6247 case ARM::VMSR_FPSCR_NZCVQC: 6248 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6249 break; 6250 case ARM::VMSR_P0: 6251 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6252 break; 6253 } 6254 6255 if (Inst.getOpcode() != ARM::FMSTAT) { 6256 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6257 6258 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 6259 if (Rt == 13 || Rt == 15) 6260 S = MCDisassembler::SoftFail; 6261 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 6262 } else 6263 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 6264 } 6265 6266 // Add explicit operand for the source sysreg, similarly to above. 6267 switch (Inst.getOpcode()) { 6268 case ARM::VMRS_FPSCR_NZCVQC: 6269 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6270 break; 6271 case ARM::VMRS_P0: 6272 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6273 break; 6274 } 6275 6276 if (featureBits[ARM::ModeThumb]) { 6277 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6278 Inst.addOperand(MCOperand::createReg(0)); 6279 } else { 6280 unsigned pred = fieldFromInstruction(Val, 28, 4); 6281 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6282 return MCDisassembler::Fail; 6283 } 6284 6285 return S; 6286 } 6287 6288 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 6289 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 6290 uint64_t Address, 6291 const MCDisassembler *Decoder) { 6292 DecodeStatus S = MCDisassembler::Success; 6293 if (Val == 0 && !zeroPermitted) 6294 S = MCDisassembler::Fail; 6295 6296 uint64_t DecVal; 6297 if (isSigned) 6298 DecVal = SignExtend32<size + 1>(Val << 1); 6299 else 6300 DecVal = (Val << 1); 6301 6302 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 6303 Decoder)) 6304 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 6305 return S; 6306 } 6307 6308 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 6309 uint64_t Address, 6310 const MCDisassembler *Decoder) { 6311 6312 uint64_t LocImm = Inst.getOperand(0).getImm(); 6313 Val = LocImm + (2 << Val); 6314 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 6315 Decoder)) 6316 Inst.addOperand(MCOperand::createImm(Val)); 6317 return MCDisassembler::Success; 6318 } 6319 6320 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 6321 uint64_t Address, 6322 const MCDisassembler *Decoder) { 6323 if (Val >= ARMCC::AL) // also exclude the non-condition NV 6324 return MCDisassembler::Fail; 6325 Inst.addOperand(MCOperand::createImm(Val)); 6326 return MCDisassembler::Success; 6327 } 6328 6329 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6330 const MCDisassembler *Decoder) { 6331 DecodeStatus S = MCDisassembler::Success; 6332 6333 if (Inst.getOpcode() == ARM::MVE_LCTP) 6334 return S; 6335 6336 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6337 fieldFromInstruction(Insn, 1, 10) << 1; 6338 switch (Inst.getOpcode()) { 6339 case ARM::t2LEUpdate: 6340 case ARM::MVE_LETP: 6341 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6342 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6343 [[fallthrough]]; 6344 case ARM::t2LE: 6345 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6346 Inst, Imm, Address, Decoder))) 6347 return MCDisassembler::Fail; 6348 break; 6349 case ARM::t2WLS: 6350 case ARM::MVE_WLSTP_8: 6351 case ARM::MVE_WLSTP_16: 6352 case ARM::MVE_WLSTP_32: 6353 case ARM::MVE_WLSTP_64: 6354 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6355 if (!Check(S, 6356 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6357 Address, Decoder)) || 6358 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6359 Inst, Imm, Address, Decoder))) 6360 return MCDisassembler::Fail; 6361 break; 6362 case ARM::t2DLS: 6363 case ARM::MVE_DLSTP_8: 6364 case ARM::MVE_DLSTP_16: 6365 case ARM::MVE_DLSTP_32: 6366 case ARM::MVE_DLSTP_64: 6367 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6368 if (Rn == 0xF) { 6369 // Enforce all the rest of the instruction bits in LCTP, which 6370 // won't have been reliably checked based on LCTP's own tablegen 6371 // record, because we came to this decode by a roundabout route. 6372 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6373 if ((Insn & ~SBZMask) != CanonicalLCTP) 6374 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6375 if (Insn != CanonicalLCTP) 6376 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6377 6378 Inst.setOpcode(ARM::MVE_LCTP); 6379 } else { 6380 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6381 if (!Check(S, DecoderGPRRegisterClass(Inst, 6382 fieldFromInstruction(Insn, 16, 4), 6383 Address, Decoder))) 6384 return MCDisassembler::Fail; 6385 } 6386 break; 6387 } 6388 return S; 6389 } 6390 6391 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6392 uint64_t Address, 6393 const MCDisassembler *Decoder) { 6394 DecodeStatus S = MCDisassembler::Success; 6395 6396 if (Val == 0) 6397 Val = 32; 6398 6399 Inst.addOperand(MCOperand::createImm(Val)); 6400 6401 return S; 6402 } 6403 6404 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6405 uint64_t Address, 6406 const MCDisassembler *Decoder) { 6407 if ((RegNo) + 1 > 11) 6408 return MCDisassembler::Fail; 6409 6410 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6411 Inst.addOperand(MCOperand::createReg(Register)); 6412 return MCDisassembler::Success; 6413 } 6414 6415 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6416 uint64_t Address, 6417 const MCDisassembler *Decoder) { 6418 if ((RegNo) > 14) 6419 return MCDisassembler::Fail; 6420 6421 unsigned Register = GPRDecoderTable[(RegNo)]; 6422 Inst.addOperand(MCOperand::createReg(Register)); 6423 return MCDisassembler::Success; 6424 } 6425 6426 static DecodeStatus 6427 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6428 uint64_t Address, 6429 const MCDisassembler *Decoder) { 6430 if (RegNo == 15) { 6431 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6432 return MCDisassembler::Success; 6433 } 6434 6435 unsigned Register = GPRDecoderTable[RegNo]; 6436 Inst.addOperand(MCOperand::createReg(Register)); 6437 6438 if (RegNo == 13) 6439 return MCDisassembler::SoftFail; 6440 6441 return MCDisassembler::Success; 6442 } 6443 6444 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6445 const MCDisassembler *Decoder) { 6446 DecodeStatus S = MCDisassembler::Success; 6447 6448 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6449 Inst.addOperand(MCOperand::createReg(0)); 6450 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6451 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6452 (fieldFromInstruction(Insn, 12, 4) << 8) | 6453 (fieldFromInstruction(Insn, 22, 1) << 12); 6454 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6455 return MCDisassembler::Fail; 6456 } 6457 } else { 6458 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6459 (fieldFromInstruction(Insn, 22, 1) << 8) | 6460 (fieldFromInstruction(Insn, 12, 4) << 9); 6461 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6462 return MCDisassembler::Fail; 6463 } 6464 } 6465 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6466 6467 return S; 6468 } 6469 6470 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6471 uint64_t Address, 6472 const MCDisassembler *Decoder) { 6473 if (RegNo > 7) 6474 return MCDisassembler::Fail; 6475 6476 unsigned Register = QPRDecoderTable[RegNo]; 6477 Inst.addOperand(MCOperand::createReg(Register)); 6478 return MCDisassembler::Success; 6479 } 6480 6481 static const uint16_t QQPRDecoderTable[] = { 6482 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6483 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6484 }; 6485 6486 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6487 uint64_t Address, 6488 const MCDisassembler *Decoder) { 6489 if (RegNo > 6) 6490 return MCDisassembler::Fail; 6491 6492 unsigned Register = QQPRDecoderTable[RegNo]; 6493 Inst.addOperand(MCOperand::createReg(Register)); 6494 return MCDisassembler::Success; 6495 } 6496 6497 static const uint16_t QQQQPRDecoderTable[] = { 6498 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6499 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6500 }; 6501 6502 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6503 uint64_t Address, 6504 const MCDisassembler *Decoder) { 6505 if (RegNo > 4) 6506 return MCDisassembler::Fail; 6507 6508 unsigned Register = QQQQPRDecoderTable[RegNo]; 6509 Inst.addOperand(MCOperand::createReg(Register)); 6510 return MCDisassembler::Success; 6511 } 6512 6513 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6514 uint64_t Address, 6515 const MCDisassembler *Decoder) { 6516 DecodeStatus S = MCDisassembler::Success; 6517 6518 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6519 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6520 // 't' as 0 and finish with a 1. 6521 unsigned Imm = 0; 6522 // We always start with a 't'. 6523 unsigned CurBit = 0; 6524 for (int i = 3; i >= 0; --i) { 6525 // If the bit we are looking at is not the same as last one, invert the 6526 // CurBit, if it is the same leave it as is. 6527 CurBit ^= (Val >> i) & 1U; 6528 6529 // Encode the CurBit at the right place in the immediate. 6530 Imm |= (CurBit << i); 6531 6532 // If we are done, finish the encoding with a 1. 6533 if ((Val & ~(~0U << i)) == 0) { 6534 Imm |= 1U << i; 6535 break; 6536 } 6537 } 6538 6539 Inst.addOperand(MCOperand::createImm(Imm)); 6540 6541 return S; 6542 } 6543 6544 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6545 uint64_t Address, 6546 const MCDisassembler *Decoder) { 6547 // The vpred_r operand type includes an MQPR register field derived 6548 // from the encoding. But we don't actually want to add an operand 6549 // to the MCInst at this stage, because AddThumbPredicate will do it 6550 // later, and will infer the register number from the TIED_TO 6551 // constraint. So this is a deliberately empty decoder method that 6552 // will inhibit the auto-generated disassembly code from adding an 6553 // operand at all. 6554 return MCDisassembler::Success; 6555 } 6556 6557 [[maybe_unused]] static DecodeStatus 6558 DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address, 6559 const MCDisassembler *Decoder) { 6560 // Similar to above, we want to ensure that no operands are added for the 6561 // vpred operands. (This is marked "maybe_unused" for the moment; because 6562 // DecoderEmitter currently (wrongly) omits operands with no instruction bits, 6563 // the decoder doesn't actually call it yet. That will be addressed in a 6564 // future change.) 6565 return MCDisassembler::Success; 6566 } 6567 6568 static DecodeStatus 6569 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6570 const MCDisassembler *Decoder) { 6571 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6572 return MCDisassembler::Success; 6573 } 6574 6575 static DecodeStatus 6576 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6577 const MCDisassembler *Decoder) { 6578 unsigned Code; 6579 switch (Val & 0x3) { 6580 case 0: 6581 Code = ARMCC::GE; 6582 break; 6583 case 1: 6584 Code = ARMCC::LT; 6585 break; 6586 case 2: 6587 Code = ARMCC::GT; 6588 break; 6589 case 3: 6590 Code = ARMCC::LE; 6591 break; 6592 } 6593 Inst.addOperand(MCOperand::createImm(Code)); 6594 return MCDisassembler::Success; 6595 } 6596 6597 static DecodeStatus 6598 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6599 const MCDisassembler *Decoder) { 6600 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6601 return MCDisassembler::Success; 6602 } 6603 6604 static DecodeStatus 6605 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6606 const MCDisassembler *Decoder) { 6607 unsigned Code; 6608 switch (Val) { 6609 default: 6610 return MCDisassembler::Fail; 6611 case 0: 6612 Code = ARMCC::EQ; 6613 break; 6614 case 1: 6615 Code = ARMCC::NE; 6616 break; 6617 case 4: 6618 Code = ARMCC::GE; 6619 break; 6620 case 5: 6621 Code = ARMCC::LT; 6622 break; 6623 case 6: 6624 Code = ARMCC::GT; 6625 break; 6626 case 7: 6627 Code = ARMCC::LE; 6628 break; 6629 } 6630 6631 Inst.addOperand(MCOperand::createImm(Code)); 6632 return MCDisassembler::Success; 6633 } 6634 6635 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6636 uint64_t Address, 6637 const MCDisassembler *Decoder) { 6638 DecodeStatus S = MCDisassembler::Success; 6639 6640 unsigned DecodedVal = 64 - Val; 6641 6642 switch (Inst.getOpcode()) { 6643 case ARM::MVE_VCVTf16s16_fix: 6644 case ARM::MVE_VCVTs16f16_fix: 6645 case ARM::MVE_VCVTf16u16_fix: 6646 case ARM::MVE_VCVTu16f16_fix: 6647 if (DecodedVal > 16) 6648 return MCDisassembler::Fail; 6649 break; 6650 case ARM::MVE_VCVTf32s32_fix: 6651 case ARM::MVE_VCVTs32f32_fix: 6652 case ARM::MVE_VCVTf32u32_fix: 6653 case ARM::MVE_VCVTu32f32_fix: 6654 if (DecodedVal > 32) 6655 return MCDisassembler::Fail; 6656 break; 6657 } 6658 6659 Inst.addOperand(MCOperand::createImm(64 - Val)); 6660 6661 return S; 6662 } 6663 6664 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6665 switch (Opcode) { 6666 case ARM::VSTR_P0_off: 6667 case ARM::VSTR_P0_pre: 6668 case ARM::VSTR_P0_post: 6669 case ARM::VLDR_P0_off: 6670 case ARM::VLDR_P0_pre: 6671 case ARM::VLDR_P0_post: 6672 return ARM::P0; 6673 default: 6674 return 0; 6675 } 6676 } 6677 6678 template <bool Writeback> 6679 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6680 uint64_t Address, 6681 const MCDisassembler *Decoder) { 6682 switch (Inst.getOpcode()) { 6683 case ARM::VSTR_FPSCR_pre: 6684 case ARM::VSTR_FPSCR_NZCVQC_pre: 6685 case ARM::VLDR_FPSCR_pre: 6686 case ARM::VLDR_FPSCR_NZCVQC_pre: 6687 case ARM::VSTR_FPSCR_off: 6688 case ARM::VSTR_FPSCR_NZCVQC_off: 6689 case ARM::VLDR_FPSCR_off: 6690 case ARM::VLDR_FPSCR_NZCVQC_off: 6691 case ARM::VSTR_FPSCR_post: 6692 case ARM::VSTR_FPSCR_NZCVQC_post: 6693 case ARM::VLDR_FPSCR_post: 6694 case ARM::VLDR_FPSCR_NZCVQC_post: 6695 const FeatureBitset &featureBits = 6696 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6697 6698 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6699 return MCDisassembler::Fail; 6700 } 6701 6702 DecodeStatus S = MCDisassembler::Success; 6703 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6704 Inst.addOperand(MCOperand::createReg(Sysreg)); 6705 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6706 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6707 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6708 6709 if (Writeback) { 6710 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6711 return MCDisassembler::Fail; 6712 } 6713 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6714 return MCDisassembler::Fail; 6715 6716 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6717 Inst.addOperand(MCOperand::createReg(0)); 6718 6719 return S; 6720 } 6721 6722 static inline DecodeStatus 6723 DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, 6724 const MCDisassembler *Decoder, unsigned Rn, 6725 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6726 DecodeStatus S = MCDisassembler::Success; 6727 6728 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6729 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6730 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6731 6732 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6733 return MCDisassembler::Fail; 6734 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6735 return MCDisassembler::Fail; 6736 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6737 return MCDisassembler::Fail; 6738 6739 return S; 6740 } 6741 6742 template <int shift> 6743 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6744 uint64_t Address, 6745 const MCDisassembler *Decoder) { 6746 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6747 fieldFromInstruction(Val, 16, 3), 6748 DecodetGPRRegisterClass, 6749 DecodeTAddrModeImm7<shift>); 6750 } 6751 6752 template <int shift> 6753 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6754 uint64_t Address, 6755 const MCDisassembler *Decoder) { 6756 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6757 fieldFromInstruction(Val, 16, 4), 6758 DecoderGPRRegisterClass, 6759 DecodeT2AddrModeImm7<shift,1>); 6760 } 6761 6762 template <int shift> 6763 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6764 uint64_t Address, 6765 const MCDisassembler *Decoder) { 6766 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6767 fieldFromInstruction(Val, 17, 3), 6768 DecodeMQPRRegisterClass, 6769 DecodeMveAddrModeQ<shift>); 6770 } 6771 6772 template <unsigned MinLog, unsigned MaxLog> 6773 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6774 uint64_t Address, 6775 const MCDisassembler *Decoder) { 6776 DecodeStatus S = MCDisassembler::Success; 6777 6778 if (Val < MinLog || Val > MaxLog) 6779 return MCDisassembler::Fail; 6780 6781 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6782 return S; 6783 } 6784 6785 template <unsigned start> 6786 static DecodeStatus 6787 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6788 const MCDisassembler *Decoder) { 6789 DecodeStatus S = MCDisassembler::Success; 6790 6791 Inst.addOperand(MCOperand::createImm(start + Val)); 6792 6793 return S; 6794 } 6795 6796 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6797 uint64_t Address, 6798 const MCDisassembler *Decoder) { 6799 DecodeStatus S = MCDisassembler::Success; 6800 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6801 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6802 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6803 fieldFromInstruction(Insn, 13, 3)); 6804 unsigned index = fieldFromInstruction(Insn, 4, 1); 6805 6806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6807 return MCDisassembler::Fail; 6808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6809 return MCDisassembler::Fail; 6810 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6811 return MCDisassembler::Fail; 6812 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6813 return MCDisassembler::Fail; 6814 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6815 return MCDisassembler::Fail; 6816 6817 return S; 6818 } 6819 6820 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6821 uint64_t Address, 6822 const MCDisassembler *Decoder) { 6823 DecodeStatus S = MCDisassembler::Success; 6824 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6825 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6826 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6827 fieldFromInstruction(Insn, 13, 3)); 6828 unsigned index = fieldFromInstruction(Insn, 4, 1); 6829 6830 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6831 return MCDisassembler::Fail; 6832 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6833 return MCDisassembler::Fail; 6834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6835 return MCDisassembler::Fail; 6836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6837 return MCDisassembler::Fail; 6838 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6839 return MCDisassembler::Fail; 6840 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6841 return MCDisassembler::Fail; 6842 6843 return S; 6844 } 6845 6846 static DecodeStatus 6847 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 6848 const MCDisassembler *Decoder) { 6849 DecodeStatus S = MCDisassembler::Success; 6850 6851 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6852 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6853 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6854 6855 if (RdaHi == 14) { 6856 // This value of RdaHi (really indicating pc, because RdaHi has to 6857 // be an odd-numbered register, so the low bit will be set by the 6858 // decode function below) indicates that we must decode as SQRSHR 6859 // or UQRSHL, which both have a single Rda register field with all 6860 // four bits. 6861 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6862 6863 switch (Inst.getOpcode()) { 6864 case ARM::MVE_ASRLr: 6865 case ARM::MVE_SQRSHRL: 6866 Inst.setOpcode(ARM::MVE_SQRSHR); 6867 break; 6868 case ARM::MVE_LSLLr: 6869 case ARM::MVE_UQRSHLL: 6870 Inst.setOpcode(ARM::MVE_UQRSHL); 6871 break; 6872 default: 6873 llvm_unreachable("Unexpected starting opcode!"); 6874 } 6875 6876 // Rda as output parameter 6877 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6878 return MCDisassembler::Fail; 6879 6880 // Rda again as input parameter 6881 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6882 return MCDisassembler::Fail; 6883 6884 // Rm, the amount to shift by 6885 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6886 return MCDisassembler::Fail; 6887 6888 if (fieldFromInstruction (Insn, 6, 3) != 4) 6889 return MCDisassembler::SoftFail; 6890 6891 if (Rda == Rm) 6892 return MCDisassembler::SoftFail; 6893 6894 return S; 6895 } 6896 6897 // Otherwise, we decode as whichever opcode our caller has already 6898 // put into Inst. Those all look the same: 6899 6900 // RdaLo,RdaHi as output parameters 6901 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6902 return MCDisassembler::Fail; 6903 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6904 return MCDisassembler::Fail; 6905 6906 // RdaLo,RdaHi again as input parameters 6907 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6908 return MCDisassembler::Fail; 6909 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6910 return MCDisassembler::Fail; 6911 6912 // Rm, the amount to shift by 6913 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6914 return MCDisassembler::Fail; 6915 6916 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6917 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6918 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6919 // Saturate, the bit position for saturation 6920 Inst.addOperand(MCOperand::createImm(Saturate)); 6921 } 6922 6923 return S; 6924 } 6925 6926 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 6927 uint64_t Address, 6928 const MCDisassembler *Decoder) { 6929 DecodeStatus S = MCDisassembler::Success; 6930 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6931 fieldFromInstruction(Insn, 13, 3)); 6932 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6933 fieldFromInstruction(Insn, 1, 3)); 6934 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6935 6936 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6937 return MCDisassembler::Fail; 6938 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6939 return MCDisassembler::Fail; 6940 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6941 return MCDisassembler::Fail; 6942 6943 return S; 6944 } 6945 6946 template <bool scalar, OperandDecoder predicate_decoder> 6947 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6948 const MCDisassembler *Decoder) { 6949 DecodeStatus S = MCDisassembler::Success; 6950 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6951 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6952 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6953 return MCDisassembler::Fail; 6954 6955 unsigned fc; 6956 6957 if (scalar) { 6958 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6959 fieldFromInstruction(Insn, 7, 1) | 6960 fieldFromInstruction(Insn, 5, 1) << 1; 6961 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6962 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6963 return MCDisassembler::Fail; 6964 } else { 6965 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6966 fieldFromInstruction(Insn, 7, 1) | 6967 fieldFromInstruction(Insn, 0, 1) << 1; 6968 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6969 fieldFromInstruction(Insn, 1, 3); 6970 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6971 return MCDisassembler::Fail; 6972 } 6973 6974 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6975 return MCDisassembler::Fail; 6976 6977 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6978 Inst.addOperand(MCOperand::createReg(0)); 6979 Inst.addOperand(MCOperand::createImm(0)); 6980 6981 return S; 6982 } 6983 6984 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6985 const MCDisassembler *Decoder) { 6986 DecodeStatus S = MCDisassembler::Success; 6987 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6988 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6989 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6990 return MCDisassembler::Fail; 6991 return S; 6992 } 6993 6994 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 6995 uint64_t Address, 6996 const MCDisassembler *Decoder) { 6997 DecodeStatus S = MCDisassembler::Success; 6998 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6999 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 7000 return S; 7001 } 7002 7003 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 7004 uint64_t Address, 7005 const MCDisassembler *Decoder) { 7006 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 7007 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 7008 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 7009 fieldFromInstruction(Insn, 12, 3) << 8 | 7010 fieldFromInstruction(Insn, 0, 8); 7011 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 7012 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 7013 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 7014 unsigned S = fieldFromInstruction(Insn, 20, 1); 7015 if (sign1 != sign2) 7016 return MCDisassembler::Fail; 7017 7018 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 7019 DecodeStatus DS = MCDisassembler::Success; 7020 if ((!Check(DS, 7021 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 7022 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 7023 return MCDisassembler::Fail; 7024 if (TypeT3) { 7025 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 7026 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 7027 } else { 7028 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 7029 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 7030 return MCDisassembler::Fail; 7031 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 7032 return MCDisassembler::Fail; 7033 } 7034 7035 return DS; 7036 } 7037 7038 static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, 7039 uint64_t Address, 7040 const MCDisassembler *Decoder) { 7041 DecodeStatus S = MCDisassembler::Success; 7042 7043 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 7044 // Adding Rn, holding memory location to save/load to/from, the only argument 7045 // that is being encoded. 7046 // '$Rn' in the assembly. 7047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 7048 return MCDisassembler::Fail; 7049 // An optional predicate, '$p' in the assembly. 7050 DecodePredicateOperand(Inst, ARMCC::AL, Address, Decoder); 7051 // An immediate that represents a floating point registers list. '$regs' in 7052 // the assembly. 7053 Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect. 7054 7055 return S; 7056 } 7057