1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &VStream, 141 raw_ostream &CStream) const override; 142 }; 143 144 /// Thumb disassembler for all Thumb platforms. 145 class ThumbDisassembler : public MCDisassembler { 146 public: 147 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 148 MCDisassembler(STI, Ctx) { 149 } 150 151 ~ThumbDisassembler() override = default; 152 153 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 154 ArrayRef<uint8_t> Bytes, uint64_t Address, 155 raw_ostream &VStream, 156 raw_ostream &CStream) const override; 157 158 private: 159 mutable ITStatus ITBlock; 160 mutable VPTStatus VPTBlock; 161 162 DecodeStatus AddThumbPredicate(MCInst&) const; 163 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 164 }; 165 166 } // end anonymous namespace 167 168 static bool Check(DecodeStatus &Out, DecodeStatus In) { 169 switch (In) { 170 case MCDisassembler::Success: 171 // Out stays the same. 172 return true; 173 case MCDisassembler::SoftFail: 174 Out = In; 175 return true; 176 case MCDisassembler::Fail: 177 Out = In; 178 return false; 179 } 180 llvm_unreachable("Invalid DecodeStatus!"); 181 } 182 183 // Forward declare these because the autogenerated code will reference them. 184 // Definitions are further down. 185 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 194 unsigned RegNo, uint64_t Address, 195 const void *Decoder); 196 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 197 unsigned RegNo, uint64_t Address, 198 const void *Decoder); 199 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 200 unsigned RegNo, uint64_t Address, 201 const void *Decoder); 202 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Address, 223 const void *Decoder); 224 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 231 unsigned RegNo, uint64_t Address, 232 const void *Decoder); 233 234 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 245 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 250 unsigned Insn, 251 uint64_t Address, 252 const void *Decoder); 253 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 260 uint64_t Address, const void *Decoder); 261 262 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 263 unsigned Insn, 264 uint64_t Adddress, 265 const void *Decoder); 266 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 381 unsigned Val, 382 uint64_t Address, 383 const void *Decoder); 384 385 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 406 uint64_t Address, const void* Decoder); 407 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 408 uint64_t Address, const void* Decoder); 409 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 410 uint64_t Address, const void* Decoder); 411 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 412 uint64_t Address, const void* Decoder); 413 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 414 uint64_t Address, const void *Decoder); 415 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 416 uint64_t Address, const void *Decoder); 417 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 418 uint64_t Address, const void *Decoder); 419 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 420 uint64_t Address, 421 const void *Decoder); 422 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 423 uint64_t Address, const void *Decoder); 424 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 425 uint64_t Address, const void *Decoder); 426 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 427 uint64_t Address, const void *Decoder); 428 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 429 uint64_t Address, const void *Decoder); 430 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 431 uint64_t Address, const void *Decoder); 432 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 433 uint64_t Address, const void *Decoder); 434 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 435 uint64_t Address, const void *Decoder); 436 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 437 uint64_t Address, const void *Decoder); 438 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 439 uint64_t Address, const void *Decoder); 440 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 441 uint64_t Address, const void *Decoder); 442 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 443 uint64_t Address, const void *Decoder); 444 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 447 uint64_t Address, const void *Decoder); 448 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 449 uint64_t Address, const void *Decoder); 450 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 451 uint64_t Address, const void *Decoder); 452 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 453 uint64_t Address, const void *Decoder); 454 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 455 uint64_t Address, const void *Decoder); 456 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 457 uint64_t Address, const void *Decoder); 458 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 459 uint64_t Address, const void *Decoder); 460 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 461 uint64_t Address, const void *Decoder); 462 463 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 464 uint64_t Address, const void *Decoder); 465 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 466 uint64_t Address, const void *Decoder); 467 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 468 uint64_t Address, const void *Decoder); 469 470 template <bool isSigned, bool isNeg, int size> 471 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 472 uint64_t Address, const void *Decoder); 473 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 474 uint64_t Address, 475 const void *Decoder); 476 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 477 uint64_t Address, 478 const void *Decoder); 479 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 480 const void *Decoder); 481 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 482 uint64_t Address, 483 const void *Decoder); 484 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 485 const void *Decoder); 486 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 489 uint64_t Address, const void *Decoder); 490 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 491 uint64_t Address, 492 const void *Decoder); 493 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 494 uint64_t Address, 495 const void *Decoder); 496 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 497 uint64_t Address, 498 const void *Decoder); 499 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 500 unsigned Val, 501 uint64_t Address, 502 const void *Decoder); 503 template<bool Writeback> 504 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 505 uint64_t Address, 506 const void *Decoder); 507 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 508 uint64_t Address, 509 const void *Decoder); 510 #include "ARMGenDisassemblerTables.inc" 511 512 static MCDisassembler *createARMDisassembler(const Target &T, 513 const MCSubtargetInfo &STI, 514 MCContext &Ctx) { 515 return new ARMDisassembler(STI, Ctx); 516 } 517 518 static MCDisassembler *createThumbDisassembler(const Target &T, 519 const MCSubtargetInfo &STI, 520 MCContext &Ctx) { 521 return new ThumbDisassembler(STI, Ctx); 522 } 523 524 // Post-decoding checks 525 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 526 uint64_t Address, raw_ostream &OS, 527 raw_ostream &CS, 528 uint32_t Insn, 529 DecodeStatus Result) { 530 switch (MI.getOpcode()) { 531 case ARM::HVC: { 532 // HVC is undefined if condition = 0xf otherwise upredictable 533 // if condition != 0xe 534 uint32_t Cond = (Insn >> 28) & 0xF; 535 if (Cond == 0xF) 536 return MCDisassembler::Fail; 537 if (Cond != 0xE) 538 return MCDisassembler::SoftFail; 539 return Result; 540 } 541 case ARM::t2ADDri: 542 case ARM::t2ADDri12: 543 case ARM::t2ADDrr: 544 case ARM::t2ADDrs: 545 case ARM::t2SUBri: 546 case ARM::t2SUBri12: 547 case ARM::t2SUBrr: 548 case ARM::t2SUBrs: 549 if (MI.getOperand(0).getReg() == ARM::SP && 550 MI.getOperand(1).getReg() != ARM::SP) 551 return MCDisassembler::SoftFail; 552 return Result; 553 default: return Result; 554 } 555 } 556 557 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 558 ArrayRef<uint8_t> Bytes, 559 uint64_t Address, raw_ostream &OS, 560 raw_ostream &CS) const { 561 CommentStream = &CS; 562 563 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 564 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 565 "mode!"); 566 567 // We want to read exactly 4 bytes of data. 568 if (Bytes.size() < 4) { 569 Size = 0; 570 return MCDisassembler::Fail; 571 } 572 573 // Encoded as a small-endian 32-bit word in the stream. 574 uint32_t Insn = 575 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 576 577 // Calling the auto-generated decoder function. 578 DecodeStatus Result = 579 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 580 if (Result != MCDisassembler::Fail) { 581 Size = 4; 582 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 583 } 584 585 struct DecodeTable { 586 const uint8_t *P; 587 bool DecodePred; 588 }; 589 590 const DecodeTable Tables[] = { 591 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 592 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 593 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 594 {DecoderTablev8Crypto32, false}, 595 }; 596 597 for (auto Table : Tables) { 598 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 599 if (Result != MCDisassembler::Fail) { 600 Size = 4; 601 // Add a fake predicate operand, because we share these instruction 602 // definitions with Thumb2 where these instructions are predicable. 603 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 604 return MCDisassembler::Fail; 605 return Result; 606 } 607 } 608 609 Result = 610 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 611 if (Result != MCDisassembler::Fail) { 612 Size = 4; 613 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 614 } 615 616 Size = 4; 617 return MCDisassembler::Fail; 618 } 619 620 namespace llvm { 621 622 extern const MCInstrDesc ARMInsts[]; 623 624 } // end namespace llvm 625 626 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 627 /// immediate Value in the MCInst. The immediate Value has had any PC 628 /// adjustment made by the caller. If the instruction is a branch instruction 629 /// then isBranch is true, else false. If the getOpInfo() function was set as 630 /// part of the setupForSymbolicDisassembly() call then that function is called 631 /// to get any symbolic information at the Address for this instruction. If 632 /// that returns non-zero then the symbolic information it returns is used to 633 /// create an MCExpr and that is added as an operand to the MCInst. If 634 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 635 /// Value is done and if a symbol is found an MCExpr is created with that, else 636 /// an MCExpr with Value is created. This function returns true if it adds an 637 /// operand to the MCInst and false otherwise. 638 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 639 bool isBranch, uint64_t InstSize, 640 MCInst &MI, const void *Decoder) { 641 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 642 // FIXME: Does it make sense for value to be negative? 643 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 644 /* Offset */ 0, InstSize); 645 } 646 647 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 648 /// referenced by a load instruction with the base register that is the Pc. 649 /// These can often be values in a literal pool near the Address of the 650 /// instruction. The Address of the instruction and its immediate Value are 651 /// used as a possible literal pool entry. The SymbolLookUp call back will 652 /// return the name of a symbol referenced by the literal pool's entry if 653 /// the referenced address is that of a symbol. Or it will return a pointer to 654 /// a literal 'C' string if the referenced address of the literal pool's entry 655 /// is an address into a section with 'C' string literals. 656 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 657 const void *Decoder) { 658 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 659 Dis->tryAddingPcLoadReferenceComment(Value, Address); 660 } 661 662 // Thumb1 instructions don't have explicit S bits. Rather, they 663 // implicitly set CPSR. Since it's not represented in the encoding, the 664 // auto-generated decoder won't inject the CPSR operand. We need to fix 665 // that as a post-pass. 666 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 667 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 668 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 669 MCInst::iterator I = MI.begin(); 670 for (unsigned i = 0; i < NumOps; ++i, ++I) { 671 if (I == MI.end()) break; 672 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 673 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 674 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 675 return; 676 } 677 } 678 679 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 680 } 681 682 static bool isVectorPredicable(unsigned Opcode) { 683 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 684 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 685 for (unsigned i = 0; i < NumOps; ++i) { 686 if (ARM::isVpred(OpInfo[i].OperandType)) 687 return true; 688 } 689 return false; 690 } 691 692 // Most Thumb instructions don't have explicit predicates in the 693 // encoding, but rather get their predicates from IT context. We need 694 // to fix up the predicate operands using this context information as a 695 // post-pass. 696 MCDisassembler::DecodeStatus 697 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 698 MCDisassembler::DecodeStatus S = Success; 699 700 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 701 702 // A few instructions actually have predicates encoded in them. Don't 703 // try to overwrite it if we're seeing one of those. 704 switch (MI.getOpcode()) { 705 case ARM::tBcc: 706 case ARM::t2Bcc: 707 case ARM::tCBZ: 708 case ARM::tCBNZ: 709 case ARM::tCPS: 710 case ARM::t2CPS3p: 711 case ARM::t2CPS2p: 712 case ARM::t2CPS1p: 713 case ARM::t2CSEL: 714 case ARM::t2CSINC: 715 case ARM::t2CSINV: 716 case ARM::t2CSNEG: 717 case ARM::tMOVSr: 718 case ARM::tSETEND: 719 // Some instructions (mostly conditional branches) are not 720 // allowed in IT blocks. 721 if (ITBlock.instrInITBlock()) 722 S = SoftFail; 723 else 724 return Success; 725 break; 726 case ARM::t2HINT: 727 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 728 S = SoftFail; 729 break; 730 case ARM::tB: 731 case ARM::t2B: 732 case ARM::t2TBB: 733 case ARM::t2TBH: 734 // Some instructions (mostly unconditional branches) can 735 // only appears at the end of, or outside of, an IT. 736 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 737 S = SoftFail; 738 break; 739 default: 740 break; 741 } 742 743 // Warn on non-VPT predicable instruction in a VPT block and a VPT 744 // predicable instruction in an IT block 745 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 746 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 747 S = SoftFail; 748 749 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 750 // assume a predicate of AL. 751 unsigned CC = ARMCC::AL; 752 unsigned VCC = ARMVCC::None; 753 if (ITBlock.instrInITBlock()) { 754 CC = ITBlock.getITCC(); 755 ITBlock.advanceITState(); 756 } else if (VPTBlock.instrInVPTBlock()) { 757 VCC = VPTBlock.getVPTPred(); 758 VPTBlock.advanceVPTState(); 759 } 760 761 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 762 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 763 764 MCInst::iterator CCI = MI.begin(); 765 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 766 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 767 } 768 769 if (ARMInsts[MI.getOpcode()].isPredicable()) { 770 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 771 ++CCI; 772 if (CC == ARMCC::AL) 773 MI.insert(CCI, MCOperand::createReg(0)); 774 else 775 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 776 } else if (CC != ARMCC::AL) { 777 Check(S, SoftFail); 778 } 779 780 MCInst::iterator VCCI = MI.begin(); 781 unsigned VCCPos; 782 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 783 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 784 } 785 786 if (isVectorPredicable(MI.getOpcode())) { 787 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 788 ++VCCI; 789 if (VCC == ARMVCC::None) 790 MI.insert(VCCI, MCOperand::createReg(0)); 791 else 792 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 793 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 794 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 795 VCCPos + 2, MCOI::TIED_TO); 796 assert(TiedOp >= 0 && 797 "Inactive register in vpred_r is not tied to an output!"); 798 MI.insert(VCCI, MI.getOperand(TiedOp)); 799 } 800 } else if (VCC != ARMVCC::None) { 801 Check(S, SoftFail); 802 } 803 804 return S; 805 } 806 807 // Thumb VFP instructions are a special case. Because we share their 808 // encodings between ARM and Thumb modes, and they are predicable in ARM 809 // mode, the auto-generated decoder will give them an (incorrect) 810 // predicate operand. We need to rewrite these operands based on the IT 811 // context as a post-pass. 812 void ThumbDisassembler::UpdateThumbVFPPredicate( 813 DecodeStatus &S, MCInst &MI) const { 814 unsigned CC; 815 CC = ITBlock.getITCC(); 816 if (CC == 0xF) 817 CC = ARMCC::AL; 818 if (ITBlock.instrInITBlock()) 819 ITBlock.advanceITState(); 820 else if (VPTBlock.instrInVPTBlock()) { 821 CC = VPTBlock.getVPTPred(); 822 VPTBlock.advanceVPTState(); 823 } 824 825 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 826 MCInst::iterator I = MI.begin(); 827 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 828 for (unsigned i = 0; i < NumOps; ++i, ++I) { 829 if (OpInfo[i].isPredicate() ) { 830 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 831 Check(S, SoftFail); 832 I->setImm(CC); 833 ++I; 834 if (CC == ARMCC::AL) 835 I->setReg(0); 836 else 837 I->setReg(ARM::CPSR); 838 return; 839 } 840 } 841 } 842 843 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 844 ArrayRef<uint8_t> Bytes, 845 uint64_t Address, 846 raw_ostream &OS, 847 raw_ostream &CS) const { 848 CommentStream = &CS; 849 850 assert(STI.getFeatureBits()[ARM::ModeThumb] && 851 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 852 853 // We want to read exactly 2 bytes of data. 854 if (Bytes.size() < 2) { 855 Size = 0; 856 return MCDisassembler::Fail; 857 } 858 859 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 860 DecodeStatus Result = 861 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 862 if (Result != MCDisassembler::Fail) { 863 Size = 2; 864 Check(Result, AddThumbPredicate(MI)); 865 return Result; 866 } 867 868 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 869 STI); 870 if (Result) { 871 Size = 2; 872 bool InITBlock = ITBlock.instrInITBlock(); 873 Check(Result, AddThumbPredicate(MI)); 874 AddThumb1SBit(MI, InITBlock); 875 return Result; 876 } 877 878 Result = 879 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 880 if (Result != MCDisassembler::Fail) { 881 Size = 2; 882 883 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 884 // the Thumb predicate. 885 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 886 Result = MCDisassembler::SoftFail; 887 888 Check(Result, AddThumbPredicate(MI)); 889 890 // If we find an IT instruction, we need to parse its condition 891 // code and mask operands so that we can apply them correctly 892 // to the subsequent instructions. 893 if (MI.getOpcode() == ARM::t2IT) { 894 unsigned Firstcond = MI.getOperand(0).getImm(); 895 unsigned Mask = MI.getOperand(1).getImm(); 896 ITBlock.setITState(Firstcond, Mask); 897 898 // An IT instruction that would give a 'NV' predicate is unpredictable. 899 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 900 CS << "unpredictable IT predicate sequence"; 901 } 902 903 return Result; 904 } 905 906 // We want to read exactly 4 bytes of data. 907 if (Bytes.size() < 4) { 908 Size = 0; 909 return MCDisassembler::Fail; 910 } 911 912 uint32_t Insn32 = 913 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 914 915 Result = 916 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 917 if (Result != MCDisassembler::Fail) { 918 Size = 4; 919 920 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 921 // the VPT predicate. 922 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 923 Result = MCDisassembler::SoftFail; 924 925 Check(Result, AddThumbPredicate(MI)); 926 927 if (isVPTOpcode(MI.getOpcode())) { 928 unsigned Mask = MI.getOperand(0).getImm(); 929 VPTBlock.setVPTState(Mask); 930 } 931 932 return Result; 933 } 934 935 Result = 936 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 937 if (Result != MCDisassembler::Fail) { 938 Size = 4; 939 bool InITBlock = ITBlock.instrInITBlock(); 940 Check(Result, AddThumbPredicate(MI)); 941 AddThumb1SBit(MI, InITBlock); 942 return Result; 943 } 944 945 Result = 946 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 947 if (Result != MCDisassembler::Fail) { 948 Size = 4; 949 Check(Result, AddThumbPredicate(MI)); 950 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 951 } 952 953 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 954 Result = 955 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 956 if (Result != MCDisassembler::Fail) { 957 Size = 4; 958 UpdateThumbVFPPredicate(Result, MI); 959 return Result; 960 } 961 } 962 963 Result = 964 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 965 if (Result != MCDisassembler::Fail) { 966 Size = 4; 967 return Result; 968 } 969 970 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 971 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 972 STI); 973 if (Result != MCDisassembler::Fail) { 974 Size = 4; 975 Check(Result, AddThumbPredicate(MI)); 976 return Result; 977 } 978 } 979 980 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 981 uint32_t NEONLdStInsn = Insn32; 982 NEONLdStInsn &= 0xF0FFFFFF; 983 NEONLdStInsn |= 0x04000000; 984 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 985 Address, this, STI); 986 if (Result != MCDisassembler::Fail) { 987 Size = 4; 988 Check(Result, AddThumbPredicate(MI)); 989 return Result; 990 } 991 } 992 993 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 994 uint32_t NEONDataInsn = Insn32; 995 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 996 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 997 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 998 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 999 Address, this, STI); 1000 if (Result != MCDisassembler::Fail) { 1001 Size = 4; 1002 Check(Result, AddThumbPredicate(MI)); 1003 return Result; 1004 } 1005 1006 uint32_t NEONCryptoInsn = Insn32; 1007 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1008 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1009 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1010 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1011 Address, this, STI); 1012 if (Result != MCDisassembler::Fail) { 1013 Size = 4; 1014 return Result; 1015 } 1016 1017 uint32_t NEONv8Insn = Insn32; 1018 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1019 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1020 this, STI); 1021 if (Result != MCDisassembler::Fail) { 1022 Size = 4; 1023 return Result; 1024 } 1025 } 1026 1027 Result = 1028 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1029 if (Result != MCDisassembler::Fail) { 1030 Size = 4; 1031 Check(Result, AddThumbPredicate(MI)); 1032 return Result; 1033 } 1034 1035 Size = 0; 1036 return MCDisassembler::Fail; 1037 } 1038 1039 extern "C" void LLVMInitializeARMDisassembler() { 1040 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1041 createARMDisassembler); 1042 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1043 createARMDisassembler); 1044 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1045 createThumbDisassembler); 1046 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1047 createThumbDisassembler); 1048 } 1049 1050 static const uint16_t GPRDecoderTable[] = { 1051 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1052 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1053 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1054 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1055 }; 1056 1057 static const uint16_t CLRMGPRDecoderTable[] = { 1058 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1059 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1060 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1061 ARM::R12, 0, ARM::LR, ARM::APSR 1062 }; 1063 1064 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1065 uint64_t Address, const void *Decoder) { 1066 if (RegNo > 15) 1067 return MCDisassembler::Fail; 1068 1069 unsigned Register = GPRDecoderTable[RegNo]; 1070 Inst.addOperand(MCOperand::createReg(Register)); 1071 return MCDisassembler::Success; 1072 } 1073 1074 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1075 uint64_t Address, 1076 const void *Decoder) { 1077 if (RegNo > 15) 1078 return MCDisassembler::Fail; 1079 1080 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1081 if (Register == 0) 1082 return MCDisassembler::Fail; 1083 1084 Inst.addOperand(MCOperand::createReg(Register)); 1085 return MCDisassembler::Success; 1086 } 1087 1088 static DecodeStatus 1089 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1090 uint64_t Address, const void *Decoder) { 1091 DecodeStatus S = MCDisassembler::Success; 1092 1093 if (RegNo == 15) 1094 S = MCDisassembler::SoftFail; 1095 1096 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1097 1098 return S; 1099 } 1100 1101 static DecodeStatus 1102 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1103 uint64_t Address, const void *Decoder) { 1104 DecodeStatus S = MCDisassembler::Success; 1105 1106 if (RegNo == 15) 1107 { 1108 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1109 return MCDisassembler::Success; 1110 } 1111 1112 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1113 return S; 1114 } 1115 1116 static DecodeStatus 1117 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1118 uint64_t Address, const void *Decoder) { 1119 DecodeStatus S = MCDisassembler::Success; 1120 1121 if (RegNo == 15) 1122 { 1123 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1124 return MCDisassembler::Success; 1125 } 1126 1127 if (RegNo == 13) 1128 S = MCDisassembler::SoftFail; 1129 1130 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1131 return S; 1132 } 1133 1134 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1135 uint64_t Address, const void *Decoder) { 1136 if (RegNo > 7) 1137 return MCDisassembler::Fail; 1138 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1139 } 1140 1141 static const uint16_t GPRPairDecoderTable[] = { 1142 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1143 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1144 }; 1145 1146 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1147 uint64_t Address, const void *Decoder) { 1148 DecodeStatus S = MCDisassembler::Success; 1149 1150 if (RegNo > 13) 1151 return MCDisassembler::Fail; 1152 1153 if ((RegNo & 1) || RegNo == 0xe) 1154 S = MCDisassembler::SoftFail; 1155 1156 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1157 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1158 return S; 1159 } 1160 1161 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1162 uint64_t Address, const void *Decoder) { 1163 unsigned Register = 0; 1164 switch (RegNo) { 1165 case 0: 1166 Register = ARM::R0; 1167 break; 1168 case 1: 1169 Register = ARM::R1; 1170 break; 1171 case 2: 1172 Register = ARM::R2; 1173 break; 1174 case 3: 1175 Register = ARM::R3; 1176 break; 1177 case 9: 1178 Register = ARM::R9; 1179 break; 1180 case 12: 1181 Register = ARM::R12; 1182 break; 1183 default: 1184 return MCDisassembler::Fail; 1185 } 1186 1187 Inst.addOperand(MCOperand::createReg(Register)); 1188 return MCDisassembler::Success; 1189 } 1190 1191 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1192 uint64_t Address, const void *Decoder) { 1193 DecodeStatus S = MCDisassembler::Success; 1194 1195 const FeatureBitset &featureBits = 1196 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1197 1198 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1199 S = MCDisassembler::SoftFail; 1200 1201 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1202 return S; 1203 } 1204 1205 static const uint16_t SPRDecoderTable[] = { 1206 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1207 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1208 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1209 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1210 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1211 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1212 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1213 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1214 }; 1215 1216 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1217 uint64_t Address, const void *Decoder) { 1218 if (RegNo > 31) 1219 return MCDisassembler::Fail; 1220 1221 unsigned Register = SPRDecoderTable[RegNo]; 1222 Inst.addOperand(MCOperand::createReg(Register)); 1223 return MCDisassembler::Success; 1224 } 1225 1226 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1227 uint64_t Address, const void *Decoder) { 1228 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1229 } 1230 1231 static const uint16_t DPRDecoderTable[] = { 1232 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1233 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1234 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1235 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1236 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1237 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1238 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1239 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1240 }; 1241 1242 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1243 uint64_t Address, const void *Decoder) { 1244 const FeatureBitset &featureBits = 1245 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1246 1247 bool hasD32 = featureBits[ARM::FeatureD32]; 1248 1249 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1250 return MCDisassembler::Fail; 1251 1252 unsigned Register = DPRDecoderTable[RegNo]; 1253 Inst.addOperand(MCOperand::createReg(Register)); 1254 return MCDisassembler::Success; 1255 } 1256 1257 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1258 uint64_t Address, const void *Decoder) { 1259 if (RegNo > 7) 1260 return MCDisassembler::Fail; 1261 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1262 } 1263 1264 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1265 uint64_t Address, const void *Decoder) { 1266 if (RegNo > 15) 1267 return MCDisassembler::Fail; 1268 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1269 } 1270 1271 static DecodeStatus 1272 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1273 uint64_t Address, const void *Decoder) { 1274 if (RegNo > 15) 1275 return MCDisassembler::Fail; 1276 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1277 } 1278 1279 static const uint16_t QPRDecoderTable[] = { 1280 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1281 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1282 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1283 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1284 }; 1285 1286 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1287 uint64_t Address, const void *Decoder) { 1288 if (RegNo > 31 || (RegNo & 1) != 0) 1289 return MCDisassembler::Fail; 1290 RegNo >>= 1; 1291 1292 unsigned Register = QPRDecoderTable[RegNo]; 1293 Inst.addOperand(MCOperand::createReg(Register)); 1294 return MCDisassembler::Success; 1295 } 1296 1297 static const uint16_t DPairDecoderTable[] = { 1298 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1299 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1300 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1301 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1302 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1303 ARM::Q15 1304 }; 1305 1306 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1307 uint64_t Address, const void *Decoder) { 1308 if (RegNo > 30) 1309 return MCDisassembler::Fail; 1310 1311 unsigned Register = DPairDecoderTable[RegNo]; 1312 Inst.addOperand(MCOperand::createReg(Register)); 1313 return MCDisassembler::Success; 1314 } 1315 1316 static const uint16_t DPairSpacedDecoderTable[] = { 1317 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1318 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1319 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1320 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1321 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1322 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1323 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1324 ARM::D28_D30, ARM::D29_D31 1325 }; 1326 1327 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1328 unsigned RegNo, 1329 uint64_t Address, 1330 const void *Decoder) { 1331 if (RegNo > 29) 1332 return MCDisassembler::Fail; 1333 1334 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1335 Inst.addOperand(MCOperand::createReg(Register)); 1336 return MCDisassembler::Success; 1337 } 1338 1339 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1340 uint64_t Address, const void *Decoder) { 1341 DecodeStatus S = MCDisassembler::Success; 1342 if (Val == 0xF) return MCDisassembler::Fail; 1343 // AL predicate is not allowed on Thumb1 branches. 1344 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1345 return MCDisassembler::Fail; 1346 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1347 Check(S, MCDisassembler::SoftFail); 1348 Inst.addOperand(MCOperand::createImm(Val)); 1349 if (Val == ARMCC::AL) { 1350 Inst.addOperand(MCOperand::createReg(0)); 1351 } else 1352 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1353 return S; 1354 } 1355 1356 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1357 uint64_t Address, const void *Decoder) { 1358 if (Val) 1359 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1360 else 1361 Inst.addOperand(MCOperand::createReg(0)); 1362 return MCDisassembler::Success; 1363 } 1364 1365 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1366 uint64_t Address, const void *Decoder) { 1367 DecodeStatus S = MCDisassembler::Success; 1368 1369 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1370 unsigned type = fieldFromInstruction(Val, 5, 2); 1371 unsigned imm = fieldFromInstruction(Val, 7, 5); 1372 1373 // Register-immediate 1374 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1375 return MCDisassembler::Fail; 1376 1377 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1378 switch (type) { 1379 case 0: 1380 Shift = ARM_AM::lsl; 1381 break; 1382 case 1: 1383 Shift = ARM_AM::lsr; 1384 break; 1385 case 2: 1386 Shift = ARM_AM::asr; 1387 break; 1388 case 3: 1389 Shift = ARM_AM::ror; 1390 break; 1391 } 1392 1393 if (Shift == ARM_AM::ror && imm == 0) 1394 Shift = ARM_AM::rrx; 1395 1396 unsigned Op = Shift | (imm << 3); 1397 Inst.addOperand(MCOperand::createImm(Op)); 1398 1399 return S; 1400 } 1401 1402 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1403 uint64_t Address, const void *Decoder) { 1404 DecodeStatus S = MCDisassembler::Success; 1405 1406 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1407 unsigned type = fieldFromInstruction(Val, 5, 2); 1408 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1409 1410 // Register-register 1411 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1412 return MCDisassembler::Fail; 1413 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1414 return MCDisassembler::Fail; 1415 1416 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1417 switch (type) { 1418 case 0: 1419 Shift = ARM_AM::lsl; 1420 break; 1421 case 1: 1422 Shift = ARM_AM::lsr; 1423 break; 1424 case 2: 1425 Shift = ARM_AM::asr; 1426 break; 1427 case 3: 1428 Shift = ARM_AM::ror; 1429 break; 1430 } 1431 1432 Inst.addOperand(MCOperand::createImm(Shift)); 1433 1434 return S; 1435 } 1436 1437 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1438 uint64_t Address, const void *Decoder) { 1439 DecodeStatus S = MCDisassembler::Success; 1440 1441 bool NeedDisjointWriteback = false; 1442 unsigned WritebackReg = 0; 1443 bool CLRM = false; 1444 switch (Inst.getOpcode()) { 1445 default: 1446 break; 1447 case ARM::LDMIA_UPD: 1448 case ARM::LDMDB_UPD: 1449 case ARM::LDMIB_UPD: 1450 case ARM::LDMDA_UPD: 1451 case ARM::t2LDMIA_UPD: 1452 case ARM::t2LDMDB_UPD: 1453 case ARM::t2STMIA_UPD: 1454 case ARM::t2STMDB_UPD: 1455 NeedDisjointWriteback = true; 1456 WritebackReg = Inst.getOperand(0).getReg(); 1457 break; 1458 case ARM::t2CLRM: 1459 CLRM = true; 1460 break; 1461 } 1462 1463 // Empty register lists are not allowed. 1464 if (Val == 0) return MCDisassembler::Fail; 1465 for (unsigned i = 0; i < 16; ++i) { 1466 if (Val & (1 << i)) { 1467 if (CLRM) { 1468 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1469 return MCDisassembler::Fail; 1470 } 1471 } else { 1472 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1473 return MCDisassembler::Fail; 1474 // Writeback not allowed if Rn is in the target list. 1475 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1476 Check(S, MCDisassembler::SoftFail); 1477 } 1478 } 1479 } 1480 1481 return S; 1482 } 1483 1484 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1485 uint64_t Address, const void *Decoder) { 1486 DecodeStatus S = MCDisassembler::Success; 1487 1488 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1489 unsigned regs = fieldFromInstruction(Val, 0, 8); 1490 1491 // In case of unpredictable encoding, tweak the operands. 1492 if (regs == 0 || (Vd + regs) > 32) { 1493 regs = Vd + regs > 32 ? 32 - Vd : regs; 1494 regs = std::max( 1u, regs); 1495 S = MCDisassembler::SoftFail; 1496 } 1497 1498 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1499 return MCDisassembler::Fail; 1500 for (unsigned i = 0; i < (regs - 1); ++i) { 1501 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1502 return MCDisassembler::Fail; 1503 } 1504 1505 return S; 1506 } 1507 1508 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1509 uint64_t Address, const void *Decoder) { 1510 DecodeStatus S = MCDisassembler::Success; 1511 1512 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1513 unsigned regs = fieldFromInstruction(Val, 1, 7); 1514 1515 // In case of unpredictable encoding, tweak the operands. 1516 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1517 regs = Vd + regs > 32 ? 32 - Vd : regs; 1518 regs = std::max( 1u, regs); 1519 regs = std::min(16u, regs); 1520 S = MCDisassembler::SoftFail; 1521 } 1522 1523 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1524 return MCDisassembler::Fail; 1525 for (unsigned i = 0; i < (regs - 1); ++i) { 1526 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1527 return MCDisassembler::Fail; 1528 } 1529 1530 return S; 1531 } 1532 1533 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1534 uint64_t Address, const void *Decoder) { 1535 // This operand encodes a mask of contiguous zeros between a specified MSB 1536 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1537 // the mask of all bits LSB-and-lower, and then xor them to create 1538 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1539 // create the final mask. 1540 unsigned msb = fieldFromInstruction(Val, 5, 5); 1541 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1542 1543 DecodeStatus S = MCDisassembler::Success; 1544 if (lsb > msb) { 1545 Check(S, MCDisassembler::SoftFail); 1546 // The check above will cause the warning for the "potentially undefined 1547 // instruction encoding" but we can't build a bad MCOperand value here 1548 // with a lsb > msb or else printing the MCInst will cause a crash. 1549 lsb = msb; 1550 } 1551 1552 uint32_t msb_mask = 0xFFFFFFFF; 1553 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1554 uint32_t lsb_mask = (1U << lsb) - 1; 1555 1556 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1557 return S; 1558 } 1559 1560 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1561 uint64_t Address, const void *Decoder) { 1562 DecodeStatus S = MCDisassembler::Success; 1563 1564 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1565 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1566 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1567 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1568 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1569 unsigned U = fieldFromInstruction(Insn, 23, 1); 1570 const FeatureBitset &featureBits = 1571 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1572 1573 switch (Inst.getOpcode()) { 1574 case ARM::LDC_OFFSET: 1575 case ARM::LDC_PRE: 1576 case ARM::LDC_POST: 1577 case ARM::LDC_OPTION: 1578 case ARM::LDCL_OFFSET: 1579 case ARM::LDCL_PRE: 1580 case ARM::LDCL_POST: 1581 case ARM::LDCL_OPTION: 1582 case ARM::STC_OFFSET: 1583 case ARM::STC_PRE: 1584 case ARM::STC_POST: 1585 case ARM::STC_OPTION: 1586 case ARM::STCL_OFFSET: 1587 case ARM::STCL_PRE: 1588 case ARM::STCL_POST: 1589 case ARM::STCL_OPTION: 1590 case ARM::t2LDC_OFFSET: 1591 case ARM::t2LDC_PRE: 1592 case ARM::t2LDC_POST: 1593 case ARM::t2LDC_OPTION: 1594 case ARM::t2LDCL_OFFSET: 1595 case ARM::t2LDCL_PRE: 1596 case ARM::t2LDCL_POST: 1597 case ARM::t2LDCL_OPTION: 1598 case ARM::t2STC_OFFSET: 1599 case ARM::t2STC_PRE: 1600 case ARM::t2STC_POST: 1601 case ARM::t2STC_OPTION: 1602 case ARM::t2STCL_OFFSET: 1603 case ARM::t2STCL_PRE: 1604 case ARM::t2STCL_POST: 1605 case ARM::t2STCL_OPTION: 1606 case ARM::t2LDC2_OFFSET: 1607 case ARM::t2LDC2L_OFFSET: 1608 case ARM::t2LDC2_PRE: 1609 case ARM::t2LDC2L_PRE: 1610 case ARM::t2STC2_OFFSET: 1611 case ARM::t2STC2L_OFFSET: 1612 case ARM::t2STC2_PRE: 1613 case ARM::t2STC2L_PRE: 1614 case ARM::LDC2_OFFSET: 1615 case ARM::LDC2L_OFFSET: 1616 case ARM::LDC2_PRE: 1617 case ARM::LDC2L_PRE: 1618 case ARM::STC2_OFFSET: 1619 case ARM::STC2L_OFFSET: 1620 case ARM::STC2_PRE: 1621 case ARM::STC2L_PRE: 1622 case ARM::t2LDC2_OPTION: 1623 case ARM::t2STC2_OPTION: 1624 case ARM::t2LDC2_POST: 1625 case ARM::t2LDC2L_POST: 1626 case ARM::t2STC2_POST: 1627 case ARM::t2STC2L_POST: 1628 case ARM::LDC2_POST: 1629 case ARM::LDC2L_POST: 1630 case ARM::STC2_POST: 1631 case ARM::STC2L_POST: 1632 if (coproc == 0xA || coproc == 0xB || 1633 (featureBits[ARM::HasV8_1MMainlineOps] && 1634 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1635 coproc == 0xE || coproc == 0xF))) 1636 return MCDisassembler::Fail; 1637 break; 1638 default: 1639 break; 1640 } 1641 1642 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1643 return MCDisassembler::Fail; 1644 1645 Inst.addOperand(MCOperand::createImm(coproc)); 1646 Inst.addOperand(MCOperand::createImm(CRd)); 1647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1648 return MCDisassembler::Fail; 1649 1650 switch (Inst.getOpcode()) { 1651 case ARM::t2LDC2_OFFSET: 1652 case ARM::t2LDC2L_OFFSET: 1653 case ARM::t2LDC2_PRE: 1654 case ARM::t2LDC2L_PRE: 1655 case ARM::t2STC2_OFFSET: 1656 case ARM::t2STC2L_OFFSET: 1657 case ARM::t2STC2_PRE: 1658 case ARM::t2STC2L_PRE: 1659 case ARM::LDC2_OFFSET: 1660 case ARM::LDC2L_OFFSET: 1661 case ARM::LDC2_PRE: 1662 case ARM::LDC2L_PRE: 1663 case ARM::STC2_OFFSET: 1664 case ARM::STC2L_OFFSET: 1665 case ARM::STC2_PRE: 1666 case ARM::STC2L_PRE: 1667 case ARM::t2LDC_OFFSET: 1668 case ARM::t2LDCL_OFFSET: 1669 case ARM::t2LDC_PRE: 1670 case ARM::t2LDCL_PRE: 1671 case ARM::t2STC_OFFSET: 1672 case ARM::t2STCL_OFFSET: 1673 case ARM::t2STC_PRE: 1674 case ARM::t2STCL_PRE: 1675 case ARM::LDC_OFFSET: 1676 case ARM::LDCL_OFFSET: 1677 case ARM::LDC_PRE: 1678 case ARM::LDCL_PRE: 1679 case ARM::STC_OFFSET: 1680 case ARM::STCL_OFFSET: 1681 case ARM::STC_PRE: 1682 case ARM::STCL_PRE: 1683 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1684 Inst.addOperand(MCOperand::createImm(imm)); 1685 break; 1686 case ARM::t2LDC2_POST: 1687 case ARM::t2LDC2L_POST: 1688 case ARM::t2STC2_POST: 1689 case ARM::t2STC2L_POST: 1690 case ARM::LDC2_POST: 1691 case ARM::LDC2L_POST: 1692 case ARM::STC2_POST: 1693 case ARM::STC2L_POST: 1694 case ARM::t2LDC_POST: 1695 case ARM::t2LDCL_POST: 1696 case ARM::t2STC_POST: 1697 case ARM::t2STCL_POST: 1698 case ARM::LDC_POST: 1699 case ARM::LDCL_POST: 1700 case ARM::STC_POST: 1701 case ARM::STCL_POST: 1702 imm |= U << 8; 1703 LLVM_FALLTHROUGH; 1704 default: 1705 // The 'option' variant doesn't encode 'U' in the immediate since 1706 // the immediate is unsigned [0,255]. 1707 Inst.addOperand(MCOperand::createImm(imm)); 1708 break; 1709 } 1710 1711 switch (Inst.getOpcode()) { 1712 case ARM::LDC_OFFSET: 1713 case ARM::LDC_PRE: 1714 case ARM::LDC_POST: 1715 case ARM::LDC_OPTION: 1716 case ARM::LDCL_OFFSET: 1717 case ARM::LDCL_PRE: 1718 case ARM::LDCL_POST: 1719 case ARM::LDCL_OPTION: 1720 case ARM::STC_OFFSET: 1721 case ARM::STC_PRE: 1722 case ARM::STC_POST: 1723 case ARM::STC_OPTION: 1724 case ARM::STCL_OFFSET: 1725 case ARM::STCL_PRE: 1726 case ARM::STCL_POST: 1727 case ARM::STCL_OPTION: 1728 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1729 return MCDisassembler::Fail; 1730 break; 1731 default: 1732 break; 1733 } 1734 1735 return S; 1736 } 1737 1738 static DecodeStatus 1739 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1740 uint64_t Address, const void *Decoder) { 1741 DecodeStatus S = MCDisassembler::Success; 1742 1743 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1744 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1745 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1746 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1747 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1748 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1749 unsigned P = fieldFromInstruction(Insn, 24, 1); 1750 unsigned W = fieldFromInstruction(Insn, 21, 1); 1751 1752 // On stores, the writeback operand precedes Rt. 1753 switch (Inst.getOpcode()) { 1754 case ARM::STR_POST_IMM: 1755 case ARM::STR_POST_REG: 1756 case ARM::STRB_POST_IMM: 1757 case ARM::STRB_POST_REG: 1758 case ARM::STRT_POST_REG: 1759 case ARM::STRT_POST_IMM: 1760 case ARM::STRBT_POST_REG: 1761 case ARM::STRBT_POST_IMM: 1762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1763 return MCDisassembler::Fail; 1764 break; 1765 default: 1766 break; 1767 } 1768 1769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1770 return MCDisassembler::Fail; 1771 1772 // On loads, the writeback operand comes after Rt. 1773 switch (Inst.getOpcode()) { 1774 case ARM::LDR_POST_IMM: 1775 case ARM::LDR_POST_REG: 1776 case ARM::LDRB_POST_IMM: 1777 case ARM::LDRB_POST_REG: 1778 case ARM::LDRBT_POST_REG: 1779 case ARM::LDRBT_POST_IMM: 1780 case ARM::LDRT_POST_REG: 1781 case ARM::LDRT_POST_IMM: 1782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1783 return MCDisassembler::Fail; 1784 break; 1785 default: 1786 break; 1787 } 1788 1789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1790 return MCDisassembler::Fail; 1791 1792 ARM_AM::AddrOpc Op = ARM_AM::add; 1793 if (!fieldFromInstruction(Insn, 23, 1)) 1794 Op = ARM_AM::sub; 1795 1796 bool writeback = (P == 0) || (W == 1); 1797 unsigned idx_mode = 0; 1798 if (P && writeback) 1799 idx_mode = ARMII::IndexModePre; 1800 else if (!P && writeback) 1801 idx_mode = ARMII::IndexModePost; 1802 1803 if (writeback && (Rn == 15 || Rn == Rt)) 1804 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1805 1806 if (reg) { 1807 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1808 return MCDisassembler::Fail; 1809 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1810 switch( fieldFromInstruction(Insn, 5, 2)) { 1811 case 0: 1812 Opc = ARM_AM::lsl; 1813 break; 1814 case 1: 1815 Opc = ARM_AM::lsr; 1816 break; 1817 case 2: 1818 Opc = ARM_AM::asr; 1819 break; 1820 case 3: 1821 Opc = ARM_AM::ror; 1822 break; 1823 default: 1824 return MCDisassembler::Fail; 1825 } 1826 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1827 if (Opc == ARM_AM::ror && amt == 0) 1828 Opc = ARM_AM::rrx; 1829 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1830 1831 Inst.addOperand(MCOperand::createImm(imm)); 1832 } else { 1833 Inst.addOperand(MCOperand::createReg(0)); 1834 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1835 Inst.addOperand(MCOperand::createImm(tmp)); 1836 } 1837 1838 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1839 return MCDisassembler::Fail; 1840 1841 return S; 1842 } 1843 1844 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1845 uint64_t Address, const void *Decoder) { 1846 DecodeStatus S = MCDisassembler::Success; 1847 1848 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1849 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1850 unsigned type = fieldFromInstruction(Val, 5, 2); 1851 unsigned imm = fieldFromInstruction(Val, 7, 5); 1852 unsigned U = fieldFromInstruction(Val, 12, 1); 1853 1854 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1855 switch (type) { 1856 case 0: 1857 ShOp = ARM_AM::lsl; 1858 break; 1859 case 1: 1860 ShOp = ARM_AM::lsr; 1861 break; 1862 case 2: 1863 ShOp = ARM_AM::asr; 1864 break; 1865 case 3: 1866 ShOp = ARM_AM::ror; 1867 break; 1868 } 1869 1870 if (ShOp == ARM_AM::ror && imm == 0) 1871 ShOp = ARM_AM::rrx; 1872 1873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1874 return MCDisassembler::Fail; 1875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1876 return MCDisassembler::Fail; 1877 unsigned shift; 1878 if (U) 1879 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1880 else 1881 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1882 Inst.addOperand(MCOperand::createImm(shift)); 1883 1884 return S; 1885 } 1886 1887 static DecodeStatus 1888 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1889 uint64_t Address, const void *Decoder) { 1890 DecodeStatus S = MCDisassembler::Success; 1891 1892 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1893 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1894 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1895 unsigned type = fieldFromInstruction(Insn, 22, 1); 1896 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1897 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1898 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1899 unsigned W = fieldFromInstruction(Insn, 21, 1); 1900 unsigned P = fieldFromInstruction(Insn, 24, 1); 1901 unsigned Rt2 = Rt + 1; 1902 1903 bool writeback = (W == 1) | (P == 0); 1904 1905 // For {LD,ST}RD, Rt must be even, else undefined. 1906 switch (Inst.getOpcode()) { 1907 case ARM::STRD: 1908 case ARM::STRD_PRE: 1909 case ARM::STRD_POST: 1910 case ARM::LDRD: 1911 case ARM::LDRD_PRE: 1912 case ARM::LDRD_POST: 1913 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1914 break; 1915 default: 1916 break; 1917 } 1918 switch (Inst.getOpcode()) { 1919 case ARM::STRD: 1920 case ARM::STRD_PRE: 1921 case ARM::STRD_POST: 1922 if (P == 0 && W == 1) 1923 S = MCDisassembler::SoftFail; 1924 1925 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1926 S = MCDisassembler::SoftFail; 1927 if (type && Rm == 15) 1928 S = MCDisassembler::SoftFail; 1929 if (Rt2 == 15) 1930 S = MCDisassembler::SoftFail; 1931 if (!type && fieldFromInstruction(Insn, 8, 4)) 1932 S = MCDisassembler::SoftFail; 1933 break; 1934 case ARM::STRH: 1935 case ARM::STRH_PRE: 1936 case ARM::STRH_POST: 1937 if (Rt == 15) 1938 S = MCDisassembler::SoftFail; 1939 if (writeback && (Rn == 15 || Rn == Rt)) 1940 S = MCDisassembler::SoftFail; 1941 if (!type && Rm == 15) 1942 S = MCDisassembler::SoftFail; 1943 break; 1944 case ARM::LDRD: 1945 case ARM::LDRD_PRE: 1946 case ARM::LDRD_POST: 1947 if (type && Rn == 15) { 1948 if (Rt2 == 15) 1949 S = MCDisassembler::SoftFail; 1950 break; 1951 } 1952 if (P == 0 && W == 1) 1953 S = MCDisassembler::SoftFail; 1954 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1955 S = MCDisassembler::SoftFail; 1956 if (!type && writeback && Rn == 15) 1957 S = MCDisassembler::SoftFail; 1958 if (writeback && (Rn == Rt || Rn == Rt2)) 1959 S = MCDisassembler::SoftFail; 1960 break; 1961 case ARM::LDRH: 1962 case ARM::LDRH_PRE: 1963 case ARM::LDRH_POST: 1964 if (type && Rn == 15) { 1965 if (Rt == 15) 1966 S = MCDisassembler::SoftFail; 1967 break; 1968 } 1969 if (Rt == 15) 1970 S = MCDisassembler::SoftFail; 1971 if (!type && Rm == 15) 1972 S = MCDisassembler::SoftFail; 1973 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1974 S = MCDisassembler::SoftFail; 1975 break; 1976 case ARM::LDRSH: 1977 case ARM::LDRSH_PRE: 1978 case ARM::LDRSH_POST: 1979 case ARM::LDRSB: 1980 case ARM::LDRSB_PRE: 1981 case ARM::LDRSB_POST: 1982 if (type && Rn == 15) { 1983 if (Rt == 15) 1984 S = MCDisassembler::SoftFail; 1985 break; 1986 } 1987 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1988 S = MCDisassembler::SoftFail; 1989 if (!type && (Rt == 15 || Rm == 15)) 1990 S = MCDisassembler::SoftFail; 1991 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1992 S = MCDisassembler::SoftFail; 1993 break; 1994 default: 1995 break; 1996 } 1997 1998 if (writeback) { // Writeback 1999 if (P) 2000 U |= ARMII::IndexModePre << 9; 2001 else 2002 U |= ARMII::IndexModePost << 9; 2003 2004 // On stores, the writeback operand precedes Rt. 2005 switch (Inst.getOpcode()) { 2006 case ARM::STRD: 2007 case ARM::STRD_PRE: 2008 case ARM::STRD_POST: 2009 case ARM::STRH: 2010 case ARM::STRH_PRE: 2011 case ARM::STRH_POST: 2012 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2013 return MCDisassembler::Fail; 2014 break; 2015 default: 2016 break; 2017 } 2018 } 2019 2020 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2021 return MCDisassembler::Fail; 2022 switch (Inst.getOpcode()) { 2023 case ARM::STRD: 2024 case ARM::STRD_PRE: 2025 case ARM::STRD_POST: 2026 case ARM::LDRD: 2027 case ARM::LDRD_PRE: 2028 case ARM::LDRD_POST: 2029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2030 return MCDisassembler::Fail; 2031 break; 2032 default: 2033 break; 2034 } 2035 2036 if (writeback) { 2037 // On loads, the writeback operand comes after Rt. 2038 switch (Inst.getOpcode()) { 2039 case ARM::LDRD: 2040 case ARM::LDRD_PRE: 2041 case ARM::LDRD_POST: 2042 case ARM::LDRH: 2043 case ARM::LDRH_PRE: 2044 case ARM::LDRH_POST: 2045 case ARM::LDRSH: 2046 case ARM::LDRSH_PRE: 2047 case ARM::LDRSH_POST: 2048 case ARM::LDRSB: 2049 case ARM::LDRSB_PRE: 2050 case ARM::LDRSB_POST: 2051 case ARM::LDRHTr: 2052 case ARM::LDRSBTr: 2053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2054 return MCDisassembler::Fail; 2055 break; 2056 default: 2057 break; 2058 } 2059 } 2060 2061 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2062 return MCDisassembler::Fail; 2063 2064 if (type) { 2065 Inst.addOperand(MCOperand::createReg(0)); 2066 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2067 } else { 2068 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2069 return MCDisassembler::Fail; 2070 Inst.addOperand(MCOperand::createImm(U)); 2071 } 2072 2073 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2074 return MCDisassembler::Fail; 2075 2076 return S; 2077 } 2078 2079 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2080 uint64_t Address, const void *Decoder) { 2081 DecodeStatus S = MCDisassembler::Success; 2082 2083 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2084 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2085 2086 switch (mode) { 2087 case 0: 2088 mode = ARM_AM::da; 2089 break; 2090 case 1: 2091 mode = ARM_AM::ia; 2092 break; 2093 case 2: 2094 mode = ARM_AM::db; 2095 break; 2096 case 3: 2097 mode = ARM_AM::ib; 2098 break; 2099 } 2100 2101 Inst.addOperand(MCOperand::createImm(mode)); 2102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2103 return MCDisassembler::Fail; 2104 2105 return S; 2106 } 2107 2108 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2109 uint64_t Address, const void *Decoder) { 2110 DecodeStatus S = MCDisassembler::Success; 2111 2112 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2113 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2114 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2115 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2116 2117 if (pred == 0xF) 2118 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2119 2120 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2121 return MCDisassembler::Fail; 2122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2123 return MCDisassembler::Fail; 2124 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2125 return MCDisassembler::Fail; 2126 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2127 return MCDisassembler::Fail; 2128 return S; 2129 } 2130 2131 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2132 unsigned Insn, 2133 uint64_t Address, const void *Decoder) { 2134 DecodeStatus S = MCDisassembler::Success; 2135 2136 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2137 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2138 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2139 2140 if (pred == 0xF) { 2141 // Ambiguous with RFE and SRS 2142 switch (Inst.getOpcode()) { 2143 case ARM::LDMDA: 2144 Inst.setOpcode(ARM::RFEDA); 2145 break; 2146 case ARM::LDMDA_UPD: 2147 Inst.setOpcode(ARM::RFEDA_UPD); 2148 break; 2149 case ARM::LDMDB: 2150 Inst.setOpcode(ARM::RFEDB); 2151 break; 2152 case ARM::LDMDB_UPD: 2153 Inst.setOpcode(ARM::RFEDB_UPD); 2154 break; 2155 case ARM::LDMIA: 2156 Inst.setOpcode(ARM::RFEIA); 2157 break; 2158 case ARM::LDMIA_UPD: 2159 Inst.setOpcode(ARM::RFEIA_UPD); 2160 break; 2161 case ARM::LDMIB: 2162 Inst.setOpcode(ARM::RFEIB); 2163 break; 2164 case ARM::LDMIB_UPD: 2165 Inst.setOpcode(ARM::RFEIB_UPD); 2166 break; 2167 case ARM::STMDA: 2168 Inst.setOpcode(ARM::SRSDA); 2169 break; 2170 case ARM::STMDA_UPD: 2171 Inst.setOpcode(ARM::SRSDA_UPD); 2172 break; 2173 case ARM::STMDB: 2174 Inst.setOpcode(ARM::SRSDB); 2175 break; 2176 case ARM::STMDB_UPD: 2177 Inst.setOpcode(ARM::SRSDB_UPD); 2178 break; 2179 case ARM::STMIA: 2180 Inst.setOpcode(ARM::SRSIA); 2181 break; 2182 case ARM::STMIA_UPD: 2183 Inst.setOpcode(ARM::SRSIA_UPD); 2184 break; 2185 case ARM::STMIB: 2186 Inst.setOpcode(ARM::SRSIB); 2187 break; 2188 case ARM::STMIB_UPD: 2189 Inst.setOpcode(ARM::SRSIB_UPD); 2190 break; 2191 default: 2192 return MCDisassembler::Fail; 2193 } 2194 2195 // For stores (which become SRS's, the only operand is the mode. 2196 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2197 // Check SRS encoding constraints 2198 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2199 fieldFromInstruction(Insn, 20, 1) == 0)) 2200 return MCDisassembler::Fail; 2201 2202 Inst.addOperand( 2203 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2204 return S; 2205 } 2206 2207 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2208 } 2209 2210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2211 return MCDisassembler::Fail; 2212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2213 return MCDisassembler::Fail; // Tied 2214 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2215 return MCDisassembler::Fail; 2216 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2217 return MCDisassembler::Fail; 2218 2219 return S; 2220 } 2221 2222 // Check for UNPREDICTABLE predicated ESB instruction 2223 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2224 uint64_t Address, const void *Decoder) { 2225 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2226 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2227 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2228 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2229 2230 DecodeStatus S = MCDisassembler::Success; 2231 2232 Inst.addOperand(MCOperand::createImm(imm8)); 2233 2234 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2235 return MCDisassembler::Fail; 2236 2237 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2238 // so all predicates should be allowed. 2239 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2240 S = MCDisassembler::SoftFail; 2241 2242 return S; 2243 } 2244 2245 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2246 uint64_t Address, const void *Decoder) { 2247 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2248 unsigned M = fieldFromInstruction(Insn, 17, 1); 2249 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2250 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2251 2252 DecodeStatus S = MCDisassembler::Success; 2253 2254 // This decoder is called from multiple location that do not check 2255 // the full encoding is valid before they do. 2256 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2257 fieldFromInstruction(Insn, 16, 1) != 0 || 2258 fieldFromInstruction(Insn, 20, 8) != 0x10) 2259 return MCDisassembler::Fail; 2260 2261 // imod == '01' --> UNPREDICTABLE 2262 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2263 // return failure here. The '01' imod value is unprintable, so there's 2264 // nothing useful we could do even if we returned UNPREDICTABLE. 2265 2266 if (imod == 1) return MCDisassembler::Fail; 2267 2268 if (imod && M) { 2269 Inst.setOpcode(ARM::CPS3p); 2270 Inst.addOperand(MCOperand::createImm(imod)); 2271 Inst.addOperand(MCOperand::createImm(iflags)); 2272 Inst.addOperand(MCOperand::createImm(mode)); 2273 } else if (imod && !M) { 2274 Inst.setOpcode(ARM::CPS2p); 2275 Inst.addOperand(MCOperand::createImm(imod)); 2276 Inst.addOperand(MCOperand::createImm(iflags)); 2277 if (mode) S = MCDisassembler::SoftFail; 2278 } else if (!imod && M) { 2279 Inst.setOpcode(ARM::CPS1p); 2280 Inst.addOperand(MCOperand::createImm(mode)); 2281 if (iflags) S = MCDisassembler::SoftFail; 2282 } else { 2283 // imod == '00' && M == '0' --> UNPREDICTABLE 2284 Inst.setOpcode(ARM::CPS1p); 2285 Inst.addOperand(MCOperand::createImm(mode)); 2286 S = MCDisassembler::SoftFail; 2287 } 2288 2289 return S; 2290 } 2291 2292 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2293 uint64_t Address, const void *Decoder) { 2294 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2295 unsigned M = fieldFromInstruction(Insn, 8, 1); 2296 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2297 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2298 2299 DecodeStatus S = MCDisassembler::Success; 2300 2301 // imod == '01' --> UNPREDICTABLE 2302 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2303 // return failure here. The '01' imod value is unprintable, so there's 2304 // nothing useful we could do even if we returned UNPREDICTABLE. 2305 2306 if (imod == 1) return MCDisassembler::Fail; 2307 2308 if (imod && M) { 2309 Inst.setOpcode(ARM::t2CPS3p); 2310 Inst.addOperand(MCOperand::createImm(imod)); 2311 Inst.addOperand(MCOperand::createImm(iflags)); 2312 Inst.addOperand(MCOperand::createImm(mode)); 2313 } else if (imod && !M) { 2314 Inst.setOpcode(ARM::t2CPS2p); 2315 Inst.addOperand(MCOperand::createImm(imod)); 2316 Inst.addOperand(MCOperand::createImm(iflags)); 2317 if (mode) S = MCDisassembler::SoftFail; 2318 } else if (!imod && M) { 2319 Inst.setOpcode(ARM::t2CPS1p); 2320 Inst.addOperand(MCOperand::createImm(mode)); 2321 if (iflags) S = MCDisassembler::SoftFail; 2322 } else { 2323 // imod == '00' && M == '0' --> this is a HINT instruction 2324 int imm = fieldFromInstruction(Insn, 0, 8); 2325 // HINT are defined only for immediate in [0..4] 2326 if(imm > 4) return MCDisassembler::Fail; 2327 Inst.setOpcode(ARM::t2HINT); 2328 Inst.addOperand(MCOperand::createImm(imm)); 2329 } 2330 2331 return S; 2332 } 2333 2334 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2335 uint64_t Address, const void *Decoder) { 2336 DecodeStatus S = MCDisassembler::Success; 2337 2338 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2339 unsigned imm = 0; 2340 2341 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2342 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2343 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2344 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2345 2346 if (Inst.getOpcode() == ARM::t2MOVTi16) 2347 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2348 return MCDisassembler::Fail; 2349 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2350 return MCDisassembler::Fail; 2351 2352 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2353 Inst.addOperand(MCOperand::createImm(imm)); 2354 2355 return S; 2356 } 2357 2358 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2359 uint64_t Address, const void *Decoder) { 2360 DecodeStatus S = MCDisassembler::Success; 2361 2362 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2363 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2364 unsigned imm = 0; 2365 2366 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2367 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2368 2369 if (Inst.getOpcode() == ARM::MOVTi16) 2370 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2371 return MCDisassembler::Fail; 2372 2373 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2374 return MCDisassembler::Fail; 2375 2376 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2377 Inst.addOperand(MCOperand::createImm(imm)); 2378 2379 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2380 return MCDisassembler::Fail; 2381 2382 return S; 2383 } 2384 2385 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2386 uint64_t Address, const void *Decoder) { 2387 DecodeStatus S = MCDisassembler::Success; 2388 2389 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2390 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2391 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2392 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2393 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2394 2395 if (pred == 0xF) 2396 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2397 2398 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2399 return MCDisassembler::Fail; 2400 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2401 return MCDisassembler::Fail; 2402 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2403 return MCDisassembler::Fail; 2404 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2405 return MCDisassembler::Fail; 2406 2407 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2408 return MCDisassembler::Fail; 2409 2410 return S; 2411 } 2412 2413 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2414 uint64_t Address, const void *Decoder) { 2415 DecodeStatus S = MCDisassembler::Success; 2416 2417 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2418 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2419 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2420 2421 if (Pred == 0xF) 2422 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2423 2424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2425 return MCDisassembler::Fail; 2426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2427 return MCDisassembler::Fail; 2428 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2429 return MCDisassembler::Fail; 2430 2431 return S; 2432 } 2433 2434 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2435 uint64_t Address, const void *Decoder) { 2436 DecodeStatus S = MCDisassembler::Success; 2437 2438 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2439 2440 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2441 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2442 2443 if (!FeatureBits[ARM::HasV8_1aOps] || 2444 !FeatureBits[ARM::HasV8Ops]) 2445 return MCDisassembler::Fail; 2446 2447 // Decoder can be called from DecodeTST, which does not check the full 2448 // encoding is valid. 2449 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2450 fieldFromInstruction(Insn, 4,4) != 0) 2451 return MCDisassembler::Fail; 2452 if (fieldFromInstruction(Insn, 10,10) != 0 || 2453 fieldFromInstruction(Insn, 0,4) != 0) 2454 S = MCDisassembler::SoftFail; 2455 2456 Inst.setOpcode(ARM::SETPAN); 2457 Inst.addOperand(MCOperand::createImm(Imm)); 2458 2459 return S; 2460 } 2461 2462 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2463 uint64_t Address, const void *Decoder) { 2464 DecodeStatus S = MCDisassembler::Success; 2465 2466 unsigned add = fieldFromInstruction(Val, 12, 1); 2467 unsigned imm = fieldFromInstruction(Val, 0, 12); 2468 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2469 2470 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2471 return MCDisassembler::Fail; 2472 2473 if (!add) imm *= -1; 2474 if (imm == 0 && !add) imm = INT32_MIN; 2475 Inst.addOperand(MCOperand::createImm(imm)); 2476 if (Rn == 15) 2477 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2478 2479 return S; 2480 } 2481 2482 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2483 uint64_t Address, const void *Decoder) { 2484 DecodeStatus S = MCDisassembler::Success; 2485 2486 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2487 // U == 1 to add imm, 0 to subtract it. 2488 unsigned U = fieldFromInstruction(Val, 8, 1); 2489 unsigned imm = fieldFromInstruction(Val, 0, 8); 2490 2491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2492 return MCDisassembler::Fail; 2493 2494 if (U) 2495 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2496 else 2497 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2498 2499 return S; 2500 } 2501 2502 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2503 uint64_t Address, const void *Decoder) { 2504 DecodeStatus S = MCDisassembler::Success; 2505 2506 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2507 // U == 1 to add imm, 0 to subtract it. 2508 unsigned U = fieldFromInstruction(Val, 8, 1); 2509 unsigned imm = fieldFromInstruction(Val, 0, 8); 2510 2511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2512 return MCDisassembler::Fail; 2513 2514 if (U) 2515 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2516 else 2517 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2518 2519 return S; 2520 } 2521 2522 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2523 uint64_t Address, const void *Decoder) { 2524 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2525 } 2526 2527 static DecodeStatus 2528 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2529 uint64_t Address, const void *Decoder) { 2530 DecodeStatus Status = MCDisassembler::Success; 2531 2532 // Note the J1 and J2 values are from the encoded instruction. So here 2533 // change them to I1 and I2 values via as documented: 2534 // I1 = NOT(J1 EOR S); 2535 // I2 = NOT(J2 EOR S); 2536 // and build the imm32 with one trailing zero as documented: 2537 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2538 unsigned S = fieldFromInstruction(Insn, 26, 1); 2539 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2540 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2541 unsigned I1 = !(J1 ^ S); 2542 unsigned I2 = !(J2 ^ S); 2543 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2544 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2545 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2546 int imm32 = SignExtend32<25>(tmp << 1); 2547 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2548 true, 4, Inst, Decoder)) 2549 Inst.addOperand(MCOperand::createImm(imm32)); 2550 2551 return Status; 2552 } 2553 2554 static DecodeStatus 2555 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2556 uint64_t Address, const void *Decoder) { 2557 DecodeStatus S = MCDisassembler::Success; 2558 2559 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2560 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2561 2562 if (pred == 0xF) { 2563 Inst.setOpcode(ARM::BLXi); 2564 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2565 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2566 true, 4, Inst, Decoder)) 2567 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2568 return S; 2569 } 2570 2571 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2572 true, 4, Inst, Decoder)) 2573 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2574 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2575 return MCDisassembler::Fail; 2576 2577 return S; 2578 } 2579 2580 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2581 uint64_t Address, const void *Decoder) { 2582 DecodeStatus S = MCDisassembler::Success; 2583 2584 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2585 unsigned align = fieldFromInstruction(Val, 4, 2); 2586 2587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2588 return MCDisassembler::Fail; 2589 if (!align) 2590 Inst.addOperand(MCOperand::createImm(0)); 2591 else 2592 Inst.addOperand(MCOperand::createImm(4 << align)); 2593 2594 return S; 2595 } 2596 2597 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2598 uint64_t Address, const void *Decoder) { 2599 DecodeStatus S = MCDisassembler::Success; 2600 2601 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2602 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2603 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2604 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2605 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2606 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2607 2608 // First output register 2609 switch (Inst.getOpcode()) { 2610 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2611 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2612 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2613 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2614 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2615 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2616 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2617 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2618 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2619 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2620 return MCDisassembler::Fail; 2621 break; 2622 case ARM::VLD2b16: 2623 case ARM::VLD2b32: 2624 case ARM::VLD2b8: 2625 case ARM::VLD2b16wb_fixed: 2626 case ARM::VLD2b16wb_register: 2627 case ARM::VLD2b32wb_fixed: 2628 case ARM::VLD2b32wb_register: 2629 case ARM::VLD2b8wb_fixed: 2630 case ARM::VLD2b8wb_register: 2631 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2632 return MCDisassembler::Fail; 2633 break; 2634 default: 2635 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2636 return MCDisassembler::Fail; 2637 } 2638 2639 // Second output register 2640 switch (Inst.getOpcode()) { 2641 case ARM::VLD3d8: 2642 case ARM::VLD3d16: 2643 case ARM::VLD3d32: 2644 case ARM::VLD3d8_UPD: 2645 case ARM::VLD3d16_UPD: 2646 case ARM::VLD3d32_UPD: 2647 case ARM::VLD4d8: 2648 case ARM::VLD4d16: 2649 case ARM::VLD4d32: 2650 case ARM::VLD4d8_UPD: 2651 case ARM::VLD4d16_UPD: 2652 case ARM::VLD4d32_UPD: 2653 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2654 return MCDisassembler::Fail; 2655 break; 2656 case ARM::VLD3q8: 2657 case ARM::VLD3q16: 2658 case ARM::VLD3q32: 2659 case ARM::VLD3q8_UPD: 2660 case ARM::VLD3q16_UPD: 2661 case ARM::VLD3q32_UPD: 2662 case ARM::VLD4q8: 2663 case ARM::VLD4q16: 2664 case ARM::VLD4q32: 2665 case ARM::VLD4q8_UPD: 2666 case ARM::VLD4q16_UPD: 2667 case ARM::VLD4q32_UPD: 2668 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2669 return MCDisassembler::Fail; 2670 break; 2671 default: 2672 break; 2673 } 2674 2675 // Third output register 2676 switch(Inst.getOpcode()) { 2677 case ARM::VLD3d8: 2678 case ARM::VLD3d16: 2679 case ARM::VLD3d32: 2680 case ARM::VLD3d8_UPD: 2681 case ARM::VLD3d16_UPD: 2682 case ARM::VLD3d32_UPD: 2683 case ARM::VLD4d8: 2684 case ARM::VLD4d16: 2685 case ARM::VLD4d32: 2686 case ARM::VLD4d8_UPD: 2687 case ARM::VLD4d16_UPD: 2688 case ARM::VLD4d32_UPD: 2689 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2690 return MCDisassembler::Fail; 2691 break; 2692 case ARM::VLD3q8: 2693 case ARM::VLD3q16: 2694 case ARM::VLD3q32: 2695 case ARM::VLD3q8_UPD: 2696 case ARM::VLD3q16_UPD: 2697 case ARM::VLD3q32_UPD: 2698 case ARM::VLD4q8: 2699 case ARM::VLD4q16: 2700 case ARM::VLD4q32: 2701 case ARM::VLD4q8_UPD: 2702 case ARM::VLD4q16_UPD: 2703 case ARM::VLD4q32_UPD: 2704 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2705 return MCDisassembler::Fail; 2706 break; 2707 default: 2708 break; 2709 } 2710 2711 // Fourth output register 2712 switch (Inst.getOpcode()) { 2713 case ARM::VLD4d8: 2714 case ARM::VLD4d16: 2715 case ARM::VLD4d32: 2716 case ARM::VLD4d8_UPD: 2717 case ARM::VLD4d16_UPD: 2718 case ARM::VLD4d32_UPD: 2719 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2720 return MCDisassembler::Fail; 2721 break; 2722 case ARM::VLD4q8: 2723 case ARM::VLD4q16: 2724 case ARM::VLD4q32: 2725 case ARM::VLD4q8_UPD: 2726 case ARM::VLD4q16_UPD: 2727 case ARM::VLD4q32_UPD: 2728 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2729 return MCDisassembler::Fail; 2730 break; 2731 default: 2732 break; 2733 } 2734 2735 // Writeback operand 2736 switch (Inst.getOpcode()) { 2737 case ARM::VLD1d8wb_fixed: 2738 case ARM::VLD1d16wb_fixed: 2739 case ARM::VLD1d32wb_fixed: 2740 case ARM::VLD1d64wb_fixed: 2741 case ARM::VLD1d8wb_register: 2742 case ARM::VLD1d16wb_register: 2743 case ARM::VLD1d32wb_register: 2744 case ARM::VLD1d64wb_register: 2745 case ARM::VLD1q8wb_fixed: 2746 case ARM::VLD1q16wb_fixed: 2747 case ARM::VLD1q32wb_fixed: 2748 case ARM::VLD1q64wb_fixed: 2749 case ARM::VLD1q8wb_register: 2750 case ARM::VLD1q16wb_register: 2751 case ARM::VLD1q32wb_register: 2752 case ARM::VLD1q64wb_register: 2753 case ARM::VLD1d8Twb_fixed: 2754 case ARM::VLD1d8Twb_register: 2755 case ARM::VLD1d16Twb_fixed: 2756 case ARM::VLD1d16Twb_register: 2757 case ARM::VLD1d32Twb_fixed: 2758 case ARM::VLD1d32Twb_register: 2759 case ARM::VLD1d64Twb_fixed: 2760 case ARM::VLD1d64Twb_register: 2761 case ARM::VLD1d8Qwb_fixed: 2762 case ARM::VLD1d8Qwb_register: 2763 case ARM::VLD1d16Qwb_fixed: 2764 case ARM::VLD1d16Qwb_register: 2765 case ARM::VLD1d32Qwb_fixed: 2766 case ARM::VLD1d32Qwb_register: 2767 case ARM::VLD1d64Qwb_fixed: 2768 case ARM::VLD1d64Qwb_register: 2769 case ARM::VLD2d8wb_fixed: 2770 case ARM::VLD2d16wb_fixed: 2771 case ARM::VLD2d32wb_fixed: 2772 case ARM::VLD2q8wb_fixed: 2773 case ARM::VLD2q16wb_fixed: 2774 case ARM::VLD2q32wb_fixed: 2775 case ARM::VLD2d8wb_register: 2776 case ARM::VLD2d16wb_register: 2777 case ARM::VLD2d32wb_register: 2778 case ARM::VLD2q8wb_register: 2779 case ARM::VLD2q16wb_register: 2780 case ARM::VLD2q32wb_register: 2781 case ARM::VLD2b8wb_fixed: 2782 case ARM::VLD2b16wb_fixed: 2783 case ARM::VLD2b32wb_fixed: 2784 case ARM::VLD2b8wb_register: 2785 case ARM::VLD2b16wb_register: 2786 case ARM::VLD2b32wb_register: 2787 Inst.addOperand(MCOperand::createImm(0)); 2788 break; 2789 case ARM::VLD3d8_UPD: 2790 case ARM::VLD3d16_UPD: 2791 case ARM::VLD3d32_UPD: 2792 case ARM::VLD3q8_UPD: 2793 case ARM::VLD3q16_UPD: 2794 case ARM::VLD3q32_UPD: 2795 case ARM::VLD4d8_UPD: 2796 case ARM::VLD4d16_UPD: 2797 case ARM::VLD4d32_UPD: 2798 case ARM::VLD4q8_UPD: 2799 case ARM::VLD4q16_UPD: 2800 case ARM::VLD4q32_UPD: 2801 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2802 return MCDisassembler::Fail; 2803 break; 2804 default: 2805 break; 2806 } 2807 2808 // AddrMode6 Base (register+alignment) 2809 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2810 return MCDisassembler::Fail; 2811 2812 // AddrMode6 Offset (register) 2813 switch (Inst.getOpcode()) { 2814 default: 2815 // The below have been updated to have explicit am6offset split 2816 // between fixed and register offset. For those instructions not 2817 // yet updated, we need to add an additional reg0 operand for the 2818 // fixed variant. 2819 // 2820 // The fixed offset encodes as Rm == 0xd, so we check for that. 2821 if (Rm == 0xd) { 2822 Inst.addOperand(MCOperand::createReg(0)); 2823 break; 2824 } 2825 // Fall through to handle the register offset variant. 2826 LLVM_FALLTHROUGH; 2827 case ARM::VLD1d8wb_fixed: 2828 case ARM::VLD1d16wb_fixed: 2829 case ARM::VLD1d32wb_fixed: 2830 case ARM::VLD1d64wb_fixed: 2831 case ARM::VLD1d8Twb_fixed: 2832 case ARM::VLD1d16Twb_fixed: 2833 case ARM::VLD1d32Twb_fixed: 2834 case ARM::VLD1d64Twb_fixed: 2835 case ARM::VLD1d8Qwb_fixed: 2836 case ARM::VLD1d16Qwb_fixed: 2837 case ARM::VLD1d32Qwb_fixed: 2838 case ARM::VLD1d64Qwb_fixed: 2839 case ARM::VLD1d8wb_register: 2840 case ARM::VLD1d16wb_register: 2841 case ARM::VLD1d32wb_register: 2842 case ARM::VLD1d64wb_register: 2843 case ARM::VLD1q8wb_fixed: 2844 case ARM::VLD1q16wb_fixed: 2845 case ARM::VLD1q32wb_fixed: 2846 case ARM::VLD1q64wb_fixed: 2847 case ARM::VLD1q8wb_register: 2848 case ARM::VLD1q16wb_register: 2849 case ARM::VLD1q32wb_register: 2850 case ARM::VLD1q64wb_register: 2851 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2852 // variant encodes Rm == 0xf. Anything else is a register offset post- 2853 // increment and we need to add the register operand to the instruction. 2854 if (Rm != 0xD && Rm != 0xF && 2855 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2856 return MCDisassembler::Fail; 2857 break; 2858 case ARM::VLD2d8wb_fixed: 2859 case ARM::VLD2d16wb_fixed: 2860 case ARM::VLD2d32wb_fixed: 2861 case ARM::VLD2b8wb_fixed: 2862 case ARM::VLD2b16wb_fixed: 2863 case ARM::VLD2b32wb_fixed: 2864 case ARM::VLD2q8wb_fixed: 2865 case ARM::VLD2q16wb_fixed: 2866 case ARM::VLD2q32wb_fixed: 2867 break; 2868 } 2869 2870 return S; 2871 } 2872 2873 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2874 uint64_t Address, const void *Decoder) { 2875 unsigned type = fieldFromInstruction(Insn, 8, 4); 2876 unsigned align = fieldFromInstruction(Insn, 4, 2); 2877 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2878 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2879 if (type == 10 && align == 3) return MCDisassembler::Fail; 2880 2881 unsigned load = fieldFromInstruction(Insn, 21, 1); 2882 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2883 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2884 } 2885 2886 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2887 uint64_t Address, const void *Decoder) { 2888 unsigned size = fieldFromInstruction(Insn, 6, 2); 2889 if (size == 3) return MCDisassembler::Fail; 2890 2891 unsigned type = fieldFromInstruction(Insn, 8, 4); 2892 unsigned align = fieldFromInstruction(Insn, 4, 2); 2893 if (type == 8 && align == 3) return MCDisassembler::Fail; 2894 if (type == 9 && align == 3) return MCDisassembler::Fail; 2895 2896 unsigned load = fieldFromInstruction(Insn, 21, 1); 2897 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2898 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2899 } 2900 2901 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2902 uint64_t Address, const void *Decoder) { 2903 unsigned size = fieldFromInstruction(Insn, 6, 2); 2904 if (size == 3) return MCDisassembler::Fail; 2905 2906 unsigned align = fieldFromInstruction(Insn, 4, 2); 2907 if (align & 2) return MCDisassembler::Fail; 2908 2909 unsigned load = fieldFromInstruction(Insn, 21, 1); 2910 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2911 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2912 } 2913 2914 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2915 uint64_t Address, const void *Decoder) { 2916 unsigned size = fieldFromInstruction(Insn, 6, 2); 2917 if (size == 3) return MCDisassembler::Fail; 2918 2919 unsigned load = fieldFromInstruction(Insn, 21, 1); 2920 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2921 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2922 } 2923 2924 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2925 uint64_t Address, const void *Decoder) { 2926 DecodeStatus S = MCDisassembler::Success; 2927 2928 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2929 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2930 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2931 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2932 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2933 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2934 2935 // Writeback Operand 2936 switch (Inst.getOpcode()) { 2937 case ARM::VST1d8wb_fixed: 2938 case ARM::VST1d16wb_fixed: 2939 case ARM::VST1d32wb_fixed: 2940 case ARM::VST1d64wb_fixed: 2941 case ARM::VST1d8wb_register: 2942 case ARM::VST1d16wb_register: 2943 case ARM::VST1d32wb_register: 2944 case ARM::VST1d64wb_register: 2945 case ARM::VST1q8wb_fixed: 2946 case ARM::VST1q16wb_fixed: 2947 case ARM::VST1q32wb_fixed: 2948 case ARM::VST1q64wb_fixed: 2949 case ARM::VST1q8wb_register: 2950 case ARM::VST1q16wb_register: 2951 case ARM::VST1q32wb_register: 2952 case ARM::VST1q64wb_register: 2953 case ARM::VST1d8Twb_fixed: 2954 case ARM::VST1d16Twb_fixed: 2955 case ARM::VST1d32Twb_fixed: 2956 case ARM::VST1d64Twb_fixed: 2957 case ARM::VST1d8Twb_register: 2958 case ARM::VST1d16Twb_register: 2959 case ARM::VST1d32Twb_register: 2960 case ARM::VST1d64Twb_register: 2961 case ARM::VST1d8Qwb_fixed: 2962 case ARM::VST1d16Qwb_fixed: 2963 case ARM::VST1d32Qwb_fixed: 2964 case ARM::VST1d64Qwb_fixed: 2965 case ARM::VST1d8Qwb_register: 2966 case ARM::VST1d16Qwb_register: 2967 case ARM::VST1d32Qwb_register: 2968 case ARM::VST1d64Qwb_register: 2969 case ARM::VST2d8wb_fixed: 2970 case ARM::VST2d16wb_fixed: 2971 case ARM::VST2d32wb_fixed: 2972 case ARM::VST2d8wb_register: 2973 case ARM::VST2d16wb_register: 2974 case ARM::VST2d32wb_register: 2975 case ARM::VST2q8wb_fixed: 2976 case ARM::VST2q16wb_fixed: 2977 case ARM::VST2q32wb_fixed: 2978 case ARM::VST2q8wb_register: 2979 case ARM::VST2q16wb_register: 2980 case ARM::VST2q32wb_register: 2981 case ARM::VST2b8wb_fixed: 2982 case ARM::VST2b16wb_fixed: 2983 case ARM::VST2b32wb_fixed: 2984 case ARM::VST2b8wb_register: 2985 case ARM::VST2b16wb_register: 2986 case ARM::VST2b32wb_register: 2987 if (Rm == 0xF) 2988 return MCDisassembler::Fail; 2989 Inst.addOperand(MCOperand::createImm(0)); 2990 break; 2991 case ARM::VST3d8_UPD: 2992 case ARM::VST3d16_UPD: 2993 case ARM::VST3d32_UPD: 2994 case ARM::VST3q8_UPD: 2995 case ARM::VST3q16_UPD: 2996 case ARM::VST3q32_UPD: 2997 case ARM::VST4d8_UPD: 2998 case ARM::VST4d16_UPD: 2999 case ARM::VST4d32_UPD: 3000 case ARM::VST4q8_UPD: 3001 case ARM::VST4q16_UPD: 3002 case ARM::VST4q32_UPD: 3003 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3004 return MCDisassembler::Fail; 3005 break; 3006 default: 3007 break; 3008 } 3009 3010 // AddrMode6 Base (register+alignment) 3011 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3012 return MCDisassembler::Fail; 3013 3014 // AddrMode6 Offset (register) 3015 switch (Inst.getOpcode()) { 3016 default: 3017 if (Rm == 0xD) 3018 Inst.addOperand(MCOperand::createReg(0)); 3019 else if (Rm != 0xF) { 3020 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3021 return MCDisassembler::Fail; 3022 } 3023 break; 3024 case ARM::VST1d8wb_fixed: 3025 case ARM::VST1d16wb_fixed: 3026 case ARM::VST1d32wb_fixed: 3027 case ARM::VST1d64wb_fixed: 3028 case ARM::VST1q8wb_fixed: 3029 case ARM::VST1q16wb_fixed: 3030 case ARM::VST1q32wb_fixed: 3031 case ARM::VST1q64wb_fixed: 3032 case ARM::VST1d8Twb_fixed: 3033 case ARM::VST1d16Twb_fixed: 3034 case ARM::VST1d32Twb_fixed: 3035 case ARM::VST1d64Twb_fixed: 3036 case ARM::VST1d8Qwb_fixed: 3037 case ARM::VST1d16Qwb_fixed: 3038 case ARM::VST1d32Qwb_fixed: 3039 case ARM::VST1d64Qwb_fixed: 3040 case ARM::VST2d8wb_fixed: 3041 case ARM::VST2d16wb_fixed: 3042 case ARM::VST2d32wb_fixed: 3043 case ARM::VST2q8wb_fixed: 3044 case ARM::VST2q16wb_fixed: 3045 case ARM::VST2q32wb_fixed: 3046 case ARM::VST2b8wb_fixed: 3047 case ARM::VST2b16wb_fixed: 3048 case ARM::VST2b32wb_fixed: 3049 break; 3050 } 3051 3052 // First input register 3053 switch (Inst.getOpcode()) { 3054 case ARM::VST1q16: 3055 case ARM::VST1q32: 3056 case ARM::VST1q64: 3057 case ARM::VST1q8: 3058 case ARM::VST1q16wb_fixed: 3059 case ARM::VST1q16wb_register: 3060 case ARM::VST1q32wb_fixed: 3061 case ARM::VST1q32wb_register: 3062 case ARM::VST1q64wb_fixed: 3063 case ARM::VST1q64wb_register: 3064 case ARM::VST1q8wb_fixed: 3065 case ARM::VST1q8wb_register: 3066 case ARM::VST2d16: 3067 case ARM::VST2d32: 3068 case ARM::VST2d8: 3069 case ARM::VST2d16wb_fixed: 3070 case ARM::VST2d16wb_register: 3071 case ARM::VST2d32wb_fixed: 3072 case ARM::VST2d32wb_register: 3073 case ARM::VST2d8wb_fixed: 3074 case ARM::VST2d8wb_register: 3075 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3076 return MCDisassembler::Fail; 3077 break; 3078 case ARM::VST2b16: 3079 case ARM::VST2b32: 3080 case ARM::VST2b8: 3081 case ARM::VST2b16wb_fixed: 3082 case ARM::VST2b16wb_register: 3083 case ARM::VST2b32wb_fixed: 3084 case ARM::VST2b32wb_register: 3085 case ARM::VST2b8wb_fixed: 3086 case ARM::VST2b8wb_register: 3087 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 break; 3090 default: 3091 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3092 return MCDisassembler::Fail; 3093 } 3094 3095 // Second input register 3096 switch (Inst.getOpcode()) { 3097 case ARM::VST3d8: 3098 case ARM::VST3d16: 3099 case ARM::VST3d32: 3100 case ARM::VST3d8_UPD: 3101 case ARM::VST3d16_UPD: 3102 case ARM::VST3d32_UPD: 3103 case ARM::VST4d8: 3104 case ARM::VST4d16: 3105 case ARM::VST4d32: 3106 case ARM::VST4d8_UPD: 3107 case ARM::VST4d16_UPD: 3108 case ARM::VST4d32_UPD: 3109 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3110 return MCDisassembler::Fail; 3111 break; 3112 case ARM::VST3q8: 3113 case ARM::VST3q16: 3114 case ARM::VST3q32: 3115 case ARM::VST3q8_UPD: 3116 case ARM::VST3q16_UPD: 3117 case ARM::VST3q32_UPD: 3118 case ARM::VST4q8: 3119 case ARM::VST4q16: 3120 case ARM::VST4q32: 3121 case ARM::VST4q8_UPD: 3122 case ARM::VST4q16_UPD: 3123 case ARM::VST4q32_UPD: 3124 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3125 return MCDisassembler::Fail; 3126 break; 3127 default: 3128 break; 3129 } 3130 3131 // Third input register 3132 switch (Inst.getOpcode()) { 3133 case ARM::VST3d8: 3134 case ARM::VST3d16: 3135 case ARM::VST3d32: 3136 case ARM::VST3d8_UPD: 3137 case ARM::VST3d16_UPD: 3138 case ARM::VST3d32_UPD: 3139 case ARM::VST4d8: 3140 case ARM::VST4d16: 3141 case ARM::VST4d32: 3142 case ARM::VST4d8_UPD: 3143 case ARM::VST4d16_UPD: 3144 case ARM::VST4d32_UPD: 3145 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3146 return MCDisassembler::Fail; 3147 break; 3148 case ARM::VST3q8: 3149 case ARM::VST3q16: 3150 case ARM::VST3q32: 3151 case ARM::VST3q8_UPD: 3152 case ARM::VST3q16_UPD: 3153 case ARM::VST3q32_UPD: 3154 case ARM::VST4q8: 3155 case ARM::VST4q16: 3156 case ARM::VST4q32: 3157 case ARM::VST4q8_UPD: 3158 case ARM::VST4q16_UPD: 3159 case ARM::VST4q32_UPD: 3160 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3161 return MCDisassembler::Fail; 3162 break; 3163 default: 3164 break; 3165 } 3166 3167 // Fourth input register 3168 switch (Inst.getOpcode()) { 3169 case ARM::VST4d8: 3170 case ARM::VST4d16: 3171 case ARM::VST4d32: 3172 case ARM::VST4d8_UPD: 3173 case ARM::VST4d16_UPD: 3174 case ARM::VST4d32_UPD: 3175 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3176 return MCDisassembler::Fail; 3177 break; 3178 case ARM::VST4q8: 3179 case ARM::VST4q16: 3180 case ARM::VST4q32: 3181 case ARM::VST4q8_UPD: 3182 case ARM::VST4q16_UPD: 3183 case ARM::VST4q32_UPD: 3184 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3185 return MCDisassembler::Fail; 3186 break; 3187 default: 3188 break; 3189 } 3190 3191 return S; 3192 } 3193 3194 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3195 uint64_t Address, const void *Decoder) { 3196 DecodeStatus S = MCDisassembler::Success; 3197 3198 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3199 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3200 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3201 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3202 unsigned align = fieldFromInstruction(Insn, 4, 1); 3203 unsigned size = fieldFromInstruction(Insn, 6, 2); 3204 3205 if (size == 0 && align == 1) 3206 return MCDisassembler::Fail; 3207 align *= (1 << size); 3208 3209 switch (Inst.getOpcode()) { 3210 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3211 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3212 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3213 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3214 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3215 return MCDisassembler::Fail; 3216 break; 3217 default: 3218 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3219 return MCDisassembler::Fail; 3220 break; 3221 } 3222 if (Rm != 0xF) { 3223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3224 return MCDisassembler::Fail; 3225 } 3226 3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 Inst.addOperand(MCOperand::createImm(align)); 3230 3231 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3232 // variant encodes Rm == 0xf. Anything else is a register offset post- 3233 // increment and we need to add the register operand to the instruction. 3234 if (Rm != 0xD && Rm != 0xF && 3235 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3236 return MCDisassembler::Fail; 3237 3238 return S; 3239 } 3240 3241 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3242 uint64_t Address, const void *Decoder) { 3243 DecodeStatus S = MCDisassembler::Success; 3244 3245 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3246 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3247 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3248 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3249 unsigned align = fieldFromInstruction(Insn, 4, 1); 3250 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3251 align *= 2*size; 3252 3253 switch (Inst.getOpcode()) { 3254 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3255 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3256 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3257 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3258 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3259 return MCDisassembler::Fail; 3260 break; 3261 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3262 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3263 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3264 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3265 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3266 return MCDisassembler::Fail; 3267 break; 3268 default: 3269 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3270 return MCDisassembler::Fail; 3271 break; 3272 } 3273 3274 if (Rm != 0xF) 3275 Inst.addOperand(MCOperand::createImm(0)); 3276 3277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3278 return MCDisassembler::Fail; 3279 Inst.addOperand(MCOperand::createImm(align)); 3280 3281 if (Rm != 0xD && Rm != 0xF) { 3282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3283 return MCDisassembler::Fail; 3284 } 3285 3286 return S; 3287 } 3288 3289 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3290 uint64_t Address, const void *Decoder) { 3291 DecodeStatus S = MCDisassembler::Success; 3292 3293 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3294 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3295 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3296 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3297 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3298 3299 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3300 return MCDisassembler::Fail; 3301 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3302 return MCDisassembler::Fail; 3303 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3304 return MCDisassembler::Fail; 3305 if (Rm != 0xF) { 3306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3307 return MCDisassembler::Fail; 3308 } 3309 3310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3311 return MCDisassembler::Fail; 3312 Inst.addOperand(MCOperand::createImm(0)); 3313 3314 if (Rm == 0xD) 3315 Inst.addOperand(MCOperand::createReg(0)); 3316 else if (Rm != 0xF) { 3317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3318 return MCDisassembler::Fail; 3319 } 3320 3321 return S; 3322 } 3323 3324 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3325 uint64_t Address, const void *Decoder) { 3326 DecodeStatus S = MCDisassembler::Success; 3327 3328 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3329 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3330 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3331 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3332 unsigned size = fieldFromInstruction(Insn, 6, 2); 3333 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3334 unsigned align = fieldFromInstruction(Insn, 4, 1); 3335 3336 if (size == 0x3) { 3337 if (align == 0) 3338 return MCDisassembler::Fail; 3339 align = 16; 3340 } else { 3341 if (size == 2) { 3342 align *= 8; 3343 } else { 3344 size = 1 << size; 3345 align *= 4*size; 3346 } 3347 } 3348 3349 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3350 return MCDisassembler::Fail; 3351 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3352 return MCDisassembler::Fail; 3353 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3354 return MCDisassembler::Fail; 3355 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3356 return MCDisassembler::Fail; 3357 if (Rm != 0xF) { 3358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3359 return MCDisassembler::Fail; 3360 } 3361 3362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3363 return MCDisassembler::Fail; 3364 Inst.addOperand(MCOperand::createImm(align)); 3365 3366 if (Rm == 0xD) 3367 Inst.addOperand(MCOperand::createReg(0)); 3368 else if (Rm != 0xF) { 3369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3370 return MCDisassembler::Fail; 3371 } 3372 3373 return S; 3374 } 3375 3376 static DecodeStatus 3377 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3378 uint64_t Address, const void *Decoder) { 3379 DecodeStatus S = MCDisassembler::Success; 3380 3381 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3382 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3383 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3384 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3385 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3386 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3387 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3388 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3389 3390 if (Q) { 3391 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3392 return MCDisassembler::Fail; 3393 } else { 3394 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3395 return MCDisassembler::Fail; 3396 } 3397 3398 Inst.addOperand(MCOperand::createImm(imm)); 3399 3400 switch (Inst.getOpcode()) { 3401 case ARM::VORRiv4i16: 3402 case ARM::VORRiv2i32: 3403 case ARM::VBICiv4i16: 3404 case ARM::VBICiv2i32: 3405 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3406 return MCDisassembler::Fail; 3407 break; 3408 case ARM::VORRiv8i16: 3409 case ARM::VORRiv4i32: 3410 case ARM::VBICiv8i16: 3411 case ARM::VBICiv4i32: 3412 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3413 return MCDisassembler::Fail; 3414 break; 3415 default: 3416 break; 3417 } 3418 3419 return S; 3420 } 3421 3422 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3423 uint64_t Address, const void *Decoder) { 3424 DecodeStatus S = MCDisassembler::Success; 3425 3426 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3427 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3428 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3429 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3430 unsigned size = fieldFromInstruction(Insn, 18, 2); 3431 3432 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3433 return MCDisassembler::Fail; 3434 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3435 return MCDisassembler::Fail; 3436 Inst.addOperand(MCOperand::createImm(8 << size)); 3437 3438 return S; 3439 } 3440 3441 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3442 uint64_t Address, const void *Decoder) { 3443 Inst.addOperand(MCOperand::createImm(8 - Val)); 3444 return MCDisassembler::Success; 3445 } 3446 3447 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3448 uint64_t Address, const void *Decoder) { 3449 Inst.addOperand(MCOperand::createImm(16 - Val)); 3450 return MCDisassembler::Success; 3451 } 3452 3453 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3454 uint64_t Address, const void *Decoder) { 3455 Inst.addOperand(MCOperand::createImm(32 - Val)); 3456 return MCDisassembler::Success; 3457 } 3458 3459 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3460 uint64_t Address, const void *Decoder) { 3461 Inst.addOperand(MCOperand::createImm(64 - Val)); 3462 return MCDisassembler::Success; 3463 } 3464 3465 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3466 uint64_t Address, const void *Decoder) { 3467 DecodeStatus S = MCDisassembler::Success; 3468 3469 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3470 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3471 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3472 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3473 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3474 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3475 unsigned op = fieldFromInstruction(Insn, 6, 1); 3476 3477 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3478 return MCDisassembler::Fail; 3479 if (op) { 3480 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3481 return MCDisassembler::Fail; // Writeback 3482 } 3483 3484 switch (Inst.getOpcode()) { 3485 case ARM::VTBL2: 3486 case ARM::VTBX2: 3487 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3488 return MCDisassembler::Fail; 3489 break; 3490 default: 3491 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3492 return MCDisassembler::Fail; 3493 } 3494 3495 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3496 return MCDisassembler::Fail; 3497 3498 return S; 3499 } 3500 3501 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3502 uint64_t Address, const void *Decoder) { 3503 DecodeStatus S = MCDisassembler::Success; 3504 3505 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3506 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3507 3508 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3509 return MCDisassembler::Fail; 3510 3511 switch(Inst.getOpcode()) { 3512 default: 3513 return MCDisassembler::Fail; 3514 case ARM::tADR: 3515 break; // tADR does not explicitly represent the PC as an operand. 3516 case ARM::tADDrSPi: 3517 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3518 break; 3519 } 3520 3521 Inst.addOperand(MCOperand::createImm(imm)); 3522 return S; 3523 } 3524 3525 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3526 uint64_t Address, const void *Decoder) { 3527 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3528 true, 2, Inst, Decoder)) 3529 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3530 return MCDisassembler::Success; 3531 } 3532 3533 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3534 uint64_t Address, const void *Decoder) { 3535 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3536 true, 4, Inst, Decoder)) 3537 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3538 return MCDisassembler::Success; 3539 } 3540 3541 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3542 uint64_t Address, const void *Decoder) { 3543 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3544 true, 2, Inst, Decoder)) 3545 Inst.addOperand(MCOperand::createImm(Val << 1)); 3546 return MCDisassembler::Success; 3547 } 3548 3549 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3550 uint64_t Address, const void *Decoder) { 3551 DecodeStatus S = MCDisassembler::Success; 3552 3553 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3554 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3555 3556 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3557 return MCDisassembler::Fail; 3558 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3559 return MCDisassembler::Fail; 3560 3561 return S; 3562 } 3563 3564 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3565 uint64_t Address, const void *Decoder) { 3566 DecodeStatus S = MCDisassembler::Success; 3567 3568 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3569 unsigned imm = fieldFromInstruction(Val, 3, 5); 3570 3571 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3572 return MCDisassembler::Fail; 3573 Inst.addOperand(MCOperand::createImm(imm)); 3574 3575 return S; 3576 } 3577 3578 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3579 uint64_t Address, const void *Decoder) { 3580 unsigned imm = Val << 2; 3581 3582 Inst.addOperand(MCOperand::createImm(imm)); 3583 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3584 3585 return MCDisassembler::Success; 3586 } 3587 3588 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3589 uint64_t Address, const void *Decoder) { 3590 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3591 Inst.addOperand(MCOperand::createImm(Val)); 3592 3593 return MCDisassembler::Success; 3594 } 3595 3596 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3597 uint64_t Address, const void *Decoder) { 3598 DecodeStatus S = MCDisassembler::Success; 3599 3600 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3601 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3602 unsigned imm = fieldFromInstruction(Val, 0, 2); 3603 3604 // Thumb stores cannot use PC as dest register. 3605 switch (Inst.getOpcode()) { 3606 case ARM::t2STRHs: 3607 case ARM::t2STRBs: 3608 case ARM::t2STRs: 3609 if (Rn == 15) 3610 return MCDisassembler::Fail; 3611 break; 3612 default: 3613 break; 3614 } 3615 3616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3617 return MCDisassembler::Fail; 3618 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3619 return MCDisassembler::Fail; 3620 Inst.addOperand(MCOperand::createImm(imm)); 3621 3622 return S; 3623 } 3624 3625 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3626 uint64_t Address, const void *Decoder) { 3627 DecodeStatus S = MCDisassembler::Success; 3628 3629 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3630 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3631 3632 const FeatureBitset &featureBits = 3633 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3634 3635 bool hasMP = featureBits[ARM::FeatureMP]; 3636 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3637 3638 if (Rn == 15) { 3639 switch (Inst.getOpcode()) { 3640 case ARM::t2LDRBs: 3641 Inst.setOpcode(ARM::t2LDRBpci); 3642 break; 3643 case ARM::t2LDRHs: 3644 Inst.setOpcode(ARM::t2LDRHpci); 3645 break; 3646 case ARM::t2LDRSHs: 3647 Inst.setOpcode(ARM::t2LDRSHpci); 3648 break; 3649 case ARM::t2LDRSBs: 3650 Inst.setOpcode(ARM::t2LDRSBpci); 3651 break; 3652 case ARM::t2LDRs: 3653 Inst.setOpcode(ARM::t2LDRpci); 3654 break; 3655 case ARM::t2PLDs: 3656 Inst.setOpcode(ARM::t2PLDpci); 3657 break; 3658 case ARM::t2PLIs: 3659 Inst.setOpcode(ARM::t2PLIpci); 3660 break; 3661 default: 3662 return MCDisassembler::Fail; 3663 } 3664 3665 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3666 } 3667 3668 if (Rt == 15) { 3669 switch (Inst.getOpcode()) { 3670 case ARM::t2LDRSHs: 3671 return MCDisassembler::Fail; 3672 case ARM::t2LDRHs: 3673 Inst.setOpcode(ARM::t2PLDWs); 3674 break; 3675 case ARM::t2LDRSBs: 3676 Inst.setOpcode(ARM::t2PLIs); 3677 break; 3678 default: 3679 break; 3680 } 3681 } 3682 3683 switch (Inst.getOpcode()) { 3684 case ARM::t2PLDs: 3685 break; 3686 case ARM::t2PLIs: 3687 if (!hasV7Ops) 3688 return MCDisassembler::Fail; 3689 break; 3690 case ARM::t2PLDWs: 3691 if (!hasV7Ops || !hasMP) 3692 return MCDisassembler::Fail; 3693 break; 3694 default: 3695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3696 return MCDisassembler::Fail; 3697 } 3698 3699 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3700 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3701 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3702 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3703 return MCDisassembler::Fail; 3704 3705 return S; 3706 } 3707 3708 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3709 uint64_t Address, const void* Decoder) { 3710 DecodeStatus S = MCDisassembler::Success; 3711 3712 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3713 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3714 unsigned U = fieldFromInstruction(Insn, 9, 1); 3715 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3716 imm |= (U << 8); 3717 imm |= (Rn << 9); 3718 unsigned add = fieldFromInstruction(Insn, 9, 1); 3719 3720 const FeatureBitset &featureBits = 3721 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3722 3723 bool hasMP = featureBits[ARM::FeatureMP]; 3724 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3725 3726 if (Rn == 15) { 3727 switch (Inst.getOpcode()) { 3728 case ARM::t2LDRi8: 3729 Inst.setOpcode(ARM::t2LDRpci); 3730 break; 3731 case ARM::t2LDRBi8: 3732 Inst.setOpcode(ARM::t2LDRBpci); 3733 break; 3734 case ARM::t2LDRSBi8: 3735 Inst.setOpcode(ARM::t2LDRSBpci); 3736 break; 3737 case ARM::t2LDRHi8: 3738 Inst.setOpcode(ARM::t2LDRHpci); 3739 break; 3740 case ARM::t2LDRSHi8: 3741 Inst.setOpcode(ARM::t2LDRSHpci); 3742 break; 3743 case ARM::t2PLDi8: 3744 Inst.setOpcode(ARM::t2PLDpci); 3745 break; 3746 case ARM::t2PLIi8: 3747 Inst.setOpcode(ARM::t2PLIpci); 3748 break; 3749 default: 3750 return MCDisassembler::Fail; 3751 } 3752 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3753 } 3754 3755 if (Rt == 15) { 3756 switch (Inst.getOpcode()) { 3757 case ARM::t2LDRSHi8: 3758 return MCDisassembler::Fail; 3759 case ARM::t2LDRHi8: 3760 if (!add) 3761 Inst.setOpcode(ARM::t2PLDWi8); 3762 break; 3763 case ARM::t2LDRSBi8: 3764 Inst.setOpcode(ARM::t2PLIi8); 3765 break; 3766 default: 3767 break; 3768 } 3769 } 3770 3771 switch (Inst.getOpcode()) { 3772 case ARM::t2PLDi8: 3773 break; 3774 case ARM::t2PLIi8: 3775 if (!hasV7Ops) 3776 return MCDisassembler::Fail; 3777 break; 3778 case ARM::t2PLDWi8: 3779 if (!hasV7Ops || !hasMP) 3780 return MCDisassembler::Fail; 3781 break; 3782 default: 3783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3784 return MCDisassembler::Fail; 3785 } 3786 3787 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3788 return MCDisassembler::Fail; 3789 return S; 3790 } 3791 3792 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3793 uint64_t Address, const void* Decoder) { 3794 DecodeStatus S = MCDisassembler::Success; 3795 3796 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3797 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3798 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3799 imm |= (Rn << 13); 3800 3801 const FeatureBitset &featureBits = 3802 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3803 3804 bool hasMP = featureBits[ARM::FeatureMP]; 3805 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3806 3807 if (Rn == 15) { 3808 switch (Inst.getOpcode()) { 3809 case ARM::t2LDRi12: 3810 Inst.setOpcode(ARM::t2LDRpci); 3811 break; 3812 case ARM::t2LDRHi12: 3813 Inst.setOpcode(ARM::t2LDRHpci); 3814 break; 3815 case ARM::t2LDRSHi12: 3816 Inst.setOpcode(ARM::t2LDRSHpci); 3817 break; 3818 case ARM::t2LDRBi12: 3819 Inst.setOpcode(ARM::t2LDRBpci); 3820 break; 3821 case ARM::t2LDRSBi12: 3822 Inst.setOpcode(ARM::t2LDRSBpci); 3823 break; 3824 case ARM::t2PLDi12: 3825 Inst.setOpcode(ARM::t2PLDpci); 3826 break; 3827 case ARM::t2PLIi12: 3828 Inst.setOpcode(ARM::t2PLIpci); 3829 break; 3830 default: 3831 return MCDisassembler::Fail; 3832 } 3833 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3834 } 3835 3836 if (Rt == 15) { 3837 switch (Inst.getOpcode()) { 3838 case ARM::t2LDRSHi12: 3839 return MCDisassembler::Fail; 3840 case ARM::t2LDRHi12: 3841 Inst.setOpcode(ARM::t2PLDWi12); 3842 break; 3843 case ARM::t2LDRSBi12: 3844 Inst.setOpcode(ARM::t2PLIi12); 3845 break; 3846 default: 3847 break; 3848 } 3849 } 3850 3851 switch (Inst.getOpcode()) { 3852 case ARM::t2PLDi12: 3853 break; 3854 case ARM::t2PLIi12: 3855 if (!hasV7Ops) 3856 return MCDisassembler::Fail; 3857 break; 3858 case ARM::t2PLDWi12: 3859 if (!hasV7Ops || !hasMP) 3860 return MCDisassembler::Fail; 3861 break; 3862 default: 3863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3864 return MCDisassembler::Fail; 3865 } 3866 3867 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3868 return MCDisassembler::Fail; 3869 return S; 3870 } 3871 3872 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3873 uint64_t Address, const void* Decoder) { 3874 DecodeStatus S = MCDisassembler::Success; 3875 3876 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3877 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3878 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3879 imm |= (Rn << 9); 3880 3881 if (Rn == 15) { 3882 switch (Inst.getOpcode()) { 3883 case ARM::t2LDRT: 3884 Inst.setOpcode(ARM::t2LDRpci); 3885 break; 3886 case ARM::t2LDRBT: 3887 Inst.setOpcode(ARM::t2LDRBpci); 3888 break; 3889 case ARM::t2LDRHT: 3890 Inst.setOpcode(ARM::t2LDRHpci); 3891 break; 3892 case ARM::t2LDRSBT: 3893 Inst.setOpcode(ARM::t2LDRSBpci); 3894 break; 3895 case ARM::t2LDRSHT: 3896 Inst.setOpcode(ARM::t2LDRSHpci); 3897 break; 3898 default: 3899 return MCDisassembler::Fail; 3900 } 3901 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3902 } 3903 3904 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3905 return MCDisassembler::Fail; 3906 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3907 return MCDisassembler::Fail; 3908 return S; 3909 } 3910 3911 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3912 uint64_t Address, const void* Decoder) { 3913 DecodeStatus S = MCDisassembler::Success; 3914 3915 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3916 unsigned U = fieldFromInstruction(Insn, 23, 1); 3917 int imm = fieldFromInstruction(Insn, 0, 12); 3918 3919 const FeatureBitset &featureBits = 3920 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3921 3922 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3923 3924 if (Rt == 15) { 3925 switch (Inst.getOpcode()) { 3926 case ARM::t2LDRBpci: 3927 case ARM::t2LDRHpci: 3928 Inst.setOpcode(ARM::t2PLDpci); 3929 break; 3930 case ARM::t2LDRSBpci: 3931 Inst.setOpcode(ARM::t2PLIpci); 3932 break; 3933 case ARM::t2LDRSHpci: 3934 return MCDisassembler::Fail; 3935 default: 3936 break; 3937 } 3938 } 3939 3940 switch(Inst.getOpcode()) { 3941 case ARM::t2PLDpci: 3942 break; 3943 case ARM::t2PLIpci: 3944 if (!hasV7Ops) 3945 return MCDisassembler::Fail; 3946 break; 3947 default: 3948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3949 return MCDisassembler::Fail; 3950 } 3951 3952 if (!U) { 3953 // Special case for #-0. 3954 if (imm == 0) 3955 imm = INT32_MIN; 3956 else 3957 imm = -imm; 3958 } 3959 Inst.addOperand(MCOperand::createImm(imm)); 3960 3961 return S; 3962 } 3963 3964 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3965 uint64_t Address, const void *Decoder) { 3966 if (Val == 0) 3967 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3968 else { 3969 int imm = Val & 0xFF; 3970 3971 if (!(Val & 0x100)) imm *= -1; 3972 Inst.addOperand(MCOperand::createImm(imm * 4)); 3973 } 3974 3975 return MCDisassembler::Success; 3976 } 3977 3978 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 3979 const void *Decoder) { 3980 if (Val == 0) 3981 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3982 else { 3983 int imm = Val & 0x7F; 3984 3985 if (!(Val & 0x80)) 3986 imm *= -1; 3987 Inst.addOperand(MCOperand::createImm(imm * 4)); 3988 } 3989 3990 return MCDisassembler::Success; 3991 } 3992 3993 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3994 uint64_t Address, const void *Decoder) { 3995 DecodeStatus S = MCDisassembler::Success; 3996 3997 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3998 unsigned imm = fieldFromInstruction(Val, 0, 9); 3999 4000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4001 return MCDisassembler::Fail; 4002 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4003 return MCDisassembler::Fail; 4004 4005 return S; 4006 } 4007 4008 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4009 uint64_t Address, 4010 const void *Decoder) { 4011 DecodeStatus S = MCDisassembler::Success; 4012 4013 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4014 unsigned imm = fieldFromInstruction(Val, 0, 8); 4015 4016 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4017 return MCDisassembler::Fail; 4018 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4019 return MCDisassembler::Fail; 4020 4021 return S; 4022 } 4023 4024 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4025 uint64_t Address, const void *Decoder) { 4026 DecodeStatus S = MCDisassembler::Success; 4027 4028 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4029 unsigned imm = fieldFromInstruction(Val, 0, 8); 4030 4031 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 4034 Inst.addOperand(MCOperand::createImm(imm)); 4035 4036 return S; 4037 } 4038 4039 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4040 uint64_t Address, const void *Decoder) { 4041 int imm = Val & 0xFF; 4042 if (Val == 0) 4043 imm = INT32_MIN; 4044 else if (!(Val & 0x100)) 4045 imm *= -1; 4046 Inst.addOperand(MCOperand::createImm(imm)); 4047 4048 return MCDisassembler::Success; 4049 } 4050 4051 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4052 uint64_t Address, const void *Decoder) { 4053 DecodeStatus S = MCDisassembler::Success; 4054 4055 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4056 unsigned imm = fieldFromInstruction(Val, 0, 9); 4057 4058 // Thumb stores cannot use PC as dest register. 4059 switch (Inst.getOpcode()) { 4060 case ARM::t2STRT: 4061 case ARM::t2STRBT: 4062 case ARM::t2STRHT: 4063 case ARM::t2STRi8: 4064 case ARM::t2STRHi8: 4065 case ARM::t2STRBi8: 4066 if (Rn == 15) 4067 return MCDisassembler::Fail; 4068 break; 4069 default: 4070 break; 4071 } 4072 4073 // Some instructions always use an additive offset. 4074 switch (Inst.getOpcode()) { 4075 case ARM::t2LDRT: 4076 case ARM::t2LDRBT: 4077 case ARM::t2LDRHT: 4078 case ARM::t2LDRSBT: 4079 case ARM::t2LDRSHT: 4080 case ARM::t2STRT: 4081 case ARM::t2STRBT: 4082 case ARM::t2STRHT: 4083 imm |= 0x100; 4084 break; 4085 default: 4086 break; 4087 } 4088 4089 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4090 return MCDisassembler::Fail; 4091 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4092 return MCDisassembler::Fail; 4093 4094 return S; 4095 } 4096 4097 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4098 uint64_t Address, const void *Decoder) { 4099 DecodeStatus S = MCDisassembler::Success; 4100 4101 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4102 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4103 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4104 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4105 addr |= Rn << 9; 4106 unsigned load = fieldFromInstruction(Insn, 20, 1); 4107 4108 if (Rn == 15) { 4109 switch (Inst.getOpcode()) { 4110 case ARM::t2LDR_PRE: 4111 case ARM::t2LDR_POST: 4112 Inst.setOpcode(ARM::t2LDRpci); 4113 break; 4114 case ARM::t2LDRB_PRE: 4115 case ARM::t2LDRB_POST: 4116 Inst.setOpcode(ARM::t2LDRBpci); 4117 break; 4118 case ARM::t2LDRH_PRE: 4119 case ARM::t2LDRH_POST: 4120 Inst.setOpcode(ARM::t2LDRHpci); 4121 break; 4122 case ARM::t2LDRSB_PRE: 4123 case ARM::t2LDRSB_POST: 4124 if (Rt == 15) 4125 Inst.setOpcode(ARM::t2PLIpci); 4126 else 4127 Inst.setOpcode(ARM::t2LDRSBpci); 4128 break; 4129 case ARM::t2LDRSH_PRE: 4130 case ARM::t2LDRSH_POST: 4131 Inst.setOpcode(ARM::t2LDRSHpci); 4132 break; 4133 default: 4134 return MCDisassembler::Fail; 4135 } 4136 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4137 } 4138 4139 if (!load) { 4140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4141 return MCDisassembler::Fail; 4142 } 4143 4144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4145 return MCDisassembler::Fail; 4146 4147 if (load) { 4148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4149 return MCDisassembler::Fail; 4150 } 4151 4152 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4153 return MCDisassembler::Fail; 4154 4155 return S; 4156 } 4157 4158 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4159 uint64_t Address, const void *Decoder) { 4160 DecodeStatus S = MCDisassembler::Success; 4161 4162 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4163 unsigned imm = fieldFromInstruction(Val, 0, 12); 4164 4165 // Thumb stores cannot use PC as dest register. 4166 switch (Inst.getOpcode()) { 4167 case ARM::t2STRi12: 4168 case ARM::t2STRBi12: 4169 case ARM::t2STRHi12: 4170 if (Rn == 15) 4171 return MCDisassembler::Fail; 4172 break; 4173 default: 4174 break; 4175 } 4176 4177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4178 return MCDisassembler::Fail; 4179 Inst.addOperand(MCOperand::createImm(imm)); 4180 4181 return S; 4182 } 4183 4184 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4185 uint64_t Address, const void *Decoder) { 4186 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4187 4188 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4189 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4190 Inst.addOperand(MCOperand::createImm(imm)); 4191 4192 return MCDisassembler::Success; 4193 } 4194 4195 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4196 uint64_t Address, const void *Decoder) { 4197 DecodeStatus S = MCDisassembler::Success; 4198 4199 if (Inst.getOpcode() == ARM::tADDrSP) { 4200 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4201 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4202 4203 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4204 return MCDisassembler::Fail; 4205 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4207 return MCDisassembler::Fail; 4208 } else if (Inst.getOpcode() == ARM::tADDspr) { 4209 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4210 4211 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4212 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4214 return MCDisassembler::Fail; 4215 } 4216 4217 return S; 4218 } 4219 4220 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4221 uint64_t Address, const void *Decoder) { 4222 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4223 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4224 4225 Inst.addOperand(MCOperand::createImm(imod)); 4226 Inst.addOperand(MCOperand::createImm(flags)); 4227 4228 return MCDisassembler::Success; 4229 } 4230 4231 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4232 uint64_t Address, const void *Decoder) { 4233 DecodeStatus S = MCDisassembler::Success; 4234 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4235 unsigned add = fieldFromInstruction(Insn, 4, 1); 4236 4237 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4238 return MCDisassembler::Fail; 4239 Inst.addOperand(MCOperand::createImm(add)); 4240 4241 return S; 4242 } 4243 4244 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4245 uint64_t Address, const void *Decoder) { 4246 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4247 // Note only one trailing zero not two. Also the J1 and J2 values are from 4248 // the encoded instruction. So here change to I1 and I2 values via: 4249 // I1 = NOT(J1 EOR S); 4250 // I2 = NOT(J2 EOR S); 4251 // and build the imm32 with two trailing zeros as documented: 4252 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4253 unsigned S = (Val >> 23) & 1; 4254 unsigned J1 = (Val >> 22) & 1; 4255 unsigned J2 = (Val >> 21) & 1; 4256 unsigned I1 = !(J1 ^ S); 4257 unsigned I2 = !(J2 ^ S); 4258 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4259 int imm32 = SignExtend32<25>(tmp << 1); 4260 4261 if (!tryAddingSymbolicOperand(Address, 4262 (Address & ~2u) + imm32 + 4, 4263 true, 4, Inst, Decoder)) 4264 Inst.addOperand(MCOperand::createImm(imm32)); 4265 return MCDisassembler::Success; 4266 } 4267 4268 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4269 uint64_t Address, const void *Decoder) { 4270 if (Val == 0xA || Val == 0xB) 4271 return MCDisassembler::Fail; 4272 4273 const FeatureBitset &featureBits = 4274 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4275 4276 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4277 return MCDisassembler::Fail; 4278 4279 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should 4280 // decode as VFP/MVE instructions. 4281 if (featureBits[ARM::HasV8_1MMainlineOps] && 4282 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || 4283 (Val & 0xE) == 0xE)) 4284 return MCDisassembler::Fail; 4285 4286 Inst.addOperand(MCOperand::createImm(Val)); 4287 return MCDisassembler::Success; 4288 } 4289 4290 static DecodeStatus 4291 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4292 uint64_t Address, const void *Decoder) { 4293 DecodeStatus S = MCDisassembler::Success; 4294 4295 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4296 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4297 4298 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4302 return MCDisassembler::Fail; 4303 return S; 4304 } 4305 4306 static DecodeStatus 4307 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4308 uint64_t Address, const void *Decoder) { 4309 DecodeStatus S = MCDisassembler::Success; 4310 4311 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4312 if (pred == 0xE || pred == 0xF) { 4313 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4314 switch (opc) { 4315 default: 4316 return MCDisassembler::Fail; 4317 case 0xf3bf8f4: 4318 Inst.setOpcode(ARM::t2DSB); 4319 break; 4320 case 0xf3bf8f5: 4321 Inst.setOpcode(ARM::t2DMB); 4322 break; 4323 case 0xf3bf8f6: 4324 Inst.setOpcode(ARM::t2ISB); 4325 break; 4326 } 4327 4328 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4329 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4330 } 4331 4332 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4333 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4334 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4335 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4336 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4337 4338 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4339 return MCDisassembler::Fail; 4340 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4341 return MCDisassembler::Fail; 4342 4343 return S; 4344 } 4345 4346 // Decode a shifted immediate operand. These basically consist 4347 // of an 8-bit value, and a 4-bit directive that specifies either 4348 // a splat operation or a rotation. 4349 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4350 uint64_t Address, const void *Decoder) { 4351 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4352 if (ctrl == 0) { 4353 unsigned byte = fieldFromInstruction(Val, 8, 2); 4354 unsigned imm = fieldFromInstruction(Val, 0, 8); 4355 switch (byte) { 4356 case 0: 4357 Inst.addOperand(MCOperand::createImm(imm)); 4358 break; 4359 case 1: 4360 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4361 break; 4362 case 2: 4363 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4364 break; 4365 case 3: 4366 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4367 (imm << 8) | imm)); 4368 break; 4369 } 4370 } else { 4371 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4372 unsigned rot = fieldFromInstruction(Val, 7, 5); 4373 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4374 Inst.addOperand(MCOperand::createImm(imm)); 4375 } 4376 4377 return MCDisassembler::Success; 4378 } 4379 4380 static DecodeStatus 4381 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4382 uint64_t Address, const void *Decoder) { 4383 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4384 true, 2, Inst, Decoder)) 4385 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4386 return MCDisassembler::Success; 4387 } 4388 4389 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4390 uint64_t Address, 4391 const void *Decoder) { 4392 // Val is passed in as S:J1:J2:imm10:imm11 4393 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4394 // the encoded instruction. So here change to I1 and I2 values via: 4395 // I1 = NOT(J1 EOR S); 4396 // I2 = NOT(J2 EOR S); 4397 // and build the imm32 with one trailing zero as documented: 4398 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4399 unsigned S = (Val >> 23) & 1; 4400 unsigned J1 = (Val >> 22) & 1; 4401 unsigned J2 = (Val >> 21) & 1; 4402 unsigned I1 = !(J1 ^ S); 4403 unsigned I2 = !(J2 ^ S); 4404 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4405 int imm32 = SignExtend32<25>(tmp << 1); 4406 4407 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4408 true, 4, Inst, Decoder)) 4409 Inst.addOperand(MCOperand::createImm(imm32)); 4410 return MCDisassembler::Success; 4411 } 4412 4413 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4414 uint64_t Address, const void *Decoder) { 4415 if (Val & ~0xf) 4416 return MCDisassembler::Fail; 4417 4418 Inst.addOperand(MCOperand::createImm(Val)); 4419 return MCDisassembler::Success; 4420 } 4421 4422 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4423 uint64_t Address, const void *Decoder) { 4424 if (Val & ~0xf) 4425 return MCDisassembler::Fail; 4426 4427 Inst.addOperand(MCOperand::createImm(Val)); 4428 return MCDisassembler::Success; 4429 } 4430 4431 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4432 uint64_t Address, const void *Decoder) { 4433 DecodeStatus S = MCDisassembler::Success; 4434 const FeatureBitset &FeatureBits = 4435 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4436 4437 if (FeatureBits[ARM::FeatureMClass]) { 4438 unsigned ValLow = Val & 0xff; 4439 4440 // Validate the SYSm value first. 4441 switch (ValLow) { 4442 case 0: // apsr 4443 case 1: // iapsr 4444 case 2: // eapsr 4445 case 3: // xpsr 4446 case 5: // ipsr 4447 case 6: // epsr 4448 case 7: // iepsr 4449 case 8: // msp 4450 case 9: // psp 4451 case 16: // primask 4452 case 20: // control 4453 break; 4454 case 17: // basepri 4455 case 18: // basepri_max 4456 case 19: // faultmask 4457 if (!(FeatureBits[ARM::HasV7Ops])) 4458 // Values basepri, basepri_max and faultmask are only valid for v7m. 4459 return MCDisassembler::Fail; 4460 break; 4461 case 0x8a: // msplim_ns 4462 case 0x8b: // psplim_ns 4463 case 0x91: // basepri_ns 4464 case 0x93: // faultmask_ns 4465 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4466 return MCDisassembler::Fail; 4467 LLVM_FALLTHROUGH; 4468 case 10: // msplim 4469 case 11: // psplim 4470 case 0x88: // msp_ns 4471 case 0x89: // psp_ns 4472 case 0x90: // primask_ns 4473 case 0x94: // control_ns 4474 case 0x98: // sp_ns 4475 if (!(FeatureBits[ARM::Feature8MSecExt])) 4476 return MCDisassembler::Fail; 4477 break; 4478 default: 4479 // Architecturally defined as unpredictable 4480 S = MCDisassembler::SoftFail; 4481 break; 4482 } 4483 4484 if (Inst.getOpcode() == ARM::t2MSR_M) { 4485 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4486 if (!(FeatureBits[ARM::HasV7Ops])) { 4487 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4488 // unpredictable. 4489 if (Mask != 2) 4490 S = MCDisassembler::SoftFail; 4491 } 4492 else { 4493 // The ARMv7-M architecture stores an additional 2-bit mask value in 4494 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4495 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4496 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4497 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4498 // only if the processor includes the DSP extension. 4499 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4500 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4501 S = MCDisassembler::SoftFail; 4502 } 4503 } 4504 } else { 4505 // A/R class 4506 if (Val == 0) 4507 return MCDisassembler::Fail; 4508 } 4509 Inst.addOperand(MCOperand::createImm(Val)); 4510 return S; 4511 } 4512 4513 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4514 uint64_t Address, const void *Decoder) { 4515 unsigned R = fieldFromInstruction(Val, 5, 1); 4516 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4517 4518 // The table of encodings for these banked registers comes from B9.2.3 of the 4519 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4520 // neater. So by fiat, these values are UNPREDICTABLE: 4521 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4522 return MCDisassembler::Fail; 4523 4524 Inst.addOperand(MCOperand::createImm(Val)); 4525 return MCDisassembler::Success; 4526 } 4527 4528 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4529 uint64_t Address, const void *Decoder) { 4530 DecodeStatus S = MCDisassembler::Success; 4531 4532 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4533 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4534 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4535 4536 if (Rn == 0xF) 4537 S = MCDisassembler::SoftFail; 4538 4539 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4540 return MCDisassembler::Fail; 4541 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4542 return MCDisassembler::Fail; 4543 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4544 return MCDisassembler::Fail; 4545 4546 return S; 4547 } 4548 4549 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4550 uint64_t Address, 4551 const void *Decoder) { 4552 DecodeStatus S = MCDisassembler::Success; 4553 4554 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4555 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4556 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4557 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4558 4559 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4560 return MCDisassembler::Fail; 4561 4562 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4563 S = MCDisassembler::SoftFail; 4564 4565 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4566 return MCDisassembler::Fail; 4567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4568 return MCDisassembler::Fail; 4569 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4570 return MCDisassembler::Fail; 4571 4572 return S; 4573 } 4574 4575 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4576 uint64_t Address, const void *Decoder) { 4577 DecodeStatus S = MCDisassembler::Success; 4578 4579 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4580 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4581 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4582 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4583 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4584 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4585 4586 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4587 4588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4589 return MCDisassembler::Fail; 4590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4591 return MCDisassembler::Fail; 4592 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4593 return MCDisassembler::Fail; 4594 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4595 return MCDisassembler::Fail; 4596 4597 return S; 4598 } 4599 4600 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4601 uint64_t Address, const void *Decoder) { 4602 DecodeStatus S = MCDisassembler::Success; 4603 4604 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4605 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4606 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4607 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4608 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4609 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4610 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4611 4612 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4613 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4614 4615 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4616 return MCDisassembler::Fail; 4617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4618 return MCDisassembler::Fail; 4619 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4620 return MCDisassembler::Fail; 4621 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4622 return MCDisassembler::Fail; 4623 4624 return S; 4625 } 4626 4627 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4628 uint64_t Address, const void *Decoder) { 4629 DecodeStatus S = MCDisassembler::Success; 4630 4631 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4632 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4633 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4634 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4635 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4636 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4637 4638 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4639 4640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4641 return MCDisassembler::Fail; 4642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4643 return MCDisassembler::Fail; 4644 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4645 return MCDisassembler::Fail; 4646 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4647 return MCDisassembler::Fail; 4648 4649 return S; 4650 } 4651 4652 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4653 uint64_t Address, const void *Decoder) { 4654 DecodeStatus S = MCDisassembler::Success; 4655 4656 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4657 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4658 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4659 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4660 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4661 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4662 4663 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4664 4665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4666 return MCDisassembler::Fail; 4667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4668 return MCDisassembler::Fail; 4669 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4670 return MCDisassembler::Fail; 4671 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4672 return MCDisassembler::Fail; 4673 4674 return S; 4675 } 4676 4677 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4678 uint64_t Address, const void *Decoder) { 4679 DecodeStatus S = MCDisassembler::Success; 4680 4681 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4682 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4683 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4684 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4685 unsigned size = fieldFromInstruction(Insn, 10, 2); 4686 4687 unsigned align = 0; 4688 unsigned index = 0; 4689 switch (size) { 4690 default: 4691 return MCDisassembler::Fail; 4692 case 0: 4693 if (fieldFromInstruction(Insn, 4, 1)) 4694 return MCDisassembler::Fail; // UNDEFINED 4695 index = fieldFromInstruction(Insn, 5, 3); 4696 break; 4697 case 1: 4698 if (fieldFromInstruction(Insn, 5, 1)) 4699 return MCDisassembler::Fail; // UNDEFINED 4700 index = fieldFromInstruction(Insn, 6, 2); 4701 if (fieldFromInstruction(Insn, 4, 1)) 4702 align = 2; 4703 break; 4704 case 2: 4705 if (fieldFromInstruction(Insn, 6, 1)) 4706 return MCDisassembler::Fail; // UNDEFINED 4707 index = fieldFromInstruction(Insn, 7, 1); 4708 4709 switch (fieldFromInstruction(Insn, 4, 2)) { 4710 case 0 : 4711 align = 0; break; 4712 case 3: 4713 align = 4; break; 4714 default: 4715 return MCDisassembler::Fail; 4716 } 4717 break; 4718 } 4719 4720 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4721 return MCDisassembler::Fail; 4722 if (Rm != 0xF) { // Writeback 4723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4724 return MCDisassembler::Fail; 4725 } 4726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4727 return MCDisassembler::Fail; 4728 Inst.addOperand(MCOperand::createImm(align)); 4729 if (Rm != 0xF) { 4730 if (Rm != 0xD) { 4731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4732 return MCDisassembler::Fail; 4733 } else 4734 Inst.addOperand(MCOperand::createReg(0)); 4735 } 4736 4737 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4738 return MCDisassembler::Fail; 4739 Inst.addOperand(MCOperand::createImm(index)); 4740 4741 return S; 4742 } 4743 4744 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4745 uint64_t Address, const void *Decoder) { 4746 DecodeStatus S = MCDisassembler::Success; 4747 4748 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4749 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4750 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4751 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4752 unsigned size = fieldFromInstruction(Insn, 10, 2); 4753 4754 unsigned align = 0; 4755 unsigned index = 0; 4756 switch (size) { 4757 default: 4758 return MCDisassembler::Fail; 4759 case 0: 4760 if (fieldFromInstruction(Insn, 4, 1)) 4761 return MCDisassembler::Fail; // UNDEFINED 4762 index = fieldFromInstruction(Insn, 5, 3); 4763 break; 4764 case 1: 4765 if (fieldFromInstruction(Insn, 5, 1)) 4766 return MCDisassembler::Fail; // UNDEFINED 4767 index = fieldFromInstruction(Insn, 6, 2); 4768 if (fieldFromInstruction(Insn, 4, 1)) 4769 align = 2; 4770 break; 4771 case 2: 4772 if (fieldFromInstruction(Insn, 6, 1)) 4773 return MCDisassembler::Fail; // UNDEFINED 4774 index = fieldFromInstruction(Insn, 7, 1); 4775 4776 switch (fieldFromInstruction(Insn, 4, 2)) { 4777 case 0: 4778 align = 0; break; 4779 case 3: 4780 align = 4; break; 4781 default: 4782 return MCDisassembler::Fail; 4783 } 4784 break; 4785 } 4786 4787 if (Rm != 0xF) { // Writeback 4788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4789 return MCDisassembler::Fail; 4790 } 4791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4792 return MCDisassembler::Fail; 4793 Inst.addOperand(MCOperand::createImm(align)); 4794 if (Rm != 0xF) { 4795 if (Rm != 0xD) { 4796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4797 return MCDisassembler::Fail; 4798 } else 4799 Inst.addOperand(MCOperand::createReg(0)); 4800 } 4801 4802 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4803 return MCDisassembler::Fail; 4804 Inst.addOperand(MCOperand::createImm(index)); 4805 4806 return S; 4807 } 4808 4809 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4810 uint64_t Address, const void *Decoder) { 4811 DecodeStatus S = MCDisassembler::Success; 4812 4813 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4814 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4815 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4816 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4817 unsigned size = fieldFromInstruction(Insn, 10, 2); 4818 4819 unsigned align = 0; 4820 unsigned index = 0; 4821 unsigned inc = 1; 4822 switch (size) { 4823 default: 4824 return MCDisassembler::Fail; 4825 case 0: 4826 index = fieldFromInstruction(Insn, 5, 3); 4827 if (fieldFromInstruction(Insn, 4, 1)) 4828 align = 2; 4829 break; 4830 case 1: 4831 index = fieldFromInstruction(Insn, 6, 2); 4832 if (fieldFromInstruction(Insn, 4, 1)) 4833 align = 4; 4834 if (fieldFromInstruction(Insn, 5, 1)) 4835 inc = 2; 4836 break; 4837 case 2: 4838 if (fieldFromInstruction(Insn, 5, 1)) 4839 return MCDisassembler::Fail; // UNDEFINED 4840 index = fieldFromInstruction(Insn, 7, 1); 4841 if (fieldFromInstruction(Insn, 4, 1) != 0) 4842 align = 8; 4843 if (fieldFromInstruction(Insn, 6, 1)) 4844 inc = 2; 4845 break; 4846 } 4847 4848 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4849 return MCDisassembler::Fail; 4850 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4851 return MCDisassembler::Fail; 4852 if (Rm != 0xF) { // Writeback 4853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4854 return MCDisassembler::Fail; 4855 } 4856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4857 return MCDisassembler::Fail; 4858 Inst.addOperand(MCOperand::createImm(align)); 4859 if (Rm != 0xF) { 4860 if (Rm != 0xD) { 4861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4862 return MCDisassembler::Fail; 4863 } else 4864 Inst.addOperand(MCOperand::createReg(0)); 4865 } 4866 4867 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4868 return MCDisassembler::Fail; 4869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4870 return MCDisassembler::Fail; 4871 Inst.addOperand(MCOperand::createImm(index)); 4872 4873 return S; 4874 } 4875 4876 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4877 uint64_t Address, const void *Decoder) { 4878 DecodeStatus S = MCDisassembler::Success; 4879 4880 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4881 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4882 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4883 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4884 unsigned size = fieldFromInstruction(Insn, 10, 2); 4885 4886 unsigned align = 0; 4887 unsigned index = 0; 4888 unsigned inc = 1; 4889 switch (size) { 4890 default: 4891 return MCDisassembler::Fail; 4892 case 0: 4893 index = fieldFromInstruction(Insn, 5, 3); 4894 if (fieldFromInstruction(Insn, 4, 1)) 4895 align = 2; 4896 break; 4897 case 1: 4898 index = fieldFromInstruction(Insn, 6, 2); 4899 if (fieldFromInstruction(Insn, 4, 1)) 4900 align = 4; 4901 if (fieldFromInstruction(Insn, 5, 1)) 4902 inc = 2; 4903 break; 4904 case 2: 4905 if (fieldFromInstruction(Insn, 5, 1)) 4906 return MCDisassembler::Fail; // UNDEFINED 4907 index = fieldFromInstruction(Insn, 7, 1); 4908 if (fieldFromInstruction(Insn, 4, 1) != 0) 4909 align = 8; 4910 if (fieldFromInstruction(Insn, 6, 1)) 4911 inc = 2; 4912 break; 4913 } 4914 4915 if (Rm != 0xF) { // Writeback 4916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4917 return MCDisassembler::Fail; 4918 } 4919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4920 return MCDisassembler::Fail; 4921 Inst.addOperand(MCOperand::createImm(align)); 4922 if (Rm != 0xF) { 4923 if (Rm != 0xD) { 4924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4925 return MCDisassembler::Fail; 4926 } else 4927 Inst.addOperand(MCOperand::createReg(0)); 4928 } 4929 4930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4931 return MCDisassembler::Fail; 4932 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4933 return MCDisassembler::Fail; 4934 Inst.addOperand(MCOperand::createImm(index)); 4935 4936 return S; 4937 } 4938 4939 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4940 uint64_t Address, const void *Decoder) { 4941 DecodeStatus S = MCDisassembler::Success; 4942 4943 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4944 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4945 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4946 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4947 unsigned size = fieldFromInstruction(Insn, 10, 2); 4948 4949 unsigned align = 0; 4950 unsigned index = 0; 4951 unsigned inc = 1; 4952 switch (size) { 4953 default: 4954 return MCDisassembler::Fail; 4955 case 0: 4956 if (fieldFromInstruction(Insn, 4, 1)) 4957 return MCDisassembler::Fail; // UNDEFINED 4958 index = fieldFromInstruction(Insn, 5, 3); 4959 break; 4960 case 1: 4961 if (fieldFromInstruction(Insn, 4, 1)) 4962 return MCDisassembler::Fail; // UNDEFINED 4963 index = fieldFromInstruction(Insn, 6, 2); 4964 if (fieldFromInstruction(Insn, 5, 1)) 4965 inc = 2; 4966 break; 4967 case 2: 4968 if (fieldFromInstruction(Insn, 4, 2)) 4969 return MCDisassembler::Fail; // UNDEFINED 4970 index = fieldFromInstruction(Insn, 7, 1); 4971 if (fieldFromInstruction(Insn, 6, 1)) 4972 inc = 2; 4973 break; 4974 } 4975 4976 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4977 return MCDisassembler::Fail; 4978 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4979 return MCDisassembler::Fail; 4980 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4981 return MCDisassembler::Fail; 4982 4983 if (Rm != 0xF) { // Writeback 4984 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4985 return MCDisassembler::Fail; 4986 } 4987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4988 return MCDisassembler::Fail; 4989 Inst.addOperand(MCOperand::createImm(align)); 4990 if (Rm != 0xF) { 4991 if (Rm != 0xD) { 4992 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4993 return MCDisassembler::Fail; 4994 } else 4995 Inst.addOperand(MCOperand::createReg(0)); 4996 } 4997 4998 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4999 return MCDisassembler::Fail; 5000 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5001 return MCDisassembler::Fail; 5002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5003 return MCDisassembler::Fail; 5004 Inst.addOperand(MCOperand::createImm(index)); 5005 5006 return S; 5007 } 5008 5009 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5010 uint64_t Address, const void *Decoder) { 5011 DecodeStatus S = MCDisassembler::Success; 5012 5013 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5014 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5015 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5016 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5017 unsigned size = fieldFromInstruction(Insn, 10, 2); 5018 5019 unsigned align = 0; 5020 unsigned index = 0; 5021 unsigned inc = 1; 5022 switch (size) { 5023 default: 5024 return MCDisassembler::Fail; 5025 case 0: 5026 if (fieldFromInstruction(Insn, 4, 1)) 5027 return MCDisassembler::Fail; // UNDEFINED 5028 index = fieldFromInstruction(Insn, 5, 3); 5029 break; 5030 case 1: 5031 if (fieldFromInstruction(Insn, 4, 1)) 5032 return MCDisassembler::Fail; // UNDEFINED 5033 index = fieldFromInstruction(Insn, 6, 2); 5034 if (fieldFromInstruction(Insn, 5, 1)) 5035 inc = 2; 5036 break; 5037 case 2: 5038 if (fieldFromInstruction(Insn, 4, 2)) 5039 return MCDisassembler::Fail; // UNDEFINED 5040 index = fieldFromInstruction(Insn, 7, 1); 5041 if (fieldFromInstruction(Insn, 6, 1)) 5042 inc = 2; 5043 break; 5044 } 5045 5046 if (Rm != 0xF) { // Writeback 5047 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5048 return MCDisassembler::Fail; 5049 } 5050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5051 return MCDisassembler::Fail; 5052 Inst.addOperand(MCOperand::createImm(align)); 5053 if (Rm != 0xF) { 5054 if (Rm != 0xD) { 5055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5056 return MCDisassembler::Fail; 5057 } else 5058 Inst.addOperand(MCOperand::createReg(0)); 5059 } 5060 5061 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5062 return MCDisassembler::Fail; 5063 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5064 return MCDisassembler::Fail; 5065 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5066 return MCDisassembler::Fail; 5067 Inst.addOperand(MCOperand::createImm(index)); 5068 5069 return S; 5070 } 5071 5072 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5073 uint64_t Address, const void *Decoder) { 5074 DecodeStatus S = MCDisassembler::Success; 5075 5076 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5077 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5078 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5079 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5080 unsigned size = fieldFromInstruction(Insn, 10, 2); 5081 5082 unsigned align = 0; 5083 unsigned index = 0; 5084 unsigned inc = 1; 5085 switch (size) { 5086 default: 5087 return MCDisassembler::Fail; 5088 case 0: 5089 if (fieldFromInstruction(Insn, 4, 1)) 5090 align = 4; 5091 index = fieldFromInstruction(Insn, 5, 3); 5092 break; 5093 case 1: 5094 if (fieldFromInstruction(Insn, 4, 1)) 5095 align = 8; 5096 index = fieldFromInstruction(Insn, 6, 2); 5097 if (fieldFromInstruction(Insn, 5, 1)) 5098 inc = 2; 5099 break; 5100 case 2: 5101 switch (fieldFromInstruction(Insn, 4, 2)) { 5102 case 0: 5103 align = 0; break; 5104 case 3: 5105 return MCDisassembler::Fail; 5106 default: 5107 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5108 } 5109 5110 index = fieldFromInstruction(Insn, 7, 1); 5111 if (fieldFromInstruction(Insn, 6, 1)) 5112 inc = 2; 5113 break; 5114 } 5115 5116 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5117 return MCDisassembler::Fail; 5118 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5119 return MCDisassembler::Fail; 5120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5121 return MCDisassembler::Fail; 5122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5123 return MCDisassembler::Fail; 5124 5125 if (Rm != 0xF) { // Writeback 5126 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5127 return MCDisassembler::Fail; 5128 } 5129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5130 return MCDisassembler::Fail; 5131 Inst.addOperand(MCOperand::createImm(align)); 5132 if (Rm != 0xF) { 5133 if (Rm != 0xD) { 5134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5135 return MCDisassembler::Fail; 5136 } else 5137 Inst.addOperand(MCOperand::createReg(0)); 5138 } 5139 5140 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5141 return MCDisassembler::Fail; 5142 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5143 return MCDisassembler::Fail; 5144 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5145 return MCDisassembler::Fail; 5146 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5147 return MCDisassembler::Fail; 5148 Inst.addOperand(MCOperand::createImm(index)); 5149 5150 return S; 5151 } 5152 5153 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5154 uint64_t Address, const void *Decoder) { 5155 DecodeStatus S = MCDisassembler::Success; 5156 5157 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5158 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5159 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5160 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5161 unsigned size = fieldFromInstruction(Insn, 10, 2); 5162 5163 unsigned align = 0; 5164 unsigned index = 0; 5165 unsigned inc = 1; 5166 switch (size) { 5167 default: 5168 return MCDisassembler::Fail; 5169 case 0: 5170 if (fieldFromInstruction(Insn, 4, 1)) 5171 align = 4; 5172 index = fieldFromInstruction(Insn, 5, 3); 5173 break; 5174 case 1: 5175 if (fieldFromInstruction(Insn, 4, 1)) 5176 align = 8; 5177 index = fieldFromInstruction(Insn, 6, 2); 5178 if (fieldFromInstruction(Insn, 5, 1)) 5179 inc = 2; 5180 break; 5181 case 2: 5182 switch (fieldFromInstruction(Insn, 4, 2)) { 5183 case 0: 5184 align = 0; break; 5185 case 3: 5186 return MCDisassembler::Fail; 5187 default: 5188 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5189 } 5190 5191 index = fieldFromInstruction(Insn, 7, 1); 5192 if (fieldFromInstruction(Insn, 6, 1)) 5193 inc = 2; 5194 break; 5195 } 5196 5197 if (Rm != 0xF) { // Writeback 5198 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5199 return MCDisassembler::Fail; 5200 } 5201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5202 return MCDisassembler::Fail; 5203 Inst.addOperand(MCOperand::createImm(align)); 5204 if (Rm != 0xF) { 5205 if (Rm != 0xD) { 5206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5207 return MCDisassembler::Fail; 5208 } else 5209 Inst.addOperand(MCOperand::createReg(0)); 5210 } 5211 5212 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5213 return MCDisassembler::Fail; 5214 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5215 return MCDisassembler::Fail; 5216 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5217 return MCDisassembler::Fail; 5218 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5219 return MCDisassembler::Fail; 5220 Inst.addOperand(MCOperand::createImm(index)); 5221 5222 return S; 5223 } 5224 5225 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5226 uint64_t Address, const void *Decoder) { 5227 DecodeStatus S = MCDisassembler::Success; 5228 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5229 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5230 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5231 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5232 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5233 5234 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5235 S = MCDisassembler::SoftFail; 5236 5237 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5238 return MCDisassembler::Fail; 5239 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5240 return MCDisassembler::Fail; 5241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5242 return MCDisassembler::Fail; 5243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5244 return MCDisassembler::Fail; 5245 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5246 return MCDisassembler::Fail; 5247 5248 return S; 5249 } 5250 5251 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5252 uint64_t Address, const void *Decoder) { 5253 DecodeStatus S = MCDisassembler::Success; 5254 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5255 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5256 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5257 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5258 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5259 5260 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5261 S = MCDisassembler::SoftFail; 5262 5263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5264 return MCDisassembler::Fail; 5265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5266 return MCDisassembler::Fail; 5267 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5268 return MCDisassembler::Fail; 5269 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5270 return MCDisassembler::Fail; 5271 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5272 return MCDisassembler::Fail; 5273 5274 return S; 5275 } 5276 5277 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5278 uint64_t Address, const void *Decoder) { 5279 DecodeStatus S = MCDisassembler::Success; 5280 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5281 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5282 5283 if (pred == 0xF) { 5284 pred = 0xE; 5285 S = MCDisassembler::SoftFail; 5286 } 5287 5288 if (mask == 0x0) 5289 return MCDisassembler::Fail; 5290 5291 // IT masks are encoded as a sequence of replacement low-order bits 5292 // for the condition code. So if the low bit of the starting 5293 // condition code is 1, then we have to flip all the bits above the 5294 // terminating bit (which is the lowest 1 bit). 5295 if (pred & 1) { 5296 unsigned LowBit = mask & -mask; 5297 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5298 mask ^= BitsAboveLowBit; 5299 } 5300 5301 Inst.addOperand(MCOperand::createImm(pred)); 5302 Inst.addOperand(MCOperand::createImm(mask)); 5303 return S; 5304 } 5305 5306 static DecodeStatus 5307 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5308 uint64_t Address, const void *Decoder) { 5309 DecodeStatus S = MCDisassembler::Success; 5310 5311 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5312 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5313 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5314 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5315 unsigned W = fieldFromInstruction(Insn, 21, 1); 5316 unsigned U = fieldFromInstruction(Insn, 23, 1); 5317 unsigned P = fieldFromInstruction(Insn, 24, 1); 5318 bool writeback = (W == 1) | (P == 0); 5319 5320 addr |= (U << 8) | (Rn << 9); 5321 5322 if (writeback && (Rn == Rt || Rn == Rt2)) 5323 Check(S, MCDisassembler::SoftFail); 5324 if (Rt == Rt2) 5325 Check(S, MCDisassembler::SoftFail); 5326 5327 // Rt 5328 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5329 return MCDisassembler::Fail; 5330 // Rt2 5331 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5332 return MCDisassembler::Fail; 5333 // Writeback operand 5334 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5335 return MCDisassembler::Fail; 5336 // addr 5337 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5338 return MCDisassembler::Fail; 5339 5340 return S; 5341 } 5342 5343 static DecodeStatus 5344 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5345 uint64_t Address, const void *Decoder) { 5346 DecodeStatus S = MCDisassembler::Success; 5347 5348 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5349 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5350 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5351 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5352 unsigned W = fieldFromInstruction(Insn, 21, 1); 5353 unsigned U = fieldFromInstruction(Insn, 23, 1); 5354 unsigned P = fieldFromInstruction(Insn, 24, 1); 5355 bool writeback = (W == 1) | (P == 0); 5356 5357 addr |= (U << 8) | (Rn << 9); 5358 5359 if (writeback && (Rn == Rt || Rn == Rt2)) 5360 Check(S, MCDisassembler::SoftFail); 5361 5362 // Writeback operand 5363 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5364 return MCDisassembler::Fail; 5365 // Rt 5366 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5367 return MCDisassembler::Fail; 5368 // Rt2 5369 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5370 return MCDisassembler::Fail; 5371 // addr 5372 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5373 return MCDisassembler::Fail; 5374 5375 return S; 5376 } 5377 5378 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5379 uint64_t Address, const void *Decoder) { 5380 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5381 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5382 if (sign1 != sign2) return MCDisassembler::Fail; 5383 5384 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5385 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5386 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5387 Val |= sign1 << 12; 5388 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5389 5390 return MCDisassembler::Success; 5391 } 5392 5393 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5394 uint64_t Address, 5395 const void *Decoder) { 5396 DecodeStatus S = MCDisassembler::Success; 5397 5398 // Shift of "asr #32" is not allowed in Thumb2 mode. 5399 if (Val == 0x20) S = MCDisassembler::Fail; 5400 Inst.addOperand(MCOperand::createImm(Val)); 5401 return S; 5402 } 5403 5404 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5405 uint64_t Address, const void *Decoder) { 5406 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5407 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5408 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5409 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5410 5411 if (pred == 0xF) 5412 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5413 5414 DecodeStatus S = MCDisassembler::Success; 5415 5416 if (Rt == Rn || Rn == Rt2) 5417 S = MCDisassembler::SoftFail; 5418 5419 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5420 return MCDisassembler::Fail; 5421 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5422 return MCDisassembler::Fail; 5423 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5424 return MCDisassembler::Fail; 5425 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5426 return MCDisassembler::Fail; 5427 5428 return S; 5429 } 5430 5431 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5432 uint64_t Address, const void *Decoder) { 5433 const FeatureBitset &featureBits = 5434 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5435 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5436 5437 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5438 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5439 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5440 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5441 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5442 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5443 unsigned op = fieldFromInstruction(Insn, 5, 1); 5444 5445 DecodeStatus S = MCDisassembler::Success; 5446 5447 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5448 if (!(imm & 0x38)) { 5449 if (cmode == 0xF) { 5450 if (op == 1) return MCDisassembler::Fail; 5451 Inst.setOpcode(ARM::VMOVv2f32); 5452 } 5453 if (hasFullFP16) { 5454 if (cmode == 0xE) { 5455 if (op == 1) { 5456 Inst.setOpcode(ARM::VMOVv1i64); 5457 } else { 5458 Inst.setOpcode(ARM::VMOVv8i8); 5459 } 5460 } 5461 if (cmode == 0xD) { 5462 if (op == 1) { 5463 Inst.setOpcode(ARM::VMVNv2i32); 5464 } else { 5465 Inst.setOpcode(ARM::VMOVv2i32); 5466 } 5467 } 5468 if (cmode == 0xC) { 5469 if (op == 1) { 5470 Inst.setOpcode(ARM::VMVNv2i32); 5471 } else { 5472 Inst.setOpcode(ARM::VMOVv2i32); 5473 } 5474 } 5475 } 5476 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5477 } 5478 5479 if (!(imm & 0x20)) return MCDisassembler::Fail; 5480 5481 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5482 return MCDisassembler::Fail; 5483 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5484 return MCDisassembler::Fail; 5485 Inst.addOperand(MCOperand::createImm(64 - imm)); 5486 5487 return S; 5488 } 5489 5490 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5491 uint64_t Address, const void *Decoder) { 5492 const FeatureBitset &featureBits = 5493 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5494 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5495 5496 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5497 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5498 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5499 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5500 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5501 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5502 unsigned op = fieldFromInstruction(Insn, 5, 1); 5503 5504 DecodeStatus S = MCDisassembler::Success; 5505 5506 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5507 if (!(imm & 0x38)) { 5508 if (cmode == 0xF) { 5509 if (op == 1) return MCDisassembler::Fail; 5510 Inst.setOpcode(ARM::VMOVv4f32); 5511 } 5512 if (hasFullFP16) { 5513 if (cmode == 0xE) { 5514 if (op == 1) { 5515 Inst.setOpcode(ARM::VMOVv2i64); 5516 } else { 5517 Inst.setOpcode(ARM::VMOVv16i8); 5518 } 5519 } 5520 if (cmode == 0xD) { 5521 if (op == 1) { 5522 Inst.setOpcode(ARM::VMVNv4i32); 5523 } else { 5524 Inst.setOpcode(ARM::VMOVv4i32); 5525 } 5526 } 5527 if (cmode == 0xC) { 5528 if (op == 1) { 5529 Inst.setOpcode(ARM::VMVNv4i32); 5530 } else { 5531 Inst.setOpcode(ARM::VMOVv4i32); 5532 } 5533 } 5534 } 5535 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5536 } 5537 5538 if (!(imm & 0x20)) return MCDisassembler::Fail; 5539 5540 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5541 return MCDisassembler::Fail; 5542 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5543 return MCDisassembler::Fail; 5544 Inst.addOperand(MCOperand::createImm(64 - imm)); 5545 5546 return S; 5547 } 5548 5549 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5550 unsigned Insn, 5551 uint64_t Address, 5552 const void *Decoder) { 5553 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5554 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5555 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5556 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5557 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5558 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5559 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5560 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5561 5562 DecodeStatus S = MCDisassembler::Success; 5563 5564 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5565 5566 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5567 return MCDisassembler::Fail; 5568 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5569 return MCDisassembler::Fail; 5570 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5571 return MCDisassembler::Fail; 5572 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5573 return MCDisassembler::Fail; 5574 // The lane index does not have any bits in the encoding, because it can only 5575 // be 0. 5576 Inst.addOperand(MCOperand::createImm(0)); 5577 Inst.addOperand(MCOperand::createImm(rotate)); 5578 5579 return S; 5580 } 5581 5582 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5583 uint64_t Address, const void *Decoder) { 5584 DecodeStatus S = MCDisassembler::Success; 5585 5586 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5587 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5588 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5589 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5590 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5591 5592 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5593 S = MCDisassembler::SoftFail; 5594 5595 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5596 return MCDisassembler::Fail; 5597 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5598 return MCDisassembler::Fail; 5599 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5600 return MCDisassembler::Fail; 5601 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5602 return MCDisassembler::Fail; 5603 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5604 return MCDisassembler::Fail; 5605 5606 return S; 5607 } 5608 5609 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5610 uint64_t Address, const void *Decoder) { 5611 DecodeStatus S = MCDisassembler::Success; 5612 5613 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5614 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5615 unsigned cop = fieldFromInstruction(Val, 8, 4); 5616 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5617 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5618 5619 if ((cop & ~0x1) == 0xa) 5620 return MCDisassembler::Fail; 5621 5622 if (Rt == Rt2) 5623 S = MCDisassembler::SoftFail; 5624 5625 // We have to check if the instruction is MRRC2 5626 // or MCRR2 when constructing the operands for 5627 // Inst. Reason is because MRRC2 stores to two 5628 // registers so it's tablegen desc has has two 5629 // outputs whereas MCRR doesn't store to any 5630 // registers so all of it's operands are listed 5631 // as inputs, therefore the operand order for 5632 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5633 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5634 5635 if (Inst.getOpcode() == ARM::MRRC2) { 5636 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5637 return MCDisassembler::Fail; 5638 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5639 return MCDisassembler::Fail; 5640 } 5641 Inst.addOperand(MCOperand::createImm(cop)); 5642 Inst.addOperand(MCOperand::createImm(opc1)); 5643 if (Inst.getOpcode() == ARM::MCRR2) { 5644 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5645 return MCDisassembler::Fail; 5646 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5647 return MCDisassembler::Fail; 5648 } 5649 Inst.addOperand(MCOperand::createImm(CRm)); 5650 5651 return S; 5652 } 5653 5654 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5655 uint64_t Address, 5656 const void *Decoder) { 5657 const FeatureBitset &featureBits = 5658 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5659 DecodeStatus S = MCDisassembler::Success; 5660 5661 // Add explicit operand for the destination sysreg, for cases where 5662 // we have to model it for code generation purposes. 5663 switch (Inst.getOpcode()) { 5664 case ARM::VMSR_FPSCR_NZCVQC: 5665 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5666 break; 5667 case ARM::VMSR_P0: 5668 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5669 break; 5670 } 5671 5672 if (Inst.getOpcode() != ARM::FMSTAT) { 5673 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5674 5675 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5676 if (Rt == 13 || Rt == 15) 5677 S = MCDisassembler::SoftFail; 5678 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5679 } else 5680 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5681 } 5682 5683 // Add explicit operand for the source sysreg, similarly to above. 5684 switch (Inst.getOpcode()) { 5685 case ARM::VMRS_FPSCR_NZCVQC: 5686 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5687 break; 5688 case ARM::VMRS_P0: 5689 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5690 break; 5691 } 5692 5693 if (featureBits[ARM::ModeThumb]) { 5694 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5695 Inst.addOperand(MCOperand::createReg(0)); 5696 } else { 5697 unsigned pred = fieldFromInstruction(Val, 28, 4); 5698 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5699 return MCDisassembler::Fail; 5700 } 5701 5702 return S; 5703 } 5704 5705 template <bool isSigned, bool isNeg, int size> 5706 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5707 uint64_t Address, 5708 const void *Decoder) { 5709 DecodeStatus S = MCDisassembler::Success; 5710 if (Val == 0) 5711 S = MCDisassembler::SoftFail; 5712 5713 uint64_t DecVal; 5714 if (isSigned) 5715 DecVal = SignExtend32<size + 1>(Val << 1); 5716 else 5717 DecVal = (Val << 1); 5718 5719 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5720 Decoder)) 5721 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5722 return S; 5723 } 5724 5725 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5726 uint64_t Address, 5727 const void *Decoder) { 5728 5729 uint64_t LocImm = Inst.getOperand(0).getImm(); 5730 Val = LocImm + (2 << Val); 5731 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5732 Decoder)) 5733 Inst.addOperand(MCOperand::createImm(Val)); 5734 return MCDisassembler::Success; 5735 } 5736 5737 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5738 uint64_t Address, 5739 const void *Decoder) { 5740 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5741 return MCDisassembler::Fail; 5742 Inst.addOperand(MCOperand::createImm(Val)); 5743 return MCDisassembler::Success; 5744 } 5745 5746 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5747 const void *Decoder) { 5748 DecodeStatus S = MCDisassembler::Success; 5749 5750 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5751 fieldFromInstruction(Insn, 1, 10) << 1; 5752 switch (Inst.getOpcode()) { 5753 case ARM::t2LEUpdate: 5754 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5755 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5756 LLVM_FALLTHROUGH; 5757 case ARM::t2LE: 5758 if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address, 5759 Decoder))) 5760 return MCDisassembler::Fail; 5761 break; 5762 case ARM::t2WLS: 5763 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5764 if (!Check(S, 5765 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5766 Address, Decoder)) || 5767 !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address, 5768 Decoder))) 5769 return MCDisassembler::Fail; 5770 break; 5771 case ARM::t2DLS: 5772 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5773 if (Rn == 0xF) { 5774 return MCDisassembler::Fail; 5775 } else { 5776 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5777 if (!Check(S, DecoderGPRRegisterClass(Inst, 5778 fieldFromInstruction(Insn, 16, 4), 5779 Address, Decoder))) 5780 return MCDisassembler::Fail; 5781 } 5782 break; 5783 } 5784 return S; 5785 } 5786 5787 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 5788 uint64_t Address, 5789 const void *Decoder) { 5790 DecodeStatus S = MCDisassembler::Success; 5791 5792 if (Val == 0) 5793 Val = 32; 5794 5795 Inst.addOperand(MCOperand::createImm(Val)); 5796 5797 return S; 5798 } 5799 5800 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 5801 uint64_t Address, const void *Decoder) { 5802 if ((RegNo) + 1 > 11) 5803 return MCDisassembler::Fail; 5804 5805 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 5806 Inst.addOperand(MCOperand::createReg(Register)); 5807 return MCDisassembler::Success; 5808 } 5809 5810 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 5811 uint64_t Address, const void *Decoder) { 5812 if ((RegNo) > 14) 5813 return MCDisassembler::Fail; 5814 5815 unsigned Register = GPRDecoderTable[(RegNo)]; 5816 Inst.addOperand(MCOperand::createReg(Register)); 5817 return MCDisassembler::Success; 5818 } 5819 5820 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 5821 const void *Decoder) { 5822 DecodeStatus S = MCDisassembler::Success; 5823 5824 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5825 Inst.addOperand(MCOperand::createReg(0)); 5826 if (Inst.getOpcode() == ARM::VSCCLRMD) { 5827 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 5828 (fieldFromInstruction(Insn, 12, 4) << 8) | 5829 (fieldFromInstruction(Insn, 22, 1) << 12); 5830 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 5831 return MCDisassembler::Fail; 5832 } 5833 } else { 5834 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 5835 (fieldFromInstruction(Insn, 22, 1) << 8) | 5836 (fieldFromInstruction(Insn, 12, 4) << 9); 5837 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 5838 return MCDisassembler::Fail; 5839 } 5840 } 5841 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5842 5843 return S; 5844 } 5845 5846 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 5847 uint64_t Address, 5848 const void *Decoder) { 5849 if (RegNo > 7) 5850 return MCDisassembler::Fail; 5851 5852 unsigned Register = QPRDecoderTable[RegNo]; 5853 Inst.addOperand(MCOperand::createReg(Register)); 5854 return MCDisassembler::Success; 5855 } 5856 5857 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 5858 uint64_t Address, 5859 const void *Decoder) { 5860 DecodeStatus S = MCDisassembler::Success; 5861 5862 // Parse VPT mask and encode it in the MCInst as an immediate with the same 5863 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 5864 // 't' as 0 and finish with a 1. 5865 unsigned Imm = 0; 5866 // We always start with a 't'. 5867 unsigned CurBit = 0; 5868 for (int i = 3; i >= 0; --i) { 5869 // If the bit we are looking at is not the same as last one, invert the 5870 // CurBit, if it is the same leave it as is. 5871 CurBit ^= (Val >> i) & 1U; 5872 5873 // Encode the CurBit at the right place in the immediate. 5874 Imm |= (CurBit << i); 5875 5876 // If we are done, finish the encoding with a 1. 5877 if ((Val & ~(~0U << i)) == 0) { 5878 Imm |= 1U << i; 5879 break; 5880 } 5881 } 5882 5883 Inst.addOperand(MCOperand::createImm(Imm)); 5884 5885 return S; 5886 } 5887 5888 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 5889 uint64_t Address, const void *Decoder) { 5890 // The vpred_r operand type includes an MQPR register field derived 5891 // from the encoding. But we don't actually want to add an operand 5892 // to the MCInst at this stage, because AddThumbPredicate will do it 5893 // later, and will infer the register number from the TIED_TO 5894 // constraint. So this is a deliberately empty decoder method that 5895 // will inhibit the auto-generated disassembly code from adding an 5896 // operand at all. 5897 return MCDisassembler::Success; 5898 } 5899 5900 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 5901 unsigned Val, 5902 uint64_t Address, 5903 const void *Decoder) { 5904 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 5905 return MCDisassembler::Success; 5906 } 5907 5908 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 5909 unsigned Val, 5910 uint64_t Address, 5911 const void *Decoder) { 5912 unsigned Code; 5913 switch (Val & 0x3) { 5914 case 0: 5915 Code = ARMCC::GE; 5916 break; 5917 case 1: 5918 Code = ARMCC::LT; 5919 break; 5920 case 2: 5921 Code = ARMCC::GT; 5922 break; 5923 case 3: 5924 Code = ARMCC::LE; 5925 break; 5926 } 5927 Inst.addOperand(MCOperand::createImm(Code)); 5928 return MCDisassembler::Success; 5929 } 5930 5931 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 5932 unsigned Val, 5933 uint64_t Address, 5934 const void *Decoder) { 5935 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 5936 return MCDisassembler::Success; 5937 } 5938 5939 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 5940 uint64_t Address, 5941 const void *Decoder) { 5942 unsigned Code; 5943 switch (Val) { 5944 default: 5945 return MCDisassembler::Fail; 5946 case 0: 5947 Code = ARMCC::EQ; 5948 break; 5949 case 1: 5950 Code = ARMCC::NE; 5951 break; 5952 case 4: 5953 Code = ARMCC::GE; 5954 break; 5955 case 5: 5956 Code = ARMCC::LT; 5957 break; 5958 case 6: 5959 Code = ARMCC::GT; 5960 break; 5961 case 7: 5962 Code = ARMCC::LE; 5963 break; 5964 } 5965 5966 Inst.addOperand(MCOperand::createImm(Code)); 5967 return MCDisassembler::Success; 5968 } 5969 5970 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 5971 switch (Opcode) { 5972 case ARM::VSTR_P0_off: 5973 case ARM::VSTR_P0_pre: 5974 case ARM::VSTR_P0_post: 5975 case ARM::VLDR_P0_off: 5976 case ARM::VLDR_P0_pre: 5977 case ARM::VLDR_P0_post: 5978 return ARM::P0; 5979 default: 5980 return 0; 5981 } 5982 } 5983 5984 template<bool Writeback> 5985 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 5986 uint64_t Address, 5987 const void *Decoder) { 5988 switch (Inst.getOpcode()) { 5989 case ARM::VSTR_FPSCR_pre: 5990 case ARM::VSTR_FPSCR_NZCVQC_pre: 5991 case ARM::VLDR_FPSCR_pre: 5992 case ARM::VLDR_FPSCR_NZCVQC_pre: 5993 case ARM::VSTR_FPSCR_off: 5994 case ARM::VSTR_FPSCR_NZCVQC_off: 5995 case ARM::VLDR_FPSCR_off: 5996 case ARM::VLDR_FPSCR_NZCVQC_off: 5997 case ARM::VSTR_FPSCR_post: 5998 case ARM::VSTR_FPSCR_NZCVQC_post: 5999 case ARM::VLDR_FPSCR_post: 6000 case ARM::VLDR_FPSCR_NZCVQC_post: 6001 const FeatureBitset &featureBits = 6002 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6003 6004 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6005 return MCDisassembler::Fail; 6006 } 6007 6008 DecodeStatus S = MCDisassembler::Success; 6009 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6010 Inst.addOperand(MCOperand::createReg(Sysreg)); 6011 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6012 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6013 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6014 6015 if (Writeback) { 6016 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6017 return MCDisassembler::Fail; 6018 } 6019 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6020 return MCDisassembler::Fail; 6021 6022 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6023 Inst.addOperand(MCOperand::createReg(0)); 6024 6025 return S; 6026 } 6027 6028 static DecodeStatus DecodeMVEOverlappingLongShift( 6029 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6030 DecodeStatus S = MCDisassembler::Success; 6031 6032 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6033 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6034 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6035 6036 if (RdaHi == 14) { 6037 // This value of RdaHi (really indicating pc, because RdaHi has to 6038 // be an odd-numbered register, so the low bit will be set by the 6039 // decode function below) indicates that we must decode as SQRSHR 6040 // or UQRSHL, which both have a single Rda register field with all 6041 // four bits. 6042 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6043 6044 switch (Inst.getOpcode()) { 6045 case ARM::MVE_ASRLr: 6046 case ARM::MVE_SQRSHRL: 6047 Inst.setOpcode(ARM::MVE_SQRSHR); 6048 break; 6049 case ARM::MVE_LSLLr: 6050 case ARM::MVE_UQRSHLL: 6051 Inst.setOpcode(ARM::MVE_UQRSHL); 6052 break; 6053 default: 6054 llvm_unreachable("Unexpected starting opcode!"); 6055 } 6056 6057 // Rda as output parameter 6058 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6059 return MCDisassembler::Fail; 6060 6061 // Rda again as input parameter 6062 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6063 return MCDisassembler::Fail; 6064 6065 // Rm, the amount to shift by 6066 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6067 return MCDisassembler::Fail; 6068 6069 return S; 6070 } 6071 6072 // Otherwise, we decode as whichever opcode our caller has already 6073 // put into Inst. Those all look the same: 6074 6075 // RdaLo,RdaHi as output parameters 6076 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6077 return MCDisassembler::Fail; 6078 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6079 return MCDisassembler::Fail; 6080 6081 // RdaLo,RdaHi again as input parameters 6082 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6083 return MCDisassembler::Fail; 6084 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6085 return MCDisassembler::Fail; 6086 6087 // Rm, the amount to shift by 6088 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6089 return MCDisassembler::Fail; 6090 6091 return S; 6092 } 6093