1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Pull DecodeStatus and its enum values into the global namespace. 28 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 29 #define Success llvm::MCDisassembler::Success 30 #define Unpredictable llvm::MCDisassembler::SoftFail 31 #define Fail llvm::MCDisassembler::Fail 32 33 // Helper macro to perform setwise reduction of the current running status 34 // and another status, and return if the new status is Fail. 35 #define CHECK(S,X) do { \ 36 S = (DecodeStatus) ((int)S & (X)); \ 37 if (S == Fail) return Fail; \ 38 } while(0) 39 40 // Forward declare these because the autogenerated code will reference them. 41 // Definitions are further down. 42 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 43 uint64_t Address, const void *Decoder); 44 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 45 unsigned RegNo, uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 50 uint64_t Address, const void *Decoder); 51 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 52 uint64_t Address, const void *Decoder); 53 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 54 uint64_t Address, const void *Decoder); 55 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 56 uint64_t Address, const void *Decoder); 57 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 58 uint64_t Address, const void *Decoder); 59 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 60 unsigned RegNo, 61 uint64_t Address, 62 const void *Decoder); 63 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 64 uint64_t Address, const void *Decoder); 65 66 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 67 uint64_t Address, const void *Decoder); 68 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 69 uint64_t Address, const void *Decoder); 70 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 71 uint64_t Address, const void *Decoder); 72 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 73 uint64_t Address, const void *Decoder); 74 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 75 uint64_t Address, const void *Decoder); 76 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 77 uint64_t Address, const void *Decoder); 78 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 79 uint64_t Address, const void *Decoder); 80 81 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 82 uint64_t Address, const void *Decoder); 83 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 84 uint64_t Address, const void *Decoder); 85 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 86 unsigned Insn, 87 uint64_t Address, 88 const void *Decoder); 89 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 90 uint64_t Address, const void *Decoder); 91 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 92 uint64_t Address, const void *Decoder); 93 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 94 uint64_t Address, const void *Decoder); 95 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 96 uint64_t Address, const void *Decoder); 97 98 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 99 unsigned Insn, 100 uint64_t Adddress, 101 const void *Decoder); 102 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 103 uint64_t Address, const void *Decoder); 104 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 105 uint64_t Address, const void *Decoder); 106 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 125 uint64_t Address, const void *Decoder); 126 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 129 uint64_t Address, const void *Decoder); 130 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 147 uint64_t Address, const void *Decoder); 148 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 181 uint64_t Address, const void *Decoder); 182 183 184 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 229 uint64_t Address, const void *Decoder); 230 231 #include "ARMGenDisassemblerTables.inc" 232 #include "ARMGenInstrInfo.inc" 233 #include "ARMGenEDInfo.inc" 234 235 using namespace llvm; 236 237 static MCDisassembler *createARMDisassembler(const Target &T) { 238 return new ARMDisassembler; 239 } 240 241 static MCDisassembler *createThumbDisassembler(const Target &T) { 242 return new ThumbDisassembler; 243 } 244 245 EDInstInfo *ARMDisassembler::getEDInfo() const { 246 return instInfoARM; 247 } 248 249 EDInstInfo *ThumbDisassembler::getEDInfo() const { 250 return instInfoARM; 251 } 252 253 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 254 const MemoryObject &Region, 255 uint64_t Address, 256 raw_ostream &os) const { 257 uint8_t bytes[4]; 258 259 // We want to read exactly 4 bytes of data. 260 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 261 return Fail; 262 263 // Encoded as a small-endian 32-bit word in the stream. 264 uint32_t insn = (bytes[3] << 24) | 265 (bytes[2] << 16) | 266 (bytes[1] << 8) | 267 (bytes[0] << 0); 268 269 // Calling the auto-generated decoder function. 270 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); 271 if (result != Fail) { 272 Size = 4; 273 return result; 274 } 275 276 // Instructions that are shared between ARM and Thumb modes. 277 // FIXME: This shouldn't really exist. It's an artifact of the 278 // fact that we fail to encode a few instructions properly for Thumb. 279 MI.clear(); 280 result = decodeCommonInstruction32(MI, insn, Address, this); 281 if (result != Fail) { 282 Size = 4; 283 return result; 284 } 285 286 // VFP and NEON instructions, similarly, are shared between ARM 287 // and Thumb modes. 288 MI.clear(); 289 result = decodeVFPInstruction32(MI, insn, Address, this); 290 if (result != Fail) { 291 Size = 4; 292 return result; 293 } 294 295 MI.clear(); 296 result = decodeNEONDataInstruction32(MI, insn, Address, this); 297 if (result != Fail) { 298 Size = 4; 299 // Add a fake predicate operand, because we share these instruction 300 // definitions with Thumb2 where these instructions are predicable. 301 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 302 return result; 303 } 304 305 MI.clear(); 306 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 307 if (result != Fail) { 308 Size = 4; 309 // Add a fake predicate operand, because we share these instruction 310 // definitions with Thumb2 where these instructions are predicable. 311 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 312 return result; 313 } 314 315 MI.clear(); 316 result = decodeNEONDupInstruction32(MI, insn, Address, this); 317 if (result != Fail) { 318 Size = 4; 319 // Add a fake predicate operand, because we share these instruction 320 // definitions with Thumb2 where these instructions are predicable. 321 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 322 return result; 323 } 324 325 MI.clear(); 326 327 return Fail; 328 } 329 330 namespace llvm { 331 extern MCInstrDesc ARMInsts[]; 332 } 333 334 // Thumb1 instructions don't have explicit S bits. Rather, they 335 // implicitly set CPSR. Since it's not represented in the encoding, the 336 // auto-generated decoder won't inject the CPSR operand. We need to fix 337 // that as a post-pass. 338 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 339 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 340 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 341 MCInst::iterator I = MI.begin(); 342 for (unsigned i = 0; i < NumOps; ++i, ++I) { 343 if (I == MI.end()) break; 344 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 345 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 346 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 347 return; 348 } 349 } 350 351 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 352 } 353 354 // Most Thumb instructions don't have explicit predicates in the 355 // encoding, but rather get their predicates from IT context. We need 356 // to fix up the predicate operands using this context information as a 357 // post-pass. 358 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 359 // A few instructions actually have predicates encoded in them. Don't 360 // try to overwrite it if we're seeing one of those. 361 switch (MI.getOpcode()) { 362 case ARM::tBcc: 363 case ARM::t2Bcc: 364 return; 365 default: 366 break; 367 } 368 369 // If we're in an IT block, base the predicate on that. Otherwise, 370 // assume a predicate of AL. 371 unsigned CC; 372 if (!ITBlock.empty()) { 373 CC = ITBlock.back(); 374 ITBlock.pop_back(); 375 } else 376 CC = ARMCC::AL; 377 378 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 379 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 380 MCInst::iterator I = MI.begin(); 381 for (unsigned i = 0; i < NumOps; ++i, ++I) { 382 if (I == MI.end()) break; 383 if (OpInfo[i].isPredicate()) { 384 I = MI.insert(I, MCOperand::CreateImm(CC)); 385 ++I; 386 if (CC == ARMCC::AL) 387 MI.insert(I, MCOperand::CreateReg(0)); 388 else 389 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 390 return; 391 } 392 } 393 394 I = MI.insert(I, MCOperand::CreateImm(CC)); 395 ++I; 396 if (CC == ARMCC::AL) 397 MI.insert(I, MCOperand::CreateReg(0)); 398 else 399 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 400 } 401 402 // Thumb VFP instructions are a special case. Because we share their 403 // encodings between ARM and Thumb modes, and they are predicable in ARM 404 // mode, the auto-generated decoder will give them an (incorrect) 405 // predicate operand. We need to rewrite these operands based on the IT 406 // context as a post-pass. 407 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 408 unsigned CC; 409 if (!ITBlock.empty()) { 410 CC = ITBlock.back(); 411 ITBlock.pop_back(); 412 } else 413 CC = ARMCC::AL; 414 415 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 416 MCInst::iterator I = MI.begin(); 417 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 418 if (OpInfo[i].isPredicate() ) { 419 I->setImm(CC); 420 ++I; 421 if (CC == ARMCC::AL) 422 I->setReg(0); 423 else 424 I->setReg(ARM::CPSR); 425 return; 426 } 427 } 428 } 429 430 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 431 const MemoryObject &Region, 432 uint64_t Address, 433 raw_ostream &os) const { 434 uint8_t bytes[4]; 435 436 // We want to read exactly 2 bytes of data. 437 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 438 return Fail; 439 440 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 441 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); 442 if (result != Fail) { 443 Size = 2; 444 AddThumbPredicate(MI); 445 return result; 446 } 447 448 MI.clear(); 449 result = decodeThumbSBitInstruction16(MI, insn16, Address, this); 450 if (result) { 451 Size = 2; 452 bool InITBlock = !ITBlock.empty(); 453 AddThumbPredicate(MI); 454 AddThumb1SBit(MI, InITBlock); 455 return result; 456 } 457 458 MI.clear(); 459 result = decodeThumb2Instruction16(MI, insn16, Address, this); 460 if (result != Fail) { 461 Size = 2; 462 AddThumbPredicate(MI); 463 464 // If we find an IT instruction, we need to parse its condition 465 // code and mask operands so that we can apply them correctly 466 // to the subsequent instructions. 467 if (MI.getOpcode() == ARM::t2IT) { 468 unsigned firstcond = MI.getOperand(0).getImm(); 469 uint32_t mask = MI.getOperand(1).getImm(); 470 unsigned zeros = CountTrailingZeros_32(mask); 471 mask >>= zeros+1; 472 473 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 474 if (firstcond ^ (mask & 1)) 475 ITBlock.push_back(firstcond ^ 1); 476 else 477 ITBlock.push_back(firstcond); 478 mask >>= 1; 479 } 480 ITBlock.push_back(firstcond); 481 } 482 483 return result; 484 } 485 486 // We want to read exactly 4 bytes of data. 487 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 488 return Fail; 489 490 uint32_t insn32 = (bytes[3] << 8) | 491 (bytes[2] << 0) | 492 (bytes[1] << 24) | 493 (bytes[0] << 16); 494 MI.clear(); 495 result = decodeThumbInstruction32(MI, insn32, Address, this); 496 if (result != Fail) { 497 Size = 4; 498 bool InITBlock = ITBlock.size(); 499 AddThumbPredicate(MI); 500 AddThumb1SBit(MI, InITBlock); 501 return result; 502 } 503 504 MI.clear(); 505 result = decodeThumb2Instruction32(MI, insn32, Address, this); 506 if (result != Fail) { 507 Size = 4; 508 AddThumbPredicate(MI); 509 return result; 510 } 511 512 MI.clear(); 513 result = decodeCommonInstruction32(MI, insn32, Address, this); 514 if (result != Fail) { 515 Size = 4; 516 AddThumbPredicate(MI); 517 return result; 518 } 519 520 MI.clear(); 521 result = decodeVFPInstruction32(MI, insn32, Address, this); 522 if (result != Fail) { 523 Size = 4; 524 UpdateThumbVFPPredicate(MI); 525 return result; 526 } 527 528 MI.clear(); 529 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 530 if (result != Fail) { 531 Size = 4; 532 AddThumbPredicate(MI); 533 return result; 534 } 535 536 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 537 MI.clear(); 538 uint32_t NEONLdStInsn = insn32; 539 NEONLdStInsn &= 0xF0FFFFFF; 540 NEONLdStInsn |= 0x04000000; 541 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 542 if (result != Fail) { 543 Size = 4; 544 AddThumbPredicate(MI); 545 return result; 546 } 547 } 548 549 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 550 MI.clear(); 551 uint32_t NEONDataInsn = insn32; 552 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 553 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 554 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 555 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 556 if (result != Fail) { 557 Size = 4; 558 AddThumbPredicate(MI); 559 return result; 560 } 561 } 562 563 return Fail; 564 } 565 566 567 extern "C" void LLVMInitializeARMDisassembler() { 568 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 569 createARMDisassembler); 570 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 571 createThumbDisassembler); 572 } 573 574 static const unsigned GPRDecoderTable[] = { 575 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 576 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 577 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 578 ARM::R12, ARM::SP, ARM::LR, ARM::PC 579 }; 580 581 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 582 uint64_t Address, const void *Decoder) { 583 if (RegNo > 15) 584 return Fail; 585 586 unsigned Register = GPRDecoderTable[RegNo]; 587 Inst.addOperand(MCOperand::CreateReg(Register)); 588 return Success; 589 } 590 591 static DecodeStatus 592 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 593 uint64_t Address, const void *Decoder) { 594 if (RegNo == 15) return Fail; 595 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 596 } 597 598 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 599 uint64_t Address, const void *Decoder) { 600 if (RegNo > 7) 601 return Fail; 602 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 603 } 604 605 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 606 uint64_t Address, const void *Decoder) { 607 unsigned Register = 0; 608 switch (RegNo) { 609 case 0: 610 Register = ARM::R0; 611 break; 612 case 1: 613 Register = ARM::R1; 614 break; 615 case 2: 616 Register = ARM::R2; 617 break; 618 case 3: 619 Register = ARM::R3; 620 break; 621 case 9: 622 Register = ARM::R9; 623 break; 624 case 12: 625 Register = ARM::R12; 626 break; 627 default: 628 return Fail; 629 } 630 631 Inst.addOperand(MCOperand::CreateReg(Register)); 632 return Success; 633 } 634 635 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 636 uint64_t Address, const void *Decoder) { 637 if (RegNo == 13 || RegNo == 15) return Fail; 638 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 639 } 640 641 static const unsigned SPRDecoderTable[] = { 642 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 643 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 644 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 645 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 646 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 647 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 648 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 649 ARM::S28, ARM::S29, ARM::S30, ARM::S31 650 }; 651 652 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 653 uint64_t Address, const void *Decoder) { 654 if (RegNo > 31) 655 return Fail; 656 657 unsigned Register = SPRDecoderTable[RegNo]; 658 Inst.addOperand(MCOperand::CreateReg(Register)); 659 return Success; 660 } 661 662 static const unsigned DPRDecoderTable[] = { 663 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 664 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 665 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 666 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 667 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 668 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 669 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 670 ARM::D28, ARM::D29, ARM::D30, ARM::D31 671 }; 672 673 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 674 uint64_t Address, const void *Decoder) { 675 if (RegNo > 31) 676 return Fail; 677 678 unsigned Register = DPRDecoderTable[RegNo]; 679 Inst.addOperand(MCOperand::CreateReg(Register)); 680 return Success; 681 } 682 683 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 684 uint64_t Address, const void *Decoder) { 685 if (RegNo > 7) 686 return Fail; 687 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 688 } 689 690 static DecodeStatus 691 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 692 uint64_t Address, const void *Decoder) { 693 if (RegNo > 15) 694 return Fail; 695 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 696 } 697 698 static const unsigned QPRDecoderTable[] = { 699 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 700 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 701 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 702 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 703 }; 704 705 706 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 707 uint64_t Address, const void *Decoder) { 708 if (RegNo > 31) 709 return Fail; 710 RegNo >>= 1; 711 712 unsigned Register = QPRDecoderTable[RegNo]; 713 Inst.addOperand(MCOperand::CreateReg(Register)); 714 return Success; 715 } 716 717 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 718 uint64_t Address, const void *Decoder) { 719 if (Val == 0xF) return Fail; 720 // AL predicate is not allowed on Thumb1 branches. 721 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 722 return Fail; 723 Inst.addOperand(MCOperand::CreateImm(Val)); 724 if (Val == ARMCC::AL) { 725 Inst.addOperand(MCOperand::CreateReg(0)); 726 } else 727 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 728 return Success; 729 } 730 731 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 732 uint64_t Address, const void *Decoder) { 733 if (Val) 734 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 735 else 736 Inst.addOperand(MCOperand::CreateReg(0)); 737 return Success; 738 } 739 740 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 741 uint64_t Address, const void *Decoder) { 742 uint32_t imm = Val & 0xFF; 743 uint32_t rot = (Val & 0xF00) >> 7; 744 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 745 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 746 return Success; 747 } 748 749 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 750 uint64_t Address, const void *Decoder) { 751 Val <<= 2; 752 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 753 return Success; 754 } 755 756 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 757 uint64_t Address, const void *Decoder) { 758 DecodeStatus S = Success; 759 760 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 761 unsigned type = fieldFromInstruction32(Val, 5, 2); 762 unsigned imm = fieldFromInstruction32(Val, 7, 5); 763 764 // Register-immediate 765 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 766 767 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 768 switch (type) { 769 case 0: 770 Shift = ARM_AM::lsl; 771 break; 772 case 1: 773 Shift = ARM_AM::lsr; 774 break; 775 case 2: 776 Shift = ARM_AM::asr; 777 break; 778 case 3: 779 Shift = ARM_AM::ror; 780 break; 781 } 782 783 if (Shift == ARM_AM::ror && imm == 0) 784 Shift = ARM_AM::rrx; 785 786 unsigned Op = Shift | (imm << 3); 787 Inst.addOperand(MCOperand::CreateImm(Op)); 788 789 return S; 790 } 791 792 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 793 uint64_t Address, const void *Decoder) { 794 DecodeStatus S = Success; 795 796 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 797 unsigned type = fieldFromInstruction32(Val, 5, 2); 798 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 799 800 // Register-register 801 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 802 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); 803 804 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 805 switch (type) { 806 case 0: 807 Shift = ARM_AM::lsl; 808 break; 809 case 1: 810 Shift = ARM_AM::lsr; 811 break; 812 case 2: 813 Shift = ARM_AM::asr; 814 break; 815 case 3: 816 Shift = ARM_AM::ror; 817 break; 818 } 819 820 Inst.addOperand(MCOperand::CreateImm(Shift)); 821 822 return S; 823 } 824 825 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 826 uint64_t Address, const void *Decoder) { 827 DecodeStatus S = Success; 828 829 // Empty register lists are not allowed. 830 if (CountPopulation_32(Val) == 0) return Fail; 831 for (unsigned i = 0; i < 16; ++i) { 832 if (Val & (1 << i)) { 833 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); 834 } 835 } 836 837 return S; 838 } 839 840 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 841 uint64_t Address, const void *Decoder) { 842 DecodeStatus S = Success; 843 844 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 845 unsigned regs = Val & 0xFF; 846 847 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); 848 for (unsigned i = 0; i < (regs - 1); ++i) { 849 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); 850 } 851 852 return S; 853 } 854 855 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 856 uint64_t Address, const void *Decoder) { 857 DecodeStatus S = Success; 858 859 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 860 unsigned regs = (Val & 0xFF) / 2; 861 862 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); 863 for (unsigned i = 0; i < (regs - 1); ++i) { 864 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); 865 } 866 867 return S; 868 } 869 870 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 871 uint64_t Address, const void *Decoder) { 872 // This operand encodes a mask of contiguous zeros between a specified MSB 873 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 874 // the mask of all bits LSB-and-lower, and then xor them to create 875 // the mask of that's all ones on [msb, lsb]. Finally we not it to 876 // create the final mask. 877 unsigned msb = fieldFromInstruction32(Val, 5, 5); 878 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 879 uint32_t msb_mask = (1 << (msb+1)) - 1; 880 uint32_t lsb_mask = (1 << lsb) - 1; 881 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 882 return Success; 883 } 884 885 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 886 uint64_t Address, const void *Decoder) { 887 DecodeStatus S = Success; 888 889 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 890 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 891 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 892 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 893 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 894 unsigned U = fieldFromInstruction32(Insn, 23, 1); 895 896 switch (Inst.getOpcode()) { 897 case ARM::LDC_OFFSET: 898 case ARM::LDC_PRE: 899 case ARM::LDC_POST: 900 case ARM::LDC_OPTION: 901 case ARM::LDCL_OFFSET: 902 case ARM::LDCL_PRE: 903 case ARM::LDCL_POST: 904 case ARM::LDCL_OPTION: 905 case ARM::STC_OFFSET: 906 case ARM::STC_PRE: 907 case ARM::STC_POST: 908 case ARM::STC_OPTION: 909 case ARM::STCL_OFFSET: 910 case ARM::STCL_PRE: 911 case ARM::STCL_POST: 912 case ARM::STCL_OPTION: 913 if (coproc == 0xA || coproc == 0xB) 914 return Fail; 915 break; 916 default: 917 break; 918 } 919 920 Inst.addOperand(MCOperand::CreateImm(coproc)); 921 Inst.addOperand(MCOperand::CreateImm(CRd)); 922 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 923 switch (Inst.getOpcode()) { 924 case ARM::LDC_OPTION: 925 case ARM::LDCL_OPTION: 926 case ARM::LDC2_OPTION: 927 case ARM::LDC2L_OPTION: 928 case ARM::STC_OPTION: 929 case ARM::STCL_OPTION: 930 case ARM::STC2_OPTION: 931 case ARM::STC2L_OPTION: 932 case ARM::LDCL_POST: 933 case ARM::STCL_POST: 934 case ARM::LDC2L_POST: 935 case ARM::STC2L_POST: 936 break; 937 default: 938 Inst.addOperand(MCOperand::CreateReg(0)); 939 break; 940 } 941 942 unsigned P = fieldFromInstruction32(Insn, 24, 1); 943 unsigned W = fieldFromInstruction32(Insn, 21, 1); 944 945 bool writeback = (P == 0) || (W == 1); 946 unsigned idx_mode = 0; 947 if (P && writeback) 948 idx_mode = ARMII::IndexModePre; 949 else if (!P && writeback) 950 idx_mode = ARMII::IndexModePost; 951 952 switch (Inst.getOpcode()) { 953 case ARM::LDCL_POST: 954 case ARM::STCL_POST: 955 case ARM::LDC2L_POST: 956 case ARM::STC2L_POST: 957 imm |= U << 8; 958 case ARM::LDC_OPTION: 959 case ARM::LDCL_OPTION: 960 case ARM::LDC2_OPTION: 961 case ARM::LDC2L_OPTION: 962 case ARM::STC_OPTION: 963 case ARM::STCL_OPTION: 964 case ARM::STC2_OPTION: 965 case ARM::STC2L_OPTION: 966 Inst.addOperand(MCOperand::CreateImm(imm)); 967 break; 968 default: 969 if (U) 970 Inst.addOperand(MCOperand::CreateImm( 971 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 972 else 973 Inst.addOperand(MCOperand::CreateImm( 974 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 975 break; 976 } 977 978 switch (Inst.getOpcode()) { 979 case ARM::LDC_OFFSET: 980 case ARM::LDC_PRE: 981 case ARM::LDC_POST: 982 case ARM::LDC_OPTION: 983 case ARM::LDCL_OFFSET: 984 case ARM::LDCL_PRE: 985 case ARM::LDCL_POST: 986 case ARM::LDCL_OPTION: 987 case ARM::STC_OFFSET: 988 case ARM::STC_PRE: 989 case ARM::STC_POST: 990 case ARM::STC_OPTION: 991 case ARM::STCL_OFFSET: 992 case ARM::STCL_PRE: 993 case ARM::STCL_POST: 994 case ARM::STCL_OPTION: 995 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 996 break; 997 default: 998 break; 999 } 1000 1001 return S; 1002 } 1003 1004 static DecodeStatus 1005 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1006 uint64_t Address, const void *Decoder) { 1007 DecodeStatus S = Success; 1008 1009 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1010 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1011 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1012 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1013 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1014 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1015 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1016 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1017 1018 // On stores, the writeback operand precedes Rt. 1019 switch (Inst.getOpcode()) { 1020 case ARM::STR_POST_IMM: 1021 case ARM::STR_POST_REG: 1022 case ARM::STRB_POST_IMM: 1023 case ARM::STRB_POST_REG: 1024 case ARM::STRT_POST_REG: 1025 case ARM::STRT_POST_IMM: 1026 case ARM::STRBT_POST_REG: 1027 case ARM::STRBT_POST_IMM: 1028 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1029 break; 1030 default: 1031 break; 1032 } 1033 1034 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1035 1036 // On loads, the writeback operand comes after Rt. 1037 switch (Inst.getOpcode()) { 1038 case ARM::LDR_POST_IMM: 1039 case ARM::LDR_POST_REG: 1040 case ARM::LDRB_POST_IMM: 1041 case ARM::LDRB_POST_REG: 1042 case ARM::LDR_PRE: 1043 case ARM::LDRB_PRE: 1044 case ARM::LDRBT_POST_REG: 1045 case ARM::LDRBT_POST_IMM: 1046 case ARM::LDRT_POST_REG: 1047 case ARM::LDRT_POST_IMM: 1048 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1049 break; 1050 default: 1051 break; 1052 } 1053 1054 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1055 1056 ARM_AM::AddrOpc Op = ARM_AM::add; 1057 if (!fieldFromInstruction32(Insn, 23, 1)) 1058 Op = ARM_AM::sub; 1059 1060 bool writeback = (P == 0) || (W == 1); 1061 unsigned idx_mode = 0; 1062 if (P && writeback) 1063 idx_mode = ARMII::IndexModePre; 1064 else if (!P && writeback) 1065 idx_mode = ARMII::IndexModePost; 1066 1067 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE 1068 1069 if (reg) { 1070 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1071 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1072 switch( fieldFromInstruction32(Insn, 5, 2)) { 1073 case 0: 1074 Opc = ARM_AM::lsl; 1075 break; 1076 case 1: 1077 Opc = ARM_AM::lsr; 1078 break; 1079 case 2: 1080 Opc = ARM_AM::asr; 1081 break; 1082 case 3: 1083 Opc = ARM_AM::ror; 1084 break; 1085 default: 1086 return Fail; 1087 } 1088 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1089 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1090 1091 Inst.addOperand(MCOperand::CreateImm(imm)); 1092 } else { 1093 Inst.addOperand(MCOperand::CreateReg(0)); 1094 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1095 Inst.addOperand(MCOperand::CreateImm(tmp)); 1096 } 1097 1098 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1099 1100 return S; 1101 } 1102 1103 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1104 uint64_t Address, const void *Decoder) { 1105 DecodeStatus S = Success; 1106 1107 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1108 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1109 unsigned type = fieldFromInstruction32(Val, 5, 2); 1110 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1111 unsigned U = fieldFromInstruction32(Val, 12, 1); 1112 1113 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1114 switch (type) { 1115 case 0: 1116 ShOp = ARM_AM::lsl; 1117 break; 1118 case 1: 1119 ShOp = ARM_AM::lsr; 1120 break; 1121 case 2: 1122 ShOp = ARM_AM::asr; 1123 break; 1124 case 3: 1125 ShOp = ARM_AM::ror; 1126 break; 1127 } 1128 1129 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1130 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1131 unsigned shift; 1132 if (U) 1133 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1134 else 1135 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1136 Inst.addOperand(MCOperand::CreateImm(shift)); 1137 1138 return S; 1139 } 1140 1141 static DecodeStatus 1142 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1143 uint64_t Address, const void *Decoder) { 1144 DecodeStatus S = Success; 1145 1146 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1147 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1148 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1149 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1150 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1151 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1152 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1153 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1154 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1155 1156 bool writeback = (W == 1) | (P == 0); 1157 1158 // For {LD,ST}RD, Rt must be even, else undefined. 1159 switch (Inst.getOpcode()) { 1160 case ARM::STRD: 1161 case ARM::STRD_PRE: 1162 case ARM::STRD_POST: 1163 case ARM::LDRD: 1164 case ARM::LDRD_PRE: 1165 case ARM::LDRD_POST: 1166 if (Rt & 0x1) return Fail; 1167 break; 1168 default: 1169 break; 1170 } 1171 1172 if (writeback) { // Writeback 1173 if (P) 1174 U |= ARMII::IndexModePre << 9; 1175 else 1176 U |= ARMII::IndexModePost << 9; 1177 1178 // On stores, the writeback operand precedes Rt. 1179 switch (Inst.getOpcode()) { 1180 case ARM::STRD: 1181 case ARM::STRD_PRE: 1182 case ARM::STRD_POST: 1183 case ARM::STRH: 1184 case ARM::STRH_PRE: 1185 case ARM::STRH_POST: 1186 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1187 break; 1188 default: 1189 break; 1190 } 1191 } 1192 1193 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1194 switch (Inst.getOpcode()) { 1195 case ARM::STRD: 1196 case ARM::STRD_PRE: 1197 case ARM::STRD_POST: 1198 case ARM::LDRD: 1199 case ARM::LDRD_PRE: 1200 case ARM::LDRD_POST: 1201 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 1202 break; 1203 default: 1204 break; 1205 } 1206 1207 if (writeback) { 1208 // On loads, the writeback operand comes after Rt. 1209 switch (Inst.getOpcode()) { 1210 case ARM::LDRD: 1211 case ARM::LDRD_PRE: 1212 case ARM::LDRD_POST: 1213 case ARM::LDRH: 1214 case ARM::LDRH_PRE: 1215 case ARM::LDRH_POST: 1216 case ARM::LDRSH: 1217 case ARM::LDRSH_PRE: 1218 case ARM::LDRSH_POST: 1219 case ARM::LDRSB: 1220 case ARM::LDRSB_PRE: 1221 case ARM::LDRSB_POST: 1222 case ARM::LDRHTr: 1223 case ARM::LDRSBTr: 1224 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1225 break; 1226 default: 1227 break; 1228 } 1229 } 1230 1231 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1232 1233 if (type) { 1234 Inst.addOperand(MCOperand::CreateReg(0)); 1235 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1236 } else { 1237 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1238 Inst.addOperand(MCOperand::CreateImm(U)); 1239 } 1240 1241 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1242 1243 return S; 1244 } 1245 1246 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1247 uint64_t Address, const void *Decoder) { 1248 DecodeStatus S = Success; 1249 1250 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1251 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1252 1253 switch (mode) { 1254 case 0: 1255 mode = ARM_AM::da; 1256 break; 1257 case 1: 1258 mode = ARM_AM::ia; 1259 break; 1260 case 2: 1261 mode = ARM_AM::db; 1262 break; 1263 case 3: 1264 mode = ARM_AM::ib; 1265 break; 1266 } 1267 1268 Inst.addOperand(MCOperand::CreateImm(mode)); 1269 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1270 1271 return S; 1272 } 1273 1274 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1275 unsigned Insn, 1276 uint64_t Address, const void *Decoder) { 1277 DecodeStatus S = Success; 1278 1279 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1280 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1281 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1282 1283 if (pred == 0xF) { 1284 switch (Inst.getOpcode()) { 1285 case ARM::LDMDA: 1286 Inst.setOpcode(ARM::RFEDA); 1287 break; 1288 case ARM::LDMDA_UPD: 1289 Inst.setOpcode(ARM::RFEDA_UPD); 1290 break; 1291 case ARM::LDMDB: 1292 Inst.setOpcode(ARM::RFEDB); 1293 break; 1294 case ARM::LDMDB_UPD: 1295 Inst.setOpcode(ARM::RFEDB_UPD); 1296 break; 1297 case ARM::LDMIA: 1298 Inst.setOpcode(ARM::RFEIA); 1299 break; 1300 case ARM::LDMIA_UPD: 1301 Inst.setOpcode(ARM::RFEIA_UPD); 1302 break; 1303 case ARM::LDMIB: 1304 Inst.setOpcode(ARM::RFEIB); 1305 break; 1306 case ARM::LDMIB_UPD: 1307 Inst.setOpcode(ARM::RFEIB_UPD); 1308 break; 1309 case ARM::STMDA: 1310 Inst.setOpcode(ARM::SRSDA); 1311 break; 1312 case ARM::STMDA_UPD: 1313 Inst.setOpcode(ARM::SRSDA_UPD); 1314 break; 1315 case ARM::STMDB: 1316 Inst.setOpcode(ARM::SRSDB); 1317 break; 1318 case ARM::STMDB_UPD: 1319 Inst.setOpcode(ARM::SRSDB_UPD); 1320 break; 1321 case ARM::STMIA: 1322 Inst.setOpcode(ARM::SRSIA); 1323 break; 1324 case ARM::STMIA_UPD: 1325 Inst.setOpcode(ARM::SRSIA_UPD); 1326 break; 1327 case ARM::STMIB: 1328 Inst.setOpcode(ARM::SRSIB); 1329 break; 1330 case ARM::STMIB_UPD: 1331 Inst.setOpcode(ARM::SRSIB_UPD); 1332 break; 1333 default: 1334 CHECK(S, Fail); 1335 } 1336 1337 // For stores (which become SRS's, the only operand is the mode. 1338 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1339 Inst.addOperand( 1340 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1341 return S; 1342 } 1343 1344 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1345 } 1346 1347 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1348 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied 1349 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1350 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); 1351 1352 return S; 1353 } 1354 1355 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1356 uint64_t Address, const void *Decoder) { 1357 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1358 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1359 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1360 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1361 1362 DecodeStatus S = Success; 1363 1364 // imod == '01' --> UNPREDICTABLE 1365 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1366 // return failure here. The '01' imod value is unprintable, so there's 1367 // nothing useful we could do even if we returned UNPREDICTABLE. 1368 1369 if (imod == 1) CHECK(S, Fail); 1370 1371 if (imod && M) { 1372 Inst.setOpcode(ARM::CPS3p); 1373 Inst.addOperand(MCOperand::CreateImm(imod)); 1374 Inst.addOperand(MCOperand::CreateImm(iflags)); 1375 Inst.addOperand(MCOperand::CreateImm(mode)); 1376 } else if (imod && !M) { 1377 Inst.setOpcode(ARM::CPS2p); 1378 Inst.addOperand(MCOperand::CreateImm(imod)); 1379 Inst.addOperand(MCOperand::CreateImm(iflags)); 1380 if (mode) CHECK(S, Unpredictable); 1381 } else if (!imod && M) { 1382 Inst.setOpcode(ARM::CPS1p); 1383 Inst.addOperand(MCOperand::CreateImm(mode)); 1384 if (iflags) CHECK(S, Unpredictable); 1385 } else { 1386 // imod == '00' && M == '0' --> UNPREDICTABLE 1387 Inst.setOpcode(ARM::CPS1p); 1388 Inst.addOperand(MCOperand::CreateImm(mode)); 1389 CHECK(S, Unpredictable); 1390 } 1391 1392 return S; 1393 } 1394 1395 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1396 uint64_t Address, const void *Decoder) { 1397 DecodeStatus S = Success; 1398 1399 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1400 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1401 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1402 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1403 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1404 1405 if (pred == 0xF) 1406 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1407 1408 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); 1409 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); 1410 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1411 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); 1412 1413 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1414 1415 return S; 1416 } 1417 1418 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1419 uint64_t Address, const void *Decoder) { 1420 DecodeStatus S = Success; 1421 1422 unsigned add = fieldFromInstruction32(Val, 12, 1); 1423 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1424 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1425 1426 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1427 1428 if (!add) imm *= -1; 1429 if (imm == 0 && !add) imm = INT32_MIN; 1430 Inst.addOperand(MCOperand::CreateImm(imm)); 1431 1432 return S; 1433 } 1434 1435 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1436 uint64_t Address, const void *Decoder) { 1437 DecodeStatus S = Success; 1438 1439 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1440 unsigned U = fieldFromInstruction32(Val, 8, 1); 1441 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1442 1443 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1444 1445 if (U) 1446 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1447 else 1448 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1449 1450 return S; 1451 } 1452 1453 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1454 uint64_t Address, const void *Decoder) { 1455 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1456 } 1457 1458 static DecodeStatus 1459 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1460 uint64_t Address, const void *Decoder) { 1461 DecodeStatus S = Success; 1462 1463 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1464 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1465 1466 if (pred == 0xF) { 1467 Inst.setOpcode(ARM::BLXi); 1468 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1469 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1470 return S; 1471 } 1472 1473 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1474 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1475 1476 return S; 1477 } 1478 1479 1480 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1481 uint64_t Address, const void *Decoder) { 1482 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1483 return Success; 1484 } 1485 1486 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1487 uint64_t Address, const void *Decoder) { 1488 DecodeStatus S = Success; 1489 1490 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1491 unsigned align = fieldFromInstruction32(Val, 4, 2); 1492 1493 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1494 if (!align) 1495 Inst.addOperand(MCOperand::CreateImm(0)); 1496 else 1497 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1498 1499 return S; 1500 } 1501 1502 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1503 uint64_t Address, const void *Decoder) { 1504 DecodeStatus S = Success; 1505 1506 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1507 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1508 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1509 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1510 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1511 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1512 1513 // First output register 1514 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1515 1516 // Second output register 1517 switch (Inst.getOpcode()) { 1518 case ARM::VLD1q8: 1519 case ARM::VLD1q16: 1520 case ARM::VLD1q32: 1521 case ARM::VLD1q64: 1522 case ARM::VLD1q8_UPD: 1523 case ARM::VLD1q16_UPD: 1524 case ARM::VLD1q32_UPD: 1525 case ARM::VLD1q64_UPD: 1526 case ARM::VLD1d8T: 1527 case ARM::VLD1d16T: 1528 case ARM::VLD1d32T: 1529 case ARM::VLD1d64T: 1530 case ARM::VLD1d8T_UPD: 1531 case ARM::VLD1d16T_UPD: 1532 case ARM::VLD1d32T_UPD: 1533 case ARM::VLD1d64T_UPD: 1534 case ARM::VLD1d8Q: 1535 case ARM::VLD1d16Q: 1536 case ARM::VLD1d32Q: 1537 case ARM::VLD1d64Q: 1538 case ARM::VLD1d8Q_UPD: 1539 case ARM::VLD1d16Q_UPD: 1540 case ARM::VLD1d32Q_UPD: 1541 case ARM::VLD1d64Q_UPD: 1542 case ARM::VLD2d8: 1543 case ARM::VLD2d16: 1544 case ARM::VLD2d32: 1545 case ARM::VLD2d8_UPD: 1546 case ARM::VLD2d16_UPD: 1547 case ARM::VLD2d32_UPD: 1548 case ARM::VLD2q8: 1549 case ARM::VLD2q16: 1550 case ARM::VLD2q32: 1551 case ARM::VLD2q8_UPD: 1552 case ARM::VLD2q16_UPD: 1553 case ARM::VLD2q32_UPD: 1554 case ARM::VLD3d8: 1555 case ARM::VLD3d16: 1556 case ARM::VLD3d32: 1557 case ARM::VLD3d8_UPD: 1558 case ARM::VLD3d16_UPD: 1559 case ARM::VLD3d32_UPD: 1560 case ARM::VLD4d8: 1561 case ARM::VLD4d16: 1562 case ARM::VLD4d32: 1563 case ARM::VLD4d8_UPD: 1564 case ARM::VLD4d16_UPD: 1565 case ARM::VLD4d32_UPD: 1566 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1567 break; 1568 case ARM::VLD2b8: 1569 case ARM::VLD2b16: 1570 case ARM::VLD2b32: 1571 case ARM::VLD2b8_UPD: 1572 case ARM::VLD2b16_UPD: 1573 case ARM::VLD2b32_UPD: 1574 case ARM::VLD3q8: 1575 case ARM::VLD3q16: 1576 case ARM::VLD3q32: 1577 case ARM::VLD3q8_UPD: 1578 case ARM::VLD3q16_UPD: 1579 case ARM::VLD3q32_UPD: 1580 case ARM::VLD4q8: 1581 case ARM::VLD4q16: 1582 case ARM::VLD4q32: 1583 case ARM::VLD4q8_UPD: 1584 case ARM::VLD4q16_UPD: 1585 case ARM::VLD4q32_UPD: 1586 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1587 default: 1588 break; 1589 } 1590 1591 // Third output register 1592 switch(Inst.getOpcode()) { 1593 case ARM::VLD1d8T: 1594 case ARM::VLD1d16T: 1595 case ARM::VLD1d32T: 1596 case ARM::VLD1d64T: 1597 case ARM::VLD1d8T_UPD: 1598 case ARM::VLD1d16T_UPD: 1599 case ARM::VLD1d32T_UPD: 1600 case ARM::VLD1d64T_UPD: 1601 case ARM::VLD1d8Q: 1602 case ARM::VLD1d16Q: 1603 case ARM::VLD1d32Q: 1604 case ARM::VLD1d64Q: 1605 case ARM::VLD1d8Q_UPD: 1606 case ARM::VLD1d16Q_UPD: 1607 case ARM::VLD1d32Q_UPD: 1608 case ARM::VLD1d64Q_UPD: 1609 case ARM::VLD2q8: 1610 case ARM::VLD2q16: 1611 case ARM::VLD2q32: 1612 case ARM::VLD2q8_UPD: 1613 case ARM::VLD2q16_UPD: 1614 case ARM::VLD2q32_UPD: 1615 case ARM::VLD3d8: 1616 case ARM::VLD3d16: 1617 case ARM::VLD3d32: 1618 case ARM::VLD3d8_UPD: 1619 case ARM::VLD3d16_UPD: 1620 case ARM::VLD3d32_UPD: 1621 case ARM::VLD4d8: 1622 case ARM::VLD4d16: 1623 case ARM::VLD4d32: 1624 case ARM::VLD4d8_UPD: 1625 case ARM::VLD4d16_UPD: 1626 case ARM::VLD4d32_UPD: 1627 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1628 break; 1629 case ARM::VLD3q8: 1630 case ARM::VLD3q16: 1631 case ARM::VLD3q32: 1632 case ARM::VLD3q8_UPD: 1633 case ARM::VLD3q16_UPD: 1634 case ARM::VLD3q32_UPD: 1635 case ARM::VLD4q8: 1636 case ARM::VLD4q16: 1637 case ARM::VLD4q32: 1638 case ARM::VLD4q8_UPD: 1639 case ARM::VLD4q16_UPD: 1640 case ARM::VLD4q32_UPD: 1641 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1642 break; 1643 default: 1644 break; 1645 } 1646 1647 // Fourth output register 1648 switch (Inst.getOpcode()) { 1649 case ARM::VLD1d8Q: 1650 case ARM::VLD1d16Q: 1651 case ARM::VLD1d32Q: 1652 case ARM::VLD1d64Q: 1653 case ARM::VLD1d8Q_UPD: 1654 case ARM::VLD1d16Q_UPD: 1655 case ARM::VLD1d32Q_UPD: 1656 case ARM::VLD1d64Q_UPD: 1657 case ARM::VLD2q8: 1658 case ARM::VLD2q16: 1659 case ARM::VLD2q32: 1660 case ARM::VLD2q8_UPD: 1661 case ARM::VLD2q16_UPD: 1662 case ARM::VLD2q32_UPD: 1663 case ARM::VLD4d8: 1664 case ARM::VLD4d16: 1665 case ARM::VLD4d32: 1666 case ARM::VLD4d8_UPD: 1667 case ARM::VLD4d16_UPD: 1668 case ARM::VLD4d32_UPD: 1669 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1670 break; 1671 case ARM::VLD4q8: 1672 case ARM::VLD4q16: 1673 case ARM::VLD4q32: 1674 case ARM::VLD4q8_UPD: 1675 case ARM::VLD4q16_UPD: 1676 case ARM::VLD4q32_UPD: 1677 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1678 break; 1679 default: 1680 break; 1681 } 1682 1683 // Writeback operand 1684 switch (Inst.getOpcode()) { 1685 case ARM::VLD1d8_UPD: 1686 case ARM::VLD1d16_UPD: 1687 case ARM::VLD1d32_UPD: 1688 case ARM::VLD1d64_UPD: 1689 case ARM::VLD1q8_UPD: 1690 case ARM::VLD1q16_UPD: 1691 case ARM::VLD1q32_UPD: 1692 case ARM::VLD1q64_UPD: 1693 case ARM::VLD1d8T_UPD: 1694 case ARM::VLD1d16T_UPD: 1695 case ARM::VLD1d32T_UPD: 1696 case ARM::VLD1d64T_UPD: 1697 case ARM::VLD1d8Q_UPD: 1698 case ARM::VLD1d16Q_UPD: 1699 case ARM::VLD1d32Q_UPD: 1700 case ARM::VLD1d64Q_UPD: 1701 case ARM::VLD2d8_UPD: 1702 case ARM::VLD2d16_UPD: 1703 case ARM::VLD2d32_UPD: 1704 case ARM::VLD2q8_UPD: 1705 case ARM::VLD2q16_UPD: 1706 case ARM::VLD2q32_UPD: 1707 case ARM::VLD2b8_UPD: 1708 case ARM::VLD2b16_UPD: 1709 case ARM::VLD2b32_UPD: 1710 case ARM::VLD3d8_UPD: 1711 case ARM::VLD3d16_UPD: 1712 case ARM::VLD3d32_UPD: 1713 case ARM::VLD3q8_UPD: 1714 case ARM::VLD3q16_UPD: 1715 case ARM::VLD3q32_UPD: 1716 case ARM::VLD4d8_UPD: 1717 case ARM::VLD4d16_UPD: 1718 case ARM::VLD4d32_UPD: 1719 case ARM::VLD4q8_UPD: 1720 case ARM::VLD4q16_UPD: 1721 case ARM::VLD4q32_UPD: 1722 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1723 break; 1724 default: 1725 break; 1726 } 1727 1728 // AddrMode6 Base (register+alignment) 1729 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1730 1731 // AddrMode6 Offset (register) 1732 if (Rm == 0xD) 1733 Inst.addOperand(MCOperand::CreateReg(0)); 1734 else if (Rm != 0xF) { 1735 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1736 } 1737 1738 return S; 1739 } 1740 1741 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1742 uint64_t Address, const void *Decoder) { 1743 DecodeStatus S = Success; 1744 1745 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1746 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1747 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1748 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1749 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1750 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1751 1752 // Writeback Operand 1753 switch (Inst.getOpcode()) { 1754 case ARM::VST1d8_UPD: 1755 case ARM::VST1d16_UPD: 1756 case ARM::VST1d32_UPD: 1757 case ARM::VST1d64_UPD: 1758 case ARM::VST1q8_UPD: 1759 case ARM::VST1q16_UPD: 1760 case ARM::VST1q32_UPD: 1761 case ARM::VST1q64_UPD: 1762 case ARM::VST1d8T_UPD: 1763 case ARM::VST1d16T_UPD: 1764 case ARM::VST1d32T_UPD: 1765 case ARM::VST1d64T_UPD: 1766 case ARM::VST1d8Q_UPD: 1767 case ARM::VST1d16Q_UPD: 1768 case ARM::VST1d32Q_UPD: 1769 case ARM::VST1d64Q_UPD: 1770 case ARM::VST2d8_UPD: 1771 case ARM::VST2d16_UPD: 1772 case ARM::VST2d32_UPD: 1773 case ARM::VST2q8_UPD: 1774 case ARM::VST2q16_UPD: 1775 case ARM::VST2q32_UPD: 1776 case ARM::VST2b8_UPD: 1777 case ARM::VST2b16_UPD: 1778 case ARM::VST2b32_UPD: 1779 case ARM::VST3d8_UPD: 1780 case ARM::VST3d16_UPD: 1781 case ARM::VST3d32_UPD: 1782 case ARM::VST3q8_UPD: 1783 case ARM::VST3q16_UPD: 1784 case ARM::VST3q32_UPD: 1785 case ARM::VST4d8_UPD: 1786 case ARM::VST4d16_UPD: 1787 case ARM::VST4d32_UPD: 1788 case ARM::VST4q8_UPD: 1789 case ARM::VST4q16_UPD: 1790 case ARM::VST4q32_UPD: 1791 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1792 break; 1793 default: 1794 break; 1795 } 1796 1797 // AddrMode6 Base (register+alignment) 1798 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1799 1800 // AddrMode6 Offset (register) 1801 if (Rm == 0xD) 1802 Inst.addOperand(MCOperand::CreateReg(0)); 1803 else if (Rm != 0xF) { 1804 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1805 } 1806 1807 // First input register 1808 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1809 1810 // Second input register 1811 switch (Inst.getOpcode()) { 1812 case ARM::VST1q8: 1813 case ARM::VST1q16: 1814 case ARM::VST1q32: 1815 case ARM::VST1q64: 1816 case ARM::VST1q8_UPD: 1817 case ARM::VST1q16_UPD: 1818 case ARM::VST1q32_UPD: 1819 case ARM::VST1q64_UPD: 1820 case ARM::VST1d8T: 1821 case ARM::VST1d16T: 1822 case ARM::VST1d32T: 1823 case ARM::VST1d64T: 1824 case ARM::VST1d8T_UPD: 1825 case ARM::VST1d16T_UPD: 1826 case ARM::VST1d32T_UPD: 1827 case ARM::VST1d64T_UPD: 1828 case ARM::VST1d8Q: 1829 case ARM::VST1d16Q: 1830 case ARM::VST1d32Q: 1831 case ARM::VST1d64Q: 1832 case ARM::VST1d8Q_UPD: 1833 case ARM::VST1d16Q_UPD: 1834 case ARM::VST1d32Q_UPD: 1835 case ARM::VST1d64Q_UPD: 1836 case ARM::VST2d8: 1837 case ARM::VST2d16: 1838 case ARM::VST2d32: 1839 case ARM::VST2d8_UPD: 1840 case ARM::VST2d16_UPD: 1841 case ARM::VST2d32_UPD: 1842 case ARM::VST2q8: 1843 case ARM::VST2q16: 1844 case ARM::VST2q32: 1845 case ARM::VST2q8_UPD: 1846 case ARM::VST2q16_UPD: 1847 case ARM::VST2q32_UPD: 1848 case ARM::VST3d8: 1849 case ARM::VST3d16: 1850 case ARM::VST3d32: 1851 case ARM::VST3d8_UPD: 1852 case ARM::VST3d16_UPD: 1853 case ARM::VST3d32_UPD: 1854 case ARM::VST4d8: 1855 case ARM::VST4d16: 1856 case ARM::VST4d32: 1857 case ARM::VST4d8_UPD: 1858 case ARM::VST4d16_UPD: 1859 case ARM::VST4d32_UPD: 1860 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1861 break; 1862 case ARM::VST2b8: 1863 case ARM::VST2b16: 1864 case ARM::VST2b32: 1865 case ARM::VST2b8_UPD: 1866 case ARM::VST2b16_UPD: 1867 case ARM::VST2b32_UPD: 1868 case ARM::VST3q8: 1869 case ARM::VST3q16: 1870 case ARM::VST3q32: 1871 case ARM::VST3q8_UPD: 1872 case ARM::VST3q16_UPD: 1873 case ARM::VST3q32_UPD: 1874 case ARM::VST4q8: 1875 case ARM::VST4q16: 1876 case ARM::VST4q32: 1877 case ARM::VST4q8_UPD: 1878 case ARM::VST4q16_UPD: 1879 case ARM::VST4q32_UPD: 1880 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1881 break; 1882 default: 1883 break; 1884 } 1885 1886 // Third input register 1887 switch (Inst.getOpcode()) { 1888 case ARM::VST1d8T: 1889 case ARM::VST1d16T: 1890 case ARM::VST1d32T: 1891 case ARM::VST1d64T: 1892 case ARM::VST1d8T_UPD: 1893 case ARM::VST1d16T_UPD: 1894 case ARM::VST1d32T_UPD: 1895 case ARM::VST1d64T_UPD: 1896 case ARM::VST1d8Q: 1897 case ARM::VST1d16Q: 1898 case ARM::VST1d32Q: 1899 case ARM::VST1d64Q: 1900 case ARM::VST1d8Q_UPD: 1901 case ARM::VST1d16Q_UPD: 1902 case ARM::VST1d32Q_UPD: 1903 case ARM::VST1d64Q_UPD: 1904 case ARM::VST2q8: 1905 case ARM::VST2q16: 1906 case ARM::VST2q32: 1907 case ARM::VST2q8_UPD: 1908 case ARM::VST2q16_UPD: 1909 case ARM::VST2q32_UPD: 1910 case ARM::VST3d8: 1911 case ARM::VST3d16: 1912 case ARM::VST3d32: 1913 case ARM::VST3d8_UPD: 1914 case ARM::VST3d16_UPD: 1915 case ARM::VST3d32_UPD: 1916 case ARM::VST4d8: 1917 case ARM::VST4d16: 1918 case ARM::VST4d32: 1919 case ARM::VST4d8_UPD: 1920 case ARM::VST4d16_UPD: 1921 case ARM::VST4d32_UPD: 1922 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1923 break; 1924 case ARM::VST3q8: 1925 case ARM::VST3q16: 1926 case ARM::VST3q32: 1927 case ARM::VST3q8_UPD: 1928 case ARM::VST3q16_UPD: 1929 case ARM::VST3q32_UPD: 1930 case ARM::VST4q8: 1931 case ARM::VST4q16: 1932 case ARM::VST4q32: 1933 case ARM::VST4q8_UPD: 1934 case ARM::VST4q16_UPD: 1935 case ARM::VST4q32_UPD: 1936 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1937 break; 1938 default: 1939 break; 1940 } 1941 1942 // Fourth input register 1943 switch (Inst.getOpcode()) { 1944 case ARM::VST1d8Q: 1945 case ARM::VST1d16Q: 1946 case ARM::VST1d32Q: 1947 case ARM::VST1d64Q: 1948 case ARM::VST1d8Q_UPD: 1949 case ARM::VST1d16Q_UPD: 1950 case ARM::VST1d32Q_UPD: 1951 case ARM::VST1d64Q_UPD: 1952 case ARM::VST2q8: 1953 case ARM::VST2q16: 1954 case ARM::VST2q32: 1955 case ARM::VST2q8_UPD: 1956 case ARM::VST2q16_UPD: 1957 case ARM::VST2q32_UPD: 1958 case ARM::VST4d8: 1959 case ARM::VST4d16: 1960 case ARM::VST4d32: 1961 case ARM::VST4d8_UPD: 1962 case ARM::VST4d16_UPD: 1963 case ARM::VST4d32_UPD: 1964 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1965 break; 1966 case ARM::VST4q8: 1967 case ARM::VST4q16: 1968 case ARM::VST4q32: 1969 case ARM::VST4q8_UPD: 1970 case ARM::VST4q16_UPD: 1971 case ARM::VST4q32_UPD: 1972 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1973 break; 1974 default: 1975 break; 1976 } 1977 1978 return S; 1979 } 1980 1981 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1982 uint64_t Address, const void *Decoder) { 1983 DecodeStatus S = Success; 1984 1985 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1986 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1987 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1988 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1989 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1990 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1991 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1992 1993 align *= (1 << size); 1994 1995 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1996 if (regs == 2) { 1997 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1998 } 1999 if (Rm != 0xF) { 2000 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2001 } 2002 2003 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2004 Inst.addOperand(MCOperand::CreateImm(align)); 2005 2006 if (Rm == 0xD) 2007 Inst.addOperand(MCOperand::CreateReg(0)); 2008 else if (Rm != 0xF) { 2009 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2010 } 2011 2012 return S; 2013 } 2014 2015 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2016 uint64_t Address, const void *Decoder) { 2017 DecodeStatus S = Success; 2018 2019 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2020 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2021 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2022 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2023 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2024 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2025 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2026 align *= 2*size; 2027 2028 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2029 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2030 if (Rm != 0xF) { 2031 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2032 } 2033 2034 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2035 Inst.addOperand(MCOperand::CreateImm(align)); 2036 2037 if (Rm == 0xD) 2038 Inst.addOperand(MCOperand::CreateReg(0)); 2039 else if (Rm != 0xF) { 2040 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2041 } 2042 2043 return S; 2044 } 2045 2046 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2047 uint64_t Address, const void *Decoder) { 2048 DecodeStatus S = Success; 2049 2050 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2051 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2052 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2053 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2054 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2055 2056 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2057 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2058 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2059 if (Rm != 0xF) { 2060 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2061 } 2062 2063 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2064 Inst.addOperand(MCOperand::CreateImm(0)); 2065 2066 if (Rm == 0xD) 2067 Inst.addOperand(MCOperand::CreateReg(0)); 2068 else if (Rm != 0xF) { 2069 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2070 } 2071 2072 return S; 2073 } 2074 2075 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2076 uint64_t Address, const void *Decoder) { 2077 DecodeStatus S = Success; 2078 2079 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2080 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2081 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2082 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2083 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2084 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2085 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2086 2087 if (size == 0x3) { 2088 size = 4; 2089 align = 16; 2090 } else { 2091 if (size == 2) { 2092 size = 1 << size; 2093 align *= 8; 2094 } else { 2095 size = 1 << size; 2096 align *= 4*size; 2097 } 2098 } 2099 2100 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2101 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2102 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2103 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); 2104 if (Rm != 0xF) { 2105 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2106 } 2107 2108 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2109 Inst.addOperand(MCOperand::CreateImm(align)); 2110 2111 if (Rm == 0xD) 2112 Inst.addOperand(MCOperand::CreateReg(0)); 2113 else if (Rm != 0xF) { 2114 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2115 } 2116 2117 return S; 2118 } 2119 2120 static DecodeStatus 2121 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2122 uint64_t Address, const void *Decoder) { 2123 DecodeStatus S = Success; 2124 2125 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2126 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2127 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2128 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2129 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2130 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2131 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2132 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2133 2134 if (Q) { 2135 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2136 } else { 2137 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2138 } 2139 2140 Inst.addOperand(MCOperand::CreateImm(imm)); 2141 2142 switch (Inst.getOpcode()) { 2143 case ARM::VORRiv4i16: 2144 case ARM::VORRiv2i32: 2145 case ARM::VBICiv4i16: 2146 case ARM::VBICiv2i32: 2147 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2148 break; 2149 case ARM::VORRiv8i16: 2150 case ARM::VORRiv4i32: 2151 case ARM::VBICiv8i16: 2152 case ARM::VBICiv4i32: 2153 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2154 break; 2155 default: 2156 break; 2157 } 2158 2159 return S; 2160 } 2161 2162 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2163 uint64_t Address, const void *Decoder) { 2164 DecodeStatus S = Success; 2165 2166 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2167 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2168 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2169 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2170 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2171 2172 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2173 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2174 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2175 2176 return S; 2177 } 2178 2179 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2180 uint64_t Address, const void *Decoder) { 2181 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2182 return Success; 2183 } 2184 2185 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2186 uint64_t Address, const void *Decoder) { 2187 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2188 return Success; 2189 } 2190 2191 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2192 uint64_t Address, const void *Decoder) { 2193 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2194 return Success; 2195 } 2196 2197 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2198 uint64_t Address, const void *Decoder) { 2199 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2200 return Success; 2201 } 2202 2203 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2204 uint64_t Address, const void *Decoder) { 2205 DecodeStatus S = Success; 2206 2207 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2208 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2209 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2210 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2211 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2212 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2213 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2214 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2215 2216 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2217 if (op) { 2218 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback 2219 } 2220 2221 for (unsigned i = 0; i < length; ++i) { 2222 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)); 2223 } 2224 2225 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2226 2227 return S; 2228 } 2229 2230 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2231 uint64_t Address, const void *Decoder) { 2232 // The immediate needs to be a fully instantiated float. However, the 2233 // auto-generated decoder is only able to fill in some of the bits 2234 // necessary. For instance, the 'b' bit is replicated multiple times, 2235 // and is even present in inverted form in one bit. We do a little 2236 // binary parsing here to fill in those missing bits, and then 2237 // reinterpret it all as a float. 2238 union { 2239 uint32_t integer; 2240 float fp; 2241 } fp_conv; 2242 2243 fp_conv.integer = Val; 2244 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2245 fp_conv.integer |= b << 26; 2246 fp_conv.integer |= b << 27; 2247 fp_conv.integer |= b << 28; 2248 fp_conv.integer |= b << 29; 2249 fp_conv.integer |= (~b & 0x1) << 30; 2250 2251 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2252 return Success; 2253 } 2254 2255 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2256 uint64_t Address, const void *Decoder) { 2257 DecodeStatus S = Success; 2258 2259 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2260 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2261 2262 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); 2263 2264 if (Inst.getOpcode() == ARM::tADR) 2265 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2266 else if (Inst.getOpcode() == ARM::tADDrSPi) 2267 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2268 else 2269 return Fail; 2270 2271 Inst.addOperand(MCOperand::CreateImm(imm)); 2272 return S; 2273 } 2274 2275 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2276 uint64_t Address, const void *Decoder) { 2277 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2278 return Success; 2279 } 2280 2281 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2282 uint64_t Address, const void *Decoder) { 2283 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2284 return Success; 2285 } 2286 2287 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2288 uint64_t Address, const void *Decoder) { 2289 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2290 return Success; 2291 } 2292 2293 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2294 uint64_t Address, const void *Decoder) { 2295 DecodeStatus S = Success; 2296 2297 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2298 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2299 2300 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2301 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); 2302 2303 return S; 2304 } 2305 2306 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2307 uint64_t Address, const void *Decoder) { 2308 DecodeStatus S = Success; 2309 2310 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2311 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2312 2313 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2314 Inst.addOperand(MCOperand::CreateImm(imm)); 2315 2316 return S; 2317 } 2318 2319 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2320 uint64_t Address, const void *Decoder) { 2321 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2322 2323 return Success; 2324 } 2325 2326 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2327 uint64_t Address, const void *Decoder) { 2328 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2329 Inst.addOperand(MCOperand::CreateImm(Val)); 2330 2331 return Success; 2332 } 2333 2334 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2335 uint64_t Address, const void *Decoder) { 2336 DecodeStatus S = Success; 2337 2338 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2339 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2340 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2341 2342 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2343 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); 2344 Inst.addOperand(MCOperand::CreateImm(imm)); 2345 2346 return S; 2347 } 2348 2349 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2350 uint64_t Address, const void *Decoder) { 2351 DecodeStatus S = Success; 2352 2353 if (Inst.getOpcode() != ARM::t2PLDs) { 2354 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2355 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2356 } 2357 2358 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2359 if (Rn == 0xF) { 2360 switch (Inst.getOpcode()) { 2361 case ARM::t2LDRBs: 2362 Inst.setOpcode(ARM::t2LDRBpci); 2363 break; 2364 case ARM::t2LDRHs: 2365 Inst.setOpcode(ARM::t2LDRHpci); 2366 break; 2367 case ARM::t2LDRSHs: 2368 Inst.setOpcode(ARM::t2LDRSHpci); 2369 break; 2370 case ARM::t2LDRSBs: 2371 Inst.setOpcode(ARM::t2LDRSBpci); 2372 break; 2373 case ARM::t2PLDs: 2374 Inst.setOpcode(ARM::t2PLDi12); 2375 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2376 break; 2377 default: 2378 return Fail; 2379 } 2380 2381 int imm = fieldFromInstruction32(Insn, 0, 12); 2382 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2383 Inst.addOperand(MCOperand::CreateImm(imm)); 2384 2385 return S; 2386 } 2387 2388 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2389 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2390 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2391 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); 2392 2393 return S; 2394 } 2395 2396 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2397 uint64_t Address, const void *Decoder) { 2398 int imm = Val & 0xFF; 2399 if (!(Val & 0x100)) imm *= -1; 2400 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2401 2402 return Success; 2403 } 2404 2405 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2406 uint64_t Address, const void *Decoder) { 2407 DecodeStatus S = Success; 2408 2409 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2410 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2411 2412 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2413 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); 2414 2415 return S; 2416 } 2417 2418 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2419 uint64_t Address, const void *Decoder) { 2420 int imm = Val & 0xFF; 2421 if (!(Val & 0x100)) imm *= -1; 2422 Inst.addOperand(MCOperand::CreateImm(imm)); 2423 2424 return Success; 2425 } 2426 2427 2428 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2429 uint64_t Address, const void *Decoder) { 2430 DecodeStatus S = Success; 2431 2432 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2433 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2434 2435 // Some instructions always use an additive offset. 2436 switch (Inst.getOpcode()) { 2437 case ARM::t2LDRT: 2438 case ARM::t2LDRBT: 2439 case ARM::t2LDRHT: 2440 case ARM::t2LDRSBT: 2441 case ARM::t2LDRSHT: 2442 imm |= 0x100; 2443 break; 2444 default: 2445 break; 2446 } 2447 2448 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2449 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); 2450 2451 return S; 2452 } 2453 2454 2455 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2456 uint64_t Address, const void *Decoder) { 2457 DecodeStatus S = Success; 2458 2459 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2460 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2461 2462 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2463 Inst.addOperand(MCOperand::CreateImm(imm)); 2464 2465 return S; 2466 } 2467 2468 2469 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2470 uint64_t Address, const void *Decoder) { 2471 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2472 2473 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2474 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2475 Inst.addOperand(MCOperand::CreateImm(imm)); 2476 2477 return Success; 2478 } 2479 2480 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2481 uint64_t Address, const void *Decoder) { 2482 DecodeStatus S = Success; 2483 2484 if (Inst.getOpcode() == ARM::tADDrSP) { 2485 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2486 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2487 2488 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2489 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2490 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2491 } else if (Inst.getOpcode() == ARM::tADDspr) { 2492 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2493 2494 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2495 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2496 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2497 } 2498 2499 return S; 2500 } 2501 2502 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2503 uint64_t Address, const void *Decoder) { 2504 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2505 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2506 2507 Inst.addOperand(MCOperand::CreateImm(imod)); 2508 Inst.addOperand(MCOperand::CreateImm(flags)); 2509 2510 return Success; 2511 } 2512 2513 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2514 uint64_t Address, const void *Decoder) { 2515 DecodeStatus S = Success; 2516 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2517 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2518 2519 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; 2520 Inst.addOperand(MCOperand::CreateImm(add)); 2521 2522 return S; 2523 } 2524 2525 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2526 uint64_t Address, const void *Decoder) { 2527 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2528 return Success; 2529 } 2530 2531 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2532 uint64_t Address, const void *Decoder) { 2533 if (Val == 0xA || Val == 0xB) 2534 return Fail; 2535 2536 Inst.addOperand(MCOperand::CreateImm(Val)); 2537 return Success; 2538 } 2539 2540 static DecodeStatus 2541 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2542 uint64_t Address, const void *Decoder) { 2543 DecodeStatus S = Success; 2544 2545 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2546 if (pred == 0xE || pred == 0xF) { 2547 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2548 switch (opc) { 2549 default: 2550 return Fail; 2551 case 0: 2552 Inst.setOpcode(ARM::t2DSB); 2553 break; 2554 case 1: 2555 Inst.setOpcode(ARM::t2DMB); 2556 break; 2557 case 2: 2558 Inst.setOpcode(ARM::t2ISB); 2559 return Success; 2560 } 2561 2562 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2563 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2564 } 2565 2566 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2567 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2568 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2569 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2570 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2571 2572 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); 2573 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2574 2575 return S; 2576 } 2577 2578 // Decode a shifted immediate operand. These basically consist 2579 // of an 8-bit value, and a 4-bit directive that specifies either 2580 // a splat operation or a rotation. 2581 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2582 uint64_t Address, const void *Decoder) { 2583 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2584 if (ctrl == 0) { 2585 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2586 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2587 switch (byte) { 2588 case 0: 2589 Inst.addOperand(MCOperand::CreateImm(imm)); 2590 break; 2591 case 1: 2592 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2593 break; 2594 case 2: 2595 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2596 break; 2597 case 3: 2598 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2599 (imm << 8) | imm)); 2600 break; 2601 } 2602 } else { 2603 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2604 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2605 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2606 Inst.addOperand(MCOperand::CreateImm(imm)); 2607 } 2608 2609 return Success; 2610 } 2611 2612 static DecodeStatus 2613 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2614 uint64_t Address, const void *Decoder){ 2615 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2616 return Success; 2617 } 2618 2619 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2620 uint64_t Address, const void *Decoder){ 2621 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2622 return Success; 2623 } 2624 2625 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2626 uint64_t Address, const void *Decoder) { 2627 switch (Val) { 2628 default: 2629 return Fail; 2630 case 0xF: // SY 2631 case 0xE: // ST 2632 case 0xB: // ISH 2633 case 0xA: // ISHST 2634 case 0x7: // NSH 2635 case 0x6: // NSHST 2636 case 0x3: // OSH 2637 case 0x2: // OSHST 2638 break; 2639 } 2640 2641 Inst.addOperand(MCOperand::CreateImm(Val)); 2642 return Success; 2643 } 2644 2645 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2646 uint64_t Address, const void *Decoder) { 2647 if (!Val) return Fail; 2648 Inst.addOperand(MCOperand::CreateImm(Val)); 2649 return Success; 2650 } 2651 2652 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2653 uint64_t Address, const void *Decoder) { 2654 DecodeStatus S = Success; 2655 2656 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2657 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2658 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2659 2660 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2661 2662 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2663 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2664 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2665 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2666 2667 return S; 2668 } 2669 2670 2671 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2672 uint64_t Address, const void *Decoder){ 2673 DecodeStatus S = Success; 2674 2675 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2676 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2677 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2678 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2679 2680 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); 2681 2682 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2683 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; 2684 2685 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2686 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2687 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2688 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2689 2690 return S; 2691 } 2692 2693 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2694 uint64_t Address, const void *Decoder) { 2695 DecodeStatus S = Success; 2696 2697 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2698 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2699 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2700 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2701 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2702 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2703 2704 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2705 2706 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2707 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2708 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); 2709 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2710 2711 return S; 2712 } 2713 2714 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2715 uint64_t Address, const void *Decoder) { 2716 DecodeStatus S = Success; 2717 2718 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2719 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2720 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2721 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2722 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2723 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2724 2725 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2726 2727 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2728 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2729 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); 2730 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2731 2732 return S; 2733 } 2734 2735 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2736 uint64_t Address, const void *Decoder) { 2737 DecodeStatus S = Success; 2738 2739 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2740 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2741 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2742 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2743 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2744 2745 unsigned align = 0; 2746 unsigned index = 0; 2747 switch (size) { 2748 default: 2749 return Fail; 2750 case 0: 2751 if (fieldFromInstruction32(Insn, 4, 1)) 2752 return Fail; // UNDEFINED 2753 index = fieldFromInstruction32(Insn, 5, 3); 2754 break; 2755 case 1: 2756 if (fieldFromInstruction32(Insn, 5, 1)) 2757 return Fail; // UNDEFINED 2758 index = fieldFromInstruction32(Insn, 6, 2); 2759 if (fieldFromInstruction32(Insn, 4, 1)) 2760 align = 2; 2761 break; 2762 case 2: 2763 if (fieldFromInstruction32(Insn, 6, 1)) 2764 return Fail; // UNDEFINED 2765 index = fieldFromInstruction32(Insn, 7, 1); 2766 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2767 align = 4; 2768 } 2769 2770 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2771 if (Rm != 0xF) { // Writeback 2772 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2773 } 2774 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2775 Inst.addOperand(MCOperand::CreateImm(align)); 2776 if (Rm != 0xF) { 2777 if (Rm != 0xD) 2778 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2779 else 2780 Inst.addOperand(MCOperand::CreateReg(0)); 2781 } 2782 2783 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2784 Inst.addOperand(MCOperand::CreateImm(index)); 2785 2786 return S; 2787 } 2788 2789 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2790 uint64_t Address, const void *Decoder) { 2791 DecodeStatus S = Success; 2792 2793 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2794 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2795 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2796 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2797 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2798 2799 unsigned align = 0; 2800 unsigned index = 0; 2801 switch (size) { 2802 default: 2803 return Fail; 2804 case 0: 2805 if (fieldFromInstruction32(Insn, 4, 1)) 2806 return Fail; // UNDEFINED 2807 index = fieldFromInstruction32(Insn, 5, 3); 2808 break; 2809 case 1: 2810 if (fieldFromInstruction32(Insn, 5, 1)) 2811 return Fail; // UNDEFINED 2812 index = fieldFromInstruction32(Insn, 6, 2); 2813 if (fieldFromInstruction32(Insn, 4, 1)) 2814 align = 2; 2815 break; 2816 case 2: 2817 if (fieldFromInstruction32(Insn, 6, 1)) 2818 return Fail; // UNDEFINED 2819 index = fieldFromInstruction32(Insn, 7, 1); 2820 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2821 align = 4; 2822 } 2823 2824 if (Rm != 0xF) { // Writeback 2825 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2826 } 2827 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2828 Inst.addOperand(MCOperand::CreateImm(align)); 2829 if (Rm != 0xF) { 2830 if (Rm != 0xD) 2831 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2832 else 2833 Inst.addOperand(MCOperand::CreateReg(0)); 2834 } 2835 2836 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2837 Inst.addOperand(MCOperand::CreateImm(index)); 2838 2839 return S; 2840 } 2841 2842 2843 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2844 uint64_t Address, const void *Decoder) { 2845 DecodeStatus S = Success; 2846 2847 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2848 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2849 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2850 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2851 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2852 2853 unsigned align = 0; 2854 unsigned index = 0; 2855 unsigned inc = 1; 2856 switch (size) { 2857 default: 2858 return Fail; 2859 case 0: 2860 index = fieldFromInstruction32(Insn, 5, 3); 2861 if (fieldFromInstruction32(Insn, 4, 1)) 2862 align = 2; 2863 break; 2864 case 1: 2865 index = fieldFromInstruction32(Insn, 6, 2); 2866 if (fieldFromInstruction32(Insn, 4, 1)) 2867 align = 4; 2868 if (fieldFromInstruction32(Insn, 5, 1)) 2869 inc = 2; 2870 break; 2871 case 2: 2872 if (fieldFromInstruction32(Insn, 5, 1)) 2873 return Fail; // UNDEFINED 2874 index = fieldFromInstruction32(Insn, 7, 1); 2875 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2876 align = 8; 2877 if (fieldFromInstruction32(Insn, 6, 1)) 2878 inc = 2; 2879 break; 2880 } 2881 2882 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2883 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2884 if (Rm != 0xF) { // Writeback 2885 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2886 } 2887 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2888 Inst.addOperand(MCOperand::CreateImm(align)); 2889 if (Rm != 0xF) { 2890 if (Rm != 0xD) 2891 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2892 else 2893 Inst.addOperand(MCOperand::CreateReg(0)); 2894 } 2895 2896 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2897 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2898 Inst.addOperand(MCOperand::CreateImm(index)); 2899 2900 return S; 2901 } 2902 2903 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2904 uint64_t Address, const void *Decoder) { 2905 DecodeStatus S = Success; 2906 2907 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2908 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2909 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2910 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2911 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2912 2913 unsigned align = 0; 2914 unsigned index = 0; 2915 unsigned inc = 1; 2916 switch (size) { 2917 default: 2918 return Fail; 2919 case 0: 2920 index = fieldFromInstruction32(Insn, 5, 3); 2921 if (fieldFromInstruction32(Insn, 4, 1)) 2922 align = 2; 2923 break; 2924 case 1: 2925 index = fieldFromInstruction32(Insn, 6, 2); 2926 if (fieldFromInstruction32(Insn, 4, 1)) 2927 align = 4; 2928 if (fieldFromInstruction32(Insn, 5, 1)) 2929 inc = 2; 2930 break; 2931 case 2: 2932 if (fieldFromInstruction32(Insn, 5, 1)) 2933 return Fail; // UNDEFINED 2934 index = fieldFromInstruction32(Insn, 7, 1); 2935 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2936 align = 8; 2937 if (fieldFromInstruction32(Insn, 6, 1)) 2938 inc = 2; 2939 break; 2940 } 2941 2942 if (Rm != 0xF) { // Writeback 2943 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2944 } 2945 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2946 Inst.addOperand(MCOperand::CreateImm(align)); 2947 if (Rm != 0xF) { 2948 if (Rm != 0xD) 2949 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2950 else 2951 Inst.addOperand(MCOperand::CreateReg(0)); 2952 } 2953 2954 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2955 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2956 Inst.addOperand(MCOperand::CreateImm(index)); 2957 2958 return S; 2959 } 2960 2961 2962 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 2963 uint64_t Address, const void *Decoder) { 2964 DecodeStatus S = Success; 2965 2966 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2967 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2968 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2969 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2970 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2971 2972 unsigned align = 0; 2973 unsigned index = 0; 2974 unsigned inc = 1; 2975 switch (size) { 2976 default: 2977 return Fail; 2978 case 0: 2979 if (fieldFromInstruction32(Insn, 4, 1)) 2980 return Fail; // UNDEFINED 2981 index = fieldFromInstruction32(Insn, 5, 3); 2982 break; 2983 case 1: 2984 if (fieldFromInstruction32(Insn, 4, 1)) 2985 return Fail; // UNDEFINED 2986 index = fieldFromInstruction32(Insn, 6, 2); 2987 if (fieldFromInstruction32(Insn, 5, 1)) 2988 inc = 2; 2989 break; 2990 case 2: 2991 if (fieldFromInstruction32(Insn, 4, 2)) 2992 return Fail; // UNDEFINED 2993 index = fieldFromInstruction32(Insn, 7, 1); 2994 if (fieldFromInstruction32(Insn, 6, 1)) 2995 inc = 2; 2996 break; 2997 } 2998 2999 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3000 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3001 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3002 3003 if (Rm != 0xF) { // Writeback 3004 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3005 } 3006 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3007 Inst.addOperand(MCOperand::CreateImm(align)); 3008 if (Rm != 0xF) { 3009 if (Rm != 0xD) 3010 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3011 else 3012 Inst.addOperand(MCOperand::CreateReg(0)); 3013 } 3014 3015 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3016 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3017 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3018 Inst.addOperand(MCOperand::CreateImm(index)); 3019 3020 return S; 3021 } 3022 3023 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3024 uint64_t Address, const void *Decoder) { 3025 DecodeStatus S = Success; 3026 3027 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3028 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3029 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3030 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3031 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3032 3033 unsigned align = 0; 3034 unsigned index = 0; 3035 unsigned inc = 1; 3036 switch (size) { 3037 default: 3038 return Fail; 3039 case 0: 3040 if (fieldFromInstruction32(Insn, 4, 1)) 3041 return Fail; // UNDEFINED 3042 index = fieldFromInstruction32(Insn, 5, 3); 3043 break; 3044 case 1: 3045 if (fieldFromInstruction32(Insn, 4, 1)) 3046 return Fail; // UNDEFINED 3047 index = fieldFromInstruction32(Insn, 6, 2); 3048 if (fieldFromInstruction32(Insn, 5, 1)) 3049 inc = 2; 3050 break; 3051 case 2: 3052 if (fieldFromInstruction32(Insn, 4, 2)) 3053 return Fail; // UNDEFINED 3054 index = fieldFromInstruction32(Insn, 7, 1); 3055 if (fieldFromInstruction32(Insn, 6, 1)) 3056 inc = 2; 3057 break; 3058 } 3059 3060 if (Rm != 0xF) { // Writeback 3061 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3062 } 3063 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3064 Inst.addOperand(MCOperand::CreateImm(align)); 3065 if (Rm != 0xF) { 3066 if (Rm != 0xD) 3067 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3068 else 3069 Inst.addOperand(MCOperand::CreateReg(0)); 3070 } 3071 3072 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3073 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3074 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3075 Inst.addOperand(MCOperand::CreateImm(index)); 3076 3077 return S; 3078 } 3079 3080 3081 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3082 uint64_t Address, const void *Decoder) { 3083 DecodeStatus S = Success; 3084 3085 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3086 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3087 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3088 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3089 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3090 3091 unsigned align = 0; 3092 unsigned index = 0; 3093 unsigned inc = 1; 3094 switch (size) { 3095 default: 3096 return Fail; 3097 case 0: 3098 if (fieldFromInstruction32(Insn, 4, 1)) 3099 align = 4; 3100 index = fieldFromInstruction32(Insn, 5, 3); 3101 break; 3102 case 1: 3103 if (fieldFromInstruction32(Insn, 4, 1)) 3104 align = 8; 3105 index = fieldFromInstruction32(Insn, 6, 2); 3106 if (fieldFromInstruction32(Insn, 5, 1)) 3107 inc = 2; 3108 break; 3109 case 2: 3110 if (fieldFromInstruction32(Insn, 4, 2)) 3111 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3112 index = fieldFromInstruction32(Insn, 7, 1); 3113 if (fieldFromInstruction32(Insn, 6, 1)) 3114 inc = 2; 3115 break; 3116 } 3117 3118 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3119 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3120 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3121 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3122 3123 if (Rm != 0xF) { // Writeback 3124 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3125 } 3126 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3127 Inst.addOperand(MCOperand::CreateImm(align)); 3128 if (Rm != 0xF) { 3129 if (Rm != 0xD) 3130 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3131 else 3132 Inst.addOperand(MCOperand::CreateReg(0)); 3133 } 3134 3135 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3136 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3137 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3138 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3139 Inst.addOperand(MCOperand::CreateImm(index)); 3140 3141 return S; 3142 } 3143 3144 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3145 uint64_t Address, const void *Decoder) { 3146 DecodeStatus S = Success; 3147 3148 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3149 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3150 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3151 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3152 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3153 3154 unsigned align = 0; 3155 unsigned index = 0; 3156 unsigned inc = 1; 3157 switch (size) { 3158 default: 3159 return Fail; 3160 case 0: 3161 if (fieldFromInstruction32(Insn, 4, 1)) 3162 align = 4; 3163 index = fieldFromInstruction32(Insn, 5, 3); 3164 break; 3165 case 1: 3166 if (fieldFromInstruction32(Insn, 4, 1)) 3167 align = 8; 3168 index = fieldFromInstruction32(Insn, 6, 2); 3169 if (fieldFromInstruction32(Insn, 5, 1)) 3170 inc = 2; 3171 break; 3172 case 2: 3173 if (fieldFromInstruction32(Insn, 4, 2)) 3174 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3175 index = fieldFromInstruction32(Insn, 7, 1); 3176 if (fieldFromInstruction32(Insn, 6, 1)) 3177 inc = 2; 3178 break; 3179 } 3180 3181 if (Rm != 0xF) { // Writeback 3182 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3183 } 3184 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3185 Inst.addOperand(MCOperand::CreateImm(align)); 3186 if (Rm != 0xF) { 3187 if (Rm != 0xD) 3188 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3189 else 3190 Inst.addOperand(MCOperand::CreateReg(0)); 3191 } 3192 3193 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3194 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3195 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3196 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3197 Inst.addOperand(MCOperand::CreateImm(index)); 3198 3199 return S; 3200 } 3201 3202 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3203 uint64_t Address, const void *Decoder) { 3204 DecodeStatus S = Success; 3205 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3206 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3207 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3208 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3209 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3210 3211 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3212 CHECK(S, Unpredictable); 3213 3214 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)); 3215 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)); 3216 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)); 3217 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)); 3218 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 3219 3220 return S; 3221 } 3222 3223 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3224 uint64_t Address, const void *Decoder) { 3225 DecodeStatus S = Success; 3226 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3227 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3228 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3229 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3230 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3231 3232 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3233 CHECK(S, Unpredictable); 3234 3235 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)); 3236 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)); 3237 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)); 3238 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)); 3239 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 3240 3241 return S; 3242 } 3243