1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &VStream, 141 raw_ostream &CStream) const override; 142 143 private: 144 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 145 ArrayRef<uint8_t> Bytes, uint64_t Address, 146 raw_ostream &VStream, 147 raw_ostream &CStream) const; 148 149 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 150 ArrayRef<uint8_t> Bytes, uint64_t Address, 151 raw_ostream &VStream, 152 raw_ostream &CStream) const; 153 154 mutable ITStatus ITBlock; 155 mutable VPTStatus VPTBlock; 156 157 DecodeStatus AddThumbPredicate(MCInst&) const; 158 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 159 }; 160 161 } // end anonymous namespace 162 163 static bool Check(DecodeStatus &Out, DecodeStatus In) { 164 switch (In) { 165 case MCDisassembler::Success: 166 // Out stays the same. 167 return true; 168 case MCDisassembler::SoftFail: 169 Out = In; 170 return true; 171 case MCDisassembler::Fail: 172 Out = In; 173 return false; 174 } 175 llvm_unreachable("Invalid DecodeStatus!"); 176 } 177 178 // Forward declare these because the autogenerated code will reference them. 179 // Definitions are further down. 180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 216 unsigned RegNo, 217 uint64_t Address, 218 const void *Decoder); 219 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 226 unsigned RegNo, uint64_t Address, 227 const void *Decoder); 228 229 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 240 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 245 unsigned Insn, 246 uint64_t Address, 247 const void *Decoder); 248 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 257 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 258 unsigned Insn, 259 uint64_t Adddress, 260 const void *Decoder); 261 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 376 unsigned Val, 377 uint64_t Address, 378 const void *Decoder); 379 380 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 401 uint64_t Address, const void* Decoder); 402 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 403 uint64_t Address, const void* Decoder); 404 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 405 uint64_t Address, const void* Decoder); 406 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 407 uint64_t Address, const void* Decoder); 408 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 415 uint64_t Address, 416 const void *Decoder); 417 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 418 uint64_t Address, const void *Decoder); 419 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 420 uint64_t Address, const void *Decoder); 421 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 422 uint64_t Address, const void *Decoder); 423 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 424 uint64_t Address, const void *Decoder); 425 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 426 uint64_t Address, const void *Decoder); 427 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 428 uint64_t Address, const void *Decoder); 429 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 430 uint64_t Address, const void *Decoder); 431 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 432 uint64_t Address, const void *Decoder); 433 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 434 uint64_t Address, const void *Decoder); 435 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 436 uint64_t Address, const void *Decoder); 437 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 438 uint64_t Address, const void *Decoder); 439 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 440 uint64_t Address, const void *Decoder); 441 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 442 uint64_t Address, const void *Decoder); 443 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 444 uint64_t Address, const void *Decoder); 445 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 446 uint64_t Address, const void *Decoder); 447 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 448 uint64_t Address, const void *Decoder); 449 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 450 uint64_t Address, const void *Decoder); 451 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 452 uint64_t Address, const void *Decoder); 453 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 454 uint64_t Address, const void *Decoder); 455 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 456 uint64_t Address, const void *Decoder); 457 458 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 459 uint64_t Address, const void *Decoder); 460 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 461 uint64_t Address, const void *Decoder); 462 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 463 uint64_t Address, const void *Decoder); 464 465 template <bool isSigned, bool isNeg, int size> 466 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 467 uint64_t Address, const void *Decoder); 468 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 469 uint64_t Address, 470 const void *Decoder); 471 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 472 uint64_t Address, 473 const void *Decoder); 474 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 475 const void *Decoder); 476 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 477 uint64_t Address, 478 const void *Decoder); 479 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 480 const void *Decoder); 481 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 482 uint64_t Address, const void *Decoder); 483 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 484 uint64_t Address, const void *Decoder); 485 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 486 uint64_t Address, 487 const void *Decoder); 488 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 489 uint64_t Address, 490 const void *Decoder); 491 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 492 uint64_t Address, 493 const void *Decoder); 494 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 495 unsigned Val, 496 uint64_t Address, 497 const void *Decoder); 498 template<bool Writeback> 499 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 500 uint64_t Address, 501 const void *Decoder); 502 template <int shift> 503 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 504 uint64_t Address, 505 const void *Decoder); 506 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 507 uint64_t Address, 508 const void *Decoder); 509 #include "ARMGenDisassemblerTables.inc" 510 511 static MCDisassembler *createARMDisassembler(const Target &T, 512 const MCSubtargetInfo &STI, 513 MCContext &Ctx) { 514 return new ARMDisassembler(STI, Ctx); 515 } 516 517 // Post-decoding checks 518 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 519 uint64_t Address, raw_ostream &OS, 520 raw_ostream &CS, 521 uint32_t Insn, 522 DecodeStatus Result) { 523 switch (MI.getOpcode()) { 524 case ARM::HVC: { 525 // HVC is undefined if condition = 0xf otherwise upredictable 526 // if condition != 0xe 527 uint32_t Cond = (Insn >> 28) & 0xF; 528 if (Cond == 0xF) 529 return MCDisassembler::Fail; 530 if (Cond != 0xE) 531 return MCDisassembler::SoftFail; 532 return Result; 533 } 534 case ARM::t2ADDri: 535 case ARM::t2ADDri12: 536 case ARM::t2ADDrr: 537 case ARM::t2ADDrs: 538 case ARM::t2SUBri: 539 case ARM::t2SUBri12: 540 case ARM::t2SUBrr: 541 case ARM::t2SUBrs: 542 if (MI.getOperand(0).getReg() == ARM::SP && 543 MI.getOperand(1).getReg() != ARM::SP) 544 return MCDisassembler::SoftFail; 545 return Result; 546 default: return Result; 547 } 548 } 549 550 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 551 ArrayRef<uint8_t> Bytes, 552 uint64_t Address, raw_ostream &OS, 553 raw_ostream &CS) const { 554 if (STI.getFeatureBits()[ARM::ModeThumb]) 555 return getThumbInstruction(MI, Size, Bytes, Address, OS, CS); 556 return getARMInstruction(MI, Size, Bytes, Address, OS, CS); 557 } 558 559 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 560 ArrayRef<uint8_t> Bytes, 561 uint64_t Address, 562 raw_ostream &OS, 563 raw_ostream &CS) const { 564 CommentStream = &CS; 565 566 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 567 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 568 "mode!"); 569 570 // We want to read exactly 4 bytes of data. 571 if (Bytes.size() < 4) { 572 Size = 0; 573 return MCDisassembler::Fail; 574 } 575 576 // Encoded as a small-endian 32-bit word in the stream. 577 uint32_t Insn = 578 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 579 580 // Calling the auto-generated decoder function. 581 DecodeStatus Result = 582 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 583 if (Result != MCDisassembler::Fail) { 584 Size = 4; 585 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 586 } 587 588 struct DecodeTable { 589 const uint8_t *P; 590 bool DecodePred; 591 }; 592 593 const DecodeTable Tables[] = { 594 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 595 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 596 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 597 {DecoderTablev8Crypto32, false}, 598 }; 599 600 for (auto Table : Tables) { 601 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 602 if (Result != MCDisassembler::Fail) { 603 Size = 4; 604 // Add a fake predicate operand, because we share these instruction 605 // definitions with Thumb2 where these instructions are predicable. 606 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 607 return MCDisassembler::Fail; 608 return Result; 609 } 610 } 611 612 Result = 613 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 614 if (Result != MCDisassembler::Fail) { 615 Size = 4; 616 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 617 } 618 619 Size = 4; 620 return MCDisassembler::Fail; 621 } 622 623 namespace llvm { 624 625 extern const MCInstrDesc ARMInsts[]; 626 627 } // end namespace llvm 628 629 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 630 /// immediate Value in the MCInst. The immediate Value has had any PC 631 /// adjustment made by the caller. If the instruction is a branch instruction 632 /// then isBranch is true, else false. If the getOpInfo() function was set as 633 /// part of the setupForSymbolicDisassembly() call then that function is called 634 /// to get any symbolic information at the Address for this instruction. If 635 /// that returns non-zero then the symbolic information it returns is used to 636 /// create an MCExpr and that is added as an operand to the MCInst. If 637 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 638 /// Value is done and if a symbol is found an MCExpr is created with that, else 639 /// an MCExpr with Value is created. This function returns true if it adds an 640 /// operand to the MCInst and false otherwise. 641 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 642 bool isBranch, uint64_t InstSize, 643 MCInst &MI, const void *Decoder) { 644 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 645 // FIXME: Does it make sense for value to be negative? 646 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 647 /* Offset */ 0, InstSize); 648 } 649 650 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 651 /// referenced by a load instruction with the base register that is the Pc. 652 /// These can often be values in a literal pool near the Address of the 653 /// instruction. The Address of the instruction and its immediate Value are 654 /// used as a possible literal pool entry. The SymbolLookUp call back will 655 /// return the name of a symbol referenced by the literal pool's entry if 656 /// the referenced address is that of a symbol. Or it will return a pointer to 657 /// a literal 'C' string if the referenced address of the literal pool's entry 658 /// is an address into a section with 'C' string literals. 659 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 660 const void *Decoder) { 661 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 662 Dis->tryAddingPcLoadReferenceComment(Value, Address); 663 } 664 665 // Thumb1 instructions don't have explicit S bits. Rather, they 666 // implicitly set CPSR. Since it's not represented in the encoding, the 667 // auto-generated decoder won't inject the CPSR operand. We need to fix 668 // that as a post-pass. 669 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 670 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 671 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 672 MCInst::iterator I = MI.begin(); 673 for (unsigned i = 0; i < NumOps; ++i, ++I) { 674 if (I == MI.end()) break; 675 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 676 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 677 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 678 return; 679 } 680 } 681 682 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 683 } 684 685 static bool isVectorPredicable(unsigned Opcode) { 686 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 687 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 688 for (unsigned i = 0; i < NumOps; ++i) { 689 if (ARM::isVpred(OpInfo[i].OperandType)) 690 return true; 691 } 692 return false; 693 } 694 695 // Most Thumb instructions don't have explicit predicates in the 696 // encoding, but rather get their predicates from IT context. We need 697 // to fix up the predicate operands using this context information as a 698 // post-pass. 699 MCDisassembler::DecodeStatus 700 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 701 MCDisassembler::DecodeStatus S = Success; 702 703 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 704 705 // A few instructions actually have predicates encoded in them. Don't 706 // try to overwrite it if we're seeing one of those. 707 switch (MI.getOpcode()) { 708 case ARM::tBcc: 709 case ARM::t2Bcc: 710 case ARM::tCBZ: 711 case ARM::tCBNZ: 712 case ARM::tCPS: 713 case ARM::t2CPS3p: 714 case ARM::t2CPS2p: 715 case ARM::t2CPS1p: 716 case ARM::t2CSEL: 717 case ARM::t2CSINC: 718 case ARM::t2CSINV: 719 case ARM::t2CSNEG: 720 case ARM::tMOVSr: 721 case ARM::tSETEND: 722 // Some instructions (mostly conditional branches) are not 723 // allowed in IT blocks. 724 if (ITBlock.instrInITBlock()) 725 S = SoftFail; 726 else 727 return Success; 728 break; 729 case ARM::t2HINT: 730 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 731 S = SoftFail; 732 break; 733 case ARM::tB: 734 case ARM::t2B: 735 case ARM::t2TBB: 736 case ARM::t2TBH: 737 // Some instructions (mostly unconditional branches) can 738 // only appears at the end of, or outside of, an IT. 739 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 740 S = SoftFail; 741 break; 742 default: 743 break; 744 } 745 746 // Warn on non-VPT predicable instruction in a VPT block and a VPT 747 // predicable instruction in an IT block 748 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 749 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 750 S = SoftFail; 751 752 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 753 // assume a predicate of AL. 754 unsigned CC = ARMCC::AL; 755 unsigned VCC = ARMVCC::None; 756 if (ITBlock.instrInITBlock()) { 757 CC = ITBlock.getITCC(); 758 ITBlock.advanceITState(); 759 } else if (VPTBlock.instrInVPTBlock()) { 760 VCC = VPTBlock.getVPTPred(); 761 VPTBlock.advanceVPTState(); 762 } 763 764 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 765 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 766 767 MCInst::iterator CCI = MI.begin(); 768 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 769 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 770 } 771 772 if (ARMInsts[MI.getOpcode()].isPredicable()) { 773 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 774 ++CCI; 775 if (CC == ARMCC::AL) 776 MI.insert(CCI, MCOperand::createReg(0)); 777 else 778 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 779 } else if (CC != ARMCC::AL) { 780 Check(S, SoftFail); 781 } 782 783 MCInst::iterator VCCI = MI.begin(); 784 unsigned VCCPos; 785 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 786 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 787 } 788 789 if (isVectorPredicable(MI.getOpcode())) { 790 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 791 ++VCCI; 792 if (VCC == ARMVCC::None) 793 MI.insert(VCCI, MCOperand::createReg(0)); 794 else 795 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 796 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 797 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 798 VCCPos + 2, MCOI::TIED_TO); 799 assert(TiedOp >= 0 && 800 "Inactive register in vpred_r is not tied to an output!"); 801 MI.insert(VCCI, MI.getOperand(TiedOp)); 802 } 803 } else if (VCC != ARMVCC::None) { 804 Check(S, SoftFail); 805 } 806 807 return S; 808 } 809 810 // Thumb VFP instructions are a special case. Because we share their 811 // encodings between ARM and Thumb modes, and they are predicable in ARM 812 // mode, the auto-generated decoder will give them an (incorrect) 813 // predicate operand. We need to rewrite these operands based on the IT 814 // context as a post-pass. 815 void ARMDisassembler::UpdateThumbVFPPredicate( 816 DecodeStatus &S, MCInst &MI) const { 817 unsigned CC; 818 CC = ITBlock.getITCC(); 819 if (CC == 0xF) 820 CC = ARMCC::AL; 821 if (ITBlock.instrInITBlock()) 822 ITBlock.advanceITState(); 823 else if (VPTBlock.instrInVPTBlock()) { 824 CC = VPTBlock.getVPTPred(); 825 VPTBlock.advanceVPTState(); 826 } 827 828 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 829 MCInst::iterator I = MI.begin(); 830 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 831 for (unsigned i = 0; i < NumOps; ++i, ++I) { 832 if (OpInfo[i].isPredicate() ) { 833 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 834 Check(S, SoftFail); 835 I->setImm(CC); 836 ++I; 837 if (CC == ARMCC::AL) 838 I->setReg(0); 839 else 840 I->setReg(ARM::CPSR); 841 return; 842 } 843 } 844 } 845 846 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 847 ArrayRef<uint8_t> Bytes, 848 uint64_t Address, 849 raw_ostream &OS, 850 raw_ostream &CS) const { 851 CommentStream = &CS; 852 853 assert(STI.getFeatureBits()[ARM::ModeThumb] && 854 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 855 856 // We want to read exactly 2 bytes of data. 857 if (Bytes.size() < 2) { 858 Size = 0; 859 return MCDisassembler::Fail; 860 } 861 862 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 863 DecodeStatus Result = 864 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 865 if (Result != MCDisassembler::Fail) { 866 Size = 2; 867 Check(Result, AddThumbPredicate(MI)); 868 return Result; 869 } 870 871 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 872 STI); 873 if (Result) { 874 Size = 2; 875 bool InITBlock = ITBlock.instrInITBlock(); 876 Check(Result, AddThumbPredicate(MI)); 877 AddThumb1SBit(MI, InITBlock); 878 return Result; 879 } 880 881 Result = 882 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 883 if (Result != MCDisassembler::Fail) { 884 Size = 2; 885 886 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 887 // the Thumb predicate. 888 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 889 Result = MCDisassembler::SoftFail; 890 891 Check(Result, AddThumbPredicate(MI)); 892 893 // If we find an IT instruction, we need to parse its condition 894 // code and mask operands so that we can apply them correctly 895 // to the subsequent instructions. 896 if (MI.getOpcode() == ARM::t2IT) { 897 unsigned Firstcond = MI.getOperand(0).getImm(); 898 unsigned Mask = MI.getOperand(1).getImm(); 899 ITBlock.setITState(Firstcond, Mask); 900 901 // An IT instruction that would give a 'NV' predicate is unpredictable. 902 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 903 CS << "unpredictable IT predicate sequence"; 904 } 905 906 return Result; 907 } 908 909 // We want to read exactly 4 bytes of data. 910 if (Bytes.size() < 4) { 911 Size = 0; 912 return MCDisassembler::Fail; 913 } 914 915 uint32_t Insn32 = 916 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 917 918 Result = 919 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 920 if (Result != MCDisassembler::Fail) { 921 Size = 4; 922 923 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 924 // the VPT predicate. 925 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 926 Result = MCDisassembler::SoftFail; 927 928 Check(Result, AddThumbPredicate(MI)); 929 930 if (isVPTOpcode(MI.getOpcode())) { 931 unsigned Mask = MI.getOperand(0).getImm(); 932 VPTBlock.setVPTState(Mask); 933 } 934 935 return Result; 936 } 937 938 Result = 939 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 940 if (Result != MCDisassembler::Fail) { 941 Size = 4; 942 bool InITBlock = ITBlock.instrInITBlock(); 943 Check(Result, AddThumbPredicate(MI)); 944 AddThumb1SBit(MI, InITBlock); 945 return Result; 946 } 947 948 Result = 949 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 950 if (Result != MCDisassembler::Fail) { 951 Size = 4; 952 Check(Result, AddThumbPredicate(MI)); 953 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 954 } 955 956 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 957 Result = 958 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 959 if (Result != MCDisassembler::Fail) { 960 Size = 4; 961 UpdateThumbVFPPredicate(Result, MI); 962 return Result; 963 } 964 } 965 966 Result = 967 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 968 if (Result != MCDisassembler::Fail) { 969 Size = 4; 970 return Result; 971 } 972 973 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 974 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 975 STI); 976 if (Result != MCDisassembler::Fail) { 977 Size = 4; 978 Check(Result, AddThumbPredicate(MI)); 979 return Result; 980 } 981 } 982 983 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 984 uint32_t NEONLdStInsn = Insn32; 985 NEONLdStInsn &= 0xF0FFFFFF; 986 NEONLdStInsn |= 0x04000000; 987 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 988 Address, this, STI); 989 if (Result != MCDisassembler::Fail) { 990 Size = 4; 991 Check(Result, AddThumbPredicate(MI)); 992 return Result; 993 } 994 } 995 996 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 997 uint32_t NEONDataInsn = Insn32; 998 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 999 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1000 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1001 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1002 Address, this, STI); 1003 if (Result != MCDisassembler::Fail) { 1004 Size = 4; 1005 Check(Result, AddThumbPredicate(MI)); 1006 return Result; 1007 } 1008 1009 uint32_t NEONCryptoInsn = Insn32; 1010 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1011 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1012 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1013 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1014 Address, this, STI); 1015 if (Result != MCDisassembler::Fail) { 1016 Size = 4; 1017 return Result; 1018 } 1019 1020 uint32_t NEONv8Insn = Insn32; 1021 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1022 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1023 this, STI); 1024 if (Result != MCDisassembler::Fail) { 1025 Size = 4; 1026 return Result; 1027 } 1028 } 1029 1030 Result = 1031 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1032 if (Result != MCDisassembler::Fail) { 1033 Size = 4; 1034 Check(Result, AddThumbPredicate(MI)); 1035 return Result; 1036 } 1037 1038 Size = 0; 1039 return MCDisassembler::Fail; 1040 } 1041 1042 extern "C" void LLVMInitializeARMDisassembler() { 1043 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1044 createARMDisassembler); 1045 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1046 createARMDisassembler); 1047 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1048 createARMDisassembler); 1049 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1050 createARMDisassembler); 1051 } 1052 1053 static const uint16_t GPRDecoderTable[] = { 1054 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1055 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1056 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1057 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1058 }; 1059 1060 static const uint16_t CLRMGPRDecoderTable[] = { 1061 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1062 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1063 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1064 ARM::R12, 0, ARM::LR, ARM::APSR 1065 }; 1066 1067 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1068 uint64_t Address, const void *Decoder) { 1069 if (RegNo > 15) 1070 return MCDisassembler::Fail; 1071 1072 unsigned Register = GPRDecoderTable[RegNo]; 1073 Inst.addOperand(MCOperand::createReg(Register)); 1074 return MCDisassembler::Success; 1075 } 1076 1077 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1078 uint64_t Address, 1079 const void *Decoder) { 1080 if (RegNo > 15) 1081 return MCDisassembler::Fail; 1082 1083 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1084 if (Register == 0) 1085 return MCDisassembler::Fail; 1086 1087 Inst.addOperand(MCOperand::createReg(Register)); 1088 return MCDisassembler::Success; 1089 } 1090 1091 static DecodeStatus 1092 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1093 uint64_t Address, const void *Decoder) { 1094 DecodeStatus S = MCDisassembler::Success; 1095 1096 if (RegNo == 15) 1097 S = MCDisassembler::SoftFail; 1098 1099 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1100 1101 return S; 1102 } 1103 1104 static DecodeStatus 1105 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1106 uint64_t Address, const void *Decoder) { 1107 DecodeStatus S = MCDisassembler::Success; 1108 1109 if (RegNo == 15) 1110 { 1111 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1112 return MCDisassembler::Success; 1113 } 1114 1115 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1116 return S; 1117 } 1118 1119 static DecodeStatus 1120 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1121 uint64_t Address, const void *Decoder) { 1122 DecodeStatus S = MCDisassembler::Success; 1123 1124 if (RegNo == 15) 1125 { 1126 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1127 return MCDisassembler::Success; 1128 } 1129 1130 if (RegNo == 13) 1131 S = MCDisassembler::SoftFail; 1132 1133 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1134 return S; 1135 } 1136 1137 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1138 uint64_t Address, const void *Decoder) { 1139 if (RegNo > 7) 1140 return MCDisassembler::Fail; 1141 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1142 } 1143 1144 static const uint16_t GPRPairDecoderTable[] = { 1145 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1146 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1147 }; 1148 1149 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1150 uint64_t Address, const void *Decoder) { 1151 DecodeStatus S = MCDisassembler::Success; 1152 1153 if (RegNo > 13) 1154 return MCDisassembler::Fail; 1155 1156 if ((RegNo & 1) || RegNo == 0xe) 1157 S = MCDisassembler::SoftFail; 1158 1159 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1160 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1161 return S; 1162 } 1163 1164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1165 uint64_t Address, const void *Decoder) { 1166 unsigned Register = 0; 1167 switch (RegNo) { 1168 case 0: 1169 Register = ARM::R0; 1170 break; 1171 case 1: 1172 Register = ARM::R1; 1173 break; 1174 case 2: 1175 Register = ARM::R2; 1176 break; 1177 case 3: 1178 Register = ARM::R3; 1179 break; 1180 case 9: 1181 Register = ARM::R9; 1182 break; 1183 case 12: 1184 Register = ARM::R12; 1185 break; 1186 default: 1187 return MCDisassembler::Fail; 1188 } 1189 1190 Inst.addOperand(MCOperand::createReg(Register)); 1191 return MCDisassembler::Success; 1192 } 1193 1194 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1195 uint64_t Address, const void *Decoder) { 1196 DecodeStatus S = MCDisassembler::Success; 1197 1198 const FeatureBitset &featureBits = 1199 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1200 1201 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1202 S = MCDisassembler::SoftFail; 1203 1204 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1205 return S; 1206 } 1207 1208 static const uint16_t SPRDecoderTable[] = { 1209 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1210 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1211 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1212 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1213 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1214 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1215 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1216 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1217 }; 1218 1219 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1220 uint64_t Address, const void *Decoder) { 1221 if (RegNo > 31) 1222 return MCDisassembler::Fail; 1223 1224 unsigned Register = SPRDecoderTable[RegNo]; 1225 Inst.addOperand(MCOperand::createReg(Register)); 1226 return MCDisassembler::Success; 1227 } 1228 1229 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1230 uint64_t Address, const void *Decoder) { 1231 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1232 } 1233 1234 static const uint16_t DPRDecoderTable[] = { 1235 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1236 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1237 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1238 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1239 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1240 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1241 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1242 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1243 }; 1244 1245 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1246 uint64_t Address, const void *Decoder) { 1247 const FeatureBitset &featureBits = 1248 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1249 1250 bool hasD32 = featureBits[ARM::FeatureD32]; 1251 1252 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1253 return MCDisassembler::Fail; 1254 1255 unsigned Register = DPRDecoderTable[RegNo]; 1256 Inst.addOperand(MCOperand::createReg(Register)); 1257 return MCDisassembler::Success; 1258 } 1259 1260 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1261 uint64_t Address, const void *Decoder) { 1262 if (RegNo > 7) 1263 return MCDisassembler::Fail; 1264 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1265 } 1266 1267 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1268 uint64_t Address, const void *Decoder) { 1269 if (RegNo > 15) 1270 return MCDisassembler::Fail; 1271 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1272 } 1273 1274 static DecodeStatus 1275 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1276 uint64_t Address, const void *Decoder) { 1277 if (RegNo > 15) 1278 return MCDisassembler::Fail; 1279 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1280 } 1281 1282 static const uint16_t QPRDecoderTable[] = { 1283 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1284 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1285 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1286 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1287 }; 1288 1289 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1290 uint64_t Address, const void *Decoder) { 1291 if (RegNo > 31 || (RegNo & 1) != 0) 1292 return MCDisassembler::Fail; 1293 RegNo >>= 1; 1294 1295 unsigned Register = QPRDecoderTable[RegNo]; 1296 Inst.addOperand(MCOperand::createReg(Register)); 1297 return MCDisassembler::Success; 1298 } 1299 1300 static const uint16_t DPairDecoderTable[] = { 1301 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1302 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1303 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1304 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1305 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1306 ARM::Q15 1307 }; 1308 1309 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1310 uint64_t Address, const void *Decoder) { 1311 if (RegNo > 30) 1312 return MCDisassembler::Fail; 1313 1314 unsigned Register = DPairDecoderTable[RegNo]; 1315 Inst.addOperand(MCOperand::createReg(Register)); 1316 return MCDisassembler::Success; 1317 } 1318 1319 static const uint16_t DPairSpacedDecoderTable[] = { 1320 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1321 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1322 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1323 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1324 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1325 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1326 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1327 ARM::D28_D30, ARM::D29_D31 1328 }; 1329 1330 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1331 unsigned RegNo, 1332 uint64_t Address, 1333 const void *Decoder) { 1334 if (RegNo > 29) 1335 return MCDisassembler::Fail; 1336 1337 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1338 Inst.addOperand(MCOperand::createReg(Register)); 1339 return MCDisassembler::Success; 1340 } 1341 1342 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1343 uint64_t Address, const void *Decoder) { 1344 DecodeStatus S = MCDisassembler::Success; 1345 if (Val == 0xF) return MCDisassembler::Fail; 1346 // AL predicate is not allowed on Thumb1 branches. 1347 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1348 return MCDisassembler::Fail; 1349 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1350 Check(S, MCDisassembler::SoftFail); 1351 Inst.addOperand(MCOperand::createImm(Val)); 1352 if (Val == ARMCC::AL) { 1353 Inst.addOperand(MCOperand::createReg(0)); 1354 } else 1355 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1356 return S; 1357 } 1358 1359 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1360 uint64_t Address, const void *Decoder) { 1361 if (Val) 1362 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1363 else 1364 Inst.addOperand(MCOperand::createReg(0)); 1365 return MCDisassembler::Success; 1366 } 1367 1368 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1369 uint64_t Address, const void *Decoder) { 1370 DecodeStatus S = MCDisassembler::Success; 1371 1372 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1373 unsigned type = fieldFromInstruction(Val, 5, 2); 1374 unsigned imm = fieldFromInstruction(Val, 7, 5); 1375 1376 // Register-immediate 1377 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1378 return MCDisassembler::Fail; 1379 1380 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1381 switch (type) { 1382 case 0: 1383 Shift = ARM_AM::lsl; 1384 break; 1385 case 1: 1386 Shift = ARM_AM::lsr; 1387 break; 1388 case 2: 1389 Shift = ARM_AM::asr; 1390 break; 1391 case 3: 1392 Shift = ARM_AM::ror; 1393 break; 1394 } 1395 1396 if (Shift == ARM_AM::ror && imm == 0) 1397 Shift = ARM_AM::rrx; 1398 1399 unsigned Op = Shift | (imm << 3); 1400 Inst.addOperand(MCOperand::createImm(Op)); 1401 1402 return S; 1403 } 1404 1405 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1406 uint64_t Address, const void *Decoder) { 1407 DecodeStatus S = MCDisassembler::Success; 1408 1409 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1410 unsigned type = fieldFromInstruction(Val, 5, 2); 1411 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1412 1413 // Register-register 1414 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1415 return MCDisassembler::Fail; 1416 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1417 return MCDisassembler::Fail; 1418 1419 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1420 switch (type) { 1421 case 0: 1422 Shift = ARM_AM::lsl; 1423 break; 1424 case 1: 1425 Shift = ARM_AM::lsr; 1426 break; 1427 case 2: 1428 Shift = ARM_AM::asr; 1429 break; 1430 case 3: 1431 Shift = ARM_AM::ror; 1432 break; 1433 } 1434 1435 Inst.addOperand(MCOperand::createImm(Shift)); 1436 1437 return S; 1438 } 1439 1440 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1441 uint64_t Address, const void *Decoder) { 1442 DecodeStatus S = MCDisassembler::Success; 1443 1444 bool NeedDisjointWriteback = false; 1445 unsigned WritebackReg = 0; 1446 bool CLRM = false; 1447 switch (Inst.getOpcode()) { 1448 default: 1449 break; 1450 case ARM::LDMIA_UPD: 1451 case ARM::LDMDB_UPD: 1452 case ARM::LDMIB_UPD: 1453 case ARM::LDMDA_UPD: 1454 case ARM::t2LDMIA_UPD: 1455 case ARM::t2LDMDB_UPD: 1456 case ARM::t2STMIA_UPD: 1457 case ARM::t2STMDB_UPD: 1458 NeedDisjointWriteback = true; 1459 WritebackReg = Inst.getOperand(0).getReg(); 1460 break; 1461 case ARM::t2CLRM: 1462 CLRM = true; 1463 break; 1464 } 1465 1466 // Empty register lists are not allowed. 1467 if (Val == 0) return MCDisassembler::Fail; 1468 for (unsigned i = 0; i < 16; ++i) { 1469 if (Val & (1 << i)) { 1470 if (CLRM) { 1471 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1472 return MCDisassembler::Fail; 1473 } 1474 } else { 1475 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1476 return MCDisassembler::Fail; 1477 // Writeback not allowed if Rn is in the target list. 1478 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1479 Check(S, MCDisassembler::SoftFail); 1480 } 1481 } 1482 } 1483 1484 return S; 1485 } 1486 1487 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1488 uint64_t Address, const void *Decoder) { 1489 DecodeStatus S = MCDisassembler::Success; 1490 1491 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1492 unsigned regs = fieldFromInstruction(Val, 0, 8); 1493 1494 // In case of unpredictable encoding, tweak the operands. 1495 if (regs == 0 || (Vd + regs) > 32) { 1496 regs = Vd + regs > 32 ? 32 - Vd : regs; 1497 regs = std::max( 1u, regs); 1498 S = MCDisassembler::SoftFail; 1499 } 1500 1501 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1502 return MCDisassembler::Fail; 1503 for (unsigned i = 0; i < (regs - 1); ++i) { 1504 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1505 return MCDisassembler::Fail; 1506 } 1507 1508 return S; 1509 } 1510 1511 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1512 uint64_t Address, const void *Decoder) { 1513 DecodeStatus S = MCDisassembler::Success; 1514 1515 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1516 unsigned regs = fieldFromInstruction(Val, 1, 7); 1517 1518 // In case of unpredictable encoding, tweak the operands. 1519 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1520 regs = Vd + regs > 32 ? 32 - Vd : regs; 1521 regs = std::max( 1u, regs); 1522 regs = std::min(16u, regs); 1523 S = MCDisassembler::SoftFail; 1524 } 1525 1526 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1527 return MCDisassembler::Fail; 1528 for (unsigned i = 0; i < (regs - 1); ++i) { 1529 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1530 return MCDisassembler::Fail; 1531 } 1532 1533 return S; 1534 } 1535 1536 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1537 uint64_t Address, const void *Decoder) { 1538 // This operand encodes a mask of contiguous zeros between a specified MSB 1539 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1540 // the mask of all bits LSB-and-lower, and then xor them to create 1541 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1542 // create the final mask. 1543 unsigned msb = fieldFromInstruction(Val, 5, 5); 1544 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1545 1546 DecodeStatus S = MCDisassembler::Success; 1547 if (lsb > msb) { 1548 Check(S, MCDisassembler::SoftFail); 1549 // The check above will cause the warning for the "potentially undefined 1550 // instruction encoding" but we can't build a bad MCOperand value here 1551 // with a lsb > msb or else printing the MCInst will cause a crash. 1552 lsb = msb; 1553 } 1554 1555 uint32_t msb_mask = 0xFFFFFFFF; 1556 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1557 uint32_t lsb_mask = (1U << lsb) - 1; 1558 1559 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1560 return S; 1561 } 1562 1563 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1564 uint64_t Address, const void *Decoder) { 1565 DecodeStatus S = MCDisassembler::Success; 1566 1567 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1568 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1569 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1570 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1571 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1572 unsigned U = fieldFromInstruction(Insn, 23, 1); 1573 const FeatureBitset &featureBits = 1574 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1575 1576 switch (Inst.getOpcode()) { 1577 case ARM::LDC_OFFSET: 1578 case ARM::LDC_PRE: 1579 case ARM::LDC_POST: 1580 case ARM::LDC_OPTION: 1581 case ARM::LDCL_OFFSET: 1582 case ARM::LDCL_PRE: 1583 case ARM::LDCL_POST: 1584 case ARM::LDCL_OPTION: 1585 case ARM::STC_OFFSET: 1586 case ARM::STC_PRE: 1587 case ARM::STC_POST: 1588 case ARM::STC_OPTION: 1589 case ARM::STCL_OFFSET: 1590 case ARM::STCL_PRE: 1591 case ARM::STCL_POST: 1592 case ARM::STCL_OPTION: 1593 case ARM::t2LDC_OFFSET: 1594 case ARM::t2LDC_PRE: 1595 case ARM::t2LDC_POST: 1596 case ARM::t2LDC_OPTION: 1597 case ARM::t2LDCL_OFFSET: 1598 case ARM::t2LDCL_PRE: 1599 case ARM::t2LDCL_POST: 1600 case ARM::t2LDCL_OPTION: 1601 case ARM::t2STC_OFFSET: 1602 case ARM::t2STC_PRE: 1603 case ARM::t2STC_POST: 1604 case ARM::t2STC_OPTION: 1605 case ARM::t2STCL_OFFSET: 1606 case ARM::t2STCL_PRE: 1607 case ARM::t2STCL_POST: 1608 case ARM::t2STCL_OPTION: 1609 case ARM::t2LDC2_OFFSET: 1610 case ARM::t2LDC2L_OFFSET: 1611 case ARM::t2LDC2_PRE: 1612 case ARM::t2LDC2L_PRE: 1613 case ARM::t2STC2_OFFSET: 1614 case ARM::t2STC2L_OFFSET: 1615 case ARM::t2STC2_PRE: 1616 case ARM::t2STC2L_PRE: 1617 case ARM::LDC2_OFFSET: 1618 case ARM::LDC2L_OFFSET: 1619 case ARM::LDC2_PRE: 1620 case ARM::LDC2L_PRE: 1621 case ARM::STC2_OFFSET: 1622 case ARM::STC2L_OFFSET: 1623 case ARM::STC2_PRE: 1624 case ARM::STC2L_PRE: 1625 case ARM::t2LDC2_OPTION: 1626 case ARM::t2STC2_OPTION: 1627 case ARM::t2LDC2_POST: 1628 case ARM::t2LDC2L_POST: 1629 case ARM::t2STC2_POST: 1630 case ARM::t2STC2L_POST: 1631 case ARM::LDC2_POST: 1632 case ARM::LDC2L_POST: 1633 case ARM::STC2_POST: 1634 case ARM::STC2L_POST: 1635 if (coproc == 0xA || coproc == 0xB || 1636 (featureBits[ARM::HasV8_1MMainlineOps] && 1637 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1638 coproc == 0xE || coproc == 0xF))) 1639 return MCDisassembler::Fail; 1640 break; 1641 default: 1642 break; 1643 } 1644 1645 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1646 return MCDisassembler::Fail; 1647 1648 Inst.addOperand(MCOperand::createImm(coproc)); 1649 Inst.addOperand(MCOperand::createImm(CRd)); 1650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1651 return MCDisassembler::Fail; 1652 1653 switch (Inst.getOpcode()) { 1654 case ARM::t2LDC2_OFFSET: 1655 case ARM::t2LDC2L_OFFSET: 1656 case ARM::t2LDC2_PRE: 1657 case ARM::t2LDC2L_PRE: 1658 case ARM::t2STC2_OFFSET: 1659 case ARM::t2STC2L_OFFSET: 1660 case ARM::t2STC2_PRE: 1661 case ARM::t2STC2L_PRE: 1662 case ARM::LDC2_OFFSET: 1663 case ARM::LDC2L_OFFSET: 1664 case ARM::LDC2_PRE: 1665 case ARM::LDC2L_PRE: 1666 case ARM::STC2_OFFSET: 1667 case ARM::STC2L_OFFSET: 1668 case ARM::STC2_PRE: 1669 case ARM::STC2L_PRE: 1670 case ARM::t2LDC_OFFSET: 1671 case ARM::t2LDCL_OFFSET: 1672 case ARM::t2LDC_PRE: 1673 case ARM::t2LDCL_PRE: 1674 case ARM::t2STC_OFFSET: 1675 case ARM::t2STCL_OFFSET: 1676 case ARM::t2STC_PRE: 1677 case ARM::t2STCL_PRE: 1678 case ARM::LDC_OFFSET: 1679 case ARM::LDCL_OFFSET: 1680 case ARM::LDC_PRE: 1681 case ARM::LDCL_PRE: 1682 case ARM::STC_OFFSET: 1683 case ARM::STCL_OFFSET: 1684 case ARM::STC_PRE: 1685 case ARM::STCL_PRE: 1686 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1687 Inst.addOperand(MCOperand::createImm(imm)); 1688 break; 1689 case ARM::t2LDC2_POST: 1690 case ARM::t2LDC2L_POST: 1691 case ARM::t2STC2_POST: 1692 case ARM::t2STC2L_POST: 1693 case ARM::LDC2_POST: 1694 case ARM::LDC2L_POST: 1695 case ARM::STC2_POST: 1696 case ARM::STC2L_POST: 1697 case ARM::t2LDC_POST: 1698 case ARM::t2LDCL_POST: 1699 case ARM::t2STC_POST: 1700 case ARM::t2STCL_POST: 1701 case ARM::LDC_POST: 1702 case ARM::LDCL_POST: 1703 case ARM::STC_POST: 1704 case ARM::STCL_POST: 1705 imm |= U << 8; 1706 LLVM_FALLTHROUGH; 1707 default: 1708 // The 'option' variant doesn't encode 'U' in the immediate since 1709 // the immediate is unsigned [0,255]. 1710 Inst.addOperand(MCOperand::createImm(imm)); 1711 break; 1712 } 1713 1714 switch (Inst.getOpcode()) { 1715 case ARM::LDC_OFFSET: 1716 case ARM::LDC_PRE: 1717 case ARM::LDC_POST: 1718 case ARM::LDC_OPTION: 1719 case ARM::LDCL_OFFSET: 1720 case ARM::LDCL_PRE: 1721 case ARM::LDCL_POST: 1722 case ARM::LDCL_OPTION: 1723 case ARM::STC_OFFSET: 1724 case ARM::STC_PRE: 1725 case ARM::STC_POST: 1726 case ARM::STC_OPTION: 1727 case ARM::STCL_OFFSET: 1728 case ARM::STCL_PRE: 1729 case ARM::STCL_POST: 1730 case ARM::STCL_OPTION: 1731 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1732 return MCDisassembler::Fail; 1733 break; 1734 default: 1735 break; 1736 } 1737 1738 return S; 1739 } 1740 1741 static DecodeStatus 1742 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1743 uint64_t Address, const void *Decoder) { 1744 DecodeStatus S = MCDisassembler::Success; 1745 1746 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1747 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1748 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1749 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1750 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1751 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1752 unsigned P = fieldFromInstruction(Insn, 24, 1); 1753 unsigned W = fieldFromInstruction(Insn, 21, 1); 1754 1755 // On stores, the writeback operand precedes Rt. 1756 switch (Inst.getOpcode()) { 1757 case ARM::STR_POST_IMM: 1758 case ARM::STR_POST_REG: 1759 case ARM::STRB_POST_IMM: 1760 case ARM::STRB_POST_REG: 1761 case ARM::STRT_POST_REG: 1762 case ARM::STRT_POST_IMM: 1763 case ARM::STRBT_POST_REG: 1764 case ARM::STRBT_POST_IMM: 1765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1766 return MCDisassembler::Fail; 1767 break; 1768 default: 1769 break; 1770 } 1771 1772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1773 return MCDisassembler::Fail; 1774 1775 // On loads, the writeback operand comes after Rt. 1776 switch (Inst.getOpcode()) { 1777 case ARM::LDR_POST_IMM: 1778 case ARM::LDR_POST_REG: 1779 case ARM::LDRB_POST_IMM: 1780 case ARM::LDRB_POST_REG: 1781 case ARM::LDRBT_POST_REG: 1782 case ARM::LDRBT_POST_IMM: 1783 case ARM::LDRT_POST_REG: 1784 case ARM::LDRT_POST_IMM: 1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1786 return MCDisassembler::Fail; 1787 break; 1788 default: 1789 break; 1790 } 1791 1792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1793 return MCDisassembler::Fail; 1794 1795 ARM_AM::AddrOpc Op = ARM_AM::add; 1796 if (!fieldFromInstruction(Insn, 23, 1)) 1797 Op = ARM_AM::sub; 1798 1799 bool writeback = (P == 0) || (W == 1); 1800 unsigned idx_mode = 0; 1801 if (P && writeback) 1802 idx_mode = ARMII::IndexModePre; 1803 else if (!P && writeback) 1804 idx_mode = ARMII::IndexModePost; 1805 1806 if (writeback && (Rn == 15 || Rn == Rt)) 1807 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1808 1809 if (reg) { 1810 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1811 return MCDisassembler::Fail; 1812 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1813 switch( fieldFromInstruction(Insn, 5, 2)) { 1814 case 0: 1815 Opc = ARM_AM::lsl; 1816 break; 1817 case 1: 1818 Opc = ARM_AM::lsr; 1819 break; 1820 case 2: 1821 Opc = ARM_AM::asr; 1822 break; 1823 case 3: 1824 Opc = ARM_AM::ror; 1825 break; 1826 default: 1827 return MCDisassembler::Fail; 1828 } 1829 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1830 if (Opc == ARM_AM::ror && amt == 0) 1831 Opc = ARM_AM::rrx; 1832 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1833 1834 Inst.addOperand(MCOperand::createImm(imm)); 1835 } else { 1836 Inst.addOperand(MCOperand::createReg(0)); 1837 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1838 Inst.addOperand(MCOperand::createImm(tmp)); 1839 } 1840 1841 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1842 return MCDisassembler::Fail; 1843 1844 return S; 1845 } 1846 1847 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1848 uint64_t Address, const void *Decoder) { 1849 DecodeStatus S = MCDisassembler::Success; 1850 1851 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1852 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1853 unsigned type = fieldFromInstruction(Val, 5, 2); 1854 unsigned imm = fieldFromInstruction(Val, 7, 5); 1855 unsigned U = fieldFromInstruction(Val, 12, 1); 1856 1857 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1858 switch (type) { 1859 case 0: 1860 ShOp = ARM_AM::lsl; 1861 break; 1862 case 1: 1863 ShOp = ARM_AM::lsr; 1864 break; 1865 case 2: 1866 ShOp = ARM_AM::asr; 1867 break; 1868 case 3: 1869 ShOp = ARM_AM::ror; 1870 break; 1871 } 1872 1873 if (ShOp == ARM_AM::ror && imm == 0) 1874 ShOp = ARM_AM::rrx; 1875 1876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1877 return MCDisassembler::Fail; 1878 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1879 return MCDisassembler::Fail; 1880 unsigned shift; 1881 if (U) 1882 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1883 else 1884 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1885 Inst.addOperand(MCOperand::createImm(shift)); 1886 1887 return S; 1888 } 1889 1890 static DecodeStatus 1891 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1892 uint64_t Address, const void *Decoder) { 1893 DecodeStatus S = MCDisassembler::Success; 1894 1895 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1896 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1897 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1898 unsigned type = fieldFromInstruction(Insn, 22, 1); 1899 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1900 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1901 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1902 unsigned W = fieldFromInstruction(Insn, 21, 1); 1903 unsigned P = fieldFromInstruction(Insn, 24, 1); 1904 unsigned Rt2 = Rt + 1; 1905 1906 bool writeback = (W == 1) | (P == 0); 1907 1908 // For {LD,ST}RD, Rt must be even, else undefined. 1909 switch (Inst.getOpcode()) { 1910 case ARM::STRD: 1911 case ARM::STRD_PRE: 1912 case ARM::STRD_POST: 1913 case ARM::LDRD: 1914 case ARM::LDRD_PRE: 1915 case ARM::LDRD_POST: 1916 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1917 break; 1918 default: 1919 break; 1920 } 1921 switch (Inst.getOpcode()) { 1922 case ARM::STRD: 1923 case ARM::STRD_PRE: 1924 case ARM::STRD_POST: 1925 if (P == 0 && W == 1) 1926 S = MCDisassembler::SoftFail; 1927 1928 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1929 S = MCDisassembler::SoftFail; 1930 if (type && Rm == 15) 1931 S = MCDisassembler::SoftFail; 1932 if (Rt2 == 15) 1933 S = MCDisassembler::SoftFail; 1934 if (!type && fieldFromInstruction(Insn, 8, 4)) 1935 S = MCDisassembler::SoftFail; 1936 break; 1937 case ARM::STRH: 1938 case ARM::STRH_PRE: 1939 case ARM::STRH_POST: 1940 if (Rt == 15) 1941 S = MCDisassembler::SoftFail; 1942 if (writeback && (Rn == 15 || Rn == Rt)) 1943 S = MCDisassembler::SoftFail; 1944 if (!type && Rm == 15) 1945 S = MCDisassembler::SoftFail; 1946 break; 1947 case ARM::LDRD: 1948 case ARM::LDRD_PRE: 1949 case ARM::LDRD_POST: 1950 if (type && Rn == 15) { 1951 if (Rt2 == 15) 1952 S = MCDisassembler::SoftFail; 1953 break; 1954 } 1955 if (P == 0 && W == 1) 1956 S = MCDisassembler::SoftFail; 1957 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1958 S = MCDisassembler::SoftFail; 1959 if (!type && writeback && Rn == 15) 1960 S = MCDisassembler::SoftFail; 1961 if (writeback && (Rn == Rt || Rn == Rt2)) 1962 S = MCDisassembler::SoftFail; 1963 break; 1964 case ARM::LDRH: 1965 case ARM::LDRH_PRE: 1966 case ARM::LDRH_POST: 1967 if (type && Rn == 15) { 1968 if (Rt == 15) 1969 S = MCDisassembler::SoftFail; 1970 break; 1971 } 1972 if (Rt == 15) 1973 S = MCDisassembler::SoftFail; 1974 if (!type && Rm == 15) 1975 S = MCDisassembler::SoftFail; 1976 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1977 S = MCDisassembler::SoftFail; 1978 break; 1979 case ARM::LDRSH: 1980 case ARM::LDRSH_PRE: 1981 case ARM::LDRSH_POST: 1982 case ARM::LDRSB: 1983 case ARM::LDRSB_PRE: 1984 case ARM::LDRSB_POST: 1985 if (type && Rn == 15) { 1986 if (Rt == 15) 1987 S = MCDisassembler::SoftFail; 1988 break; 1989 } 1990 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1991 S = MCDisassembler::SoftFail; 1992 if (!type && (Rt == 15 || Rm == 15)) 1993 S = MCDisassembler::SoftFail; 1994 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1995 S = MCDisassembler::SoftFail; 1996 break; 1997 default: 1998 break; 1999 } 2000 2001 if (writeback) { // Writeback 2002 if (P) 2003 U |= ARMII::IndexModePre << 9; 2004 else 2005 U |= ARMII::IndexModePost << 9; 2006 2007 // On stores, the writeback operand precedes Rt. 2008 switch (Inst.getOpcode()) { 2009 case ARM::STRD: 2010 case ARM::STRD_PRE: 2011 case ARM::STRD_POST: 2012 case ARM::STRH: 2013 case ARM::STRH_PRE: 2014 case ARM::STRH_POST: 2015 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2016 return MCDisassembler::Fail; 2017 break; 2018 default: 2019 break; 2020 } 2021 } 2022 2023 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2024 return MCDisassembler::Fail; 2025 switch (Inst.getOpcode()) { 2026 case ARM::STRD: 2027 case ARM::STRD_PRE: 2028 case ARM::STRD_POST: 2029 case ARM::LDRD: 2030 case ARM::LDRD_PRE: 2031 case ARM::LDRD_POST: 2032 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2033 return MCDisassembler::Fail; 2034 break; 2035 default: 2036 break; 2037 } 2038 2039 if (writeback) { 2040 // On loads, the writeback operand comes after Rt. 2041 switch (Inst.getOpcode()) { 2042 case ARM::LDRD: 2043 case ARM::LDRD_PRE: 2044 case ARM::LDRD_POST: 2045 case ARM::LDRH: 2046 case ARM::LDRH_PRE: 2047 case ARM::LDRH_POST: 2048 case ARM::LDRSH: 2049 case ARM::LDRSH_PRE: 2050 case ARM::LDRSH_POST: 2051 case ARM::LDRSB: 2052 case ARM::LDRSB_PRE: 2053 case ARM::LDRSB_POST: 2054 case ARM::LDRHTr: 2055 case ARM::LDRSBTr: 2056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2057 return MCDisassembler::Fail; 2058 break; 2059 default: 2060 break; 2061 } 2062 } 2063 2064 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2065 return MCDisassembler::Fail; 2066 2067 if (type) { 2068 Inst.addOperand(MCOperand::createReg(0)); 2069 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2070 } else { 2071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2072 return MCDisassembler::Fail; 2073 Inst.addOperand(MCOperand::createImm(U)); 2074 } 2075 2076 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2077 return MCDisassembler::Fail; 2078 2079 return S; 2080 } 2081 2082 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2083 uint64_t Address, const void *Decoder) { 2084 DecodeStatus S = MCDisassembler::Success; 2085 2086 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2087 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2088 2089 switch (mode) { 2090 case 0: 2091 mode = ARM_AM::da; 2092 break; 2093 case 1: 2094 mode = ARM_AM::ia; 2095 break; 2096 case 2: 2097 mode = ARM_AM::db; 2098 break; 2099 case 3: 2100 mode = ARM_AM::ib; 2101 break; 2102 } 2103 2104 Inst.addOperand(MCOperand::createImm(mode)); 2105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2106 return MCDisassembler::Fail; 2107 2108 return S; 2109 } 2110 2111 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2112 uint64_t Address, const void *Decoder) { 2113 DecodeStatus S = MCDisassembler::Success; 2114 2115 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2116 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2117 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2118 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2119 2120 if (pred == 0xF) 2121 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2122 2123 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2124 return MCDisassembler::Fail; 2125 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2126 return MCDisassembler::Fail; 2127 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2128 return MCDisassembler::Fail; 2129 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2130 return MCDisassembler::Fail; 2131 return S; 2132 } 2133 2134 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2135 unsigned Insn, 2136 uint64_t Address, const void *Decoder) { 2137 DecodeStatus S = MCDisassembler::Success; 2138 2139 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2140 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2141 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2142 2143 if (pred == 0xF) { 2144 // Ambiguous with RFE and SRS 2145 switch (Inst.getOpcode()) { 2146 case ARM::LDMDA: 2147 Inst.setOpcode(ARM::RFEDA); 2148 break; 2149 case ARM::LDMDA_UPD: 2150 Inst.setOpcode(ARM::RFEDA_UPD); 2151 break; 2152 case ARM::LDMDB: 2153 Inst.setOpcode(ARM::RFEDB); 2154 break; 2155 case ARM::LDMDB_UPD: 2156 Inst.setOpcode(ARM::RFEDB_UPD); 2157 break; 2158 case ARM::LDMIA: 2159 Inst.setOpcode(ARM::RFEIA); 2160 break; 2161 case ARM::LDMIA_UPD: 2162 Inst.setOpcode(ARM::RFEIA_UPD); 2163 break; 2164 case ARM::LDMIB: 2165 Inst.setOpcode(ARM::RFEIB); 2166 break; 2167 case ARM::LDMIB_UPD: 2168 Inst.setOpcode(ARM::RFEIB_UPD); 2169 break; 2170 case ARM::STMDA: 2171 Inst.setOpcode(ARM::SRSDA); 2172 break; 2173 case ARM::STMDA_UPD: 2174 Inst.setOpcode(ARM::SRSDA_UPD); 2175 break; 2176 case ARM::STMDB: 2177 Inst.setOpcode(ARM::SRSDB); 2178 break; 2179 case ARM::STMDB_UPD: 2180 Inst.setOpcode(ARM::SRSDB_UPD); 2181 break; 2182 case ARM::STMIA: 2183 Inst.setOpcode(ARM::SRSIA); 2184 break; 2185 case ARM::STMIA_UPD: 2186 Inst.setOpcode(ARM::SRSIA_UPD); 2187 break; 2188 case ARM::STMIB: 2189 Inst.setOpcode(ARM::SRSIB); 2190 break; 2191 case ARM::STMIB_UPD: 2192 Inst.setOpcode(ARM::SRSIB_UPD); 2193 break; 2194 default: 2195 return MCDisassembler::Fail; 2196 } 2197 2198 // For stores (which become SRS's, the only operand is the mode. 2199 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2200 // Check SRS encoding constraints 2201 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2202 fieldFromInstruction(Insn, 20, 1) == 0)) 2203 return MCDisassembler::Fail; 2204 2205 Inst.addOperand( 2206 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2207 return S; 2208 } 2209 2210 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2211 } 2212 2213 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2214 return MCDisassembler::Fail; 2215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2216 return MCDisassembler::Fail; // Tied 2217 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2218 return MCDisassembler::Fail; 2219 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2220 return MCDisassembler::Fail; 2221 2222 return S; 2223 } 2224 2225 // Check for UNPREDICTABLE predicated ESB instruction 2226 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2227 uint64_t Address, const void *Decoder) { 2228 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2229 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2230 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2231 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2232 2233 DecodeStatus S = MCDisassembler::Success; 2234 2235 Inst.addOperand(MCOperand::createImm(imm8)); 2236 2237 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2238 return MCDisassembler::Fail; 2239 2240 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2241 // so all predicates should be allowed. 2242 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2243 S = MCDisassembler::SoftFail; 2244 2245 return S; 2246 } 2247 2248 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2249 uint64_t Address, const void *Decoder) { 2250 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2251 unsigned M = fieldFromInstruction(Insn, 17, 1); 2252 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2253 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2254 2255 DecodeStatus S = MCDisassembler::Success; 2256 2257 // This decoder is called from multiple location that do not check 2258 // the full encoding is valid before they do. 2259 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2260 fieldFromInstruction(Insn, 16, 1) != 0 || 2261 fieldFromInstruction(Insn, 20, 8) != 0x10) 2262 return MCDisassembler::Fail; 2263 2264 // imod == '01' --> UNPREDICTABLE 2265 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2266 // return failure here. The '01' imod value is unprintable, so there's 2267 // nothing useful we could do even if we returned UNPREDICTABLE. 2268 2269 if (imod == 1) return MCDisassembler::Fail; 2270 2271 if (imod && M) { 2272 Inst.setOpcode(ARM::CPS3p); 2273 Inst.addOperand(MCOperand::createImm(imod)); 2274 Inst.addOperand(MCOperand::createImm(iflags)); 2275 Inst.addOperand(MCOperand::createImm(mode)); 2276 } else if (imod && !M) { 2277 Inst.setOpcode(ARM::CPS2p); 2278 Inst.addOperand(MCOperand::createImm(imod)); 2279 Inst.addOperand(MCOperand::createImm(iflags)); 2280 if (mode) S = MCDisassembler::SoftFail; 2281 } else if (!imod && M) { 2282 Inst.setOpcode(ARM::CPS1p); 2283 Inst.addOperand(MCOperand::createImm(mode)); 2284 if (iflags) S = MCDisassembler::SoftFail; 2285 } else { 2286 // imod == '00' && M == '0' --> UNPREDICTABLE 2287 Inst.setOpcode(ARM::CPS1p); 2288 Inst.addOperand(MCOperand::createImm(mode)); 2289 S = MCDisassembler::SoftFail; 2290 } 2291 2292 return S; 2293 } 2294 2295 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2296 uint64_t Address, const void *Decoder) { 2297 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2298 unsigned M = fieldFromInstruction(Insn, 8, 1); 2299 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2300 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2301 2302 DecodeStatus S = MCDisassembler::Success; 2303 2304 // imod == '01' --> UNPREDICTABLE 2305 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2306 // return failure here. The '01' imod value is unprintable, so there's 2307 // nothing useful we could do even if we returned UNPREDICTABLE. 2308 2309 if (imod == 1) return MCDisassembler::Fail; 2310 2311 if (imod && M) { 2312 Inst.setOpcode(ARM::t2CPS3p); 2313 Inst.addOperand(MCOperand::createImm(imod)); 2314 Inst.addOperand(MCOperand::createImm(iflags)); 2315 Inst.addOperand(MCOperand::createImm(mode)); 2316 } else if (imod && !M) { 2317 Inst.setOpcode(ARM::t2CPS2p); 2318 Inst.addOperand(MCOperand::createImm(imod)); 2319 Inst.addOperand(MCOperand::createImm(iflags)); 2320 if (mode) S = MCDisassembler::SoftFail; 2321 } else if (!imod && M) { 2322 Inst.setOpcode(ARM::t2CPS1p); 2323 Inst.addOperand(MCOperand::createImm(mode)); 2324 if (iflags) S = MCDisassembler::SoftFail; 2325 } else { 2326 // imod == '00' && M == '0' --> this is a HINT instruction 2327 int imm = fieldFromInstruction(Insn, 0, 8); 2328 // HINT are defined only for immediate in [0..4] 2329 if(imm > 4) return MCDisassembler::Fail; 2330 Inst.setOpcode(ARM::t2HINT); 2331 Inst.addOperand(MCOperand::createImm(imm)); 2332 } 2333 2334 return S; 2335 } 2336 2337 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2338 uint64_t Address, const void *Decoder) { 2339 DecodeStatus S = MCDisassembler::Success; 2340 2341 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2342 unsigned imm = 0; 2343 2344 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2345 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2346 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2347 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2348 2349 if (Inst.getOpcode() == ARM::t2MOVTi16) 2350 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2351 return MCDisassembler::Fail; 2352 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2353 return MCDisassembler::Fail; 2354 2355 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2356 Inst.addOperand(MCOperand::createImm(imm)); 2357 2358 return S; 2359 } 2360 2361 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2362 uint64_t Address, const void *Decoder) { 2363 DecodeStatus S = MCDisassembler::Success; 2364 2365 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2366 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2367 unsigned imm = 0; 2368 2369 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2370 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2371 2372 if (Inst.getOpcode() == ARM::MOVTi16) 2373 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2374 return MCDisassembler::Fail; 2375 2376 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2377 return MCDisassembler::Fail; 2378 2379 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2380 Inst.addOperand(MCOperand::createImm(imm)); 2381 2382 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2383 return MCDisassembler::Fail; 2384 2385 return S; 2386 } 2387 2388 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2389 uint64_t Address, const void *Decoder) { 2390 DecodeStatus S = MCDisassembler::Success; 2391 2392 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2393 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2394 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2395 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2396 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2397 2398 if (pred == 0xF) 2399 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2400 2401 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2402 return MCDisassembler::Fail; 2403 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2404 return MCDisassembler::Fail; 2405 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2406 return MCDisassembler::Fail; 2407 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2408 return MCDisassembler::Fail; 2409 2410 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2411 return MCDisassembler::Fail; 2412 2413 return S; 2414 } 2415 2416 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2417 uint64_t Address, const void *Decoder) { 2418 DecodeStatus S = MCDisassembler::Success; 2419 2420 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2421 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2422 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2423 2424 if (Pred == 0xF) 2425 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2426 2427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2428 return MCDisassembler::Fail; 2429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2430 return MCDisassembler::Fail; 2431 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2432 return MCDisassembler::Fail; 2433 2434 return S; 2435 } 2436 2437 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2438 uint64_t Address, const void *Decoder) { 2439 DecodeStatus S = MCDisassembler::Success; 2440 2441 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2442 2443 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2444 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2445 2446 if (!FeatureBits[ARM::HasV8_1aOps] || 2447 !FeatureBits[ARM::HasV8Ops]) 2448 return MCDisassembler::Fail; 2449 2450 // Decoder can be called from DecodeTST, which does not check the full 2451 // encoding is valid. 2452 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2453 fieldFromInstruction(Insn, 4,4) != 0) 2454 return MCDisassembler::Fail; 2455 if (fieldFromInstruction(Insn, 10,10) != 0 || 2456 fieldFromInstruction(Insn, 0,4) != 0) 2457 S = MCDisassembler::SoftFail; 2458 2459 Inst.setOpcode(ARM::SETPAN); 2460 Inst.addOperand(MCOperand::createImm(Imm)); 2461 2462 return S; 2463 } 2464 2465 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2466 uint64_t Address, const void *Decoder) { 2467 DecodeStatus S = MCDisassembler::Success; 2468 2469 unsigned add = fieldFromInstruction(Val, 12, 1); 2470 unsigned imm = fieldFromInstruction(Val, 0, 12); 2471 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2472 2473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2474 return MCDisassembler::Fail; 2475 2476 if (!add) imm *= -1; 2477 if (imm == 0 && !add) imm = INT32_MIN; 2478 Inst.addOperand(MCOperand::createImm(imm)); 2479 if (Rn == 15) 2480 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2481 2482 return S; 2483 } 2484 2485 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2486 uint64_t Address, const void *Decoder) { 2487 DecodeStatus S = MCDisassembler::Success; 2488 2489 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2490 // U == 1 to add imm, 0 to subtract it. 2491 unsigned U = fieldFromInstruction(Val, 8, 1); 2492 unsigned imm = fieldFromInstruction(Val, 0, 8); 2493 2494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2495 return MCDisassembler::Fail; 2496 2497 if (U) 2498 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2499 else 2500 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2501 2502 return S; 2503 } 2504 2505 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2506 uint64_t Address, const void *Decoder) { 2507 DecodeStatus S = MCDisassembler::Success; 2508 2509 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2510 // U == 1 to add imm, 0 to subtract it. 2511 unsigned U = fieldFromInstruction(Val, 8, 1); 2512 unsigned imm = fieldFromInstruction(Val, 0, 8); 2513 2514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2515 return MCDisassembler::Fail; 2516 2517 if (U) 2518 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2519 else 2520 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2521 2522 return S; 2523 } 2524 2525 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2526 uint64_t Address, const void *Decoder) { 2527 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2528 } 2529 2530 static DecodeStatus 2531 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2532 uint64_t Address, const void *Decoder) { 2533 DecodeStatus Status = MCDisassembler::Success; 2534 2535 // Note the J1 and J2 values are from the encoded instruction. So here 2536 // change them to I1 and I2 values via as documented: 2537 // I1 = NOT(J1 EOR S); 2538 // I2 = NOT(J2 EOR S); 2539 // and build the imm32 with one trailing zero as documented: 2540 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2541 unsigned S = fieldFromInstruction(Insn, 26, 1); 2542 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2543 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2544 unsigned I1 = !(J1 ^ S); 2545 unsigned I2 = !(J2 ^ S); 2546 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2547 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2548 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2549 int imm32 = SignExtend32<25>(tmp << 1); 2550 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2551 true, 4, Inst, Decoder)) 2552 Inst.addOperand(MCOperand::createImm(imm32)); 2553 2554 return Status; 2555 } 2556 2557 static DecodeStatus 2558 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2559 uint64_t Address, const void *Decoder) { 2560 DecodeStatus S = MCDisassembler::Success; 2561 2562 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2563 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2564 2565 if (pred == 0xF) { 2566 Inst.setOpcode(ARM::BLXi); 2567 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2568 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2569 true, 4, Inst, Decoder)) 2570 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2571 return S; 2572 } 2573 2574 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2575 true, 4, Inst, Decoder)) 2576 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2577 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2578 return MCDisassembler::Fail; 2579 2580 return S; 2581 } 2582 2583 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2584 uint64_t Address, const void *Decoder) { 2585 DecodeStatus S = MCDisassembler::Success; 2586 2587 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2588 unsigned align = fieldFromInstruction(Val, 4, 2); 2589 2590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2591 return MCDisassembler::Fail; 2592 if (!align) 2593 Inst.addOperand(MCOperand::createImm(0)); 2594 else 2595 Inst.addOperand(MCOperand::createImm(4 << align)); 2596 2597 return S; 2598 } 2599 2600 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2601 uint64_t Address, const void *Decoder) { 2602 DecodeStatus S = MCDisassembler::Success; 2603 2604 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2605 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2606 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2607 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2608 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2609 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2610 2611 // First output register 2612 switch (Inst.getOpcode()) { 2613 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2614 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2615 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2616 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2617 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2618 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2619 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2620 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2621 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2622 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2623 return MCDisassembler::Fail; 2624 break; 2625 case ARM::VLD2b16: 2626 case ARM::VLD2b32: 2627 case ARM::VLD2b8: 2628 case ARM::VLD2b16wb_fixed: 2629 case ARM::VLD2b16wb_register: 2630 case ARM::VLD2b32wb_fixed: 2631 case ARM::VLD2b32wb_register: 2632 case ARM::VLD2b8wb_fixed: 2633 case ARM::VLD2b8wb_register: 2634 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2635 return MCDisassembler::Fail; 2636 break; 2637 default: 2638 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2639 return MCDisassembler::Fail; 2640 } 2641 2642 // Second output register 2643 switch (Inst.getOpcode()) { 2644 case ARM::VLD3d8: 2645 case ARM::VLD3d16: 2646 case ARM::VLD3d32: 2647 case ARM::VLD3d8_UPD: 2648 case ARM::VLD3d16_UPD: 2649 case ARM::VLD3d32_UPD: 2650 case ARM::VLD4d8: 2651 case ARM::VLD4d16: 2652 case ARM::VLD4d32: 2653 case ARM::VLD4d8_UPD: 2654 case ARM::VLD4d16_UPD: 2655 case ARM::VLD4d32_UPD: 2656 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2657 return MCDisassembler::Fail; 2658 break; 2659 case ARM::VLD3q8: 2660 case ARM::VLD3q16: 2661 case ARM::VLD3q32: 2662 case ARM::VLD3q8_UPD: 2663 case ARM::VLD3q16_UPD: 2664 case ARM::VLD3q32_UPD: 2665 case ARM::VLD4q8: 2666 case ARM::VLD4q16: 2667 case ARM::VLD4q32: 2668 case ARM::VLD4q8_UPD: 2669 case ARM::VLD4q16_UPD: 2670 case ARM::VLD4q32_UPD: 2671 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2672 return MCDisassembler::Fail; 2673 break; 2674 default: 2675 break; 2676 } 2677 2678 // Third output register 2679 switch(Inst.getOpcode()) { 2680 case ARM::VLD3d8: 2681 case ARM::VLD3d16: 2682 case ARM::VLD3d32: 2683 case ARM::VLD3d8_UPD: 2684 case ARM::VLD3d16_UPD: 2685 case ARM::VLD3d32_UPD: 2686 case ARM::VLD4d8: 2687 case ARM::VLD4d16: 2688 case ARM::VLD4d32: 2689 case ARM::VLD4d8_UPD: 2690 case ARM::VLD4d16_UPD: 2691 case ARM::VLD4d32_UPD: 2692 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2693 return MCDisassembler::Fail; 2694 break; 2695 case ARM::VLD3q8: 2696 case ARM::VLD3q16: 2697 case ARM::VLD3q32: 2698 case ARM::VLD3q8_UPD: 2699 case ARM::VLD3q16_UPD: 2700 case ARM::VLD3q32_UPD: 2701 case ARM::VLD4q8: 2702 case ARM::VLD4q16: 2703 case ARM::VLD4q32: 2704 case ARM::VLD4q8_UPD: 2705 case ARM::VLD4q16_UPD: 2706 case ARM::VLD4q32_UPD: 2707 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2708 return MCDisassembler::Fail; 2709 break; 2710 default: 2711 break; 2712 } 2713 2714 // Fourth output register 2715 switch (Inst.getOpcode()) { 2716 case ARM::VLD4d8: 2717 case ARM::VLD4d16: 2718 case ARM::VLD4d32: 2719 case ARM::VLD4d8_UPD: 2720 case ARM::VLD4d16_UPD: 2721 case ARM::VLD4d32_UPD: 2722 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2723 return MCDisassembler::Fail; 2724 break; 2725 case ARM::VLD4q8: 2726 case ARM::VLD4q16: 2727 case ARM::VLD4q32: 2728 case ARM::VLD4q8_UPD: 2729 case ARM::VLD4q16_UPD: 2730 case ARM::VLD4q32_UPD: 2731 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2732 return MCDisassembler::Fail; 2733 break; 2734 default: 2735 break; 2736 } 2737 2738 // Writeback operand 2739 switch (Inst.getOpcode()) { 2740 case ARM::VLD1d8wb_fixed: 2741 case ARM::VLD1d16wb_fixed: 2742 case ARM::VLD1d32wb_fixed: 2743 case ARM::VLD1d64wb_fixed: 2744 case ARM::VLD1d8wb_register: 2745 case ARM::VLD1d16wb_register: 2746 case ARM::VLD1d32wb_register: 2747 case ARM::VLD1d64wb_register: 2748 case ARM::VLD1q8wb_fixed: 2749 case ARM::VLD1q16wb_fixed: 2750 case ARM::VLD1q32wb_fixed: 2751 case ARM::VLD1q64wb_fixed: 2752 case ARM::VLD1q8wb_register: 2753 case ARM::VLD1q16wb_register: 2754 case ARM::VLD1q32wb_register: 2755 case ARM::VLD1q64wb_register: 2756 case ARM::VLD1d8Twb_fixed: 2757 case ARM::VLD1d8Twb_register: 2758 case ARM::VLD1d16Twb_fixed: 2759 case ARM::VLD1d16Twb_register: 2760 case ARM::VLD1d32Twb_fixed: 2761 case ARM::VLD1d32Twb_register: 2762 case ARM::VLD1d64Twb_fixed: 2763 case ARM::VLD1d64Twb_register: 2764 case ARM::VLD1d8Qwb_fixed: 2765 case ARM::VLD1d8Qwb_register: 2766 case ARM::VLD1d16Qwb_fixed: 2767 case ARM::VLD1d16Qwb_register: 2768 case ARM::VLD1d32Qwb_fixed: 2769 case ARM::VLD1d32Qwb_register: 2770 case ARM::VLD1d64Qwb_fixed: 2771 case ARM::VLD1d64Qwb_register: 2772 case ARM::VLD2d8wb_fixed: 2773 case ARM::VLD2d16wb_fixed: 2774 case ARM::VLD2d32wb_fixed: 2775 case ARM::VLD2q8wb_fixed: 2776 case ARM::VLD2q16wb_fixed: 2777 case ARM::VLD2q32wb_fixed: 2778 case ARM::VLD2d8wb_register: 2779 case ARM::VLD2d16wb_register: 2780 case ARM::VLD2d32wb_register: 2781 case ARM::VLD2q8wb_register: 2782 case ARM::VLD2q16wb_register: 2783 case ARM::VLD2q32wb_register: 2784 case ARM::VLD2b8wb_fixed: 2785 case ARM::VLD2b16wb_fixed: 2786 case ARM::VLD2b32wb_fixed: 2787 case ARM::VLD2b8wb_register: 2788 case ARM::VLD2b16wb_register: 2789 case ARM::VLD2b32wb_register: 2790 Inst.addOperand(MCOperand::createImm(0)); 2791 break; 2792 case ARM::VLD3d8_UPD: 2793 case ARM::VLD3d16_UPD: 2794 case ARM::VLD3d32_UPD: 2795 case ARM::VLD3q8_UPD: 2796 case ARM::VLD3q16_UPD: 2797 case ARM::VLD3q32_UPD: 2798 case ARM::VLD4d8_UPD: 2799 case ARM::VLD4d16_UPD: 2800 case ARM::VLD4d32_UPD: 2801 case ARM::VLD4q8_UPD: 2802 case ARM::VLD4q16_UPD: 2803 case ARM::VLD4q32_UPD: 2804 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2805 return MCDisassembler::Fail; 2806 break; 2807 default: 2808 break; 2809 } 2810 2811 // AddrMode6 Base (register+alignment) 2812 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2813 return MCDisassembler::Fail; 2814 2815 // AddrMode6 Offset (register) 2816 switch (Inst.getOpcode()) { 2817 default: 2818 // The below have been updated to have explicit am6offset split 2819 // between fixed and register offset. For those instructions not 2820 // yet updated, we need to add an additional reg0 operand for the 2821 // fixed variant. 2822 // 2823 // The fixed offset encodes as Rm == 0xd, so we check for that. 2824 if (Rm == 0xd) { 2825 Inst.addOperand(MCOperand::createReg(0)); 2826 break; 2827 } 2828 // Fall through to handle the register offset variant. 2829 LLVM_FALLTHROUGH; 2830 case ARM::VLD1d8wb_fixed: 2831 case ARM::VLD1d16wb_fixed: 2832 case ARM::VLD1d32wb_fixed: 2833 case ARM::VLD1d64wb_fixed: 2834 case ARM::VLD1d8Twb_fixed: 2835 case ARM::VLD1d16Twb_fixed: 2836 case ARM::VLD1d32Twb_fixed: 2837 case ARM::VLD1d64Twb_fixed: 2838 case ARM::VLD1d8Qwb_fixed: 2839 case ARM::VLD1d16Qwb_fixed: 2840 case ARM::VLD1d32Qwb_fixed: 2841 case ARM::VLD1d64Qwb_fixed: 2842 case ARM::VLD1d8wb_register: 2843 case ARM::VLD1d16wb_register: 2844 case ARM::VLD1d32wb_register: 2845 case ARM::VLD1d64wb_register: 2846 case ARM::VLD1q8wb_fixed: 2847 case ARM::VLD1q16wb_fixed: 2848 case ARM::VLD1q32wb_fixed: 2849 case ARM::VLD1q64wb_fixed: 2850 case ARM::VLD1q8wb_register: 2851 case ARM::VLD1q16wb_register: 2852 case ARM::VLD1q32wb_register: 2853 case ARM::VLD1q64wb_register: 2854 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2855 // variant encodes Rm == 0xf. Anything else is a register offset post- 2856 // increment and we need to add the register operand to the instruction. 2857 if (Rm != 0xD && Rm != 0xF && 2858 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2859 return MCDisassembler::Fail; 2860 break; 2861 case ARM::VLD2d8wb_fixed: 2862 case ARM::VLD2d16wb_fixed: 2863 case ARM::VLD2d32wb_fixed: 2864 case ARM::VLD2b8wb_fixed: 2865 case ARM::VLD2b16wb_fixed: 2866 case ARM::VLD2b32wb_fixed: 2867 case ARM::VLD2q8wb_fixed: 2868 case ARM::VLD2q16wb_fixed: 2869 case ARM::VLD2q32wb_fixed: 2870 break; 2871 } 2872 2873 return S; 2874 } 2875 2876 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2877 uint64_t Address, const void *Decoder) { 2878 unsigned type = fieldFromInstruction(Insn, 8, 4); 2879 unsigned align = fieldFromInstruction(Insn, 4, 2); 2880 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2881 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2882 if (type == 10 && align == 3) return MCDisassembler::Fail; 2883 2884 unsigned load = fieldFromInstruction(Insn, 21, 1); 2885 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2886 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2887 } 2888 2889 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2890 uint64_t Address, const void *Decoder) { 2891 unsigned size = fieldFromInstruction(Insn, 6, 2); 2892 if (size == 3) return MCDisassembler::Fail; 2893 2894 unsigned type = fieldFromInstruction(Insn, 8, 4); 2895 unsigned align = fieldFromInstruction(Insn, 4, 2); 2896 if (type == 8 && align == 3) return MCDisassembler::Fail; 2897 if (type == 9 && align == 3) return MCDisassembler::Fail; 2898 2899 unsigned load = fieldFromInstruction(Insn, 21, 1); 2900 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2901 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2902 } 2903 2904 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2905 uint64_t Address, const void *Decoder) { 2906 unsigned size = fieldFromInstruction(Insn, 6, 2); 2907 if (size == 3) return MCDisassembler::Fail; 2908 2909 unsigned align = fieldFromInstruction(Insn, 4, 2); 2910 if (align & 2) return MCDisassembler::Fail; 2911 2912 unsigned load = fieldFromInstruction(Insn, 21, 1); 2913 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2914 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2915 } 2916 2917 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2918 uint64_t Address, const void *Decoder) { 2919 unsigned size = fieldFromInstruction(Insn, 6, 2); 2920 if (size == 3) return MCDisassembler::Fail; 2921 2922 unsigned load = fieldFromInstruction(Insn, 21, 1); 2923 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2924 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2925 } 2926 2927 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2928 uint64_t Address, const void *Decoder) { 2929 DecodeStatus S = MCDisassembler::Success; 2930 2931 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2932 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2933 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2934 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2935 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2936 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2937 2938 // Writeback Operand 2939 switch (Inst.getOpcode()) { 2940 case ARM::VST1d8wb_fixed: 2941 case ARM::VST1d16wb_fixed: 2942 case ARM::VST1d32wb_fixed: 2943 case ARM::VST1d64wb_fixed: 2944 case ARM::VST1d8wb_register: 2945 case ARM::VST1d16wb_register: 2946 case ARM::VST1d32wb_register: 2947 case ARM::VST1d64wb_register: 2948 case ARM::VST1q8wb_fixed: 2949 case ARM::VST1q16wb_fixed: 2950 case ARM::VST1q32wb_fixed: 2951 case ARM::VST1q64wb_fixed: 2952 case ARM::VST1q8wb_register: 2953 case ARM::VST1q16wb_register: 2954 case ARM::VST1q32wb_register: 2955 case ARM::VST1q64wb_register: 2956 case ARM::VST1d8Twb_fixed: 2957 case ARM::VST1d16Twb_fixed: 2958 case ARM::VST1d32Twb_fixed: 2959 case ARM::VST1d64Twb_fixed: 2960 case ARM::VST1d8Twb_register: 2961 case ARM::VST1d16Twb_register: 2962 case ARM::VST1d32Twb_register: 2963 case ARM::VST1d64Twb_register: 2964 case ARM::VST1d8Qwb_fixed: 2965 case ARM::VST1d16Qwb_fixed: 2966 case ARM::VST1d32Qwb_fixed: 2967 case ARM::VST1d64Qwb_fixed: 2968 case ARM::VST1d8Qwb_register: 2969 case ARM::VST1d16Qwb_register: 2970 case ARM::VST1d32Qwb_register: 2971 case ARM::VST1d64Qwb_register: 2972 case ARM::VST2d8wb_fixed: 2973 case ARM::VST2d16wb_fixed: 2974 case ARM::VST2d32wb_fixed: 2975 case ARM::VST2d8wb_register: 2976 case ARM::VST2d16wb_register: 2977 case ARM::VST2d32wb_register: 2978 case ARM::VST2q8wb_fixed: 2979 case ARM::VST2q16wb_fixed: 2980 case ARM::VST2q32wb_fixed: 2981 case ARM::VST2q8wb_register: 2982 case ARM::VST2q16wb_register: 2983 case ARM::VST2q32wb_register: 2984 case ARM::VST2b8wb_fixed: 2985 case ARM::VST2b16wb_fixed: 2986 case ARM::VST2b32wb_fixed: 2987 case ARM::VST2b8wb_register: 2988 case ARM::VST2b16wb_register: 2989 case ARM::VST2b32wb_register: 2990 if (Rm == 0xF) 2991 return MCDisassembler::Fail; 2992 Inst.addOperand(MCOperand::createImm(0)); 2993 break; 2994 case ARM::VST3d8_UPD: 2995 case ARM::VST3d16_UPD: 2996 case ARM::VST3d32_UPD: 2997 case ARM::VST3q8_UPD: 2998 case ARM::VST3q16_UPD: 2999 case ARM::VST3q32_UPD: 3000 case ARM::VST4d8_UPD: 3001 case ARM::VST4d16_UPD: 3002 case ARM::VST4d32_UPD: 3003 case ARM::VST4q8_UPD: 3004 case ARM::VST4q16_UPD: 3005 case ARM::VST4q32_UPD: 3006 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3007 return MCDisassembler::Fail; 3008 break; 3009 default: 3010 break; 3011 } 3012 3013 // AddrMode6 Base (register+alignment) 3014 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3015 return MCDisassembler::Fail; 3016 3017 // AddrMode6 Offset (register) 3018 switch (Inst.getOpcode()) { 3019 default: 3020 if (Rm == 0xD) 3021 Inst.addOperand(MCOperand::createReg(0)); 3022 else if (Rm != 0xF) { 3023 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3024 return MCDisassembler::Fail; 3025 } 3026 break; 3027 case ARM::VST1d8wb_fixed: 3028 case ARM::VST1d16wb_fixed: 3029 case ARM::VST1d32wb_fixed: 3030 case ARM::VST1d64wb_fixed: 3031 case ARM::VST1q8wb_fixed: 3032 case ARM::VST1q16wb_fixed: 3033 case ARM::VST1q32wb_fixed: 3034 case ARM::VST1q64wb_fixed: 3035 case ARM::VST1d8Twb_fixed: 3036 case ARM::VST1d16Twb_fixed: 3037 case ARM::VST1d32Twb_fixed: 3038 case ARM::VST1d64Twb_fixed: 3039 case ARM::VST1d8Qwb_fixed: 3040 case ARM::VST1d16Qwb_fixed: 3041 case ARM::VST1d32Qwb_fixed: 3042 case ARM::VST1d64Qwb_fixed: 3043 case ARM::VST2d8wb_fixed: 3044 case ARM::VST2d16wb_fixed: 3045 case ARM::VST2d32wb_fixed: 3046 case ARM::VST2q8wb_fixed: 3047 case ARM::VST2q16wb_fixed: 3048 case ARM::VST2q32wb_fixed: 3049 case ARM::VST2b8wb_fixed: 3050 case ARM::VST2b16wb_fixed: 3051 case ARM::VST2b32wb_fixed: 3052 break; 3053 } 3054 3055 // First input register 3056 switch (Inst.getOpcode()) { 3057 case ARM::VST1q16: 3058 case ARM::VST1q32: 3059 case ARM::VST1q64: 3060 case ARM::VST1q8: 3061 case ARM::VST1q16wb_fixed: 3062 case ARM::VST1q16wb_register: 3063 case ARM::VST1q32wb_fixed: 3064 case ARM::VST1q32wb_register: 3065 case ARM::VST1q64wb_fixed: 3066 case ARM::VST1q64wb_register: 3067 case ARM::VST1q8wb_fixed: 3068 case ARM::VST1q8wb_register: 3069 case ARM::VST2d16: 3070 case ARM::VST2d32: 3071 case ARM::VST2d8: 3072 case ARM::VST2d16wb_fixed: 3073 case ARM::VST2d16wb_register: 3074 case ARM::VST2d32wb_fixed: 3075 case ARM::VST2d32wb_register: 3076 case ARM::VST2d8wb_fixed: 3077 case ARM::VST2d8wb_register: 3078 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3079 return MCDisassembler::Fail; 3080 break; 3081 case ARM::VST2b16: 3082 case ARM::VST2b32: 3083 case ARM::VST2b8: 3084 case ARM::VST2b16wb_fixed: 3085 case ARM::VST2b16wb_register: 3086 case ARM::VST2b32wb_fixed: 3087 case ARM::VST2b32wb_register: 3088 case ARM::VST2b8wb_fixed: 3089 case ARM::VST2b8wb_register: 3090 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3091 return MCDisassembler::Fail; 3092 break; 3093 default: 3094 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3095 return MCDisassembler::Fail; 3096 } 3097 3098 // Second input register 3099 switch (Inst.getOpcode()) { 3100 case ARM::VST3d8: 3101 case ARM::VST3d16: 3102 case ARM::VST3d32: 3103 case ARM::VST3d8_UPD: 3104 case ARM::VST3d16_UPD: 3105 case ARM::VST3d32_UPD: 3106 case ARM::VST4d8: 3107 case ARM::VST4d16: 3108 case ARM::VST4d32: 3109 case ARM::VST4d8_UPD: 3110 case ARM::VST4d16_UPD: 3111 case ARM::VST4d32_UPD: 3112 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3113 return MCDisassembler::Fail; 3114 break; 3115 case ARM::VST3q8: 3116 case ARM::VST3q16: 3117 case ARM::VST3q32: 3118 case ARM::VST3q8_UPD: 3119 case ARM::VST3q16_UPD: 3120 case ARM::VST3q32_UPD: 3121 case ARM::VST4q8: 3122 case ARM::VST4q16: 3123 case ARM::VST4q32: 3124 case ARM::VST4q8_UPD: 3125 case ARM::VST4q16_UPD: 3126 case ARM::VST4q32_UPD: 3127 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3128 return MCDisassembler::Fail; 3129 break; 3130 default: 3131 break; 3132 } 3133 3134 // Third input register 3135 switch (Inst.getOpcode()) { 3136 case ARM::VST3d8: 3137 case ARM::VST3d16: 3138 case ARM::VST3d32: 3139 case ARM::VST3d8_UPD: 3140 case ARM::VST3d16_UPD: 3141 case ARM::VST3d32_UPD: 3142 case ARM::VST4d8: 3143 case ARM::VST4d16: 3144 case ARM::VST4d32: 3145 case ARM::VST4d8_UPD: 3146 case ARM::VST4d16_UPD: 3147 case ARM::VST4d32_UPD: 3148 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3149 return MCDisassembler::Fail; 3150 break; 3151 case ARM::VST3q8: 3152 case ARM::VST3q16: 3153 case ARM::VST3q32: 3154 case ARM::VST3q8_UPD: 3155 case ARM::VST3q16_UPD: 3156 case ARM::VST3q32_UPD: 3157 case ARM::VST4q8: 3158 case ARM::VST4q16: 3159 case ARM::VST4q32: 3160 case ARM::VST4q8_UPD: 3161 case ARM::VST4q16_UPD: 3162 case ARM::VST4q32_UPD: 3163 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3164 return MCDisassembler::Fail; 3165 break; 3166 default: 3167 break; 3168 } 3169 3170 // Fourth input register 3171 switch (Inst.getOpcode()) { 3172 case ARM::VST4d8: 3173 case ARM::VST4d16: 3174 case ARM::VST4d32: 3175 case ARM::VST4d8_UPD: 3176 case ARM::VST4d16_UPD: 3177 case ARM::VST4d32_UPD: 3178 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3179 return MCDisassembler::Fail; 3180 break; 3181 case ARM::VST4q8: 3182 case ARM::VST4q16: 3183 case ARM::VST4q32: 3184 case ARM::VST4q8_UPD: 3185 case ARM::VST4q16_UPD: 3186 case ARM::VST4q32_UPD: 3187 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3188 return MCDisassembler::Fail; 3189 break; 3190 default: 3191 break; 3192 } 3193 3194 return S; 3195 } 3196 3197 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3198 uint64_t Address, const void *Decoder) { 3199 DecodeStatus S = MCDisassembler::Success; 3200 3201 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3202 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3203 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3204 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3205 unsigned align = fieldFromInstruction(Insn, 4, 1); 3206 unsigned size = fieldFromInstruction(Insn, 6, 2); 3207 3208 if (size == 0 && align == 1) 3209 return MCDisassembler::Fail; 3210 align *= (1 << size); 3211 3212 switch (Inst.getOpcode()) { 3213 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3214 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3215 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3216 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3217 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3218 return MCDisassembler::Fail; 3219 break; 3220 default: 3221 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3222 return MCDisassembler::Fail; 3223 break; 3224 } 3225 if (Rm != 0xF) { 3226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3227 return MCDisassembler::Fail; 3228 } 3229 3230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3231 return MCDisassembler::Fail; 3232 Inst.addOperand(MCOperand::createImm(align)); 3233 3234 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3235 // variant encodes Rm == 0xf. Anything else is a register offset post- 3236 // increment and we need to add the register operand to the instruction. 3237 if (Rm != 0xD && Rm != 0xF && 3238 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3239 return MCDisassembler::Fail; 3240 3241 return S; 3242 } 3243 3244 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3245 uint64_t Address, const void *Decoder) { 3246 DecodeStatus S = MCDisassembler::Success; 3247 3248 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3249 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3250 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3251 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3252 unsigned align = fieldFromInstruction(Insn, 4, 1); 3253 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3254 align *= 2*size; 3255 3256 switch (Inst.getOpcode()) { 3257 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3258 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3259 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3260 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3261 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3262 return MCDisassembler::Fail; 3263 break; 3264 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3265 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3266 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3267 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3268 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3269 return MCDisassembler::Fail; 3270 break; 3271 default: 3272 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3273 return MCDisassembler::Fail; 3274 break; 3275 } 3276 3277 if (Rm != 0xF) 3278 Inst.addOperand(MCOperand::createImm(0)); 3279 3280 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3281 return MCDisassembler::Fail; 3282 Inst.addOperand(MCOperand::createImm(align)); 3283 3284 if (Rm != 0xD && Rm != 0xF) { 3285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3286 return MCDisassembler::Fail; 3287 } 3288 3289 return S; 3290 } 3291 3292 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3293 uint64_t Address, const void *Decoder) { 3294 DecodeStatus S = MCDisassembler::Success; 3295 3296 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3297 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3298 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3299 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3300 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3301 3302 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3303 return MCDisassembler::Fail; 3304 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3305 return MCDisassembler::Fail; 3306 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3307 return MCDisassembler::Fail; 3308 if (Rm != 0xF) { 3309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3310 return MCDisassembler::Fail; 3311 } 3312 3313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3314 return MCDisassembler::Fail; 3315 Inst.addOperand(MCOperand::createImm(0)); 3316 3317 if (Rm == 0xD) 3318 Inst.addOperand(MCOperand::createReg(0)); 3319 else if (Rm != 0xF) { 3320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3321 return MCDisassembler::Fail; 3322 } 3323 3324 return S; 3325 } 3326 3327 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3328 uint64_t Address, const void *Decoder) { 3329 DecodeStatus S = MCDisassembler::Success; 3330 3331 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3332 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3333 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3334 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3335 unsigned size = fieldFromInstruction(Insn, 6, 2); 3336 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3337 unsigned align = fieldFromInstruction(Insn, 4, 1); 3338 3339 if (size == 0x3) { 3340 if (align == 0) 3341 return MCDisassembler::Fail; 3342 align = 16; 3343 } else { 3344 if (size == 2) { 3345 align *= 8; 3346 } else { 3347 size = 1 << size; 3348 align *= 4*size; 3349 } 3350 } 3351 3352 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3353 return MCDisassembler::Fail; 3354 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3357 return MCDisassembler::Fail; 3358 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3359 return MCDisassembler::Fail; 3360 if (Rm != 0xF) { 3361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3362 return MCDisassembler::Fail; 3363 } 3364 3365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 Inst.addOperand(MCOperand::createImm(align)); 3368 3369 if (Rm == 0xD) 3370 Inst.addOperand(MCOperand::createReg(0)); 3371 else if (Rm != 0xF) { 3372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3373 return MCDisassembler::Fail; 3374 } 3375 3376 return S; 3377 } 3378 3379 static DecodeStatus 3380 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3381 uint64_t Address, const void *Decoder) { 3382 DecodeStatus S = MCDisassembler::Success; 3383 3384 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3385 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3386 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3387 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3388 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3389 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3390 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3391 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3392 3393 if (Q) { 3394 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3395 return MCDisassembler::Fail; 3396 } else { 3397 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3398 return MCDisassembler::Fail; 3399 } 3400 3401 Inst.addOperand(MCOperand::createImm(imm)); 3402 3403 switch (Inst.getOpcode()) { 3404 case ARM::VORRiv4i16: 3405 case ARM::VORRiv2i32: 3406 case ARM::VBICiv4i16: 3407 case ARM::VBICiv2i32: 3408 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 break; 3411 case ARM::VORRiv8i16: 3412 case ARM::VORRiv4i32: 3413 case ARM::VBICiv8i16: 3414 case ARM::VBICiv4i32: 3415 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3416 return MCDisassembler::Fail; 3417 break; 3418 default: 3419 break; 3420 } 3421 3422 return S; 3423 } 3424 3425 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3426 uint64_t Address, const void *Decoder) { 3427 DecodeStatus S = MCDisassembler::Success; 3428 3429 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3430 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3431 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3432 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3433 unsigned size = fieldFromInstruction(Insn, 18, 2); 3434 3435 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3436 return MCDisassembler::Fail; 3437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3438 return MCDisassembler::Fail; 3439 Inst.addOperand(MCOperand::createImm(8 << size)); 3440 3441 return S; 3442 } 3443 3444 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3445 uint64_t Address, const void *Decoder) { 3446 Inst.addOperand(MCOperand::createImm(8 - Val)); 3447 return MCDisassembler::Success; 3448 } 3449 3450 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3451 uint64_t Address, const void *Decoder) { 3452 Inst.addOperand(MCOperand::createImm(16 - Val)); 3453 return MCDisassembler::Success; 3454 } 3455 3456 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3457 uint64_t Address, const void *Decoder) { 3458 Inst.addOperand(MCOperand::createImm(32 - Val)); 3459 return MCDisassembler::Success; 3460 } 3461 3462 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3463 uint64_t Address, const void *Decoder) { 3464 Inst.addOperand(MCOperand::createImm(64 - Val)); 3465 return MCDisassembler::Success; 3466 } 3467 3468 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3469 uint64_t Address, const void *Decoder) { 3470 DecodeStatus S = MCDisassembler::Success; 3471 3472 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3473 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3474 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3475 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3476 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3477 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3478 unsigned op = fieldFromInstruction(Insn, 6, 1); 3479 3480 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3481 return MCDisassembler::Fail; 3482 if (op) { 3483 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3484 return MCDisassembler::Fail; // Writeback 3485 } 3486 3487 switch (Inst.getOpcode()) { 3488 case ARM::VTBL2: 3489 case ARM::VTBX2: 3490 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3491 return MCDisassembler::Fail; 3492 break; 3493 default: 3494 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3495 return MCDisassembler::Fail; 3496 } 3497 3498 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3499 return MCDisassembler::Fail; 3500 3501 return S; 3502 } 3503 3504 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3505 uint64_t Address, const void *Decoder) { 3506 DecodeStatus S = MCDisassembler::Success; 3507 3508 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3509 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3510 3511 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3512 return MCDisassembler::Fail; 3513 3514 switch(Inst.getOpcode()) { 3515 default: 3516 return MCDisassembler::Fail; 3517 case ARM::tADR: 3518 break; // tADR does not explicitly represent the PC as an operand. 3519 case ARM::tADDrSPi: 3520 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3521 break; 3522 } 3523 3524 Inst.addOperand(MCOperand::createImm(imm)); 3525 return S; 3526 } 3527 3528 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3529 uint64_t Address, const void *Decoder) { 3530 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3531 true, 2, Inst, Decoder)) 3532 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3533 return MCDisassembler::Success; 3534 } 3535 3536 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3537 uint64_t Address, const void *Decoder) { 3538 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3539 true, 4, Inst, Decoder)) 3540 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3541 return MCDisassembler::Success; 3542 } 3543 3544 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3545 uint64_t Address, const void *Decoder) { 3546 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3547 true, 2, Inst, Decoder)) 3548 Inst.addOperand(MCOperand::createImm(Val << 1)); 3549 return MCDisassembler::Success; 3550 } 3551 3552 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3553 uint64_t Address, const void *Decoder) { 3554 DecodeStatus S = MCDisassembler::Success; 3555 3556 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3557 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3558 3559 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3560 return MCDisassembler::Fail; 3561 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3562 return MCDisassembler::Fail; 3563 3564 return S; 3565 } 3566 3567 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3568 uint64_t Address, const void *Decoder) { 3569 DecodeStatus S = MCDisassembler::Success; 3570 3571 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3572 unsigned imm = fieldFromInstruction(Val, 3, 5); 3573 3574 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3575 return MCDisassembler::Fail; 3576 Inst.addOperand(MCOperand::createImm(imm)); 3577 3578 return S; 3579 } 3580 3581 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3582 uint64_t Address, const void *Decoder) { 3583 unsigned imm = Val << 2; 3584 3585 Inst.addOperand(MCOperand::createImm(imm)); 3586 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3587 3588 return MCDisassembler::Success; 3589 } 3590 3591 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3592 uint64_t Address, const void *Decoder) { 3593 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3594 Inst.addOperand(MCOperand::createImm(Val)); 3595 3596 return MCDisassembler::Success; 3597 } 3598 3599 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3600 uint64_t Address, const void *Decoder) { 3601 DecodeStatus S = MCDisassembler::Success; 3602 3603 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3604 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3605 unsigned imm = fieldFromInstruction(Val, 0, 2); 3606 3607 // Thumb stores cannot use PC as dest register. 3608 switch (Inst.getOpcode()) { 3609 case ARM::t2STRHs: 3610 case ARM::t2STRBs: 3611 case ARM::t2STRs: 3612 if (Rn == 15) 3613 return MCDisassembler::Fail; 3614 break; 3615 default: 3616 break; 3617 } 3618 3619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3620 return MCDisassembler::Fail; 3621 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3622 return MCDisassembler::Fail; 3623 Inst.addOperand(MCOperand::createImm(imm)); 3624 3625 return S; 3626 } 3627 3628 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3629 uint64_t Address, const void *Decoder) { 3630 DecodeStatus S = MCDisassembler::Success; 3631 3632 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3633 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3634 3635 const FeatureBitset &featureBits = 3636 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3637 3638 bool hasMP = featureBits[ARM::FeatureMP]; 3639 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3640 3641 if (Rn == 15) { 3642 switch (Inst.getOpcode()) { 3643 case ARM::t2LDRBs: 3644 Inst.setOpcode(ARM::t2LDRBpci); 3645 break; 3646 case ARM::t2LDRHs: 3647 Inst.setOpcode(ARM::t2LDRHpci); 3648 break; 3649 case ARM::t2LDRSHs: 3650 Inst.setOpcode(ARM::t2LDRSHpci); 3651 break; 3652 case ARM::t2LDRSBs: 3653 Inst.setOpcode(ARM::t2LDRSBpci); 3654 break; 3655 case ARM::t2LDRs: 3656 Inst.setOpcode(ARM::t2LDRpci); 3657 break; 3658 case ARM::t2PLDs: 3659 Inst.setOpcode(ARM::t2PLDpci); 3660 break; 3661 case ARM::t2PLIs: 3662 Inst.setOpcode(ARM::t2PLIpci); 3663 break; 3664 default: 3665 return MCDisassembler::Fail; 3666 } 3667 3668 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3669 } 3670 3671 if (Rt == 15) { 3672 switch (Inst.getOpcode()) { 3673 case ARM::t2LDRSHs: 3674 return MCDisassembler::Fail; 3675 case ARM::t2LDRHs: 3676 Inst.setOpcode(ARM::t2PLDWs); 3677 break; 3678 case ARM::t2LDRSBs: 3679 Inst.setOpcode(ARM::t2PLIs); 3680 break; 3681 default: 3682 break; 3683 } 3684 } 3685 3686 switch (Inst.getOpcode()) { 3687 case ARM::t2PLDs: 3688 break; 3689 case ARM::t2PLIs: 3690 if (!hasV7Ops) 3691 return MCDisassembler::Fail; 3692 break; 3693 case ARM::t2PLDWs: 3694 if (!hasV7Ops || !hasMP) 3695 return MCDisassembler::Fail; 3696 break; 3697 default: 3698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3699 return MCDisassembler::Fail; 3700 } 3701 3702 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3703 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3704 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3705 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3706 return MCDisassembler::Fail; 3707 3708 return S; 3709 } 3710 3711 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3712 uint64_t Address, const void* Decoder) { 3713 DecodeStatus S = MCDisassembler::Success; 3714 3715 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3716 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3717 unsigned U = fieldFromInstruction(Insn, 9, 1); 3718 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3719 imm |= (U << 8); 3720 imm |= (Rn << 9); 3721 unsigned add = fieldFromInstruction(Insn, 9, 1); 3722 3723 const FeatureBitset &featureBits = 3724 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3725 3726 bool hasMP = featureBits[ARM::FeatureMP]; 3727 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3728 3729 if (Rn == 15) { 3730 switch (Inst.getOpcode()) { 3731 case ARM::t2LDRi8: 3732 Inst.setOpcode(ARM::t2LDRpci); 3733 break; 3734 case ARM::t2LDRBi8: 3735 Inst.setOpcode(ARM::t2LDRBpci); 3736 break; 3737 case ARM::t2LDRSBi8: 3738 Inst.setOpcode(ARM::t2LDRSBpci); 3739 break; 3740 case ARM::t2LDRHi8: 3741 Inst.setOpcode(ARM::t2LDRHpci); 3742 break; 3743 case ARM::t2LDRSHi8: 3744 Inst.setOpcode(ARM::t2LDRSHpci); 3745 break; 3746 case ARM::t2PLDi8: 3747 Inst.setOpcode(ARM::t2PLDpci); 3748 break; 3749 case ARM::t2PLIi8: 3750 Inst.setOpcode(ARM::t2PLIpci); 3751 break; 3752 default: 3753 return MCDisassembler::Fail; 3754 } 3755 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3756 } 3757 3758 if (Rt == 15) { 3759 switch (Inst.getOpcode()) { 3760 case ARM::t2LDRSHi8: 3761 return MCDisassembler::Fail; 3762 case ARM::t2LDRHi8: 3763 if (!add) 3764 Inst.setOpcode(ARM::t2PLDWi8); 3765 break; 3766 case ARM::t2LDRSBi8: 3767 Inst.setOpcode(ARM::t2PLIi8); 3768 break; 3769 default: 3770 break; 3771 } 3772 } 3773 3774 switch (Inst.getOpcode()) { 3775 case ARM::t2PLDi8: 3776 break; 3777 case ARM::t2PLIi8: 3778 if (!hasV7Ops) 3779 return MCDisassembler::Fail; 3780 break; 3781 case ARM::t2PLDWi8: 3782 if (!hasV7Ops || !hasMP) 3783 return MCDisassembler::Fail; 3784 break; 3785 default: 3786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3787 return MCDisassembler::Fail; 3788 } 3789 3790 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3791 return MCDisassembler::Fail; 3792 return S; 3793 } 3794 3795 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3796 uint64_t Address, const void* Decoder) { 3797 DecodeStatus S = MCDisassembler::Success; 3798 3799 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3800 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3801 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3802 imm |= (Rn << 13); 3803 3804 const FeatureBitset &featureBits = 3805 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3806 3807 bool hasMP = featureBits[ARM::FeatureMP]; 3808 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3809 3810 if (Rn == 15) { 3811 switch (Inst.getOpcode()) { 3812 case ARM::t2LDRi12: 3813 Inst.setOpcode(ARM::t2LDRpci); 3814 break; 3815 case ARM::t2LDRHi12: 3816 Inst.setOpcode(ARM::t2LDRHpci); 3817 break; 3818 case ARM::t2LDRSHi12: 3819 Inst.setOpcode(ARM::t2LDRSHpci); 3820 break; 3821 case ARM::t2LDRBi12: 3822 Inst.setOpcode(ARM::t2LDRBpci); 3823 break; 3824 case ARM::t2LDRSBi12: 3825 Inst.setOpcode(ARM::t2LDRSBpci); 3826 break; 3827 case ARM::t2PLDi12: 3828 Inst.setOpcode(ARM::t2PLDpci); 3829 break; 3830 case ARM::t2PLIi12: 3831 Inst.setOpcode(ARM::t2PLIpci); 3832 break; 3833 default: 3834 return MCDisassembler::Fail; 3835 } 3836 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3837 } 3838 3839 if (Rt == 15) { 3840 switch (Inst.getOpcode()) { 3841 case ARM::t2LDRSHi12: 3842 return MCDisassembler::Fail; 3843 case ARM::t2LDRHi12: 3844 Inst.setOpcode(ARM::t2PLDWi12); 3845 break; 3846 case ARM::t2LDRSBi12: 3847 Inst.setOpcode(ARM::t2PLIi12); 3848 break; 3849 default: 3850 break; 3851 } 3852 } 3853 3854 switch (Inst.getOpcode()) { 3855 case ARM::t2PLDi12: 3856 break; 3857 case ARM::t2PLIi12: 3858 if (!hasV7Ops) 3859 return MCDisassembler::Fail; 3860 break; 3861 case ARM::t2PLDWi12: 3862 if (!hasV7Ops || !hasMP) 3863 return MCDisassembler::Fail; 3864 break; 3865 default: 3866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3867 return MCDisassembler::Fail; 3868 } 3869 3870 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3871 return MCDisassembler::Fail; 3872 return S; 3873 } 3874 3875 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3876 uint64_t Address, const void* Decoder) { 3877 DecodeStatus S = MCDisassembler::Success; 3878 3879 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3880 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3881 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3882 imm |= (Rn << 9); 3883 3884 if (Rn == 15) { 3885 switch (Inst.getOpcode()) { 3886 case ARM::t2LDRT: 3887 Inst.setOpcode(ARM::t2LDRpci); 3888 break; 3889 case ARM::t2LDRBT: 3890 Inst.setOpcode(ARM::t2LDRBpci); 3891 break; 3892 case ARM::t2LDRHT: 3893 Inst.setOpcode(ARM::t2LDRHpci); 3894 break; 3895 case ARM::t2LDRSBT: 3896 Inst.setOpcode(ARM::t2LDRSBpci); 3897 break; 3898 case ARM::t2LDRSHT: 3899 Inst.setOpcode(ARM::t2LDRSHpci); 3900 break; 3901 default: 3902 return MCDisassembler::Fail; 3903 } 3904 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3905 } 3906 3907 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3908 return MCDisassembler::Fail; 3909 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3910 return MCDisassembler::Fail; 3911 return S; 3912 } 3913 3914 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3915 uint64_t Address, const void* Decoder) { 3916 DecodeStatus S = MCDisassembler::Success; 3917 3918 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3919 unsigned U = fieldFromInstruction(Insn, 23, 1); 3920 int imm = fieldFromInstruction(Insn, 0, 12); 3921 3922 const FeatureBitset &featureBits = 3923 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3924 3925 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3926 3927 if (Rt == 15) { 3928 switch (Inst.getOpcode()) { 3929 case ARM::t2LDRBpci: 3930 case ARM::t2LDRHpci: 3931 Inst.setOpcode(ARM::t2PLDpci); 3932 break; 3933 case ARM::t2LDRSBpci: 3934 Inst.setOpcode(ARM::t2PLIpci); 3935 break; 3936 case ARM::t2LDRSHpci: 3937 return MCDisassembler::Fail; 3938 default: 3939 break; 3940 } 3941 } 3942 3943 switch(Inst.getOpcode()) { 3944 case ARM::t2PLDpci: 3945 break; 3946 case ARM::t2PLIpci: 3947 if (!hasV7Ops) 3948 return MCDisassembler::Fail; 3949 break; 3950 default: 3951 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3952 return MCDisassembler::Fail; 3953 } 3954 3955 if (!U) { 3956 // Special case for #-0. 3957 if (imm == 0) 3958 imm = INT32_MIN; 3959 else 3960 imm = -imm; 3961 } 3962 Inst.addOperand(MCOperand::createImm(imm)); 3963 3964 return S; 3965 } 3966 3967 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3968 uint64_t Address, const void *Decoder) { 3969 if (Val == 0) 3970 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3971 else { 3972 int imm = Val & 0xFF; 3973 3974 if (!(Val & 0x100)) imm *= -1; 3975 Inst.addOperand(MCOperand::createImm(imm * 4)); 3976 } 3977 3978 return MCDisassembler::Success; 3979 } 3980 3981 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 3982 const void *Decoder) { 3983 if (Val == 0) 3984 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3985 else { 3986 int imm = Val & 0x7F; 3987 3988 if (!(Val & 0x80)) 3989 imm *= -1; 3990 Inst.addOperand(MCOperand::createImm(imm * 4)); 3991 } 3992 3993 return MCDisassembler::Success; 3994 } 3995 3996 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3997 uint64_t Address, const void *Decoder) { 3998 DecodeStatus S = MCDisassembler::Success; 3999 4000 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4001 unsigned imm = fieldFromInstruction(Val, 0, 9); 4002 4003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4004 return MCDisassembler::Fail; 4005 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4006 return MCDisassembler::Fail; 4007 4008 return S; 4009 } 4010 4011 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4012 uint64_t Address, 4013 const void *Decoder) { 4014 DecodeStatus S = MCDisassembler::Success; 4015 4016 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4017 unsigned imm = fieldFromInstruction(Val, 0, 8); 4018 4019 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4022 return MCDisassembler::Fail; 4023 4024 return S; 4025 } 4026 4027 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4028 uint64_t Address, const void *Decoder) { 4029 DecodeStatus S = MCDisassembler::Success; 4030 4031 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4032 unsigned imm = fieldFromInstruction(Val, 0, 8); 4033 4034 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4035 return MCDisassembler::Fail; 4036 4037 Inst.addOperand(MCOperand::createImm(imm)); 4038 4039 return S; 4040 } 4041 4042 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4043 uint64_t Address, const void *Decoder) { 4044 int imm = Val & 0xFF; 4045 if (Val == 0) 4046 imm = INT32_MIN; 4047 else if (!(Val & 0x100)) 4048 imm *= -1; 4049 Inst.addOperand(MCOperand::createImm(imm)); 4050 4051 return MCDisassembler::Success; 4052 } 4053 4054 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4055 uint64_t Address, const void *Decoder) { 4056 DecodeStatus S = MCDisassembler::Success; 4057 4058 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4059 unsigned imm = fieldFromInstruction(Val, 0, 9); 4060 4061 // Thumb stores cannot use PC as dest register. 4062 switch (Inst.getOpcode()) { 4063 case ARM::t2STRT: 4064 case ARM::t2STRBT: 4065 case ARM::t2STRHT: 4066 case ARM::t2STRi8: 4067 case ARM::t2STRHi8: 4068 case ARM::t2STRBi8: 4069 if (Rn == 15) 4070 return MCDisassembler::Fail; 4071 break; 4072 default: 4073 break; 4074 } 4075 4076 // Some instructions always use an additive offset. 4077 switch (Inst.getOpcode()) { 4078 case ARM::t2LDRT: 4079 case ARM::t2LDRBT: 4080 case ARM::t2LDRHT: 4081 case ARM::t2LDRSBT: 4082 case ARM::t2LDRSHT: 4083 case ARM::t2STRT: 4084 case ARM::t2STRBT: 4085 case ARM::t2STRHT: 4086 imm |= 0x100; 4087 break; 4088 default: 4089 break; 4090 } 4091 4092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4093 return MCDisassembler::Fail; 4094 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4095 return MCDisassembler::Fail; 4096 4097 return S; 4098 } 4099 4100 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4101 uint64_t Address, const void *Decoder) { 4102 DecodeStatus S = MCDisassembler::Success; 4103 4104 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4105 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4106 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4107 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4108 addr |= Rn << 9; 4109 unsigned load = fieldFromInstruction(Insn, 20, 1); 4110 4111 if (Rn == 15) { 4112 switch (Inst.getOpcode()) { 4113 case ARM::t2LDR_PRE: 4114 case ARM::t2LDR_POST: 4115 Inst.setOpcode(ARM::t2LDRpci); 4116 break; 4117 case ARM::t2LDRB_PRE: 4118 case ARM::t2LDRB_POST: 4119 Inst.setOpcode(ARM::t2LDRBpci); 4120 break; 4121 case ARM::t2LDRH_PRE: 4122 case ARM::t2LDRH_POST: 4123 Inst.setOpcode(ARM::t2LDRHpci); 4124 break; 4125 case ARM::t2LDRSB_PRE: 4126 case ARM::t2LDRSB_POST: 4127 if (Rt == 15) 4128 Inst.setOpcode(ARM::t2PLIpci); 4129 else 4130 Inst.setOpcode(ARM::t2LDRSBpci); 4131 break; 4132 case ARM::t2LDRSH_PRE: 4133 case ARM::t2LDRSH_POST: 4134 Inst.setOpcode(ARM::t2LDRSHpci); 4135 break; 4136 default: 4137 return MCDisassembler::Fail; 4138 } 4139 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4140 } 4141 4142 if (!load) { 4143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4144 return MCDisassembler::Fail; 4145 } 4146 4147 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4148 return MCDisassembler::Fail; 4149 4150 if (load) { 4151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4152 return MCDisassembler::Fail; 4153 } 4154 4155 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4156 return MCDisassembler::Fail; 4157 4158 return S; 4159 } 4160 4161 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4162 uint64_t Address, const void *Decoder) { 4163 DecodeStatus S = MCDisassembler::Success; 4164 4165 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4166 unsigned imm = fieldFromInstruction(Val, 0, 12); 4167 4168 // Thumb stores cannot use PC as dest register. 4169 switch (Inst.getOpcode()) { 4170 case ARM::t2STRi12: 4171 case ARM::t2STRBi12: 4172 case ARM::t2STRHi12: 4173 if (Rn == 15) 4174 return MCDisassembler::Fail; 4175 break; 4176 default: 4177 break; 4178 } 4179 4180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4181 return MCDisassembler::Fail; 4182 Inst.addOperand(MCOperand::createImm(imm)); 4183 4184 return S; 4185 } 4186 4187 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4188 uint64_t Address, const void *Decoder) { 4189 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4190 4191 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4192 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4193 Inst.addOperand(MCOperand::createImm(imm)); 4194 4195 return MCDisassembler::Success; 4196 } 4197 4198 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4199 uint64_t Address, const void *Decoder) { 4200 DecodeStatus S = MCDisassembler::Success; 4201 4202 if (Inst.getOpcode() == ARM::tADDrSP) { 4203 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4204 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4205 4206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4207 return MCDisassembler::Fail; 4208 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4210 return MCDisassembler::Fail; 4211 } else if (Inst.getOpcode() == ARM::tADDspr) { 4212 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4213 4214 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4215 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4217 return MCDisassembler::Fail; 4218 } 4219 4220 return S; 4221 } 4222 4223 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4224 uint64_t Address, const void *Decoder) { 4225 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4226 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4227 4228 Inst.addOperand(MCOperand::createImm(imod)); 4229 Inst.addOperand(MCOperand::createImm(flags)); 4230 4231 return MCDisassembler::Success; 4232 } 4233 4234 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4235 uint64_t Address, const void *Decoder) { 4236 DecodeStatus S = MCDisassembler::Success; 4237 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4238 unsigned add = fieldFromInstruction(Insn, 4, 1); 4239 4240 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4241 return MCDisassembler::Fail; 4242 Inst.addOperand(MCOperand::createImm(add)); 4243 4244 return S; 4245 } 4246 4247 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4248 uint64_t Address, const void *Decoder) { 4249 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4250 // Note only one trailing zero not two. Also the J1 and J2 values are from 4251 // the encoded instruction. So here change to I1 and I2 values via: 4252 // I1 = NOT(J1 EOR S); 4253 // I2 = NOT(J2 EOR S); 4254 // and build the imm32 with two trailing zeros as documented: 4255 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4256 unsigned S = (Val >> 23) & 1; 4257 unsigned J1 = (Val >> 22) & 1; 4258 unsigned J2 = (Val >> 21) & 1; 4259 unsigned I1 = !(J1 ^ S); 4260 unsigned I2 = !(J2 ^ S); 4261 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4262 int imm32 = SignExtend32<25>(tmp << 1); 4263 4264 if (!tryAddingSymbolicOperand(Address, 4265 (Address & ~2u) + imm32 + 4, 4266 true, 4, Inst, Decoder)) 4267 Inst.addOperand(MCOperand::createImm(imm32)); 4268 return MCDisassembler::Success; 4269 } 4270 4271 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4272 uint64_t Address, const void *Decoder) { 4273 if (Val == 0xA || Val == 0xB) 4274 return MCDisassembler::Fail; 4275 4276 const FeatureBitset &featureBits = 4277 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4278 4279 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4280 return MCDisassembler::Fail; 4281 4282 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should 4283 // decode as VFP/MVE instructions. 4284 if (featureBits[ARM::HasV8_1MMainlineOps] && 4285 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || 4286 (Val & 0xE) == 0xE)) 4287 return MCDisassembler::Fail; 4288 4289 Inst.addOperand(MCOperand::createImm(Val)); 4290 return MCDisassembler::Success; 4291 } 4292 4293 static DecodeStatus 4294 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4295 uint64_t Address, const void *Decoder) { 4296 DecodeStatus S = MCDisassembler::Success; 4297 4298 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4299 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4300 4301 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4303 return MCDisassembler::Fail; 4304 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4305 return MCDisassembler::Fail; 4306 return S; 4307 } 4308 4309 static DecodeStatus 4310 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4311 uint64_t Address, const void *Decoder) { 4312 DecodeStatus S = MCDisassembler::Success; 4313 4314 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4315 if (pred == 0xE || pred == 0xF) { 4316 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4317 switch (opc) { 4318 default: 4319 return MCDisassembler::Fail; 4320 case 0xf3bf8f4: 4321 Inst.setOpcode(ARM::t2DSB); 4322 break; 4323 case 0xf3bf8f5: 4324 Inst.setOpcode(ARM::t2DMB); 4325 break; 4326 case 0xf3bf8f6: 4327 Inst.setOpcode(ARM::t2ISB); 4328 break; 4329 } 4330 4331 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4332 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4333 } 4334 4335 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4336 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4337 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4338 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4339 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4340 4341 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4342 return MCDisassembler::Fail; 4343 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4344 return MCDisassembler::Fail; 4345 4346 return S; 4347 } 4348 4349 // Decode a shifted immediate operand. These basically consist 4350 // of an 8-bit value, and a 4-bit directive that specifies either 4351 // a splat operation or a rotation. 4352 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4353 uint64_t Address, const void *Decoder) { 4354 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4355 if (ctrl == 0) { 4356 unsigned byte = fieldFromInstruction(Val, 8, 2); 4357 unsigned imm = fieldFromInstruction(Val, 0, 8); 4358 switch (byte) { 4359 case 0: 4360 Inst.addOperand(MCOperand::createImm(imm)); 4361 break; 4362 case 1: 4363 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4364 break; 4365 case 2: 4366 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4367 break; 4368 case 3: 4369 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4370 (imm << 8) | imm)); 4371 break; 4372 } 4373 } else { 4374 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4375 unsigned rot = fieldFromInstruction(Val, 7, 5); 4376 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4377 Inst.addOperand(MCOperand::createImm(imm)); 4378 } 4379 4380 return MCDisassembler::Success; 4381 } 4382 4383 static DecodeStatus 4384 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4385 uint64_t Address, const void *Decoder) { 4386 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4387 true, 2, Inst, Decoder)) 4388 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4389 return MCDisassembler::Success; 4390 } 4391 4392 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4393 uint64_t Address, 4394 const void *Decoder) { 4395 // Val is passed in as S:J1:J2:imm10:imm11 4396 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4397 // the encoded instruction. So here change to I1 and I2 values via: 4398 // I1 = NOT(J1 EOR S); 4399 // I2 = NOT(J2 EOR S); 4400 // and build the imm32 with one trailing zero as documented: 4401 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4402 unsigned S = (Val >> 23) & 1; 4403 unsigned J1 = (Val >> 22) & 1; 4404 unsigned J2 = (Val >> 21) & 1; 4405 unsigned I1 = !(J1 ^ S); 4406 unsigned I2 = !(J2 ^ S); 4407 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4408 int imm32 = SignExtend32<25>(tmp << 1); 4409 4410 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4411 true, 4, Inst, Decoder)) 4412 Inst.addOperand(MCOperand::createImm(imm32)); 4413 return MCDisassembler::Success; 4414 } 4415 4416 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4417 uint64_t Address, const void *Decoder) { 4418 if (Val & ~0xf) 4419 return MCDisassembler::Fail; 4420 4421 Inst.addOperand(MCOperand::createImm(Val)); 4422 return MCDisassembler::Success; 4423 } 4424 4425 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4426 uint64_t Address, const void *Decoder) { 4427 if (Val & ~0xf) 4428 return MCDisassembler::Fail; 4429 4430 Inst.addOperand(MCOperand::createImm(Val)); 4431 return MCDisassembler::Success; 4432 } 4433 4434 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4435 uint64_t Address, const void *Decoder) { 4436 DecodeStatus S = MCDisassembler::Success; 4437 const FeatureBitset &FeatureBits = 4438 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4439 4440 if (FeatureBits[ARM::FeatureMClass]) { 4441 unsigned ValLow = Val & 0xff; 4442 4443 // Validate the SYSm value first. 4444 switch (ValLow) { 4445 case 0: // apsr 4446 case 1: // iapsr 4447 case 2: // eapsr 4448 case 3: // xpsr 4449 case 5: // ipsr 4450 case 6: // epsr 4451 case 7: // iepsr 4452 case 8: // msp 4453 case 9: // psp 4454 case 16: // primask 4455 case 20: // control 4456 break; 4457 case 17: // basepri 4458 case 18: // basepri_max 4459 case 19: // faultmask 4460 if (!(FeatureBits[ARM::HasV7Ops])) 4461 // Values basepri, basepri_max and faultmask are only valid for v7m. 4462 return MCDisassembler::Fail; 4463 break; 4464 case 0x8a: // msplim_ns 4465 case 0x8b: // psplim_ns 4466 case 0x91: // basepri_ns 4467 case 0x93: // faultmask_ns 4468 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4469 return MCDisassembler::Fail; 4470 LLVM_FALLTHROUGH; 4471 case 10: // msplim 4472 case 11: // psplim 4473 case 0x88: // msp_ns 4474 case 0x89: // psp_ns 4475 case 0x90: // primask_ns 4476 case 0x94: // control_ns 4477 case 0x98: // sp_ns 4478 if (!(FeatureBits[ARM::Feature8MSecExt])) 4479 return MCDisassembler::Fail; 4480 break; 4481 default: 4482 // Architecturally defined as unpredictable 4483 S = MCDisassembler::SoftFail; 4484 break; 4485 } 4486 4487 if (Inst.getOpcode() == ARM::t2MSR_M) { 4488 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4489 if (!(FeatureBits[ARM::HasV7Ops])) { 4490 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4491 // unpredictable. 4492 if (Mask != 2) 4493 S = MCDisassembler::SoftFail; 4494 } 4495 else { 4496 // The ARMv7-M architecture stores an additional 2-bit mask value in 4497 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4498 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4499 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4500 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4501 // only if the processor includes the DSP extension. 4502 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4503 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4504 S = MCDisassembler::SoftFail; 4505 } 4506 } 4507 } else { 4508 // A/R class 4509 if (Val == 0) 4510 return MCDisassembler::Fail; 4511 } 4512 Inst.addOperand(MCOperand::createImm(Val)); 4513 return S; 4514 } 4515 4516 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4517 uint64_t Address, const void *Decoder) { 4518 unsigned R = fieldFromInstruction(Val, 5, 1); 4519 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4520 4521 // The table of encodings for these banked registers comes from B9.2.3 of the 4522 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4523 // neater. So by fiat, these values are UNPREDICTABLE: 4524 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4525 return MCDisassembler::Fail; 4526 4527 Inst.addOperand(MCOperand::createImm(Val)); 4528 return MCDisassembler::Success; 4529 } 4530 4531 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4532 uint64_t Address, const void *Decoder) { 4533 DecodeStatus S = MCDisassembler::Success; 4534 4535 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4536 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4537 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4538 4539 if (Rn == 0xF) 4540 S = MCDisassembler::SoftFail; 4541 4542 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4543 return MCDisassembler::Fail; 4544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4545 return MCDisassembler::Fail; 4546 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4547 return MCDisassembler::Fail; 4548 4549 return S; 4550 } 4551 4552 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4553 uint64_t Address, 4554 const void *Decoder) { 4555 DecodeStatus S = MCDisassembler::Success; 4556 4557 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4558 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4559 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4560 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4561 4562 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4563 return MCDisassembler::Fail; 4564 4565 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4566 S = MCDisassembler::SoftFail; 4567 4568 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4569 return MCDisassembler::Fail; 4570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4571 return MCDisassembler::Fail; 4572 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4573 return MCDisassembler::Fail; 4574 4575 return S; 4576 } 4577 4578 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4579 uint64_t Address, const void *Decoder) { 4580 DecodeStatus S = MCDisassembler::Success; 4581 4582 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4583 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4584 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4585 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4586 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4587 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4588 4589 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4590 4591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4592 return MCDisassembler::Fail; 4593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4594 return MCDisassembler::Fail; 4595 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4596 return MCDisassembler::Fail; 4597 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4598 return MCDisassembler::Fail; 4599 4600 return S; 4601 } 4602 4603 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4604 uint64_t Address, const void *Decoder) { 4605 DecodeStatus S = MCDisassembler::Success; 4606 4607 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4608 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4609 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4610 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4611 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4612 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4613 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4614 4615 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4616 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4617 4618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4619 return MCDisassembler::Fail; 4620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4621 return MCDisassembler::Fail; 4622 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4623 return MCDisassembler::Fail; 4624 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4625 return MCDisassembler::Fail; 4626 4627 return S; 4628 } 4629 4630 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4631 uint64_t Address, const void *Decoder) { 4632 DecodeStatus S = MCDisassembler::Success; 4633 4634 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4635 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4636 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4637 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4638 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4639 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4640 4641 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4642 4643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4644 return MCDisassembler::Fail; 4645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4646 return MCDisassembler::Fail; 4647 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4648 return MCDisassembler::Fail; 4649 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4650 return MCDisassembler::Fail; 4651 4652 return S; 4653 } 4654 4655 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4656 uint64_t Address, const void *Decoder) { 4657 DecodeStatus S = MCDisassembler::Success; 4658 4659 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4660 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4661 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4662 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4663 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4664 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4665 4666 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4667 4668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4669 return MCDisassembler::Fail; 4670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4671 return MCDisassembler::Fail; 4672 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4673 return MCDisassembler::Fail; 4674 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4675 return MCDisassembler::Fail; 4676 4677 return S; 4678 } 4679 4680 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4681 uint64_t Address, const void *Decoder) { 4682 DecodeStatus S = MCDisassembler::Success; 4683 4684 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4685 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4686 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4687 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4688 unsigned size = fieldFromInstruction(Insn, 10, 2); 4689 4690 unsigned align = 0; 4691 unsigned index = 0; 4692 switch (size) { 4693 default: 4694 return MCDisassembler::Fail; 4695 case 0: 4696 if (fieldFromInstruction(Insn, 4, 1)) 4697 return MCDisassembler::Fail; // UNDEFINED 4698 index = fieldFromInstruction(Insn, 5, 3); 4699 break; 4700 case 1: 4701 if (fieldFromInstruction(Insn, 5, 1)) 4702 return MCDisassembler::Fail; // UNDEFINED 4703 index = fieldFromInstruction(Insn, 6, 2); 4704 if (fieldFromInstruction(Insn, 4, 1)) 4705 align = 2; 4706 break; 4707 case 2: 4708 if (fieldFromInstruction(Insn, 6, 1)) 4709 return MCDisassembler::Fail; // UNDEFINED 4710 index = fieldFromInstruction(Insn, 7, 1); 4711 4712 switch (fieldFromInstruction(Insn, 4, 2)) { 4713 case 0 : 4714 align = 0; break; 4715 case 3: 4716 align = 4; break; 4717 default: 4718 return MCDisassembler::Fail; 4719 } 4720 break; 4721 } 4722 4723 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4724 return MCDisassembler::Fail; 4725 if (Rm != 0xF) { // Writeback 4726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4727 return MCDisassembler::Fail; 4728 } 4729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4730 return MCDisassembler::Fail; 4731 Inst.addOperand(MCOperand::createImm(align)); 4732 if (Rm != 0xF) { 4733 if (Rm != 0xD) { 4734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4735 return MCDisassembler::Fail; 4736 } else 4737 Inst.addOperand(MCOperand::createReg(0)); 4738 } 4739 4740 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4741 return MCDisassembler::Fail; 4742 Inst.addOperand(MCOperand::createImm(index)); 4743 4744 return S; 4745 } 4746 4747 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4748 uint64_t Address, const void *Decoder) { 4749 DecodeStatus S = MCDisassembler::Success; 4750 4751 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4752 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4753 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4754 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4755 unsigned size = fieldFromInstruction(Insn, 10, 2); 4756 4757 unsigned align = 0; 4758 unsigned index = 0; 4759 switch (size) { 4760 default: 4761 return MCDisassembler::Fail; 4762 case 0: 4763 if (fieldFromInstruction(Insn, 4, 1)) 4764 return MCDisassembler::Fail; // UNDEFINED 4765 index = fieldFromInstruction(Insn, 5, 3); 4766 break; 4767 case 1: 4768 if (fieldFromInstruction(Insn, 5, 1)) 4769 return MCDisassembler::Fail; // UNDEFINED 4770 index = fieldFromInstruction(Insn, 6, 2); 4771 if (fieldFromInstruction(Insn, 4, 1)) 4772 align = 2; 4773 break; 4774 case 2: 4775 if (fieldFromInstruction(Insn, 6, 1)) 4776 return MCDisassembler::Fail; // UNDEFINED 4777 index = fieldFromInstruction(Insn, 7, 1); 4778 4779 switch (fieldFromInstruction(Insn, 4, 2)) { 4780 case 0: 4781 align = 0; break; 4782 case 3: 4783 align = 4; break; 4784 default: 4785 return MCDisassembler::Fail; 4786 } 4787 break; 4788 } 4789 4790 if (Rm != 0xF) { // Writeback 4791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4792 return MCDisassembler::Fail; 4793 } 4794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4795 return MCDisassembler::Fail; 4796 Inst.addOperand(MCOperand::createImm(align)); 4797 if (Rm != 0xF) { 4798 if (Rm != 0xD) { 4799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4800 return MCDisassembler::Fail; 4801 } else 4802 Inst.addOperand(MCOperand::createReg(0)); 4803 } 4804 4805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4806 return MCDisassembler::Fail; 4807 Inst.addOperand(MCOperand::createImm(index)); 4808 4809 return S; 4810 } 4811 4812 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4813 uint64_t Address, const void *Decoder) { 4814 DecodeStatus S = MCDisassembler::Success; 4815 4816 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4817 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4818 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4819 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4820 unsigned size = fieldFromInstruction(Insn, 10, 2); 4821 4822 unsigned align = 0; 4823 unsigned index = 0; 4824 unsigned inc = 1; 4825 switch (size) { 4826 default: 4827 return MCDisassembler::Fail; 4828 case 0: 4829 index = fieldFromInstruction(Insn, 5, 3); 4830 if (fieldFromInstruction(Insn, 4, 1)) 4831 align = 2; 4832 break; 4833 case 1: 4834 index = fieldFromInstruction(Insn, 6, 2); 4835 if (fieldFromInstruction(Insn, 4, 1)) 4836 align = 4; 4837 if (fieldFromInstruction(Insn, 5, 1)) 4838 inc = 2; 4839 break; 4840 case 2: 4841 if (fieldFromInstruction(Insn, 5, 1)) 4842 return MCDisassembler::Fail; // UNDEFINED 4843 index = fieldFromInstruction(Insn, 7, 1); 4844 if (fieldFromInstruction(Insn, 4, 1) != 0) 4845 align = 8; 4846 if (fieldFromInstruction(Insn, 6, 1)) 4847 inc = 2; 4848 break; 4849 } 4850 4851 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4852 return MCDisassembler::Fail; 4853 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4854 return MCDisassembler::Fail; 4855 if (Rm != 0xF) { // Writeback 4856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4857 return MCDisassembler::Fail; 4858 } 4859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4860 return MCDisassembler::Fail; 4861 Inst.addOperand(MCOperand::createImm(align)); 4862 if (Rm != 0xF) { 4863 if (Rm != 0xD) { 4864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4865 return MCDisassembler::Fail; 4866 } else 4867 Inst.addOperand(MCOperand::createReg(0)); 4868 } 4869 4870 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4871 return MCDisassembler::Fail; 4872 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4873 return MCDisassembler::Fail; 4874 Inst.addOperand(MCOperand::createImm(index)); 4875 4876 return S; 4877 } 4878 4879 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4880 uint64_t Address, const void *Decoder) { 4881 DecodeStatus S = MCDisassembler::Success; 4882 4883 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4884 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4885 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4886 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4887 unsigned size = fieldFromInstruction(Insn, 10, 2); 4888 4889 unsigned align = 0; 4890 unsigned index = 0; 4891 unsigned inc = 1; 4892 switch (size) { 4893 default: 4894 return MCDisassembler::Fail; 4895 case 0: 4896 index = fieldFromInstruction(Insn, 5, 3); 4897 if (fieldFromInstruction(Insn, 4, 1)) 4898 align = 2; 4899 break; 4900 case 1: 4901 index = fieldFromInstruction(Insn, 6, 2); 4902 if (fieldFromInstruction(Insn, 4, 1)) 4903 align = 4; 4904 if (fieldFromInstruction(Insn, 5, 1)) 4905 inc = 2; 4906 break; 4907 case 2: 4908 if (fieldFromInstruction(Insn, 5, 1)) 4909 return MCDisassembler::Fail; // UNDEFINED 4910 index = fieldFromInstruction(Insn, 7, 1); 4911 if (fieldFromInstruction(Insn, 4, 1) != 0) 4912 align = 8; 4913 if (fieldFromInstruction(Insn, 6, 1)) 4914 inc = 2; 4915 break; 4916 } 4917 4918 if (Rm != 0xF) { // Writeback 4919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4920 return MCDisassembler::Fail; 4921 } 4922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4923 return MCDisassembler::Fail; 4924 Inst.addOperand(MCOperand::createImm(align)); 4925 if (Rm != 0xF) { 4926 if (Rm != 0xD) { 4927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4928 return MCDisassembler::Fail; 4929 } else 4930 Inst.addOperand(MCOperand::createReg(0)); 4931 } 4932 4933 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4934 return MCDisassembler::Fail; 4935 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4936 return MCDisassembler::Fail; 4937 Inst.addOperand(MCOperand::createImm(index)); 4938 4939 return S; 4940 } 4941 4942 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4943 uint64_t Address, const void *Decoder) { 4944 DecodeStatus S = MCDisassembler::Success; 4945 4946 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4947 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4948 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4949 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4950 unsigned size = fieldFromInstruction(Insn, 10, 2); 4951 4952 unsigned align = 0; 4953 unsigned index = 0; 4954 unsigned inc = 1; 4955 switch (size) { 4956 default: 4957 return MCDisassembler::Fail; 4958 case 0: 4959 if (fieldFromInstruction(Insn, 4, 1)) 4960 return MCDisassembler::Fail; // UNDEFINED 4961 index = fieldFromInstruction(Insn, 5, 3); 4962 break; 4963 case 1: 4964 if (fieldFromInstruction(Insn, 4, 1)) 4965 return MCDisassembler::Fail; // UNDEFINED 4966 index = fieldFromInstruction(Insn, 6, 2); 4967 if (fieldFromInstruction(Insn, 5, 1)) 4968 inc = 2; 4969 break; 4970 case 2: 4971 if (fieldFromInstruction(Insn, 4, 2)) 4972 return MCDisassembler::Fail; // UNDEFINED 4973 index = fieldFromInstruction(Insn, 7, 1); 4974 if (fieldFromInstruction(Insn, 6, 1)) 4975 inc = 2; 4976 break; 4977 } 4978 4979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4980 return MCDisassembler::Fail; 4981 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4982 return MCDisassembler::Fail; 4983 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4984 return MCDisassembler::Fail; 4985 4986 if (Rm != 0xF) { // Writeback 4987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4988 return MCDisassembler::Fail; 4989 } 4990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4991 return MCDisassembler::Fail; 4992 Inst.addOperand(MCOperand::createImm(align)); 4993 if (Rm != 0xF) { 4994 if (Rm != 0xD) { 4995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4996 return MCDisassembler::Fail; 4997 } else 4998 Inst.addOperand(MCOperand::createReg(0)); 4999 } 5000 5001 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5002 return MCDisassembler::Fail; 5003 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5004 return MCDisassembler::Fail; 5005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5006 return MCDisassembler::Fail; 5007 Inst.addOperand(MCOperand::createImm(index)); 5008 5009 return S; 5010 } 5011 5012 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5013 uint64_t Address, const void *Decoder) { 5014 DecodeStatus S = MCDisassembler::Success; 5015 5016 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5017 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5018 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5019 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5020 unsigned size = fieldFromInstruction(Insn, 10, 2); 5021 5022 unsigned align = 0; 5023 unsigned index = 0; 5024 unsigned inc = 1; 5025 switch (size) { 5026 default: 5027 return MCDisassembler::Fail; 5028 case 0: 5029 if (fieldFromInstruction(Insn, 4, 1)) 5030 return MCDisassembler::Fail; // UNDEFINED 5031 index = fieldFromInstruction(Insn, 5, 3); 5032 break; 5033 case 1: 5034 if (fieldFromInstruction(Insn, 4, 1)) 5035 return MCDisassembler::Fail; // UNDEFINED 5036 index = fieldFromInstruction(Insn, 6, 2); 5037 if (fieldFromInstruction(Insn, 5, 1)) 5038 inc = 2; 5039 break; 5040 case 2: 5041 if (fieldFromInstruction(Insn, 4, 2)) 5042 return MCDisassembler::Fail; // UNDEFINED 5043 index = fieldFromInstruction(Insn, 7, 1); 5044 if (fieldFromInstruction(Insn, 6, 1)) 5045 inc = 2; 5046 break; 5047 } 5048 5049 if (Rm != 0xF) { // Writeback 5050 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5051 return MCDisassembler::Fail; 5052 } 5053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5054 return MCDisassembler::Fail; 5055 Inst.addOperand(MCOperand::createImm(align)); 5056 if (Rm != 0xF) { 5057 if (Rm != 0xD) { 5058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5059 return MCDisassembler::Fail; 5060 } else 5061 Inst.addOperand(MCOperand::createReg(0)); 5062 } 5063 5064 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5065 return MCDisassembler::Fail; 5066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5067 return MCDisassembler::Fail; 5068 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5069 return MCDisassembler::Fail; 5070 Inst.addOperand(MCOperand::createImm(index)); 5071 5072 return S; 5073 } 5074 5075 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5076 uint64_t Address, const void *Decoder) { 5077 DecodeStatus S = MCDisassembler::Success; 5078 5079 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5080 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5081 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5082 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5083 unsigned size = fieldFromInstruction(Insn, 10, 2); 5084 5085 unsigned align = 0; 5086 unsigned index = 0; 5087 unsigned inc = 1; 5088 switch (size) { 5089 default: 5090 return MCDisassembler::Fail; 5091 case 0: 5092 if (fieldFromInstruction(Insn, 4, 1)) 5093 align = 4; 5094 index = fieldFromInstruction(Insn, 5, 3); 5095 break; 5096 case 1: 5097 if (fieldFromInstruction(Insn, 4, 1)) 5098 align = 8; 5099 index = fieldFromInstruction(Insn, 6, 2); 5100 if (fieldFromInstruction(Insn, 5, 1)) 5101 inc = 2; 5102 break; 5103 case 2: 5104 switch (fieldFromInstruction(Insn, 4, 2)) { 5105 case 0: 5106 align = 0; break; 5107 case 3: 5108 return MCDisassembler::Fail; 5109 default: 5110 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5111 } 5112 5113 index = fieldFromInstruction(Insn, 7, 1); 5114 if (fieldFromInstruction(Insn, 6, 1)) 5115 inc = 2; 5116 break; 5117 } 5118 5119 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5120 return MCDisassembler::Fail; 5121 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5122 return MCDisassembler::Fail; 5123 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5124 return MCDisassembler::Fail; 5125 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5126 return MCDisassembler::Fail; 5127 5128 if (Rm != 0xF) { // Writeback 5129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5130 return MCDisassembler::Fail; 5131 } 5132 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5133 return MCDisassembler::Fail; 5134 Inst.addOperand(MCOperand::createImm(align)); 5135 if (Rm != 0xF) { 5136 if (Rm != 0xD) { 5137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5138 return MCDisassembler::Fail; 5139 } else 5140 Inst.addOperand(MCOperand::createReg(0)); 5141 } 5142 5143 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5144 return MCDisassembler::Fail; 5145 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5146 return MCDisassembler::Fail; 5147 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5148 return MCDisassembler::Fail; 5149 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5150 return MCDisassembler::Fail; 5151 Inst.addOperand(MCOperand::createImm(index)); 5152 5153 return S; 5154 } 5155 5156 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5157 uint64_t Address, const void *Decoder) { 5158 DecodeStatus S = MCDisassembler::Success; 5159 5160 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5161 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5162 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5163 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5164 unsigned size = fieldFromInstruction(Insn, 10, 2); 5165 5166 unsigned align = 0; 5167 unsigned index = 0; 5168 unsigned inc = 1; 5169 switch (size) { 5170 default: 5171 return MCDisassembler::Fail; 5172 case 0: 5173 if (fieldFromInstruction(Insn, 4, 1)) 5174 align = 4; 5175 index = fieldFromInstruction(Insn, 5, 3); 5176 break; 5177 case 1: 5178 if (fieldFromInstruction(Insn, 4, 1)) 5179 align = 8; 5180 index = fieldFromInstruction(Insn, 6, 2); 5181 if (fieldFromInstruction(Insn, 5, 1)) 5182 inc = 2; 5183 break; 5184 case 2: 5185 switch (fieldFromInstruction(Insn, 4, 2)) { 5186 case 0: 5187 align = 0; break; 5188 case 3: 5189 return MCDisassembler::Fail; 5190 default: 5191 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5192 } 5193 5194 index = fieldFromInstruction(Insn, 7, 1); 5195 if (fieldFromInstruction(Insn, 6, 1)) 5196 inc = 2; 5197 break; 5198 } 5199 5200 if (Rm != 0xF) { // Writeback 5201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5202 return MCDisassembler::Fail; 5203 } 5204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5205 return MCDisassembler::Fail; 5206 Inst.addOperand(MCOperand::createImm(align)); 5207 if (Rm != 0xF) { 5208 if (Rm != 0xD) { 5209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5210 return MCDisassembler::Fail; 5211 } else 5212 Inst.addOperand(MCOperand::createReg(0)); 5213 } 5214 5215 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5216 return MCDisassembler::Fail; 5217 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5218 return MCDisassembler::Fail; 5219 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5220 return MCDisassembler::Fail; 5221 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5222 return MCDisassembler::Fail; 5223 Inst.addOperand(MCOperand::createImm(index)); 5224 5225 return S; 5226 } 5227 5228 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5229 uint64_t Address, const void *Decoder) { 5230 DecodeStatus S = MCDisassembler::Success; 5231 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5232 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5233 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5234 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5235 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5236 5237 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5238 S = MCDisassembler::SoftFail; 5239 5240 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5241 return MCDisassembler::Fail; 5242 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5243 return MCDisassembler::Fail; 5244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5245 return MCDisassembler::Fail; 5246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5247 return MCDisassembler::Fail; 5248 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5249 return MCDisassembler::Fail; 5250 5251 return S; 5252 } 5253 5254 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5255 uint64_t Address, const void *Decoder) { 5256 DecodeStatus S = MCDisassembler::Success; 5257 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5258 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5259 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5260 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5261 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5262 5263 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5264 S = MCDisassembler::SoftFail; 5265 5266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5267 return MCDisassembler::Fail; 5268 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5269 return MCDisassembler::Fail; 5270 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5271 return MCDisassembler::Fail; 5272 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5273 return MCDisassembler::Fail; 5274 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5275 return MCDisassembler::Fail; 5276 5277 return S; 5278 } 5279 5280 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5281 uint64_t Address, const void *Decoder) { 5282 DecodeStatus S = MCDisassembler::Success; 5283 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5284 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5285 5286 if (pred == 0xF) { 5287 pred = 0xE; 5288 S = MCDisassembler::SoftFail; 5289 } 5290 5291 if (mask == 0x0) 5292 return MCDisassembler::Fail; 5293 5294 // IT masks are encoded as a sequence of replacement low-order bits 5295 // for the condition code. So if the low bit of the starting 5296 // condition code is 1, then we have to flip all the bits above the 5297 // terminating bit (which is the lowest 1 bit). 5298 if (pred & 1) { 5299 unsigned LowBit = mask & -mask; 5300 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5301 mask ^= BitsAboveLowBit; 5302 } 5303 5304 Inst.addOperand(MCOperand::createImm(pred)); 5305 Inst.addOperand(MCOperand::createImm(mask)); 5306 return S; 5307 } 5308 5309 static DecodeStatus 5310 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5311 uint64_t Address, const void *Decoder) { 5312 DecodeStatus S = MCDisassembler::Success; 5313 5314 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5315 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5316 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5317 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5318 unsigned W = fieldFromInstruction(Insn, 21, 1); 5319 unsigned U = fieldFromInstruction(Insn, 23, 1); 5320 unsigned P = fieldFromInstruction(Insn, 24, 1); 5321 bool writeback = (W == 1) | (P == 0); 5322 5323 addr |= (U << 8) | (Rn << 9); 5324 5325 if (writeback && (Rn == Rt || Rn == Rt2)) 5326 Check(S, MCDisassembler::SoftFail); 5327 if (Rt == Rt2) 5328 Check(S, MCDisassembler::SoftFail); 5329 5330 // Rt 5331 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5332 return MCDisassembler::Fail; 5333 // Rt2 5334 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5335 return MCDisassembler::Fail; 5336 // Writeback operand 5337 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5338 return MCDisassembler::Fail; 5339 // addr 5340 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5341 return MCDisassembler::Fail; 5342 5343 return S; 5344 } 5345 5346 static DecodeStatus 5347 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5348 uint64_t Address, const void *Decoder) { 5349 DecodeStatus S = MCDisassembler::Success; 5350 5351 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5352 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5353 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5354 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5355 unsigned W = fieldFromInstruction(Insn, 21, 1); 5356 unsigned U = fieldFromInstruction(Insn, 23, 1); 5357 unsigned P = fieldFromInstruction(Insn, 24, 1); 5358 bool writeback = (W == 1) | (P == 0); 5359 5360 addr |= (U << 8) | (Rn << 9); 5361 5362 if (writeback && (Rn == Rt || Rn == Rt2)) 5363 Check(S, MCDisassembler::SoftFail); 5364 5365 // Writeback operand 5366 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5367 return MCDisassembler::Fail; 5368 // Rt 5369 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5370 return MCDisassembler::Fail; 5371 // Rt2 5372 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5373 return MCDisassembler::Fail; 5374 // addr 5375 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5376 return MCDisassembler::Fail; 5377 5378 return S; 5379 } 5380 5381 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5382 uint64_t Address, const void *Decoder) { 5383 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5384 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5385 if (sign1 != sign2) return MCDisassembler::Fail; 5386 5387 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5388 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5389 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5390 Val |= sign1 << 12; 5391 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5392 5393 return MCDisassembler::Success; 5394 } 5395 5396 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5397 uint64_t Address, 5398 const void *Decoder) { 5399 DecodeStatus S = MCDisassembler::Success; 5400 5401 // Shift of "asr #32" is not allowed in Thumb2 mode. 5402 if (Val == 0x20) S = MCDisassembler::Fail; 5403 Inst.addOperand(MCOperand::createImm(Val)); 5404 return S; 5405 } 5406 5407 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5408 uint64_t Address, const void *Decoder) { 5409 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5410 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5411 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5412 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5413 5414 if (pred == 0xF) 5415 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5416 5417 DecodeStatus S = MCDisassembler::Success; 5418 5419 if (Rt == Rn || Rn == Rt2) 5420 S = MCDisassembler::SoftFail; 5421 5422 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5423 return MCDisassembler::Fail; 5424 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5425 return MCDisassembler::Fail; 5426 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5427 return MCDisassembler::Fail; 5428 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5429 return MCDisassembler::Fail; 5430 5431 return S; 5432 } 5433 5434 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5435 uint64_t Address, const void *Decoder) { 5436 const FeatureBitset &featureBits = 5437 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5438 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5439 5440 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5441 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5442 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5443 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5444 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5445 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5446 unsigned op = fieldFromInstruction(Insn, 5, 1); 5447 5448 DecodeStatus S = MCDisassembler::Success; 5449 5450 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5451 if (!(imm & 0x38)) { 5452 if (cmode == 0xF) { 5453 if (op == 1) return MCDisassembler::Fail; 5454 Inst.setOpcode(ARM::VMOVv2f32); 5455 } 5456 if (hasFullFP16) { 5457 if (cmode == 0xE) { 5458 if (op == 1) { 5459 Inst.setOpcode(ARM::VMOVv1i64); 5460 } else { 5461 Inst.setOpcode(ARM::VMOVv8i8); 5462 } 5463 } 5464 if (cmode == 0xD) { 5465 if (op == 1) { 5466 Inst.setOpcode(ARM::VMVNv2i32); 5467 } else { 5468 Inst.setOpcode(ARM::VMOVv2i32); 5469 } 5470 } 5471 if (cmode == 0xC) { 5472 if (op == 1) { 5473 Inst.setOpcode(ARM::VMVNv2i32); 5474 } else { 5475 Inst.setOpcode(ARM::VMOVv2i32); 5476 } 5477 } 5478 } 5479 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5480 } 5481 5482 if (!(imm & 0x20)) return MCDisassembler::Fail; 5483 5484 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5485 return MCDisassembler::Fail; 5486 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5487 return MCDisassembler::Fail; 5488 Inst.addOperand(MCOperand::createImm(64 - imm)); 5489 5490 return S; 5491 } 5492 5493 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5494 uint64_t Address, const void *Decoder) { 5495 const FeatureBitset &featureBits = 5496 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5497 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5498 5499 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5500 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5501 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5502 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5503 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5504 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5505 unsigned op = fieldFromInstruction(Insn, 5, 1); 5506 5507 DecodeStatus S = MCDisassembler::Success; 5508 5509 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5510 if (!(imm & 0x38)) { 5511 if (cmode == 0xF) { 5512 if (op == 1) return MCDisassembler::Fail; 5513 Inst.setOpcode(ARM::VMOVv4f32); 5514 } 5515 if (hasFullFP16) { 5516 if (cmode == 0xE) { 5517 if (op == 1) { 5518 Inst.setOpcode(ARM::VMOVv2i64); 5519 } else { 5520 Inst.setOpcode(ARM::VMOVv16i8); 5521 } 5522 } 5523 if (cmode == 0xD) { 5524 if (op == 1) { 5525 Inst.setOpcode(ARM::VMVNv4i32); 5526 } else { 5527 Inst.setOpcode(ARM::VMOVv4i32); 5528 } 5529 } 5530 if (cmode == 0xC) { 5531 if (op == 1) { 5532 Inst.setOpcode(ARM::VMVNv4i32); 5533 } else { 5534 Inst.setOpcode(ARM::VMOVv4i32); 5535 } 5536 } 5537 } 5538 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5539 } 5540 5541 if (!(imm & 0x20)) return MCDisassembler::Fail; 5542 5543 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5544 return MCDisassembler::Fail; 5545 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5546 return MCDisassembler::Fail; 5547 Inst.addOperand(MCOperand::createImm(64 - imm)); 5548 5549 return S; 5550 } 5551 5552 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5553 unsigned Insn, 5554 uint64_t Address, 5555 const void *Decoder) { 5556 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5557 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5558 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5559 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5560 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5561 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5562 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5563 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5564 5565 DecodeStatus S = MCDisassembler::Success; 5566 5567 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5568 5569 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5570 return MCDisassembler::Fail; 5571 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5572 return MCDisassembler::Fail; 5573 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5574 return MCDisassembler::Fail; 5575 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5576 return MCDisassembler::Fail; 5577 // The lane index does not have any bits in the encoding, because it can only 5578 // be 0. 5579 Inst.addOperand(MCOperand::createImm(0)); 5580 Inst.addOperand(MCOperand::createImm(rotate)); 5581 5582 return S; 5583 } 5584 5585 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5586 uint64_t Address, const void *Decoder) { 5587 DecodeStatus S = MCDisassembler::Success; 5588 5589 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5590 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5591 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5592 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5593 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5594 5595 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5596 S = MCDisassembler::SoftFail; 5597 5598 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5599 return MCDisassembler::Fail; 5600 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5601 return MCDisassembler::Fail; 5602 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5603 return MCDisassembler::Fail; 5604 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5605 return MCDisassembler::Fail; 5606 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5607 return MCDisassembler::Fail; 5608 5609 return S; 5610 } 5611 5612 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5613 uint64_t Address, const void *Decoder) { 5614 DecodeStatus S = MCDisassembler::Success; 5615 5616 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5617 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5618 unsigned cop = fieldFromInstruction(Val, 8, 4); 5619 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5620 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5621 5622 if ((cop & ~0x1) == 0xa) 5623 return MCDisassembler::Fail; 5624 5625 if (Rt == Rt2) 5626 S = MCDisassembler::SoftFail; 5627 5628 // We have to check if the instruction is MRRC2 5629 // or MCRR2 when constructing the operands for 5630 // Inst. Reason is because MRRC2 stores to two 5631 // registers so it's tablegen desc has has two 5632 // outputs whereas MCRR doesn't store to any 5633 // registers so all of it's operands are listed 5634 // as inputs, therefore the operand order for 5635 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5636 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5637 5638 if (Inst.getOpcode() == ARM::MRRC2) { 5639 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5640 return MCDisassembler::Fail; 5641 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5642 return MCDisassembler::Fail; 5643 } 5644 Inst.addOperand(MCOperand::createImm(cop)); 5645 Inst.addOperand(MCOperand::createImm(opc1)); 5646 if (Inst.getOpcode() == ARM::MCRR2) { 5647 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5648 return MCDisassembler::Fail; 5649 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5650 return MCDisassembler::Fail; 5651 } 5652 Inst.addOperand(MCOperand::createImm(CRm)); 5653 5654 return S; 5655 } 5656 5657 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5658 uint64_t Address, 5659 const void *Decoder) { 5660 const FeatureBitset &featureBits = 5661 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5662 DecodeStatus S = MCDisassembler::Success; 5663 5664 // Add explicit operand for the destination sysreg, for cases where 5665 // we have to model it for code generation purposes. 5666 switch (Inst.getOpcode()) { 5667 case ARM::VMSR_FPSCR_NZCVQC: 5668 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5669 break; 5670 case ARM::VMSR_P0: 5671 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5672 break; 5673 } 5674 5675 if (Inst.getOpcode() != ARM::FMSTAT) { 5676 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5677 5678 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5679 if (Rt == 13 || Rt == 15) 5680 S = MCDisassembler::SoftFail; 5681 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5682 } else 5683 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5684 } 5685 5686 // Add explicit operand for the source sysreg, similarly to above. 5687 switch (Inst.getOpcode()) { 5688 case ARM::VMRS_FPSCR_NZCVQC: 5689 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5690 break; 5691 case ARM::VMRS_P0: 5692 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5693 break; 5694 } 5695 5696 if (featureBits[ARM::ModeThumb]) { 5697 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5698 Inst.addOperand(MCOperand::createReg(0)); 5699 } else { 5700 unsigned pred = fieldFromInstruction(Val, 28, 4); 5701 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5702 return MCDisassembler::Fail; 5703 } 5704 5705 return S; 5706 } 5707 5708 template <bool isSigned, bool isNeg, int size> 5709 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5710 uint64_t Address, 5711 const void *Decoder) { 5712 DecodeStatus S = MCDisassembler::Success; 5713 if (Val == 0) 5714 S = MCDisassembler::SoftFail; 5715 5716 uint64_t DecVal; 5717 if (isSigned) 5718 DecVal = SignExtend32<size + 1>(Val << 1); 5719 else 5720 DecVal = (Val << 1); 5721 5722 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5723 Decoder)) 5724 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5725 return S; 5726 } 5727 5728 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5729 uint64_t Address, 5730 const void *Decoder) { 5731 5732 uint64_t LocImm = Inst.getOperand(0).getImm(); 5733 Val = LocImm + (2 << Val); 5734 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5735 Decoder)) 5736 Inst.addOperand(MCOperand::createImm(Val)); 5737 return MCDisassembler::Success; 5738 } 5739 5740 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5741 uint64_t Address, 5742 const void *Decoder) { 5743 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5744 return MCDisassembler::Fail; 5745 Inst.addOperand(MCOperand::createImm(Val)); 5746 return MCDisassembler::Success; 5747 } 5748 5749 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5750 const void *Decoder) { 5751 DecodeStatus S = MCDisassembler::Success; 5752 5753 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5754 fieldFromInstruction(Insn, 1, 10) << 1; 5755 switch (Inst.getOpcode()) { 5756 case ARM::t2LEUpdate: 5757 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5758 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5759 LLVM_FALLTHROUGH; 5760 case ARM::t2LE: 5761 if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address, 5762 Decoder))) 5763 return MCDisassembler::Fail; 5764 break; 5765 case ARM::t2WLS: 5766 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5767 if (!Check(S, 5768 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5769 Address, Decoder)) || 5770 !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address, 5771 Decoder))) 5772 return MCDisassembler::Fail; 5773 break; 5774 case ARM::t2DLS: 5775 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5776 if (Rn == 0xF) { 5777 return MCDisassembler::Fail; 5778 } else { 5779 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5780 if (!Check(S, DecoderGPRRegisterClass(Inst, 5781 fieldFromInstruction(Insn, 16, 4), 5782 Address, Decoder))) 5783 return MCDisassembler::Fail; 5784 } 5785 break; 5786 } 5787 return S; 5788 } 5789 5790 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 5791 uint64_t Address, 5792 const void *Decoder) { 5793 DecodeStatus S = MCDisassembler::Success; 5794 5795 if (Val == 0) 5796 Val = 32; 5797 5798 Inst.addOperand(MCOperand::createImm(Val)); 5799 5800 return S; 5801 } 5802 5803 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 5804 uint64_t Address, const void *Decoder) { 5805 if ((RegNo) + 1 > 11) 5806 return MCDisassembler::Fail; 5807 5808 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 5809 Inst.addOperand(MCOperand::createReg(Register)); 5810 return MCDisassembler::Success; 5811 } 5812 5813 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 5814 uint64_t Address, const void *Decoder) { 5815 if ((RegNo) > 14) 5816 return MCDisassembler::Fail; 5817 5818 unsigned Register = GPRDecoderTable[(RegNo)]; 5819 Inst.addOperand(MCOperand::createReg(Register)); 5820 return MCDisassembler::Success; 5821 } 5822 5823 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 5824 const void *Decoder) { 5825 DecodeStatus S = MCDisassembler::Success; 5826 5827 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5828 Inst.addOperand(MCOperand::createReg(0)); 5829 if (Inst.getOpcode() == ARM::VSCCLRMD) { 5830 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 5831 (fieldFromInstruction(Insn, 12, 4) << 8) | 5832 (fieldFromInstruction(Insn, 22, 1) << 12); 5833 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 5834 return MCDisassembler::Fail; 5835 } 5836 } else { 5837 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 5838 (fieldFromInstruction(Insn, 22, 1) << 8) | 5839 (fieldFromInstruction(Insn, 12, 4) << 9); 5840 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 5841 return MCDisassembler::Fail; 5842 } 5843 } 5844 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5845 5846 return S; 5847 } 5848 5849 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 5850 uint64_t Address, 5851 const void *Decoder) { 5852 if (RegNo > 7) 5853 return MCDisassembler::Fail; 5854 5855 unsigned Register = QPRDecoderTable[RegNo]; 5856 Inst.addOperand(MCOperand::createReg(Register)); 5857 return MCDisassembler::Success; 5858 } 5859 5860 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 5861 uint64_t Address, 5862 const void *Decoder) { 5863 DecodeStatus S = MCDisassembler::Success; 5864 5865 // Parse VPT mask and encode it in the MCInst as an immediate with the same 5866 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 5867 // 't' as 0 and finish with a 1. 5868 unsigned Imm = 0; 5869 // We always start with a 't'. 5870 unsigned CurBit = 0; 5871 for (int i = 3; i >= 0; --i) { 5872 // If the bit we are looking at is not the same as last one, invert the 5873 // CurBit, if it is the same leave it as is. 5874 CurBit ^= (Val >> i) & 1U; 5875 5876 // Encode the CurBit at the right place in the immediate. 5877 Imm |= (CurBit << i); 5878 5879 // If we are done, finish the encoding with a 1. 5880 if ((Val & ~(~0U << i)) == 0) { 5881 Imm |= 1U << i; 5882 break; 5883 } 5884 } 5885 5886 Inst.addOperand(MCOperand::createImm(Imm)); 5887 5888 return S; 5889 } 5890 5891 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 5892 uint64_t Address, const void *Decoder) { 5893 // The vpred_r operand type includes an MQPR register field derived 5894 // from the encoding. But we don't actually want to add an operand 5895 // to the MCInst at this stage, because AddThumbPredicate will do it 5896 // later, and will infer the register number from the TIED_TO 5897 // constraint. So this is a deliberately empty decoder method that 5898 // will inhibit the auto-generated disassembly code from adding an 5899 // operand at all. 5900 return MCDisassembler::Success; 5901 } 5902 5903 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 5904 unsigned Val, 5905 uint64_t Address, 5906 const void *Decoder) { 5907 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 5908 return MCDisassembler::Success; 5909 } 5910 5911 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 5912 unsigned Val, 5913 uint64_t Address, 5914 const void *Decoder) { 5915 unsigned Code; 5916 switch (Val & 0x3) { 5917 case 0: 5918 Code = ARMCC::GE; 5919 break; 5920 case 1: 5921 Code = ARMCC::LT; 5922 break; 5923 case 2: 5924 Code = ARMCC::GT; 5925 break; 5926 case 3: 5927 Code = ARMCC::LE; 5928 break; 5929 } 5930 Inst.addOperand(MCOperand::createImm(Code)); 5931 return MCDisassembler::Success; 5932 } 5933 5934 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 5935 unsigned Val, 5936 uint64_t Address, 5937 const void *Decoder) { 5938 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 5939 return MCDisassembler::Success; 5940 } 5941 5942 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 5943 uint64_t Address, 5944 const void *Decoder) { 5945 unsigned Code; 5946 switch (Val) { 5947 default: 5948 return MCDisassembler::Fail; 5949 case 0: 5950 Code = ARMCC::EQ; 5951 break; 5952 case 1: 5953 Code = ARMCC::NE; 5954 break; 5955 case 4: 5956 Code = ARMCC::GE; 5957 break; 5958 case 5: 5959 Code = ARMCC::LT; 5960 break; 5961 case 6: 5962 Code = ARMCC::GT; 5963 break; 5964 case 7: 5965 Code = ARMCC::LE; 5966 break; 5967 } 5968 5969 Inst.addOperand(MCOperand::createImm(Code)); 5970 return MCDisassembler::Success; 5971 } 5972 5973 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 5974 switch (Opcode) { 5975 case ARM::VSTR_P0_off: 5976 case ARM::VSTR_P0_pre: 5977 case ARM::VSTR_P0_post: 5978 case ARM::VLDR_P0_off: 5979 case ARM::VLDR_P0_pre: 5980 case ARM::VLDR_P0_post: 5981 return ARM::P0; 5982 default: 5983 return 0; 5984 } 5985 } 5986 5987 template<bool Writeback> 5988 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 5989 uint64_t Address, 5990 const void *Decoder) { 5991 switch (Inst.getOpcode()) { 5992 case ARM::VSTR_FPSCR_pre: 5993 case ARM::VSTR_FPSCR_NZCVQC_pre: 5994 case ARM::VLDR_FPSCR_pre: 5995 case ARM::VLDR_FPSCR_NZCVQC_pre: 5996 case ARM::VSTR_FPSCR_off: 5997 case ARM::VSTR_FPSCR_NZCVQC_off: 5998 case ARM::VLDR_FPSCR_off: 5999 case ARM::VLDR_FPSCR_NZCVQC_off: 6000 case ARM::VSTR_FPSCR_post: 6001 case ARM::VSTR_FPSCR_NZCVQC_post: 6002 case ARM::VLDR_FPSCR_post: 6003 case ARM::VLDR_FPSCR_NZCVQC_post: 6004 const FeatureBitset &featureBits = 6005 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6006 6007 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6008 return MCDisassembler::Fail; 6009 } 6010 6011 DecodeStatus S = MCDisassembler::Success; 6012 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6013 Inst.addOperand(MCOperand::createReg(Sysreg)); 6014 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6015 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6016 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6017 6018 if (Writeback) { 6019 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6020 return MCDisassembler::Fail; 6021 } 6022 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6023 return MCDisassembler::Fail; 6024 6025 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6026 Inst.addOperand(MCOperand::createReg(0)); 6027 6028 return S; 6029 } 6030 6031 template <int shift> 6032 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6033 uint64_t Address, 6034 const void *Decoder) { 6035 Val <<= shift; 6036 6037 Inst.addOperand(MCOperand::createImm(Val)); 6038 return MCDisassembler::Success; 6039 } 6040 6041 static DecodeStatus DecodeMVEOverlappingLongShift( 6042 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6043 DecodeStatus S = MCDisassembler::Success; 6044 6045 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6046 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6047 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6048 6049 if (RdaHi == 14) { 6050 // This value of RdaHi (really indicating pc, because RdaHi has to 6051 // be an odd-numbered register, so the low bit will be set by the 6052 // decode function below) indicates that we must decode as SQRSHR 6053 // or UQRSHL, which both have a single Rda register field with all 6054 // four bits. 6055 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6056 6057 switch (Inst.getOpcode()) { 6058 case ARM::MVE_ASRLr: 6059 case ARM::MVE_SQRSHRL: 6060 Inst.setOpcode(ARM::MVE_SQRSHR); 6061 break; 6062 case ARM::MVE_LSLLr: 6063 case ARM::MVE_UQRSHLL: 6064 Inst.setOpcode(ARM::MVE_UQRSHL); 6065 break; 6066 default: 6067 llvm_unreachable("Unexpected starting opcode!"); 6068 } 6069 6070 // Rda as output parameter 6071 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6072 return MCDisassembler::Fail; 6073 6074 // Rda again as input parameter 6075 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6076 return MCDisassembler::Fail; 6077 6078 // Rm, the amount to shift by 6079 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6080 return MCDisassembler::Fail; 6081 6082 return S; 6083 } 6084 6085 // Otherwise, we decode as whichever opcode our caller has already 6086 // put into Inst. Those all look the same: 6087 6088 // RdaLo,RdaHi as output parameters 6089 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6090 return MCDisassembler::Fail; 6091 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6092 return MCDisassembler::Fail; 6093 6094 // RdaLo,RdaHi again as input parameters 6095 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6096 return MCDisassembler::Fail; 6097 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6098 return MCDisassembler::Fail; 6099 6100 // Rm, the amount to shift by 6101 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6102 return MCDisassembler::Fail; 6103 6104 return S; 6105 } 6106