1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Pull DecodeStatus and its enum values into the global namespace. 28 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 29 #define Success llvm::MCDisassembler::Success 30 #define Unpredictable llvm::MCDisassembler::SoftFail 31 #define Fail llvm::MCDisassembler::Fail 32 33 // Helper macro to perform setwise reduction of the current running status 34 // and another status, and return if the new status is Fail. 35 #define CHECK(S,X) do { \ 36 S = (DecodeStatus) ((int)S & (X)); \ 37 if (S == Fail) return Fail; \ 38 } while(0) 39 40 // Forward declare these because the autogenerated code will reference them. 41 // Definitions are further down. 42 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 43 uint64_t Address, const void *Decoder); 44 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 45 unsigned RegNo, uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 50 uint64_t Address, const void *Decoder); 51 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 52 uint64_t Address, const void *Decoder); 53 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 54 uint64_t Address, const void *Decoder); 55 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 56 uint64_t Address, const void *Decoder); 57 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 58 uint64_t Address, const void *Decoder); 59 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 60 unsigned RegNo, 61 uint64_t Address, 62 const void *Decoder); 63 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 64 uint64_t Address, const void *Decoder); 65 66 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 67 uint64_t Address, const void *Decoder); 68 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 69 uint64_t Address, const void *Decoder); 70 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 71 uint64_t Address, const void *Decoder); 72 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 73 uint64_t Address, const void *Decoder); 74 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 75 uint64_t Address, const void *Decoder); 76 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 77 uint64_t Address, const void *Decoder); 78 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 79 uint64_t Address, const void *Decoder); 80 81 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 82 uint64_t Address, const void *Decoder); 83 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 84 uint64_t Address, const void *Decoder); 85 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 86 unsigned Insn, 87 uint64_t Address, 88 const void *Decoder); 89 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 90 uint64_t Address, const void *Decoder); 91 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 92 uint64_t Address, const void *Decoder); 93 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 94 uint64_t Address, const void *Decoder); 95 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 96 uint64_t Address, const void *Decoder); 97 98 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 99 unsigned Insn, 100 uint64_t Adddress, 101 const void *Decoder); 102 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 103 uint64_t Address, const void *Decoder); 104 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 105 uint64_t Address, const void *Decoder); 106 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 125 uint64_t Address, const void *Decoder); 126 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 129 uint64_t Address, const void *Decoder); 130 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 147 uint64_t Address, const void *Decoder); 148 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178 179 180 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 225 uint64_t Address, const void *Decoder); 226 227 #include "ARMGenDisassemblerTables.inc" 228 #include "ARMGenInstrInfo.inc" 229 #include "ARMGenEDInfo.inc" 230 231 using namespace llvm; 232 233 static MCDisassembler *createARMDisassembler(const Target &T) { 234 return new ARMDisassembler; 235 } 236 237 static MCDisassembler *createThumbDisassembler(const Target &T) { 238 return new ThumbDisassembler; 239 } 240 241 EDInstInfo *ARMDisassembler::getEDInfo() const { 242 return instInfoARM; 243 } 244 245 EDInstInfo *ThumbDisassembler::getEDInfo() const { 246 return instInfoARM; 247 } 248 249 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 250 const MemoryObject &Region, 251 uint64_t Address, 252 raw_ostream &os) const { 253 uint8_t bytes[4]; 254 255 // We want to read exactly 4 bytes of data. 256 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 257 return Fail; 258 259 // Encoded as a small-endian 32-bit word in the stream. 260 uint32_t insn = (bytes[3] << 24) | 261 (bytes[2] << 16) | 262 (bytes[1] << 8) | 263 (bytes[0] << 0); 264 265 // Calling the auto-generated decoder function. 266 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); 267 if (result != Fail) { 268 Size = 4; 269 return result; 270 } 271 272 // Instructions that are shared between ARM and Thumb modes. 273 // FIXME: This shouldn't really exist. It's an artifact of the 274 // fact that we fail to encode a few instructions properly for Thumb. 275 MI.clear(); 276 result = decodeCommonInstruction32(MI, insn, Address, this); 277 if (result != Fail) { 278 Size = 4; 279 return result; 280 } 281 282 // VFP and NEON instructions, similarly, are shared between ARM 283 // and Thumb modes. 284 MI.clear(); 285 result = decodeVFPInstruction32(MI, insn, Address, this); 286 if (result != Fail) { 287 Size = 4; 288 return result; 289 } 290 291 MI.clear(); 292 result = decodeNEONDataInstruction32(MI, insn, Address, this); 293 if (result != Fail) { 294 Size = 4; 295 // Add a fake predicate operand, because we share these instruction 296 // definitions with Thumb2 where these instructions are predicable. 297 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 298 return result; 299 } 300 301 MI.clear(); 302 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 303 if (result != Fail) { 304 Size = 4; 305 // Add a fake predicate operand, because we share these instruction 306 // definitions with Thumb2 where these instructions are predicable. 307 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 308 return result; 309 } 310 311 MI.clear(); 312 result = decodeNEONDupInstruction32(MI, insn, Address, this); 313 if (result != Fail) { 314 Size = 4; 315 // Add a fake predicate operand, because we share these instruction 316 // definitions with Thumb2 where these instructions are predicable. 317 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 318 return result; 319 } 320 321 MI.clear(); 322 323 return Fail; 324 } 325 326 namespace llvm { 327 extern MCInstrDesc ARMInsts[]; 328 } 329 330 // Thumb1 instructions don't have explicit S bits. Rather, they 331 // implicitly set CPSR. Since it's not represented in the encoding, the 332 // auto-generated decoder won't inject the CPSR operand. We need to fix 333 // that as a post-pass. 334 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 335 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 336 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 337 MCInst::iterator I = MI.begin(); 338 for (unsigned i = 0; i < NumOps; ++i, ++I) { 339 if (I == MI.end()) break; 340 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 341 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 342 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 343 return; 344 } 345 } 346 347 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 348 } 349 350 // Most Thumb instructions don't have explicit predicates in the 351 // encoding, but rather get their predicates from IT context. We need 352 // to fix up the predicate operands using this context information as a 353 // post-pass. 354 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 355 // A few instructions actually have predicates encoded in them. Don't 356 // try to overwrite it if we're seeing one of those. 357 switch (MI.getOpcode()) { 358 case ARM::tBcc: 359 case ARM::t2Bcc: 360 return; 361 default: 362 break; 363 } 364 365 // If we're in an IT block, base the predicate on that. Otherwise, 366 // assume a predicate of AL. 367 unsigned CC; 368 if (!ITBlock.empty()) { 369 CC = ITBlock.back(); 370 ITBlock.pop_back(); 371 } else 372 CC = ARMCC::AL; 373 374 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 375 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 376 MCInst::iterator I = MI.begin(); 377 for (unsigned i = 0; i < NumOps; ++i, ++I) { 378 if (I == MI.end()) break; 379 if (OpInfo[i].isPredicate()) { 380 I = MI.insert(I, MCOperand::CreateImm(CC)); 381 ++I; 382 if (CC == ARMCC::AL) 383 MI.insert(I, MCOperand::CreateReg(0)); 384 else 385 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 386 return; 387 } 388 } 389 390 I = MI.insert(I, MCOperand::CreateImm(CC)); 391 ++I; 392 if (CC == ARMCC::AL) 393 MI.insert(I, MCOperand::CreateReg(0)); 394 else 395 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 396 } 397 398 // Thumb VFP instructions are a special case. Because we share their 399 // encodings between ARM and Thumb modes, and they are predicable in ARM 400 // mode, the auto-generated decoder will give them an (incorrect) 401 // predicate operand. We need to rewrite these operands based on the IT 402 // context as a post-pass. 403 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 404 unsigned CC; 405 if (!ITBlock.empty()) { 406 CC = ITBlock.back(); 407 ITBlock.pop_back(); 408 } else 409 CC = ARMCC::AL; 410 411 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 412 MCInst::iterator I = MI.begin(); 413 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 414 if (OpInfo[i].isPredicate() ) { 415 I->setImm(CC); 416 ++I; 417 if (CC == ARMCC::AL) 418 I->setReg(0); 419 else 420 I->setReg(ARM::CPSR); 421 return; 422 } 423 } 424 } 425 426 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 427 const MemoryObject &Region, 428 uint64_t Address, 429 raw_ostream &os) const { 430 uint8_t bytes[4]; 431 432 // We want to read exactly 2 bytes of data. 433 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 434 return Fail; 435 436 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 437 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); 438 if (result != Fail) { 439 Size = 2; 440 AddThumbPredicate(MI); 441 return result; 442 } 443 444 MI.clear(); 445 result = decodeThumbSBitInstruction16(MI, insn16, Address, this); 446 if (result) { 447 Size = 2; 448 bool InITBlock = !ITBlock.empty(); 449 AddThumbPredicate(MI); 450 AddThumb1SBit(MI, InITBlock); 451 return result; 452 } 453 454 MI.clear(); 455 result = decodeThumb2Instruction16(MI, insn16, Address, this); 456 if (result != Fail) { 457 Size = 2; 458 AddThumbPredicate(MI); 459 460 // If we find an IT instruction, we need to parse its condition 461 // code and mask operands so that we can apply them correctly 462 // to the subsequent instructions. 463 if (MI.getOpcode() == ARM::t2IT) { 464 unsigned firstcond = MI.getOperand(0).getImm(); 465 uint32_t mask = MI.getOperand(1).getImm(); 466 unsigned zeros = CountTrailingZeros_32(mask); 467 mask >>= zeros+1; 468 469 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 470 if (firstcond ^ (mask & 1)) 471 ITBlock.push_back(firstcond ^ 1); 472 else 473 ITBlock.push_back(firstcond); 474 mask >>= 1; 475 } 476 ITBlock.push_back(firstcond); 477 } 478 479 return result; 480 } 481 482 // We want to read exactly 4 bytes of data. 483 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 484 return Fail; 485 486 uint32_t insn32 = (bytes[3] << 8) | 487 (bytes[2] << 0) | 488 (bytes[1] << 24) | 489 (bytes[0] << 16); 490 MI.clear(); 491 result = decodeThumbInstruction32(MI, insn32, Address, this); 492 if (result != Fail) { 493 Size = 4; 494 bool InITBlock = ITBlock.size(); 495 AddThumbPredicate(MI); 496 AddThumb1SBit(MI, InITBlock); 497 return result; 498 } 499 500 MI.clear(); 501 result = decodeThumb2Instruction32(MI, insn32, Address, this); 502 if (result != Fail) { 503 Size = 4; 504 AddThumbPredicate(MI); 505 return result; 506 } 507 508 MI.clear(); 509 result = decodeCommonInstruction32(MI, insn32, Address, this); 510 if (result != Fail) { 511 Size = 4; 512 AddThumbPredicate(MI); 513 return result; 514 } 515 516 MI.clear(); 517 result = decodeVFPInstruction32(MI, insn32, Address, this); 518 if (result != Fail) { 519 Size = 4; 520 UpdateThumbVFPPredicate(MI); 521 return result; 522 } 523 524 MI.clear(); 525 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 526 if (result != Fail) { 527 Size = 4; 528 AddThumbPredicate(MI); 529 return result; 530 } 531 532 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 533 MI.clear(); 534 uint32_t NEONLdStInsn = insn32; 535 NEONLdStInsn &= 0xF0FFFFFF; 536 NEONLdStInsn |= 0x04000000; 537 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 538 if (result != Fail) { 539 Size = 4; 540 AddThumbPredicate(MI); 541 return result; 542 } 543 } 544 545 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 546 MI.clear(); 547 uint32_t NEONDataInsn = insn32; 548 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 549 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 550 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 551 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 552 if (result != Fail) { 553 Size = 4; 554 AddThumbPredicate(MI); 555 return result; 556 } 557 } 558 559 return Fail; 560 } 561 562 563 extern "C" void LLVMInitializeARMDisassembler() { 564 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 565 createARMDisassembler); 566 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 567 createThumbDisassembler); 568 } 569 570 static const unsigned GPRDecoderTable[] = { 571 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 572 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 573 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 574 ARM::R12, ARM::SP, ARM::LR, ARM::PC 575 }; 576 577 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 578 uint64_t Address, const void *Decoder) { 579 if (RegNo > 15) 580 return Fail; 581 582 unsigned Register = GPRDecoderTable[RegNo]; 583 Inst.addOperand(MCOperand::CreateReg(Register)); 584 return Success; 585 } 586 587 static DecodeStatus 588 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 589 uint64_t Address, const void *Decoder) { 590 if (RegNo == 15) return Fail; 591 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 592 } 593 594 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 595 uint64_t Address, const void *Decoder) { 596 if (RegNo > 7) 597 return Fail; 598 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 599 } 600 601 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 602 uint64_t Address, const void *Decoder) { 603 unsigned Register = 0; 604 switch (RegNo) { 605 case 0: 606 Register = ARM::R0; 607 break; 608 case 1: 609 Register = ARM::R1; 610 break; 611 case 2: 612 Register = ARM::R2; 613 break; 614 case 3: 615 Register = ARM::R3; 616 break; 617 case 9: 618 Register = ARM::R9; 619 break; 620 case 12: 621 Register = ARM::R12; 622 break; 623 default: 624 return Fail; 625 } 626 627 Inst.addOperand(MCOperand::CreateReg(Register)); 628 return Success; 629 } 630 631 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 632 uint64_t Address, const void *Decoder) { 633 if (RegNo == 13 || RegNo == 15) return Fail; 634 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 635 } 636 637 static const unsigned SPRDecoderTable[] = { 638 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 639 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 640 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 641 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 642 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 643 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 644 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 645 ARM::S28, ARM::S29, ARM::S30, ARM::S31 646 }; 647 648 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 649 uint64_t Address, const void *Decoder) { 650 if (RegNo > 31) 651 return Fail; 652 653 unsigned Register = SPRDecoderTable[RegNo]; 654 Inst.addOperand(MCOperand::CreateReg(Register)); 655 return Success; 656 } 657 658 static const unsigned DPRDecoderTable[] = { 659 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 660 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 661 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 662 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 663 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 664 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 665 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 666 ARM::D28, ARM::D29, ARM::D30, ARM::D31 667 }; 668 669 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 670 uint64_t Address, const void *Decoder) { 671 if (RegNo > 31) 672 return Fail; 673 674 unsigned Register = DPRDecoderTable[RegNo]; 675 Inst.addOperand(MCOperand::CreateReg(Register)); 676 return Success; 677 } 678 679 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 680 uint64_t Address, const void *Decoder) { 681 if (RegNo > 7) 682 return Fail; 683 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 684 } 685 686 static DecodeStatus 687 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 688 uint64_t Address, const void *Decoder) { 689 if (RegNo > 15) 690 return Fail; 691 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 692 } 693 694 static const unsigned QPRDecoderTable[] = { 695 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 696 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 697 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 698 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 699 }; 700 701 702 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 703 uint64_t Address, const void *Decoder) { 704 if (RegNo > 31) 705 return Fail; 706 RegNo >>= 1; 707 708 unsigned Register = QPRDecoderTable[RegNo]; 709 Inst.addOperand(MCOperand::CreateReg(Register)); 710 return Success; 711 } 712 713 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 714 uint64_t Address, const void *Decoder) { 715 if (Val == 0xF) return Fail; 716 // AL predicate is not allowed on Thumb1 branches. 717 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 718 return Fail; 719 Inst.addOperand(MCOperand::CreateImm(Val)); 720 if (Val == ARMCC::AL) { 721 Inst.addOperand(MCOperand::CreateReg(0)); 722 } else 723 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 724 return Success; 725 } 726 727 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 728 uint64_t Address, const void *Decoder) { 729 if (Val) 730 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 731 else 732 Inst.addOperand(MCOperand::CreateReg(0)); 733 return Success; 734 } 735 736 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 737 uint64_t Address, const void *Decoder) { 738 uint32_t imm = Val & 0xFF; 739 uint32_t rot = (Val & 0xF00) >> 7; 740 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 741 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 742 return Success; 743 } 744 745 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 746 uint64_t Address, const void *Decoder) { 747 Val <<= 2; 748 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 749 return Success; 750 } 751 752 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 753 uint64_t Address, const void *Decoder) { 754 DecodeStatus S = Success; 755 756 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 757 unsigned type = fieldFromInstruction32(Val, 5, 2); 758 unsigned imm = fieldFromInstruction32(Val, 7, 5); 759 760 // Register-immediate 761 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 762 763 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 764 switch (type) { 765 case 0: 766 Shift = ARM_AM::lsl; 767 break; 768 case 1: 769 Shift = ARM_AM::lsr; 770 break; 771 case 2: 772 Shift = ARM_AM::asr; 773 break; 774 case 3: 775 Shift = ARM_AM::ror; 776 break; 777 } 778 779 if (Shift == ARM_AM::ror && imm == 0) 780 Shift = ARM_AM::rrx; 781 782 unsigned Op = Shift | (imm << 3); 783 Inst.addOperand(MCOperand::CreateImm(Op)); 784 785 return S; 786 } 787 788 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 789 uint64_t Address, const void *Decoder) { 790 DecodeStatus S = Success; 791 792 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 793 unsigned type = fieldFromInstruction32(Val, 5, 2); 794 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 795 796 // Register-register 797 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 798 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); 799 800 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 801 switch (type) { 802 case 0: 803 Shift = ARM_AM::lsl; 804 break; 805 case 1: 806 Shift = ARM_AM::lsr; 807 break; 808 case 2: 809 Shift = ARM_AM::asr; 810 break; 811 case 3: 812 Shift = ARM_AM::ror; 813 break; 814 } 815 816 Inst.addOperand(MCOperand::CreateImm(Shift)); 817 818 return S; 819 } 820 821 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 822 uint64_t Address, const void *Decoder) { 823 DecodeStatus S = Success; 824 825 // Empty register lists are not allowed. 826 if (CountPopulation_32(Val) == 0) return Fail; 827 for (unsigned i = 0; i < 16; ++i) { 828 if (Val & (1 << i)) { 829 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); 830 } 831 } 832 833 return S; 834 } 835 836 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 837 uint64_t Address, const void *Decoder) { 838 DecodeStatus S = Success; 839 840 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 841 unsigned regs = Val & 0xFF; 842 843 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); 844 for (unsigned i = 0; i < (regs - 1); ++i) { 845 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); 846 } 847 848 return S; 849 } 850 851 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 852 uint64_t Address, const void *Decoder) { 853 DecodeStatus S = Success; 854 855 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 856 unsigned regs = (Val & 0xFF) / 2; 857 858 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); 859 for (unsigned i = 0; i < (regs - 1); ++i) { 860 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); 861 } 862 863 return S; 864 } 865 866 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 867 uint64_t Address, const void *Decoder) { 868 // This operand encodes a mask of contiguous zeros between a specified MSB 869 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 870 // the mask of all bits LSB-and-lower, and then xor them to create 871 // the mask of that's all ones on [msb, lsb]. Finally we not it to 872 // create the final mask. 873 unsigned msb = fieldFromInstruction32(Val, 5, 5); 874 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 875 uint32_t msb_mask = (1 << (msb+1)) - 1; 876 uint32_t lsb_mask = (1 << lsb) - 1; 877 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 878 return Success; 879 } 880 881 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 882 uint64_t Address, const void *Decoder) { 883 DecodeStatus S = Success; 884 885 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 886 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 887 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 888 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 889 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 890 unsigned U = fieldFromInstruction32(Insn, 23, 1); 891 892 switch (Inst.getOpcode()) { 893 case ARM::LDC_OFFSET: 894 case ARM::LDC_PRE: 895 case ARM::LDC_POST: 896 case ARM::LDC_OPTION: 897 case ARM::LDCL_OFFSET: 898 case ARM::LDCL_PRE: 899 case ARM::LDCL_POST: 900 case ARM::LDCL_OPTION: 901 case ARM::STC_OFFSET: 902 case ARM::STC_PRE: 903 case ARM::STC_POST: 904 case ARM::STC_OPTION: 905 case ARM::STCL_OFFSET: 906 case ARM::STCL_PRE: 907 case ARM::STCL_POST: 908 case ARM::STCL_OPTION: 909 if (coproc == 0xA || coproc == 0xB) 910 return Fail; 911 break; 912 default: 913 break; 914 } 915 916 Inst.addOperand(MCOperand::CreateImm(coproc)); 917 Inst.addOperand(MCOperand::CreateImm(CRd)); 918 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 919 switch (Inst.getOpcode()) { 920 case ARM::LDC_OPTION: 921 case ARM::LDCL_OPTION: 922 case ARM::LDC2_OPTION: 923 case ARM::LDC2L_OPTION: 924 case ARM::STC_OPTION: 925 case ARM::STCL_OPTION: 926 case ARM::STC2_OPTION: 927 case ARM::STC2L_OPTION: 928 case ARM::LDCL_POST: 929 case ARM::STCL_POST: 930 break; 931 default: 932 Inst.addOperand(MCOperand::CreateReg(0)); 933 break; 934 } 935 936 unsigned P = fieldFromInstruction32(Insn, 24, 1); 937 unsigned W = fieldFromInstruction32(Insn, 21, 1); 938 939 bool writeback = (P == 0) || (W == 1); 940 unsigned idx_mode = 0; 941 if (P && writeback) 942 idx_mode = ARMII::IndexModePre; 943 else if (!P && writeback) 944 idx_mode = ARMII::IndexModePost; 945 946 switch (Inst.getOpcode()) { 947 case ARM::LDCL_POST: 948 case ARM::STCL_POST: 949 imm |= U << 8; 950 case ARM::LDC_OPTION: 951 case ARM::LDCL_OPTION: 952 case ARM::LDC2_OPTION: 953 case ARM::LDC2L_OPTION: 954 case ARM::STC_OPTION: 955 case ARM::STCL_OPTION: 956 case ARM::STC2_OPTION: 957 case ARM::STC2L_OPTION: 958 Inst.addOperand(MCOperand::CreateImm(imm)); 959 break; 960 default: 961 if (U) 962 Inst.addOperand(MCOperand::CreateImm( 963 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 964 else 965 Inst.addOperand(MCOperand::CreateImm( 966 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 967 break; 968 } 969 970 switch (Inst.getOpcode()) { 971 case ARM::LDC_OFFSET: 972 case ARM::LDC_PRE: 973 case ARM::LDC_POST: 974 case ARM::LDC_OPTION: 975 case ARM::LDCL_OFFSET: 976 case ARM::LDCL_PRE: 977 case ARM::LDCL_POST: 978 case ARM::LDCL_OPTION: 979 case ARM::STC_OFFSET: 980 case ARM::STC_PRE: 981 case ARM::STC_POST: 982 case ARM::STC_OPTION: 983 case ARM::STCL_OFFSET: 984 case ARM::STCL_PRE: 985 case ARM::STCL_POST: 986 case ARM::STCL_OPTION: 987 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 988 break; 989 default: 990 break; 991 } 992 993 return S; 994 } 995 996 static DecodeStatus 997 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 998 uint64_t Address, const void *Decoder) { 999 DecodeStatus S = Success; 1000 1001 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1002 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1003 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1004 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1005 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1006 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1007 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1008 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1009 1010 // On stores, the writeback operand precedes Rt. 1011 switch (Inst.getOpcode()) { 1012 case ARM::STR_POST_IMM: 1013 case ARM::STR_POST_REG: 1014 case ARM::STRB_POST_IMM: 1015 case ARM::STRB_POST_REG: 1016 case ARM::STRT_POST_REG: 1017 case ARM::STRT_POST_IMM: 1018 case ARM::STRBT_POST_REG: 1019 case ARM::STRBT_POST_IMM: 1020 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1021 break; 1022 default: 1023 break; 1024 } 1025 1026 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1027 1028 // On loads, the writeback operand comes after Rt. 1029 switch (Inst.getOpcode()) { 1030 case ARM::LDR_POST_IMM: 1031 case ARM::LDR_POST_REG: 1032 case ARM::LDRB_POST_IMM: 1033 case ARM::LDRB_POST_REG: 1034 case ARM::LDR_PRE: 1035 case ARM::LDRB_PRE: 1036 case ARM::LDRBT_POST_REG: 1037 case ARM::LDRBT_POST_IMM: 1038 case ARM::LDRT_POST_REG: 1039 case ARM::LDRT_POST_IMM: 1040 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1041 break; 1042 default: 1043 break; 1044 } 1045 1046 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1047 1048 ARM_AM::AddrOpc Op = ARM_AM::add; 1049 if (!fieldFromInstruction32(Insn, 23, 1)) 1050 Op = ARM_AM::sub; 1051 1052 bool writeback = (P == 0) || (W == 1); 1053 unsigned idx_mode = 0; 1054 if (P && writeback) 1055 idx_mode = ARMII::IndexModePre; 1056 else if (!P && writeback) 1057 idx_mode = ARMII::IndexModePost; 1058 1059 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE 1060 1061 if (reg) { 1062 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1063 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1064 switch( fieldFromInstruction32(Insn, 5, 2)) { 1065 case 0: 1066 Opc = ARM_AM::lsl; 1067 break; 1068 case 1: 1069 Opc = ARM_AM::lsr; 1070 break; 1071 case 2: 1072 Opc = ARM_AM::asr; 1073 break; 1074 case 3: 1075 Opc = ARM_AM::ror; 1076 break; 1077 default: 1078 return Fail; 1079 } 1080 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1081 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1082 1083 Inst.addOperand(MCOperand::CreateImm(imm)); 1084 } else { 1085 Inst.addOperand(MCOperand::CreateReg(0)); 1086 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1087 Inst.addOperand(MCOperand::CreateImm(tmp)); 1088 } 1089 1090 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1091 1092 return S; 1093 } 1094 1095 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1096 uint64_t Address, const void *Decoder) { 1097 DecodeStatus S = Success; 1098 1099 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1100 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1101 unsigned type = fieldFromInstruction32(Val, 5, 2); 1102 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1103 unsigned U = fieldFromInstruction32(Val, 12, 1); 1104 1105 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1106 switch (type) { 1107 case 0: 1108 ShOp = ARM_AM::lsl; 1109 break; 1110 case 1: 1111 ShOp = ARM_AM::lsr; 1112 break; 1113 case 2: 1114 ShOp = ARM_AM::asr; 1115 break; 1116 case 3: 1117 ShOp = ARM_AM::ror; 1118 break; 1119 } 1120 1121 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1122 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1123 unsigned shift; 1124 if (U) 1125 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1126 else 1127 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1128 Inst.addOperand(MCOperand::CreateImm(shift)); 1129 1130 return S; 1131 } 1132 1133 static DecodeStatus 1134 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1135 uint64_t Address, const void *Decoder) { 1136 DecodeStatus S = Success; 1137 1138 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1139 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1140 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1141 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1142 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1143 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1144 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1145 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1146 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1147 1148 bool writeback = (W == 1) | (P == 0); 1149 1150 // For {LD,ST}RD, Rt must be even, else undefined. 1151 switch (Inst.getOpcode()) { 1152 case ARM::STRD: 1153 case ARM::STRD_PRE: 1154 case ARM::STRD_POST: 1155 case ARM::LDRD: 1156 case ARM::LDRD_PRE: 1157 case ARM::LDRD_POST: 1158 if (Rt & 0x1) return Fail; 1159 break; 1160 default: 1161 break; 1162 } 1163 1164 if (writeback) { // Writeback 1165 if (P) 1166 U |= ARMII::IndexModePre << 9; 1167 else 1168 U |= ARMII::IndexModePost << 9; 1169 1170 // On stores, the writeback operand precedes Rt. 1171 switch (Inst.getOpcode()) { 1172 case ARM::STRD: 1173 case ARM::STRD_PRE: 1174 case ARM::STRD_POST: 1175 case ARM::STRH: 1176 case ARM::STRH_PRE: 1177 case ARM::STRH_POST: 1178 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1179 break; 1180 default: 1181 break; 1182 } 1183 } 1184 1185 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1186 switch (Inst.getOpcode()) { 1187 case ARM::STRD: 1188 case ARM::STRD_PRE: 1189 case ARM::STRD_POST: 1190 case ARM::LDRD: 1191 case ARM::LDRD_PRE: 1192 case ARM::LDRD_POST: 1193 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 1194 break; 1195 default: 1196 break; 1197 } 1198 1199 if (writeback) { 1200 // On loads, the writeback operand comes after Rt. 1201 switch (Inst.getOpcode()) { 1202 case ARM::LDRD: 1203 case ARM::LDRD_PRE: 1204 case ARM::LDRD_POST: 1205 case ARM::LDRH: 1206 case ARM::LDRH_PRE: 1207 case ARM::LDRH_POST: 1208 case ARM::LDRSH: 1209 case ARM::LDRSH_PRE: 1210 case ARM::LDRSH_POST: 1211 case ARM::LDRSB: 1212 case ARM::LDRSB_PRE: 1213 case ARM::LDRSB_POST: 1214 case ARM::LDRHTr: 1215 case ARM::LDRSBTr: 1216 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1217 break; 1218 default: 1219 break; 1220 } 1221 } 1222 1223 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1224 1225 if (type) { 1226 Inst.addOperand(MCOperand::CreateReg(0)); 1227 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1228 } else { 1229 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1230 Inst.addOperand(MCOperand::CreateImm(U)); 1231 } 1232 1233 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1234 1235 return S; 1236 } 1237 1238 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1239 uint64_t Address, const void *Decoder) { 1240 DecodeStatus S = Success; 1241 1242 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1243 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1244 1245 switch (mode) { 1246 case 0: 1247 mode = ARM_AM::da; 1248 break; 1249 case 1: 1250 mode = ARM_AM::ia; 1251 break; 1252 case 2: 1253 mode = ARM_AM::db; 1254 break; 1255 case 3: 1256 mode = ARM_AM::ib; 1257 break; 1258 } 1259 1260 Inst.addOperand(MCOperand::CreateImm(mode)); 1261 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1262 1263 return S; 1264 } 1265 1266 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1267 unsigned Insn, 1268 uint64_t Address, const void *Decoder) { 1269 DecodeStatus S = Success; 1270 1271 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1272 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1273 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1274 1275 if (pred == 0xF) { 1276 switch (Inst.getOpcode()) { 1277 case ARM::STMDA: 1278 Inst.setOpcode(ARM::RFEDA); 1279 break; 1280 case ARM::STMDA_UPD: 1281 Inst.setOpcode(ARM::RFEDA_UPD); 1282 break; 1283 case ARM::STMDB: 1284 Inst.setOpcode(ARM::RFEDB); 1285 break; 1286 case ARM::STMDB_UPD: 1287 Inst.setOpcode(ARM::RFEDB_UPD); 1288 break; 1289 case ARM::STMIA: 1290 Inst.setOpcode(ARM::RFEIA); 1291 break; 1292 case ARM::STMIA_UPD: 1293 Inst.setOpcode(ARM::RFEIA_UPD); 1294 break; 1295 case ARM::STMIB: 1296 Inst.setOpcode(ARM::RFEIB); 1297 break; 1298 case ARM::STMIB_UPD: 1299 Inst.setOpcode(ARM::RFEIB_UPD); 1300 break; 1301 } 1302 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1303 } 1304 1305 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1306 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied 1307 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1308 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); 1309 1310 return S; 1311 } 1312 1313 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1314 uint64_t Address, const void *Decoder) { 1315 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1316 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1317 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1318 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1319 1320 // imod == '01' --> UNPREDICTABLE 1321 if (imod == 1) return Fail; 1322 1323 if (M && mode && imod && iflags) { 1324 Inst.setOpcode(ARM::CPS3p); 1325 Inst.addOperand(MCOperand::CreateImm(imod)); 1326 Inst.addOperand(MCOperand::CreateImm(iflags)); 1327 Inst.addOperand(MCOperand::CreateImm(mode)); 1328 return Success; 1329 } else if (!mode && !M) { 1330 Inst.setOpcode(ARM::CPS2p); 1331 Inst.addOperand(MCOperand::CreateImm(imod)); 1332 Inst.addOperand(MCOperand::CreateImm(iflags)); 1333 return Success; 1334 } else if (!imod && !iflags && M) { 1335 Inst.setOpcode(ARM::CPS1p); 1336 Inst.addOperand(MCOperand::CreateImm(mode)); 1337 return Success; 1338 } 1339 1340 return Fail; 1341 } 1342 1343 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1344 uint64_t Address, const void *Decoder) { 1345 DecodeStatus S = Success; 1346 1347 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1348 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1349 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1350 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1351 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1352 1353 if (pred == 0xF) 1354 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1355 1356 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); 1357 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); 1358 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1359 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); 1360 1361 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1362 1363 return S; 1364 } 1365 1366 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1367 uint64_t Address, const void *Decoder) { 1368 DecodeStatus S = Success; 1369 1370 unsigned add = fieldFromInstruction32(Val, 12, 1); 1371 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1372 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1373 1374 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1375 1376 if (!add) imm *= -1; 1377 if (imm == 0 && !add) imm = INT32_MIN; 1378 Inst.addOperand(MCOperand::CreateImm(imm)); 1379 1380 return S; 1381 } 1382 1383 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1384 uint64_t Address, const void *Decoder) { 1385 DecodeStatus S = Success; 1386 1387 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1388 unsigned U = fieldFromInstruction32(Val, 8, 1); 1389 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1390 1391 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1392 1393 if (U) 1394 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1395 else 1396 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1397 1398 return S; 1399 } 1400 1401 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1402 uint64_t Address, const void *Decoder) { 1403 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1404 } 1405 1406 static DecodeStatus 1407 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1408 uint64_t Address, const void *Decoder) { 1409 DecodeStatus S = Success; 1410 1411 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1412 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1413 1414 if (pred == 0xF) { 1415 Inst.setOpcode(ARM::BLXi); 1416 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1417 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1418 return S; 1419 } 1420 1421 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1422 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1423 1424 return S; 1425 } 1426 1427 1428 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1429 uint64_t Address, const void *Decoder) { 1430 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1431 return Success; 1432 } 1433 1434 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1435 uint64_t Address, const void *Decoder) { 1436 DecodeStatus S = Success; 1437 1438 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1439 unsigned align = fieldFromInstruction32(Val, 4, 2); 1440 1441 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1442 if (!align) 1443 Inst.addOperand(MCOperand::CreateImm(0)); 1444 else 1445 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1446 1447 return S; 1448 } 1449 1450 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1451 uint64_t Address, const void *Decoder) { 1452 DecodeStatus S = Success; 1453 1454 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1455 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1456 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1457 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1458 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1459 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1460 1461 // First output register 1462 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1463 1464 // Second output register 1465 switch (Inst.getOpcode()) { 1466 case ARM::VLD1q8: 1467 case ARM::VLD1q16: 1468 case ARM::VLD1q32: 1469 case ARM::VLD1q64: 1470 case ARM::VLD1q8_UPD: 1471 case ARM::VLD1q16_UPD: 1472 case ARM::VLD1q32_UPD: 1473 case ARM::VLD1q64_UPD: 1474 case ARM::VLD1d8T: 1475 case ARM::VLD1d16T: 1476 case ARM::VLD1d32T: 1477 case ARM::VLD1d64T: 1478 case ARM::VLD1d8T_UPD: 1479 case ARM::VLD1d16T_UPD: 1480 case ARM::VLD1d32T_UPD: 1481 case ARM::VLD1d64T_UPD: 1482 case ARM::VLD1d8Q: 1483 case ARM::VLD1d16Q: 1484 case ARM::VLD1d32Q: 1485 case ARM::VLD1d64Q: 1486 case ARM::VLD1d8Q_UPD: 1487 case ARM::VLD1d16Q_UPD: 1488 case ARM::VLD1d32Q_UPD: 1489 case ARM::VLD1d64Q_UPD: 1490 case ARM::VLD2d8: 1491 case ARM::VLD2d16: 1492 case ARM::VLD2d32: 1493 case ARM::VLD2d8_UPD: 1494 case ARM::VLD2d16_UPD: 1495 case ARM::VLD2d32_UPD: 1496 case ARM::VLD2q8: 1497 case ARM::VLD2q16: 1498 case ARM::VLD2q32: 1499 case ARM::VLD2q8_UPD: 1500 case ARM::VLD2q16_UPD: 1501 case ARM::VLD2q32_UPD: 1502 case ARM::VLD3d8: 1503 case ARM::VLD3d16: 1504 case ARM::VLD3d32: 1505 case ARM::VLD3d8_UPD: 1506 case ARM::VLD3d16_UPD: 1507 case ARM::VLD3d32_UPD: 1508 case ARM::VLD4d8: 1509 case ARM::VLD4d16: 1510 case ARM::VLD4d32: 1511 case ARM::VLD4d8_UPD: 1512 case ARM::VLD4d16_UPD: 1513 case ARM::VLD4d32_UPD: 1514 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1515 break; 1516 case ARM::VLD2b8: 1517 case ARM::VLD2b16: 1518 case ARM::VLD2b32: 1519 case ARM::VLD2b8_UPD: 1520 case ARM::VLD2b16_UPD: 1521 case ARM::VLD2b32_UPD: 1522 case ARM::VLD3q8: 1523 case ARM::VLD3q16: 1524 case ARM::VLD3q32: 1525 case ARM::VLD3q8_UPD: 1526 case ARM::VLD3q16_UPD: 1527 case ARM::VLD3q32_UPD: 1528 case ARM::VLD4q8: 1529 case ARM::VLD4q16: 1530 case ARM::VLD4q32: 1531 case ARM::VLD4q8_UPD: 1532 case ARM::VLD4q16_UPD: 1533 case ARM::VLD4q32_UPD: 1534 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1535 default: 1536 break; 1537 } 1538 1539 // Third output register 1540 switch(Inst.getOpcode()) { 1541 case ARM::VLD1d8T: 1542 case ARM::VLD1d16T: 1543 case ARM::VLD1d32T: 1544 case ARM::VLD1d64T: 1545 case ARM::VLD1d8T_UPD: 1546 case ARM::VLD1d16T_UPD: 1547 case ARM::VLD1d32T_UPD: 1548 case ARM::VLD1d64T_UPD: 1549 case ARM::VLD1d8Q: 1550 case ARM::VLD1d16Q: 1551 case ARM::VLD1d32Q: 1552 case ARM::VLD1d64Q: 1553 case ARM::VLD1d8Q_UPD: 1554 case ARM::VLD1d16Q_UPD: 1555 case ARM::VLD1d32Q_UPD: 1556 case ARM::VLD1d64Q_UPD: 1557 case ARM::VLD2q8: 1558 case ARM::VLD2q16: 1559 case ARM::VLD2q32: 1560 case ARM::VLD2q8_UPD: 1561 case ARM::VLD2q16_UPD: 1562 case ARM::VLD2q32_UPD: 1563 case ARM::VLD3d8: 1564 case ARM::VLD3d16: 1565 case ARM::VLD3d32: 1566 case ARM::VLD3d8_UPD: 1567 case ARM::VLD3d16_UPD: 1568 case ARM::VLD3d32_UPD: 1569 case ARM::VLD4d8: 1570 case ARM::VLD4d16: 1571 case ARM::VLD4d32: 1572 case ARM::VLD4d8_UPD: 1573 case ARM::VLD4d16_UPD: 1574 case ARM::VLD4d32_UPD: 1575 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1576 break; 1577 case ARM::VLD3q8: 1578 case ARM::VLD3q16: 1579 case ARM::VLD3q32: 1580 case ARM::VLD3q8_UPD: 1581 case ARM::VLD3q16_UPD: 1582 case ARM::VLD3q32_UPD: 1583 case ARM::VLD4q8: 1584 case ARM::VLD4q16: 1585 case ARM::VLD4q32: 1586 case ARM::VLD4q8_UPD: 1587 case ARM::VLD4q16_UPD: 1588 case ARM::VLD4q32_UPD: 1589 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1590 break; 1591 default: 1592 break; 1593 } 1594 1595 // Fourth output register 1596 switch (Inst.getOpcode()) { 1597 case ARM::VLD1d8Q: 1598 case ARM::VLD1d16Q: 1599 case ARM::VLD1d32Q: 1600 case ARM::VLD1d64Q: 1601 case ARM::VLD1d8Q_UPD: 1602 case ARM::VLD1d16Q_UPD: 1603 case ARM::VLD1d32Q_UPD: 1604 case ARM::VLD1d64Q_UPD: 1605 case ARM::VLD2q8: 1606 case ARM::VLD2q16: 1607 case ARM::VLD2q32: 1608 case ARM::VLD2q8_UPD: 1609 case ARM::VLD2q16_UPD: 1610 case ARM::VLD2q32_UPD: 1611 case ARM::VLD4d8: 1612 case ARM::VLD4d16: 1613 case ARM::VLD4d32: 1614 case ARM::VLD4d8_UPD: 1615 case ARM::VLD4d16_UPD: 1616 case ARM::VLD4d32_UPD: 1617 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1618 break; 1619 case ARM::VLD4q8: 1620 case ARM::VLD4q16: 1621 case ARM::VLD4q32: 1622 case ARM::VLD4q8_UPD: 1623 case ARM::VLD4q16_UPD: 1624 case ARM::VLD4q32_UPD: 1625 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1626 break; 1627 default: 1628 break; 1629 } 1630 1631 // Writeback operand 1632 switch (Inst.getOpcode()) { 1633 case ARM::VLD1d8_UPD: 1634 case ARM::VLD1d16_UPD: 1635 case ARM::VLD1d32_UPD: 1636 case ARM::VLD1d64_UPD: 1637 case ARM::VLD1q8_UPD: 1638 case ARM::VLD1q16_UPD: 1639 case ARM::VLD1q32_UPD: 1640 case ARM::VLD1q64_UPD: 1641 case ARM::VLD1d8T_UPD: 1642 case ARM::VLD1d16T_UPD: 1643 case ARM::VLD1d32T_UPD: 1644 case ARM::VLD1d64T_UPD: 1645 case ARM::VLD1d8Q_UPD: 1646 case ARM::VLD1d16Q_UPD: 1647 case ARM::VLD1d32Q_UPD: 1648 case ARM::VLD1d64Q_UPD: 1649 case ARM::VLD2d8_UPD: 1650 case ARM::VLD2d16_UPD: 1651 case ARM::VLD2d32_UPD: 1652 case ARM::VLD2q8_UPD: 1653 case ARM::VLD2q16_UPD: 1654 case ARM::VLD2q32_UPD: 1655 case ARM::VLD2b8_UPD: 1656 case ARM::VLD2b16_UPD: 1657 case ARM::VLD2b32_UPD: 1658 case ARM::VLD3d8_UPD: 1659 case ARM::VLD3d16_UPD: 1660 case ARM::VLD3d32_UPD: 1661 case ARM::VLD3q8_UPD: 1662 case ARM::VLD3q16_UPD: 1663 case ARM::VLD3q32_UPD: 1664 case ARM::VLD4d8_UPD: 1665 case ARM::VLD4d16_UPD: 1666 case ARM::VLD4d32_UPD: 1667 case ARM::VLD4q8_UPD: 1668 case ARM::VLD4q16_UPD: 1669 case ARM::VLD4q32_UPD: 1670 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1671 break; 1672 default: 1673 break; 1674 } 1675 1676 // AddrMode6 Base (register+alignment) 1677 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1678 1679 // AddrMode6 Offset (register) 1680 if (Rm == 0xD) 1681 Inst.addOperand(MCOperand::CreateReg(0)); 1682 else if (Rm != 0xF) { 1683 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1684 } 1685 1686 return S; 1687 } 1688 1689 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1690 uint64_t Address, const void *Decoder) { 1691 DecodeStatus S = Success; 1692 1693 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1694 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1695 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1696 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1697 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1698 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1699 1700 // Writeback Operand 1701 switch (Inst.getOpcode()) { 1702 case ARM::VST1d8_UPD: 1703 case ARM::VST1d16_UPD: 1704 case ARM::VST1d32_UPD: 1705 case ARM::VST1d64_UPD: 1706 case ARM::VST1q8_UPD: 1707 case ARM::VST1q16_UPD: 1708 case ARM::VST1q32_UPD: 1709 case ARM::VST1q64_UPD: 1710 case ARM::VST1d8T_UPD: 1711 case ARM::VST1d16T_UPD: 1712 case ARM::VST1d32T_UPD: 1713 case ARM::VST1d64T_UPD: 1714 case ARM::VST1d8Q_UPD: 1715 case ARM::VST1d16Q_UPD: 1716 case ARM::VST1d32Q_UPD: 1717 case ARM::VST1d64Q_UPD: 1718 case ARM::VST2d8_UPD: 1719 case ARM::VST2d16_UPD: 1720 case ARM::VST2d32_UPD: 1721 case ARM::VST2q8_UPD: 1722 case ARM::VST2q16_UPD: 1723 case ARM::VST2q32_UPD: 1724 case ARM::VST2b8_UPD: 1725 case ARM::VST2b16_UPD: 1726 case ARM::VST2b32_UPD: 1727 case ARM::VST3d8_UPD: 1728 case ARM::VST3d16_UPD: 1729 case ARM::VST3d32_UPD: 1730 case ARM::VST3q8_UPD: 1731 case ARM::VST3q16_UPD: 1732 case ARM::VST3q32_UPD: 1733 case ARM::VST4d8_UPD: 1734 case ARM::VST4d16_UPD: 1735 case ARM::VST4d32_UPD: 1736 case ARM::VST4q8_UPD: 1737 case ARM::VST4q16_UPD: 1738 case ARM::VST4q32_UPD: 1739 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1740 break; 1741 default: 1742 break; 1743 } 1744 1745 // AddrMode6 Base (register+alignment) 1746 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1747 1748 // AddrMode6 Offset (register) 1749 if (Rm == 0xD) 1750 Inst.addOperand(MCOperand::CreateReg(0)); 1751 else if (Rm != 0xF) { 1752 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1753 } 1754 1755 // First input register 1756 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1757 1758 // Second input register 1759 switch (Inst.getOpcode()) { 1760 case ARM::VST1q8: 1761 case ARM::VST1q16: 1762 case ARM::VST1q32: 1763 case ARM::VST1q64: 1764 case ARM::VST1q8_UPD: 1765 case ARM::VST1q16_UPD: 1766 case ARM::VST1q32_UPD: 1767 case ARM::VST1q64_UPD: 1768 case ARM::VST1d8T: 1769 case ARM::VST1d16T: 1770 case ARM::VST1d32T: 1771 case ARM::VST1d64T: 1772 case ARM::VST1d8T_UPD: 1773 case ARM::VST1d16T_UPD: 1774 case ARM::VST1d32T_UPD: 1775 case ARM::VST1d64T_UPD: 1776 case ARM::VST1d8Q: 1777 case ARM::VST1d16Q: 1778 case ARM::VST1d32Q: 1779 case ARM::VST1d64Q: 1780 case ARM::VST1d8Q_UPD: 1781 case ARM::VST1d16Q_UPD: 1782 case ARM::VST1d32Q_UPD: 1783 case ARM::VST1d64Q_UPD: 1784 case ARM::VST2d8: 1785 case ARM::VST2d16: 1786 case ARM::VST2d32: 1787 case ARM::VST2d8_UPD: 1788 case ARM::VST2d16_UPD: 1789 case ARM::VST2d32_UPD: 1790 case ARM::VST2q8: 1791 case ARM::VST2q16: 1792 case ARM::VST2q32: 1793 case ARM::VST2q8_UPD: 1794 case ARM::VST2q16_UPD: 1795 case ARM::VST2q32_UPD: 1796 case ARM::VST3d8: 1797 case ARM::VST3d16: 1798 case ARM::VST3d32: 1799 case ARM::VST3d8_UPD: 1800 case ARM::VST3d16_UPD: 1801 case ARM::VST3d32_UPD: 1802 case ARM::VST4d8: 1803 case ARM::VST4d16: 1804 case ARM::VST4d32: 1805 case ARM::VST4d8_UPD: 1806 case ARM::VST4d16_UPD: 1807 case ARM::VST4d32_UPD: 1808 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1809 break; 1810 case ARM::VST2b8: 1811 case ARM::VST2b16: 1812 case ARM::VST2b32: 1813 case ARM::VST2b8_UPD: 1814 case ARM::VST2b16_UPD: 1815 case ARM::VST2b32_UPD: 1816 case ARM::VST3q8: 1817 case ARM::VST3q16: 1818 case ARM::VST3q32: 1819 case ARM::VST3q8_UPD: 1820 case ARM::VST3q16_UPD: 1821 case ARM::VST3q32_UPD: 1822 case ARM::VST4q8: 1823 case ARM::VST4q16: 1824 case ARM::VST4q32: 1825 case ARM::VST4q8_UPD: 1826 case ARM::VST4q16_UPD: 1827 case ARM::VST4q32_UPD: 1828 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1829 break; 1830 default: 1831 break; 1832 } 1833 1834 // Third input register 1835 switch (Inst.getOpcode()) { 1836 case ARM::VST1d8T: 1837 case ARM::VST1d16T: 1838 case ARM::VST1d32T: 1839 case ARM::VST1d64T: 1840 case ARM::VST1d8T_UPD: 1841 case ARM::VST1d16T_UPD: 1842 case ARM::VST1d32T_UPD: 1843 case ARM::VST1d64T_UPD: 1844 case ARM::VST1d8Q: 1845 case ARM::VST1d16Q: 1846 case ARM::VST1d32Q: 1847 case ARM::VST1d64Q: 1848 case ARM::VST1d8Q_UPD: 1849 case ARM::VST1d16Q_UPD: 1850 case ARM::VST1d32Q_UPD: 1851 case ARM::VST1d64Q_UPD: 1852 case ARM::VST2q8: 1853 case ARM::VST2q16: 1854 case ARM::VST2q32: 1855 case ARM::VST2q8_UPD: 1856 case ARM::VST2q16_UPD: 1857 case ARM::VST2q32_UPD: 1858 case ARM::VST3d8: 1859 case ARM::VST3d16: 1860 case ARM::VST3d32: 1861 case ARM::VST3d8_UPD: 1862 case ARM::VST3d16_UPD: 1863 case ARM::VST3d32_UPD: 1864 case ARM::VST4d8: 1865 case ARM::VST4d16: 1866 case ARM::VST4d32: 1867 case ARM::VST4d8_UPD: 1868 case ARM::VST4d16_UPD: 1869 case ARM::VST4d32_UPD: 1870 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1871 break; 1872 case ARM::VST3q8: 1873 case ARM::VST3q16: 1874 case ARM::VST3q32: 1875 case ARM::VST3q8_UPD: 1876 case ARM::VST3q16_UPD: 1877 case ARM::VST3q32_UPD: 1878 case ARM::VST4q8: 1879 case ARM::VST4q16: 1880 case ARM::VST4q32: 1881 case ARM::VST4q8_UPD: 1882 case ARM::VST4q16_UPD: 1883 case ARM::VST4q32_UPD: 1884 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1885 break; 1886 default: 1887 break; 1888 } 1889 1890 // Fourth input register 1891 switch (Inst.getOpcode()) { 1892 case ARM::VST1d8Q: 1893 case ARM::VST1d16Q: 1894 case ARM::VST1d32Q: 1895 case ARM::VST1d64Q: 1896 case ARM::VST1d8Q_UPD: 1897 case ARM::VST1d16Q_UPD: 1898 case ARM::VST1d32Q_UPD: 1899 case ARM::VST1d64Q_UPD: 1900 case ARM::VST2q8: 1901 case ARM::VST2q16: 1902 case ARM::VST2q32: 1903 case ARM::VST2q8_UPD: 1904 case ARM::VST2q16_UPD: 1905 case ARM::VST2q32_UPD: 1906 case ARM::VST4d8: 1907 case ARM::VST4d16: 1908 case ARM::VST4d32: 1909 case ARM::VST4d8_UPD: 1910 case ARM::VST4d16_UPD: 1911 case ARM::VST4d32_UPD: 1912 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1913 break; 1914 case ARM::VST4q8: 1915 case ARM::VST4q16: 1916 case ARM::VST4q32: 1917 case ARM::VST4q8_UPD: 1918 case ARM::VST4q16_UPD: 1919 case ARM::VST4q32_UPD: 1920 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1921 break; 1922 default: 1923 break; 1924 } 1925 1926 return S; 1927 } 1928 1929 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1930 uint64_t Address, const void *Decoder) { 1931 DecodeStatus S = Success; 1932 1933 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1934 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1935 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1936 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1937 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1938 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1939 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1940 1941 align *= (1 << size); 1942 1943 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1944 if (regs == 2) { 1945 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1946 } 1947 if (Rm == 0xD) { 1948 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1949 } 1950 1951 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1952 Inst.addOperand(MCOperand::CreateImm(align)); 1953 1954 if (Rm == 0xD) 1955 Inst.addOperand(MCOperand::CreateReg(0)); 1956 else if (Rm != 0xF) { 1957 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1958 } 1959 1960 return S; 1961 } 1962 1963 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1964 uint64_t Address, const void *Decoder) { 1965 DecodeStatus S = Success; 1966 1967 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1968 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1969 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1970 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1971 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1972 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1973 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1974 align *= 2*size; 1975 1976 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1977 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 1978 if (Rm == 0xD) { 1979 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1980 } 1981 1982 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1983 Inst.addOperand(MCOperand::CreateImm(align)); 1984 1985 if (Rm == 0xD) 1986 Inst.addOperand(MCOperand::CreateReg(0)); 1987 else if (Rm != 0xF) { 1988 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1989 } 1990 1991 return S; 1992 } 1993 1994 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1995 uint64_t Address, const void *Decoder) { 1996 DecodeStatus S = Success; 1997 1998 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1999 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2000 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2001 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2002 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2003 2004 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2005 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2006 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2007 if (Rm == 0xD) { 2008 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2009 } 2010 2011 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2012 Inst.addOperand(MCOperand::CreateImm(0)); 2013 2014 if (Rm == 0xD) 2015 Inst.addOperand(MCOperand::CreateReg(0)); 2016 else if (Rm != 0xF) { 2017 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2018 } 2019 2020 return S; 2021 } 2022 2023 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2024 uint64_t Address, const void *Decoder) { 2025 DecodeStatus S = Success; 2026 2027 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2028 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2029 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2030 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2031 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2032 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2033 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2034 2035 if (size == 0x3) { 2036 size = 4; 2037 align = 16; 2038 } else { 2039 if (size == 2) { 2040 size = 1 << size; 2041 align *= 8; 2042 } else { 2043 size = 1 << size; 2044 align *= 4*size; 2045 } 2046 } 2047 2048 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2049 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2050 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2051 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); 2052 if (Rm == 0xD) { 2053 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2054 } 2055 2056 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2057 Inst.addOperand(MCOperand::CreateImm(align)); 2058 2059 if (Rm == 0xD) 2060 Inst.addOperand(MCOperand::CreateReg(0)); 2061 else if (Rm != 0xF) { 2062 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2063 } 2064 2065 return S; 2066 } 2067 2068 static DecodeStatus 2069 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2070 uint64_t Address, const void *Decoder) { 2071 DecodeStatus S = Success; 2072 2073 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2074 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2075 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2076 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2077 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2078 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2079 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2080 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2081 2082 if (Q) { 2083 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2084 } else { 2085 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2086 } 2087 2088 Inst.addOperand(MCOperand::CreateImm(imm)); 2089 2090 switch (Inst.getOpcode()) { 2091 case ARM::VORRiv4i16: 2092 case ARM::VORRiv2i32: 2093 case ARM::VBICiv4i16: 2094 case ARM::VBICiv2i32: 2095 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2096 break; 2097 case ARM::VORRiv8i16: 2098 case ARM::VORRiv4i32: 2099 case ARM::VBICiv8i16: 2100 case ARM::VBICiv4i32: 2101 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2102 break; 2103 default: 2104 break; 2105 } 2106 2107 return S; 2108 } 2109 2110 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2111 uint64_t Address, const void *Decoder) { 2112 DecodeStatus S = Success; 2113 2114 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2115 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2116 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2117 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2118 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2119 2120 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2121 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2122 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2123 2124 return S; 2125 } 2126 2127 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2128 uint64_t Address, const void *Decoder) { 2129 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2130 return Success; 2131 } 2132 2133 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2134 uint64_t Address, const void *Decoder) { 2135 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2136 return Success; 2137 } 2138 2139 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2140 uint64_t Address, const void *Decoder) { 2141 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2142 return Success; 2143 } 2144 2145 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2146 uint64_t Address, const void *Decoder) { 2147 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2148 return Success; 2149 } 2150 2151 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2152 uint64_t Address, const void *Decoder) { 2153 DecodeStatus S = Success; 2154 2155 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2156 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2157 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2158 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2159 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2160 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2161 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2162 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2163 2164 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2165 if (op) { 2166 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback 2167 } 2168 2169 for (unsigned i = 0; i < length; ++i) { 2170 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)); 2171 } 2172 2173 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2174 2175 return S; 2176 } 2177 2178 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2179 uint64_t Address, const void *Decoder) { 2180 // The immediate needs to be a fully instantiated float. However, the 2181 // auto-generated decoder is only able to fill in some of the bits 2182 // necessary. For instance, the 'b' bit is replicated multiple times, 2183 // and is even present in inverted form in one bit. We do a little 2184 // binary parsing here to fill in those missing bits, and then 2185 // reinterpret it all as a float. 2186 union { 2187 uint32_t integer; 2188 float fp; 2189 } fp_conv; 2190 2191 fp_conv.integer = Val; 2192 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2193 fp_conv.integer |= b << 26; 2194 fp_conv.integer |= b << 27; 2195 fp_conv.integer |= b << 28; 2196 fp_conv.integer |= b << 29; 2197 fp_conv.integer |= (~b & 0x1) << 30; 2198 2199 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2200 return Success; 2201 } 2202 2203 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2204 uint64_t Address, const void *Decoder) { 2205 DecodeStatus S = Success; 2206 2207 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2208 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2209 2210 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); 2211 2212 if (Inst.getOpcode() == ARM::tADR) 2213 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2214 else if (Inst.getOpcode() == ARM::tADDrSPi) 2215 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2216 else 2217 return Fail; 2218 2219 Inst.addOperand(MCOperand::CreateImm(imm)); 2220 return S; 2221 } 2222 2223 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2224 uint64_t Address, const void *Decoder) { 2225 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2226 return Success; 2227 } 2228 2229 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2230 uint64_t Address, const void *Decoder) { 2231 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2232 return Success; 2233 } 2234 2235 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2236 uint64_t Address, const void *Decoder) { 2237 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2238 return Success; 2239 } 2240 2241 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2242 uint64_t Address, const void *Decoder) { 2243 DecodeStatus S = Success; 2244 2245 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2246 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2247 2248 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2249 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); 2250 2251 return S; 2252 } 2253 2254 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2255 uint64_t Address, const void *Decoder) { 2256 DecodeStatus S = Success; 2257 2258 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2259 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2260 2261 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2262 Inst.addOperand(MCOperand::CreateImm(imm)); 2263 2264 return S; 2265 } 2266 2267 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2268 uint64_t Address, const void *Decoder) { 2269 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2270 2271 return Success; 2272 } 2273 2274 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2275 uint64_t Address, const void *Decoder) { 2276 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2277 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2278 2279 return Success; 2280 } 2281 2282 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2283 uint64_t Address, const void *Decoder) { 2284 DecodeStatus S = Success; 2285 2286 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2287 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2288 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2289 2290 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2291 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); 2292 Inst.addOperand(MCOperand::CreateImm(imm)); 2293 2294 return S; 2295 } 2296 2297 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2298 uint64_t Address, const void *Decoder) { 2299 DecodeStatus S = Success; 2300 2301 if (Inst.getOpcode() != ARM::t2PLDs) { 2302 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2303 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2304 } 2305 2306 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2307 if (Rn == 0xF) { 2308 switch (Inst.getOpcode()) { 2309 case ARM::t2LDRBs: 2310 Inst.setOpcode(ARM::t2LDRBpci); 2311 break; 2312 case ARM::t2LDRHs: 2313 Inst.setOpcode(ARM::t2LDRHpci); 2314 break; 2315 case ARM::t2LDRSHs: 2316 Inst.setOpcode(ARM::t2LDRSHpci); 2317 break; 2318 case ARM::t2LDRSBs: 2319 Inst.setOpcode(ARM::t2LDRSBpci); 2320 break; 2321 case ARM::t2PLDs: 2322 Inst.setOpcode(ARM::t2PLDi12); 2323 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2324 break; 2325 default: 2326 return Fail; 2327 } 2328 2329 int imm = fieldFromInstruction32(Insn, 0, 12); 2330 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2331 Inst.addOperand(MCOperand::CreateImm(imm)); 2332 2333 return S; 2334 } 2335 2336 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2337 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2338 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2339 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); 2340 2341 return S; 2342 } 2343 2344 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2345 uint64_t Address, const void *Decoder) { 2346 int imm = Val & 0xFF; 2347 if (!(Val & 0x100)) imm *= -1; 2348 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2349 2350 return Success; 2351 } 2352 2353 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2354 uint64_t Address, const void *Decoder) { 2355 DecodeStatus S = Success; 2356 2357 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2358 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2359 2360 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2361 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); 2362 2363 return S; 2364 } 2365 2366 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2367 uint64_t Address, const void *Decoder) { 2368 int imm = Val & 0xFF; 2369 if (!(Val & 0x100)) imm *= -1; 2370 Inst.addOperand(MCOperand::CreateImm(imm)); 2371 2372 return Success; 2373 } 2374 2375 2376 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2377 uint64_t Address, const void *Decoder) { 2378 DecodeStatus S = Success; 2379 2380 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2381 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2382 2383 // Some instructions always use an additive offset. 2384 switch (Inst.getOpcode()) { 2385 case ARM::t2LDRT: 2386 case ARM::t2LDRBT: 2387 case ARM::t2LDRHT: 2388 case ARM::t2LDRSBT: 2389 case ARM::t2LDRSHT: 2390 imm |= 0x100; 2391 break; 2392 default: 2393 break; 2394 } 2395 2396 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2397 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); 2398 2399 return S; 2400 } 2401 2402 2403 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2404 uint64_t Address, const void *Decoder) { 2405 DecodeStatus S = Success; 2406 2407 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2408 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2409 2410 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2411 Inst.addOperand(MCOperand::CreateImm(imm)); 2412 2413 return S; 2414 } 2415 2416 2417 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2418 uint64_t Address, const void *Decoder) { 2419 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2420 2421 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2422 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2423 Inst.addOperand(MCOperand::CreateImm(imm)); 2424 2425 return Success; 2426 } 2427 2428 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2429 uint64_t Address, const void *Decoder) { 2430 DecodeStatus S = Success; 2431 2432 if (Inst.getOpcode() == ARM::tADDrSP) { 2433 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2434 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2435 2436 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2437 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2438 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2439 } else if (Inst.getOpcode() == ARM::tADDspr) { 2440 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2441 2442 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2443 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2444 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2445 } 2446 2447 return S; 2448 } 2449 2450 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2451 uint64_t Address, const void *Decoder) { 2452 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2453 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2454 2455 Inst.addOperand(MCOperand::CreateImm(imod)); 2456 Inst.addOperand(MCOperand::CreateImm(flags)); 2457 2458 return Success; 2459 } 2460 2461 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2462 uint64_t Address, const void *Decoder) { 2463 DecodeStatus S = Success; 2464 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2465 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2466 2467 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; 2468 Inst.addOperand(MCOperand::CreateImm(add)); 2469 2470 return S; 2471 } 2472 2473 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2474 uint64_t Address, const void *Decoder) { 2475 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2476 return Success; 2477 } 2478 2479 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2480 uint64_t Address, const void *Decoder) { 2481 if (Val == 0xA || Val == 0xB) 2482 return Fail; 2483 2484 Inst.addOperand(MCOperand::CreateImm(Val)); 2485 return Success; 2486 } 2487 2488 static DecodeStatus 2489 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2490 uint64_t Address, const void *Decoder) { 2491 DecodeStatus S = Success; 2492 2493 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2494 if (pred == 0xE || pred == 0xF) { 2495 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2496 switch (opc) { 2497 default: 2498 return Fail; 2499 case 0: 2500 Inst.setOpcode(ARM::t2DSB); 2501 break; 2502 case 1: 2503 Inst.setOpcode(ARM::t2DMB); 2504 break; 2505 case 2: 2506 Inst.setOpcode(ARM::t2ISB); 2507 return Success; 2508 } 2509 2510 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2511 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2512 } 2513 2514 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2515 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2516 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2517 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2518 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2519 2520 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); 2521 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2522 2523 return S; 2524 } 2525 2526 // Decode a shifted immediate operand. These basically consist 2527 // of an 8-bit value, and a 4-bit directive that specifies either 2528 // a splat operation or a rotation. 2529 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2530 uint64_t Address, const void *Decoder) { 2531 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2532 if (ctrl == 0) { 2533 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2534 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2535 switch (byte) { 2536 case 0: 2537 Inst.addOperand(MCOperand::CreateImm(imm)); 2538 break; 2539 case 1: 2540 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2541 break; 2542 case 2: 2543 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2544 break; 2545 case 3: 2546 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2547 (imm << 8) | imm)); 2548 break; 2549 } 2550 } else { 2551 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2552 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2553 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2554 Inst.addOperand(MCOperand::CreateImm(imm)); 2555 } 2556 2557 return Success; 2558 } 2559 2560 static DecodeStatus 2561 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2562 uint64_t Address, const void *Decoder){ 2563 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2564 return Success; 2565 } 2566 2567 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2568 uint64_t Address, const void *Decoder){ 2569 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2570 return Success; 2571 } 2572 2573 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2574 uint64_t Address, const void *Decoder) { 2575 switch (Val) { 2576 default: 2577 return Fail; 2578 case 0xF: // SY 2579 case 0xE: // ST 2580 case 0xB: // ISH 2581 case 0xA: // ISHST 2582 case 0x7: // NSH 2583 case 0x6: // NSHST 2584 case 0x3: // OSH 2585 case 0x2: // OSHST 2586 break; 2587 } 2588 2589 Inst.addOperand(MCOperand::CreateImm(Val)); 2590 return Success; 2591 } 2592 2593 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2594 uint64_t Address, const void *Decoder) { 2595 if (!Val) return Fail; 2596 Inst.addOperand(MCOperand::CreateImm(Val)); 2597 return Success; 2598 } 2599 2600 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2601 uint64_t Address, const void *Decoder) { 2602 DecodeStatus S = Success; 2603 2604 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2605 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2606 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2607 2608 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2609 2610 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2611 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2612 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2613 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2614 2615 return S; 2616 } 2617 2618 2619 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2620 uint64_t Address, const void *Decoder){ 2621 DecodeStatus S = Success; 2622 2623 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2624 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2625 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2626 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2627 2628 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); 2629 2630 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2631 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; 2632 2633 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2634 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2635 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2636 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2637 2638 return S; 2639 } 2640 2641 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2642 uint64_t Address, const void *Decoder) { 2643 DecodeStatus S = Success; 2644 2645 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2646 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2647 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2648 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2649 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2650 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2651 2652 if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE 2653 2654 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2655 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2656 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); 2657 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2658 2659 return S; 2660 } 2661 2662 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2663 uint64_t Address, const void *Decoder) { 2664 DecodeStatus S = Success; 2665 2666 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2667 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2668 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2669 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2670 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2671 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2672 2673 if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE 2674 2675 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2676 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2677 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); 2678 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2679 2680 return S; 2681 } 2682 2683 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2684 uint64_t Address, const void *Decoder) { 2685 DecodeStatus S = Success; 2686 2687 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2688 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2689 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2690 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2691 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2692 2693 unsigned align = 0; 2694 unsigned index = 0; 2695 switch (size) { 2696 default: 2697 return Fail; 2698 case 0: 2699 if (fieldFromInstruction32(Insn, 4, 1)) 2700 return Fail; // UNDEFINED 2701 index = fieldFromInstruction32(Insn, 5, 3); 2702 break; 2703 case 1: 2704 if (fieldFromInstruction32(Insn, 5, 1)) 2705 return Fail; // UNDEFINED 2706 index = fieldFromInstruction32(Insn, 6, 2); 2707 if (fieldFromInstruction32(Insn, 4, 1)) 2708 align = 2; 2709 break; 2710 case 2: 2711 if (fieldFromInstruction32(Insn, 6, 1)) 2712 return Fail; // UNDEFINED 2713 index = fieldFromInstruction32(Insn, 7, 1); 2714 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2715 align = 4; 2716 } 2717 2718 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2719 if (Rm != 0xF) { // Writeback 2720 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2721 } 2722 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2723 Inst.addOperand(MCOperand::CreateImm(align)); 2724 if (Rm != 0xF && Rm != 0xD) { 2725 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2726 } 2727 2728 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2729 Inst.addOperand(MCOperand::CreateImm(index)); 2730 2731 return S; 2732 } 2733 2734 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2735 uint64_t Address, const void *Decoder) { 2736 DecodeStatus S = Success; 2737 2738 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2739 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2740 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2741 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2742 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2743 2744 unsigned align = 0; 2745 unsigned index = 0; 2746 switch (size) { 2747 default: 2748 return Fail; 2749 case 0: 2750 if (fieldFromInstruction32(Insn, 4, 1)) 2751 return Fail; // UNDEFINED 2752 index = fieldFromInstruction32(Insn, 5, 3); 2753 break; 2754 case 1: 2755 if (fieldFromInstruction32(Insn, 5, 1)) 2756 return Fail; // UNDEFINED 2757 index = fieldFromInstruction32(Insn, 6, 2); 2758 if (fieldFromInstruction32(Insn, 4, 1)) 2759 align = 2; 2760 break; 2761 case 2: 2762 if (fieldFromInstruction32(Insn, 6, 1)) 2763 return Fail; // UNDEFINED 2764 index = fieldFromInstruction32(Insn, 7, 1); 2765 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2766 align = 4; 2767 } 2768 2769 if (Rm != 0xF) { // Writeback 2770 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2771 } 2772 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2773 Inst.addOperand(MCOperand::CreateImm(align)); 2774 if (Rm != 0xF && Rm != 0xD) { 2775 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2776 } 2777 2778 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2779 Inst.addOperand(MCOperand::CreateImm(index)); 2780 2781 return S; 2782 } 2783 2784 2785 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2786 uint64_t Address, const void *Decoder) { 2787 DecodeStatus S = Success; 2788 2789 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2790 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2791 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2792 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2793 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2794 2795 unsigned align = 0; 2796 unsigned index = 0; 2797 unsigned inc = 1; 2798 switch (size) { 2799 default: 2800 return Fail; 2801 case 0: 2802 index = fieldFromInstruction32(Insn, 5, 3); 2803 if (fieldFromInstruction32(Insn, 4, 1)) 2804 align = 2; 2805 break; 2806 case 1: 2807 index = fieldFromInstruction32(Insn, 6, 2); 2808 if (fieldFromInstruction32(Insn, 4, 1)) 2809 align = 4; 2810 if (fieldFromInstruction32(Insn, 5, 1)) 2811 inc = 2; 2812 break; 2813 case 2: 2814 if (fieldFromInstruction32(Insn, 5, 1)) 2815 return Fail; // UNDEFINED 2816 index = fieldFromInstruction32(Insn, 7, 1); 2817 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2818 align = 8; 2819 if (fieldFromInstruction32(Insn, 6, 1)) 2820 inc = 2; 2821 break; 2822 } 2823 2824 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2825 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2826 if (Rm != 0xF) { // Writeback 2827 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2828 } 2829 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2830 Inst.addOperand(MCOperand::CreateImm(align)); 2831 if (Rm != 0xF && Rm != 0xD) { 2832 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2833 } 2834 2835 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2836 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2837 Inst.addOperand(MCOperand::CreateImm(index)); 2838 2839 return S; 2840 } 2841 2842 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2843 uint64_t Address, const void *Decoder) { 2844 DecodeStatus S = Success; 2845 2846 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2847 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2848 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2849 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2850 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2851 2852 unsigned align = 0; 2853 unsigned index = 0; 2854 unsigned inc = 1; 2855 switch (size) { 2856 default: 2857 return Fail; 2858 case 0: 2859 index = fieldFromInstruction32(Insn, 5, 3); 2860 if (fieldFromInstruction32(Insn, 4, 1)) 2861 align = 2; 2862 break; 2863 case 1: 2864 index = fieldFromInstruction32(Insn, 6, 2); 2865 if (fieldFromInstruction32(Insn, 4, 1)) 2866 align = 4; 2867 if (fieldFromInstruction32(Insn, 5, 1)) 2868 inc = 2; 2869 break; 2870 case 2: 2871 if (fieldFromInstruction32(Insn, 5, 1)) 2872 return Fail; // UNDEFINED 2873 index = fieldFromInstruction32(Insn, 7, 1); 2874 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2875 align = 8; 2876 if (fieldFromInstruction32(Insn, 6, 1)) 2877 inc = 2; 2878 break; 2879 } 2880 2881 if (Rm != 0xF) { // Writeback 2882 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2883 } 2884 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2885 Inst.addOperand(MCOperand::CreateImm(align)); 2886 if (Rm != 0xF && Rm != 0xD) { 2887 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2888 } 2889 2890 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2891 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2892 Inst.addOperand(MCOperand::CreateImm(index)); 2893 2894 return S; 2895 } 2896 2897 2898 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 2899 uint64_t Address, const void *Decoder) { 2900 DecodeStatus S = Success; 2901 2902 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2903 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2904 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2905 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2906 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2907 2908 unsigned align = 0; 2909 unsigned index = 0; 2910 unsigned inc = 1; 2911 switch (size) { 2912 default: 2913 return Fail; 2914 case 0: 2915 if (fieldFromInstruction32(Insn, 4, 1)) 2916 return Fail; // UNDEFINED 2917 index = fieldFromInstruction32(Insn, 5, 3); 2918 break; 2919 case 1: 2920 if (fieldFromInstruction32(Insn, 4, 1)) 2921 return Fail; // UNDEFINED 2922 index = fieldFromInstruction32(Insn, 6, 2); 2923 if (fieldFromInstruction32(Insn, 5, 1)) 2924 inc = 2; 2925 break; 2926 case 2: 2927 if (fieldFromInstruction32(Insn, 4, 2)) 2928 return Fail; // UNDEFINED 2929 index = fieldFromInstruction32(Insn, 7, 1); 2930 if (fieldFromInstruction32(Insn, 6, 1)) 2931 inc = 2; 2932 break; 2933 } 2934 2935 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2936 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2937 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2938 2939 if (Rm != 0xF) { // Writeback 2940 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2941 } 2942 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2943 Inst.addOperand(MCOperand::CreateImm(align)); 2944 if (Rm != 0xF && Rm != 0xD) { 2945 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2946 } 2947 2948 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2949 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2950 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2951 Inst.addOperand(MCOperand::CreateImm(index)); 2952 2953 return S; 2954 } 2955 2956 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 2957 uint64_t Address, const void *Decoder) { 2958 DecodeStatus S = Success; 2959 2960 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2961 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2962 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2963 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2964 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2965 2966 unsigned align = 0; 2967 unsigned index = 0; 2968 unsigned inc = 1; 2969 switch (size) { 2970 default: 2971 return Fail; 2972 case 0: 2973 if (fieldFromInstruction32(Insn, 4, 1)) 2974 return Fail; // UNDEFINED 2975 index = fieldFromInstruction32(Insn, 5, 3); 2976 break; 2977 case 1: 2978 if (fieldFromInstruction32(Insn, 4, 1)) 2979 return Fail; // UNDEFINED 2980 index = fieldFromInstruction32(Insn, 6, 2); 2981 if (fieldFromInstruction32(Insn, 5, 1)) 2982 inc = 2; 2983 break; 2984 case 2: 2985 if (fieldFromInstruction32(Insn, 4, 2)) 2986 return Fail; // UNDEFINED 2987 index = fieldFromInstruction32(Insn, 7, 1); 2988 if (fieldFromInstruction32(Insn, 6, 1)) 2989 inc = 2; 2990 break; 2991 } 2992 2993 if (Rm != 0xF) { // Writeback 2994 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2995 } 2996 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2997 Inst.addOperand(MCOperand::CreateImm(align)); 2998 if (Rm != 0xF && Rm != 0xD) { 2999 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3000 } 3001 3002 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3003 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3004 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3005 Inst.addOperand(MCOperand::CreateImm(index)); 3006 3007 return S; 3008 } 3009 3010 3011 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3012 uint64_t Address, const void *Decoder) { 3013 DecodeStatus S = Success; 3014 3015 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3016 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3017 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3018 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3019 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3020 3021 unsigned align = 0; 3022 unsigned index = 0; 3023 unsigned inc = 1; 3024 switch (size) { 3025 default: 3026 return Fail; 3027 case 0: 3028 if (fieldFromInstruction32(Insn, 4, 1)) 3029 align = 4; 3030 index = fieldFromInstruction32(Insn, 5, 3); 3031 break; 3032 case 1: 3033 if (fieldFromInstruction32(Insn, 4, 1)) 3034 align = 8; 3035 index = fieldFromInstruction32(Insn, 6, 2); 3036 if (fieldFromInstruction32(Insn, 5, 1)) 3037 inc = 2; 3038 break; 3039 case 2: 3040 if (fieldFromInstruction32(Insn, 4, 2)) 3041 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3042 index = fieldFromInstruction32(Insn, 7, 1); 3043 if (fieldFromInstruction32(Insn, 6, 1)) 3044 inc = 2; 3045 break; 3046 } 3047 3048 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3049 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3050 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3051 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3052 3053 if (Rm != 0xF) { // Writeback 3054 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3055 } 3056 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3057 Inst.addOperand(MCOperand::CreateImm(align)); 3058 if (Rm != 0xF && Rm != 0xD) { 3059 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3060 } 3061 3062 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3063 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3064 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3065 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3066 Inst.addOperand(MCOperand::CreateImm(index)); 3067 3068 return S; 3069 } 3070 3071 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3072 uint64_t Address, const void *Decoder) { 3073 DecodeStatus S = Success; 3074 3075 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3076 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3077 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3078 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3079 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3080 3081 unsigned align = 0; 3082 unsigned index = 0; 3083 unsigned inc = 1; 3084 switch (size) { 3085 default: 3086 return Fail; 3087 case 0: 3088 if (fieldFromInstruction32(Insn, 4, 1)) 3089 align = 4; 3090 index = fieldFromInstruction32(Insn, 5, 3); 3091 break; 3092 case 1: 3093 if (fieldFromInstruction32(Insn, 4, 1)) 3094 align = 8; 3095 index = fieldFromInstruction32(Insn, 6, 2); 3096 if (fieldFromInstruction32(Insn, 5, 1)) 3097 inc = 2; 3098 break; 3099 case 2: 3100 if (fieldFromInstruction32(Insn, 4, 2)) 3101 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3102 index = fieldFromInstruction32(Insn, 7, 1); 3103 if (fieldFromInstruction32(Insn, 6, 1)) 3104 inc = 2; 3105 break; 3106 } 3107 3108 if (Rm != 0xF) { // Writeback 3109 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3110 } 3111 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3112 Inst.addOperand(MCOperand::CreateImm(align)); 3113 if (Rm != 0xF && Rm != 0xD) { 3114 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3115 } 3116 3117 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3118 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3119 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3120 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3121 Inst.addOperand(MCOperand::CreateImm(index)); 3122 3123 return S; 3124 } 3125 3126