1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCDisassembler.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCFixedLenDisassembler.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/LEB128.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <vector> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "arm-disassembler" 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 // Handles the condition code status of instructions in IT blocks 35 class ITStatus 36 { 37 public: 38 // Returns the condition code for instruction in IT block 39 unsigned getITCC() { 40 unsigned CC = ARMCC::AL; 41 if (instrInITBlock()) 42 CC = ITStates.back(); 43 return CC; 44 } 45 46 // Advances the IT block state to the next T or E 47 void advanceITState() { 48 ITStates.pop_back(); 49 } 50 51 // Returns true if the current instruction is in an IT block 52 bool instrInITBlock() { 53 return !ITStates.empty(); 54 } 55 56 // Returns true if current instruction is the last instruction in an IT block 57 bool instrLastInITBlock() { 58 return ITStates.size() == 1; 59 } 60 61 // Called when decoding an IT instruction. Sets the IT state for the following 62 // instructions that for the IT block. Firstcond and Mask correspond to the 63 // fields in the IT instruction encoding. 64 void setITState(char Firstcond, char Mask) { 65 // (3 - the number of trailing zeros) is the number of then / else. 66 unsigned CondBit0 = Firstcond & 1; 67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 69 assert(NumTZ <= 3 && "Invalid IT mask!"); 70 // push condition codes onto the stack the correct order for the pops 71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 72 bool T = ((Mask >> Pos) & 1) == CondBit0; 73 if (T) 74 ITStates.push_back(CCBits); 75 else 76 ITStates.push_back(CCBits ^ 1); 77 } 78 ITStates.push_back(CCBits); 79 } 80 81 private: 82 std::vector<unsigned char> ITStates; 83 }; 84 } 85 86 namespace { 87 /// ARM disassembler for all ARM platforms. 88 class ARMDisassembler : public MCDisassembler { 89 public: 90 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 91 MCDisassembler(STI, Ctx) { 92 } 93 94 ~ARMDisassembler() override {} 95 96 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 97 ArrayRef<uint8_t> Bytes, uint64_t Address, 98 raw_ostream &VStream, 99 raw_ostream &CStream) const override; 100 }; 101 102 /// Thumb disassembler for all Thumb platforms. 103 class ThumbDisassembler : public MCDisassembler { 104 public: 105 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 106 MCDisassembler(STI, Ctx) { 107 } 108 109 ~ThumbDisassembler() override {} 110 111 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 112 ArrayRef<uint8_t> Bytes, uint64_t Address, 113 raw_ostream &VStream, 114 raw_ostream &CStream) const override; 115 116 private: 117 mutable ITStatus ITBlock; 118 DecodeStatus AddThumbPredicate(MCInst&) const; 119 void UpdateThumbVFPPredicate(MCInst&) const; 120 }; 121 } 122 123 static bool Check(DecodeStatus &Out, DecodeStatus In) { 124 switch (In) { 125 case MCDisassembler::Success: 126 // Out stays the same. 127 return true; 128 case MCDisassembler::SoftFail: 129 Out = In; 130 return true; 131 case MCDisassembler::Fail: 132 Out = In; 133 return false; 134 } 135 llvm_unreachable("Invalid DecodeStatus!"); 136 } 137 138 139 // Forward declare these because the autogenerated code will reference them. 140 // Definitions are further down. 141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, const void *Decoder); 143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 144 unsigned RegNo, uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 147 unsigned RegNo, uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 150 uint64_t Address, const void *Decoder); 151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 164 unsigned RegNo, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 172 unsigned RegNo, uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 191 unsigned Insn, 192 uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 201 uint64_t Address, const void *Decoder); 202 203 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 204 unsigned Insn, 205 uint64_t Adddress, 206 const void *Decoder); 207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 318 319 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 340 uint64_t Address, const void* Decoder); 341 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 342 uint64_t Address, const void* Decoder); 343 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void* Decoder); 345 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void* Decoder); 347 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 390 uint64_t Address, const void *Decoder); 391 392 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 #include "ARMGenDisassemblerTables.inc" 397 398 static MCDisassembler *createARMDisassembler(const Target &T, 399 const MCSubtargetInfo &STI, 400 MCContext &Ctx) { 401 return new ARMDisassembler(STI, Ctx); 402 } 403 404 static MCDisassembler *createThumbDisassembler(const Target &T, 405 const MCSubtargetInfo &STI, 406 MCContext &Ctx) { 407 return new ThumbDisassembler(STI, Ctx); 408 } 409 410 // Post-decoding checks 411 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 412 uint64_t Address, raw_ostream &OS, 413 raw_ostream &CS, 414 uint32_t Insn, 415 DecodeStatus Result) 416 { 417 switch (MI.getOpcode()) { 418 case ARM::HVC: { 419 // HVC is undefined if condition = 0xf otherwise upredictable 420 // if condition != 0xe 421 uint32_t Cond = (Insn >> 28) & 0xF; 422 if (Cond == 0xF) 423 return MCDisassembler::Fail; 424 if (Cond != 0xE) 425 return MCDisassembler::SoftFail; 426 return Result; 427 } 428 default: return Result; 429 } 430 } 431 432 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 433 ArrayRef<uint8_t> Bytes, 434 uint64_t Address, raw_ostream &OS, 435 raw_ostream &CS) const { 436 CommentStream = &CS; 437 438 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 439 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 440 "mode!"); 441 442 // We want to read exactly 4 bytes of data. 443 if (Bytes.size() < 4) { 444 Size = 0; 445 return MCDisassembler::Fail; 446 } 447 448 // Encoded as a small-endian 32-bit word in the stream. 449 uint32_t Insn = 450 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 451 452 // Calling the auto-generated decoder function. 453 DecodeStatus Result = 454 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 455 if (Result != MCDisassembler::Fail) { 456 Size = 4; 457 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 458 } 459 460 // VFP and NEON instructions, similarly, are shared between ARM 461 // and Thumb modes. 462 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI); 463 if (Result != MCDisassembler::Fail) { 464 Size = 4; 465 return Result; 466 } 467 468 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI); 469 if (Result != MCDisassembler::Fail) { 470 Size = 4; 471 return Result; 472 } 473 474 Result = 475 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI); 476 if (Result != MCDisassembler::Fail) { 477 Size = 4; 478 // Add a fake predicate operand, because we share these instruction 479 // definitions with Thumb2 where these instructions are predicable. 480 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 481 return MCDisassembler::Fail; 482 return Result; 483 } 484 485 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address, 486 this, STI); 487 if (Result != MCDisassembler::Fail) { 488 Size = 4; 489 // Add a fake predicate operand, because we share these instruction 490 // definitions with Thumb2 where these instructions are predicable. 491 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 492 return MCDisassembler::Fail; 493 return Result; 494 } 495 496 Result = 497 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI); 498 if (Result != MCDisassembler::Fail) { 499 Size = 4; 500 // Add a fake predicate operand, because we share these instruction 501 // definitions with Thumb2 where these instructions are predicable. 502 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 503 return MCDisassembler::Fail; 504 return Result; 505 } 506 507 Result = 508 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI); 509 if (Result != MCDisassembler::Fail) { 510 Size = 4; 511 return Result; 512 } 513 514 Result = 515 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI); 516 if (Result != MCDisassembler::Fail) { 517 Size = 4; 518 return Result; 519 } 520 521 Size = 0; 522 return MCDisassembler::Fail; 523 } 524 525 namespace llvm { 526 extern const MCInstrDesc ARMInsts[]; 527 } 528 529 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 530 /// immediate Value in the MCInst. The immediate Value has had any PC 531 /// adjustment made by the caller. If the instruction is a branch instruction 532 /// then isBranch is true, else false. If the getOpInfo() function was set as 533 /// part of the setupForSymbolicDisassembly() call then that function is called 534 /// to get any symbolic information at the Address for this instruction. If 535 /// that returns non-zero then the symbolic information it returns is used to 536 /// create an MCExpr and that is added as an operand to the MCInst. If 537 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 538 /// Value is done and if a symbol is found an MCExpr is created with that, else 539 /// an MCExpr with Value is created. This function returns true if it adds an 540 /// operand to the MCInst and false otherwise. 541 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 542 bool isBranch, uint64_t InstSize, 543 MCInst &MI, const void *Decoder) { 544 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 545 // FIXME: Does it make sense for value to be negative? 546 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 547 /* Offset */ 0, InstSize); 548 } 549 550 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 551 /// referenced by a load instruction with the base register that is the Pc. 552 /// These can often be values in a literal pool near the Address of the 553 /// instruction. The Address of the instruction and its immediate Value are 554 /// used as a possible literal pool entry. The SymbolLookUp call back will 555 /// return the name of a symbol referenced by the literal pool's entry if 556 /// the referenced address is that of a symbol. Or it will return a pointer to 557 /// a literal 'C' string if the referenced address of the literal pool's entry 558 /// is an address into a section with 'C' string literals. 559 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 560 const void *Decoder) { 561 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 562 Dis->tryAddingPcLoadReferenceComment(Value, Address); 563 } 564 565 // Thumb1 instructions don't have explicit S bits. Rather, they 566 // implicitly set CPSR. Since it's not represented in the encoding, the 567 // auto-generated decoder won't inject the CPSR operand. We need to fix 568 // that as a post-pass. 569 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 570 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 571 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 572 MCInst::iterator I = MI.begin(); 573 for (unsigned i = 0; i < NumOps; ++i, ++I) { 574 if (I == MI.end()) break; 575 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 576 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 577 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 578 return; 579 } 580 } 581 582 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 583 } 584 585 // Most Thumb instructions don't have explicit predicates in the 586 // encoding, but rather get their predicates from IT context. We need 587 // to fix up the predicate operands using this context information as a 588 // post-pass. 589 MCDisassembler::DecodeStatus 590 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 591 MCDisassembler::DecodeStatus S = Success; 592 593 // A few instructions actually have predicates encoded in them. Don't 594 // try to overwrite it if we're seeing one of those. 595 switch (MI.getOpcode()) { 596 case ARM::tBcc: 597 case ARM::t2Bcc: 598 case ARM::tCBZ: 599 case ARM::tCBNZ: 600 case ARM::tCPS: 601 case ARM::t2CPS3p: 602 case ARM::t2CPS2p: 603 case ARM::t2CPS1p: 604 case ARM::tMOVSr: 605 case ARM::tSETEND: 606 // Some instructions (mostly conditional branches) are not 607 // allowed in IT blocks. 608 if (ITBlock.instrInITBlock()) 609 S = SoftFail; 610 else 611 return Success; 612 break; 613 case ARM::tB: 614 case ARM::t2B: 615 case ARM::t2TBB: 616 case ARM::t2TBH: 617 // Some instructions (mostly unconditional branches) can 618 // only appears at the end of, or outside of, an IT. 619 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 620 S = SoftFail; 621 break; 622 default: 623 break; 624 } 625 626 // If we're in an IT block, base the predicate on that. Otherwise, 627 // assume a predicate of AL. 628 unsigned CC; 629 CC = ITBlock.getITCC(); 630 if (CC == 0xF) 631 CC = ARMCC::AL; 632 if (ITBlock.instrInITBlock()) 633 ITBlock.advanceITState(); 634 635 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 636 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 637 MCInst::iterator I = MI.begin(); 638 for (unsigned i = 0; i < NumOps; ++i, ++I) { 639 if (I == MI.end()) break; 640 if (OpInfo[i].isPredicate()) { 641 I = MI.insert(I, MCOperand::createImm(CC)); 642 ++I; 643 if (CC == ARMCC::AL) 644 MI.insert(I, MCOperand::createReg(0)); 645 else 646 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 647 return S; 648 } 649 } 650 651 I = MI.insert(I, MCOperand::createImm(CC)); 652 ++I; 653 if (CC == ARMCC::AL) 654 MI.insert(I, MCOperand::createReg(0)); 655 else 656 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 657 658 return S; 659 } 660 661 // Thumb VFP instructions are a special case. Because we share their 662 // encodings between ARM and Thumb modes, and they are predicable in ARM 663 // mode, the auto-generated decoder will give them an (incorrect) 664 // predicate operand. We need to rewrite these operands based on the IT 665 // context as a post-pass. 666 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 667 unsigned CC; 668 CC = ITBlock.getITCC(); 669 if (ITBlock.instrInITBlock()) 670 ITBlock.advanceITState(); 671 672 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 673 MCInst::iterator I = MI.begin(); 674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 675 for (unsigned i = 0; i < NumOps; ++i, ++I) { 676 if (OpInfo[i].isPredicate() ) { 677 I->setImm(CC); 678 ++I; 679 if (CC == ARMCC::AL) 680 I->setReg(0); 681 else 682 I->setReg(ARM::CPSR); 683 return; 684 } 685 } 686 } 687 688 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 689 ArrayRef<uint8_t> Bytes, 690 uint64_t Address, 691 raw_ostream &OS, 692 raw_ostream &CS) const { 693 CommentStream = &CS; 694 695 assert(STI.getFeatureBits()[ARM::ModeThumb] && 696 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 697 698 // We want to read exactly 2 bytes of data. 699 if (Bytes.size() < 2) { 700 Size = 0; 701 return MCDisassembler::Fail; 702 } 703 704 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 705 DecodeStatus Result = 706 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 707 if (Result != MCDisassembler::Fail) { 708 Size = 2; 709 Check(Result, AddThumbPredicate(MI)); 710 return Result; 711 } 712 713 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 714 STI); 715 if (Result) { 716 Size = 2; 717 bool InITBlock = ITBlock.instrInITBlock(); 718 Check(Result, AddThumbPredicate(MI)); 719 AddThumb1SBit(MI, InITBlock); 720 return Result; 721 } 722 723 Result = 724 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 725 if (Result != MCDisassembler::Fail) { 726 Size = 2; 727 728 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 729 // the Thumb predicate. 730 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 731 Result = MCDisassembler::SoftFail; 732 733 Check(Result, AddThumbPredicate(MI)); 734 735 // If we find an IT instruction, we need to parse its condition 736 // code and mask operands so that we can apply them correctly 737 // to the subsequent instructions. 738 if (MI.getOpcode() == ARM::t2IT) { 739 740 unsigned Firstcond = MI.getOperand(0).getImm(); 741 unsigned Mask = MI.getOperand(1).getImm(); 742 ITBlock.setITState(Firstcond, Mask); 743 } 744 745 return Result; 746 } 747 748 // We want to read exactly 4 bytes of data. 749 if (Bytes.size() < 4) { 750 Size = 0; 751 return MCDisassembler::Fail; 752 } 753 754 uint32_t Insn32 = 755 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 756 Result = 757 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 758 if (Result != MCDisassembler::Fail) { 759 Size = 4; 760 bool InITBlock = ITBlock.instrInITBlock(); 761 Check(Result, AddThumbPredicate(MI)); 762 AddThumb1SBit(MI, InITBlock); 763 return Result; 764 } 765 766 Result = 767 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 768 if (Result != MCDisassembler::Fail) { 769 Size = 4; 770 Check(Result, AddThumbPredicate(MI)); 771 return Result; 772 } 773 774 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 775 Result = 776 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 777 if (Result != MCDisassembler::Fail) { 778 Size = 4; 779 UpdateThumbVFPPredicate(MI); 780 return Result; 781 } 782 } 783 784 Result = 785 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 786 if (Result != MCDisassembler::Fail) { 787 Size = 4; 788 return Result; 789 } 790 791 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 792 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 793 STI); 794 if (Result != MCDisassembler::Fail) { 795 Size = 4; 796 Check(Result, AddThumbPredicate(MI)); 797 return Result; 798 } 799 } 800 801 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 802 uint32_t NEONLdStInsn = Insn32; 803 NEONLdStInsn &= 0xF0FFFFFF; 804 NEONLdStInsn |= 0x04000000; 805 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 806 Address, this, STI); 807 if (Result != MCDisassembler::Fail) { 808 Size = 4; 809 Check(Result, AddThumbPredicate(MI)); 810 return Result; 811 } 812 } 813 814 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 815 uint32_t NEONDataInsn = Insn32; 816 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 817 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 818 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 819 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 820 Address, this, STI); 821 if (Result != MCDisassembler::Fail) { 822 Size = 4; 823 Check(Result, AddThumbPredicate(MI)); 824 return Result; 825 } 826 827 uint32_t NEONCryptoInsn = Insn32; 828 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 829 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 830 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 831 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 832 Address, this, STI); 833 if (Result != MCDisassembler::Fail) { 834 Size = 4; 835 return Result; 836 } 837 838 uint32_t NEONv8Insn = Insn32; 839 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 840 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 841 this, STI); 842 if (Result != MCDisassembler::Fail) { 843 Size = 4; 844 return Result; 845 } 846 } 847 848 Size = 0; 849 return MCDisassembler::Fail; 850 } 851 852 853 extern "C" void LLVMInitializeARMDisassembler() { 854 TargetRegistry::RegisterMCDisassembler(TheARMLETarget, 855 createARMDisassembler); 856 TargetRegistry::RegisterMCDisassembler(TheARMBETarget, 857 createARMDisassembler); 858 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget, 859 createThumbDisassembler); 860 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget, 861 createThumbDisassembler); 862 } 863 864 static const uint16_t GPRDecoderTable[] = { 865 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 866 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 867 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 868 ARM::R12, ARM::SP, ARM::LR, ARM::PC 869 }; 870 871 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 872 uint64_t Address, const void *Decoder) { 873 if (RegNo > 15) 874 return MCDisassembler::Fail; 875 876 unsigned Register = GPRDecoderTable[RegNo]; 877 Inst.addOperand(MCOperand::createReg(Register)); 878 return MCDisassembler::Success; 879 } 880 881 static DecodeStatus 882 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 883 uint64_t Address, const void *Decoder) { 884 DecodeStatus S = MCDisassembler::Success; 885 886 if (RegNo == 15) 887 S = MCDisassembler::SoftFail; 888 889 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 890 891 return S; 892 } 893 894 static DecodeStatus 895 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 896 uint64_t Address, const void *Decoder) { 897 DecodeStatus S = MCDisassembler::Success; 898 899 if (RegNo == 15) 900 { 901 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 902 return MCDisassembler::Success; 903 } 904 905 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 906 return S; 907 } 908 909 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 910 uint64_t Address, const void *Decoder) { 911 if (RegNo > 7) 912 return MCDisassembler::Fail; 913 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 914 } 915 916 static const uint16_t GPRPairDecoderTable[] = { 917 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 918 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 919 }; 920 921 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 922 uint64_t Address, const void *Decoder) { 923 DecodeStatus S = MCDisassembler::Success; 924 925 if (RegNo > 13) 926 return MCDisassembler::Fail; 927 928 if ((RegNo & 1) || RegNo == 0xe) 929 S = MCDisassembler::SoftFail; 930 931 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 932 Inst.addOperand(MCOperand::createReg(RegisterPair)); 933 return S; 934 } 935 936 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 937 uint64_t Address, const void *Decoder) { 938 unsigned Register = 0; 939 switch (RegNo) { 940 case 0: 941 Register = ARM::R0; 942 break; 943 case 1: 944 Register = ARM::R1; 945 break; 946 case 2: 947 Register = ARM::R2; 948 break; 949 case 3: 950 Register = ARM::R3; 951 break; 952 case 9: 953 Register = ARM::R9; 954 break; 955 case 12: 956 Register = ARM::R12; 957 break; 958 default: 959 return MCDisassembler::Fail; 960 } 961 962 Inst.addOperand(MCOperand::createReg(Register)); 963 return MCDisassembler::Success; 964 } 965 966 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 967 uint64_t Address, const void *Decoder) { 968 DecodeStatus S = MCDisassembler::Success; 969 if (RegNo == 13 || RegNo == 15) 970 S = MCDisassembler::SoftFail; 971 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 972 return S; 973 } 974 975 static const uint16_t SPRDecoderTable[] = { 976 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 977 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 978 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 979 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 980 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 981 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 982 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 983 ARM::S28, ARM::S29, ARM::S30, ARM::S31 984 }; 985 986 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 987 uint64_t Address, const void *Decoder) { 988 if (RegNo > 31) 989 return MCDisassembler::Fail; 990 991 unsigned Register = SPRDecoderTable[RegNo]; 992 Inst.addOperand(MCOperand::createReg(Register)); 993 return MCDisassembler::Success; 994 } 995 996 static const uint16_t DPRDecoderTable[] = { 997 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 998 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 999 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1000 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1001 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1002 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1003 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1004 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1005 }; 1006 1007 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1008 uint64_t Address, const void *Decoder) { 1009 const FeatureBitset &featureBits = 1010 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1011 1012 bool hasD16 = featureBits[ARM::FeatureD16]; 1013 1014 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1015 return MCDisassembler::Fail; 1016 1017 unsigned Register = DPRDecoderTable[RegNo]; 1018 Inst.addOperand(MCOperand::createReg(Register)); 1019 return MCDisassembler::Success; 1020 } 1021 1022 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1023 uint64_t Address, const void *Decoder) { 1024 if (RegNo > 7) 1025 return MCDisassembler::Fail; 1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1027 } 1028 1029 static DecodeStatus 1030 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1031 uint64_t Address, const void *Decoder) { 1032 if (RegNo > 15) 1033 return MCDisassembler::Fail; 1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1035 } 1036 1037 static const uint16_t QPRDecoderTable[] = { 1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1042 }; 1043 1044 1045 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1046 uint64_t Address, const void *Decoder) { 1047 if (RegNo > 31 || (RegNo & 1) != 0) 1048 return MCDisassembler::Fail; 1049 RegNo >>= 1; 1050 1051 unsigned Register = QPRDecoderTable[RegNo]; 1052 Inst.addOperand(MCOperand::createReg(Register)); 1053 return MCDisassembler::Success; 1054 } 1055 1056 static const uint16_t DPairDecoderTable[] = { 1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1062 ARM::Q15 1063 }; 1064 1065 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1066 uint64_t Address, const void *Decoder) { 1067 if (RegNo > 30) 1068 return MCDisassembler::Fail; 1069 1070 unsigned Register = DPairDecoderTable[RegNo]; 1071 Inst.addOperand(MCOperand::createReg(Register)); 1072 return MCDisassembler::Success; 1073 } 1074 1075 static const uint16_t DPairSpacedDecoderTable[] = { 1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1083 ARM::D28_D30, ARM::D29_D31 1084 }; 1085 1086 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1087 unsigned RegNo, 1088 uint64_t Address, 1089 const void *Decoder) { 1090 if (RegNo > 29) 1091 return MCDisassembler::Fail; 1092 1093 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1094 Inst.addOperand(MCOperand::createReg(Register)); 1095 return MCDisassembler::Success; 1096 } 1097 1098 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1099 uint64_t Address, const void *Decoder) { 1100 if (Val == 0xF) return MCDisassembler::Fail; 1101 // AL predicate is not allowed on Thumb1 branches. 1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1103 return MCDisassembler::Fail; 1104 Inst.addOperand(MCOperand::createImm(Val)); 1105 if (Val == ARMCC::AL) { 1106 Inst.addOperand(MCOperand::createReg(0)); 1107 } else 1108 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1109 return MCDisassembler::Success; 1110 } 1111 1112 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1113 uint64_t Address, const void *Decoder) { 1114 if (Val) 1115 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1116 else 1117 Inst.addOperand(MCOperand::createReg(0)); 1118 return MCDisassembler::Success; 1119 } 1120 1121 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1122 uint64_t Address, const void *Decoder) { 1123 DecodeStatus S = MCDisassembler::Success; 1124 1125 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1126 unsigned type = fieldFromInstruction(Val, 5, 2); 1127 unsigned imm = fieldFromInstruction(Val, 7, 5); 1128 1129 // Register-immediate 1130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1131 return MCDisassembler::Fail; 1132 1133 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1134 switch (type) { 1135 case 0: 1136 Shift = ARM_AM::lsl; 1137 break; 1138 case 1: 1139 Shift = ARM_AM::lsr; 1140 break; 1141 case 2: 1142 Shift = ARM_AM::asr; 1143 break; 1144 case 3: 1145 Shift = ARM_AM::ror; 1146 break; 1147 } 1148 1149 if (Shift == ARM_AM::ror && imm == 0) 1150 Shift = ARM_AM::rrx; 1151 1152 unsigned Op = Shift | (imm << 3); 1153 Inst.addOperand(MCOperand::createImm(Op)); 1154 1155 return S; 1156 } 1157 1158 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1159 uint64_t Address, const void *Decoder) { 1160 DecodeStatus S = MCDisassembler::Success; 1161 1162 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1163 unsigned type = fieldFromInstruction(Val, 5, 2); 1164 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1165 1166 // Register-register 1167 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1168 return MCDisassembler::Fail; 1169 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1170 return MCDisassembler::Fail; 1171 1172 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1173 switch (type) { 1174 case 0: 1175 Shift = ARM_AM::lsl; 1176 break; 1177 case 1: 1178 Shift = ARM_AM::lsr; 1179 break; 1180 case 2: 1181 Shift = ARM_AM::asr; 1182 break; 1183 case 3: 1184 Shift = ARM_AM::ror; 1185 break; 1186 } 1187 1188 Inst.addOperand(MCOperand::createImm(Shift)); 1189 1190 return S; 1191 } 1192 1193 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1194 uint64_t Address, const void *Decoder) { 1195 DecodeStatus S = MCDisassembler::Success; 1196 1197 bool NeedDisjointWriteback = false; 1198 unsigned WritebackReg = 0; 1199 switch (Inst.getOpcode()) { 1200 default: 1201 break; 1202 case ARM::LDMIA_UPD: 1203 case ARM::LDMDB_UPD: 1204 case ARM::LDMIB_UPD: 1205 case ARM::LDMDA_UPD: 1206 case ARM::t2LDMIA_UPD: 1207 case ARM::t2LDMDB_UPD: 1208 case ARM::t2STMIA_UPD: 1209 case ARM::t2STMDB_UPD: 1210 NeedDisjointWriteback = true; 1211 WritebackReg = Inst.getOperand(0).getReg(); 1212 break; 1213 } 1214 1215 // Empty register lists are not allowed. 1216 if (Val == 0) return MCDisassembler::Fail; 1217 for (unsigned i = 0; i < 16; ++i) { 1218 if (Val & (1 << i)) { 1219 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1220 return MCDisassembler::Fail; 1221 // Writeback not allowed if Rn is in the target list. 1222 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1223 Check(S, MCDisassembler::SoftFail); 1224 } 1225 } 1226 1227 return S; 1228 } 1229 1230 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1231 uint64_t Address, const void *Decoder) { 1232 DecodeStatus S = MCDisassembler::Success; 1233 1234 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1235 unsigned regs = fieldFromInstruction(Val, 0, 8); 1236 1237 // In case of unpredictable encoding, tweak the operands. 1238 if (regs == 0 || (Vd + regs) > 32) { 1239 regs = Vd + regs > 32 ? 32 - Vd : regs; 1240 regs = std::max( 1u, regs); 1241 S = MCDisassembler::SoftFail; 1242 } 1243 1244 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1245 return MCDisassembler::Fail; 1246 for (unsigned i = 0; i < (regs - 1); ++i) { 1247 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1248 return MCDisassembler::Fail; 1249 } 1250 1251 return S; 1252 } 1253 1254 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1255 uint64_t Address, const void *Decoder) { 1256 DecodeStatus S = MCDisassembler::Success; 1257 1258 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1259 unsigned regs = fieldFromInstruction(Val, 1, 7); 1260 1261 // In case of unpredictable encoding, tweak the operands. 1262 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1263 regs = Vd + regs > 32 ? 32 - Vd : regs; 1264 regs = std::max( 1u, regs); 1265 regs = std::min(16u, regs); 1266 S = MCDisassembler::SoftFail; 1267 } 1268 1269 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1270 return MCDisassembler::Fail; 1271 for (unsigned i = 0; i < (regs - 1); ++i) { 1272 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1273 return MCDisassembler::Fail; 1274 } 1275 1276 return S; 1277 } 1278 1279 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1280 uint64_t Address, const void *Decoder) { 1281 // This operand encodes a mask of contiguous zeros between a specified MSB 1282 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1283 // the mask of all bits LSB-and-lower, and then xor them to create 1284 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1285 // create the final mask. 1286 unsigned msb = fieldFromInstruction(Val, 5, 5); 1287 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1288 1289 DecodeStatus S = MCDisassembler::Success; 1290 if (lsb > msb) { 1291 Check(S, MCDisassembler::SoftFail); 1292 // The check above will cause the warning for the "potentially undefined 1293 // instruction encoding" but we can't build a bad MCOperand value here 1294 // with a lsb > msb or else printing the MCInst will cause a crash. 1295 lsb = msb; 1296 } 1297 1298 uint32_t msb_mask = 0xFFFFFFFF; 1299 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1300 uint32_t lsb_mask = (1U << lsb) - 1; 1301 1302 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1303 return S; 1304 } 1305 1306 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1307 uint64_t Address, const void *Decoder) { 1308 DecodeStatus S = MCDisassembler::Success; 1309 1310 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1311 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1312 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1313 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1314 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1315 unsigned U = fieldFromInstruction(Insn, 23, 1); 1316 1317 switch (Inst.getOpcode()) { 1318 case ARM::LDC_OFFSET: 1319 case ARM::LDC_PRE: 1320 case ARM::LDC_POST: 1321 case ARM::LDC_OPTION: 1322 case ARM::LDCL_OFFSET: 1323 case ARM::LDCL_PRE: 1324 case ARM::LDCL_POST: 1325 case ARM::LDCL_OPTION: 1326 case ARM::STC_OFFSET: 1327 case ARM::STC_PRE: 1328 case ARM::STC_POST: 1329 case ARM::STC_OPTION: 1330 case ARM::STCL_OFFSET: 1331 case ARM::STCL_PRE: 1332 case ARM::STCL_POST: 1333 case ARM::STCL_OPTION: 1334 case ARM::t2LDC_OFFSET: 1335 case ARM::t2LDC_PRE: 1336 case ARM::t2LDC_POST: 1337 case ARM::t2LDC_OPTION: 1338 case ARM::t2LDCL_OFFSET: 1339 case ARM::t2LDCL_PRE: 1340 case ARM::t2LDCL_POST: 1341 case ARM::t2LDCL_OPTION: 1342 case ARM::t2STC_OFFSET: 1343 case ARM::t2STC_PRE: 1344 case ARM::t2STC_POST: 1345 case ARM::t2STC_OPTION: 1346 case ARM::t2STCL_OFFSET: 1347 case ARM::t2STCL_PRE: 1348 case ARM::t2STCL_POST: 1349 case ARM::t2STCL_OPTION: 1350 if (coproc == 0xA || coproc == 0xB) 1351 return MCDisassembler::Fail; 1352 break; 1353 default: 1354 break; 1355 } 1356 1357 const FeatureBitset &featureBits = 1358 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1359 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1360 return MCDisassembler::Fail; 1361 1362 Inst.addOperand(MCOperand::createImm(coproc)); 1363 Inst.addOperand(MCOperand::createImm(CRd)); 1364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1365 return MCDisassembler::Fail; 1366 1367 switch (Inst.getOpcode()) { 1368 case ARM::t2LDC2_OFFSET: 1369 case ARM::t2LDC2L_OFFSET: 1370 case ARM::t2LDC2_PRE: 1371 case ARM::t2LDC2L_PRE: 1372 case ARM::t2STC2_OFFSET: 1373 case ARM::t2STC2L_OFFSET: 1374 case ARM::t2STC2_PRE: 1375 case ARM::t2STC2L_PRE: 1376 case ARM::LDC2_OFFSET: 1377 case ARM::LDC2L_OFFSET: 1378 case ARM::LDC2_PRE: 1379 case ARM::LDC2L_PRE: 1380 case ARM::STC2_OFFSET: 1381 case ARM::STC2L_OFFSET: 1382 case ARM::STC2_PRE: 1383 case ARM::STC2L_PRE: 1384 case ARM::t2LDC_OFFSET: 1385 case ARM::t2LDCL_OFFSET: 1386 case ARM::t2LDC_PRE: 1387 case ARM::t2LDCL_PRE: 1388 case ARM::t2STC_OFFSET: 1389 case ARM::t2STCL_OFFSET: 1390 case ARM::t2STC_PRE: 1391 case ARM::t2STCL_PRE: 1392 case ARM::LDC_OFFSET: 1393 case ARM::LDCL_OFFSET: 1394 case ARM::LDC_PRE: 1395 case ARM::LDCL_PRE: 1396 case ARM::STC_OFFSET: 1397 case ARM::STCL_OFFSET: 1398 case ARM::STC_PRE: 1399 case ARM::STCL_PRE: 1400 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1401 Inst.addOperand(MCOperand::createImm(imm)); 1402 break; 1403 case ARM::t2LDC2_POST: 1404 case ARM::t2LDC2L_POST: 1405 case ARM::t2STC2_POST: 1406 case ARM::t2STC2L_POST: 1407 case ARM::LDC2_POST: 1408 case ARM::LDC2L_POST: 1409 case ARM::STC2_POST: 1410 case ARM::STC2L_POST: 1411 case ARM::t2LDC_POST: 1412 case ARM::t2LDCL_POST: 1413 case ARM::t2STC_POST: 1414 case ARM::t2STCL_POST: 1415 case ARM::LDC_POST: 1416 case ARM::LDCL_POST: 1417 case ARM::STC_POST: 1418 case ARM::STCL_POST: 1419 imm |= U << 8; 1420 // fall through. 1421 default: 1422 // The 'option' variant doesn't encode 'U' in the immediate since 1423 // the immediate is unsigned [0,255]. 1424 Inst.addOperand(MCOperand::createImm(imm)); 1425 break; 1426 } 1427 1428 switch (Inst.getOpcode()) { 1429 case ARM::LDC_OFFSET: 1430 case ARM::LDC_PRE: 1431 case ARM::LDC_POST: 1432 case ARM::LDC_OPTION: 1433 case ARM::LDCL_OFFSET: 1434 case ARM::LDCL_PRE: 1435 case ARM::LDCL_POST: 1436 case ARM::LDCL_OPTION: 1437 case ARM::STC_OFFSET: 1438 case ARM::STC_PRE: 1439 case ARM::STC_POST: 1440 case ARM::STC_OPTION: 1441 case ARM::STCL_OFFSET: 1442 case ARM::STCL_PRE: 1443 case ARM::STCL_POST: 1444 case ARM::STCL_OPTION: 1445 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1446 return MCDisassembler::Fail; 1447 break; 1448 default: 1449 break; 1450 } 1451 1452 return S; 1453 } 1454 1455 static DecodeStatus 1456 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1457 uint64_t Address, const void *Decoder) { 1458 DecodeStatus S = MCDisassembler::Success; 1459 1460 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1461 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1462 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1463 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1464 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1465 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1466 unsigned P = fieldFromInstruction(Insn, 24, 1); 1467 unsigned W = fieldFromInstruction(Insn, 21, 1); 1468 1469 // On stores, the writeback operand precedes Rt. 1470 switch (Inst.getOpcode()) { 1471 case ARM::STR_POST_IMM: 1472 case ARM::STR_POST_REG: 1473 case ARM::STRB_POST_IMM: 1474 case ARM::STRB_POST_REG: 1475 case ARM::STRT_POST_REG: 1476 case ARM::STRT_POST_IMM: 1477 case ARM::STRBT_POST_REG: 1478 case ARM::STRBT_POST_IMM: 1479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1480 return MCDisassembler::Fail; 1481 break; 1482 default: 1483 break; 1484 } 1485 1486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1487 return MCDisassembler::Fail; 1488 1489 // On loads, the writeback operand comes after Rt. 1490 switch (Inst.getOpcode()) { 1491 case ARM::LDR_POST_IMM: 1492 case ARM::LDR_POST_REG: 1493 case ARM::LDRB_POST_IMM: 1494 case ARM::LDRB_POST_REG: 1495 case ARM::LDRBT_POST_REG: 1496 case ARM::LDRBT_POST_IMM: 1497 case ARM::LDRT_POST_REG: 1498 case ARM::LDRT_POST_IMM: 1499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1500 return MCDisassembler::Fail; 1501 break; 1502 default: 1503 break; 1504 } 1505 1506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1507 return MCDisassembler::Fail; 1508 1509 ARM_AM::AddrOpc Op = ARM_AM::add; 1510 if (!fieldFromInstruction(Insn, 23, 1)) 1511 Op = ARM_AM::sub; 1512 1513 bool writeback = (P == 0) || (W == 1); 1514 unsigned idx_mode = 0; 1515 if (P && writeback) 1516 idx_mode = ARMII::IndexModePre; 1517 else if (!P && writeback) 1518 idx_mode = ARMII::IndexModePost; 1519 1520 if (writeback && (Rn == 15 || Rn == Rt)) 1521 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1522 1523 if (reg) { 1524 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1525 return MCDisassembler::Fail; 1526 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1527 switch( fieldFromInstruction(Insn, 5, 2)) { 1528 case 0: 1529 Opc = ARM_AM::lsl; 1530 break; 1531 case 1: 1532 Opc = ARM_AM::lsr; 1533 break; 1534 case 2: 1535 Opc = ARM_AM::asr; 1536 break; 1537 case 3: 1538 Opc = ARM_AM::ror; 1539 break; 1540 default: 1541 return MCDisassembler::Fail; 1542 } 1543 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1544 if (Opc == ARM_AM::ror && amt == 0) 1545 Opc = ARM_AM::rrx; 1546 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1547 1548 Inst.addOperand(MCOperand::createImm(imm)); 1549 } else { 1550 Inst.addOperand(MCOperand::createReg(0)); 1551 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1552 Inst.addOperand(MCOperand::createImm(tmp)); 1553 } 1554 1555 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1556 return MCDisassembler::Fail; 1557 1558 return S; 1559 } 1560 1561 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1562 uint64_t Address, const void *Decoder) { 1563 DecodeStatus S = MCDisassembler::Success; 1564 1565 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1566 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1567 unsigned type = fieldFromInstruction(Val, 5, 2); 1568 unsigned imm = fieldFromInstruction(Val, 7, 5); 1569 unsigned U = fieldFromInstruction(Val, 12, 1); 1570 1571 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1572 switch (type) { 1573 case 0: 1574 ShOp = ARM_AM::lsl; 1575 break; 1576 case 1: 1577 ShOp = ARM_AM::lsr; 1578 break; 1579 case 2: 1580 ShOp = ARM_AM::asr; 1581 break; 1582 case 3: 1583 ShOp = ARM_AM::ror; 1584 break; 1585 } 1586 1587 if (ShOp == ARM_AM::ror && imm == 0) 1588 ShOp = ARM_AM::rrx; 1589 1590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1591 return MCDisassembler::Fail; 1592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1593 return MCDisassembler::Fail; 1594 unsigned shift; 1595 if (U) 1596 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1597 else 1598 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1599 Inst.addOperand(MCOperand::createImm(shift)); 1600 1601 return S; 1602 } 1603 1604 static DecodeStatus 1605 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1606 uint64_t Address, const void *Decoder) { 1607 DecodeStatus S = MCDisassembler::Success; 1608 1609 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1610 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1611 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1612 unsigned type = fieldFromInstruction(Insn, 22, 1); 1613 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1614 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1615 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1616 unsigned W = fieldFromInstruction(Insn, 21, 1); 1617 unsigned P = fieldFromInstruction(Insn, 24, 1); 1618 unsigned Rt2 = Rt + 1; 1619 1620 bool writeback = (W == 1) | (P == 0); 1621 1622 // For {LD,ST}RD, Rt must be even, else undefined. 1623 switch (Inst.getOpcode()) { 1624 case ARM::STRD: 1625 case ARM::STRD_PRE: 1626 case ARM::STRD_POST: 1627 case ARM::LDRD: 1628 case ARM::LDRD_PRE: 1629 case ARM::LDRD_POST: 1630 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1631 break; 1632 default: 1633 break; 1634 } 1635 switch (Inst.getOpcode()) { 1636 case ARM::STRD: 1637 case ARM::STRD_PRE: 1638 case ARM::STRD_POST: 1639 if (P == 0 && W == 1) 1640 S = MCDisassembler::SoftFail; 1641 1642 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1643 S = MCDisassembler::SoftFail; 1644 if (type && Rm == 15) 1645 S = MCDisassembler::SoftFail; 1646 if (Rt2 == 15) 1647 S = MCDisassembler::SoftFail; 1648 if (!type && fieldFromInstruction(Insn, 8, 4)) 1649 S = MCDisassembler::SoftFail; 1650 break; 1651 case ARM::STRH: 1652 case ARM::STRH_PRE: 1653 case ARM::STRH_POST: 1654 if (Rt == 15) 1655 S = MCDisassembler::SoftFail; 1656 if (writeback && (Rn == 15 || Rn == Rt)) 1657 S = MCDisassembler::SoftFail; 1658 if (!type && Rm == 15) 1659 S = MCDisassembler::SoftFail; 1660 break; 1661 case ARM::LDRD: 1662 case ARM::LDRD_PRE: 1663 case ARM::LDRD_POST: 1664 if (type && Rn == 15){ 1665 if (Rt2 == 15) 1666 S = MCDisassembler::SoftFail; 1667 break; 1668 } 1669 if (P == 0 && W == 1) 1670 S = MCDisassembler::SoftFail; 1671 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1672 S = MCDisassembler::SoftFail; 1673 if (!type && writeback && Rn == 15) 1674 S = MCDisassembler::SoftFail; 1675 if (writeback && (Rn == Rt || Rn == Rt2)) 1676 S = MCDisassembler::SoftFail; 1677 break; 1678 case ARM::LDRH: 1679 case ARM::LDRH_PRE: 1680 case ARM::LDRH_POST: 1681 if (type && Rn == 15){ 1682 if (Rt == 15) 1683 S = MCDisassembler::SoftFail; 1684 break; 1685 } 1686 if (Rt == 15) 1687 S = MCDisassembler::SoftFail; 1688 if (!type && Rm == 15) 1689 S = MCDisassembler::SoftFail; 1690 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1691 S = MCDisassembler::SoftFail; 1692 break; 1693 case ARM::LDRSH: 1694 case ARM::LDRSH_PRE: 1695 case ARM::LDRSH_POST: 1696 case ARM::LDRSB: 1697 case ARM::LDRSB_PRE: 1698 case ARM::LDRSB_POST: 1699 if (type && Rn == 15){ 1700 if (Rt == 15) 1701 S = MCDisassembler::SoftFail; 1702 break; 1703 } 1704 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1705 S = MCDisassembler::SoftFail; 1706 if (!type && (Rt == 15 || Rm == 15)) 1707 S = MCDisassembler::SoftFail; 1708 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1709 S = MCDisassembler::SoftFail; 1710 break; 1711 default: 1712 break; 1713 } 1714 1715 if (writeback) { // Writeback 1716 if (P) 1717 U |= ARMII::IndexModePre << 9; 1718 else 1719 U |= ARMII::IndexModePost << 9; 1720 1721 // On stores, the writeback operand precedes Rt. 1722 switch (Inst.getOpcode()) { 1723 case ARM::STRD: 1724 case ARM::STRD_PRE: 1725 case ARM::STRD_POST: 1726 case ARM::STRH: 1727 case ARM::STRH_PRE: 1728 case ARM::STRH_POST: 1729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1730 return MCDisassembler::Fail; 1731 break; 1732 default: 1733 break; 1734 } 1735 } 1736 1737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1738 return MCDisassembler::Fail; 1739 switch (Inst.getOpcode()) { 1740 case ARM::STRD: 1741 case ARM::STRD_PRE: 1742 case ARM::STRD_POST: 1743 case ARM::LDRD: 1744 case ARM::LDRD_PRE: 1745 case ARM::LDRD_POST: 1746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1747 return MCDisassembler::Fail; 1748 break; 1749 default: 1750 break; 1751 } 1752 1753 if (writeback) { 1754 // On loads, the writeback operand comes after Rt. 1755 switch (Inst.getOpcode()) { 1756 case ARM::LDRD: 1757 case ARM::LDRD_PRE: 1758 case ARM::LDRD_POST: 1759 case ARM::LDRH: 1760 case ARM::LDRH_PRE: 1761 case ARM::LDRH_POST: 1762 case ARM::LDRSH: 1763 case ARM::LDRSH_PRE: 1764 case ARM::LDRSH_POST: 1765 case ARM::LDRSB: 1766 case ARM::LDRSB_PRE: 1767 case ARM::LDRSB_POST: 1768 case ARM::LDRHTr: 1769 case ARM::LDRSBTr: 1770 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1771 return MCDisassembler::Fail; 1772 break; 1773 default: 1774 break; 1775 } 1776 } 1777 1778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1779 return MCDisassembler::Fail; 1780 1781 if (type) { 1782 Inst.addOperand(MCOperand::createReg(0)); 1783 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1784 } else { 1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1786 return MCDisassembler::Fail; 1787 Inst.addOperand(MCOperand::createImm(U)); 1788 } 1789 1790 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1791 return MCDisassembler::Fail; 1792 1793 return S; 1794 } 1795 1796 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1797 uint64_t Address, const void *Decoder) { 1798 DecodeStatus S = MCDisassembler::Success; 1799 1800 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1801 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1802 1803 switch (mode) { 1804 case 0: 1805 mode = ARM_AM::da; 1806 break; 1807 case 1: 1808 mode = ARM_AM::ia; 1809 break; 1810 case 2: 1811 mode = ARM_AM::db; 1812 break; 1813 case 3: 1814 mode = ARM_AM::ib; 1815 break; 1816 } 1817 1818 Inst.addOperand(MCOperand::createImm(mode)); 1819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1820 return MCDisassembler::Fail; 1821 1822 return S; 1823 } 1824 1825 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1826 uint64_t Address, const void *Decoder) { 1827 DecodeStatus S = MCDisassembler::Success; 1828 1829 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1830 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1831 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1832 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1833 1834 if (pred == 0xF) 1835 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1836 1837 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1838 return MCDisassembler::Fail; 1839 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1840 return MCDisassembler::Fail; 1841 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1842 return MCDisassembler::Fail; 1843 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1844 return MCDisassembler::Fail; 1845 return S; 1846 } 1847 1848 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1849 unsigned Insn, 1850 uint64_t Address, const void *Decoder) { 1851 DecodeStatus S = MCDisassembler::Success; 1852 1853 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1854 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1855 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1856 1857 if (pred == 0xF) { 1858 // Ambiguous with RFE and SRS 1859 switch (Inst.getOpcode()) { 1860 case ARM::LDMDA: 1861 Inst.setOpcode(ARM::RFEDA); 1862 break; 1863 case ARM::LDMDA_UPD: 1864 Inst.setOpcode(ARM::RFEDA_UPD); 1865 break; 1866 case ARM::LDMDB: 1867 Inst.setOpcode(ARM::RFEDB); 1868 break; 1869 case ARM::LDMDB_UPD: 1870 Inst.setOpcode(ARM::RFEDB_UPD); 1871 break; 1872 case ARM::LDMIA: 1873 Inst.setOpcode(ARM::RFEIA); 1874 break; 1875 case ARM::LDMIA_UPD: 1876 Inst.setOpcode(ARM::RFEIA_UPD); 1877 break; 1878 case ARM::LDMIB: 1879 Inst.setOpcode(ARM::RFEIB); 1880 break; 1881 case ARM::LDMIB_UPD: 1882 Inst.setOpcode(ARM::RFEIB_UPD); 1883 break; 1884 case ARM::STMDA: 1885 Inst.setOpcode(ARM::SRSDA); 1886 break; 1887 case ARM::STMDA_UPD: 1888 Inst.setOpcode(ARM::SRSDA_UPD); 1889 break; 1890 case ARM::STMDB: 1891 Inst.setOpcode(ARM::SRSDB); 1892 break; 1893 case ARM::STMDB_UPD: 1894 Inst.setOpcode(ARM::SRSDB_UPD); 1895 break; 1896 case ARM::STMIA: 1897 Inst.setOpcode(ARM::SRSIA); 1898 break; 1899 case ARM::STMIA_UPD: 1900 Inst.setOpcode(ARM::SRSIA_UPD); 1901 break; 1902 case ARM::STMIB: 1903 Inst.setOpcode(ARM::SRSIB); 1904 break; 1905 case ARM::STMIB_UPD: 1906 Inst.setOpcode(ARM::SRSIB_UPD); 1907 break; 1908 default: 1909 return MCDisassembler::Fail; 1910 } 1911 1912 // For stores (which become SRS's, the only operand is the mode. 1913 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1914 // Check SRS encoding constraints 1915 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1916 fieldFromInstruction(Insn, 20, 1) == 0)) 1917 return MCDisassembler::Fail; 1918 1919 Inst.addOperand( 1920 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 1921 return S; 1922 } 1923 1924 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1925 } 1926 1927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1928 return MCDisassembler::Fail; 1929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1930 return MCDisassembler::Fail; // Tied 1931 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1932 return MCDisassembler::Fail; 1933 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1934 return MCDisassembler::Fail; 1935 1936 return S; 1937 } 1938 1939 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1940 uint64_t Address, const void *Decoder) { 1941 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1942 unsigned M = fieldFromInstruction(Insn, 17, 1); 1943 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1944 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1945 1946 DecodeStatus S = MCDisassembler::Success; 1947 1948 // This decoder is called from multiple location that do not check 1949 // the full encoding is valid before they do. 1950 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1951 fieldFromInstruction(Insn, 16, 1) != 0 || 1952 fieldFromInstruction(Insn, 20, 8) != 0x10) 1953 return MCDisassembler::Fail; 1954 1955 // imod == '01' --> UNPREDICTABLE 1956 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1957 // return failure here. The '01' imod value is unprintable, so there's 1958 // nothing useful we could do even if we returned UNPREDICTABLE. 1959 1960 if (imod == 1) return MCDisassembler::Fail; 1961 1962 if (imod && M) { 1963 Inst.setOpcode(ARM::CPS3p); 1964 Inst.addOperand(MCOperand::createImm(imod)); 1965 Inst.addOperand(MCOperand::createImm(iflags)); 1966 Inst.addOperand(MCOperand::createImm(mode)); 1967 } else if (imod && !M) { 1968 Inst.setOpcode(ARM::CPS2p); 1969 Inst.addOperand(MCOperand::createImm(imod)); 1970 Inst.addOperand(MCOperand::createImm(iflags)); 1971 if (mode) S = MCDisassembler::SoftFail; 1972 } else if (!imod && M) { 1973 Inst.setOpcode(ARM::CPS1p); 1974 Inst.addOperand(MCOperand::createImm(mode)); 1975 if (iflags) S = MCDisassembler::SoftFail; 1976 } else { 1977 // imod == '00' && M == '0' --> UNPREDICTABLE 1978 Inst.setOpcode(ARM::CPS1p); 1979 Inst.addOperand(MCOperand::createImm(mode)); 1980 S = MCDisassembler::SoftFail; 1981 } 1982 1983 return S; 1984 } 1985 1986 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1987 uint64_t Address, const void *Decoder) { 1988 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1989 unsigned M = fieldFromInstruction(Insn, 8, 1); 1990 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1991 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1992 1993 DecodeStatus S = MCDisassembler::Success; 1994 1995 // imod == '01' --> UNPREDICTABLE 1996 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1997 // return failure here. The '01' imod value is unprintable, so there's 1998 // nothing useful we could do even if we returned UNPREDICTABLE. 1999 2000 if (imod == 1) return MCDisassembler::Fail; 2001 2002 if (imod && M) { 2003 Inst.setOpcode(ARM::t2CPS3p); 2004 Inst.addOperand(MCOperand::createImm(imod)); 2005 Inst.addOperand(MCOperand::createImm(iflags)); 2006 Inst.addOperand(MCOperand::createImm(mode)); 2007 } else if (imod && !M) { 2008 Inst.setOpcode(ARM::t2CPS2p); 2009 Inst.addOperand(MCOperand::createImm(imod)); 2010 Inst.addOperand(MCOperand::createImm(iflags)); 2011 if (mode) S = MCDisassembler::SoftFail; 2012 } else if (!imod && M) { 2013 Inst.setOpcode(ARM::t2CPS1p); 2014 Inst.addOperand(MCOperand::createImm(mode)); 2015 if (iflags) S = MCDisassembler::SoftFail; 2016 } else { 2017 // imod == '00' && M == '0' --> this is a HINT instruction 2018 int imm = fieldFromInstruction(Insn, 0, 8); 2019 // HINT are defined only for immediate in [0..4] 2020 if(imm > 4) return MCDisassembler::Fail; 2021 Inst.setOpcode(ARM::t2HINT); 2022 Inst.addOperand(MCOperand::createImm(imm)); 2023 } 2024 2025 return S; 2026 } 2027 2028 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2029 uint64_t Address, const void *Decoder) { 2030 DecodeStatus S = MCDisassembler::Success; 2031 2032 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2033 unsigned imm = 0; 2034 2035 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2036 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2037 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2038 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2039 2040 if (Inst.getOpcode() == ARM::t2MOVTi16) 2041 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2042 return MCDisassembler::Fail; 2043 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2044 return MCDisassembler::Fail; 2045 2046 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2047 Inst.addOperand(MCOperand::createImm(imm)); 2048 2049 return S; 2050 } 2051 2052 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2053 uint64_t Address, const void *Decoder) { 2054 DecodeStatus S = MCDisassembler::Success; 2055 2056 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2057 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2058 unsigned imm = 0; 2059 2060 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2061 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2062 2063 if (Inst.getOpcode() == ARM::MOVTi16) 2064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2065 return MCDisassembler::Fail; 2066 2067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2068 return MCDisassembler::Fail; 2069 2070 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2071 Inst.addOperand(MCOperand::createImm(imm)); 2072 2073 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2074 return MCDisassembler::Fail; 2075 2076 return S; 2077 } 2078 2079 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2080 uint64_t Address, const void *Decoder) { 2081 DecodeStatus S = MCDisassembler::Success; 2082 2083 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2084 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2085 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2086 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2087 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2088 2089 if (pred == 0xF) 2090 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2091 2092 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2093 return MCDisassembler::Fail; 2094 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2095 return MCDisassembler::Fail; 2096 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2097 return MCDisassembler::Fail; 2098 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2099 return MCDisassembler::Fail; 2100 2101 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2102 return MCDisassembler::Fail; 2103 2104 return S; 2105 } 2106 2107 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2108 uint64_t Address, const void *Decoder) { 2109 DecodeStatus S = MCDisassembler::Success; 2110 2111 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2112 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2113 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2114 2115 if (Pred == 0xF) 2116 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2117 2118 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2119 return MCDisassembler::Fail; 2120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2121 return MCDisassembler::Fail; 2122 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2123 return MCDisassembler::Fail; 2124 2125 return S; 2126 } 2127 2128 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2129 uint64_t Address, const void *Decoder) { 2130 DecodeStatus S = MCDisassembler::Success; 2131 2132 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2133 2134 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2135 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2136 2137 if (!FeatureBits[ARM::HasV8_1aOps] || 2138 !FeatureBits[ARM::HasV8Ops]) 2139 return MCDisassembler::Fail; 2140 2141 // Decoder can be called from DecodeTST, which does not check the full 2142 // encoding is valid. 2143 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2144 fieldFromInstruction(Insn, 4,4) != 0) 2145 return MCDisassembler::Fail; 2146 if (fieldFromInstruction(Insn, 10,10) != 0 || 2147 fieldFromInstruction(Insn, 0,4) != 0) 2148 S = MCDisassembler::SoftFail; 2149 2150 Inst.setOpcode(ARM::SETPAN); 2151 Inst.addOperand(MCOperand::createImm(Imm)); 2152 2153 return S; 2154 } 2155 2156 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2157 uint64_t Address, const void *Decoder) { 2158 DecodeStatus S = MCDisassembler::Success; 2159 2160 unsigned add = fieldFromInstruction(Val, 12, 1); 2161 unsigned imm = fieldFromInstruction(Val, 0, 12); 2162 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2163 2164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2165 return MCDisassembler::Fail; 2166 2167 if (!add) imm *= -1; 2168 if (imm == 0 && !add) imm = INT32_MIN; 2169 Inst.addOperand(MCOperand::createImm(imm)); 2170 if (Rn == 15) 2171 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2172 2173 return S; 2174 } 2175 2176 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2177 uint64_t Address, const void *Decoder) { 2178 DecodeStatus S = MCDisassembler::Success; 2179 2180 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2181 unsigned U = fieldFromInstruction(Val, 8, 1); 2182 unsigned imm = fieldFromInstruction(Val, 0, 8); 2183 2184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2185 return MCDisassembler::Fail; 2186 2187 if (U) 2188 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2189 else 2190 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2191 2192 return S; 2193 } 2194 2195 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2196 uint64_t Address, const void *Decoder) { 2197 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2198 } 2199 2200 static DecodeStatus 2201 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2202 uint64_t Address, const void *Decoder) { 2203 DecodeStatus Status = MCDisassembler::Success; 2204 2205 // Note the J1 and J2 values are from the encoded instruction. So here 2206 // change them to I1 and I2 values via as documented: 2207 // I1 = NOT(J1 EOR S); 2208 // I2 = NOT(J2 EOR S); 2209 // and build the imm32 with one trailing zero as documented: 2210 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2211 unsigned S = fieldFromInstruction(Insn, 26, 1); 2212 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2213 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2214 unsigned I1 = !(J1 ^ S); 2215 unsigned I2 = !(J2 ^ S); 2216 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2217 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2218 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2219 int imm32 = SignExtend32<25>(tmp << 1); 2220 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2221 true, 4, Inst, Decoder)) 2222 Inst.addOperand(MCOperand::createImm(imm32)); 2223 2224 return Status; 2225 } 2226 2227 static DecodeStatus 2228 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2229 uint64_t Address, const void *Decoder) { 2230 DecodeStatus S = MCDisassembler::Success; 2231 2232 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2233 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2234 2235 if (pred == 0xF) { 2236 Inst.setOpcode(ARM::BLXi); 2237 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2238 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2239 true, 4, Inst, Decoder)) 2240 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2241 return S; 2242 } 2243 2244 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2245 true, 4, Inst, Decoder)) 2246 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2247 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2248 return MCDisassembler::Fail; 2249 2250 return S; 2251 } 2252 2253 2254 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2255 uint64_t Address, const void *Decoder) { 2256 DecodeStatus S = MCDisassembler::Success; 2257 2258 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2259 unsigned align = fieldFromInstruction(Val, 4, 2); 2260 2261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2262 return MCDisassembler::Fail; 2263 if (!align) 2264 Inst.addOperand(MCOperand::createImm(0)); 2265 else 2266 Inst.addOperand(MCOperand::createImm(4 << align)); 2267 2268 return S; 2269 } 2270 2271 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2272 uint64_t Address, const void *Decoder) { 2273 DecodeStatus S = MCDisassembler::Success; 2274 2275 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2276 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2277 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2278 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2279 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2280 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2281 2282 // First output register 2283 switch (Inst.getOpcode()) { 2284 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2285 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2286 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2287 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2288 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2289 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2290 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2291 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2292 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2293 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2294 return MCDisassembler::Fail; 2295 break; 2296 case ARM::VLD2b16: 2297 case ARM::VLD2b32: 2298 case ARM::VLD2b8: 2299 case ARM::VLD2b16wb_fixed: 2300 case ARM::VLD2b16wb_register: 2301 case ARM::VLD2b32wb_fixed: 2302 case ARM::VLD2b32wb_register: 2303 case ARM::VLD2b8wb_fixed: 2304 case ARM::VLD2b8wb_register: 2305 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2306 return MCDisassembler::Fail; 2307 break; 2308 default: 2309 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2310 return MCDisassembler::Fail; 2311 } 2312 2313 // Second output register 2314 switch (Inst.getOpcode()) { 2315 case ARM::VLD3d8: 2316 case ARM::VLD3d16: 2317 case ARM::VLD3d32: 2318 case ARM::VLD3d8_UPD: 2319 case ARM::VLD3d16_UPD: 2320 case ARM::VLD3d32_UPD: 2321 case ARM::VLD4d8: 2322 case ARM::VLD4d16: 2323 case ARM::VLD4d32: 2324 case ARM::VLD4d8_UPD: 2325 case ARM::VLD4d16_UPD: 2326 case ARM::VLD4d32_UPD: 2327 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2328 return MCDisassembler::Fail; 2329 break; 2330 case ARM::VLD3q8: 2331 case ARM::VLD3q16: 2332 case ARM::VLD3q32: 2333 case ARM::VLD3q8_UPD: 2334 case ARM::VLD3q16_UPD: 2335 case ARM::VLD3q32_UPD: 2336 case ARM::VLD4q8: 2337 case ARM::VLD4q16: 2338 case ARM::VLD4q32: 2339 case ARM::VLD4q8_UPD: 2340 case ARM::VLD4q16_UPD: 2341 case ARM::VLD4q32_UPD: 2342 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2343 return MCDisassembler::Fail; 2344 default: 2345 break; 2346 } 2347 2348 // Third output register 2349 switch(Inst.getOpcode()) { 2350 case ARM::VLD3d8: 2351 case ARM::VLD3d16: 2352 case ARM::VLD3d32: 2353 case ARM::VLD3d8_UPD: 2354 case ARM::VLD3d16_UPD: 2355 case ARM::VLD3d32_UPD: 2356 case ARM::VLD4d8: 2357 case ARM::VLD4d16: 2358 case ARM::VLD4d32: 2359 case ARM::VLD4d8_UPD: 2360 case ARM::VLD4d16_UPD: 2361 case ARM::VLD4d32_UPD: 2362 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2363 return MCDisassembler::Fail; 2364 break; 2365 case ARM::VLD3q8: 2366 case ARM::VLD3q16: 2367 case ARM::VLD3q32: 2368 case ARM::VLD3q8_UPD: 2369 case ARM::VLD3q16_UPD: 2370 case ARM::VLD3q32_UPD: 2371 case ARM::VLD4q8: 2372 case ARM::VLD4q16: 2373 case ARM::VLD4q32: 2374 case ARM::VLD4q8_UPD: 2375 case ARM::VLD4q16_UPD: 2376 case ARM::VLD4q32_UPD: 2377 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2378 return MCDisassembler::Fail; 2379 break; 2380 default: 2381 break; 2382 } 2383 2384 // Fourth output register 2385 switch (Inst.getOpcode()) { 2386 case ARM::VLD4d8: 2387 case ARM::VLD4d16: 2388 case ARM::VLD4d32: 2389 case ARM::VLD4d8_UPD: 2390 case ARM::VLD4d16_UPD: 2391 case ARM::VLD4d32_UPD: 2392 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2393 return MCDisassembler::Fail; 2394 break; 2395 case ARM::VLD4q8: 2396 case ARM::VLD4q16: 2397 case ARM::VLD4q32: 2398 case ARM::VLD4q8_UPD: 2399 case ARM::VLD4q16_UPD: 2400 case ARM::VLD4q32_UPD: 2401 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2402 return MCDisassembler::Fail; 2403 break; 2404 default: 2405 break; 2406 } 2407 2408 // Writeback operand 2409 switch (Inst.getOpcode()) { 2410 case ARM::VLD1d8wb_fixed: 2411 case ARM::VLD1d16wb_fixed: 2412 case ARM::VLD1d32wb_fixed: 2413 case ARM::VLD1d64wb_fixed: 2414 case ARM::VLD1d8wb_register: 2415 case ARM::VLD1d16wb_register: 2416 case ARM::VLD1d32wb_register: 2417 case ARM::VLD1d64wb_register: 2418 case ARM::VLD1q8wb_fixed: 2419 case ARM::VLD1q16wb_fixed: 2420 case ARM::VLD1q32wb_fixed: 2421 case ARM::VLD1q64wb_fixed: 2422 case ARM::VLD1q8wb_register: 2423 case ARM::VLD1q16wb_register: 2424 case ARM::VLD1q32wb_register: 2425 case ARM::VLD1q64wb_register: 2426 case ARM::VLD1d8Twb_fixed: 2427 case ARM::VLD1d8Twb_register: 2428 case ARM::VLD1d16Twb_fixed: 2429 case ARM::VLD1d16Twb_register: 2430 case ARM::VLD1d32Twb_fixed: 2431 case ARM::VLD1d32Twb_register: 2432 case ARM::VLD1d64Twb_fixed: 2433 case ARM::VLD1d64Twb_register: 2434 case ARM::VLD1d8Qwb_fixed: 2435 case ARM::VLD1d8Qwb_register: 2436 case ARM::VLD1d16Qwb_fixed: 2437 case ARM::VLD1d16Qwb_register: 2438 case ARM::VLD1d32Qwb_fixed: 2439 case ARM::VLD1d32Qwb_register: 2440 case ARM::VLD1d64Qwb_fixed: 2441 case ARM::VLD1d64Qwb_register: 2442 case ARM::VLD2d8wb_fixed: 2443 case ARM::VLD2d16wb_fixed: 2444 case ARM::VLD2d32wb_fixed: 2445 case ARM::VLD2q8wb_fixed: 2446 case ARM::VLD2q16wb_fixed: 2447 case ARM::VLD2q32wb_fixed: 2448 case ARM::VLD2d8wb_register: 2449 case ARM::VLD2d16wb_register: 2450 case ARM::VLD2d32wb_register: 2451 case ARM::VLD2q8wb_register: 2452 case ARM::VLD2q16wb_register: 2453 case ARM::VLD2q32wb_register: 2454 case ARM::VLD2b8wb_fixed: 2455 case ARM::VLD2b16wb_fixed: 2456 case ARM::VLD2b32wb_fixed: 2457 case ARM::VLD2b8wb_register: 2458 case ARM::VLD2b16wb_register: 2459 case ARM::VLD2b32wb_register: 2460 Inst.addOperand(MCOperand::createImm(0)); 2461 break; 2462 case ARM::VLD3d8_UPD: 2463 case ARM::VLD3d16_UPD: 2464 case ARM::VLD3d32_UPD: 2465 case ARM::VLD3q8_UPD: 2466 case ARM::VLD3q16_UPD: 2467 case ARM::VLD3q32_UPD: 2468 case ARM::VLD4d8_UPD: 2469 case ARM::VLD4d16_UPD: 2470 case ARM::VLD4d32_UPD: 2471 case ARM::VLD4q8_UPD: 2472 case ARM::VLD4q16_UPD: 2473 case ARM::VLD4q32_UPD: 2474 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2475 return MCDisassembler::Fail; 2476 break; 2477 default: 2478 break; 2479 } 2480 2481 // AddrMode6 Base (register+alignment) 2482 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2483 return MCDisassembler::Fail; 2484 2485 // AddrMode6 Offset (register) 2486 switch (Inst.getOpcode()) { 2487 default: 2488 // The below have been updated to have explicit am6offset split 2489 // between fixed and register offset. For those instructions not 2490 // yet updated, we need to add an additional reg0 operand for the 2491 // fixed variant. 2492 // 2493 // The fixed offset encodes as Rm == 0xd, so we check for that. 2494 if (Rm == 0xd) { 2495 Inst.addOperand(MCOperand::createReg(0)); 2496 break; 2497 } 2498 // Fall through to handle the register offset variant. 2499 case ARM::VLD1d8wb_fixed: 2500 case ARM::VLD1d16wb_fixed: 2501 case ARM::VLD1d32wb_fixed: 2502 case ARM::VLD1d64wb_fixed: 2503 case ARM::VLD1d8Twb_fixed: 2504 case ARM::VLD1d16Twb_fixed: 2505 case ARM::VLD1d32Twb_fixed: 2506 case ARM::VLD1d64Twb_fixed: 2507 case ARM::VLD1d8Qwb_fixed: 2508 case ARM::VLD1d16Qwb_fixed: 2509 case ARM::VLD1d32Qwb_fixed: 2510 case ARM::VLD1d64Qwb_fixed: 2511 case ARM::VLD1d8wb_register: 2512 case ARM::VLD1d16wb_register: 2513 case ARM::VLD1d32wb_register: 2514 case ARM::VLD1d64wb_register: 2515 case ARM::VLD1q8wb_fixed: 2516 case ARM::VLD1q16wb_fixed: 2517 case ARM::VLD1q32wb_fixed: 2518 case ARM::VLD1q64wb_fixed: 2519 case ARM::VLD1q8wb_register: 2520 case ARM::VLD1q16wb_register: 2521 case ARM::VLD1q32wb_register: 2522 case ARM::VLD1q64wb_register: 2523 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2524 // variant encodes Rm == 0xf. Anything else is a register offset post- 2525 // increment and we need to add the register operand to the instruction. 2526 if (Rm != 0xD && Rm != 0xF && 2527 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2528 return MCDisassembler::Fail; 2529 break; 2530 case ARM::VLD2d8wb_fixed: 2531 case ARM::VLD2d16wb_fixed: 2532 case ARM::VLD2d32wb_fixed: 2533 case ARM::VLD2b8wb_fixed: 2534 case ARM::VLD2b16wb_fixed: 2535 case ARM::VLD2b32wb_fixed: 2536 case ARM::VLD2q8wb_fixed: 2537 case ARM::VLD2q16wb_fixed: 2538 case ARM::VLD2q32wb_fixed: 2539 break; 2540 } 2541 2542 return S; 2543 } 2544 2545 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2546 uint64_t Address, const void *Decoder) { 2547 unsigned type = fieldFromInstruction(Insn, 8, 4); 2548 unsigned align = fieldFromInstruction(Insn, 4, 2); 2549 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2550 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2551 if (type == 10 && align == 3) return MCDisassembler::Fail; 2552 2553 unsigned load = fieldFromInstruction(Insn, 21, 1); 2554 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2555 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2556 } 2557 2558 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2559 uint64_t Address, const void *Decoder) { 2560 unsigned size = fieldFromInstruction(Insn, 6, 2); 2561 if (size == 3) return MCDisassembler::Fail; 2562 2563 unsigned type = fieldFromInstruction(Insn, 8, 4); 2564 unsigned align = fieldFromInstruction(Insn, 4, 2); 2565 if (type == 8 && align == 3) return MCDisassembler::Fail; 2566 if (type == 9 && align == 3) return MCDisassembler::Fail; 2567 2568 unsigned load = fieldFromInstruction(Insn, 21, 1); 2569 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2570 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2571 } 2572 2573 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2574 uint64_t Address, const void *Decoder) { 2575 unsigned size = fieldFromInstruction(Insn, 6, 2); 2576 if (size == 3) return MCDisassembler::Fail; 2577 2578 unsigned align = fieldFromInstruction(Insn, 4, 2); 2579 if (align & 2) return MCDisassembler::Fail; 2580 2581 unsigned load = fieldFromInstruction(Insn, 21, 1); 2582 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2583 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2584 } 2585 2586 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2587 uint64_t Address, const void *Decoder) { 2588 unsigned size = fieldFromInstruction(Insn, 6, 2); 2589 if (size == 3) return MCDisassembler::Fail; 2590 2591 unsigned load = fieldFromInstruction(Insn, 21, 1); 2592 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2593 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2594 } 2595 2596 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2597 uint64_t Address, const void *Decoder) { 2598 DecodeStatus S = MCDisassembler::Success; 2599 2600 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2601 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2602 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2603 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2604 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2605 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2606 2607 // Writeback Operand 2608 switch (Inst.getOpcode()) { 2609 case ARM::VST1d8wb_fixed: 2610 case ARM::VST1d16wb_fixed: 2611 case ARM::VST1d32wb_fixed: 2612 case ARM::VST1d64wb_fixed: 2613 case ARM::VST1d8wb_register: 2614 case ARM::VST1d16wb_register: 2615 case ARM::VST1d32wb_register: 2616 case ARM::VST1d64wb_register: 2617 case ARM::VST1q8wb_fixed: 2618 case ARM::VST1q16wb_fixed: 2619 case ARM::VST1q32wb_fixed: 2620 case ARM::VST1q64wb_fixed: 2621 case ARM::VST1q8wb_register: 2622 case ARM::VST1q16wb_register: 2623 case ARM::VST1q32wb_register: 2624 case ARM::VST1q64wb_register: 2625 case ARM::VST1d8Twb_fixed: 2626 case ARM::VST1d16Twb_fixed: 2627 case ARM::VST1d32Twb_fixed: 2628 case ARM::VST1d64Twb_fixed: 2629 case ARM::VST1d8Twb_register: 2630 case ARM::VST1d16Twb_register: 2631 case ARM::VST1d32Twb_register: 2632 case ARM::VST1d64Twb_register: 2633 case ARM::VST1d8Qwb_fixed: 2634 case ARM::VST1d16Qwb_fixed: 2635 case ARM::VST1d32Qwb_fixed: 2636 case ARM::VST1d64Qwb_fixed: 2637 case ARM::VST1d8Qwb_register: 2638 case ARM::VST1d16Qwb_register: 2639 case ARM::VST1d32Qwb_register: 2640 case ARM::VST1d64Qwb_register: 2641 case ARM::VST2d8wb_fixed: 2642 case ARM::VST2d16wb_fixed: 2643 case ARM::VST2d32wb_fixed: 2644 case ARM::VST2d8wb_register: 2645 case ARM::VST2d16wb_register: 2646 case ARM::VST2d32wb_register: 2647 case ARM::VST2q8wb_fixed: 2648 case ARM::VST2q16wb_fixed: 2649 case ARM::VST2q32wb_fixed: 2650 case ARM::VST2q8wb_register: 2651 case ARM::VST2q16wb_register: 2652 case ARM::VST2q32wb_register: 2653 case ARM::VST2b8wb_fixed: 2654 case ARM::VST2b16wb_fixed: 2655 case ARM::VST2b32wb_fixed: 2656 case ARM::VST2b8wb_register: 2657 case ARM::VST2b16wb_register: 2658 case ARM::VST2b32wb_register: 2659 if (Rm == 0xF) 2660 return MCDisassembler::Fail; 2661 Inst.addOperand(MCOperand::createImm(0)); 2662 break; 2663 case ARM::VST3d8_UPD: 2664 case ARM::VST3d16_UPD: 2665 case ARM::VST3d32_UPD: 2666 case ARM::VST3q8_UPD: 2667 case ARM::VST3q16_UPD: 2668 case ARM::VST3q32_UPD: 2669 case ARM::VST4d8_UPD: 2670 case ARM::VST4d16_UPD: 2671 case ARM::VST4d32_UPD: 2672 case ARM::VST4q8_UPD: 2673 case ARM::VST4q16_UPD: 2674 case ARM::VST4q32_UPD: 2675 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2676 return MCDisassembler::Fail; 2677 break; 2678 default: 2679 break; 2680 } 2681 2682 // AddrMode6 Base (register+alignment) 2683 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2684 return MCDisassembler::Fail; 2685 2686 // AddrMode6 Offset (register) 2687 switch (Inst.getOpcode()) { 2688 default: 2689 if (Rm == 0xD) 2690 Inst.addOperand(MCOperand::createReg(0)); 2691 else if (Rm != 0xF) { 2692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2693 return MCDisassembler::Fail; 2694 } 2695 break; 2696 case ARM::VST1d8wb_fixed: 2697 case ARM::VST1d16wb_fixed: 2698 case ARM::VST1d32wb_fixed: 2699 case ARM::VST1d64wb_fixed: 2700 case ARM::VST1q8wb_fixed: 2701 case ARM::VST1q16wb_fixed: 2702 case ARM::VST1q32wb_fixed: 2703 case ARM::VST1q64wb_fixed: 2704 case ARM::VST1d8Twb_fixed: 2705 case ARM::VST1d16Twb_fixed: 2706 case ARM::VST1d32Twb_fixed: 2707 case ARM::VST1d64Twb_fixed: 2708 case ARM::VST1d8Qwb_fixed: 2709 case ARM::VST1d16Qwb_fixed: 2710 case ARM::VST1d32Qwb_fixed: 2711 case ARM::VST1d64Qwb_fixed: 2712 case ARM::VST2d8wb_fixed: 2713 case ARM::VST2d16wb_fixed: 2714 case ARM::VST2d32wb_fixed: 2715 case ARM::VST2q8wb_fixed: 2716 case ARM::VST2q16wb_fixed: 2717 case ARM::VST2q32wb_fixed: 2718 case ARM::VST2b8wb_fixed: 2719 case ARM::VST2b16wb_fixed: 2720 case ARM::VST2b32wb_fixed: 2721 break; 2722 } 2723 2724 2725 // First input register 2726 switch (Inst.getOpcode()) { 2727 case ARM::VST1q16: 2728 case ARM::VST1q32: 2729 case ARM::VST1q64: 2730 case ARM::VST1q8: 2731 case ARM::VST1q16wb_fixed: 2732 case ARM::VST1q16wb_register: 2733 case ARM::VST1q32wb_fixed: 2734 case ARM::VST1q32wb_register: 2735 case ARM::VST1q64wb_fixed: 2736 case ARM::VST1q64wb_register: 2737 case ARM::VST1q8wb_fixed: 2738 case ARM::VST1q8wb_register: 2739 case ARM::VST2d16: 2740 case ARM::VST2d32: 2741 case ARM::VST2d8: 2742 case ARM::VST2d16wb_fixed: 2743 case ARM::VST2d16wb_register: 2744 case ARM::VST2d32wb_fixed: 2745 case ARM::VST2d32wb_register: 2746 case ARM::VST2d8wb_fixed: 2747 case ARM::VST2d8wb_register: 2748 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 break; 2751 case ARM::VST2b16: 2752 case ARM::VST2b32: 2753 case ARM::VST2b8: 2754 case ARM::VST2b16wb_fixed: 2755 case ARM::VST2b16wb_register: 2756 case ARM::VST2b32wb_fixed: 2757 case ARM::VST2b32wb_register: 2758 case ARM::VST2b8wb_fixed: 2759 case ARM::VST2b8wb_register: 2760 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2761 return MCDisassembler::Fail; 2762 break; 2763 default: 2764 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2765 return MCDisassembler::Fail; 2766 } 2767 2768 // Second input register 2769 switch (Inst.getOpcode()) { 2770 case ARM::VST3d8: 2771 case ARM::VST3d16: 2772 case ARM::VST3d32: 2773 case ARM::VST3d8_UPD: 2774 case ARM::VST3d16_UPD: 2775 case ARM::VST3d32_UPD: 2776 case ARM::VST4d8: 2777 case ARM::VST4d16: 2778 case ARM::VST4d32: 2779 case ARM::VST4d8_UPD: 2780 case ARM::VST4d16_UPD: 2781 case ARM::VST4d32_UPD: 2782 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2783 return MCDisassembler::Fail; 2784 break; 2785 case ARM::VST3q8: 2786 case ARM::VST3q16: 2787 case ARM::VST3q32: 2788 case ARM::VST3q8_UPD: 2789 case ARM::VST3q16_UPD: 2790 case ARM::VST3q32_UPD: 2791 case ARM::VST4q8: 2792 case ARM::VST4q16: 2793 case ARM::VST4q32: 2794 case ARM::VST4q8_UPD: 2795 case ARM::VST4q16_UPD: 2796 case ARM::VST4q32_UPD: 2797 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2798 return MCDisassembler::Fail; 2799 break; 2800 default: 2801 break; 2802 } 2803 2804 // Third input register 2805 switch (Inst.getOpcode()) { 2806 case ARM::VST3d8: 2807 case ARM::VST3d16: 2808 case ARM::VST3d32: 2809 case ARM::VST3d8_UPD: 2810 case ARM::VST3d16_UPD: 2811 case ARM::VST3d32_UPD: 2812 case ARM::VST4d8: 2813 case ARM::VST4d16: 2814 case ARM::VST4d32: 2815 case ARM::VST4d8_UPD: 2816 case ARM::VST4d16_UPD: 2817 case ARM::VST4d32_UPD: 2818 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2819 return MCDisassembler::Fail; 2820 break; 2821 case ARM::VST3q8: 2822 case ARM::VST3q16: 2823 case ARM::VST3q32: 2824 case ARM::VST3q8_UPD: 2825 case ARM::VST3q16_UPD: 2826 case ARM::VST3q32_UPD: 2827 case ARM::VST4q8: 2828 case ARM::VST4q16: 2829 case ARM::VST4q32: 2830 case ARM::VST4q8_UPD: 2831 case ARM::VST4q16_UPD: 2832 case ARM::VST4q32_UPD: 2833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 break; 2836 default: 2837 break; 2838 } 2839 2840 // Fourth input register 2841 switch (Inst.getOpcode()) { 2842 case ARM::VST4d8: 2843 case ARM::VST4d16: 2844 case ARM::VST4d32: 2845 case ARM::VST4d8_UPD: 2846 case ARM::VST4d16_UPD: 2847 case ARM::VST4d32_UPD: 2848 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2849 return MCDisassembler::Fail; 2850 break; 2851 case ARM::VST4q8: 2852 case ARM::VST4q16: 2853 case ARM::VST4q32: 2854 case ARM::VST4q8_UPD: 2855 case ARM::VST4q16_UPD: 2856 case ARM::VST4q32_UPD: 2857 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2858 return MCDisassembler::Fail; 2859 break; 2860 default: 2861 break; 2862 } 2863 2864 return S; 2865 } 2866 2867 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2868 uint64_t Address, const void *Decoder) { 2869 DecodeStatus S = MCDisassembler::Success; 2870 2871 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2872 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2873 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2874 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2875 unsigned align = fieldFromInstruction(Insn, 4, 1); 2876 unsigned size = fieldFromInstruction(Insn, 6, 2); 2877 2878 if (size == 0 && align == 1) 2879 return MCDisassembler::Fail; 2880 align *= (1 << size); 2881 2882 switch (Inst.getOpcode()) { 2883 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2884 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2885 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2886 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2887 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2888 return MCDisassembler::Fail; 2889 break; 2890 default: 2891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2892 return MCDisassembler::Fail; 2893 break; 2894 } 2895 if (Rm != 0xF) { 2896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2897 return MCDisassembler::Fail; 2898 } 2899 2900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2901 return MCDisassembler::Fail; 2902 Inst.addOperand(MCOperand::createImm(align)); 2903 2904 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2905 // variant encodes Rm == 0xf. Anything else is a register offset post- 2906 // increment and we need to add the register operand to the instruction. 2907 if (Rm != 0xD && Rm != 0xF && 2908 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 2911 return S; 2912 } 2913 2914 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2915 uint64_t Address, const void *Decoder) { 2916 DecodeStatus S = MCDisassembler::Success; 2917 2918 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2919 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2920 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2921 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2922 unsigned align = fieldFromInstruction(Insn, 4, 1); 2923 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2924 align *= 2*size; 2925 2926 switch (Inst.getOpcode()) { 2927 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2928 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2929 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2930 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2931 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2932 return MCDisassembler::Fail; 2933 break; 2934 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2935 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2936 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2937 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2938 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2939 return MCDisassembler::Fail; 2940 break; 2941 default: 2942 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2943 return MCDisassembler::Fail; 2944 break; 2945 } 2946 2947 if (Rm != 0xF) 2948 Inst.addOperand(MCOperand::createImm(0)); 2949 2950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2951 return MCDisassembler::Fail; 2952 Inst.addOperand(MCOperand::createImm(align)); 2953 2954 if (Rm != 0xD && Rm != 0xF) { 2955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2956 return MCDisassembler::Fail; 2957 } 2958 2959 return S; 2960 } 2961 2962 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2963 uint64_t Address, const void *Decoder) { 2964 DecodeStatus S = MCDisassembler::Success; 2965 2966 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2967 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2968 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2969 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2970 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2971 2972 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2973 return MCDisassembler::Fail; 2974 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2975 return MCDisassembler::Fail; 2976 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2977 return MCDisassembler::Fail; 2978 if (Rm != 0xF) { 2979 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2980 return MCDisassembler::Fail; 2981 } 2982 2983 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 Inst.addOperand(MCOperand::createImm(0)); 2986 2987 if (Rm == 0xD) 2988 Inst.addOperand(MCOperand::createReg(0)); 2989 else if (Rm != 0xF) { 2990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2991 return MCDisassembler::Fail; 2992 } 2993 2994 return S; 2995 } 2996 2997 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2998 uint64_t Address, const void *Decoder) { 2999 DecodeStatus S = MCDisassembler::Success; 3000 3001 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3002 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3003 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3004 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3005 unsigned size = fieldFromInstruction(Insn, 6, 2); 3006 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3007 unsigned align = fieldFromInstruction(Insn, 4, 1); 3008 3009 if (size == 0x3) { 3010 if (align == 0) 3011 return MCDisassembler::Fail; 3012 align = 16; 3013 } else { 3014 if (size == 2) { 3015 align *= 8; 3016 } else { 3017 size = 1 << size; 3018 align *= 4*size; 3019 } 3020 } 3021 3022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3023 return MCDisassembler::Fail; 3024 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3025 return MCDisassembler::Fail; 3026 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3027 return MCDisassembler::Fail; 3028 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3029 return MCDisassembler::Fail; 3030 if (Rm != 0xF) { 3031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3032 return MCDisassembler::Fail; 3033 } 3034 3035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3036 return MCDisassembler::Fail; 3037 Inst.addOperand(MCOperand::createImm(align)); 3038 3039 if (Rm == 0xD) 3040 Inst.addOperand(MCOperand::createReg(0)); 3041 else if (Rm != 0xF) { 3042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3043 return MCDisassembler::Fail; 3044 } 3045 3046 return S; 3047 } 3048 3049 static DecodeStatus 3050 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3051 uint64_t Address, const void *Decoder) { 3052 DecodeStatus S = MCDisassembler::Success; 3053 3054 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3055 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3056 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3057 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3058 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3059 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3060 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3061 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3062 3063 if (Q) { 3064 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3065 return MCDisassembler::Fail; 3066 } else { 3067 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3068 return MCDisassembler::Fail; 3069 } 3070 3071 Inst.addOperand(MCOperand::createImm(imm)); 3072 3073 switch (Inst.getOpcode()) { 3074 case ARM::VORRiv4i16: 3075 case ARM::VORRiv2i32: 3076 case ARM::VBICiv4i16: 3077 case ARM::VBICiv2i32: 3078 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3079 return MCDisassembler::Fail; 3080 break; 3081 case ARM::VORRiv8i16: 3082 case ARM::VORRiv4i32: 3083 case ARM::VBICiv8i16: 3084 case ARM::VBICiv4i32: 3085 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3086 return MCDisassembler::Fail; 3087 break; 3088 default: 3089 break; 3090 } 3091 3092 return S; 3093 } 3094 3095 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3096 uint64_t Address, const void *Decoder) { 3097 DecodeStatus S = MCDisassembler::Success; 3098 3099 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3100 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3101 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3102 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3103 unsigned size = fieldFromInstruction(Insn, 18, 2); 3104 3105 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3108 return MCDisassembler::Fail; 3109 Inst.addOperand(MCOperand::createImm(8 << size)); 3110 3111 return S; 3112 } 3113 3114 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3115 uint64_t Address, const void *Decoder) { 3116 Inst.addOperand(MCOperand::createImm(8 - Val)); 3117 return MCDisassembler::Success; 3118 } 3119 3120 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3121 uint64_t Address, const void *Decoder) { 3122 Inst.addOperand(MCOperand::createImm(16 - Val)); 3123 return MCDisassembler::Success; 3124 } 3125 3126 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3127 uint64_t Address, const void *Decoder) { 3128 Inst.addOperand(MCOperand::createImm(32 - Val)); 3129 return MCDisassembler::Success; 3130 } 3131 3132 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3133 uint64_t Address, const void *Decoder) { 3134 Inst.addOperand(MCOperand::createImm(64 - Val)); 3135 return MCDisassembler::Success; 3136 } 3137 3138 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3139 uint64_t Address, const void *Decoder) { 3140 DecodeStatus S = MCDisassembler::Success; 3141 3142 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3143 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3144 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3145 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3146 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3147 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3148 unsigned op = fieldFromInstruction(Insn, 6, 1); 3149 3150 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3151 return MCDisassembler::Fail; 3152 if (op) { 3153 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3154 return MCDisassembler::Fail; // Writeback 3155 } 3156 3157 switch (Inst.getOpcode()) { 3158 case ARM::VTBL2: 3159 case ARM::VTBX2: 3160 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3161 return MCDisassembler::Fail; 3162 break; 3163 default: 3164 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3165 return MCDisassembler::Fail; 3166 } 3167 3168 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3169 return MCDisassembler::Fail; 3170 3171 return S; 3172 } 3173 3174 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3175 uint64_t Address, const void *Decoder) { 3176 DecodeStatus S = MCDisassembler::Success; 3177 3178 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3179 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3180 3181 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3182 return MCDisassembler::Fail; 3183 3184 switch(Inst.getOpcode()) { 3185 default: 3186 return MCDisassembler::Fail; 3187 case ARM::tADR: 3188 break; // tADR does not explicitly represent the PC as an operand. 3189 case ARM::tADDrSPi: 3190 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3191 break; 3192 } 3193 3194 Inst.addOperand(MCOperand::createImm(imm)); 3195 return S; 3196 } 3197 3198 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3199 uint64_t Address, const void *Decoder) { 3200 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3201 true, 2, Inst, Decoder)) 3202 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3203 return MCDisassembler::Success; 3204 } 3205 3206 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3207 uint64_t Address, const void *Decoder) { 3208 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3209 true, 4, Inst, Decoder)) 3210 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3211 return MCDisassembler::Success; 3212 } 3213 3214 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3215 uint64_t Address, const void *Decoder) { 3216 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3217 true, 2, Inst, Decoder)) 3218 Inst.addOperand(MCOperand::createImm(Val << 1)); 3219 return MCDisassembler::Success; 3220 } 3221 3222 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3223 uint64_t Address, const void *Decoder) { 3224 DecodeStatus S = MCDisassembler::Success; 3225 3226 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3227 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3228 3229 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3232 return MCDisassembler::Fail; 3233 3234 return S; 3235 } 3236 3237 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3238 uint64_t Address, const void *Decoder) { 3239 DecodeStatus S = MCDisassembler::Success; 3240 3241 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3242 unsigned imm = fieldFromInstruction(Val, 3, 5); 3243 3244 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3245 return MCDisassembler::Fail; 3246 Inst.addOperand(MCOperand::createImm(imm)); 3247 3248 return S; 3249 } 3250 3251 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3252 uint64_t Address, const void *Decoder) { 3253 unsigned imm = Val << 2; 3254 3255 Inst.addOperand(MCOperand::createImm(imm)); 3256 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3257 3258 return MCDisassembler::Success; 3259 } 3260 3261 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3262 uint64_t Address, const void *Decoder) { 3263 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3264 Inst.addOperand(MCOperand::createImm(Val)); 3265 3266 return MCDisassembler::Success; 3267 } 3268 3269 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3270 uint64_t Address, const void *Decoder) { 3271 DecodeStatus S = MCDisassembler::Success; 3272 3273 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3274 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3275 unsigned imm = fieldFromInstruction(Val, 0, 2); 3276 3277 // Thumb stores cannot use PC as dest register. 3278 switch (Inst.getOpcode()) { 3279 case ARM::t2STRHs: 3280 case ARM::t2STRBs: 3281 case ARM::t2STRs: 3282 if (Rn == 15) 3283 return MCDisassembler::Fail; 3284 default: 3285 break; 3286 } 3287 3288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3289 return MCDisassembler::Fail; 3290 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3291 return MCDisassembler::Fail; 3292 Inst.addOperand(MCOperand::createImm(imm)); 3293 3294 return S; 3295 } 3296 3297 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3298 uint64_t Address, const void *Decoder) { 3299 DecodeStatus S = MCDisassembler::Success; 3300 3301 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3302 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3303 3304 const FeatureBitset &featureBits = 3305 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3306 3307 bool hasMP = featureBits[ARM::FeatureMP]; 3308 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3309 3310 if (Rn == 15) { 3311 switch (Inst.getOpcode()) { 3312 case ARM::t2LDRBs: 3313 Inst.setOpcode(ARM::t2LDRBpci); 3314 break; 3315 case ARM::t2LDRHs: 3316 Inst.setOpcode(ARM::t2LDRHpci); 3317 break; 3318 case ARM::t2LDRSHs: 3319 Inst.setOpcode(ARM::t2LDRSHpci); 3320 break; 3321 case ARM::t2LDRSBs: 3322 Inst.setOpcode(ARM::t2LDRSBpci); 3323 break; 3324 case ARM::t2LDRs: 3325 Inst.setOpcode(ARM::t2LDRpci); 3326 break; 3327 case ARM::t2PLDs: 3328 Inst.setOpcode(ARM::t2PLDpci); 3329 break; 3330 case ARM::t2PLIs: 3331 Inst.setOpcode(ARM::t2PLIpci); 3332 break; 3333 default: 3334 return MCDisassembler::Fail; 3335 } 3336 3337 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3338 } 3339 3340 if (Rt == 15) { 3341 switch (Inst.getOpcode()) { 3342 case ARM::t2LDRSHs: 3343 return MCDisassembler::Fail; 3344 case ARM::t2LDRHs: 3345 Inst.setOpcode(ARM::t2PLDWs); 3346 break; 3347 case ARM::t2LDRSBs: 3348 Inst.setOpcode(ARM::t2PLIs); 3349 default: 3350 break; 3351 } 3352 } 3353 3354 switch (Inst.getOpcode()) { 3355 case ARM::t2PLDs: 3356 break; 3357 case ARM::t2PLIs: 3358 if (!hasV7Ops) 3359 return MCDisassembler::Fail; 3360 break; 3361 case ARM::t2PLDWs: 3362 if (!hasV7Ops || !hasMP) 3363 return MCDisassembler::Fail; 3364 break; 3365 default: 3366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3367 return MCDisassembler::Fail; 3368 } 3369 3370 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3371 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3372 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3373 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3374 return MCDisassembler::Fail; 3375 3376 return S; 3377 } 3378 3379 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3380 uint64_t Address, const void* Decoder) { 3381 DecodeStatus S = MCDisassembler::Success; 3382 3383 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3384 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3385 unsigned U = fieldFromInstruction(Insn, 9, 1); 3386 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3387 imm |= (U << 8); 3388 imm |= (Rn << 9); 3389 unsigned add = fieldFromInstruction(Insn, 9, 1); 3390 3391 const FeatureBitset &featureBits = 3392 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3393 3394 bool hasMP = featureBits[ARM::FeatureMP]; 3395 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3396 3397 if (Rn == 15) { 3398 switch (Inst.getOpcode()) { 3399 case ARM::t2LDRi8: 3400 Inst.setOpcode(ARM::t2LDRpci); 3401 break; 3402 case ARM::t2LDRBi8: 3403 Inst.setOpcode(ARM::t2LDRBpci); 3404 break; 3405 case ARM::t2LDRSBi8: 3406 Inst.setOpcode(ARM::t2LDRSBpci); 3407 break; 3408 case ARM::t2LDRHi8: 3409 Inst.setOpcode(ARM::t2LDRHpci); 3410 break; 3411 case ARM::t2LDRSHi8: 3412 Inst.setOpcode(ARM::t2LDRSHpci); 3413 break; 3414 case ARM::t2PLDi8: 3415 Inst.setOpcode(ARM::t2PLDpci); 3416 break; 3417 case ARM::t2PLIi8: 3418 Inst.setOpcode(ARM::t2PLIpci); 3419 break; 3420 default: 3421 return MCDisassembler::Fail; 3422 } 3423 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3424 } 3425 3426 if (Rt == 15) { 3427 switch (Inst.getOpcode()) { 3428 case ARM::t2LDRSHi8: 3429 return MCDisassembler::Fail; 3430 case ARM::t2LDRHi8: 3431 if (!add) 3432 Inst.setOpcode(ARM::t2PLDWi8); 3433 break; 3434 case ARM::t2LDRSBi8: 3435 Inst.setOpcode(ARM::t2PLIi8); 3436 break; 3437 default: 3438 break; 3439 } 3440 } 3441 3442 switch (Inst.getOpcode()) { 3443 case ARM::t2PLDi8: 3444 break; 3445 case ARM::t2PLIi8: 3446 if (!hasV7Ops) 3447 return MCDisassembler::Fail; 3448 break; 3449 case ARM::t2PLDWi8: 3450 if (!hasV7Ops || !hasMP) 3451 return MCDisassembler::Fail; 3452 break; 3453 default: 3454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3455 return MCDisassembler::Fail; 3456 } 3457 3458 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3459 return MCDisassembler::Fail; 3460 return S; 3461 } 3462 3463 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3464 uint64_t Address, const void* Decoder) { 3465 DecodeStatus S = MCDisassembler::Success; 3466 3467 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3468 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3469 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3470 imm |= (Rn << 13); 3471 3472 const FeatureBitset &featureBits = 3473 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3474 3475 bool hasMP = featureBits[ARM::FeatureMP]; 3476 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3477 3478 if (Rn == 15) { 3479 switch (Inst.getOpcode()) { 3480 case ARM::t2LDRi12: 3481 Inst.setOpcode(ARM::t2LDRpci); 3482 break; 3483 case ARM::t2LDRHi12: 3484 Inst.setOpcode(ARM::t2LDRHpci); 3485 break; 3486 case ARM::t2LDRSHi12: 3487 Inst.setOpcode(ARM::t2LDRSHpci); 3488 break; 3489 case ARM::t2LDRBi12: 3490 Inst.setOpcode(ARM::t2LDRBpci); 3491 break; 3492 case ARM::t2LDRSBi12: 3493 Inst.setOpcode(ARM::t2LDRSBpci); 3494 break; 3495 case ARM::t2PLDi12: 3496 Inst.setOpcode(ARM::t2PLDpci); 3497 break; 3498 case ARM::t2PLIi12: 3499 Inst.setOpcode(ARM::t2PLIpci); 3500 break; 3501 default: 3502 return MCDisassembler::Fail; 3503 } 3504 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3505 } 3506 3507 if (Rt == 15) { 3508 switch (Inst.getOpcode()) { 3509 case ARM::t2LDRSHi12: 3510 return MCDisassembler::Fail; 3511 case ARM::t2LDRHi12: 3512 Inst.setOpcode(ARM::t2PLDWi12); 3513 break; 3514 case ARM::t2LDRSBi12: 3515 Inst.setOpcode(ARM::t2PLIi12); 3516 break; 3517 default: 3518 break; 3519 } 3520 } 3521 3522 switch (Inst.getOpcode()) { 3523 case ARM::t2PLDi12: 3524 break; 3525 case ARM::t2PLIi12: 3526 if (!hasV7Ops) 3527 return MCDisassembler::Fail; 3528 break; 3529 case ARM::t2PLDWi12: 3530 if (!hasV7Ops || !hasMP) 3531 return MCDisassembler::Fail; 3532 break; 3533 default: 3534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3535 return MCDisassembler::Fail; 3536 } 3537 3538 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3539 return MCDisassembler::Fail; 3540 return S; 3541 } 3542 3543 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3544 uint64_t Address, const void* Decoder) { 3545 DecodeStatus S = MCDisassembler::Success; 3546 3547 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3548 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3549 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3550 imm |= (Rn << 9); 3551 3552 if (Rn == 15) { 3553 switch (Inst.getOpcode()) { 3554 case ARM::t2LDRT: 3555 Inst.setOpcode(ARM::t2LDRpci); 3556 break; 3557 case ARM::t2LDRBT: 3558 Inst.setOpcode(ARM::t2LDRBpci); 3559 break; 3560 case ARM::t2LDRHT: 3561 Inst.setOpcode(ARM::t2LDRHpci); 3562 break; 3563 case ARM::t2LDRSBT: 3564 Inst.setOpcode(ARM::t2LDRSBpci); 3565 break; 3566 case ARM::t2LDRSHT: 3567 Inst.setOpcode(ARM::t2LDRSHpci); 3568 break; 3569 default: 3570 return MCDisassembler::Fail; 3571 } 3572 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3573 } 3574 3575 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3576 return MCDisassembler::Fail; 3577 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 return S; 3580 } 3581 3582 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3583 uint64_t Address, const void* Decoder) { 3584 DecodeStatus S = MCDisassembler::Success; 3585 3586 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3587 unsigned U = fieldFromInstruction(Insn, 23, 1); 3588 int imm = fieldFromInstruction(Insn, 0, 12); 3589 3590 const FeatureBitset &featureBits = 3591 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3592 3593 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3594 3595 if (Rt == 15) { 3596 switch (Inst.getOpcode()) { 3597 case ARM::t2LDRBpci: 3598 case ARM::t2LDRHpci: 3599 Inst.setOpcode(ARM::t2PLDpci); 3600 break; 3601 case ARM::t2LDRSBpci: 3602 Inst.setOpcode(ARM::t2PLIpci); 3603 break; 3604 case ARM::t2LDRSHpci: 3605 return MCDisassembler::Fail; 3606 default: 3607 break; 3608 } 3609 } 3610 3611 switch(Inst.getOpcode()) { 3612 case ARM::t2PLDpci: 3613 break; 3614 case ARM::t2PLIpci: 3615 if (!hasV7Ops) 3616 return MCDisassembler::Fail; 3617 break; 3618 default: 3619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3620 return MCDisassembler::Fail; 3621 } 3622 3623 if (!U) { 3624 // Special case for #-0. 3625 if (imm == 0) 3626 imm = INT32_MIN; 3627 else 3628 imm = -imm; 3629 } 3630 Inst.addOperand(MCOperand::createImm(imm)); 3631 3632 return S; 3633 } 3634 3635 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3636 uint64_t Address, const void *Decoder) { 3637 if (Val == 0) 3638 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3639 else { 3640 int imm = Val & 0xFF; 3641 3642 if (!(Val & 0x100)) imm *= -1; 3643 Inst.addOperand(MCOperand::createImm(imm * 4)); 3644 } 3645 3646 return MCDisassembler::Success; 3647 } 3648 3649 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3650 uint64_t Address, const void *Decoder) { 3651 DecodeStatus S = MCDisassembler::Success; 3652 3653 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3654 unsigned imm = fieldFromInstruction(Val, 0, 9); 3655 3656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3657 return MCDisassembler::Fail; 3658 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3659 return MCDisassembler::Fail; 3660 3661 return S; 3662 } 3663 3664 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3665 uint64_t Address, const void *Decoder) { 3666 DecodeStatus S = MCDisassembler::Success; 3667 3668 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3669 unsigned imm = fieldFromInstruction(Val, 0, 8); 3670 3671 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3672 return MCDisassembler::Fail; 3673 3674 Inst.addOperand(MCOperand::createImm(imm)); 3675 3676 return S; 3677 } 3678 3679 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3680 uint64_t Address, const void *Decoder) { 3681 int imm = Val & 0xFF; 3682 if (Val == 0) 3683 imm = INT32_MIN; 3684 else if (!(Val & 0x100)) 3685 imm *= -1; 3686 Inst.addOperand(MCOperand::createImm(imm)); 3687 3688 return MCDisassembler::Success; 3689 } 3690 3691 3692 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3693 uint64_t Address, const void *Decoder) { 3694 DecodeStatus S = MCDisassembler::Success; 3695 3696 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3697 unsigned imm = fieldFromInstruction(Val, 0, 9); 3698 3699 // Thumb stores cannot use PC as dest register. 3700 switch (Inst.getOpcode()) { 3701 case ARM::t2STRT: 3702 case ARM::t2STRBT: 3703 case ARM::t2STRHT: 3704 case ARM::t2STRi8: 3705 case ARM::t2STRHi8: 3706 case ARM::t2STRBi8: 3707 if (Rn == 15) 3708 return MCDisassembler::Fail; 3709 break; 3710 default: 3711 break; 3712 } 3713 3714 // Some instructions always use an additive offset. 3715 switch (Inst.getOpcode()) { 3716 case ARM::t2LDRT: 3717 case ARM::t2LDRBT: 3718 case ARM::t2LDRHT: 3719 case ARM::t2LDRSBT: 3720 case ARM::t2LDRSHT: 3721 case ARM::t2STRT: 3722 case ARM::t2STRBT: 3723 case ARM::t2STRHT: 3724 imm |= 0x100; 3725 break; 3726 default: 3727 break; 3728 } 3729 3730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3731 return MCDisassembler::Fail; 3732 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3733 return MCDisassembler::Fail; 3734 3735 return S; 3736 } 3737 3738 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3739 uint64_t Address, const void *Decoder) { 3740 DecodeStatus S = MCDisassembler::Success; 3741 3742 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3743 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3744 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3745 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3746 addr |= Rn << 9; 3747 unsigned load = fieldFromInstruction(Insn, 20, 1); 3748 3749 if (Rn == 15) { 3750 switch (Inst.getOpcode()) { 3751 case ARM::t2LDR_PRE: 3752 case ARM::t2LDR_POST: 3753 Inst.setOpcode(ARM::t2LDRpci); 3754 break; 3755 case ARM::t2LDRB_PRE: 3756 case ARM::t2LDRB_POST: 3757 Inst.setOpcode(ARM::t2LDRBpci); 3758 break; 3759 case ARM::t2LDRH_PRE: 3760 case ARM::t2LDRH_POST: 3761 Inst.setOpcode(ARM::t2LDRHpci); 3762 break; 3763 case ARM::t2LDRSB_PRE: 3764 case ARM::t2LDRSB_POST: 3765 if (Rt == 15) 3766 Inst.setOpcode(ARM::t2PLIpci); 3767 else 3768 Inst.setOpcode(ARM::t2LDRSBpci); 3769 break; 3770 case ARM::t2LDRSH_PRE: 3771 case ARM::t2LDRSH_POST: 3772 Inst.setOpcode(ARM::t2LDRSHpci); 3773 break; 3774 default: 3775 return MCDisassembler::Fail; 3776 } 3777 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3778 } 3779 3780 if (!load) { 3781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3782 return MCDisassembler::Fail; 3783 } 3784 3785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3786 return MCDisassembler::Fail; 3787 3788 if (load) { 3789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3790 return MCDisassembler::Fail; 3791 } 3792 3793 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3794 return MCDisassembler::Fail; 3795 3796 return S; 3797 } 3798 3799 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3800 uint64_t Address, const void *Decoder) { 3801 DecodeStatus S = MCDisassembler::Success; 3802 3803 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3804 unsigned imm = fieldFromInstruction(Val, 0, 12); 3805 3806 // Thumb stores cannot use PC as dest register. 3807 switch (Inst.getOpcode()) { 3808 case ARM::t2STRi12: 3809 case ARM::t2STRBi12: 3810 case ARM::t2STRHi12: 3811 if (Rn == 15) 3812 return MCDisassembler::Fail; 3813 default: 3814 break; 3815 } 3816 3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3818 return MCDisassembler::Fail; 3819 Inst.addOperand(MCOperand::createImm(imm)); 3820 3821 return S; 3822 } 3823 3824 3825 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3826 uint64_t Address, const void *Decoder) { 3827 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3828 3829 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3830 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3831 Inst.addOperand(MCOperand::createImm(imm)); 3832 3833 return MCDisassembler::Success; 3834 } 3835 3836 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3837 uint64_t Address, const void *Decoder) { 3838 DecodeStatus S = MCDisassembler::Success; 3839 3840 if (Inst.getOpcode() == ARM::tADDrSP) { 3841 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3842 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3843 3844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3845 return MCDisassembler::Fail; 3846 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3848 return MCDisassembler::Fail; 3849 } else if (Inst.getOpcode() == ARM::tADDspr) { 3850 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3851 3852 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3853 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3855 return MCDisassembler::Fail; 3856 } 3857 3858 return S; 3859 } 3860 3861 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3862 uint64_t Address, const void *Decoder) { 3863 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3864 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3865 3866 Inst.addOperand(MCOperand::createImm(imod)); 3867 Inst.addOperand(MCOperand::createImm(flags)); 3868 3869 return MCDisassembler::Success; 3870 } 3871 3872 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3873 uint64_t Address, const void *Decoder) { 3874 DecodeStatus S = MCDisassembler::Success; 3875 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3876 unsigned add = fieldFromInstruction(Insn, 4, 1); 3877 3878 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3879 return MCDisassembler::Fail; 3880 Inst.addOperand(MCOperand::createImm(add)); 3881 3882 return S; 3883 } 3884 3885 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3886 uint64_t Address, const void *Decoder) { 3887 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3888 // Note only one trailing zero not two. Also the J1 and J2 values are from 3889 // the encoded instruction. So here change to I1 and I2 values via: 3890 // I1 = NOT(J1 EOR S); 3891 // I2 = NOT(J2 EOR S); 3892 // and build the imm32 with two trailing zeros as documented: 3893 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3894 unsigned S = (Val >> 23) & 1; 3895 unsigned J1 = (Val >> 22) & 1; 3896 unsigned J2 = (Val >> 21) & 1; 3897 unsigned I1 = !(J1 ^ S); 3898 unsigned I2 = !(J2 ^ S); 3899 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3900 int imm32 = SignExtend32<25>(tmp << 1); 3901 3902 if (!tryAddingSymbolicOperand(Address, 3903 (Address & ~2u) + imm32 + 4, 3904 true, 4, Inst, Decoder)) 3905 Inst.addOperand(MCOperand::createImm(imm32)); 3906 return MCDisassembler::Success; 3907 } 3908 3909 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3910 uint64_t Address, const void *Decoder) { 3911 if (Val == 0xA || Val == 0xB) 3912 return MCDisassembler::Fail; 3913 3914 const FeatureBitset &featureBits = 3915 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3916 3917 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 3918 return MCDisassembler::Fail; 3919 3920 Inst.addOperand(MCOperand::createImm(Val)); 3921 return MCDisassembler::Success; 3922 } 3923 3924 static DecodeStatus 3925 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3926 uint64_t Address, const void *Decoder) { 3927 DecodeStatus S = MCDisassembler::Success; 3928 3929 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3930 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3931 3932 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3933 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3934 return MCDisassembler::Fail; 3935 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3936 return MCDisassembler::Fail; 3937 return S; 3938 } 3939 3940 static DecodeStatus 3941 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3942 uint64_t Address, const void *Decoder) { 3943 DecodeStatus S = MCDisassembler::Success; 3944 3945 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3946 if (pred == 0xE || pred == 0xF) { 3947 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3948 switch (opc) { 3949 default: 3950 return MCDisassembler::Fail; 3951 case 0xf3bf8f4: 3952 Inst.setOpcode(ARM::t2DSB); 3953 break; 3954 case 0xf3bf8f5: 3955 Inst.setOpcode(ARM::t2DMB); 3956 break; 3957 case 0xf3bf8f6: 3958 Inst.setOpcode(ARM::t2ISB); 3959 break; 3960 } 3961 3962 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3963 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3964 } 3965 3966 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3967 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3968 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3969 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3970 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3971 3972 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3973 return MCDisassembler::Fail; 3974 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3975 return MCDisassembler::Fail; 3976 3977 return S; 3978 } 3979 3980 // Decode a shifted immediate operand. These basically consist 3981 // of an 8-bit value, and a 4-bit directive that specifies either 3982 // a splat operation or a rotation. 3983 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3984 uint64_t Address, const void *Decoder) { 3985 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3986 if (ctrl == 0) { 3987 unsigned byte = fieldFromInstruction(Val, 8, 2); 3988 unsigned imm = fieldFromInstruction(Val, 0, 8); 3989 switch (byte) { 3990 case 0: 3991 Inst.addOperand(MCOperand::createImm(imm)); 3992 break; 3993 case 1: 3994 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 3995 break; 3996 case 2: 3997 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 3998 break; 3999 case 3: 4000 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4001 (imm << 8) | imm)); 4002 break; 4003 } 4004 } else { 4005 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4006 unsigned rot = fieldFromInstruction(Val, 7, 5); 4007 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4008 Inst.addOperand(MCOperand::createImm(imm)); 4009 } 4010 4011 return MCDisassembler::Success; 4012 } 4013 4014 static DecodeStatus 4015 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4016 uint64_t Address, const void *Decoder){ 4017 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4018 true, 2, Inst, Decoder)) 4019 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4020 return MCDisassembler::Success; 4021 } 4022 4023 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4024 uint64_t Address, const void *Decoder){ 4025 // Val is passed in as S:J1:J2:imm10:imm11 4026 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4027 // the encoded instruction. So here change to I1 and I2 values via: 4028 // I1 = NOT(J1 EOR S); 4029 // I2 = NOT(J2 EOR S); 4030 // and build the imm32 with one trailing zero as documented: 4031 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4032 unsigned S = (Val >> 23) & 1; 4033 unsigned J1 = (Val >> 22) & 1; 4034 unsigned J2 = (Val >> 21) & 1; 4035 unsigned I1 = !(J1 ^ S); 4036 unsigned I2 = !(J2 ^ S); 4037 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4038 int imm32 = SignExtend32<25>(tmp << 1); 4039 4040 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4041 true, 4, Inst, Decoder)) 4042 Inst.addOperand(MCOperand::createImm(imm32)); 4043 return MCDisassembler::Success; 4044 } 4045 4046 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4047 uint64_t Address, const void *Decoder) { 4048 if (Val & ~0xf) 4049 return MCDisassembler::Fail; 4050 4051 Inst.addOperand(MCOperand::createImm(Val)); 4052 return MCDisassembler::Success; 4053 } 4054 4055 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4056 uint64_t Address, const void *Decoder) { 4057 if (Val & ~0xf) 4058 return MCDisassembler::Fail; 4059 4060 Inst.addOperand(MCOperand::createImm(Val)); 4061 return MCDisassembler::Success; 4062 } 4063 4064 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4065 uint64_t Address, const void *Decoder) { 4066 DecodeStatus S = MCDisassembler::Success; 4067 const FeatureBitset &FeatureBits = 4068 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4069 4070 if (FeatureBits[ARM::FeatureMClass]) { 4071 unsigned ValLow = Val & 0xff; 4072 4073 // Validate the SYSm value first. 4074 switch (ValLow) { 4075 case 0: // apsr 4076 case 1: // iapsr 4077 case 2: // eapsr 4078 case 3: // xpsr 4079 case 5: // ipsr 4080 case 6: // epsr 4081 case 7: // iepsr 4082 case 8: // msp 4083 case 9: // psp 4084 case 16: // primask 4085 case 20: // control 4086 break; 4087 case 17: // basepri 4088 case 18: // basepri_max 4089 case 19: // faultmask 4090 if (!(FeatureBits[ARM::HasV7Ops])) 4091 // Values basepri, basepri_max and faultmask are only valid for v7m. 4092 return MCDisassembler::Fail; 4093 break; 4094 default: 4095 return MCDisassembler::Fail; 4096 } 4097 4098 if (Inst.getOpcode() == ARM::t2MSR_M) { 4099 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4100 if (!(FeatureBits[ARM::HasV7Ops])) { 4101 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4102 // unpredictable. 4103 if (Mask != 2) 4104 S = MCDisassembler::SoftFail; 4105 } 4106 else { 4107 // The ARMv7-M architecture stores an additional 2-bit mask value in 4108 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4109 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4110 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4111 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4112 // only if the processor includes the DSP extension. 4113 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4114 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4115 S = MCDisassembler::SoftFail; 4116 } 4117 } 4118 } else { 4119 // A/R class 4120 if (Val == 0) 4121 return MCDisassembler::Fail; 4122 } 4123 Inst.addOperand(MCOperand::createImm(Val)); 4124 return S; 4125 } 4126 4127 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4128 uint64_t Address, const void *Decoder) { 4129 4130 unsigned R = fieldFromInstruction(Val, 5, 1); 4131 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4132 4133 // The table of encodings for these banked registers comes from B9.2.3 of the 4134 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4135 // neater. So by fiat, these values are UNPREDICTABLE: 4136 if (!R) { 4137 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || 4138 SysM == 0x1a || SysM == 0x1b) 4139 return MCDisassembler::SoftFail; 4140 } else { 4141 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && 4142 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) 4143 return MCDisassembler::SoftFail; 4144 } 4145 4146 Inst.addOperand(MCOperand::createImm(Val)); 4147 return MCDisassembler::Success; 4148 } 4149 4150 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4151 uint64_t Address, const void *Decoder) { 4152 DecodeStatus S = MCDisassembler::Success; 4153 4154 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4155 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4156 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4157 4158 if (Rn == 0xF) 4159 S = MCDisassembler::SoftFail; 4160 4161 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4162 return MCDisassembler::Fail; 4163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4164 return MCDisassembler::Fail; 4165 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4166 return MCDisassembler::Fail; 4167 4168 return S; 4169 } 4170 4171 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4172 uint64_t Address, const void *Decoder){ 4173 DecodeStatus S = MCDisassembler::Success; 4174 4175 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4176 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4177 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4178 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4179 4180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4181 return MCDisassembler::Fail; 4182 4183 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4184 S = MCDisassembler::SoftFail; 4185 4186 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4187 return MCDisassembler::Fail; 4188 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4189 return MCDisassembler::Fail; 4190 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4191 return MCDisassembler::Fail; 4192 4193 return S; 4194 } 4195 4196 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4197 uint64_t Address, const void *Decoder) { 4198 DecodeStatus S = MCDisassembler::Success; 4199 4200 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4201 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4202 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4203 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4204 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4205 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4206 4207 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4208 4209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4210 return MCDisassembler::Fail; 4211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4212 return MCDisassembler::Fail; 4213 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4214 return MCDisassembler::Fail; 4215 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4216 return MCDisassembler::Fail; 4217 4218 return S; 4219 } 4220 4221 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4222 uint64_t Address, const void *Decoder) { 4223 DecodeStatus S = MCDisassembler::Success; 4224 4225 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4226 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4227 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4228 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4229 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4230 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4231 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4232 4233 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4234 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4235 4236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4237 return MCDisassembler::Fail; 4238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4239 return MCDisassembler::Fail; 4240 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4241 return MCDisassembler::Fail; 4242 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4243 return MCDisassembler::Fail; 4244 4245 return S; 4246 } 4247 4248 4249 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4250 uint64_t Address, const void *Decoder) { 4251 DecodeStatus S = MCDisassembler::Success; 4252 4253 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4254 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4255 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4256 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4257 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4258 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4259 4260 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4261 4262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4263 return MCDisassembler::Fail; 4264 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4265 return MCDisassembler::Fail; 4266 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4267 return MCDisassembler::Fail; 4268 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4269 return MCDisassembler::Fail; 4270 4271 return S; 4272 } 4273 4274 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4275 uint64_t Address, const void *Decoder) { 4276 DecodeStatus S = MCDisassembler::Success; 4277 4278 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4279 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4280 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4281 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4282 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4283 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4284 4285 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4286 4287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4288 return MCDisassembler::Fail; 4289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4290 return MCDisassembler::Fail; 4291 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4292 return MCDisassembler::Fail; 4293 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4294 return MCDisassembler::Fail; 4295 4296 return S; 4297 } 4298 4299 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4300 uint64_t Address, const void *Decoder) { 4301 DecodeStatus S = MCDisassembler::Success; 4302 4303 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4304 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4305 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4306 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4307 unsigned size = fieldFromInstruction(Insn, 10, 2); 4308 4309 unsigned align = 0; 4310 unsigned index = 0; 4311 switch (size) { 4312 default: 4313 return MCDisassembler::Fail; 4314 case 0: 4315 if (fieldFromInstruction(Insn, 4, 1)) 4316 return MCDisassembler::Fail; // UNDEFINED 4317 index = fieldFromInstruction(Insn, 5, 3); 4318 break; 4319 case 1: 4320 if (fieldFromInstruction(Insn, 5, 1)) 4321 return MCDisassembler::Fail; // UNDEFINED 4322 index = fieldFromInstruction(Insn, 6, 2); 4323 if (fieldFromInstruction(Insn, 4, 1)) 4324 align = 2; 4325 break; 4326 case 2: 4327 if (fieldFromInstruction(Insn, 6, 1)) 4328 return MCDisassembler::Fail; // UNDEFINED 4329 index = fieldFromInstruction(Insn, 7, 1); 4330 4331 switch (fieldFromInstruction(Insn, 4, 2)) { 4332 case 0 : 4333 align = 0; break; 4334 case 3: 4335 align = 4; break; 4336 default: 4337 return MCDisassembler::Fail; 4338 } 4339 break; 4340 } 4341 4342 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 if (Rm != 0xF) { // Writeback 4345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4346 return MCDisassembler::Fail; 4347 } 4348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4349 return MCDisassembler::Fail; 4350 Inst.addOperand(MCOperand::createImm(align)); 4351 if (Rm != 0xF) { 4352 if (Rm != 0xD) { 4353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4354 return MCDisassembler::Fail; 4355 } else 4356 Inst.addOperand(MCOperand::createReg(0)); 4357 } 4358 4359 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4360 return MCDisassembler::Fail; 4361 Inst.addOperand(MCOperand::createImm(index)); 4362 4363 return S; 4364 } 4365 4366 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4367 uint64_t Address, const void *Decoder) { 4368 DecodeStatus S = MCDisassembler::Success; 4369 4370 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4371 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4372 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4373 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4374 unsigned size = fieldFromInstruction(Insn, 10, 2); 4375 4376 unsigned align = 0; 4377 unsigned index = 0; 4378 switch (size) { 4379 default: 4380 return MCDisassembler::Fail; 4381 case 0: 4382 if (fieldFromInstruction(Insn, 4, 1)) 4383 return MCDisassembler::Fail; // UNDEFINED 4384 index = fieldFromInstruction(Insn, 5, 3); 4385 break; 4386 case 1: 4387 if (fieldFromInstruction(Insn, 5, 1)) 4388 return MCDisassembler::Fail; // UNDEFINED 4389 index = fieldFromInstruction(Insn, 6, 2); 4390 if (fieldFromInstruction(Insn, 4, 1)) 4391 align = 2; 4392 break; 4393 case 2: 4394 if (fieldFromInstruction(Insn, 6, 1)) 4395 return MCDisassembler::Fail; // UNDEFINED 4396 index = fieldFromInstruction(Insn, 7, 1); 4397 4398 switch (fieldFromInstruction(Insn, 4, 2)) { 4399 case 0: 4400 align = 0; break; 4401 case 3: 4402 align = 4; break; 4403 default: 4404 return MCDisassembler::Fail; 4405 } 4406 break; 4407 } 4408 4409 if (Rm != 0xF) { // Writeback 4410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4411 return MCDisassembler::Fail; 4412 } 4413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4414 return MCDisassembler::Fail; 4415 Inst.addOperand(MCOperand::createImm(align)); 4416 if (Rm != 0xF) { 4417 if (Rm != 0xD) { 4418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4419 return MCDisassembler::Fail; 4420 } else 4421 Inst.addOperand(MCOperand::createReg(0)); 4422 } 4423 4424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4425 return MCDisassembler::Fail; 4426 Inst.addOperand(MCOperand::createImm(index)); 4427 4428 return S; 4429 } 4430 4431 4432 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4433 uint64_t Address, const void *Decoder) { 4434 DecodeStatus S = MCDisassembler::Success; 4435 4436 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4437 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4438 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4439 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4440 unsigned size = fieldFromInstruction(Insn, 10, 2); 4441 4442 unsigned align = 0; 4443 unsigned index = 0; 4444 unsigned inc = 1; 4445 switch (size) { 4446 default: 4447 return MCDisassembler::Fail; 4448 case 0: 4449 index = fieldFromInstruction(Insn, 5, 3); 4450 if (fieldFromInstruction(Insn, 4, 1)) 4451 align = 2; 4452 break; 4453 case 1: 4454 index = fieldFromInstruction(Insn, 6, 2); 4455 if (fieldFromInstruction(Insn, 4, 1)) 4456 align = 4; 4457 if (fieldFromInstruction(Insn, 5, 1)) 4458 inc = 2; 4459 break; 4460 case 2: 4461 if (fieldFromInstruction(Insn, 5, 1)) 4462 return MCDisassembler::Fail; // UNDEFINED 4463 index = fieldFromInstruction(Insn, 7, 1); 4464 if (fieldFromInstruction(Insn, 4, 1) != 0) 4465 align = 8; 4466 if (fieldFromInstruction(Insn, 6, 1)) 4467 inc = 2; 4468 break; 4469 } 4470 4471 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4472 return MCDisassembler::Fail; 4473 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4474 return MCDisassembler::Fail; 4475 if (Rm != 0xF) { // Writeback 4476 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4477 return MCDisassembler::Fail; 4478 } 4479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4480 return MCDisassembler::Fail; 4481 Inst.addOperand(MCOperand::createImm(align)); 4482 if (Rm != 0xF) { 4483 if (Rm != 0xD) { 4484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4485 return MCDisassembler::Fail; 4486 } else 4487 Inst.addOperand(MCOperand::createReg(0)); 4488 } 4489 4490 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4491 return MCDisassembler::Fail; 4492 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4493 return MCDisassembler::Fail; 4494 Inst.addOperand(MCOperand::createImm(index)); 4495 4496 return S; 4497 } 4498 4499 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4500 uint64_t Address, const void *Decoder) { 4501 DecodeStatus S = MCDisassembler::Success; 4502 4503 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4504 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4505 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4506 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4507 unsigned size = fieldFromInstruction(Insn, 10, 2); 4508 4509 unsigned align = 0; 4510 unsigned index = 0; 4511 unsigned inc = 1; 4512 switch (size) { 4513 default: 4514 return MCDisassembler::Fail; 4515 case 0: 4516 index = fieldFromInstruction(Insn, 5, 3); 4517 if (fieldFromInstruction(Insn, 4, 1)) 4518 align = 2; 4519 break; 4520 case 1: 4521 index = fieldFromInstruction(Insn, 6, 2); 4522 if (fieldFromInstruction(Insn, 4, 1)) 4523 align = 4; 4524 if (fieldFromInstruction(Insn, 5, 1)) 4525 inc = 2; 4526 break; 4527 case 2: 4528 if (fieldFromInstruction(Insn, 5, 1)) 4529 return MCDisassembler::Fail; // UNDEFINED 4530 index = fieldFromInstruction(Insn, 7, 1); 4531 if (fieldFromInstruction(Insn, 4, 1) != 0) 4532 align = 8; 4533 if (fieldFromInstruction(Insn, 6, 1)) 4534 inc = 2; 4535 break; 4536 } 4537 4538 if (Rm != 0xF) { // Writeback 4539 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4540 return MCDisassembler::Fail; 4541 } 4542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4543 return MCDisassembler::Fail; 4544 Inst.addOperand(MCOperand::createImm(align)); 4545 if (Rm != 0xF) { 4546 if (Rm != 0xD) { 4547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4548 return MCDisassembler::Fail; 4549 } else 4550 Inst.addOperand(MCOperand::createReg(0)); 4551 } 4552 4553 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4554 return MCDisassembler::Fail; 4555 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4556 return MCDisassembler::Fail; 4557 Inst.addOperand(MCOperand::createImm(index)); 4558 4559 return S; 4560 } 4561 4562 4563 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4564 uint64_t Address, const void *Decoder) { 4565 DecodeStatus S = MCDisassembler::Success; 4566 4567 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4568 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4569 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4570 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4571 unsigned size = fieldFromInstruction(Insn, 10, 2); 4572 4573 unsigned align = 0; 4574 unsigned index = 0; 4575 unsigned inc = 1; 4576 switch (size) { 4577 default: 4578 return MCDisassembler::Fail; 4579 case 0: 4580 if (fieldFromInstruction(Insn, 4, 1)) 4581 return MCDisassembler::Fail; // UNDEFINED 4582 index = fieldFromInstruction(Insn, 5, 3); 4583 break; 4584 case 1: 4585 if (fieldFromInstruction(Insn, 4, 1)) 4586 return MCDisassembler::Fail; // UNDEFINED 4587 index = fieldFromInstruction(Insn, 6, 2); 4588 if (fieldFromInstruction(Insn, 5, 1)) 4589 inc = 2; 4590 break; 4591 case 2: 4592 if (fieldFromInstruction(Insn, 4, 2)) 4593 return MCDisassembler::Fail; // UNDEFINED 4594 index = fieldFromInstruction(Insn, 7, 1); 4595 if (fieldFromInstruction(Insn, 6, 1)) 4596 inc = 2; 4597 break; 4598 } 4599 4600 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4601 return MCDisassembler::Fail; 4602 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4603 return MCDisassembler::Fail; 4604 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4605 return MCDisassembler::Fail; 4606 4607 if (Rm != 0xF) { // Writeback 4608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4609 return MCDisassembler::Fail; 4610 } 4611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4612 return MCDisassembler::Fail; 4613 Inst.addOperand(MCOperand::createImm(align)); 4614 if (Rm != 0xF) { 4615 if (Rm != 0xD) { 4616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4617 return MCDisassembler::Fail; 4618 } else 4619 Inst.addOperand(MCOperand::createReg(0)); 4620 } 4621 4622 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4623 return MCDisassembler::Fail; 4624 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4625 return MCDisassembler::Fail; 4626 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4627 return MCDisassembler::Fail; 4628 Inst.addOperand(MCOperand::createImm(index)); 4629 4630 return S; 4631 } 4632 4633 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4634 uint64_t Address, const void *Decoder) { 4635 DecodeStatus S = MCDisassembler::Success; 4636 4637 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4638 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4639 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4640 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4641 unsigned size = fieldFromInstruction(Insn, 10, 2); 4642 4643 unsigned align = 0; 4644 unsigned index = 0; 4645 unsigned inc = 1; 4646 switch (size) { 4647 default: 4648 return MCDisassembler::Fail; 4649 case 0: 4650 if (fieldFromInstruction(Insn, 4, 1)) 4651 return MCDisassembler::Fail; // UNDEFINED 4652 index = fieldFromInstruction(Insn, 5, 3); 4653 break; 4654 case 1: 4655 if (fieldFromInstruction(Insn, 4, 1)) 4656 return MCDisassembler::Fail; // UNDEFINED 4657 index = fieldFromInstruction(Insn, 6, 2); 4658 if (fieldFromInstruction(Insn, 5, 1)) 4659 inc = 2; 4660 break; 4661 case 2: 4662 if (fieldFromInstruction(Insn, 4, 2)) 4663 return MCDisassembler::Fail; // UNDEFINED 4664 index = fieldFromInstruction(Insn, 7, 1); 4665 if (fieldFromInstruction(Insn, 6, 1)) 4666 inc = 2; 4667 break; 4668 } 4669 4670 if (Rm != 0xF) { // Writeback 4671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4672 return MCDisassembler::Fail; 4673 } 4674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4675 return MCDisassembler::Fail; 4676 Inst.addOperand(MCOperand::createImm(align)); 4677 if (Rm != 0xF) { 4678 if (Rm != 0xD) { 4679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4680 return MCDisassembler::Fail; 4681 } else 4682 Inst.addOperand(MCOperand::createReg(0)); 4683 } 4684 4685 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4686 return MCDisassembler::Fail; 4687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4688 return MCDisassembler::Fail; 4689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4690 return MCDisassembler::Fail; 4691 Inst.addOperand(MCOperand::createImm(index)); 4692 4693 return S; 4694 } 4695 4696 4697 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4698 uint64_t Address, const void *Decoder) { 4699 DecodeStatus S = MCDisassembler::Success; 4700 4701 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4702 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4703 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4704 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4705 unsigned size = fieldFromInstruction(Insn, 10, 2); 4706 4707 unsigned align = 0; 4708 unsigned index = 0; 4709 unsigned inc = 1; 4710 switch (size) { 4711 default: 4712 return MCDisassembler::Fail; 4713 case 0: 4714 if (fieldFromInstruction(Insn, 4, 1)) 4715 align = 4; 4716 index = fieldFromInstruction(Insn, 5, 3); 4717 break; 4718 case 1: 4719 if (fieldFromInstruction(Insn, 4, 1)) 4720 align = 8; 4721 index = fieldFromInstruction(Insn, 6, 2); 4722 if (fieldFromInstruction(Insn, 5, 1)) 4723 inc = 2; 4724 break; 4725 case 2: 4726 switch (fieldFromInstruction(Insn, 4, 2)) { 4727 case 0: 4728 align = 0; break; 4729 case 3: 4730 return MCDisassembler::Fail; 4731 default: 4732 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4733 } 4734 4735 index = fieldFromInstruction(Insn, 7, 1); 4736 if (fieldFromInstruction(Insn, 6, 1)) 4737 inc = 2; 4738 break; 4739 } 4740 4741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4742 return MCDisassembler::Fail; 4743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4744 return MCDisassembler::Fail; 4745 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4746 return MCDisassembler::Fail; 4747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4748 return MCDisassembler::Fail; 4749 4750 if (Rm != 0xF) { // Writeback 4751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4752 return MCDisassembler::Fail; 4753 } 4754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4755 return MCDisassembler::Fail; 4756 Inst.addOperand(MCOperand::createImm(align)); 4757 if (Rm != 0xF) { 4758 if (Rm != 0xD) { 4759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4760 return MCDisassembler::Fail; 4761 } else 4762 Inst.addOperand(MCOperand::createReg(0)); 4763 } 4764 4765 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4766 return MCDisassembler::Fail; 4767 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4768 return MCDisassembler::Fail; 4769 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4770 return MCDisassembler::Fail; 4771 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4772 return MCDisassembler::Fail; 4773 Inst.addOperand(MCOperand::createImm(index)); 4774 4775 return S; 4776 } 4777 4778 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4779 uint64_t Address, const void *Decoder) { 4780 DecodeStatus S = MCDisassembler::Success; 4781 4782 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4783 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4784 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4785 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4786 unsigned size = fieldFromInstruction(Insn, 10, 2); 4787 4788 unsigned align = 0; 4789 unsigned index = 0; 4790 unsigned inc = 1; 4791 switch (size) { 4792 default: 4793 return MCDisassembler::Fail; 4794 case 0: 4795 if (fieldFromInstruction(Insn, 4, 1)) 4796 align = 4; 4797 index = fieldFromInstruction(Insn, 5, 3); 4798 break; 4799 case 1: 4800 if (fieldFromInstruction(Insn, 4, 1)) 4801 align = 8; 4802 index = fieldFromInstruction(Insn, 6, 2); 4803 if (fieldFromInstruction(Insn, 5, 1)) 4804 inc = 2; 4805 break; 4806 case 2: 4807 switch (fieldFromInstruction(Insn, 4, 2)) { 4808 case 0: 4809 align = 0; break; 4810 case 3: 4811 return MCDisassembler::Fail; 4812 default: 4813 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4814 } 4815 4816 index = fieldFromInstruction(Insn, 7, 1); 4817 if (fieldFromInstruction(Insn, 6, 1)) 4818 inc = 2; 4819 break; 4820 } 4821 4822 if (Rm != 0xF) { // Writeback 4823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4824 return MCDisassembler::Fail; 4825 } 4826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4827 return MCDisassembler::Fail; 4828 Inst.addOperand(MCOperand::createImm(align)); 4829 if (Rm != 0xF) { 4830 if (Rm != 0xD) { 4831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4832 return MCDisassembler::Fail; 4833 } else 4834 Inst.addOperand(MCOperand::createReg(0)); 4835 } 4836 4837 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4838 return MCDisassembler::Fail; 4839 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4840 return MCDisassembler::Fail; 4841 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4842 return MCDisassembler::Fail; 4843 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4844 return MCDisassembler::Fail; 4845 Inst.addOperand(MCOperand::createImm(index)); 4846 4847 return S; 4848 } 4849 4850 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4851 uint64_t Address, const void *Decoder) { 4852 DecodeStatus S = MCDisassembler::Success; 4853 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4854 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4855 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4856 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4857 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4858 4859 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4860 S = MCDisassembler::SoftFail; 4861 4862 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4863 return MCDisassembler::Fail; 4864 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4865 return MCDisassembler::Fail; 4866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4867 return MCDisassembler::Fail; 4868 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4869 return MCDisassembler::Fail; 4870 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4871 return MCDisassembler::Fail; 4872 4873 return S; 4874 } 4875 4876 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4877 uint64_t Address, const void *Decoder) { 4878 DecodeStatus S = MCDisassembler::Success; 4879 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4880 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4881 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4882 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4883 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4884 4885 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4886 S = MCDisassembler::SoftFail; 4887 4888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4889 return MCDisassembler::Fail; 4890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4891 return MCDisassembler::Fail; 4892 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4893 return MCDisassembler::Fail; 4894 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4895 return MCDisassembler::Fail; 4896 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4897 return MCDisassembler::Fail; 4898 4899 return S; 4900 } 4901 4902 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4903 uint64_t Address, const void *Decoder) { 4904 DecodeStatus S = MCDisassembler::Success; 4905 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4906 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4907 4908 if (pred == 0xF) { 4909 pred = 0xE; 4910 S = MCDisassembler::SoftFail; 4911 } 4912 4913 if (mask == 0x0) 4914 return MCDisassembler::Fail; 4915 4916 Inst.addOperand(MCOperand::createImm(pred)); 4917 Inst.addOperand(MCOperand::createImm(mask)); 4918 return S; 4919 } 4920 4921 static DecodeStatus 4922 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4923 uint64_t Address, const void *Decoder) { 4924 DecodeStatus S = MCDisassembler::Success; 4925 4926 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4927 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4928 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4929 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4930 unsigned W = fieldFromInstruction(Insn, 21, 1); 4931 unsigned U = fieldFromInstruction(Insn, 23, 1); 4932 unsigned P = fieldFromInstruction(Insn, 24, 1); 4933 bool writeback = (W == 1) | (P == 0); 4934 4935 addr |= (U << 8) | (Rn << 9); 4936 4937 if (writeback && (Rn == Rt || Rn == Rt2)) 4938 Check(S, MCDisassembler::SoftFail); 4939 if (Rt == Rt2) 4940 Check(S, MCDisassembler::SoftFail); 4941 4942 // Rt 4943 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4944 return MCDisassembler::Fail; 4945 // Rt2 4946 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4947 return MCDisassembler::Fail; 4948 // Writeback operand 4949 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4950 return MCDisassembler::Fail; 4951 // addr 4952 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4953 return MCDisassembler::Fail; 4954 4955 return S; 4956 } 4957 4958 static DecodeStatus 4959 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4960 uint64_t Address, const void *Decoder) { 4961 DecodeStatus S = MCDisassembler::Success; 4962 4963 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4964 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4965 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4966 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4967 unsigned W = fieldFromInstruction(Insn, 21, 1); 4968 unsigned U = fieldFromInstruction(Insn, 23, 1); 4969 unsigned P = fieldFromInstruction(Insn, 24, 1); 4970 bool writeback = (W == 1) | (P == 0); 4971 4972 addr |= (U << 8) | (Rn << 9); 4973 4974 if (writeback && (Rn == Rt || Rn == Rt2)) 4975 Check(S, MCDisassembler::SoftFail); 4976 4977 // Writeback operand 4978 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4979 return MCDisassembler::Fail; 4980 // Rt 4981 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4982 return MCDisassembler::Fail; 4983 // Rt2 4984 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4985 return MCDisassembler::Fail; 4986 // addr 4987 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4988 return MCDisassembler::Fail; 4989 4990 return S; 4991 } 4992 4993 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4994 uint64_t Address, const void *Decoder) { 4995 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4996 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4997 if (sign1 != sign2) return MCDisassembler::Fail; 4998 4999 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5000 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5001 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5002 Val |= sign1 << 12; 5003 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5004 5005 return MCDisassembler::Success; 5006 } 5007 5008 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5009 uint64_t Address, 5010 const void *Decoder) { 5011 DecodeStatus S = MCDisassembler::Success; 5012 5013 // Shift of "asr #32" is not allowed in Thumb2 mode. 5014 if (Val == 0x20) S = MCDisassembler::Fail; 5015 Inst.addOperand(MCOperand::createImm(Val)); 5016 return S; 5017 } 5018 5019 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5020 uint64_t Address, const void *Decoder) { 5021 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5022 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5023 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5024 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5025 5026 if (pred == 0xF) 5027 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5028 5029 DecodeStatus S = MCDisassembler::Success; 5030 5031 if (Rt == Rn || Rn == Rt2) 5032 S = MCDisassembler::SoftFail; 5033 5034 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5035 return MCDisassembler::Fail; 5036 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5037 return MCDisassembler::Fail; 5038 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5039 return MCDisassembler::Fail; 5040 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5041 return MCDisassembler::Fail; 5042 5043 return S; 5044 } 5045 5046 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5047 uint64_t Address, const void *Decoder) { 5048 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5049 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5050 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5051 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5052 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5053 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5054 unsigned op = fieldFromInstruction(Insn, 5, 1); 5055 5056 DecodeStatus S = MCDisassembler::Success; 5057 5058 // VMOVv2f32 is ambiguous with these decodings. 5059 if (!(imm & 0x38) && cmode == 0xF) { 5060 if (op == 1) return MCDisassembler::Fail; 5061 Inst.setOpcode(ARM::VMOVv2f32); 5062 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5063 } 5064 5065 if (!(imm & 0x20)) return MCDisassembler::Fail; 5066 5067 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5068 return MCDisassembler::Fail; 5069 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5070 return MCDisassembler::Fail; 5071 Inst.addOperand(MCOperand::createImm(64 - imm)); 5072 5073 return S; 5074 } 5075 5076 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5077 uint64_t Address, const void *Decoder) { 5078 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5079 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5080 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5081 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5082 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5083 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5084 unsigned op = fieldFromInstruction(Insn, 5, 1); 5085 5086 DecodeStatus S = MCDisassembler::Success; 5087 5088 // VMOVv4f32 is ambiguous with these decodings. 5089 if (!(imm & 0x38) && cmode == 0xF) { 5090 if (op == 1) return MCDisassembler::Fail; 5091 Inst.setOpcode(ARM::VMOVv4f32); 5092 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5093 } 5094 5095 if (!(imm & 0x20)) return MCDisassembler::Fail; 5096 5097 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5098 return MCDisassembler::Fail; 5099 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5100 return MCDisassembler::Fail; 5101 Inst.addOperand(MCOperand::createImm(64 - imm)); 5102 5103 return S; 5104 } 5105 5106 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5107 uint64_t Address, const void *Decoder) { 5108 DecodeStatus S = MCDisassembler::Success; 5109 5110 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5111 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5112 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5113 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5114 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5115 5116 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5117 S = MCDisassembler::SoftFail; 5118 5119 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5120 return MCDisassembler::Fail; 5121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5122 return MCDisassembler::Fail; 5123 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5124 return MCDisassembler::Fail; 5125 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5126 return MCDisassembler::Fail; 5127 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5128 return MCDisassembler::Fail; 5129 5130 return S; 5131 } 5132 5133 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 5134 uint64_t Address, const void *Decoder) { 5135 5136 DecodeStatus S = MCDisassembler::Success; 5137 5138 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5139 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5140 unsigned cop = fieldFromInstruction(Val, 8, 4); 5141 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5142 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5143 5144 if ((cop & ~0x1) == 0xa) 5145 return MCDisassembler::Fail; 5146 5147 if (Rt == Rt2) 5148 S = MCDisassembler::SoftFail; 5149 5150 Inst.addOperand(MCOperand::createImm(cop)); 5151 Inst.addOperand(MCOperand::createImm(opc1)); 5152 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5153 return MCDisassembler::Fail; 5154 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5155 return MCDisassembler::Fail; 5156 Inst.addOperand(MCOperand::createImm(CRm)); 5157 5158 return S; 5159 } 5160 5161