1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "llvm/MC/MCDisassembler.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "MCTargetDesc/ARMBaseInfo.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/LEB128.h" 25 #include "llvm/Support/MemoryObject.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <vector> 29 30 using namespace llvm; 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI) : 94 MCDisassembler(STI) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 102 const MemoryObject ®ion, uint64_t address, 103 raw_ostream &vStream, 104 raw_ostream &cStream) const override; 105 }; 106 107 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 108 class ThumbDisassembler : public MCDisassembler { 109 public: 110 /// Constructor - Initializes the disassembler. 111 /// 112 ThumbDisassembler(const MCSubtargetInfo &STI) : 113 MCDisassembler(STI) { 114 } 115 116 ~ThumbDisassembler() { 117 } 118 119 /// getInstruction - See MCDisassembler. 120 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 121 const MemoryObject ®ion, uint64_t address, 122 raw_ostream &vStream, 123 raw_ostream &cStream) const override; 124 125 private: 126 mutable ITStatus ITBlock; 127 DecodeStatus AddThumbPredicate(MCInst&) const; 128 void UpdateThumbVFPPredicate(MCInst&) const; 129 }; 130 } 131 132 static bool Check(DecodeStatus &Out, DecodeStatus In) { 133 switch (In) { 134 case MCDisassembler::Success: 135 // Out stays the same. 136 return true; 137 case MCDisassembler::SoftFail: 138 Out = In; 139 return true; 140 case MCDisassembler::Fail: 141 Out = In; 142 return false; 143 } 144 llvm_unreachable("Invalid DecodeStatus!"); 145 } 146 147 148 // Forward declare these because the autogenerated code will reference them. 149 // Definitions are further down. 150 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 153 unsigned RegNo, uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 156 unsigned RegNo, uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 173 unsigned RegNo, 174 uint64_t Address, 175 const void *Decoder); 176 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 181 unsigned RegNo, uint64_t Address, 182 const void *Decoder); 183 184 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 197 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 202 unsigned Insn, 203 uint64_t Address, 204 const void *Decoder); 205 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 214 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 215 unsigned Insn, 216 uint64_t Adddress, 217 const void *Decoder); 218 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 323 324 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void* Decoder); 346 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void* Decoder); 348 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void* Decoder); 350 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 397 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 #include "ARMGenDisassemblerTables.inc" 402 403 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 404 return new ARMDisassembler(STI); 405 } 406 407 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 408 return new ThumbDisassembler(STI); 409 } 410 411 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 412 const MemoryObject &Region, 413 uint64_t Address, 414 raw_ostream &os, 415 raw_ostream &cs) const { 416 CommentStream = &cs; 417 418 uint8_t bytes[4]; 419 420 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 421 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 422 423 // We want to read exactly 4 bytes of data. 424 if (Region.readBytes(Address, 4, bytes) == -1) { 425 Size = 0; 426 return MCDisassembler::Fail; 427 } 428 429 // Encoded as a small-endian 32-bit word in the stream. 430 uint32_t insn = (bytes[3] << 24) | 431 (bytes[2] << 16) | 432 (bytes[1] << 8) | 433 (bytes[0] << 0); 434 435 // Calling the auto-generated decoder function. 436 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 437 Address, this, STI); 438 if (result != MCDisassembler::Fail) { 439 Size = 4; 440 return result; 441 } 442 443 // VFP and NEON instructions, similarly, are shared between ARM 444 // and Thumb modes. 445 MI.clear(); 446 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 447 if (result != MCDisassembler::Fail) { 448 Size = 4; 449 return result; 450 } 451 452 MI.clear(); 453 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI); 454 if (result != MCDisassembler::Fail) { 455 Size = 4; 456 return result; 457 } 458 459 MI.clear(); 460 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 461 this, STI); 462 if (result != MCDisassembler::Fail) { 463 Size = 4; 464 // Add a fake predicate operand, because we share these instruction 465 // definitions with Thumb2 where these instructions are predicable. 466 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 467 return MCDisassembler::Fail; 468 return result; 469 } 470 471 MI.clear(); 472 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 473 this, STI); 474 if (result != MCDisassembler::Fail) { 475 Size = 4; 476 // Add a fake predicate operand, because we share these instruction 477 // definitions with Thumb2 where these instructions are predicable. 478 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 479 return MCDisassembler::Fail; 480 return result; 481 } 482 483 MI.clear(); 484 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 485 this, STI); 486 if (result != MCDisassembler::Fail) { 487 Size = 4; 488 // Add a fake predicate operand, because we share these instruction 489 // definitions with Thumb2 where these instructions are predicable. 490 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 491 return MCDisassembler::Fail; 492 return result; 493 } 494 495 MI.clear(); 496 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address, 497 this, STI); 498 if (result != MCDisassembler::Fail) { 499 Size = 4; 500 return result; 501 } 502 503 MI.clear(); 504 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address, 505 this, STI); 506 if (result != MCDisassembler::Fail) { 507 Size = 4; 508 return result; 509 } 510 511 MI.clear(); 512 Size = 0; 513 return MCDisassembler::Fail; 514 } 515 516 namespace llvm { 517 extern const MCInstrDesc ARMInsts[]; 518 } 519 520 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 521 /// immediate Value in the MCInst. The immediate Value has had any PC 522 /// adjustment made by the caller. If the instruction is a branch instruction 523 /// then isBranch is true, else false. If the getOpInfo() function was set as 524 /// part of the setupForSymbolicDisassembly() call then that function is called 525 /// to get any symbolic information at the Address for this instruction. If 526 /// that returns non-zero then the symbolic information it returns is used to 527 /// create an MCExpr and that is added as an operand to the MCInst. If 528 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 529 /// Value is done and if a symbol is found an MCExpr is created with that, else 530 /// an MCExpr with Value is created. This function returns true if it adds an 531 /// operand to the MCInst and false otherwise. 532 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 533 bool isBranch, uint64_t InstSize, 534 MCInst &MI, const void *Decoder) { 535 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 536 // FIXME: Does it make sense for value to be negative? 537 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 538 /* Offset */ 0, InstSize); 539 } 540 541 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 542 /// referenced by a load instruction with the base register that is the Pc. 543 /// These can often be values in a literal pool near the Address of the 544 /// instruction. The Address of the instruction and its immediate Value are 545 /// used as a possible literal pool entry. The SymbolLookUp call back will 546 /// return the name of a symbol referenced by the literal pool's entry if 547 /// the referenced address is that of a symbol. Or it will return a pointer to 548 /// a literal 'C' string if the referenced address of the literal pool's entry 549 /// is an address into a section with 'C' string literals. 550 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 551 const void *Decoder) { 552 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 553 Dis->tryAddingPcLoadReferenceComment(Value, Address); 554 } 555 556 // Thumb1 instructions don't have explicit S bits. Rather, they 557 // implicitly set CPSR. Since it's not represented in the encoding, the 558 // auto-generated decoder won't inject the CPSR operand. We need to fix 559 // that as a post-pass. 560 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 561 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 562 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 563 MCInst::iterator I = MI.begin(); 564 for (unsigned i = 0; i < NumOps; ++i, ++I) { 565 if (I == MI.end()) break; 566 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 567 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 568 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 569 return; 570 } 571 } 572 573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 574 } 575 576 // Most Thumb instructions don't have explicit predicates in the 577 // encoding, but rather get their predicates from IT context. We need 578 // to fix up the predicate operands using this context information as a 579 // post-pass. 580 MCDisassembler::DecodeStatus 581 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 582 MCDisassembler::DecodeStatus S = Success; 583 584 // A few instructions actually have predicates encoded in them. Don't 585 // try to overwrite it if we're seeing one of those. 586 switch (MI.getOpcode()) { 587 case ARM::tBcc: 588 case ARM::t2Bcc: 589 case ARM::tCBZ: 590 case ARM::tCBNZ: 591 case ARM::tCPS: 592 case ARM::t2CPS3p: 593 case ARM::t2CPS2p: 594 case ARM::t2CPS1p: 595 case ARM::tMOVSr: 596 case ARM::tSETEND: 597 // Some instructions (mostly conditional branches) are not 598 // allowed in IT blocks. 599 if (ITBlock.instrInITBlock()) 600 S = SoftFail; 601 else 602 return Success; 603 break; 604 case ARM::tB: 605 case ARM::t2B: 606 case ARM::t2TBB: 607 case ARM::t2TBH: 608 // Some instructions (mostly unconditional branches) can 609 // only appears at the end of, or outside of, an IT. 610 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 611 S = SoftFail; 612 break; 613 default: 614 break; 615 } 616 617 // If we're in an IT block, base the predicate on that. Otherwise, 618 // assume a predicate of AL. 619 unsigned CC; 620 CC = ITBlock.getITCC(); 621 if (CC == 0xF) 622 CC = ARMCC::AL; 623 if (ITBlock.instrInITBlock()) 624 ITBlock.advanceITState(); 625 626 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 627 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 628 MCInst::iterator I = MI.begin(); 629 for (unsigned i = 0; i < NumOps; ++i, ++I) { 630 if (I == MI.end()) break; 631 if (OpInfo[i].isPredicate()) { 632 I = MI.insert(I, MCOperand::CreateImm(CC)); 633 ++I; 634 if (CC == ARMCC::AL) 635 MI.insert(I, MCOperand::CreateReg(0)); 636 else 637 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 638 return S; 639 } 640 } 641 642 I = MI.insert(I, MCOperand::CreateImm(CC)); 643 ++I; 644 if (CC == ARMCC::AL) 645 MI.insert(I, MCOperand::CreateReg(0)); 646 else 647 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 648 649 return S; 650 } 651 652 // Thumb VFP instructions are a special case. Because we share their 653 // encodings between ARM and Thumb modes, and they are predicable in ARM 654 // mode, the auto-generated decoder will give them an (incorrect) 655 // predicate operand. We need to rewrite these operands based on the IT 656 // context as a post-pass. 657 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 658 unsigned CC; 659 CC = ITBlock.getITCC(); 660 if (ITBlock.instrInITBlock()) 661 ITBlock.advanceITState(); 662 663 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 664 MCInst::iterator I = MI.begin(); 665 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 666 for (unsigned i = 0; i < NumOps; ++i, ++I) { 667 if (OpInfo[i].isPredicate() ) { 668 I->setImm(CC); 669 ++I; 670 if (CC == ARMCC::AL) 671 I->setReg(0); 672 else 673 I->setReg(ARM::CPSR); 674 return; 675 } 676 } 677 } 678 679 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 680 const MemoryObject &Region, 681 uint64_t Address, 682 raw_ostream &os, 683 raw_ostream &cs) const { 684 CommentStream = &cs; 685 686 uint8_t bytes[4]; 687 688 assert((STI.getFeatureBits() & ARM::ModeThumb) && 689 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 690 691 // We want to read exactly 2 bytes of data. 692 if (Region.readBytes(Address, 2, bytes) == -1) { 693 Size = 0; 694 return MCDisassembler::Fail; 695 } 696 697 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 698 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 699 Address, this, STI); 700 if (result != MCDisassembler::Fail) { 701 Size = 2; 702 Check(result, AddThumbPredicate(MI)); 703 return result; 704 } 705 706 MI.clear(); 707 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 708 Address, this, STI); 709 if (result) { 710 Size = 2; 711 bool InITBlock = ITBlock.instrInITBlock(); 712 Check(result, AddThumbPredicate(MI)); 713 AddThumb1SBit(MI, InITBlock); 714 return result; 715 } 716 717 MI.clear(); 718 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 719 Address, this, STI); 720 if (result != MCDisassembler::Fail) { 721 Size = 2; 722 723 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 724 // the Thumb predicate. 725 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 726 result = MCDisassembler::SoftFail; 727 728 Check(result, AddThumbPredicate(MI)); 729 730 // If we find an IT instruction, we need to parse its condition 731 // code and mask operands so that we can apply them correctly 732 // to the subsequent instructions. 733 if (MI.getOpcode() == ARM::t2IT) { 734 735 unsigned Firstcond = MI.getOperand(0).getImm(); 736 unsigned Mask = MI.getOperand(1).getImm(); 737 ITBlock.setITState(Firstcond, Mask); 738 } 739 740 return result; 741 } 742 743 // We want to read exactly 4 bytes of data. 744 if (Region.readBytes(Address, 4, bytes) == -1) { 745 Size = 0; 746 return MCDisassembler::Fail; 747 } 748 749 uint32_t insn32 = (bytes[3] << 8) | 750 (bytes[2] << 0) | 751 (bytes[1] << 24) | 752 (bytes[0] << 16); 753 MI.clear(); 754 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 755 this, STI); 756 if (result != MCDisassembler::Fail) { 757 Size = 4; 758 bool InITBlock = ITBlock.instrInITBlock(); 759 Check(result, AddThumbPredicate(MI)); 760 AddThumb1SBit(MI, InITBlock); 761 return result; 762 } 763 764 MI.clear(); 765 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 766 this, STI); 767 if (result != MCDisassembler::Fail) { 768 Size = 4; 769 Check(result, AddThumbPredicate(MI)); 770 return result; 771 } 772 773 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 774 MI.clear(); 775 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 776 if (result != MCDisassembler::Fail) { 777 Size = 4; 778 UpdateThumbVFPPredicate(MI); 779 return result; 780 } 781 } 782 783 MI.clear(); 784 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI); 785 if (result != MCDisassembler::Fail) { 786 Size = 4; 787 return result; 788 } 789 790 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 791 MI.clear(); 792 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 793 this, STI); 794 if (result != MCDisassembler::Fail) { 795 Size = 4; 796 Check(result, AddThumbPredicate(MI)); 797 return result; 798 } 799 } 800 801 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 802 MI.clear(); 803 uint32_t NEONLdStInsn = insn32; 804 NEONLdStInsn &= 0xF0FFFFFF; 805 NEONLdStInsn |= 0x04000000; 806 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 807 Address, this, STI); 808 if (result != MCDisassembler::Fail) { 809 Size = 4; 810 Check(result, AddThumbPredicate(MI)); 811 return result; 812 } 813 } 814 815 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 816 MI.clear(); 817 uint32_t NEONDataInsn = insn32; 818 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 819 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 820 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 821 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 822 Address, this, STI); 823 if (result != MCDisassembler::Fail) { 824 Size = 4; 825 Check(result, AddThumbPredicate(MI)); 826 return result; 827 } 828 829 MI.clear(); 830 uint32_t NEONCryptoInsn = insn32; 831 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 832 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 833 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 834 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 835 Address, this, STI); 836 if (result != MCDisassembler::Fail) { 837 Size = 4; 838 return result; 839 } 840 841 MI.clear(); 842 uint32_t NEONv8Insn = insn32; 843 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 844 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 845 this, STI); 846 if (result != MCDisassembler::Fail) { 847 Size = 4; 848 return result; 849 } 850 } 851 852 MI.clear(); 853 Size = 0; 854 return MCDisassembler::Fail; 855 } 856 857 858 extern "C" void LLVMInitializeARMDisassembler() { 859 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 860 createARMDisassembler); 861 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 862 createThumbDisassembler); 863 } 864 865 static const uint16_t GPRDecoderTable[] = { 866 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 867 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 868 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 869 ARM::R12, ARM::SP, ARM::LR, ARM::PC 870 }; 871 872 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 873 uint64_t Address, const void *Decoder) { 874 if (RegNo > 15) 875 return MCDisassembler::Fail; 876 877 unsigned Register = GPRDecoderTable[RegNo]; 878 Inst.addOperand(MCOperand::CreateReg(Register)); 879 return MCDisassembler::Success; 880 } 881 882 static DecodeStatus 883 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 884 uint64_t Address, const void *Decoder) { 885 DecodeStatus S = MCDisassembler::Success; 886 887 if (RegNo == 15) 888 S = MCDisassembler::SoftFail; 889 890 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 891 892 return S; 893 } 894 895 static DecodeStatus 896 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 897 uint64_t Address, const void *Decoder) { 898 DecodeStatus S = MCDisassembler::Success; 899 900 if (RegNo == 15) 901 { 902 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 903 return MCDisassembler::Success; 904 } 905 906 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 907 return S; 908 } 909 910 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 911 uint64_t Address, const void *Decoder) { 912 if (RegNo > 7) 913 return MCDisassembler::Fail; 914 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 915 } 916 917 static const uint16_t GPRPairDecoderTable[] = { 918 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 919 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 920 }; 921 922 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 923 uint64_t Address, const void *Decoder) { 924 DecodeStatus S = MCDisassembler::Success; 925 926 if (RegNo > 13) 927 return MCDisassembler::Fail; 928 929 if ((RegNo & 1) || RegNo == 0xe) 930 S = MCDisassembler::SoftFail; 931 932 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 933 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 934 return S; 935 } 936 937 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 938 uint64_t Address, const void *Decoder) { 939 unsigned Register = 0; 940 switch (RegNo) { 941 case 0: 942 Register = ARM::R0; 943 break; 944 case 1: 945 Register = ARM::R1; 946 break; 947 case 2: 948 Register = ARM::R2; 949 break; 950 case 3: 951 Register = ARM::R3; 952 break; 953 case 9: 954 Register = ARM::R9; 955 break; 956 case 12: 957 Register = ARM::R12; 958 break; 959 default: 960 return MCDisassembler::Fail; 961 } 962 963 Inst.addOperand(MCOperand::CreateReg(Register)); 964 return MCDisassembler::Success; 965 } 966 967 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 968 uint64_t Address, const void *Decoder) { 969 DecodeStatus S = MCDisassembler::Success; 970 if (RegNo == 13 || RegNo == 15) 971 S = MCDisassembler::SoftFail; 972 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 973 return S; 974 } 975 976 static const uint16_t SPRDecoderTable[] = { 977 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 978 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 979 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 980 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 981 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 982 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 983 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 984 ARM::S28, ARM::S29, ARM::S30, ARM::S31 985 }; 986 987 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 988 uint64_t Address, const void *Decoder) { 989 if (RegNo > 31) 990 return MCDisassembler::Fail; 991 992 unsigned Register = SPRDecoderTable[RegNo]; 993 Inst.addOperand(MCOperand::CreateReg(Register)); 994 return MCDisassembler::Success; 995 } 996 997 static const uint16_t DPRDecoderTable[] = { 998 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 999 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1000 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1001 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1002 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1003 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1004 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1005 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1006 }; 1007 1008 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1009 uint64_t Address, const void *Decoder) { 1010 if (RegNo > 31) 1011 return MCDisassembler::Fail; 1012 1013 unsigned Register = DPRDecoderTable[RegNo]; 1014 Inst.addOperand(MCOperand::CreateReg(Register)); 1015 return MCDisassembler::Success; 1016 } 1017 1018 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1019 uint64_t Address, const void *Decoder) { 1020 if (RegNo > 7) 1021 return MCDisassembler::Fail; 1022 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1023 } 1024 1025 static DecodeStatus 1026 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1027 uint64_t Address, const void *Decoder) { 1028 if (RegNo > 15) 1029 return MCDisassembler::Fail; 1030 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1031 } 1032 1033 static const uint16_t QPRDecoderTable[] = { 1034 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1035 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1036 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1037 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1038 }; 1039 1040 1041 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1042 uint64_t Address, const void *Decoder) { 1043 if (RegNo > 31 || (RegNo & 1) != 0) 1044 return MCDisassembler::Fail; 1045 RegNo >>= 1; 1046 1047 unsigned Register = QPRDecoderTable[RegNo]; 1048 Inst.addOperand(MCOperand::CreateReg(Register)); 1049 return MCDisassembler::Success; 1050 } 1051 1052 static const uint16_t DPairDecoderTable[] = { 1053 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1054 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1055 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1056 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1057 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1058 ARM::Q15 1059 }; 1060 1061 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1062 uint64_t Address, const void *Decoder) { 1063 if (RegNo > 30) 1064 return MCDisassembler::Fail; 1065 1066 unsigned Register = DPairDecoderTable[RegNo]; 1067 Inst.addOperand(MCOperand::CreateReg(Register)); 1068 return MCDisassembler::Success; 1069 } 1070 1071 static const uint16_t DPairSpacedDecoderTable[] = { 1072 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1073 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1074 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1075 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1076 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1077 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1078 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1079 ARM::D28_D30, ARM::D29_D31 1080 }; 1081 1082 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1083 unsigned RegNo, 1084 uint64_t Address, 1085 const void *Decoder) { 1086 if (RegNo > 29) 1087 return MCDisassembler::Fail; 1088 1089 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1090 Inst.addOperand(MCOperand::CreateReg(Register)); 1091 return MCDisassembler::Success; 1092 } 1093 1094 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1095 uint64_t Address, const void *Decoder) { 1096 if (Val == 0xF) return MCDisassembler::Fail; 1097 // AL predicate is not allowed on Thumb1 branches. 1098 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1099 return MCDisassembler::Fail; 1100 Inst.addOperand(MCOperand::CreateImm(Val)); 1101 if (Val == ARMCC::AL) { 1102 Inst.addOperand(MCOperand::CreateReg(0)); 1103 } else 1104 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1105 return MCDisassembler::Success; 1106 } 1107 1108 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1109 uint64_t Address, const void *Decoder) { 1110 if (Val) 1111 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1112 else 1113 Inst.addOperand(MCOperand::CreateReg(0)); 1114 return MCDisassembler::Success; 1115 } 1116 1117 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1118 uint64_t Address, const void *Decoder) { 1119 uint32_t imm = Val & 0xFF; 1120 uint32_t rot = (Val & 0xF00) >> 7; 1121 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1122 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1123 return MCDisassembler::Success; 1124 } 1125 1126 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1127 uint64_t Address, const void *Decoder) { 1128 DecodeStatus S = MCDisassembler::Success; 1129 1130 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1131 unsigned type = fieldFromInstruction(Val, 5, 2); 1132 unsigned imm = fieldFromInstruction(Val, 7, 5); 1133 1134 // Register-immediate 1135 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1136 return MCDisassembler::Fail; 1137 1138 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1139 switch (type) { 1140 case 0: 1141 Shift = ARM_AM::lsl; 1142 break; 1143 case 1: 1144 Shift = ARM_AM::lsr; 1145 break; 1146 case 2: 1147 Shift = ARM_AM::asr; 1148 break; 1149 case 3: 1150 Shift = ARM_AM::ror; 1151 break; 1152 } 1153 1154 if (Shift == ARM_AM::ror && imm == 0) 1155 Shift = ARM_AM::rrx; 1156 1157 unsigned Op = Shift | (imm << 3); 1158 Inst.addOperand(MCOperand::CreateImm(Op)); 1159 1160 return S; 1161 } 1162 1163 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1164 uint64_t Address, const void *Decoder) { 1165 DecodeStatus S = MCDisassembler::Success; 1166 1167 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1168 unsigned type = fieldFromInstruction(Val, 5, 2); 1169 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1170 1171 // Register-register 1172 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1173 return MCDisassembler::Fail; 1174 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1175 return MCDisassembler::Fail; 1176 1177 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1178 switch (type) { 1179 case 0: 1180 Shift = ARM_AM::lsl; 1181 break; 1182 case 1: 1183 Shift = ARM_AM::lsr; 1184 break; 1185 case 2: 1186 Shift = ARM_AM::asr; 1187 break; 1188 case 3: 1189 Shift = ARM_AM::ror; 1190 break; 1191 } 1192 1193 Inst.addOperand(MCOperand::CreateImm(Shift)); 1194 1195 return S; 1196 } 1197 1198 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1199 uint64_t Address, const void *Decoder) { 1200 DecodeStatus S = MCDisassembler::Success; 1201 1202 bool NeedDisjointWriteback = false; 1203 unsigned WritebackReg = 0; 1204 switch (Inst.getOpcode()) { 1205 default: 1206 break; 1207 case ARM::LDMIA_UPD: 1208 case ARM::LDMDB_UPD: 1209 case ARM::LDMIB_UPD: 1210 case ARM::LDMDA_UPD: 1211 case ARM::t2LDMIA_UPD: 1212 case ARM::t2LDMDB_UPD: 1213 case ARM::t2STMIA_UPD: 1214 case ARM::t2STMDB_UPD: 1215 NeedDisjointWriteback = true; 1216 WritebackReg = Inst.getOperand(0).getReg(); 1217 break; 1218 } 1219 1220 // Empty register lists are not allowed. 1221 if (Val == 0) return MCDisassembler::Fail; 1222 for (unsigned i = 0; i < 16; ++i) { 1223 if (Val & (1 << i)) { 1224 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1225 return MCDisassembler::Fail; 1226 // Writeback not allowed if Rn is in the target list. 1227 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1228 Check(S, MCDisassembler::SoftFail); 1229 } 1230 } 1231 1232 return S; 1233 } 1234 1235 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1236 uint64_t Address, const void *Decoder) { 1237 DecodeStatus S = MCDisassembler::Success; 1238 1239 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1240 unsigned regs = fieldFromInstruction(Val, 0, 8); 1241 1242 // In case of unpredictable encoding, tweak the operands. 1243 if (regs == 0 || (Vd + regs) > 32) { 1244 regs = Vd + regs > 32 ? 32 - Vd : regs; 1245 regs = std::max( 1u, regs); 1246 S = MCDisassembler::SoftFail; 1247 } 1248 1249 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1250 return MCDisassembler::Fail; 1251 for (unsigned i = 0; i < (regs - 1); ++i) { 1252 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1253 return MCDisassembler::Fail; 1254 } 1255 1256 return S; 1257 } 1258 1259 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1260 uint64_t Address, const void *Decoder) { 1261 DecodeStatus S = MCDisassembler::Success; 1262 1263 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1264 unsigned regs = fieldFromInstruction(Val, 1, 7); 1265 1266 // In case of unpredictable encoding, tweak the operands. 1267 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1268 regs = Vd + regs > 32 ? 32 - Vd : regs; 1269 regs = std::max( 1u, regs); 1270 regs = std::min(16u, regs); 1271 S = MCDisassembler::SoftFail; 1272 } 1273 1274 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1275 return MCDisassembler::Fail; 1276 for (unsigned i = 0; i < (regs - 1); ++i) { 1277 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1278 return MCDisassembler::Fail; 1279 } 1280 1281 return S; 1282 } 1283 1284 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1285 uint64_t Address, const void *Decoder) { 1286 // This operand encodes a mask of contiguous zeros between a specified MSB 1287 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1288 // the mask of all bits LSB-and-lower, and then xor them to create 1289 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1290 // create the final mask. 1291 unsigned msb = fieldFromInstruction(Val, 5, 5); 1292 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1293 1294 DecodeStatus S = MCDisassembler::Success; 1295 if (lsb > msb) { 1296 Check(S, MCDisassembler::SoftFail); 1297 // The check above will cause the warning for the "potentially undefined 1298 // instruction encoding" but we can't build a bad MCOperand value here 1299 // with a lsb > msb or else printing the MCInst will cause a crash. 1300 lsb = msb; 1301 } 1302 1303 uint32_t msb_mask = 0xFFFFFFFF; 1304 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1305 uint32_t lsb_mask = (1U << lsb) - 1; 1306 1307 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1308 return S; 1309 } 1310 1311 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1312 uint64_t Address, const void *Decoder) { 1313 DecodeStatus S = MCDisassembler::Success; 1314 1315 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1316 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1317 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1318 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1319 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1320 unsigned U = fieldFromInstruction(Insn, 23, 1); 1321 1322 switch (Inst.getOpcode()) { 1323 case ARM::LDC_OFFSET: 1324 case ARM::LDC_PRE: 1325 case ARM::LDC_POST: 1326 case ARM::LDC_OPTION: 1327 case ARM::LDCL_OFFSET: 1328 case ARM::LDCL_PRE: 1329 case ARM::LDCL_POST: 1330 case ARM::LDCL_OPTION: 1331 case ARM::STC_OFFSET: 1332 case ARM::STC_PRE: 1333 case ARM::STC_POST: 1334 case ARM::STC_OPTION: 1335 case ARM::STCL_OFFSET: 1336 case ARM::STCL_PRE: 1337 case ARM::STCL_POST: 1338 case ARM::STCL_OPTION: 1339 case ARM::t2LDC_OFFSET: 1340 case ARM::t2LDC_PRE: 1341 case ARM::t2LDC_POST: 1342 case ARM::t2LDC_OPTION: 1343 case ARM::t2LDCL_OFFSET: 1344 case ARM::t2LDCL_PRE: 1345 case ARM::t2LDCL_POST: 1346 case ARM::t2LDCL_OPTION: 1347 case ARM::t2STC_OFFSET: 1348 case ARM::t2STC_PRE: 1349 case ARM::t2STC_POST: 1350 case ARM::t2STC_OPTION: 1351 case ARM::t2STCL_OFFSET: 1352 case ARM::t2STCL_PRE: 1353 case ARM::t2STCL_POST: 1354 case ARM::t2STCL_OPTION: 1355 if (coproc == 0xA || coproc == 0xB) 1356 return MCDisassembler::Fail; 1357 break; 1358 default: 1359 break; 1360 } 1361 1362 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 1363 .getFeatureBits(); 1364 if ((featureBits & ARM::HasV8Ops) && (coproc != 14)) 1365 return MCDisassembler::Fail; 1366 1367 Inst.addOperand(MCOperand::CreateImm(coproc)); 1368 Inst.addOperand(MCOperand::CreateImm(CRd)); 1369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1370 return MCDisassembler::Fail; 1371 1372 switch (Inst.getOpcode()) { 1373 case ARM::t2LDC2_OFFSET: 1374 case ARM::t2LDC2L_OFFSET: 1375 case ARM::t2LDC2_PRE: 1376 case ARM::t2LDC2L_PRE: 1377 case ARM::t2STC2_OFFSET: 1378 case ARM::t2STC2L_OFFSET: 1379 case ARM::t2STC2_PRE: 1380 case ARM::t2STC2L_PRE: 1381 case ARM::LDC2_OFFSET: 1382 case ARM::LDC2L_OFFSET: 1383 case ARM::LDC2_PRE: 1384 case ARM::LDC2L_PRE: 1385 case ARM::STC2_OFFSET: 1386 case ARM::STC2L_OFFSET: 1387 case ARM::STC2_PRE: 1388 case ARM::STC2L_PRE: 1389 case ARM::t2LDC_OFFSET: 1390 case ARM::t2LDCL_OFFSET: 1391 case ARM::t2LDC_PRE: 1392 case ARM::t2LDCL_PRE: 1393 case ARM::t2STC_OFFSET: 1394 case ARM::t2STCL_OFFSET: 1395 case ARM::t2STC_PRE: 1396 case ARM::t2STCL_PRE: 1397 case ARM::LDC_OFFSET: 1398 case ARM::LDCL_OFFSET: 1399 case ARM::LDC_PRE: 1400 case ARM::LDCL_PRE: 1401 case ARM::STC_OFFSET: 1402 case ARM::STCL_OFFSET: 1403 case ARM::STC_PRE: 1404 case ARM::STCL_PRE: 1405 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1406 Inst.addOperand(MCOperand::CreateImm(imm)); 1407 break; 1408 case ARM::t2LDC2_POST: 1409 case ARM::t2LDC2L_POST: 1410 case ARM::t2STC2_POST: 1411 case ARM::t2STC2L_POST: 1412 case ARM::LDC2_POST: 1413 case ARM::LDC2L_POST: 1414 case ARM::STC2_POST: 1415 case ARM::STC2L_POST: 1416 case ARM::t2LDC_POST: 1417 case ARM::t2LDCL_POST: 1418 case ARM::t2STC_POST: 1419 case ARM::t2STCL_POST: 1420 case ARM::LDC_POST: 1421 case ARM::LDCL_POST: 1422 case ARM::STC_POST: 1423 case ARM::STCL_POST: 1424 imm |= U << 8; 1425 // fall through. 1426 default: 1427 // The 'option' variant doesn't encode 'U' in the immediate since 1428 // the immediate is unsigned [0,255]. 1429 Inst.addOperand(MCOperand::CreateImm(imm)); 1430 break; 1431 } 1432 1433 switch (Inst.getOpcode()) { 1434 case ARM::LDC_OFFSET: 1435 case ARM::LDC_PRE: 1436 case ARM::LDC_POST: 1437 case ARM::LDC_OPTION: 1438 case ARM::LDCL_OFFSET: 1439 case ARM::LDCL_PRE: 1440 case ARM::LDCL_POST: 1441 case ARM::LDCL_OPTION: 1442 case ARM::STC_OFFSET: 1443 case ARM::STC_PRE: 1444 case ARM::STC_POST: 1445 case ARM::STC_OPTION: 1446 case ARM::STCL_OFFSET: 1447 case ARM::STCL_PRE: 1448 case ARM::STCL_POST: 1449 case ARM::STCL_OPTION: 1450 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1451 return MCDisassembler::Fail; 1452 break; 1453 default: 1454 break; 1455 } 1456 1457 return S; 1458 } 1459 1460 static DecodeStatus 1461 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1462 uint64_t Address, const void *Decoder) { 1463 DecodeStatus S = MCDisassembler::Success; 1464 1465 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1466 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1467 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1468 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1469 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1470 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1471 unsigned P = fieldFromInstruction(Insn, 24, 1); 1472 unsigned W = fieldFromInstruction(Insn, 21, 1); 1473 1474 // On stores, the writeback operand precedes Rt. 1475 switch (Inst.getOpcode()) { 1476 case ARM::STR_POST_IMM: 1477 case ARM::STR_POST_REG: 1478 case ARM::STRB_POST_IMM: 1479 case ARM::STRB_POST_REG: 1480 case ARM::STRT_POST_REG: 1481 case ARM::STRT_POST_IMM: 1482 case ARM::STRBT_POST_REG: 1483 case ARM::STRBT_POST_IMM: 1484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1485 return MCDisassembler::Fail; 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1492 return MCDisassembler::Fail; 1493 1494 // On loads, the writeback operand comes after Rt. 1495 switch (Inst.getOpcode()) { 1496 case ARM::LDR_POST_IMM: 1497 case ARM::LDR_POST_REG: 1498 case ARM::LDRB_POST_IMM: 1499 case ARM::LDRB_POST_REG: 1500 case ARM::LDRBT_POST_REG: 1501 case ARM::LDRBT_POST_IMM: 1502 case ARM::LDRT_POST_REG: 1503 case ARM::LDRT_POST_IMM: 1504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1505 return MCDisassembler::Fail; 1506 break; 1507 default: 1508 break; 1509 } 1510 1511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1512 return MCDisassembler::Fail; 1513 1514 ARM_AM::AddrOpc Op = ARM_AM::add; 1515 if (!fieldFromInstruction(Insn, 23, 1)) 1516 Op = ARM_AM::sub; 1517 1518 bool writeback = (P == 0) || (W == 1); 1519 unsigned idx_mode = 0; 1520 if (P && writeback) 1521 idx_mode = ARMII::IndexModePre; 1522 else if (!P && writeback) 1523 idx_mode = ARMII::IndexModePost; 1524 1525 if (writeback && (Rn == 15 || Rn == Rt)) 1526 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1527 1528 if (reg) { 1529 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1530 return MCDisassembler::Fail; 1531 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1532 switch( fieldFromInstruction(Insn, 5, 2)) { 1533 case 0: 1534 Opc = ARM_AM::lsl; 1535 break; 1536 case 1: 1537 Opc = ARM_AM::lsr; 1538 break; 1539 case 2: 1540 Opc = ARM_AM::asr; 1541 break; 1542 case 3: 1543 Opc = ARM_AM::ror; 1544 break; 1545 default: 1546 return MCDisassembler::Fail; 1547 } 1548 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1549 if (Opc == ARM_AM::ror && amt == 0) 1550 Opc = ARM_AM::rrx; 1551 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1552 1553 Inst.addOperand(MCOperand::CreateImm(imm)); 1554 } else { 1555 Inst.addOperand(MCOperand::CreateReg(0)); 1556 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1557 Inst.addOperand(MCOperand::CreateImm(tmp)); 1558 } 1559 1560 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1561 return MCDisassembler::Fail; 1562 1563 return S; 1564 } 1565 1566 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1567 uint64_t Address, const void *Decoder) { 1568 DecodeStatus S = MCDisassembler::Success; 1569 1570 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1571 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1572 unsigned type = fieldFromInstruction(Val, 5, 2); 1573 unsigned imm = fieldFromInstruction(Val, 7, 5); 1574 unsigned U = fieldFromInstruction(Val, 12, 1); 1575 1576 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1577 switch (type) { 1578 case 0: 1579 ShOp = ARM_AM::lsl; 1580 break; 1581 case 1: 1582 ShOp = ARM_AM::lsr; 1583 break; 1584 case 2: 1585 ShOp = ARM_AM::asr; 1586 break; 1587 case 3: 1588 ShOp = ARM_AM::ror; 1589 break; 1590 } 1591 1592 if (ShOp == ARM_AM::ror && imm == 0) 1593 ShOp = ARM_AM::rrx; 1594 1595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1596 return MCDisassembler::Fail; 1597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1598 return MCDisassembler::Fail; 1599 unsigned shift; 1600 if (U) 1601 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1602 else 1603 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1604 Inst.addOperand(MCOperand::CreateImm(shift)); 1605 1606 return S; 1607 } 1608 1609 static DecodeStatus 1610 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1611 uint64_t Address, const void *Decoder) { 1612 DecodeStatus S = MCDisassembler::Success; 1613 1614 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1615 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1616 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1617 unsigned type = fieldFromInstruction(Insn, 22, 1); 1618 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1619 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1620 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1621 unsigned W = fieldFromInstruction(Insn, 21, 1); 1622 unsigned P = fieldFromInstruction(Insn, 24, 1); 1623 unsigned Rt2 = Rt + 1; 1624 1625 bool writeback = (W == 1) | (P == 0); 1626 1627 // For {LD,ST}RD, Rt must be even, else undefined. 1628 switch (Inst.getOpcode()) { 1629 case ARM::STRD: 1630 case ARM::STRD_PRE: 1631 case ARM::STRD_POST: 1632 case ARM::LDRD: 1633 case ARM::LDRD_PRE: 1634 case ARM::LDRD_POST: 1635 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1636 break; 1637 default: 1638 break; 1639 } 1640 switch (Inst.getOpcode()) { 1641 case ARM::STRD: 1642 case ARM::STRD_PRE: 1643 case ARM::STRD_POST: 1644 if (P == 0 && W == 1) 1645 S = MCDisassembler::SoftFail; 1646 1647 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1648 S = MCDisassembler::SoftFail; 1649 if (type && Rm == 15) 1650 S = MCDisassembler::SoftFail; 1651 if (Rt2 == 15) 1652 S = MCDisassembler::SoftFail; 1653 if (!type && fieldFromInstruction(Insn, 8, 4)) 1654 S = MCDisassembler::SoftFail; 1655 break; 1656 case ARM::STRH: 1657 case ARM::STRH_PRE: 1658 case ARM::STRH_POST: 1659 if (Rt == 15) 1660 S = MCDisassembler::SoftFail; 1661 if (writeback && (Rn == 15 || Rn == Rt)) 1662 S = MCDisassembler::SoftFail; 1663 if (!type && Rm == 15) 1664 S = MCDisassembler::SoftFail; 1665 break; 1666 case ARM::LDRD: 1667 case ARM::LDRD_PRE: 1668 case ARM::LDRD_POST: 1669 if (type && Rn == 15){ 1670 if (Rt2 == 15) 1671 S = MCDisassembler::SoftFail; 1672 break; 1673 } 1674 if (P == 0 && W == 1) 1675 S = MCDisassembler::SoftFail; 1676 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1677 S = MCDisassembler::SoftFail; 1678 if (!type && writeback && Rn == 15) 1679 S = MCDisassembler::SoftFail; 1680 if (writeback && (Rn == Rt || Rn == Rt2)) 1681 S = MCDisassembler::SoftFail; 1682 break; 1683 case ARM::LDRH: 1684 case ARM::LDRH_PRE: 1685 case ARM::LDRH_POST: 1686 if (type && Rn == 15){ 1687 if (Rt == 15) 1688 S = MCDisassembler::SoftFail; 1689 break; 1690 } 1691 if (Rt == 15) 1692 S = MCDisassembler::SoftFail; 1693 if (!type && Rm == 15) 1694 S = MCDisassembler::SoftFail; 1695 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1696 S = MCDisassembler::SoftFail; 1697 break; 1698 case ARM::LDRSH: 1699 case ARM::LDRSH_PRE: 1700 case ARM::LDRSH_POST: 1701 case ARM::LDRSB: 1702 case ARM::LDRSB_PRE: 1703 case ARM::LDRSB_POST: 1704 if (type && Rn == 15){ 1705 if (Rt == 15) 1706 S = MCDisassembler::SoftFail; 1707 break; 1708 } 1709 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1710 S = MCDisassembler::SoftFail; 1711 if (!type && (Rt == 15 || Rm == 15)) 1712 S = MCDisassembler::SoftFail; 1713 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1714 S = MCDisassembler::SoftFail; 1715 break; 1716 default: 1717 break; 1718 } 1719 1720 if (writeback) { // Writeback 1721 if (P) 1722 U |= ARMII::IndexModePre << 9; 1723 else 1724 U |= ARMII::IndexModePost << 9; 1725 1726 // On stores, the writeback operand precedes Rt. 1727 switch (Inst.getOpcode()) { 1728 case ARM::STRD: 1729 case ARM::STRD_PRE: 1730 case ARM::STRD_POST: 1731 case ARM::STRH: 1732 case ARM::STRH_PRE: 1733 case ARM::STRH_POST: 1734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1735 return MCDisassembler::Fail; 1736 break; 1737 default: 1738 break; 1739 } 1740 } 1741 1742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1743 return MCDisassembler::Fail; 1744 switch (Inst.getOpcode()) { 1745 case ARM::STRD: 1746 case ARM::STRD_PRE: 1747 case ARM::STRD_POST: 1748 case ARM::LDRD: 1749 case ARM::LDRD_PRE: 1750 case ARM::LDRD_POST: 1751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1752 return MCDisassembler::Fail; 1753 break; 1754 default: 1755 break; 1756 } 1757 1758 if (writeback) { 1759 // On loads, the writeback operand comes after Rt. 1760 switch (Inst.getOpcode()) { 1761 case ARM::LDRD: 1762 case ARM::LDRD_PRE: 1763 case ARM::LDRD_POST: 1764 case ARM::LDRH: 1765 case ARM::LDRH_PRE: 1766 case ARM::LDRH_POST: 1767 case ARM::LDRSH: 1768 case ARM::LDRSH_PRE: 1769 case ARM::LDRSH_POST: 1770 case ARM::LDRSB: 1771 case ARM::LDRSB_PRE: 1772 case ARM::LDRSB_POST: 1773 case ARM::LDRHTr: 1774 case ARM::LDRSBTr: 1775 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1776 return MCDisassembler::Fail; 1777 break; 1778 default: 1779 break; 1780 } 1781 } 1782 1783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1784 return MCDisassembler::Fail; 1785 1786 if (type) { 1787 Inst.addOperand(MCOperand::CreateReg(0)); 1788 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1789 } else { 1790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1791 return MCDisassembler::Fail; 1792 Inst.addOperand(MCOperand::CreateImm(U)); 1793 } 1794 1795 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1796 return MCDisassembler::Fail; 1797 1798 return S; 1799 } 1800 1801 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1802 uint64_t Address, const void *Decoder) { 1803 DecodeStatus S = MCDisassembler::Success; 1804 1805 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1806 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1807 1808 switch (mode) { 1809 case 0: 1810 mode = ARM_AM::da; 1811 break; 1812 case 1: 1813 mode = ARM_AM::ia; 1814 break; 1815 case 2: 1816 mode = ARM_AM::db; 1817 break; 1818 case 3: 1819 mode = ARM_AM::ib; 1820 break; 1821 } 1822 1823 Inst.addOperand(MCOperand::CreateImm(mode)); 1824 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1825 return MCDisassembler::Fail; 1826 1827 return S; 1828 } 1829 1830 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1831 uint64_t Address, const void *Decoder) { 1832 DecodeStatus S = MCDisassembler::Success; 1833 1834 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1835 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1836 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1837 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1838 1839 if (pred == 0xF) 1840 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1841 1842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1843 return MCDisassembler::Fail; 1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1845 return MCDisassembler::Fail; 1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1847 return MCDisassembler::Fail; 1848 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1849 return MCDisassembler::Fail; 1850 return S; 1851 } 1852 1853 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1854 unsigned Insn, 1855 uint64_t Address, const void *Decoder) { 1856 DecodeStatus S = MCDisassembler::Success; 1857 1858 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1859 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1860 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1861 1862 if (pred == 0xF) { 1863 // Ambiguous with RFE and SRS 1864 switch (Inst.getOpcode()) { 1865 case ARM::LDMDA: 1866 Inst.setOpcode(ARM::RFEDA); 1867 break; 1868 case ARM::LDMDA_UPD: 1869 Inst.setOpcode(ARM::RFEDA_UPD); 1870 break; 1871 case ARM::LDMDB: 1872 Inst.setOpcode(ARM::RFEDB); 1873 break; 1874 case ARM::LDMDB_UPD: 1875 Inst.setOpcode(ARM::RFEDB_UPD); 1876 break; 1877 case ARM::LDMIA: 1878 Inst.setOpcode(ARM::RFEIA); 1879 break; 1880 case ARM::LDMIA_UPD: 1881 Inst.setOpcode(ARM::RFEIA_UPD); 1882 break; 1883 case ARM::LDMIB: 1884 Inst.setOpcode(ARM::RFEIB); 1885 break; 1886 case ARM::LDMIB_UPD: 1887 Inst.setOpcode(ARM::RFEIB_UPD); 1888 break; 1889 case ARM::STMDA: 1890 Inst.setOpcode(ARM::SRSDA); 1891 break; 1892 case ARM::STMDA_UPD: 1893 Inst.setOpcode(ARM::SRSDA_UPD); 1894 break; 1895 case ARM::STMDB: 1896 Inst.setOpcode(ARM::SRSDB); 1897 break; 1898 case ARM::STMDB_UPD: 1899 Inst.setOpcode(ARM::SRSDB_UPD); 1900 break; 1901 case ARM::STMIA: 1902 Inst.setOpcode(ARM::SRSIA); 1903 break; 1904 case ARM::STMIA_UPD: 1905 Inst.setOpcode(ARM::SRSIA_UPD); 1906 break; 1907 case ARM::STMIB: 1908 Inst.setOpcode(ARM::SRSIB); 1909 break; 1910 case ARM::STMIB_UPD: 1911 Inst.setOpcode(ARM::SRSIB_UPD); 1912 break; 1913 default: 1914 return MCDisassembler::Fail; 1915 } 1916 1917 // For stores (which become SRS's, the only operand is the mode. 1918 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1919 // Check SRS encoding constraints 1920 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1921 fieldFromInstruction(Insn, 20, 1) == 0)) 1922 return MCDisassembler::Fail; 1923 1924 Inst.addOperand( 1925 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1926 return S; 1927 } 1928 1929 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1930 } 1931 1932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1933 return MCDisassembler::Fail; 1934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1935 return MCDisassembler::Fail; // Tied 1936 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1937 return MCDisassembler::Fail; 1938 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1939 return MCDisassembler::Fail; 1940 1941 return S; 1942 } 1943 1944 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1945 uint64_t Address, const void *Decoder) { 1946 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1947 unsigned M = fieldFromInstruction(Insn, 17, 1); 1948 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1949 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1950 1951 DecodeStatus S = MCDisassembler::Success; 1952 1953 // This decoder is called from multiple location that do not check 1954 // the full encoding is valid before they do. 1955 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1956 fieldFromInstruction(Insn, 16, 1) != 0 || 1957 fieldFromInstruction(Insn, 20, 8) != 0x10) 1958 return MCDisassembler::Fail; 1959 1960 // imod == '01' --> UNPREDICTABLE 1961 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1962 // return failure here. The '01' imod value is unprintable, so there's 1963 // nothing useful we could do even if we returned UNPREDICTABLE. 1964 1965 if (imod == 1) return MCDisassembler::Fail; 1966 1967 if (imod && M) { 1968 Inst.setOpcode(ARM::CPS3p); 1969 Inst.addOperand(MCOperand::CreateImm(imod)); 1970 Inst.addOperand(MCOperand::CreateImm(iflags)); 1971 Inst.addOperand(MCOperand::CreateImm(mode)); 1972 } else if (imod && !M) { 1973 Inst.setOpcode(ARM::CPS2p); 1974 Inst.addOperand(MCOperand::CreateImm(imod)); 1975 Inst.addOperand(MCOperand::CreateImm(iflags)); 1976 if (mode) S = MCDisassembler::SoftFail; 1977 } else if (!imod && M) { 1978 Inst.setOpcode(ARM::CPS1p); 1979 Inst.addOperand(MCOperand::CreateImm(mode)); 1980 if (iflags) S = MCDisassembler::SoftFail; 1981 } else { 1982 // imod == '00' && M == '0' --> UNPREDICTABLE 1983 Inst.setOpcode(ARM::CPS1p); 1984 Inst.addOperand(MCOperand::CreateImm(mode)); 1985 S = MCDisassembler::SoftFail; 1986 } 1987 1988 return S; 1989 } 1990 1991 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 1992 uint64_t Address, const void *Decoder) { 1993 unsigned imod = fieldFromInstruction(Insn, 9, 2); 1994 unsigned M = fieldFromInstruction(Insn, 8, 1); 1995 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 1996 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1997 1998 DecodeStatus S = MCDisassembler::Success; 1999 2000 // imod == '01' --> UNPREDICTABLE 2001 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2002 // return failure here. The '01' imod value is unprintable, so there's 2003 // nothing useful we could do even if we returned UNPREDICTABLE. 2004 2005 if (imod == 1) return MCDisassembler::Fail; 2006 2007 if (imod && M) { 2008 Inst.setOpcode(ARM::t2CPS3p); 2009 Inst.addOperand(MCOperand::CreateImm(imod)); 2010 Inst.addOperand(MCOperand::CreateImm(iflags)); 2011 Inst.addOperand(MCOperand::CreateImm(mode)); 2012 } else if (imod && !M) { 2013 Inst.setOpcode(ARM::t2CPS2p); 2014 Inst.addOperand(MCOperand::CreateImm(imod)); 2015 Inst.addOperand(MCOperand::CreateImm(iflags)); 2016 if (mode) S = MCDisassembler::SoftFail; 2017 } else if (!imod && M) { 2018 Inst.setOpcode(ARM::t2CPS1p); 2019 Inst.addOperand(MCOperand::CreateImm(mode)); 2020 if (iflags) S = MCDisassembler::SoftFail; 2021 } else { 2022 // imod == '00' && M == '0' --> this is a HINT instruction 2023 int imm = fieldFromInstruction(Insn, 0, 8); 2024 // HINT are defined only for immediate in [0..4] 2025 if(imm > 4) return MCDisassembler::Fail; 2026 Inst.setOpcode(ARM::t2HINT); 2027 Inst.addOperand(MCOperand::CreateImm(imm)); 2028 } 2029 2030 return S; 2031 } 2032 2033 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2034 uint64_t Address, const void *Decoder) { 2035 DecodeStatus S = MCDisassembler::Success; 2036 2037 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2038 unsigned imm = 0; 2039 2040 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2041 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2042 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2043 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2044 2045 if (Inst.getOpcode() == ARM::t2MOVTi16) 2046 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2047 return MCDisassembler::Fail; 2048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2049 return MCDisassembler::Fail; 2050 2051 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2052 Inst.addOperand(MCOperand::CreateImm(imm)); 2053 2054 return S; 2055 } 2056 2057 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2058 uint64_t Address, const void *Decoder) { 2059 DecodeStatus S = MCDisassembler::Success; 2060 2061 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2062 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2063 unsigned imm = 0; 2064 2065 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2066 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2067 2068 if (Inst.getOpcode() == ARM::MOVTi16) 2069 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2070 return MCDisassembler::Fail; 2071 2072 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2073 return MCDisassembler::Fail; 2074 2075 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2076 Inst.addOperand(MCOperand::CreateImm(imm)); 2077 2078 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2079 return MCDisassembler::Fail; 2080 2081 return S; 2082 } 2083 2084 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2085 uint64_t Address, const void *Decoder) { 2086 DecodeStatus S = MCDisassembler::Success; 2087 2088 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2089 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2090 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2091 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2092 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2093 2094 if (pred == 0xF) 2095 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2096 2097 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2098 return MCDisassembler::Fail; 2099 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2100 return MCDisassembler::Fail; 2101 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2102 return MCDisassembler::Fail; 2103 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2104 return MCDisassembler::Fail; 2105 2106 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2107 return MCDisassembler::Fail; 2108 2109 return S; 2110 } 2111 2112 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2113 uint64_t Address, const void *Decoder) { 2114 DecodeStatus S = MCDisassembler::Success; 2115 2116 unsigned add = fieldFromInstruction(Val, 12, 1); 2117 unsigned imm = fieldFromInstruction(Val, 0, 12); 2118 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2119 2120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2121 return MCDisassembler::Fail; 2122 2123 if (!add) imm *= -1; 2124 if (imm == 0 && !add) imm = INT32_MIN; 2125 Inst.addOperand(MCOperand::CreateImm(imm)); 2126 if (Rn == 15) 2127 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2128 2129 return S; 2130 } 2131 2132 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2133 uint64_t Address, const void *Decoder) { 2134 DecodeStatus S = MCDisassembler::Success; 2135 2136 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2137 unsigned U = fieldFromInstruction(Val, 8, 1); 2138 unsigned imm = fieldFromInstruction(Val, 0, 8); 2139 2140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2141 return MCDisassembler::Fail; 2142 2143 if (U) 2144 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2145 else 2146 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2147 2148 return S; 2149 } 2150 2151 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2152 uint64_t Address, const void *Decoder) { 2153 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2154 } 2155 2156 static DecodeStatus 2157 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2158 uint64_t Address, const void *Decoder) { 2159 DecodeStatus Status = MCDisassembler::Success; 2160 2161 // Note the J1 and J2 values are from the encoded instruction. So here 2162 // change them to I1 and I2 values via as documented: 2163 // I1 = NOT(J1 EOR S); 2164 // I2 = NOT(J2 EOR S); 2165 // and build the imm32 with one trailing zero as documented: 2166 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2167 unsigned S = fieldFromInstruction(Insn, 26, 1); 2168 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2169 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2170 unsigned I1 = !(J1 ^ S); 2171 unsigned I2 = !(J2 ^ S); 2172 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2173 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2174 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2175 int imm32 = SignExtend32<25>(tmp << 1); 2176 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2177 true, 4, Inst, Decoder)) 2178 Inst.addOperand(MCOperand::CreateImm(imm32)); 2179 2180 return Status; 2181 } 2182 2183 static DecodeStatus 2184 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2185 uint64_t Address, const void *Decoder) { 2186 DecodeStatus S = MCDisassembler::Success; 2187 2188 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2189 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2190 2191 if (pred == 0xF) { 2192 Inst.setOpcode(ARM::BLXi); 2193 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2194 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2195 true, 4, Inst, Decoder)) 2196 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2197 return S; 2198 } 2199 2200 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2201 true, 4, Inst, Decoder)) 2202 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2203 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2204 return MCDisassembler::Fail; 2205 2206 return S; 2207 } 2208 2209 2210 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2211 uint64_t Address, const void *Decoder) { 2212 DecodeStatus S = MCDisassembler::Success; 2213 2214 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2215 unsigned align = fieldFromInstruction(Val, 4, 2); 2216 2217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2218 return MCDisassembler::Fail; 2219 if (!align) 2220 Inst.addOperand(MCOperand::CreateImm(0)); 2221 else 2222 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2223 2224 return S; 2225 } 2226 2227 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2228 uint64_t Address, const void *Decoder) { 2229 DecodeStatus S = MCDisassembler::Success; 2230 2231 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2232 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2233 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2234 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2235 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2236 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2237 2238 // First output register 2239 switch (Inst.getOpcode()) { 2240 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2241 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2242 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2243 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2244 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2245 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2246 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2247 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2248 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2249 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2250 return MCDisassembler::Fail; 2251 break; 2252 case ARM::VLD2b16: 2253 case ARM::VLD2b32: 2254 case ARM::VLD2b8: 2255 case ARM::VLD2b16wb_fixed: 2256 case ARM::VLD2b16wb_register: 2257 case ARM::VLD2b32wb_fixed: 2258 case ARM::VLD2b32wb_register: 2259 case ARM::VLD2b8wb_fixed: 2260 case ARM::VLD2b8wb_register: 2261 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2262 return MCDisassembler::Fail; 2263 break; 2264 default: 2265 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2266 return MCDisassembler::Fail; 2267 } 2268 2269 // Second output register 2270 switch (Inst.getOpcode()) { 2271 case ARM::VLD3d8: 2272 case ARM::VLD3d16: 2273 case ARM::VLD3d32: 2274 case ARM::VLD3d8_UPD: 2275 case ARM::VLD3d16_UPD: 2276 case ARM::VLD3d32_UPD: 2277 case ARM::VLD4d8: 2278 case ARM::VLD4d16: 2279 case ARM::VLD4d32: 2280 case ARM::VLD4d8_UPD: 2281 case ARM::VLD4d16_UPD: 2282 case ARM::VLD4d32_UPD: 2283 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2284 return MCDisassembler::Fail; 2285 break; 2286 case ARM::VLD3q8: 2287 case ARM::VLD3q16: 2288 case ARM::VLD3q32: 2289 case ARM::VLD3q8_UPD: 2290 case ARM::VLD3q16_UPD: 2291 case ARM::VLD3q32_UPD: 2292 case ARM::VLD4q8: 2293 case ARM::VLD4q16: 2294 case ARM::VLD4q32: 2295 case ARM::VLD4q8_UPD: 2296 case ARM::VLD4q16_UPD: 2297 case ARM::VLD4q32_UPD: 2298 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2299 return MCDisassembler::Fail; 2300 default: 2301 break; 2302 } 2303 2304 // Third output register 2305 switch(Inst.getOpcode()) { 2306 case ARM::VLD3d8: 2307 case ARM::VLD3d16: 2308 case ARM::VLD3d32: 2309 case ARM::VLD3d8_UPD: 2310 case ARM::VLD3d16_UPD: 2311 case ARM::VLD3d32_UPD: 2312 case ARM::VLD4d8: 2313 case ARM::VLD4d16: 2314 case ARM::VLD4d32: 2315 case ARM::VLD4d8_UPD: 2316 case ARM::VLD4d16_UPD: 2317 case ARM::VLD4d32_UPD: 2318 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2319 return MCDisassembler::Fail; 2320 break; 2321 case ARM::VLD3q8: 2322 case ARM::VLD3q16: 2323 case ARM::VLD3q32: 2324 case ARM::VLD3q8_UPD: 2325 case ARM::VLD3q16_UPD: 2326 case ARM::VLD3q32_UPD: 2327 case ARM::VLD4q8: 2328 case ARM::VLD4q16: 2329 case ARM::VLD4q32: 2330 case ARM::VLD4q8_UPD: 2331 case ARM::VLD4q16_UPD: 2332 case ARM::VLD4q32_UPD: 2333 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2334 return MCDisassembler::Fail; 2335 break; 2336 default: 2337 break; 2338 } 2339 2340 // Fourth output register 2341 switch (Inst.getOpcode()) { 2342 case ARM::VLD4d8: 2343 case ARM::VLD4d16: 2344 case ARM::VLD4d32: 2345 case ARM::VLD4d8_UPD: 2346 case ARM::VLD4d16_UPD: 2347 case ARM::VLD4d32_UPD: 2348 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2349 return MCDisassembler::Fail; 2350 break; 2351 case ARM::VLD4q8: 2352 case ARM::VLD4q16: 2353 case ARM::VLD4q32: 2354 case ARM::VLD4q8_UPD: 2355 case ARM::VLD4q16_UPD: 2356 case ARM::VLD4q32_UPD: 2357 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2358 return MCDisassembler::Fail; 2359 break; 2360 default: 2361 break; 2362 } 2363 2364 // Writeback operand 2365 switch (Inst.getOpcode()) { 2366 case ARM::VLD1d8wb_fixed: 2367 case ARM::VLD1d16wb_fixed: 2368 case ARM::VLD1d32wb_fixed: 2369 case ARM::VLD1d64wb_fixed: 2370 case ARM::VLD1d8wb_register: 2371 case ARM::VLD1d16wb_register: 2372 case ARM::VLD1d32wb_register: 2373 case ARM::VLD1d64wb_register: 2374 case ARM::VLD1q8wb_fixed: 2375 case ARM::VLD1q16wb_fixed: 2376 case ARM::VLD1q32wb_fixed: 2377 case ARM::VLD1q64wb_fixed: 2378 case ARM::VLD1q8wb_register: 2379 case ARM::VLD1q16wb_register: 2380 case ARM::VLD1q32wb_register: 2381 case ARM::VLD1q64wb_register: 2382 case ARM::VLD1d8Twb_fixed: 2383 case ARM::VLD1d8Twb_register: 2384 case ARM::VLD1d16Twb_fixed: 2385 case ARM::VLD1d16Twb_register: 2386 case ARM::VLD1d32Twb_fixed: 2387 case ARM::VLD1d32Twb_register: 2388 case ARM::VLD1d64Twb_fixed: 2389 case ARM::VLD1d64Twb_register: 2390 case ARM::VLD1d8Qwb_fixed: 2391 case ARM::VLD1d8Qwb_register: 2392 case ARM::VLD1d16Qwb_fixed: 2393 case ARM::VLD1d16Qwb_register: 2394 case ARM::VLD1d32Qwb_fixed: 2395 case ARM::VLD1d32Qwb_register: 2396 case ARM::VLD1d64Qwb_fixed: 2397 case ARM::VLD1d64Qwb_register: 2398 case ARM::VLD2d8wb_fixed: 2399 case ARM::VLD2d16wb_fixed: 2400 case ARM::VLD2d32wb_fixed: 2401 case ARM::VLD2q8wb_fixed: 2402 case ARM::VLD2q16wb_fixed: 2403 case ARM::VLD2q32wb_fixed: 2404 case ARM::VLD2d8wb_register: 2405 case ARM::VLD2d16wb_register: 2406 case ARM::VLD2d32wb_register: 2407 case ARM::VLD2q8wb_register: 2408 case ARM::VLD2q16wb_register: 2409 case ARM::VLD2q32wb_register: 2410 case ARM::VLD2b8wb_fixed: 2411 case ARM::VLD2b16wb_fixed: 2412 case ARM::VLD2b32wb_fixed: 2413 case ARM::VLD2b8wb_register: 2414 case ARM::VLD2b16wb_register: 2415 case ARM::VLD2b32wb_register: 2416 Inst.addOperand(MCOperand::CreateImm(0)); 2417 break; 2418 case ARM::VLD3d8_UPD: 2419 case ARM::VLD3d16_UPD: 2420 case ARM::VLD3d32_UPD: 2421 case ARM::VLD3q8_UPD: 2422 case ARM::VLD3q16_UPD: 2423 case ARM::VLD3q32_UPD: 2424 case ARM::VLD4d8_UPD: 2425 case ARM::VLD4d16_UPD: 2426 case ARM::VLD4d32_UPD: 2427 case ARM::VLD4q8_UPD: 2428 case ARM::VLD4q16_UPD: 2429 case ARM::VLD4q32_UPD: 2430 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2431 return MCDisassembler::Fail; 2432 break; 2433 default: 2434 break; 2435 } 2436 2437 // AddrMode6 Base (register+alignment) 2438 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2439 return MCDisassembler::Fail; 2440 2441 // AddrMode6 Offset (register) 2442 switch (Inst.getOpcode()) { 2443 default: 2444 // The below have been updated to have explicit am6offset split 2445 // between fixed and register offset. For those instructions not 2446 // yet updated, we need to add an additional reg0 operand for the 2447 // fixed variant. 2448 // 2449 // The fixed offset encodes as Rm == 0xd, so we check for that. 2450 if (Rm == 0xd) { 2451 Inst.addOperand(MCOperand::CreateReg(0)); 2452 break; 2453 } 2454 // Fall through to handle the register offset variant. 2455 case ARM::VLD1d8wb_fixed: 2456 case ARM::VLD1d16wb_fixed: 2457 case ARM::VLD1d32wb_fixed: 2458 case ARM::VLD1d64wb_fixed: 2459 case ARM::VLD1d8Twb_fixed: 2460 case ARM::VLD1d16Twb_fixed: 2461 case ARM::VLD1d32Twb_fixed: 2462 case ARM::VLD1d64Twb_fixed: 2463 case ARM::VLD1d8Qwb_fixed: 2464 case ARM::VLD1d16Qwb_fixed: 2465 case ARM::VLD1d32Qwb_fixed: 2466 case ARM::VLD1d64Qwb_fixed: 2467 case ARM::VLD1d8wb_register: 2468 case ARM::VLD1d16wb_register: 2469 case ARM::VLD1d32wb_register: 2470 case ARM::VLD1d64wb_register: 2471 case ARM::VLD1q8wb_fixed: 2472 case ARM::VLD1q16wb_fixed: 2473 case ARM::VLD1q32wb_fixed: 2474 case ARM::VLD1q64wb_fixed: 2475 case ARM::VLD1q8wb_register: 2476 case ARM::VLD1q16wb_register: 2477 case ARM::VLD1q32wb_register: 2478 case ARM::VLD1q64wb_register: 2479 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2480 // variant encodes Rm == 0xf. Anything else is a register offset post- 2481 // increment and we need to add the register operand to the instruction. 2482 if (Rm != 0xD && Rm != 0xF && 2483 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2484 return MCDisassembler::Fail; 2485 break; 2486 case ARM::VLD2d8wb_fixed: 2487 case ARM::VLD2d16wb_fixed: 2488 case ARM::VLD2d32wb_fixed: 2489 case ARM::VLD2b8wb_fixed: 2490 case ARM::VLD2b16wb_fixed: 2491 case ARM::VLD2b32wb_fixed: 2492 case ARM::VLD2q8wb_fixed: 2493 case ARM::VLD2q16wb_fixed: 2494 case ARM::VLD2q32wb_fixed: 2495 break; 2496 } 2497 2498 return S; 2499 } 2500 2501 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2502 uint64_t Address, const void *Decoder) { 2503 unsigned type = fieldFromInstruction(Insn, 8, 4); 2504 unsigned align = fieldFromInstruction(Insn, 4, 2); 2505 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2506 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2507 if (type == 10 && align == 3) return MCDisassembler::Fail; 2508 2509 unsigned load = fieldFromInstruction(Insn, 21, 1); 2510 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2511 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2512 } 2513 2514 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2515 uint64_t Address, const void *Decoder) { 2516 unsigned size = fieldFromInstruction(Insn, 6, 2); 2517 if (size == 3) return MCDisassembler::Fail; 2518 2519 unsigned type = fieldFromInstruction(Insn, 8, 4); 2520 unsigned align = fieldFromInstruction(Insn, 4, 2); 2521 if (type == 8 && align == 3) return MCDisassembler::Fail; 2522 if (type == 9 && align == 3) return MCDisassembler::Fail; 2523 2524 unsigned load = fieldFromInstruction(Insn, 21, 1); 2525 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2526 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2527 } 2528 2529 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2530 uint64_t Address, const void *Decoder) { 2531 unsigned size = fieldFromInstruction(Insn, 6, 2); 2532 if (size == 3) return MCDisassembler::Fail; 2533 2534 unsigned align = fieldFromInstruction(Insn, 4, 2); 2535 if (align & 2) return MCDisassembler::Fail; 2536 2537 unsigned load = fieldFromInstruction(Insn, 21, 1); 2538 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2539 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2540 } 2541 2542 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2543 uint64_t Address, const void *Decoder) { 2544 unsigned size = fieldFromInstruction(Insn, 6, 2); 2545 if (size == 3) return MCDisassembler::Fail; 2546 2547 unsigned load = fieldFromInstruction(Insn, 21, 1); 2548 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2549 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2550 } 2551 2552 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2553 uint64_t Address, const void *Decoder) { 2554 DecodeStatus S = MCDisassembler::Success; 2555 2556 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2557 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2558 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2559 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2560 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2561 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2562 2563 // Writeback Operand 2564 switch (Inst.getOpcode()) { 2565 case ARM::VST1d8wb_fixed: 2566 case ARM::VST1d16wb_fixed: 2567 case ARM::VST1d32wb_fixed: 2568 case ARM::VST1d64wb_fixed: 2569 case ARM::VST1d8wb_register: 2570 case ARM::VST1d16wb_register: 2571 case ARM::VST1d32wb_register: 2572 case ARM::VST1d64wb_register: 2573 case ARM::VST1q8wb_fixed: 2574 case ARM::VST1q16wb_fixed: 2575 case ARM::VST1q32wb_fixed: 2576 case ARM::VST1q64wb_fixed: 2577 case ARM::VST1q8wb_register: 2578 case ARM::VST1q16wb_register: 2579 case ARM::VST1q32wb_register: 2580 case ARM::VST1q64wb_register: 2581 case ARM::VST1d8Twb_fixed: 2582 case ARM::VST1d16Twb_fixed: 2583 case ARM::VST1d32Twb_fixed: 2584 case ARM::VST1d64Twb_fixed: 2585 case ARM::VST1d8Twb_register: 2586 case ARM::VST1d16Twb_register: 2587 case ARM::VST1d32Twb_register: 2588 case ARM::VST1d64Twb_register: 2589 case ARM::VST1d8Qwb_fixed: 2590 case ARM::VST1d16Qwb_fixed: 2591 case ARM::VST1d32Qwb_fixed: 2592 case ARM::VST1d64Qwb_fixed: 2593 case ARM::VST1d8Qwb_register: 2594 case ARM::VST1d16Qwb_register: 2595 case ARM::VST1d32Qwb_register: 2596 case ARM::VST1d64Qwb_register: 2597 case ARM::VST2d8wb_fixed: 2598 case ARM::VST2d16wb_fixed: 2599 case ARM::VST2d32wb_fixed: 2600 case ARM::VST2d8wb_register: 2601 case ARM::VST2d16wb_register: 2602 case ARM::VST2d32wb_register: 2603 case ARM::VST2q8wb_fixed: 2604 case ARM::VST2q16wb_fixed: 2605 case ARM::VST2q32wb_fixed: 2606 case ARM::VST2q8wb_register: 2607 case ARM::VST2q16wb_register: 2608 case ARM::VST2q32wb_register: 2609 case ARM::VST2b8wb_fixed: 2610 case ARM::VST2b16wb_fixed: 2611 case ARM::VST2b32wb_fixed: 2612 case ARM::VST2b8wb_register: 2613 case ARM::VST2b16wb_register: 2614 case ARM::VST2b32wb_register: 2615 if (Rm == 0xF) 2616 return MCDisassembler::Fail; 2617 Inst.addOperand(MCOperand::CreateImm(0)); 2618 break; 2619 case ARM::VST3d8_UPD: 2620 case ARM::VST3d16_UPD: 2621 case ARM::VST3d32_UPD: 2622 case ARM::VST3q8_UPD: 2623 case ARM::VST3q16_UPD: 2624 case ARM::VST3q32_UPD: 2625 case ARM::VST4d8_UPD: 2626 case ARM::VST4d16_UPD: 2627 case ARM::VST4d32_UPD: 2628 case ARM::VST4q8_UPD: 2629 case ARM::VST4q16_UPD: 2630 case ARM::VST4q32_UPD: 2631 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2632 return MCDisassembler::Fail; 2633 break; 2634 default: 2635 break; 2636 } 2637 2638 // AddrMode6 Base (register+alignment) 2639 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2640 return MCDisassembler::Fail; 2641 2642 // AddrMode6 Offset (register) 2643 switch (Inst.getOpcode()) { 2644 default: 2645 if (Rm == 0xD) 2646 Inst.addOperand(MCOperand::CreateReg(0)); 2647 else if (Rm != 0xF) { 2648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2649 return MCDisassembler::Fail; 2650 } 2651 break; 2652 case ARM::VST1d8wb_fixed: 2653 case ARM::VST1d16wb_fixed: 2654 case ARM::VST1d32wb_fixed: 2655 case ARM::VST1d64wb_fixed: 2656 case ARM::VST1q8wb_fixed: 2657 case ARM::VST1q16wb_fixed: 2658 case ARM::VST1q32wb_fixed: 2659 case ARM::VST1q64wb_fixed: 2660 case ARM::VST1d8Twb_fixed: 2661 case ARM::VST1d16Twb_fixed: 2662 case ARM::VST1d32Twb_fixed: 2663 case ARM::VST1d64Twb_fixed: 2664 case ARM::VST1d8Qwb_fixed: 2665 case ARM::VST1d16Qwb_fixed: 2666 case ARM::VST1d32Qwb_fixed: 2667 case ARM::VST1d64Qwb_fixed: 2668 case ARM::VST2d8wb_fixed: 2669 case ARM::VST2d16wb_fixed: 2670 case ARM::VST2d32wb_fixed: 2671 case ARM::VST2q8wb_fixed: 2672 case ARM::VST2q16wb_fixed: 2673 case ARM::VST2q32wb_fixed: 2674 case ARM::VST2b8wb_fixed: 2675 case ARM::VST2b16wb_fixed: 2676 case ARM::VST2b32wb_fixed: 2677 break; 2678 } 2679 2680 2681 // First input register 2682 switch (Inst.getOpcode()) { 2683 case ARM::VST1q16: 2684 case ARM::VST1q32: 2685 case ARM::VST1q64: 2686 case ARM::VST1q8: 2687 case ARM::VST1q16wb_fixed: 2688 case ARM::VST1q16wb_register: 2689 case ARM::VST1q32wb_fixed: 2690 case ARM::VST1q32wb_register: 2691 case ARM::VST1q64wb_fixed: 2692 case ARM::VST1q64wb_register: 2693 case ARM::VST1q8wb_fixed: 2694 case ARM::VST1q8wb_register: 2695 case ARM::VST2d16: 2696 case ARM::VST2d32: 2697 case ARM::VST2d8: 2698 case ARM::VST2d16wb_fixed: 2699 case ARM::VST2d16wb_register: 2700 case ARM::VST2d32wb_fixed: 2701 case ARM::VST2d32wb_register: 2702 case ARM::VST2d8wb_fixed: 2703 case ARM::VST2d8wb_register: 2704 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2705 return MCDisassembler::Fail; 2706 break; 2707 case ARM::VST2b16: 2708 case ARM::VST2b32: 2709 case ARM::VST2b8: 2710 case ARM::VST2b16wb_fixed: 2711 case ARM::VST2b16wb_register: 2712 case ARM::VST2b32wb_fixed: 2713 case ARM::VST2b32wb_register: 2714 case ARM::VST2b8wb_fixed: 2715 case ARM::VST2b8wb_register: 2716 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2717 return MCDisassembler::Fail; 2718 break; 2719 default: 2720 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2721 return MCDisassembler::Fail; 2722 } 2723 2724 // Second input register 2725 switch (Inst.getOpcode()) { 2726 case ARM::VST3d8: 2727 case ARM::VST3d16: 2728 case ARM::VST3d32: 2729 case ARM::VST3d8_UPD: 2730 case ARM::VST3d16_UPD: 2731 case ARM::VST3d32_UPD: 2732 case ARM::VST4d8: 2733 case ARM::VST4d16: 2734 case ARM::VST4d32: 2735 case ARM::VST4d8_UPD: 2736 case ARM::VST4d16_UPD: 2737 case ARM::VST4d32_UPD: 2738 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2739 return MCDisassembler::Fail; 2740 break; 2741 case ARM::VST3q8: 2742 case ARM::VST3q16: 2743 case ARM::VST3q32: 2744 case ARM::VST3q8_UPD: 2745 case ARM::VST3q16_UPD: 2746 case ARM::VST3q32_UPD: 2747 case ARM::VST4q8: 2748 case ARM::VST4q16: 2749 case ARM::VST4q32: 2750 case ARM::VST4q8_UPD: 2751 case ARM::VST4q16_UPD: 2752 case ARM::VST4q32_UPD: 2753 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2754 return MCDisassembler::Fail; 2755 break; 2756 default: 2757 break; 2758 } 2759 2760 // Third input register 2761 switch (Inst.getOpcode()) { 2762 case ARM::VST3d8: 2763 case ARM::VST3d16: 2764 case ARM::VST3d32: 2765 case ARM::VST3d8_UPD: 2766 case ARM::VST3d16_UPD: 2767 case ARM::VST3d32_UPD: 2768 case ARM::VST4d8: 2769 case ARM::VST4d16: 2770 case ARM::VST4d32: 2771 case ARM::VST4d8_UPD: 2772 case ARM::VST4d16_UPD: 2773 case ARM::VST4d32_UPD: 2774 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2775 return MCDisassembler::Fail; 2776 break; 2777 case ARM::VST3q8: 2778 case ARM::VST3q16: 2779 case ARM::VST3q32: 2780 case ARM::VST3q8_UPD: 2781 case ARM::VST3q16_UPD: 2782 case ARM::VST3q32_UPD: 2783 case ARM::VST4q8: 2784 case ARM::VST4q16: 2785 case ARM::VST4q32: 2786 case ARM::VST4q8_UPD: 2787 case ARM::VST4q16_UPD: 2788 case ARM::VST4q32_UPD: 2789 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2790 return MCDisassembler::Fail; 2791 break; 2792 default: 2793 break; 2794 } 2795 2796 // Fourth input register 2797 switch (Inst.getOpcode()) { 2798 case ARM::VST4d8: 2799 case ARM::VST4d16: 2800 case ARM::VST4d32: 2801 case ARM::VST4d8_UPD: 2802 case ARM::VST4d16_UPD: 2803 case ARM::VST4d32_UPD: 2804 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2805 return MCDisassembler::Fail; 2806 break; 2807 case ARM::VST4q8: 2808 case ARM::VST4q16: 2809 case ARM::VST4q32: 2810 case ARM::VST4q8_UPD: 2811 case ARM::VST4q16_UPD: 2812 case ARM::VST4q32_UPD: 2813 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2814 return MCDisassembler::Fail; 2815 break; 2816 default: 2817 break; 2818 } 2819 2820 return S; 2821 } 2822 2823 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2824 uint64_t Address, const void *Decoder) { 2825 DecodeStatus S = MCDisassembler::Success; 2826 2827 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2828 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2829 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2830 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2831 unsigned align = fieldFromInstruction(Insn, 4, 1); 2832 unsigned size = fieldFromInstruction(Insn, 6, 2); 2833 2834 if (size == 0 && align == 1) 2835 return MCDisassembler::Fail; 2836 align *= (1 << size); 2837 2838 switch (Inst.getOpcode()) { 2839 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2840 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2841 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2842 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2843 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2844 return MCDisassembler::Fail; 2845 break; 2846 default: 2847 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2848 return MCDisassembler::Fail; 2849 break; 2850 } 2851 if (Rm != 0xF) { 2852 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2853 return MCDisassembler::Fail; 2854 } 2855 2856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2857 return MCDisassembler::Fail; 2858 Inst.addOperand(MCOperand::CreateImm(align)); 2859 2860 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2861 // variant encodes Rm == 0xf. Anything else is a register offset post- 2862 // increment and we need to add the register operand to the instruction. 2863 if (Rm != 0xD && Rm != 0xF && 2864 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2865 return MCDisassembler::Fail; 2866 2867 return S; 2868 } 2869 2870 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2871 uint64_t Address, const void *Decoder) { 2872 DecodeStatus S = MCDisassembler::Success; 2873 2874 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2875 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2876 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2877 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2878 unsigned align = fieldFromInstruction(Insn, 4, 1); 2879 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2880 align *= 2*size; 2881 2882 switch (Inst.getOpcode()) { 2883 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2884 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2885 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2886 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2887 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2888 return MCDisassembler::Fail; 2889 break; 2890 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2891 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2892 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2893 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2894 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2895 return MCDisassembler::Fail; 2896 break; 2897 default: 2898 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2899 return MCDisassembler::Fail; 2900 break; 2901 } 2902 2903 if (Rm != 0xF) 2904 Inst.addOperand(MCOperand::CreateImm(0)); 2905 2906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2907 return MCDisassembler::Fail; 2908 Inst.addOperand(MCOperand::CreateImm(align)); 2909 2910 if (Rm != 0xD && Rm != 0xF) { 2911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2912 return MCDisassembler::Fail; 2913 } 2914 2915 return S; 2916 } 2917 2918 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2919 uint64_t Address, const void *Decoder) { 2920 DecodeStatus S = MCDisassembler::Success; 2921 2922 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2923 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2924 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2925 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2926 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2927 2928 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2929 return MCDisassembler::Fail; 2930 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2931 return MCDisassembler::Fail; 2932 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2933 return MCDisassembler::Fail; 2934 if (Rm != 0xF) { 2935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2936 return MCDisassembler::Fail; 2937 } 2938 2939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2940 return MCDisassembler::Fail; 2941 Inst.addOperand(MCOperand::CreateImm(0)); 2942 2943 if (Rm == 0xD) 2944 Inst.addOperand(MCOperand::CreateReg(0)); 2945 else if (Rm != 0xF) { 2946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2947 return MCDisassembler::Fail; 2948 } 2949 2950 return S; 2951 } 2952 2953 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2954 uint64_t Address, const void *Decoder) { 2955 DecodeStatus S = MCDisassembler::Success; 2956 2957 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2958 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2959 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2960 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2961 unsigned size = fieldFromInstruction(Insn, 6, 2); 2962 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2963 unsigned align = fieldFromInstruction(Insn, 4, 1); 2964 2965 if (size == 0x3) { 2966 if (align == 0) 2967 return MCDisassembler::Fail; 2968 size = 4; 2969 align = 16; 2970 } else { 2971 if (size == 2) { 2972 size = 1 << size; 2973 align *= 8; 2974 } else { 2975 size = 1 << size; 2976 align *= 4*size; 2977 } 2978 } 2979 2980 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2981 return MCDisassembler::Fail; 2982 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2983 return MCDisassembler::Fail; 2984 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2985 return MCDisassembler::Fail; 2986 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2987 return MCDisassembler::Fail; 2988 if (Rm != 0xF) { 2989 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2990 return MCDisassembler::Fail; 2991 } 2992 2993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2994 return MCDisassembler::Fail; 2995 Inst.addOperand(MCOperand::CreateImm(align)); 2996 2997 if (Rm == 0xD) 2998 Inst.addOperand(MCOperand::CreateReg(0)); 2999 else if (Rm != 0xF) { 3000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3001 return MCDisassembler::Fail; 3002 } 3003 3004 return S; 3005 } 3006 3007 static DecodeStatus 3008 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3009 uint64_t Address, const void *Decoder) { 3010 DecodeStatus S = MCDisassembler::Success; 3011 3012 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3013 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3014 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3015 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3016 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3017 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3018 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3019 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3020 3021 if (Q) { 3022 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3023 return MCDisassembler::Fail; 3024 } else { 3025 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3026 return MCDisassembler::Fail; 3027 } 3028 3029 Inst.addOperand(MCOperand::CreateImm(imm)); 3030 3031 switch (Inst.getOpcode()) { 3032 case ARM::VORRiv4i16: 3033 case ARM::VORRiv2i32: 3034 case ARM::VBICiv4i16: 3035 case ARM::VBICiv2i32: 3036 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3037 return MCDisassembler::Fail; 3038 break; 3039 case ARM::VORRiv8i16: 3040 case ARM::VORRiv4i32: 3041 case ARM::VBICiv8i16: 3042 case ARM::VBICiv4i32: 3043 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3044 return MCDisassembler::Fail; 3045 break; 3046 default: 3047 break; 3048 } 3049 3050 return S; 3051 } 3052 3053 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3054 uint64_t Address, const void *Decoder) { 3055 DecodeStatus S = MCDisassembler::Success; 3056 3057 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3058 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3059 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3060 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3061 unsigned size = fieldFromInstruction(Insn, 18, 2); 3062 3063 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3064 return MCDisassembler::Fail; 3065 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3066 return MCDisassembler::Fail; 3067 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3068 3069 return S; 3070 } 3071 3072 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3073 uint64_t Address, const void *Decoder) { 3074 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3075 return MCDisassembler::Success; 3076 } 3077 3078 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3079 uint64_t Address, const void *Decoder) { 3080 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3081 return MCDisassembler::Success; 3082 } 3083 3084 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3085 uint64_t Address, const void *Decoder) { 3086 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3087 return MCDisassembler::Success; 3088 } 3089 3090 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3091 uint64_t Address, const void *Decoder) { 3092 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3093 return MCDisassembler::Success; 3094 } 3095 3096 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3097 uint64_t Address, const void *Decoder) { 3098 DecodeStatus S = MCDisassembler::Success; 3099 3100 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3101 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3102 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3103 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3104 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3105 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3106 unsigned op = fieldFromInstruction(Insn, 6, 1); 3107 3108 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3109 return MCDisassembler::Fail; 3110 if (op) { 3111 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3112 return MCDisassembler::Fail; // Writeback 3113 } 3114 3115 switch (Inst.getOpcode()) { 3116 case ARM::VTBL2: 3117 case ARM::VTBX2: 3118 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3119 return MCDisassembler::Fail; 3120 break; 3121 default: 3122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3123 return MCDisassembler::Fail; 3124 } 3125 3126 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3127 return MCDisassembler::Fail; 3128 3129 return S; 3130 } 3131 3132 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3133 uint64_t Address, const void *Decoder) { 3134 DecodeStatus S = MCDisassembler::Success; 3135 3136 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3137 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3138 3139 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3140 return MCDisassembler::Fail; 3141 3142 switch(Inst.getOpcode()) { 3143 default: 3144 return MCDisassembler::Fail; 3145 case ARM::tADR: 3146 break; // tADR does not explicitly represent the PC as an operand. 3147 case ARM::tADDrSPi: 3148 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3149 break; 3150 } 3151 3152 Inst.addOperand(MCOperand::CreateImm(imm)); 3153 return S; 3154 } 3155 3156 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3157 uint64_t Address, const void *Decoder) { 3158 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3159 true, 2, Inst, Decoder)) 3160 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3161 return MCDisassembler::Success; 3162 } 3163 3164 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3165 uint64_t Address, const void *Decoder) { 3166 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3167 true, 4, Inst, Decoder)) 3168 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3169 return MCDisassembler::Success; 3170 } 3171 3172 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3173 uint64_t Address, const void *Decoder) { 3174 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3175 true, 2, Inst, Decoder)) 3176 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3177 return MCDisassembler::Success; 3178 } 3179 3180 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3181 uint64_t Address, const void *Decoder) { 3182 DecodeStatus S = MCDisassembler::Success; 3183 3184 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3185 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3186 3187 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3188 return MCDisassembler::Fail; 3189 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 3192 return S; 3193 } 3194 3195 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3196 uint64_t Address, const void *Decoder) { 3197 DecodeStatus S = MCDisassembler::Success; 3198 3199 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3200 unsigned imm = fieldFromInstruction(Val, 3, 5); 3201 3202 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3203 return MCDisassembler::Fail; 3204 Inst.addOperand(MCOperand::CreateImm(imm)); 3205 3206 return S; 3207 } 3208 3209 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3210 uint64_t Address, const void *Decoder) { 3211 unsigned imm = Val << 2; 3212 3213 Inst.addOperand(MCOperand::CreateImm(imm)); 3214 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3215 3216 return MCDisassembler::Success; 3217 } 3218 3219 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3220 uint64_t Address, const void *Decoder) { 3221 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3222 Inst.addOperand(MCOperand::CreateImm(Val)); 3223 3224 return MCDisassembler::Success; 3225 } 3226 3227 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3228 uint64_t Address, const void *Decoder) { 3229 DecodeStatus S = MCDisassembler::Success; 3230 3231 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3232 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3233 unsigned imm = fieldFromInstruction(Val, 0, 2); 3234 3235 // Thumb stores cannot use PC as dest register. 3236 switch (Inst.getOpcode()) { 3237 case ARM::t2STRHs: 3238 case ARM::t2STRBs: 3239 case ARM::t2STRs: 3240 if (Rn == 15) 3241 return MCDisassembler::Fail; 3242 default: 3243 break; 3244 } 3245 3246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3247 return MCDisassembler::Fail; 3248 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3249 return MCDisassembler::Fail; 3250 Inst.addOperand(MCOperand::CreateImm(imm)); 3251 3252 return S; 3253 } 3254 3255 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3256 uint64_t Address, const void *Decoder) { 3257 DecodeStatus S = MCDisassembler::Success; 3258 3259 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3260 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3261 3262 if (Rn == 15) { 3263 switch (Inst.getOpcode()) { 3264 case ARM::t2LDRBs: 3265 Inst.setOpcode(ARM::t2LDRBpci); 3266 break; 3267 case ARM::t2LDRHs: 3268 Inst.setOpcode(ARM::t2LDRHpci); 3269 break; 3270 case ARM::t2LDRSHs: 3271 Inst.setOpcode(ARM::t2LDRSHpci); 3272 break; 3273 case ARM::t2LDRSBs: 3274 Inst.setOpcode(ARM::t2LDRSBpci); 3275 break; 3276 case ARM::t2LDRs: 3277 Inst.setOpcode(ARM::t2LDRpci); 3278 break; 3279 case ARM::t2PLDs: 3280 Inst.setOpcode(ARM::t2PLDpci); 3281 break; 3282 case ARM::t2PLIs: 3283 Inst.setOpcode(ARM::t2PLIpci); 3284 break; 3285 default: 3286 return MCDisassembler::Fail; 3287 } 3288 3289 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3290 } 3291 3292 if (Rt == 15) { 3293 switch (Inst.getOpcode()) { 3294 case ARM::t2LDRSHs: 3295 return MCDisassembler::Fail; 3296 case ARM::t2LDRHs: 3297 // FIXME: this instruction is only available with MP extensions, 3298 // this should be checked first but we don't have access to the 3299 // feature bits here. 3300 Inst.setOpcode(ARM::t2PLDWs); 3301 break; 3302 default: 3303 break; 3304 } 3305 } 3306 3307 switch (Inst.getOpcode()) { 3308 case ARM::t2PLDs: 3309 case ARM::t2PLDWs: 3310 case ARM::t2PLIs: 3311 break; 3312 default: 3313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3314 return MCDisassembler::Fail; 3315 } 3316 3317 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3318 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3319 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3320 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3321 return MCDisassembler::Fail; 3322 3323 return S; 3324 } 3325 3326 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3327 uint64_t Address, const void* Decoder) { 3328 DecodeStatus S = MCDisassembler::Success; 3329 3330 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3331 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3332 unsigned U = fieldFromInstruction(Insn, 9, 1); 3333 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3334 imm |= (U << 8); 3335 imm |= (Rn << 9); 3336 3337 if (Rn == 15) { 3338 switch (Inst.getOpcode()) { 3339 case ARM::t2LDRi8: 3340 Inst.setOpcode(ARM::t2LDRpci); 3341 break; 3342 case ARM::t2LDRBi8: 3343 Inst.setOpcode(ARM::t2LDRBpci); 3344 break; 3345 case ARM::t2LDRSBi8: 3346 Inst.setOpcode(ARM::t2LDRSBpci); 3347 break; 3348 case ARM::t2LDRHi8: 3349 Inst.setOpcode(ARM::t2LDRHpci); 3350 break; 3351 case ARM::t2LDRSHi8: 3352 Inst.setOpcode(ARM::t2LDRSHpci); 3353 break; 3354 case ARM::t2PLDi8: 3355 Inst.setOpcode(ARM::t2PLDpci); 3356 break; 3357 case ARM::t2PLIi8: 3358 Inst.setOpcode(ARM::t2PLIpci); 3359 break; 3360 default: 3361 return MCDisassembler::Fail; 3362 } 3363 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3364 } 3365 3366 if (Rt == 15) { 3367 switch (Inst.getOpcode()) { 3368 case ARM::t2LDRSHi8: 3369 return MCDisassembler::Fail; 3370 default: 3371 break; 3372 } 3373 } 3374 3375 switch (Inst.getOpcode()) { 3376 case ARM::t2PLDi8: 3377 case ARM::t2PLIi8: 3378 case ARM::t2PLDWi8: 3379 break; 3380 default: 3381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3382 return MCDisassembler::Fail; 3383 } 3384 3385 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3386 return MCDisassembler::Fail; 3387 return S; 3388 } 3389 3390 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3391 uint64_t Address, const void* Decoder) { 3392 DecodeStatus S = MCDisassembler::Success; 3393 3394 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3395 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3396 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3397 imm |= (Rn << 13); 3398 3399 if (Rn == 15) { 3400 switch (Inst.getOpcode()) { 3401 case ARM::t2LDRi12: 3402 Inst.setOpcode(ARM::t2LDRpci); 3403 break; 3404 case ARM::t2LDRHi12: 3405 Inst.setOpcode(ARM::t2LDRHpci); 3406 break; 3407 case ARM::t2LDRSHi12: 3408 Inst.setOpcode(ARM::t2LDRSHpci); 3409 break; 3410 case ARM::t2LDRBi12: 3411 Inst.setOpcode(ARM::t2LDRBpci); 3412 break; 3413 case ARM::t2LDRSBi12: 3414 Inst.setOpcode(ARM::t2LDRSBpci); 3415 break; 3416 case ARM::t2PLDi12: 3417 Inst.setOpcode(ARM::t2PLDpci); 3418 break; 3419 case ARM::t2PLIi12: 3420 Inst.setOpcode(ARM::t2PLIpci); 3421 break; 3422 default: 3423 return MCDisassembler::Fail; 3424 } 3425 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3426 } 3427 3428 if (Rt == 15) { 3429 switch (Inst.getOpcode()) { 3430 case ARM::t2LDRSHi12: 3431 return MCDisassembler::Fail; 3432 case ARM::t2LDRHi12: 3433 Inst.setOpcode(ARM::t2PLDi12); 3434 break; 3435 default: 3436 break; 3437 } 3438 } 3439 3440 switch (Inst.getOpcode()) { 3441 case ARM::t2PLDi12: 3442 case ARM::t2PLDWi12: 3443 case ARM::t2PLIi12: 3444 break; 3445 default: 3446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3447 return MCDisassembler::Fail; 3448 } 3449 3450 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3451 return MCDisassembler::Fail; 3452 return S; 3453 } 3454 3455 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3456 uint64_t Address, const void* Decoder) { 3457 DecodeStatus S = MCDisassembler::Success; 3458 3459 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3460 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3461 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3462 imm |= (Rn << 9); 3463 3464 if (Rn == 15) { 3465 switch (Inst.getOpcode()) { 3466 case ARM::t2LDRT: 3467 Inst.setOpcode(ARM::t2LDRpci); 3468 break; 3469 case ARM::t2LDRBT: 3470 Inst.setOpcode(ARM::t2LDRBpci); 3471 break; 3472 case ARM::t2LDRHT: 3473 Inst.setOpcode(ARM::t2LDRHpci); 3474 break; 3475 case ARM::t2LDRSBT: 3476 Inst.setOpcode(ARM::t2LDRSBpci); 3477 break; 3478 case ARM::t2LDRSHT: 3479 Inst.setOpcode(ARM::t2LDRSHpci); 3480 break; 3481 default: 3482 return MCDisassembler::Fail; 3483 } 3484 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3485 } 3486 3487 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3488 return MCDisassembler::Fail; 3489 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3490 return MCDisassembler::Fail; 3491 return S; 3492 } 3493 3494 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3495 uint64_t Address, const void* Decoder) { 3496 DecodeStatus S = MCDisassembler::Success; 3497 3498 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3499 unsigned U = fieldFromInstruction(Insn, 23, 1); 3500 int imm = fieldFromInstruction(Insn, 0, 12); 3501 3502 if (Rt == 15) { 3503 switch (Inst.getOpcode()) { 3504 case ARM::t2LDRBpci: 3505 case ARM::t2LDRHpci: 3506 Inst.setOpcode(ARM::t2PLDpci); 3507 break; 3508 case ARM::t2LDRSBpci: 3509 Inst.setOpcode(ARM::t2PLIpci); 3510 break; 3511 case ARM::t2LDRSHpci: 3512 return MCDisassembler::Fail; 3513 default: 3514 break; 3515 } 3516 } 3517 3518 switch(Inst.getOpcode()) { 3519 case ARM::t2PLDpci: 3520 case ARM::t2PLIpci: 3521 break; 3522 default: 3523 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3524 return MCDisassembler::Fail; 3525 } 3526 3527 if (!U) { 3528 // Special case for #-0. 3529 if (imm == 0) 3530 imm = INT32_MIN; 3531 else 3532 imm = -imm; 3533 } 3534 Inst.addOperand(MCOperand::CreateImm(imm)); 3535 3536 return S; 3537 } 3538 3539 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3540 uint64_t Address, const void *Decoder) { 3541 if (Val == 0) 3542 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3543 else { 3544 int imm = Val & 0xFF; 3545 3546 if (!(Val & 0x100)) imm *= -1; 3547 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3548 } 3549 3550 return MCDisassembler::Success; 3551 } 3552 3553 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3554 uint64_t Address, const void *Decoder) { 3555 DecodeStatus S = MCDisassembler::Success; 3556 3557 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3558 unsigned imm = fieldFromInstruction(Val, 0, 9); 3559 3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 3565 return S; 3566 } 3567 3568 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3569 uint64_t Address, const void *Decoder) { 3570 DecodeStatus S = MCDisassembler::Success; 3571 3572 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3573 unsigned imm = fieldFromInstruction(Val, 0, 8); 3574 3575 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3576 return MCDisassembler::Fail; 3577 3578 Inst.addOperand(MCOperand::CreateImm(imm)); 3579 3580 return S; 3581 } 3582 3583 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3584 uint64_t Address, const void *Decoder) { 3585 int imm = Val & 0xFF; 3586 if (Val == 0) 3587 imm = INT32_MIN; 3588 else if (!(Val & 0x100)) 3589 imm *= -1; 3590 Inst.addOperand(MCOperand::CreateImm(imm)); 3591 3592 return MCDisassembler::Success; 3593 } 3594 3595 3596 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3597 uint64_t Address, const void *Decoder) { 3598 DecodeStatus S = MCDisassembler::Success; 3599 3600 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3601 unsigned imm = fieldFromInstruction(Val, 0, 9); 3602 3603 // Thumb stores cannot use PC as dest register. 3604 switch (Inst.getOpcode()) { 3605 case ARM::t2STRT: 3606 case ARM::t2STRBT: 3607 case ARM::t2STRHT: 3608 case ARM::t2STRi8: 3609 case ARM::t2STRHi8: 3610 case ARM::t2STRBi8: 3611 if (Rn == 15) 3612 return MCDisassembler::Fail; 3613 break; 3614 default: 3615 break; 3616 } 3617 3618 // Some instructions always use an additive offset. 3619 switch (Inst.getOpcode()) { 3620 case ARM::t2LDRT: 3621 case ARM::t2LDRBT: 3622 case ARM::t2LDRHT: 3623 case ARM::t2LDRSBT: 3624 case ARM::t2LDRSHT: 3625 case ARM::t2STRT: 3626 case ARM::t2STRBT: 3627 case ARM::t2STRHT: 3628 imm |= 0x100; 3629 break; 3630 default: 3631 break; 3632 } 3633 3634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3637 return MCDisassembler::Fail; 3638 3639 return S; 3640 } 3641 3642 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3643 uint64_t Address, const void *Decoder) { 3644 DecodeStatus S = MCDisassembler::Success; 3645 3646 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3647 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3648 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3649 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3650 addr |= Rn << 9; 3651 unsigned load = fieldFromInstruction(Insn, 20, 1); 3652 3653 if (Rn == 15) { 3654 switch (Inst.getOpcode()) { 3655 case ARM::t2LDR_PRE: 3656 case ARM::t2LDR_POST: 3657 Inst.setOpcode(ARM::t2LDRpci); 3658 break; 3659 case ARM::t2LDRB_PRE: 3660 case ARM::t2LDRB_POST: 3661 Inst.setOpcode(ARM::t2LDRBpci); 3662 break; 3663 case ARM::t2LDRH_PRE: 3664 case ARM::t2LDRH_POST: 3665 Inst.setOpcode(ARM::t2LDRHpci); 3666 break; 3667 case ARM::t2LDRSB_PRE: 3668 case ARM::t2LDRSB_POST: 3669 if (Rt == 15) 3670 Inst.setOpcode(ARM::t2PLIpci); 3671 else 3672 Inst.setOpcode(ARM::t2LDRSBpci); 3673 break; 3674 case ARM::t2LDRSH_PRE: 3675 case ARM::t2LDRSH_POST: 3676 Inst.setOpcode(ARM::t2LDRSHpci); 3677 break; 3678 default: 3679 return MCDisassembler::Fail; 3680 } 3681 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3682 } 3683 3684 if (!load) { 3685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3686 return MCDisassembler::Fail; 3687 } 3688 3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 3692 if (load) { 3693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3694 return MCDisassembler::Fail; 3695 } 3696 3697 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3698 return MCDisassembler::Fail; 3699 3700 return S; 3701 } 3702 3703 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3704 uint64_t Address, const void *Decoder) { 3705 DecodeStatus S = MCDisassembler::Success; 3706 3707 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3708 unsigned imm = fieldFromInstruction(Val, 0, 12); 3709 3710 // Thumb stores cannot use PC as dest register. 3711 switch (Inst.getOpcode()) { 3712 case ARM::t2STRi12: 3713 case ARM::t2STRBi12: 3714 case ARM::t2STRHi12: 3715 if (Rn == 15) 3716 return MCDisassembler::Fail; 3717 default: 3718 break; 3719 } 3720 3721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3722 return MCDisassembler::Fail; 3723 Inst.addOperand(MCOperand::CreateImm(imm)); 3724 3725 return S; 3726 } 3727 3728 3729 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3730 uint64_t Address, const void *Decoder) { 3731 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3732 3733 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3734 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3735 Inst.addOperand(MCOperand::CreateImm(imm)); 3736 3737 return MCDisassembler::Success; 3738 } 3739 3740 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3741 uint64_t Address, const void *Decoder) { 3742 DecodeStatus S = MCDisassembler::Success; 3743 3744 if (Inst.getOpcode() == ARM::tADDrSP) { 3745 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3746 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3747 3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3749 return MCDisassembler::Fail; 3750 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3752 return MCDisassembler::Fail; 3753 } else if (Inst.getOpcode() == ARM::tADDspr) { 3754 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3755 3756 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3757 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3759 return MCDisassembler::Fail; 3760 } 3761 3762 return S; 3763 } 3764 3765 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3766 uint64_t Address, const void *Decoder) { 3767 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3768 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3769 3770 Inst.addOperand(MCOperand::CreateImm(imod)); 3771 Inst.addOperand(MCOperand::CreateImm(flags)); 3772 3773 return MCDisassembler::Success; 3774 } 3775 3776 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3777 uint64_t Address, const void *Decoder) { 3778 DecodeStatus S = MCDisassembler::Success; 3779 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3780 unsigned add = fieldFromInstruction(Insn, 4, 1); 3781 3782 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3783 return MCDisassembler::Fail; 3784 Inst.addOperand(MCOperand::CreateImm(add)); 3785 3786 return S; 3787 } 3788 3789 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3790 uint64_t Address, const void *Decoder) { 3791 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3792 // Note only one trailing zero not two. Also the J1 and J2 values are from 3793 // the encoded instruction. So here change to I1 and I2 values via: 3794 // I1 = NOT(J1 EOR S); 3795 // I2 = NOT(J2 EOR S); 3796 // and build the imm32 with two trailing zeros as documented: 3797 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3798 unsigned S = (Val >> 23) & 1; 3799 unsigned J1 = (Val >> 22) & 1; 3800 unsigned J2 = (Val >> 21) & 1; 3801 unsigned I1 = !(J1 ^ S); 3802 unsigned I2 = !(J2 ^ S); 3803 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3804 int imm32 = SignExtend32<25>(tmp << 1); 3805 3806 if (!tryAddingSymbolicOperand(Address, 3807 (Address & ~2u) + imm32 + 4, 3808 true, 4, Inst, Decoder)) 3809 Inst.addOperand(MCOperand::CreateImm(imm32)); 3810 return MCDisassembler::Success; 3811 } 3812 3813 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3814 uint64_t Address, const void *Decoder) { 3815 if (Val == 0xA || Val == 0xB) 3816 return MCDisassembler::Fail; 3817 3818 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3819 .getFeatureBits(); 3820 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15)) 3821 return MCDisassembler::Fail; 3822 3823 Inst.addOperand(MCOperand::CreateImm(Val)); 3824 return MCDisassembler::Success; 3825 } 3826 3827 static DecodeStatus 3828 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3829 uint64_t Address, const void *Decoder) { 3830 DecodeStatus S = MCDisassembler::Success; 3831 3832 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3833 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3834 3835 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3837 return MCDisassembler::Fail; 3838 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3839 return MCDisassembler::Fail; 3840 return S; 3841 } 3842 3843 static DecodeStatus 3844 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3845 uint64_t Address, const void *Decoder) { 3846 DecodeStatus S = MCDisassembler::Success; 3847 3848 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3849 if (pred == 0xE || pred == 0xF) { 3850 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3851 switch (opc) { 3852 default: 3853 return MCDisassembler::Fail; 3854 case 0xf3bf8f4: 3855 Inst.setOpcode(ARM::t2DSB); 3856 break; 3857 case 0xf3bf8f5: 3858 Inst.setOpcode(ARM::t2DMB); 3859 break; 3860 case 0xf3bf8f6: 3861 Inst.setOpcode(ARM::t2ISB); 3862 break; 3863 } 3864 3865 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3866 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3867 } 3868 3869 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3870 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3871 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3872 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3873 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3874 3875 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3876 return MCDisassembler::Fail; 3877 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3878 return MCDisassembler::Fail; 3879 3880 return S; 3881 } 3882 3883 // Decode a shifted immediate operand. These basically consist 3884 // of an 8-bit value, and a 4-bit directive that specifies either 3885 // a splat operation or a rotation. 3886 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3887 uint64_t Address, const void *Decoder) { 3888 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3889 if (ctrl == 0) { 3890 unsigned byte = fieldFromInstruction(Val, 8, 2); 3891 unsigned imm = fieldFromInstruction(Val, 0, 8); 3892 switch (byte) { 3893 case 0: 3894 Inst.addOperand(MCOperand::CreateImm(imm)); 3895 break; 3896 case 1: 3897 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3898 break; 3899 case 2: 3900 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3901 break; 3902 case 3: 3903 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3904 (imm << 8) | imm)); 3905 break; 3906 } 3907 } else { 3908 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3909 unsigned rot = fieldFromInstruction(Val, 7, 5); 3910 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3911 Inst.addOperand(MCOperand::CreateImm(imm)); 3912 } 3913 3914 return MCDisassembler::Success; 3915 } 3916 3917 static DecodeStatus 3918 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3919 uint64_t Address, const void *Decoder){ 3920 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3921 true, 2, Inst, Decoder)) 3922 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3923 return MCDisassembler::Success; 3924 } 3925 3926 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3927 uint64_t Address, const void *Decoder){ 3928 // Val is passed in as S:J1:J2:imm10:imm11 3929 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3930 // the encoded instruction. So here change to I1 and I2 values via: 3931 // I1 = NOT(J1 EOR S); 3932 // I2 = NOT(J2 EOR S); 3933 // and build the imm32 with one trailing zero as documented: 3934 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3935 unsigned S = (Val >> 23) & 1; 3936 unsigned J1 = (Val >> 22) & 1; 3937 unsigned J2 = (Val >> 21) & 1; 3938 unsigned I1 = !(J1 ^ S); 3939 unsigned I2 = !(J2 ^ S); 3940 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3941 int imm32 = SignExtend32<25>(tmp << 1); 3942 3943 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 3944 true, 4, Inst, Decoder)) 3945 Inst.addOperand(MCOperand::CreateImm(imm32)); 3946 return MCDisassembler::Success; 3947 } 3948 3949 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 3950 uint64_t Address, const void *Decoder) { 3951 if (Val & ~0xf) 3952 return MCDisassembler::Fail; 3953 3954 Inst.addOperand(MCOperand::CreateImm(Val)); 3955 return MCDisassembler::Success; 3956 } 3957 3958 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 3959 uint64_t Address, const void *Decoder) { 3960 if (Val & ~0xf) 3961 return MCDisassembler::Fail; 3962 3963 Inst.addOperand(MCOperand::CreateImm(Val)); 3964 return MCDisassembler::Success; 3965 } 3966 3967 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 3968 uint64_t Address, const void *Decoder) { 3969 if (!Val) return MCDisassembler::Fail; 3970 Inst.addOperand(MCOperand::CreateImm(Val)); 3971 return MCDisassembler::Success; 3972 } 3973 3974 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 3975 uint64_t Address, const void *Decoder) { 3976 DecodeStatus S = MCDisassembler::Success; 3977 3978 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3979 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3980 unsigned pred = fieldFromInstruction(Insn, 28, 4); 3981 3982 if (Rn == 0xF) 3983 S = MCDisassembler::SoftFail; 3984 3985 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 3986 return MCDisassembler::Fail; 3987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3988 return MCDisassembler::Fail; 3989 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3990 return MCDisassembler::Fail; 3991 3992 return S; 3993 } 3994 3995 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 3996 uint64_t Address, const void *Decoder){ 3997 DecodeStatus S = MCDisassembler::Success; 3998 3999 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4000 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4001 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4002 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4003 4004 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4005 return MCDisassembler::Fail; 4006 4007 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4008 S = MCDisassembler::SoftFail; 4009 4010 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4011 return MCDisassembler::Fail; 4012 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4013 return MCDisassembler::Fail; 4014 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4015 return MCDisassembler::Fail; 4016 4017 return S; 4018 } 4019 4020 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4021 uint64_t Address, const void *Decoder) { 4022 DecodeStatus S = MCDisassembler::Success; 4023 4024 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4025 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4026 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4027 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4028 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4029 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4030 4031 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4032 4033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4034 return MCDisassembler::Fail; 4035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4036 return MCDisassembler::Fail; 4037 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4038 return MCDisassembler::Fail; 4039 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4040 return MCDisassembler::Fail; 4041 4042 return S; 4043 } 4044 4045 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4046 uint64_t Address, const void *Decoder) { 4047 DecodeStatus S = MCDisassembler::Success; 4048 4049 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4050 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4051 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4052 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4053 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4054 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4055 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4056 4057 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4058 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4059 4060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4061 return MCDisassembler::Fail; 4062 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4063 return MCDisassembler::Fail; 4064 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4065 return MCDisassembler::Fail; 4066 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4067 return MCDisassembler::Fail; 4068 4069 return S; 4070 } 4071 4072 4073 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4074 uint64_t Address, const void *Decoder) { 4075 DecodeStatus S = MCDisassembler::Success; 4076 4077 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4078 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4079 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4080 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4081 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4082 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4083 4084 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4085 4086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4087 return MCDisassembler::Fail; 4088 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4089 return MCDisassembler::Fail; 4090 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4091 return MCDisassembler::Fail; 4092 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4093 return MCDisassembler::Fail; 4094 4095 return S; 4096 } 4097 4098 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4099 uint64_t Address, const void *Decoder) { 4100 DecodeStatus S = MCDisassembler::Success; 4101 4102 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4103 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4104 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4105 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4106 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4107 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4108 4109 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4110 4111 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4112 return MCDisassembler::Fail; 4113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4114 return MCDisassembler::Fail; 4115 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4116 return MCDisassembler::Fail; 4117 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4118 return MCDisassembler::Fail; 4119 4120 return S; 4121 } 4122 4123 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4124 uint64_t Address, const void *Decoder) { 4125 DecodeStatus S = MCDisassembler::Success; 4126 4127 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4128 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4129 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4130 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4131 unsigned size = fieldFromInstruction(Insn, 10, 2); 4132 4133 unsigned align = 0; 4134 unsigned index = 0; 4135 switch (size) { 4136 default: 4137 return MCDisassembler::Fail; 4138 case 0: 4139 if (fieldFromInstruction(Insn, 4, 1)) 4140 return MCDisassembler::Fail; // UNDEFINED 4141 index = fieldFromInstruction(Insn, 5, 3); 4142 break; 4143 case 1: 4144 if (fieldFromInstruction(Insn, 5, 1)) 4145 return MCDisassembler::Fail; // UNDEFINED 4146 index = fieldFromInstruction(Insn, 6, 2); 4147 if (fieldFromInstruction(Insn, 4, 1)) 4148 align = 2; 4149 break; 4150 case 2: 4151 if (fieldFromInstruction(Insn, 6, 1)) 4152 return MCDisassembler::Fail; // UNDEFINED 4153 index = fieldFromInstruction(Insn, 7, 1); 4154 4155 switch (fieldFromInstruction(Insn, 4, 2)) { 4156 case 0 : 4157 align = 0; break; 4158 case 3: 4159 align = 4; break; 4160 default: 4161 return MCDisassembler::Fail; 4162 } 4163 break; 4164 } 4165 4166 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4167 return MCDisassembler::Fail; 4168 if (Rm != 0xF) { // Writeback 4169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4170 return MCDisassembler::Fail; 4171 } 4172 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4173 return MCDisassembler::Fail; 4174 Inst.addOperand(MCOperand::CreateImm(align)); 4175 if (Rm != 0xF) { 4176 if (Rm != 0xD) { 4177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4178 return MCDisassembler::Fail; 4179 } else 4180 Inst.addOperand(MCOperand::CreateReg(0)); 4181 } 4182 4183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4184 return MCDisassembler::Fail; 4185 Inst.addOperand(MCOperand::CreateImm(index)); 4186 4187 return S; 4188 } 4189 4190 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4191 uint64_t Address, const void *Decoder) { 4192 DecodeStatus S = MCDisassembler::Success; 4193 4194 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4195 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4196 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4197 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4198 unsigned size = fieldFromInstruction(Insn, 10, 2); 4199 4200 unsigned align = 0; 4201 unsigned index = 0; 4202 switch (size) { 4203 default: 4204 return MCDisassembler::Fail; 4205 case 0: 4206 if (fieldFromInstruction(Insn, 4, 1)) 4207 return MCDisassembler::Fail; // UNDEFINED 4208 index = fieldFromInstruction(Insn, 5, 3); 4209 break; 4210 case 1: 4211 if (fieldFromInstruction(Insn, 5, 1)) 4212 return MCDisassembler::Fail; // UNDEFINED 4213 index = fieldFromInstruction(Insn, 6, 2); 4214 if (fieldFromInstruction(Insn, 4, 1)) 4215 align = 2; 4216 break; 4217 case 2: 4218 if (fieldFromInstruction(Insn, 6, 1)) 4219 return MCDisassembler::Fail; // UNDEFINED 4220 index = fieldFromInstruction(Insn, 7, 1); 4221 4222 switch (fieldFromInstruction(Insn, 4, 2)) { 4223 case 0: 4224 align = 0; break; 4225 case 3: 4226 align = 4; break; 4227 default: 4228 return MCDisassembler::Fail; 4229 } 4230 break; 4231 } 4232 4233 if (Rm != 0xF) { // Writeback 4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 } 4237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4238 return MCDisassembler::Fail; 4239 Inst.addOperand(MCOperand::CreateImm(align)); 4240 if (Rm != 0xF) { 4241 if (Rm != 0xD) { 4242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4243 return MCDisassembler::Fail; 4244 } else 4245 Inst.addOperand(MCOperand::CreateReg(0)); 4246 } 4247 4248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4249 return MCDisassembler::Fail; 4250 Inst.addOperand(MCOperand::CreateImm(index)); 4251 4252 return S; 4253 } 4254 4255 4256 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4257 uint64_t Address, const void *Decoder) { 4258 DecodeStatus S = MCDisassembler::Success; 4259 4260 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4261 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4262 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4263 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4264 unsigned size = fieldFromInstruction(Insn, 10, 2); 4265 4266 unsigned align = 0; 4267 unsigned index = 0; 4268 unsigned inc = 1; 4269 switch (size) { 4270 default: 4271 return MCDisassembler::Fail; 4272 case 0: 4273 index = fieldFromInstruction(Insn, 5, 3); 4274 if (fieldFromInstruction(Insn, 4, 1)) 4275 align = 2; 4276 break; 4277 case 1: 4278 index = fieldFromInstruction(Insn, 6, 2); 4279 if (fieldFromInstruction(Insn, 4, 1)) 4280 align = 4; 4281 if (fieldFromInstruction(Insn, 5, 1)) 4282 inc = 2; 4283 break; 4284 case 2: 4285 if (fieldFromInstruction(Insn, 5, 1)) 4286 return MCDisassembler::Fail; // UNDEFINED 4287 index = fieldFromInstruction(Insn, 7, 1); 4288 if (fieldFromInstruction(Insn, 4, 1) != 0) 4289 align = 8; 4290 if (fieldFromInstruction(Insn, 6, 1)) 4291 inc = 2; 4292 break; 4293 } 4294 4295 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4296 return MCDisassembler::Fail; 4297 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4298 return MCDisassembler::Fail; 4299 if (Rm != 0xF) { // Writeback 4300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4301 return MCDisassembler::Fail; 4302 } 4303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 Inst.addOperand(MCOperand::CreateImm(align)); 4306 if (Rm != 0xF) { 4307 if (Rm != 0xD) { 4308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4309 return MCDisassembler::Fail; 4310 } else 4311 Inst.addOperand(MCOperand::CreateReg(0)); 4312 } 4313 4314 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4315 return MCDisassembler::Fail; 4316 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4317 return MCDisassembler::Fail; 4318 Inst.addOperand(MCOperand::CreateImm(index)); 4319 4320 return S; 4321 } 4322 4323 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4324 uint64_t Address, const void *Decoder) { 4325 DecodeStatus S = MCDisassembler::Success; 4326 4327 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4328 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4329 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4330 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4331 unsigned size = fieldFromInstruction(Insn, 10, 2); 4332 4333 unsigned align = 0; 4334 unsigned index = 0; 4335 unsigned inc = 1; 4336 switch (size) { 4337 default: 4338 return MCDisassembler::Fail; 4339 case 0: 4340 index = fieldFromInstruction(Insn, 5, 3); 4341 if (fieldFromInstruction(Insn, 4, 1)) 4342 align = 2; 4343 break; 4344 case 1: 4345 index = fieldFromInstruction(Insn, 6, 2); 4346 if (fieldFromInstruction(Insn, 4, 1)) 4347 align = 4; 4348 if (fieldFromInstruction(Insn, 5, 1)) 4349 inc = 2; 4350 break; 4351 case 2: 4352 if (fieldFromInstruction(Insn, 5, 1)) 4353 return MCDisassembler::Fail; // UNDEFINED 4354 index = fieldFromInstruction(Insn, 7, 1); 4355 if (fieldFromInstruction(Insn, 4, 1) != 0) 4356 align = 8; 4357 if (fieldFromInstruction(Insn, 6, 1)) 4358 inc = 2; 4359 break; 4360 } 4361 4362 if (Rm != 0xF) { // Writeback 4363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4364 return MCDisassembler::Fail; 4365 } 4366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4367 return MCDisassembler::Fail; 4368 Inst.addOperand(MCOperand::CreateImm(align)); 4369 if (Rm != 0xF) { 4370 if (Rm != 0xD) { 4371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4372 return MCDisassembler::Fail; 4373 } else 4374 Inst.addOperand(MCOperand::CreateReg(0)); 4375 } 4376 4377 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4378 return MCDisassembler::Fail; 4379 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4380 return MCDisassembler::Fail; 4381 Inst.addOperand(MCOperand::CreateImm(index)); 4382 4383 return S; 4384 } 4385 4386 4387 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4388 uint64_t Address, const void *Decoder) { 4389 DecodeStatus S = MCDisassembler::Success; 4390 4391 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4392 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4393 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4394 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4395 unsigned size = fieldFromInstruction(Insn, 10, 2); 4396 4397 unsigned align = 0; 4398 unsigned index = 0; 4399 unsigned inc = 1; 4400 switch (size) { 4401 default: 4402 return MCDisassembler::Fail; 4403 case 0: 4404 if (fieldFromInstruction(Insn, 4, 1)) 4405 return MCDisassembler::Fail; // UNDEFINED 4406 index = fieldFromInstruction(Insn, 5, 3); 4407 break; 4408 case 1: 4409 if (fieldFromInstruction(Insn, 4, 1)) 4410 return MCDisassembler::Fail; // UNDEFINED 4411 index = fieldFromInstruction(Insn, 6, 2); 4412 if (fieldFromInstruction(Insn, 5, 1)) 4413 inc = 2; 4414 break; 4415 case 2: 4416 if (fieldFromInstruction(Insn, 4, 2)) 4417 return MCDisassembler::Fail; // UNDEFINED 4418 index = fieldFromInstruction(Insn, 7, 1); 4419 if (fieldFromInstruction(Insn, 6, 1)) 4420 inc = 2; 4421 break; 4422 } 4423 4424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4425 return MCDisassembler::Fail; 4426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4427 return MCDisassembler::Fail; 4428 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4429 return MCDisassembler::Fail; 4430 4431 if (Rm != 0xF) { // Writeback 4432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4433 return MCDisassembler::Fail; 4434 } 4435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4436 return MCDisassembler::Fail; 4437 Inst.addOperand(MCOperand::CreateImm(align)); 4438 if (Rm != 0xF) { 4439 if (Rm != 0xD) { 4440 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4441 return MCDisassembler::Fail; 4442 } else 4443 Inst.addOperand(MCOperand::CreateReg(0)); 4444 } 4445 4446 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4447 return MCDisassembler::Fail; 4448 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4449 return MCDisassembler::Fail; 4450 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4451 return MCDisassembler::Fail; 4452 Inst.addOperand(MCOperand::CreateImm(index)); 4453 4454 return S; 4455 } 4456 4457 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4458 uint64_t Address, const void *Decoder) { 4459 DecodeStatus S = MCDisassembler::Success; 4460 4461 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4462 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4463 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4464 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4465 unsigned size = fieldFromInstruction(Insn, 10, 2); 4466 4467 unsigned align = 0; 4468 unsigned index = 0; 4469 unsigned inc = 1; 4470 switch (size) { 4471 default: 4472 return MCDisassembler::Fail; 4473 case 0: 4474 if (fieldFromInstruction(Insn, 4, 1)) 4475 return MCDisassembler::Fail; // UNDEFINED 4476 index = fieldFromInstruction(Insn, 5, 3); 4477 break; 4478 case 1: 4479 if (fieldFromInstruction(Insn, 4, 1)) 4480 return MCDisassembler::Fail; // UNDEFINED 4481 index = fieldFromInstruction(Insn, 6, 2); 4482 if (fieldFromInstruction(Insn, 5, 1)) 4483 inc = 2; 4484 break; 4485 case 2: 4486 if (fieldFromInstruction(Insn, 4, 2)) 4487 return MCDisassembler::Fail; // UNDEFINED 4488 index = fieldFromInstruction(Insn, 7, 1); 4489 if (fieldFromInstruction(Insn, 6, 1)) 4490 inc = 2; 4491 break; 4492 } 4493 4494 if (Rm != 0xF) { // Writeback 4495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4496 return MCDisassembler::Fail; 4497 } 4498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4499 return MCDisassembler::Fail; 4500 Inst.addOperand(MCOperand::CreateImm(align)); 4501 if (Rm != 0xF) { 4502 if (Rm != 0xD) { 4503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4504 return MCDisassembler::Fail; 4505 } else 4506 Inst.addOperand(MCOperand::CreateReg(0)); 4507 } 4508 4509 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4510 return MCDisassembler::Fail; 4511 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4512 return MCDisassembler::Fail; 4513 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4514 return MCDisassembler::Fail; 4515 Inst.addOperand(MCOperand::CreateImm(index)); 4516 4517 return S; 4518 } 4519 4520 4521 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4522 uint64_t Address, const void *Decoder) { 4523 DecodeStatus S = MCDisassembler::Success; 4524 4525 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4526 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4527 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4528 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4529 unsigned size = fieldFromInstruction(Insn, 10, 2); 4530 4531 unsigned align = 0; 4532 unsigned index = 0; 4533 unsigned inc = 1; 4534 switch (size) { 4535 default: 4536 return MCDisassembler::Fail; 4537 case 0: 4538 if (fieldFromInstruction(Insn, 4, 1)) 4539 align = 4; 4540 index = fieldFromInstruction(Insn, 5, 3); 4541 break; 4542 case 1: 4543 if (fieldFromInstruction(Insn, 4, 1)) 4544 align = 8; 4545 index = fieldFromInstruction(Insn, 6, 2); 4546 if (fieldFromInstruction(Insn, 5, 1)) 4547 inc = 2; 4548 break; 4549 case 2: 4550 switch (fieldFromInstruction(Insn, 4, 2)) { 4551 case 0: 4552 align = 0; break; 4553 case 3: 4554 return MCDisassembler::Fail; 4555 default: 4556 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4557 } 4558 4559 index = fieldFromInstruction(Insn, 7, 1); 4560 if (fieldFromInstruction(Insn, 6, 1)) 4561 inc = 2; 4562 break; 4563 } 4564 4565 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4566 return MCDisassembler::Fail; 4567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4568 return MCDisassembler::Fail; 4569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4570 return MCDisassembler::Fail; 4571 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4572 return MCDisassembler::Fail; 4573 4574 if (Rm != 0xF) { // Writeback 4575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4576 return MCDisassembler::Fail; 4577 } 4578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4579 return MCDisassembler::Fail; 4580 Inst.addOperand(MCOperand::CreateImm(align)); 4581 if (Rm != 0xF) { 4582 if (Rm != 0xD) { 4583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4584 return MCDisassembler::Fail; 4585 } else 4586 Inst.addOperand(MCOperand::CreateReg(0)); 4587 } 4588 4589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4590 return MCDisassembler::Fail; 4591 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4592 return MCDisassembler::Fail; 4593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4594 return MCDisassembler::Fail; 4595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4596 return MCDisassembler::Fail; 4597 Inst.addOperand(MCOperand::CreateImm(index)); 4598 4599 return S; 4600 } 4601 4602 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4603 uint64_t Address, const void *Decoder) { 4604 DecodeStatus S = MCDisassembler::Success; 4605 4606 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4607 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4608 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4609 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4610 unsigned size = fieldFromInstruction(Insn, 10, 2); 4611 4612 unsigned align = 0; 4613 unsigned index = 0; 4614 unsigned inc = 1; 4615 switch (size) { 4616 default: 4617 return MCDisassembler::Fail; 4618 case 0: 4619 if (fieldFromInstruction(Insn, 4, 1)) 4620 align = 4; 4621 index = fieldFromInstruction(Insn, 5, 3); 4622 break; 4623 case 1: 4624 if (fieldFromInstruction(Insn, 4, 1)) 4625 align = 8; 4626 index = fieldFromInstruction(Insn, 6, 2); 4627 if (fieldFromInstruction(Insn, 5, 1)) 4628 inc = 2; 4629 break; 4630 case 2: 4631 switch (fieldFromInstruction(Insn, 4, 2)) { 4632 case 0: 4633 align = 0; break; 4634 case 3: 4635 return MCDisassembler::Fail; 4636 default: 4637 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4638 } 4639 4640 index = fieldFromInstruction(Insn, 7, 1); 4641 if (fieldFromInstruction(Insn, 6, 1)) 4642 inc = 2; 4643 break; 4644 } 4645 4646 if (Rm != 0xF) { // Writeback 4647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4648 return MCDisassembler::Fail; 4649 } 4650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4651 return MCDisassembler::Fail; 4652 Inst.addOperand(MCOperand::CreateImm(align)); 4653 if (Rm != 0xF) { 4654 if (Rm != 0xD) { 4655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4656 return MCDisassembler::Fail; 4657 } else 4658 Inst.addOperand(MCOperand::CreateReg(0)); 4659 } 4660 4661 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4662 return MCDisassembler::Fail; 4663 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4664 return MCDisassembler::Fail; 4665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4666 return MCDisassembler::Fail; 4667 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4668 return MCDisassembler::Fail; 4669 Inst.addOperand(MCOperand::CreateImm(index)); 4670 4671 return S; 4672 } 4673 4674 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4675 uint64_t Address, const void *Decoder) { 4676 DecodeStatus S = MCDisassembler::Success; 4677 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4678 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4679 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4680 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4681 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4682 4683 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4684 S = MCDisassembler::SoftFail; 4685 4686 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4687 return MCDisassembler::Fail; 4688 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4689 return MCDisassembler::Fail; 4690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4691 return MCDisassembler::Fail; 4692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4693 return MCDisassembler::Fail; 4694 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4695 return MCDisassembler::Fail; 4696 4697 return S; 4698 } 4699 4700 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4701 uint64_t Address, const void *Decoder) { 4702 DecodeStatus S = MCDisassembler::Success; 4703 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4704 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4705 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4706 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4707 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4708 4709 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4710 S = MCDisassembler::SoftFail; 4711 4712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4713 return MCDisassembler::Fail; 4714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4715 return MCDisassembler::Fail; 4716 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4717 return MCDisassembler::Fail; 4718 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4719 return MCDisassembler::Fail; 4720 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4721 return MCDisassembler::Fail; 4722 4723 return S; 4724 } 4725 4726 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4727 uint64_t Address, const void *Decoder) { 4728 DecodeStatus S = MCDisassembler::Success; 4729 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4730 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4731 4732 if (pred == 0xF) { 4733 pred = 0xE; 4734 S = MCDisassembler::SoftFail; 4735 } 4736 4737 if (mask == 0x0) 4738 return MCDisassembler::Fail; 4739 4740 Inst.addOperand(MCOperand::CreateImm(pred)); 4741 Inst.addOperand(MCOperand::CreateImm(mask)); 4742 return S; 4743 } 4744 4745 static DecodeStatus 4746 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4747 uint64_t Address, const void *Decoder) { 4748 DecodeStatus S = MCDisassembler::Success; 4749 4750 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4751 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4752 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4753 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4754 unsigned W = fieldFromInstruction(Insn, 21, 1); 4755 unsigned U = fieldFromInstruction(Insn, 23, 1); 4756 unsigned P = fieldFromInstruction(Insn, 24, 1); 4757 bool writeback = (W == 1) | (P == 0); 4758 4759 addr |= (U << 8) | (Rn << 9); 4760 4761 if (writeback && (Rn == Rt || Rn == Rt2)) 4762 Check(S, MCDisassembler::SoftFail); 4763 if (Rt == Rt2) 4764 Check(S, MCDisassembler::SoftFail); 4765 4766 // Rt 4767 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4768 return MCDisassembler::Fail; 4769 // Rt2 4770 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4771 return MCDisassembler::Fail; 4772 // Writeback operand 4773 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4774 return MCDisassembler::Fail; 4775 // addr 4776 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4777 return MCDisassembler::Fail; 4778 4779 return S; 4780 } 4781 4782 static DecodeStatus 4783 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4784 uint64_t Address, const void *Decoder) { 4785 DecodeStatus S = MCDisassembler::Success; 4786 4787 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4788 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4789 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4790 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4791 unsigned W = fieldFromInstruction(Insn, 21, 1); 4792 unsigned U = fieldFromInstruction(Insn, 23, 1); 4793 unsigned P = fieldFromInstruction(Insn, 24, 1); 4794 bool writeback = (W == 1) | (P == 0); 4795 4796 addr |= (U << 8) | (Rn << 9); 4797 4798 if (writeback && (Rn == Rt || Rn == Rt2)) 4799 Check(S, MCDisassembler::SoftFail); 4800 4801 // Writeback operand 4802 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4803 return MCDisassembler::Fail; 4804 // Rt 4805 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4806 return MCDisassembler::Fail; 4807 // Rt2 4808 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4809 return MCDisassembler::Fail; 4810 // addr 4811 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4812 return MCDisassembler::Fail; 4813 4814 return S; 4815 } 4816 4817 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4818 uint64_t Address, const void *Decoder) { 4819 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4820 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4821 if (sign1 != sign2) return MCDisassembler::Fail; 4822 4823 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4824 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4825 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4826 Val |= sign1 << 12; 4827 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4828 4829 return MCDisassembler::Success; 4830 } 4831 4832 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4833 uint64_t Address, 4834 const void *Decoder) { 4835 DecodeStatus S = MCDisassembler::Success; 4836 4837 // Shift of "asr #32" is not allowed in Thumb2 mode. 4838 if (Val == 0x20) S = MCDisassembler::SoftFail; 4839 Inst.addOperand(MCOperand::CreateImm(Val)); 4840 return S; 4841 } 4842 4843 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4844 uint64_t Address, const void *Decoder) { 4845 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4846 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4847 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4848 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4849 4850 if (pred == 0xF) 4851 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4852 4853 DecodeStatus S = MCDisassembler::Success; 4854 4855 if (Rt == Rn || Rn == Rt2) 4856 S = MCDisassembler::SoftFail; 4857 4858 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4859 return MCDisassembler::Fail; 4860 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4861 return MCDisassembler::Fail; 4862 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4863 return MCDisassembler::Fail; 4864 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4865 return MCDisassembler::Fail; 4866 4867 return S; 4868 } 4869 4870 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 4871 uint64_t Address, const void *Decoder) { 4872 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4873 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4874 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4875 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4876 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4877 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4878 unsigned op = fieldFromInstruction(Insn, 5, 1); 4879 4880 DecodeStatus S = MCDisassembler::Success; 4881 4882 // VMOVv2f32 is ambiguous with these decodings. 4883 if (!(imm & 0x38) && cmode == 0xF) { 4884 if (op == 1) return MCDisassembler::Fail; 4885 Inst.setOpcode(ARM::VMOVv2f32); 4886 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4887 } 4888 4889 if (!(imm & 0x20)) return MCDisassembler::Fail; 4890 4891 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4892 return MCDisassembler::Fail; 4893 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4894 return MCDisassembler::Fail; 4895 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4896 4897 return S; 4898 } 4899 4900 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 4901 uint64_t Address, const void *Decoder) { 4902 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 4903 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 4904 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 4905 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 4906 unsigned imm = fieldFromInstruction(Insn, 16, 6); 4907 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 4908 unsigned op = fieldFromInstruction(Insn, 5, 1); 4909 4910 DecodeStatus S = MCDisassembler::Success; 4911 4912 // VMOVv4f32 is ambiguous with these decodings. 4913 if (!(imm & 0x38) && cmode == 0xF) { 4914 if (op == 1) return MCDisassembler::Fail; 4915 Inst.setOpcode(ARM::VMOVv4f32); 4916 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4917 } 4918 4919 if (!(imm & 0x20)) return MCDisassembler::Fail; 4920 4921 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4922 return MCDisassembler::Fail; 4923 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4924 return MCDisassembler::Fail; 4925 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4926 4927 return S; 4928 } 4929 4930 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 4931 uint64_t Address, const void *Decoder) { 4932 DecodeStatus S = MCDisassembler::Success; 4933 4934 unsigned Rn = fieldFromInstruction(Val, 16, 4); 4935 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4936 unsigned Rm = fieldFromInstruction(Val, 0, 4); 4937 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 4938 unsigned Cond = fieldFromInstruction(Val, 28, 4); 4939 4940 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 4941 S = MCDisassembler::SoftFail; 4942 4943 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4944 return MCDisassembler::Fail; 4945 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4946 return MCDisassembler::Fail; 4947 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 4948 return MCDisassembler::Fail; 4949 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 4950 return MCDisassembler::Fail; 4951 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 4952 return MCDisassembler::Fail; 4953 4954 return S; 4955 } 4956 4957 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 4958 uint64_t Address, const void *Decoder) { 4959 4960 DecodeStatus S = MCDisassembler::Success; 4961 4962 unsigned CRm = fieldFromInstruction(Val, 0, 4); 4963 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 4964 unsigned cop = fieldFromInstruction(Val, 8, 4); 4965 unsigned Rt = fieldFromInstruction(Val, 12, 4); 4966 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 4967 4968 if ((cop & ~0x1) == 0xa) 4969 return MCDisassembler::Fail; 4970 4971 if (Rt == Rt2) 4972 S = MCDisassembler::SoftFail; 4973 4974 Inst.addOperand(MCOperand::CreateImm(cop)); 4975 Inst.addOperand(MCOperand::CreateImm(opc1)); 4976 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4977 return MCDisassembler::Fail; 4978 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4979 return MCDisassembler::Fail; 4980 Inst.addOperand(MCOperand::CreateImm(CRm)); 4981 4982 return S; 4983 } 4984 4985