1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 137 uint64_t Address, const void *Decoder); 138 static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 139 uint64_t Address, const void *Decoder); 140 static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 143 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 144 uint64_t Address, const void *Decoder); 145 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 146 uint64_t Address, const void *Decoder); 147 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 148 uint64_t Address, const void *Decoder); 149 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 150 uint64_t Address, const void *Decoder); 151 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 152 uint64_t Address, const void *Decoder); 153 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 154 uint64_t Address, const void *Decoder); 155 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 156 uint64_t Address, const void *Decoder); 157 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 158 uint64_t Address, const void *Decoder); 159 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 160 uint64_t Address, const void *Decoder); 161 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 162 uint64_t Address, const void *Decoder); 163 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 164 uint64_t Address, const void *Decoder); 165 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 166 uint64_t Address, const void *Decoder); 167 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 168 uint64_t Address, const void *Decoder); 169 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 170 uint64_t Address, const void *Decoder); 171 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 172 uint64_t Address, const void *Decoder); 173 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 174 uint64_t Address, const void *Decoder); 175 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 176 uint64_t Address, const void *Decoder); 177 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 178 uint64_t Address, const void *Decoder); 179 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 192 #include "ARMGenDisassemblerTables.inc" 193 #include "ARMGenInstrInfo.inc" 194 #include "ARMGenEDInfo.inc" 195 196 using namespace llvm; 197 198 static MCDisassembler *createARMDisassembler(const Target &T) { 199 return new ARMDisassembler; 200 } 201 202 static MCDisassembler *createThumbDisassembler(const Target &T) { 203 return new ThumbDisassembler; 204 } 205 206 EDInstInfo *ARMDisassembler::getEDInfo() const { 207 return instInfoARM; 208 } 209 210 EDInstInfo *ThumbDisassembler::getEDInfo() const { 211 return instInfoARM; 212 } 213 214 215 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 216 const MemoryObject &Region, 217 uint64_t Address,raw_ostream &os) const { 218 uint8_t bytes[4]; 219 220 // We want to read exactly 4 bytes of data. 221 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 222 return false; 223 224 // Encoded as a small-endian 32-bit word in the stream. 225 uint32_t insn = (bytes[3] << 24) | 226 (bytes[2] << 16) | 227 (bytes[1] << 8) | 228 (bytes[0] << 0); 229 230 // Calling the auto-generated decoder function. 231 bool result = decodeARMInstruction32(MI, insn, Address, this); 232 if (result) { 233 Size = 4; 234 return true; 235 } 236 237 // Instructions that are shared between ARM and Thumb modes. 238 // FIXME: This shouldn't really exist. It's an artifact of the 239 // fact that we fail to encode a few instructions properly for Thumb. 240 MI.clear(); 241 result = decodeCommonInstruction32(MI, insn, Address, this); 242 if (result) { 243 Size = 4; 244 return true; 245 } 246 247 // VFP and NEON instructions, similarly, are shared between ARM 248 // and Thumb modes. 249 MI.clear(); 250 result = decodeVFPInstruction32(MI, insn, Address, this); 251 if (result) { 252 Size = 4; 253 return true; 254 } 255 256 MI.clear(); 257 result = decodeNEONDataInstruction32(MI, insn, Address, this); 258 if (result) { 259 Size = 4; 260 // Add a fake predicate operand, because we share these instruction 261 // definitions with Thumb2 where these instructions are predicable. 262 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 263 return true; 264 } 265 266 MI.clear(); 267 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 268 if (result) { 269 Size = 4; 270 // Add a fake predicate operand, because we share these instruction 271 // definitions with Thumb2 where these instructions are predicable. 272 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 273 return true; 274 } 275 276 MI.clear(); 277 result = decodeNEONDupInstruction32(MI, insn, Address, this); 278 if (result) { 279 Size = 4; 280 // Add a fake predicate operand, because we share these instruction 281 // definitions with Thumb2 where these instructions are predicable. 282 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 283 return true; 284 } 285 286 MI.clear(); 287 288 return false; 289 } 290 291 namespace llvm { 292 extern MCInstrDesc ARMInsts[]; 293 } 294 295 // Thumb1 instructions don't have explicit S bits. Rather, they 296 // implicitly set CPSR. Since it's not represented in the encoding, the 297 // auto-generated decoder won't inject the CPSR operand. We need to fix 298 // that as a post-pass. 299 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 300 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 301 MCInst::iterator I = MI.begin(); 302 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 303 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 304 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 305 return; 306 } 307 } 308 309 if (OpInfo[MI.size()].isOptionalDef() && 310 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 311 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 312 } 313 314 // Most Thumb instructions don't have explicit predicates in the 315 // encoding, but rather get their predicates from IT context. We need 316 // to fix up the predicate operands using this context information as a 317 // post-pass. 318 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 319 // A few instructions actually have predicates encoded in them. Don't 320 // try to overwrite it if we're seeing one of those. 321 switch (MI.getOpcode()) { 322 case ARM::tBcc: 323 case ARM::t2Bcc: 324 return; 325 default: 326 break; 327 } 328 329 // If we're in an IT block, base the predicate on that. Otherwise, 330 // assume a predicate of AL. 331 unsigned CC; 332 if (!ITBlock.empty()) { 333 CC = ITBlock.back(); 334 ITBlock.pop_back(); 335 } else 336 CC = ARMCC::AL; 337 338 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 339 MCInst::iterator I = MI.begin(); 340 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 341 if (OpInfo[i].isPredicate()) { 342 I = MI.insert(I, MCOperand::CreateImm(CC)); 343 ++I; 344 if (CC == ARMCC::AL) 345 MI.insert(I, MCOperand::CreateReg(0)); 346 else 347 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 348 return; 349 } 350 } 351 352 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 353 if (CC == ARMCC::AL) 354 MI.insert(MI.end(), MCOperand::CreateReg(0)); 355 else 356 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 357 } 358 359 // Thumb VFP instructions are a special case. Because we share their 360 // encodings between ARM and Thumb modes, and they are predicable in ARM 361 // mode, the auto-generated decoder will give them an (incorrect) 362 // predicate operand. We need to rewrite these operands based on the IT 363 // context as a post-pass. 364 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 365 unsigned CC; 366 if (!ITBlock.empty()) { 367 CC = ITBlock.back(); 368 ITBlock.pop_back(); 369 } else 370 CC = ARMCC::AL; 371 372 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 373 MCInst::iterator I = MI.begin(); 374 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 375 if (OpInfo[i].isPredicate() ) { 376 I->setImm(CC); 377 ++I; 378 if (CC == ARMCC::AL) 379 I->setReg(0); 380 else 381 I->setReg(ARM::CPSR); 382 return; 383 } 384 } 385 } 386 387 388 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 389 const MemoryObject &Region, 390 uint64_t Address,raw_ostream &os) const { 391 uint8_t bytes[4]; 392 393 // We want to read exactly 2 bytes of data. 394 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 395 return false; 396 397 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 398 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 399 if (result) { 400 Size = 2; 401 bool InITBlock = !ITBlock.empty(); 402 AddThumbPredicate(MI); 403 AddThumb1SBit(MI, InITBlock); 404 return true; 405 } 406 407 MI.clear(); 408 result = decodeThumb2Instruction16(MI, insn16, Address, this); 409 if (result) { 410 Size = 2; 411 AddThumbPredicate(MI); 412 413 // If we find an IT instruction, we need to parse its condition 414 // code and mask operands so that we can apply them correctly 415 // to the subsequent instructions. 416 if (MI.getOpcode() == ARM::t2IT) { 417 unsigned firstcond = MI.getOperand(0).getImm(); 418 uint32_t mask = MI.getOperand(1).getImm(); 419 unsigned zeros = CountTrailingZeros_32(mask); 420 mask >>= zeros+1; 421 422 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 423 if (firstcond ^ (mask & 1)) 424 ITBlock.push_back(firstcond ^ 1); 425 else 426 ITBlock.push_back(firstcond); 427 mask >>= 1; 428 } 429 ITBlock.push_back(firstcond); 430 } 431 432 return true; 433 } 434 435 // We want to read exactly 4 bytes of data. 436 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 437 return false; 438 439 uint32_t insn32 = (bytes[3] << 8) | 440 (bytes[2] << 0) | 441 (bytes[1] << 24) | 442 (bytes[0] << 16); 443 MI.clear(); 444 result = decodeThumbInstruction32(MI, insn32, Address, this); 445 if (result) { 446 Size = 4; 447 bool InITBlock = ITBlock.size(); 448 AddThumbPredicate(MI); 449 AddThumb1SBit(MI, InITBlock); 450 return true; 451 } 452 453 MI.clear(); 454 result = decodeThumb2Instruction32(MI, insn32, Address, this); 455 if (result) { 456 Size = 4; 457 AddThumbPredicate(MI); 458 return true; 459 } 460 461 MI.clear(); 462 result = decodeCommonInstruction32(MI, insn32, Address, this); 463 if (result) { 464 Size = 4; 465 AddThumbPredicate(MI); 466 return true; 467 } 468 469 MI.clear(); 470 result = decodeVFPInstruction32(MI, insn32, Address, this); 471 if (result) { 472 Size = 4; 473 UpdateThumbVFPPredicate(MI); 474 return true; 475 } 476 477 MI.clear(); 478 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 479 uint32_t NEONDataInsn = insn32; 480 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 481 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 482 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 483 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 484 if (result) { 485 Size = 4; 486 AddThumbPredicate(MI); 487 return true; 488 } 489 } 490 491 MI.clear(); 492 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); 493 if (result) { 494 Size = 4; 495 AddThumbPredicate(MI); 496 return true; 497 } 498 499 MI.clear(); 500 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 501 if (result) { 502 Size = 4; 503 AddThumbPredicate(MI); 504 return true; 505 } 506 507 return false; 508 } 509 510 511 extern "C" void LLVMInitializeARMDisassembler() { 512 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 513 createARMDisassembler); 514 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 515 createThumbDisassembler); 516 } 517 518 static const unsigned GPRDecoderTable[] = { 519 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 520 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 521 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 522 ARM::R12, ARM::SP, ARM::LR, ARM::PC 523 }; 524 525 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 526 uint64_t Address, const void *Decoder) { 527 if (RegNo > 15) 528 return false; 529 530 unsigned Register = GPRDecoderTable[RegNo]; 531 Inst.addOperand(MCOperand::CreateReg(Register)); 532 return true; 533 } 534 535 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 536 uint64_t Address, const void *Decoder) { 537 if (RegNo == 15) return false; 538 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 539 } 540 541 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 542 uint64_t Address, const void *Decoder) { 543 if (RegNo > 7) 544 return false; 545 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 546 } 547 548 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 549 uint64_t Address, const void *Decoder) { 550 unsigned Register = 0; 551 switch (RegNo) { 552 case 0: 553 Register = ARM::R0; 554 break; 555 case 1: 556 Register = ARM::R1; 557 break; 558 case 2: 559 Register = ARM::R2; 560 break; 561 case 3: 562 Register = ARM::R3; 563 break; 564 case 9: 565 Register = ARM::R9; 566 break; 567 case 12: 568 Register = ARM::R12; 569 break; 570 default: 571 return false; 572 } 573 574 Inst.addOperand(MCOperand::CreateReg(Register)); 575 return true; 576 } 577 578 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 579 uint64_t Address, const void *Decoder) { 580 if (RegNo == 13 || RegNo == 15) return false; 581 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 582 } 583 584 static const unsigned SPRDecoderTable[] = { 585 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 586 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 587 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 588 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 589 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 590 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 591 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 592 ARM::S28, ARM::S29, ARM::S30, ARM::S31 593 }; 594 595 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 596 uint64_t Address, const void *Decoder) { 597 if (RegNo > 31) 598 return false; 599 600 unsigned Register = SPRDecoderTable[RegNo]; 601 Inst.addOperand(MCOperand::CreateReg(Register)); 602 return true; 603 } 604 605 static const unsigned DPRDecoderTable[] = { 606 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 607 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 608 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 609 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 610 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 611 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 612 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 613 ARM::D28, ARM::D29, ARM::D30, ARM::D31 614 }; 615 616 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 617 uint64_t Address, const void *Decoder) { 618 if (RegNo > 31) 619 return false; 620 621 unsigned Register = DPRDecoderTable[RegNo]; 622 Inst.addOperand(MCOperand::CreateReg(Register)); 623 return true; 624 } 625 626 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 627 uint64_t Address, const void *Decoder) { 628 if (RegNo > 7) 629 return false; 630 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 631 } 632 633 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 634 uint64_t Address, const void *Decoder) { 635 if (RegNo > 15) 636 return false; 637 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 638 } 639 640 static const unsigned QPRDecoderTable[] = { 641 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 642 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 643 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 644 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 645 }; 646 647 648 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 649 uint64_t Address, const void *Decoder) { 650 if (RegNo > 31) 651 return false; 652 RegNo >>= 1; 653 654 unsigned Register = QPRDecoderTable[RegNo]; 655 Inst.addOperand(MCOperand::CreateReg(Register)); 656 return true; 657 } 658 659 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 660 uint64_t Address, const void *Decoder) { 661 if (Val == 0xF) return false; 662 // AL predicate is not allowed on Thumb1 branches. 663 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 664 return false; 665 Inst.addOperand(MCOperand::CreateImm(Val)); 666 if (Val == ARMCC::AL) { 667 Inst.addOperand(MCOperand::CreateReg(0)); 668 } else 669 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 670 return true; 671 } 672 673 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 674 uint64_t Address, const void *Decoder) { 675 if (Val) 676 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 677 else 678 Inst.addOperand(MCOperand::CreateReg(0)); 679 return true; 680 } 681 682 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 683 uint64_t Address, const void *Decoder) { 684 uint32_t imm = Val & 0xFF; 685 uint32_t rot = (Val & 0xF00) >> 7; 686 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 687 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 688 return true; 689 } 690 691 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 692 uint64_t Address, const void *Decoder) { 693 Val <<= 2; 694 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 695 return true; 696 } 697 698 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 699 uint64_t Address, const void *Decoder) { 700 701 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 702 unsigned type = fieldFromInstruction32(Val, 5, 2); 703 unsigned imm = fieldFromInstruction32(Val, 7, 5); 704 705 // Register-immediate 706 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 707 708 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 709 switch (type) { 710 case 0: 711 Shift = ARM_AM::lsl; 712 break; 713 case 1: 714 Shift = ARM_AM::lsr; 715 break; 716 case 2: 717 Shift = ARM_AM::asr; 718 break; 719 case 3: 720 Shift = ARM_AM::ror; 721 break; 722 } 723 724 if (Shift == ARM_AM::ror && imm == 0) 725 Shift = ARM_AM::rrx; 726 727 unsigned Op = Shift | (imm << 3); 728 Inst.addOperand(MCOperand::CreateImm(Op)); 729 730 return true; 731 } 732 733 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 734 uint64_t Address, const void *Decoder) { 735 736 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 737 unsigned type = fieldFromInstruction32(Val, 5, 2); 738 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 739 740 // Register-register 741 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 742 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 743 744 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 745 switch (type) { 746 case 0: 747 Shift = ARM_AM::lsl; 748 break; 749 case 1: 750 Shift = ARM_AM::lsr; 751 break; 752 case 2: 753 Shift = ARM_AM::asr; 754 break; 755 case 3: 756 Shift = ARM_AM::ror; 757 break; 758 } 759 760 Inst.addOperand(MCOperand::CreateImm(Shift)); 761 762 return true; 763 } 764 765 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 766 uint64_t Address, const void *Decoder) { 767 // Empty register lists are not allowed. 768 if (CountPopulation_32(Val) == 0) return false; 769 for (unsigned i = 0; i < 16; ++i) { 770 if (Val & (1 << i)) { 771 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 772 } 773 } 774 775 return true; 776 } 777 778 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 779 uint64_t Address, const void *Decoder) { 780 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 781 unsigned regs = Val & 0xFF; 782 783 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 784 for (unsigned i = 0; i < (regs - 1); ++i) { 785 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 786 } 787 788 return true; 789 } 790 791 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 792 uint64_t Address, const void *Decoder) { 793 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 794 unsigned regs = (Val & 0xFF) / 2; 795 796 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 797 for (unsigned i = 0; i < (regs - 1); ++i) { 798 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 799 } 800 801 return true; 802 } 803 804 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 805 uint64_t Address, const void *Decoder) { 806 // This operand encodes a mask of contiguous zeros between a specified MSB 807 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 808 // the mask of all bits LSB-and-lower, and then xor them to create 809 // the mask of that's all ones on [msb, lsb]. Finally we not it to 810 // create the final mask. 811 unsigned msb = fieldFromInstruction32(Val, 5, 5); 812 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 813 uint32_t msb_mask = (1 << (msb+1)) - 1; 814 uint32_t lsb_mask = (1 << lsb) - 1; 815 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 816 return true; 817 } 818 819 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 820 uint64_t Address, const void *Decoder) { 821 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 822 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 823 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 824 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 825 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 826 unsigned U = fieldFromInstruction32(Insn, 23, 1); 827 828 switch (Inst.getOpcode()) { 829 case ARM::LDC_OFFSET: 830 case ARM::LDC_PRE: 831 case ARM::LDC_POST: 832 case ARM::LDC_OPTION: 833 case ARM::LDCL_OFFSET: 834 case ARM::LDCL_PRE: 835 case ARM::LDCL_POST: 836 case ARM::LDCL_OPTION: 837 case ARM::STC_OFFSET: 838 case ARM::STC_PRE: 839 case ARM::STC_POST: 840 case ARM::STC_OPTION: 841 case ARM::STCL_OFFSET: 842 case ARM::STCL_PRE: 843 case ARM::STCL_POST: 844 case ARM::STCL_OPTION: 845 if (coproc == 0xA || coproc == 0xB) 846 return false; 847 break; 848 default: 849 break; 850 } 851 852 Inst.addOperand(MCOperand::CreateImm(coproc)); 853 Inst.addOperand(MCOperand::CreateImm(CRd)); 854 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 855 switch (Inst.getOpcode()) { 856 case ARM::LDC_OPTION: 857 case ARM::LDCL_OPTION: 858 case ARM::LDC2_OPTION: 859 case ARM::LDC2L_OPTION: 860 case ARM::STC_OPTION: 861 case ARM::STCL_OPTION: 862 case ARM::STC2_OPTION: 863 case ARM::STC2L_OPTION: 864 case ARM::LDCL_POST: 865 case ARM::STCL_POST: 866 break; 867 default: 868 Inst.addOperand(MCOperand::CreateReg(0)); 869 break; 870 } 871 872 unsigned P = fieldFromInstruction32(Insn, 24, 1); 873 unsigned W = fieldFromInstruction32(Insn, 21, 1); 874 875 bool writeback = (P == 0) || (W == 1); 876 unsigned idx_mode = 0; 877 if (P && writeback) 878 idx_mode = ARMII::IndexModePre; 879 else if (!P && writeback) 880 idx_mode = ARMII::IndexModePost; 881 882 switch (Inst.getOpcode()) { 883 case ARM::LDCL_POST: 884 case ARM::STCL_POST: 885 imm |= U << 8; 886 case ARM::LDC_OPTION: 887 case ARM::LDCL_OPTION: 888 case ARM::LDC2_OPTION: 889 case ARM::LDC2L_OPTION: 890 case ARM::STC_OPTION: 891 case ARM::STCL_OPTION: 892 case ARM::STC2_OPTION: 893 case ARM::STC2L_OPTION: 894 Inst.addOperand(MCOperand::CreateImm(imm)); 895 break; 896 default: 897 if (U) 898 Inst.addOperand(MCOperand::CreateImm( 899 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 900 else 901 Inst.addOperand(MCOperand::CreateImm( 902 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 903 break; 904 } 905 906 switch (Inst.getOpcode()) { 907 case ARM::LDC_OFFSET: 908 case ARM::LDC_PRE: 909 case ARM::LDC_POST: 910 case ARM::LDC_OPTION: 911 case ARM::LDCL_OFFSET: 912 case ARM::LDCL_PRE: 913 case ARM::LDCL_POST: 914 case ARM::LDCL_OPTION: 915 case ARM::STC_OFFSET: 916 case ARM::STC_PRE: 917 case ARM::STC_POST: 918 case ARM::STC_OPTION: 919 case ARM::STCL_OFFSET: 920 case ARM::STCL_PRE: 921 case ARM::STCL_POST: 922 case ARM::STCL_OPTION: 923 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 924 break; 925 default: 926 break; 927 } 928 929 return true; 930 } 931 932 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 933 uint64_t Address, const void *Decoder) { 934 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 935 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 936 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 937 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 938 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 939 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 940 unsigned P = fieldFromInstruction32(Insn, 24, 1); 941 unsigned W = fieldFromInstruction32(Insn, 21, 1); 942 943 // On stores, the writeback operand precedes Rt. 944 switch (Inst.getOpcode()) { 945 case ARM::STR_POST_IMM: 946 case ARM::STR_POST_REG: 947 case ARM::STRB_POST_IMM: 948 case ARM::STRB_POST_REG: 949 case ARM::STRT_POST_REG: 950 case ARM::STRT_POST_IMM: 951 case ARM::STRBT_POST_REG: 952 case ARM::STRBT_POST_IMM: 953 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 954 break; 955 default: 956 break; 957 } 958 959 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 960 961 // On loads, the writeback operand comes after Rt. 962 switch (Inst.getOpcode()) { 963 case ARM::LDR_POST_IMM: 964 case ARM::LDR_POST_REG: 965 case ARM::LDRB_POST_IMM: 966 case ARM::LDRB_POST_REG: 967 case ARM::LDR_PRE: 968 case ARM::LDRBT_POST_REG: 969 case ARM::LDRBT_POST_IMM: 970 case ARM::LDRT_POST_REG: 971 case ARM::LDRT_POST_IMM: 972 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 973 return false; 974 break; 975 default: 976 break; 977 } 978 979 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 980 981 ARM_AM::AddrOpc Op = ARM_AM::add; 982 if (!fieldFromInstruction32(Insn, 23, 1)) 983 Op = ARM_AM::sub; 984 985 bool writeback = (P == 0) || (W == 1); 986 unsigned idx_mode = 0; 987 if (P && writeback) 988 idx_mode = ARMII::IndexModePre; 989 else if (!P && writeback) 990 idx_mode = ARMII::IndexModePost; 991 992 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE 993 994 if (reg) { 995 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 996 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 997 switch( fieldFromInstruction32(Insn, 5, 2)) { 998 case 0: 999 Opc = ARM_AM::lsl; 1000 break; 1001 case 1: 1002 Opc = ARM_AM::lsr; 1003 break; 1004 case 2: 1005 Opc = ARM_AM::asr; 1006 break; 1007 case 3: 1008 Opc = ARM_AM::ror; 1009 break; 1010 default: 1011 return false; 1012 } 1013 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1014 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1015 1016 Inst.addOperand(MCOperand::CreateImm(imm)); 1017 } else { 1018 Inst.addOperand(MCOperand::CreateReg(0)); 1019 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1020 Inst.addOperand(MCOperand::CreateImm(tmp)); 1021 } 1022 1023 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1024 1025 return true; 1026 } 1027 1028 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1029 uint64_t Address, const void *Decoder) { 1030 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1031 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1032 unsigned type = fieldFromInstruction32(Val, 5, 2); 1033 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1034 unsigned U = fieldFromInstruction32(Val, 12, 1); 1035 1036 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1037 switch (type) { 1038 case 0: 1039 ShOp = ARM_AM::lsl; 1040 break; 1041 case 1: 1042 ShOp = ARM_AM::lsr; 1043 break; 1044 case 2: 1045 ShOp = ARM_AM::asr; 1046 break; 1047 case 3: 1048 ShOp = ARM_AM::ror; 1049 break; 1050 } 1051 1052 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1053 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1054 unsigned shift; 1055 if (U) 1056 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1057 else 1058 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1059 Inst.addOperand(MCOperand::CreateImm(shift)); 1060 1061 return true; 1062 } 1063 1064 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1065 uint64_t Address, const void *Decoder) { 1066 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1067 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1068 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1069 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1070 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1071 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1072 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1073 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1074 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1075 1076 bool writeback = (W == 1) | (P == 0); 1077 if (writeback) { // Writeback 1078 if (P) 1079 U |= ARMII::IndexModePre << 9; 1080 else 1081 U |= ARMII::IndexModePost << 9; 1082 1083 // On stores, the writeback operand precedes Rt. 1084 switch (Inst.getOpcode()) { 1085 case ARM::STRD: 1086 case ARM::STRD_PRE: 1087 case ARM::STRD_POST: 1088 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1089 return false; 1090 break; 1091 default: 1092 break; 1093 } 1094 } 1095 1096 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1097 return false; 1098 switch (Inst.getOpcode()) { 1099 case ARM::STRD: 1100 case ARM::STRD_PRE: 1101 case ARM::STRD_POST: 1102 case ARM::LDRD: 1103 case ARM::LDRD_PRE: 1104 case ARM::LDRD_POST: 1105 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1106 return false; 1107 break; 1108 default: 1109 break; 1110 } 1111 1112 if (writeback) { 1113 // On loads, the writeback operand comes after Rt. 1114 switch (Inst.getOpcode()) { 1115 case ARM::LDRD: 1116 case ARM::LDRD_PRE: 1117 case ARM::LDRD_POST: 1118 case ARM::LDRHTr: 1119 case ARM::LDRSBTr: 1120 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1121 return false; 1122 break; 1123 default: 1124 break; 1125 } 1126 } 1127 1128 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1129 return false; 1130 1131 if (type) { 1132 Inst.addOperand(MCOperand::CreateReg(0)); 1133 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1134 } else { 1135 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1136 return false; 1137 Inst.addOperand(MCOperand::CreateImm(U)); 1138 } 1139 1140 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1141 1142 return true; 1143 } 1144 1145 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1146 uint64_t Address, const void *Decoder) { 1147 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1148 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1149 1150 switch (mode) { 1151 case 0: 1152 mode = ARM_AM::da; 1153 break; 1154 case 1: 1155 mode = ARM_AM::ia; 1156 break; 1157 case 2: 1158 mode = ARM_AM::db; 1159 break; 1160 case 3: 1161 mode = ARM_AM::ib; 1162 break; 1163 } 1164 1165 Inst.addOperand(MCOperand::CreateImm(mode)); 1166 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1167 1168 return true; 1169 } 1170 1171 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1172 unsigned Insn, 1173 uint64_t Address, const void *Decoder) { 1174 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1175 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1176 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1177 1178 if (pred == 0xF) { 1179 switch (Inst.getOpcode()) { 1180 case ARM::STMDA: 1181 Inst.setOpcode(ARM::RFEDA); 1182 break; 1183 case ARM::STMDA_UPD: 1184 Inst.setOpcode(ARM::RFEDA_UPD); 1185 break; 1186 case ARM::STMDB: 1187 Inst.setOpcode(ARM::RFEDB); 1188 break; 1189 case ARM::STMDB_UPD: 1190 Inst.setOpcode(ARM::RFEDB_UPD); 1191 break; 1192 case ARM::STMIA: 1193 Inst.setOpcode(ARM::RFEIA); 1194 break; 1195 case ARM::STMIA_UPD: 1196 Inst.setOpcode(ARM::RFEIA_UPD); 1197 break; 1198 case ARM::STMIB: 1199 Inst.setOpcode(ARM::RFEIB); 1200 break; 1201 case ARM::STMIB_UPD: 1202 Inst.setOpcode(ARM::RFEIB_UPD); 1203 break; 1204 } 1205 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1206 } 1207 1208 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1209 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1210 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1211 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1212 return false; 1213 1214 return true; 1215 } 1216 1217 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1218 uint64_t Address, const void *Decoder) { 1219 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1220 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1221 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1222 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1223 1224 // imod == '01' --> UNPREDICTABLE 1225 if (imod == 1) return false; 1226 1227 if (M && mode && imod && iflags) { 1228 Inst.setOpcode(ARM::CPS3p); 1229 Inst.addOperand(MCOperand::CreateImm(imod)); 1230 Inst.addOperand(MCOperand::CreateImm(iflags)); 1231 Inst.addOperand(MCOperand::CreateImm(mode)); 1232 return true; 1233 } else if (!mode && !M) { 1234 Inst.setOpcode(ARM::CPS2p); 1235 Inst.addOperand(MCOperand::CreateImm(imod)); 1236 Inst.addOperand(MCOperand::CreateImm(iflags)); 1237 return true; 1238 } else if (!imod && !iflags && M) { 1239 Inst.setOpcode(ARM::CPS1p); 1240 Inst.addOperand(MCOperand::CreateImm(mode)); 1241 return true; 1242 } 1243 1244 return false; 1245 } 1246 1247 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1248 uint64_t Address, const void *Decoder) { 1249 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1250 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1251 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1252 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1253 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1254 1255 if (pred == 0xF) 1256 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1257 1258 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1259 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1260 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1261 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1262 return false; 1263 1264 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1265 1266 return true; 1267 } 1268 1269 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1270 uint64_t Address, const void *Decoder) { 1271 unsigned add = fieldFromInstruction32(Val, 12, 1); 1272 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1273 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1274 1275 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1276 return false; 1277 1278 if (!add) imm *= -1; 1279 if (imm == 0 && !add) imm = INT32_MIN; 1280 Inst.addOperand(MCOperand::CreateImm(imm)); 1281 1282 return true; 1283 } 1284 1285 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1286 uint64_t Address, const void *Decoder) { 1287 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1288 unsigned U = fieldFromInstruction32(Val, 8, 1); 1289 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1290 1291 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1292 return false; 1293 1294 if (U) 1295 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1296 else 1297 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1298 1299 return true; 1300 } 1301 1302 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1303 uint64_t Address, const void *Decoder) { 1304 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1305 } 1306 1307 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1308 uint64_t Address, const void *Decoder) { 1309 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1310 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1311 1312 if (pred == 0xF) { 1313 Inst.setOpcode(ARM::BLXi); 1314 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1315 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1316 return true; 1317 } 1318 1319 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1320 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1321 1322 return true; 1323 } 1324 1325 1326 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1327 uint64_t Address, const void *Decoder) { 1328 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1329 return true; 1330 } 1331 1332 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1333 uint64_t Address, const void *Decoder) { 1334 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1335 unsigned align = fieldFromInstruction32(Val, 4, 2); 1336 1337 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1338 return false; 1339 if (!align) 1340 Inst.addOperand(MCOperand::CreateImm(0)); 1341 else 1342 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1343 1344 return true; 1345 } 1346 1347 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1348 uint64_t Address, const void *Decoder) { 1349 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1350 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1351 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1352 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1353 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1354 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1355 1356 // First output register 1357 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1358 1359 // Second output register 1360 switch (Inst.getOpcode()) { 1361 case ARM::VLD1q8: 1362 case ARM::VLD1q16: 1363 case ARM::VLD1q32: 1364 case ARM::VLD1q64: 1365 case ARM::VLD1q8_UPD: 1366 case ARM::VLD1q16_UPD: 1367 case ARM::VLD1q32_UPD: 1368 case ARM::VLD1q64_UPD: 1369 case ARM::VLD1d8T: 1370 case ARM::VLD1d16T: 1371 case ARM::VLD1d32T: 1372 case ARM::VLD1d64T: 1373 case ARM::VLD1d8T_UPD: 1374 case ARM::VLD1d16T_UPD: 1375 case ARM::VLD1d32T_UPD: 1376 case ARM::VLD1d64T_UPD: 1377 case ARM::VLD1d8Q: 1378 case ARM::VLD1d16Q: 1379 case ARM::VLD1d32Q: 1380 case ARM::VLD1d64Q: 1381 case ARM::VLD1d8Q_UPD: 1382 case ARM::VLD1d16Q_UPD: 1383 case ARM::VLD1d32Q_UPD: 1384 case ARM::VLD1d64Q_UPD: 1385 case ARM::VLD2d8: 1386 case ARM::VLD2d16: 1387 case ARM::VLD2d32: 1388 case ARM::VLD2d8_UPD: 1389 case ARM::VLD2d16_UPD: 1390 case ARM::VLD2d32_UPD: 1391 case ARM::VLD2q8: 1392 case ARM::VLD2q16: 1393 case ARM::VLD2q32: 1394 case ARM::VLD2q8_UPD: 1395 case ARM::VLD2q16_UPD: 1396 case ARM::VLD2q32_UPD: 1397 case ARM::VLD3d8: 1398 case ARM::VLD3d16: 1399 case ARM::VLD3d32: 1400 case ARM::VLD3d8_UPD: 1401 case ARM::VLD3d16_UPD: 1402 case ARM::VLD3d32_UPD: 1403 case ARM::VLD4d8: 1404 case ARM::VLD4d16: 1405 case ARM::VLD4d32: 1406 case ARM::VLD4d8_UPD: 1407 case ARM::VLD4d16_UPD: 1408 case ARM::VLD4d32_UPD: 1409 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1410 break; 1411 case ARM::VLD2b8: 1412 case ARM::VLD2b16: 1413 case ARM::VLD2b32: 1414 case ARM::VLD2b8_UPD: 1415 case ARM::VLD2b16_UPD: 1416 case ARM::VLD2b32_UPD: 1417 case ARM::VLD3q8: 1418 case ARM::VLD3q16: 1419 case ARM::VLD3q32: 1420 case ARM::VLD3q8_UPD: 1421 case ARM::VLD3q16_UPD: 1422 case ARM::VLD3q32_UPD: 1423 case ARM::VLD4q8: 1424 case ARM::VLD4q16: 1425 case ARM::VLD4q32: 1426 case ARM::VLD4q8_UPD: 1427 case ARM::VLD4q16_UPD: 1428 case ARM::VLD4q32_UPD: 1429 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1430 default: 1431 break; 1432 } 1433 1434 // Third output register 1435 switch(Inst.getOpcode()) { 1436 case ARM::VLD1d8T: 1437 case ARM::VLD1d16T: 1438 case ARM::VLD1d32T: 1439 case ARM::VLD1d64T: 1440 case ARM::VLD1d8T_UPD: 1441 case ARM::VLD1d16T_UPD: 1442 case ARM::VLD1d32T_UPD: 1443 case ARM::VLD1d64T_UPD: 1444 case ARM::VLD1d8Q: 1445 case ARM::VLD1d16Q: 1446 case ARM::VLD1d32Q: 1447 case ARM::VLD1d64Q: 1448 case ARM::VLD1d8Q_UPD: 1449 case ARM::VLD1d16Q_UPD: 1450 case ARM::VLD1d32Q_UPD: 1451 case ARM::VLD1d64Q_UPD: 1452 case ARM::VLD2q8: 1453 case ARM::VLD2q16: 1454 case ARM::VLD2q32: 1455 case ARM::VLD2q8_UPD: 1456 case ARM::VLD2q16_UPD: 1457 case ARM::VLD2q32_UPD: 1458 case ARM::VLD3d8: 1459 case ARM::VLD3d16: 1460 case ARM::VLD3d32: 1461 case ARM::VLD3d8_UPD: 1462 case ARM::VLD3d16_UPD: 1463 case ARM::VLD3d32_UPD: 1464 case ARM::VLD4d8: 1465 case ARM::VLD4d16: 1466 case ARM::VLD4d32: 1467 case ARM::VLD4d8_UPD: 1468 case ARM::VLD4d16_UPD: 1469 case ARM::VLD4d32_UPD: 1470 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1471 break; 1472 case ARM::VLD3q8: 1473 case ARM::VLD3q16: 1474 case ARM::VLD3q32: 1475 case ARM::VLD3q8_UPD: 1476 case ARM::VLD3q16_UPD: 1477 case ARM::VLD3q32_UPD: 1478 case ARM::VLD4q8: 1479 case ARM::VLD4q16: 1480 case ARM::VLD4q32: 1481 case ARM::VLD4q8_UPD: 1482 case ARM::VLD4q16_UPD: 1483 case ARM::VLD4q32_UPD: 1484 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1485 break; 1486 default: 1487 break; 1488 } 1489 1490 // Fourth output register 1491 switch (Inst.getOpcode()) { 1492 case ARM::VLD1d8Q: 1493 case ARM::VLD1d16Q: 1494 case ARM::VLD1d32Q: 1495 case ARM::VLD1d64Q: 1496 case ARM::VLD1d8Q_UPD: 1497 case ARM::VLD1d16Q_UPD: 1498 case ARM::VLD1d32Q_UPD: 1499 case ARM::VLD1d64Q_UPD: 1500 case ARM::VLD2q8: 1501 case ARM::VLD2q16: 1502 case ARM::VLD2q32: 1503 case ARM::VLD2q8_UPD: 1504 case ARM::VLD2q16_UPD: 1505 case ARM::VLD2q32_UPD: 1506 case ARM::VLD4d8: 1507 case ARM::VLD4d16: 1508 case ARM::VLD4d32: 1509 case ARM::VLD4d8_UPD: 1510 case ARM::VLD4d16_UPD: 1511 case ARM::VLD4d32_UPD: 1512 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1513 break; 1514 case ARM::VLD4q8: 1515 case ARM::VLD4q16: 1516 case ARM::VLD4q32: 1517 case ARM::VLD4q8_UPD: 1518 case ARM::VLD4q16_UPD: 1519 case ARM::VLD4q32_UPD: 1520 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1521 break; 1522 default: 1523 break; 1524 } 1525 1526 // Writeback operand 1527 switch (Inst.getOpcode()) { 1528 case ARM::VLD1d8_UPD: 1529 case ARM::VLD1d16_UPD: 1530 case ARM::VLD1d32_UPD: 1531 case ARM::VLD1d64_UPD: 1532 case ARM::VLD1q8_UPD: 1533 case ARM::VLD1q16_UPD: 1534 case ARM::VLD1q32_UPD: 1535 case ARM::VLD1q64_UPD: 1536 case ARM::VLD1d8T_UPD: 1537 case ARM::VLD1d16T_UPD: 1538 case ARM::VLD1d32T_UPD: 1539 case ARM::VLD1d64T_UPD: 1540 case ARM::VLD1d8Q_UPD: 1541 case ARM::VLD1d16Q_UPD: 1542 case ARM::VLD1d32Q_UPD: 1543 case ARM::VLD1d64Q_UPD: 1544 case ARM::VLD2d8_UPD: 1545 case ARM::VLD2d16_UPD: 1546 case ARM::VLD2d32_UPD: 1547 case ARM::VLD2q8_UPD: 1548 case ARM::VLD2q16_UPD: 1549 case ARM::VLD2q32_UPD: 1550 case ARM::VLD2b8_UPD: 1551 case ARM::VLD2b16_UPD: 1552 case ARM::VLD2b32_UPD: 1553 case ARM::VLD3d8_UPD: 1554 case ARM::VLD3d16_UPD: 1555 case ARM::VLD3d32_UPD: 1556 case ARM::VLD3q8_UPD: 1557 case ARM::VLD3q16_UPD: 1558 case ARM::VLD3q32_UPD: 1559 case ARM::VLD4d8_UPD: 1560 case ARM::VLD4d16_UPD: 1561 case ARM::VLD4d32_UPD: 1562 case ARM::VLD4q8_UPD: 1563 case ARM::VLD4q16_UPD: 1564 case ARM::VLD4q32_UPD: 1565 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1566 break; 1567 default: 1568 break; 1569 } 1570 1571 // AddrMode6 Base (register+alignment) 1572 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1573 1574 // AddrMode6 Offset (register) 1575 if (Rm == 0xD) 1576 Inst.addOperand(MCOperand::CreateReg(0)); 1577 else if (Rm != 0xF) { 1578 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1579 return false; 1580 } 1581 1582 return true; 1583 } 1584 1585 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1586 uint64_t Address, const void *Decoder) { 1587 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1588 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1589 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1590 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1591 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1592 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1593 1594 // Writeback Operand 1595 switch (Inst.getOpcode()) { 1596 case ARM::VST1d8_UPD: 1597 case ARM::VST1d16_UPD: 1598 case ARM::VST1d32_UPD: 1599 case ARM::VST1d64_UPD: 1600 case ARM::VST1q8_UPD: 1601 case ARM::VST1q16_UPD: 1602 case ARM::VST1q32_UPD: 1603 case ARM::VST1q64_UPD: 1604 case ARM::VST1d8T_UPD: 1605 case ARM::VST1d16T_UPD: 1606 case ARM::VST1d32T_UPD: 1607 case ARM::VST1d64T_UPD: 1608 case ARM::VST1d8Q_UPD: 1609 case ARM::VST1d16Q_UPD: 1610 case ARM::VST1d32Q_UPD: 1611 case ARM::VST1d64Q_UPD: 1612 case ARM::VST2d8_UPD: 1613 case ARM::VST2d16_UPD: 1614 case ARM::VST2d32_UPD: 1615 case ARM::VST2q8_UPD: 1616 case ARM::VST2q16_UPD: 1617 case ARM::VST2q32_UPD: 1618 case ARM::VST2b8_UPD: 1619 case ARM::VST2b16_UPD: 1620 case ARM::VST2b32_UPD: 1621 case ARM::VST3d8_UPD: 1622 case ARM::VST3d16_UPD: 1623 case ARM::VST3d32_UPD: 1624 case ARM::VST3q8_UPD: 1625 case ARM::VST3q16_UPD: 1626 case ARM::VST3q32_UPD: 1627 case ARM::VST4d8_UPD: 1628 case ARM::VST4d16_UPD: 1629 case ARM::VST4d32_UPD: 1630 case ARM::VST4q8_UPD: 1631 case ARM::VST4q16_UPD: 1632 case ARM::VST4q32_UPD: 1633 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1634 return false; 1635 break; 1636 default: 1637 break; 1638 } 1639 1640 // AddrMode6 Base (register+alignment) 1641 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1642 1643 // AddrMode6 Offset (register) 1644 if (Rm == 0xD) 1645 Inst.addOperand(MCOperand::CreateReg(0)); 1646 else if (Rm != 0xF) { 1647 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1648 } 1649 1650 // First input register 1651 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1652 1653 // Second input register 1654 switch (Inst.getOpcode()) { 1655 case ARM::VST1q8: 1656 case ARM::VST1q16: 1657 case ARM::VST1q32: 1658 case ARM::VST1q64: 1659 case ARM::VST1q8_UPD: 1660 case ARM::VST1q16_UPD: 1661 case ARM::VST1q32_UPD: 1662 case ARM::VST1q64_UPD: 1663 case ARM::VST1d8T: 1664 case ARM::VST1d16T: 1665 case ARM::VST1d32T: 1666 case ARM::VST1d64T: 1667 case ARM::VST1d8T_UPD: 1668 case ARM::VST1d16T_UPD: 1669 case ARM::VST1d32T_UPD: 1670 case ARM::VST1d64T_UPD: 1671 case ARM::VST1d8Q: 1672 case ARM::VST1d16Q: 1673 case ARM::VST1d32Q: 1674 case ARM::VST1d64Q: 1675 case ARM::VST1d8Q_UPD: 1676 case ARM::VST1d16Q_UPD: 1677 case ARM::VST1d32Q_UPD: 1678 case ARM::VST1d64Q_UPD: 1679 case ARM::VST2d8: 1680 case ARM::VST2d16: 1681 case ARM::VST2d32: 1682 case ARM::VST2d8_UPD: 1683 case ARM::VST2d16_UPD: 1684 case ARM::VST2d32_UPD: 1685 case ARM::VST2q8: 1686 case ARM::VST2q16: 1687 case ARM::VST2q32: 1688 case ARM::VST2q8_UPD: 1689 case ARM::VST2q16_UPD: 1690 case ARM::VST2q32_UPD: 1691 case ARM::VST3d8: 1692 case ARM::VST3d16: 1693 case ARM::VST3d32: 1694 case ARM::VST3d8_UPD: 1695 case ARM::VST3d16_UPD: 1696 case ARM::VST3d32_UPD: 1697 case ARM::VST4d8: 1698 case ARM::VST4d16: 1699 case ARM::VST4d32: 1700 case ARM::VST4d8_UPD: 1701 case ARM::VST4d16_UPD: 1702 case ARM::VST4d32_UPD: 1703 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1704 break; 1705 case ARM::VST2b8: 1706 case ARM::VST2b16: 1707 case ARM::VST2b32: 1708 case ARM::VST2b8_UPD: 1709 case ARM::VST2b16_UPD: 1710 case ARM::VST2b32_UPD: 1711 case ARM::VST3q8: 1712 case ARM::VST3q16: 1713 case ARM::VST3q32: 1714 case ARM::VST3q8_UPD: 1715 case ARM::VST3q16_UPD: 1716 case ARM::VST3q32_UPD: 1717 case ARM::VST4q8: 1718 case ARM::VST4q16: 1719 case ARM::VST4q32: 1720 case ARM::VST4q8_UPD: 1721 case ARM::VST4q16_UPD: 1722 case ARM::VST4q32_UPD: 1723 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1724 break; 1725 default: 1726 break; 1727 } 1728 1729 // Third input register 1730 switch (Inst.getOpcode()) { 1731 case ARM::VST1d8T: 1732 case ARM::VST1d16T: 1733 case ARM::VST1d32T: 1734 case ARM::VST1d64T: 1735 case ARM::VST1d8T_UPD: 1736 case ARM::VST1d16T_UPD: 1737 case ARM::VST1d32T_UPD: 1738 case ARM::VST1d64T_UPD: 1739 case ARM::VST1d8Q: 1740 case ARM::VST1d16Q: 1741 case ARM::VST1d32Q: 1742 case ARM::VST1d64Q: 1743 case ARM::VST1d8Q_UPD: 1744 case ARM::VST1d16Q_UPD: 1745 case ARM::VST1d32Q_UPD: 1746 case ARM::VST1d64Q_UPD: 1747 case ARM::VST2q8: 1748 case ARM::VST2q16: 1749 case ARM::VST2q32: 1750 case ARM::VST2q8_UPD: 1751 case ARM::VST2q16_UPD: 1752 case ARM::VST2q32_UPD: 1753 case ARM::VST3d8: 1754 case ARM::VST3d16: 1755 case ARM::VST3d32: 1756 case ARM::VST3d8_UPD: 1757 case ARM::VST3d16_UPD: 1758 case ARM::VST3d32_UPD: 1759 case ARM::VST4d8: 1760 case ARM::VST4d16: 1761 case ARM::VST4d32: 1762 case ARM::VST4d8_UPD: 1763 case ARM::VST4d16_UPD: 1764 case ARM::VST4d32_UPD: 1765 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1766 break; 1767 case ARM::VST3q8: 1768 case ARM::VST3q16: 1769 case ARM::VST3q32: 1770 case ARM::VST3q8_UPD: 1771 case ARM::VST3q16_UPD: 1772 case ARM::VST3q32_UPD: 1773 case ARM::VST4q8: 1774 case ARM::VST4q16: 1775 case ARM::VST4q32: 1776 case ARM::VST4q8_UPD: 1777 case ARM::VST4q16_UPD: 1778 case ARM::VST4q32_UPD: 1779 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1780 break; 1781 default: 1782 break; 1783 } 1784 1785 // Fourth input register 1786 switch (Inst.getOpcode()) { 1787 case ARM::VST1d8Q: 1788 case ARM::VST1d16Q: 1789 case ARM::VST1d32Q: 1790 case ARM::VST1d64Q: 1791 case ARM::VST1d8Q_UPD: 1792 case ARM::VST1d16Q_UPD: 1793 case ARM::VST1d32Q_UPD: 1794 case ARM::VST1d64Q_UPD: 1795 case ARM::VST2q8: 1796 case ARM::VST2q16: 1797 case ARM::VST2q32: 1798 case ARM::VST2q8_UPD: 1799 case ARM::VST2q16_UPD: 1800 case ARM::VST2q32_UPD: 1801 case ARM::VST4d8: 1802 case ARM::VST4d16: 1803 case ARM::VST4d32: 1804 case ARM::VST4d8_UPD: 1805 case ARM::VST4d16_UPD: 1806 case ARM::VST4d32_UPD: 1807 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1808 break; 1809 case ARM::VST4q8: 1810 case ARM::VST4q16: 1811 case ARM::VST4q32: 1812 case ARM::VST4q8_UPD: 1813 case ARM::VST4q16_UPD: 1814 case ARM::VST4q32_UPD: 1815 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1816 break; 1817 default: 1818 break; 1819 } 1820 1821 return true; 1822 } 1823 1824 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1825 uint64_t Address, const void *Decoder) { 1826 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1827 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1828 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1829 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1830 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1831 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1832 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1833 1834 align *= (1 << size); 1835 1836 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1837 if (regs == 2) { 1838 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1839 } 1840 if (Rm == 0xD) { 1841 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1842 } 1843 1844 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1845 Inst.addOperand(MCOperand::CreateImm(align)); 1846 1847 if (Rm == 0xD) 1848 Inst.addOperand(MCOperand::CreateReg(0)); 1849 else if (Rm != 0xF) { 1850 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1851 } 1852 1853 return true; 1854 } 1855 1856 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1857 uint64_t Address, const void *Decoder) { 1858 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1859 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1860 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1861 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1862 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1863 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1864 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1865 align *= 2*size; 1866 1867 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1868 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1869 if (Rm == 0xD) { 1870 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1871 } 1872 1873 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1874 Inst.addOperand(MCOperand::CreateImm(align)); 1875 1876 if (Rm == 0xD) 1877 Inst.addOperand(MCOperand::CreateReg(0)); 1878 else if (Rm != 0xF) { 1879 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1880 } 1881 1882 return true; 1883 } 1884 1885 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1886 uint64_t Address, const void *Decoder) { 1887 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1888 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1889 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1890 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1891 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1892 1893 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1894 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1895 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1896 return false; 1897 if (Rm == 0xD) { 1898 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1899 } 1900 1901 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1902 Inst.addOperand(MCOperand::CreateImm(0)); 1903 1904 if (Rm == 0xD) 1905 Inst.addOperand(MCOperand::CreateReg(0)); 1906 else if (Rm != 0xF) { 1907 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1908 } 1909 1910 return true; 1911 } 1912 1913 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1914 uint64_t Address, const void *Decoder) { 1915 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1916 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1917 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1918 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1919 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1920 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1921 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1922 1923 if (size == 0x3) { 1924 size = 4; 1925 align = 16; 1926 } else { 1927 if (size == 2) { 1928 size = 1 << size; 1929 align *= 8; 1930 } else { 1931 size = 1 << size; 1932 align *= 4*size; 1933 } 1934 } 1935 1936 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1937 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1938 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1939 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 1940 return false; 1941 if (Rm == 0xD) { 1942 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1943 } 1944 1945 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1946 Inst.addOperand(MCOperand::CreateImm(align)); 1947 1948 if (Rm == 0xD) 1949 Inst.addOperand(MCOperand::CreateReg(0)); 1950 else if (Rm != 0xF) { 1951 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1952 } 1953 1954 return true; 1955 } 1956 1957 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1958 uint64_t Address, const void *Decoder) { 1959 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1960 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1961 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1962 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1963 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1964 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1965 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1966 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1967 1968 if (Q) { 1969 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1970 } else { 1971 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1972 } 1973 1974 Inst.addOperand(MCOperand::CreateImm(imm)); 1975 1976 switch (Inst.getOpcode()) { 1977 case ARM::VORRiv4i16: 1978 case ARM::VORRiv2i32: 1979 case ARM::VBICiv4i16: 1980 case ARM::VBICiv2i32: 1981 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1982 break; 1983 case ARM::VORRiv8i16: 1984 case ARM::VORRiv4i32: 1985 case ARM::VBICiv8i16: 1986 case ARM::VBICiv4i32: 1987 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1988 break; 1989 default: 1990 break; 1991 } 1992 1993 return true; 1994 } 1995 1996 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 1997 uint64_t Address, const void *Decoder) { 1998 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1999 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2000 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2001 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2002 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2003 2004 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2005 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2006 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2007 2008 return true; 2009 } 2010 2011 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2012 uint64_t Address, const void *Decoder) { 2013 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2014 return true; 2015 } 2016 2017 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2018 uint64_t Address, const void *Decoder) { 2019 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2020 return true; 2021 } 2022 2023 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2024 uint64_t Address, const void *Decoder) { 2025 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2026 return true; 2027 } 2028 2029 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2030 uint64_t Address, const void *Decoder) { 2031 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2032 return true; 2033 } 2034 2035 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2036 uint64_t Address, const void *Decoder) { 2037 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2038 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2039 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2040 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2041 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2042 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2043 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2044 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2045 2046 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2047 if (op) { 2048 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2049 } 2050 2051 for (unsigned i = 0; i < length; ++i) { 2052 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2053 } 2054 2055 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2056 2057 return true; 2058 } 2059 2060 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2061 uint64_t Address, const void *Decoder) { 2062 // The immediate needs to be a fully instantiated float. However, the 2063 // auto-generated decoder is only able to fill in some of the bits 2064 // necessary. For instance, the 'b' bit is replicated multiple times, 2065 // and is even present in inverted form in one bit. We do a little 2066 // binary parsing here to fill in those missing bits, and then 2067 // reinterpret it all as a float. 2068 union { 2069 uint32_t integer; 2070 float fp; 2071 } fp_conv; 2072 2073 fp_conv.integer = Val; 2074 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2075 fp_conv.integer |= b << 26; 2076 fp_conv.integer |= b << 27; 2077 fp_conv.integer |= b << 28; 2078 fp_conv.integer |= b << 29; 2079 fp_conv.integer |= (~b & 0x1) << 30; 2080 2081 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2082 return true; 2083 } 2084 2085 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2086 uint64_t Address, const void *Decoder) { 2087 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2088 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2089 2090 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2091 2092 if (Inst.getOpcode() == ARM::tADR) 2093 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2094 else if (Inst.getOpcode() == ARM::tADDrSPi) 2095 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2096 else 2097 return false; 2098 2099 Inst.addOperand(MCOperand::CreateImm(imm)); 2100 return true; 2101 } 2102 2103 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2104 uint64_t Address, const void *Decoder) { 2105 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2106 return true; 2107 } 2108 2109 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2110 uint64_t Address, const void *Decoder) { 2111 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2112 return true; 2113 } 2114 2115 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2116 uint64_t Address, const void *Decoder) { 2117 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2118 return true; 2119 } 2120 2121 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2122 uint64_t Address, const void *Decoder) { 2123 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2124 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2125 2126 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2127 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2128 return false; 2129 2130 return true; 2131 } 2132 2133 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2134 uint64_t Address, const void *Decoder) { 2135 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2136 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2137 2138 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2139 Inst.addOperand(MCOperand::CreateImm(imm)); 2140 2141 return true; 2142 } 2143 2144 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2145 uint64_t Address, const void *Decoder) { 2146 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2147 2148 return true; 2149 } 2150 2151 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2152 uint64_t Address, const void *Decoder) { 2153 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2154 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2155 2156 return true; 2157 } 2158 2159 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2160 uint64_t Address, const void *Decoder) { 2161 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2162 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2163 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2164 2165 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2166 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2167 return false; 2168 Inst.addOperand(MCOperand::CreateImm(imm)); 2169 2170 return true; 2171 } 2172 2173 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2174 uint64_t Address, const void *Decoder) { 2175 if (Inst.getOpcode() != ARM::t2PLDs) { 2176 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2177 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2178 } 2179 2180 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2181 if (Rn == 0xF) { 2182 switch (Inst.getOpcode()) { 2183 case ARM::t2LDRBs: 2184 Inst.setOpcode(ARM::t2LDRBpci); 2185 break; 2186 case ARM::t2LDRHs: 2187 Inst.setOpcode(ARM::t2LDRHpci); 2188 break; 2189 case ARM::t2LDRSHs: 2190 Inst.setOpcode(ARM::t2LDRSHpci); 2191 break; 2192 case ARM::t2LDRSBs: 2193 Inst.setOpcode(ARM::t2LDRSBpci); 2194 break; 2195 case ARM::t2PLDs: 2196 Inst.setOpcode(ARM::t2PLDi12); 2197 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2198 break; 2199 default: 2200 return false; 2201 } 2202 2203 int imm = fieldFromInstruction32(Insn, 0, 12); 2204 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2205 Inst.addOperand(MCOperand::CreateImm(imm)); 2206 2207 return true; 2208 } 2209 2210 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2211 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2212 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2213 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2214 2215 return true; 2216 } 2217 2218 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2219 uint64_t Address, const void *Decoder) { 2220 int imm = Val & 0xFF; 2221 if (!(Val & 0x100)) imm *= -1; 2222 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2223 2224 return true; 2225 } 2226 2227 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2228 uint64_t Address, const void *Decoder) { 2229 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2230 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2231 2232 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2233 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2234 return false; 2235 2236 return true; 2237 } 2238 2239 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2240 uint64_t Address, const void *Decoder) { 2241 int imm = Val & 0xFF; 2242 if (!(Val & 0x100)) imm *= -1; 2243 Inst.addOperand(MCOperand::CreateImm(imm)); 2244 2245 return true; 2246 } 2247 2248 2249 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2250 uint64_t Address, const void *Decoder) { 2251 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2252 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2253 2254 // Some instructions always use an additive offset. 2255 switch (Inst.getOpcode()) { 2256 case ARM::t2LDRT: 2257 case ARM::t2LDRBT: 2258 case ARM::t2LDRHT: 2259 case ARM::t2LDRSBT: 2260 case ARM::t2LDRSHT: 2261 imm |= 0x100; 2262 break; 2263 default: 2264 break; 2265 } 2266 2267 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2268 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2269 return false; 2270 2271 return true; 2272 } 2273 2274 2275 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2276 uint64_t Address, const void *Decoder) { 2277 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2278 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2279 2280 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2281 Inst.addOperand(MCOperand::CreateImm(imm)); 2282 2283 return true; 2284 } 2285 2286 2287 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2288 uint64_t Address, const void *Decoder) { 2289 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2290 2291 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2292 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2293 Inst.addOperand(MCOperand::CreateImm(imm)); 2294 2295 return true; 2296 } 2297 2298 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2299 uint64_t Address, const void *Decoder) { 2300 if (Inst.getOpcode() == ARM::tADDrSP) { 2301 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2302 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2303 2304 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2305 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2306 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2307 } else if (Inst.getOpcode() == ARM::tADDspr) { 2308 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2309 2310 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2311 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2312 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2313 } 2314 2315 return true; 2316 } 2317 2318 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2319 uint64_t Address, const void *Decoder) { 2320 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2321 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2322 2323 Inst.addOperand(MCOperand::CreateImm(imod)); 2324 Inst.addOperand(MCOperand::CreateImm(flags)); 2325 2326 return true; 2327 } 2328 2329 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2330 uint64_t Address, const void *Decoder) { 2331 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2332 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2333 2334 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2335 Inst.addOperand(MCOperand::CreateImm(add)); 2336 2337 return true; 2338 } 2339 2340 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2341 uint64_t Address, const void *Decoder) { 2342 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2343 return true; 2344 } 2345 2346 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2347 uint64_t Address, const void *Decoder) { 2348 if (Val == 0xA || Val == 0xB) 2349 return false; 2350 2351 Inst.addOperand(MCOperand::CreateImm(Val)); 2352 return true; 2353 } 2354 2355 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2356 uint64_t Address, const void *Decoder) { 2357 if (Val == 0) 2358 Inst.addOperand(MCOperand::CreateImm(32)); 2359 else 2360 Inst.addOperand(MCOperand::CreateImm(Val)); 2361 return true; 2362 } 2363 2364 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2365 uint64_t Address, const void *Decoder) { 2366 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2367 if (pred == 0xE || pred == 0xF) { 2368 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2369 switch (opc) { 2370 default: 2371 return false; 2372 case 0: 2373 Inst.setOpcode(ARM::t2DSB); 2374 break; 2375 case 1: 2376 Inst.setOpcode(ARM::t2DMB); 2377 break; 2378 case 2: 2379 Inst.setOpcode(ARM::t2ISB); 2380 return true; 2381 } 2382 2383 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2384 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2385 } 2386 2387 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2388 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2389 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2390 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2391 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2392 2393 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2394 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2395 return false; 2396 2397 return true; 2398 } 2399 2400 // Decode a shifted immediate operand. These basically consist 2401 // of an 8-bit value, and a 4-bit directive that specifies either 2402 // a splat operation or a rotation. 2403 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2404 uint64_t Address, const void *Decoder) { 2405 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2406 if (ctrl == 0) { 2407 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2408 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2409 switch (byte) { 2410 case 0: 2411 Inst.addOperand(MCOperand::CreateImm(imm)); 2412 break; 2413 case 1: 2414 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2415 break; 2416 case 2: 2417 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2418 break; 2419 case 3: 2420 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2421 (imm << 8) | imm)); 2422 break; 2423 } 2424 } else { 2425 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2426 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2427 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2428 Inst.addOperand(MCOperand::CreateImm(imm)); 2429 } 2430 2431 return true; 2432 } 2433 2434 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2435 uint64_t Address, const void *Decoder){ 2436 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2437 return true; 2438 } 2439 2440 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2441 uint64_t Address, const void *Decoder){ 2442 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2443 return true; 2444 } 2445 2446 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, 2447 uint64_t Address, const void *Decoder) { 2448 bool isImm = fieldFromInstruction32(Val, 9, 1); 2449 bool isAdd = fieldFromInstruction32(Val, 8, 1); 2450 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2451 2452 if (!isImm) { 2453 if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false; 2454 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); 2455 } else { 2456 Inst.addOperand(MCOperand::CreateReg(0)); 2457 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); 2458 } 2459 2460 return true; 2461 } 2462 2463 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2464 uint64_t Address, const void *Decoder) { 2465 switch (Val) { 2466 default: 2467 return false; 2468 case 0xF: // SY 2469 case 0xE: // ST 2470 case 0xB: // ISH 2471 case 0xA: // ISHST 2472 case 0x7: // NSH 2473 case 0x6: // NSHST 2474 case 0x3: // OSH 2475 case 0x2: // OSHST 2476 break; 2477 } 2478 2479 Inst.addOperand(MCOperand::CreateImm(Val)); 2480 return true; 2481 } 2482 2483 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2484 uint64_t Address, const void *Decoder) { 2485 if (!Val) return false; 2486 Inst.addOperand(MCOperand::CreateImm(Val)); 2487 return true; 2488 } 2489 2490 static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2491 uint64_t Address, const void *Decoder) { 2492 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2493 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2494 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2495 2496 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2497 2498 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2499 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2500 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2501 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2502 2503 return true; 2504 } 2505 2506 2507 static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2508 uint64_t Address, const void *Decoder) { 2509 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2510 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2511 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2512 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2513 2514 if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2515 2516 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2517 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; 2518 2519 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2520 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2521 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2522 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2523 2524 return true; 2525 } 2526 2527 2528