1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/ARMAddressingModes.h" 10 #include "MCTargetDesc/ARMBaseInfo.h" 11 #include "MCTargetDesc/ARMMCTargetDesc.h" 12 #include "Utils/ARMBaseInfo.h" 13 #include "llvm/MC/MCContext.h" 14 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 15 #include "llvm/MC/MCFixedLenDisassembler.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCSubtargetInfo.h" 19 #include "llvm/MC/SubtargetFeature.h" 20 #include "llvm/Support/Compiler.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <algorithm> 26 #include <cassert> 27 #include <cstdint> 28 #include <vector> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "arm-disassembler" 33 34 using DecodeStatus = MCDisassembler::DecodeStatus; 35 36 namespace { 37 38 // Handles the condition code status of instructions in IT blocks 39 class ITStatus 40 { 41 public: 42 // Returns the condition code for instruction in IT block 43 unsigned getITCC() { 44 unsigned CC = ARMCC::AL; 45 if (instrInITBlock()) 46 CC = ITStates.back(); 47 return CC; 48 } 49 50 // Advances the IT block state to the next T or E 51 void advanceITState() { 52 ITStates.pop_back(); 53 } 54 55 // Returns true if the current instruction is in an IT block 56 bool instrInITBlock() { 57 return !ITStates.empty(); 58 } 59 60 // Returns true if current instruction is the last instruction in an IT block 61 bool instrLastInITBlock() { 62 return ITStates.size() == 1; 63 } 64 65 // Called when decoding an IT instruction. Sets the IT state for the following 66 // instructions that for the IT block. Firstcond and Mask correspond to the 67 // fields in the IT instruction encoding. 68 void setITState(char Firstcond, char Mask) { 69 // (3 - the number of trailing zeros) is the number of then / else. 70 unsigned CondBit0 = Firstcond & 1; 71 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 72 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 73 assert(NumTZ <= 3 && "Invalid IT mask!"); 74 // push condition codes onto the stack the correct order for the pops 75 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 76 bool T = ((Mask >> Pos) & 1) == CondBit0; 77 if (T) 78 ITStates.push_back(CCBits); 79 else 80 ITStates.push_back(CCBits ^ 1); 81 } 82 ITStates.push_back(CCBits); 83 } 84 85 private: 86 std::vector<unsigned char> ITStates; 87 }; 88 89 /// ARM disassembler for all ARM platforms. 90 class ARMDisassembler : public MCDisassembler { 91 public: 92 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 93 MCDisassembler(STI, Ctx) { 94 } 95 96 ~ARMDisassembler() override = default; 97 98 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 99 ArrayRef<uint8_t> Bytes, uint64_t Address, 100 raw_ostream &VStream, 101 raw_ostream &CStream) const override; 102 }; 103 104 /// Thumb disassembler for all Thumb platforms. 105 class ThumbDisassembler : public MCDisassembler { 106 public: 107 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 108 MCDisassembler(STI, Ctx) { 109 } 110 111 ~ThumbDisassembler() override = default; 112 113 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 114 ArrayRef<uint8_t> Bytes, uint64_t Address, 115 raw_ostream &VStream, 116 raw_ostream &CStream) const override; 117 118 private: 119 mutable ITStatus ITBlock; 120 121 DecodeStatus AddThumbPredicate(MCInst&) const; 122 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 123 }; 124 125 } // end anonymous namespace 126 127 static bool Check(DecodeStatus &Out, DecodeStatus In) { 128 switch (In) { 129 case MCDisassembler::Success: 130 // Out stays the same. 131 return true; 132 case MCDisassembler::SoftFail: 133 Out = In; 134 return true; 135 case MCDisassembler::Fail: 136 Out = In; 137 return false; 138 } 139 llvm_unreachable("Invalid DecodeStatus!"); 140 } 141 142 // Forward declare these because the autogenerated code will reference them. 143 // Definitions are further down. 144 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 147 unsigned RegNo, uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 150 unsigned RegNo, uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 179 unsigned RegNo, uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 193 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 198 unsigned Insn, 199 uint64_t Address, 200 const void *Decoder); 201 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 210 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 211 unsigned Insn, 212 uint64_t Adddress, 213 const void *Decoder); 214 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 329 unsigned Val, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void* Decoder); 355 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void* Decoder); 357 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void* Decoder); 359 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void* Decoder); 361 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 406 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 413 #include "ARMGenDisassemblerTables.inc" 414 415 static MCDisassembler *createARMDisassembler(const Target &T, 416 const MCSubtargetInfo &STI, 417 MCContext &Ctx) { 418 return new ARMDisassembler(STI, Ctx); 419 } 420 421 static MCDisassembler *createThumbDisassembler(const Target &T, 422 const MCSubtargetInfo &STI, 423 MCContext &Ctx) { 424 return new ThumbDisassembler(STI, Ctx); 425 } 426 427 // Post-decoding checks 428 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 429 uint64_t Address, raw_ostream &OS, 430 raw_ostream &CS, 431 uint32_t Insn, 432 DecodeStatus Result) { 433 switch (MI.getOpcode()) { 434 case ARM::HVC: { 435 // HVC is undefined if condition = 0xf otherwise upredictable 436 // if condition != 0xe 437 uint32_t Cond = (Insn >> 28) & 0xF; 438 if (Cond == 0xF) 439 return MCDisassembler::Fail; 440 if (Cond != 0xE) 441 return MCDisassembler::SoftFail; 442 return Result; 443 } 444 default: return Result; 445 } 446 } 447 448 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 449 ArrayRef<uint8_t> Bytes, 450 uint64_t Address, raw_ostream &OS, 451 raw_ostream &CS) const { 452 CommentStream = &CS; 453 454 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 455 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 456 "mode!"); 457 458 // We want to read exactly 4 bytes of data. 459 if (Bytes.size() < 4) { 460 Size = 0; 461 return MCDisassembler::Fail; 462 } 463 464 // Encoded as a small-endian 32-bit word in the stream. 465 uint32_t Insn = 466 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 467 468 // Calling the auto-generated decoder function. 469 DecodeStatus Result = 470 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 471 if (Result != MCDisassembler::Fail) { 472 Size = 4; 473 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 474 } 475 476 struct DecodeTable { 477 const uint8_t *P; 478 bool DecodePred; 479 }; 480 481 const DecodeTable Tables[] = { 482 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 483 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 484 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 485 {DecoderTablev8Crypto32, false}, 486 }; 487 488 for (auto Table : Tables) { 489 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 490 if (Result != MCDisassembler::Fail) { 491 Size = 4; 492 // Add a fake predicate operand, because we share these instruction 493 // definitions with Thumb2 where these instructions are predicable. 494 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 495 return MCDisassembler::Fail; 496 return Result; 497 } 498 } 499 500 Result = 501 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 502 if (Result != MCDisassembler::Fail) { 503 Size = 4; 504 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 505 } 506 507 Size = 4; 508 return MCDisassembler::Fail; 509 } 510 511 namespace llvm { 512 513 extern const MCInstrDesc ARMInsts[]; 514 515 } // end namespace llvm 516 517 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 518 /// immediate Value in the MCInst. The immediate Value has had any PC 519 /// adjustment made by the caller. If the instruction is a branch instruction 520 /// then isBranch is true, else false. If the getOpInfo() function was set as 521 /// part of the setupForSymbolicDisassembly() call then that function is called 522 /// to get any symbolic information at the Address for this instruction. If 523 /// that returns non-zero then the symbolic information it returns is used to 524 /// create an MCExpr and that is added as an operand to the MCInst. If 525 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 526 /// Value is done and if a symbol is found an MCExpr is created with that, else 527 /// an MCExpr with Value is created. This function returns true if it adds an 528 /// operand to the MCInst and false otherwise. 529 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 530 bool isBranch, uint64_t InstSize, 531 MCInst &MI, const void *Decoder) { 532 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 533 // FIXME: Does it make sense for value to be negative? 534 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 535 /* Offset */ 0, InstSize); 536 } 537 538 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 539 /// referenced by a load instruction with the base register that is the Pc. 540 /// These can often be values in a literal pool near the Address of the 541 /// instruction. The Address of the instruction and its immediate Value are 542 /// used as a possible literal pool entry. The SymbolLookUp call back will 543 /// return the name of a symbol referenced by the literal pool's entry if 544 /// the referenced address is that of a symbol. Or it will return a pointer to 545 /// a literal 'C' string if the referenced address of the literal pool's entry 546 /// is an address into a section with 'C' string literals. 547 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 548 const void *Decoder) { 549 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 550 Dis->tryAddingPcLoadReferenceComment(Value, Address); 551 } 552 553 // Thumb1 instructions don't have explicit S bits. Rather, they 554 // implicitly set CPSR. Since it's not represented in the encoding, the 555 // auto-generated decoder won't inject the CPSR operand. We need to fix 556 // that as a post-pass. 557 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 558 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 559 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 560 MCInst::iterator I = MI.begin(); 561 for (unsigned i = 0; i < NumOps; ++i, ++I) { 562 if (I == MI.end()) break; 563 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 564 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 565 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 566 return; 567 } 568 } 569 570 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 571 } 572 573 // Most Thumb instructions don't have explicit predicates in the 574 // encoding, but rather get their predicates from IT context. We need 575 // to fix up the predicate operands using this context information as a 576 // post-pass. 577 MCDisassembler::DecodeStatus 578 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 579 MCDisassembler::DecodeStatus S = Success; 580 581 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 582 583 // A few instructions actually have predicates encoded in them. Don't 584 // try to overwrite it if we're seeing one of those. 585 switch (MI.getOpcode()) { 586 case ARM::tBcc: 587 case ARM::t2Bcc: 588 case ARM::tCBZ: 589 case ARM::tCBNZ: 590 case ARM::tCPS: 591 case ARM::t2CPS3p: 592 case ARM::t2CPS2p: 593 case ARM::t2CPS1p: 594 case ARM::tMOVSr: 595 case ARM::tSETEND: 596 // Some instructions (mostly conditional branches) are not 597 // allowed in IT blocks. 598 if (ITBlock.instrInITBlock()) 599 S = SoftFail; 600 else 601 return Success; 602 break; 603 case ARM::t2HINT: 604 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 605 S = SoftFail; 606 break; 607 case ARM::tB: 608 case ARM::t2B: 609 case ARM::t2TBB: 610 case ARM::t2TBH: 611 // Some instructions (mostly unconditional branches) can 612 // only appears at the end of, or outside of, an IT. 613 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 614 S = SoftFail; 615 break; 616 default: 617 break; 618 } 619 620 // If we're in an IT block, base the predicate on that. Otherwise, 621 // assume a predicate of AL. 622 unsigned CC; 623 CC = ITBlock.getITCC(); 624 if (CC == 0xF) 625 CC = ARMCC::AL; 626 if (ITBlock.instrInITBlock()) 627 ITBlock.advanceITState(); 628 629 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 630 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 631 MCInst::iterator I = MI.begin(); 632 for (unsigned i = 0; i < NumOps; ++i, ++I) { 633 if (I == MI.end()) break; 634 if (OpInfo[i].isPredicate()) { 635 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 636 Check(S, SoftFail); 637 I = MI.insert(I, MCOperand::createImm(CC)); 638 ++I; 639 if (CC == ARMCC::AL) 640 MI.insert(I, MCOperand::createReg(0)); 641 else 642 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 643 return S; 644 } 645 } 646 647 I = MI.insert(I, MCOperand::createImm(CC)); 648 ++I; 649 if (CC == ARMCC::AL) 650 MI.insert(I, MCOperand::createReg(0)); 651 else 652 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 653 654 return S; 655 } 656 657 // Thumb VFP instructions are a special case. Because we share their 658 // encodings between ARM and Thumb modes, and they are predicable in ARM 659 // mode, the auto-generated decoder will give them an (incorrect) 660 // predicate operand. We need to rewrite these operands based on the IT 661 // context as a post-pass. 662 void ThumbDisassembler::UpdateThumbVFPPredicate( 663 DecodeStatus &S, MCInst &MI) const { 664 unsigned CC; 665 CC = ITBlock.getITCC(); 666 if (CC == 0xF) 667 CC = ARMCC::AL; 668 if (ITBlock.instrInITBlock()) 669 ITBlock.advanceITState(); 670 671 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 672 MCInst::iterator I = MI.begin(); 673 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 674 for (unsigned i = 0; i < NumOps; ++i, ++I) { 675 if (OpInfo[i].isPredicate() ) { 676 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 677 Check(S, SoftFail); 678 I->setImm(CC); 679 ++I; 680 if (CC == ARMCC::AL) 681 I->setReg(0); 682 else 683 I->setReg(ARM::CPSR); 684 return; 685 } 686 } 687 } 688 689 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 690 ArrayRef<uint8_t> Bytes, 691 uint64_t Address, 692 raw_ostream &OS, 693 raw_ostream &CS) const { 694 CommentStream = &CS; 695 696 assert(STI.getFeatureBits()[ARM::ModeThumb] && 697 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 698 699 // We want to read exactly 2 bytes of data. 700 if (Bytes.size() < 2) { 701 Size = 0; 702 return MCDisassembler::Fail; 703 } 704 705 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 706 DecodeStatus Result = 707 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 708 if (Result != MCDisassembler::Fail) { 709 Size = 2; 710 Check(Result, AddThumbPredicate(MI)); 711 return Result; 712 } 713 714 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 715 STI); 716 if (Result) { 717 Size = 2; 718 bool InITBlock = ITBlock.instrInITBlock(); 719 Check(Result, AddThumbPredicate(MI)); 720 AddThumb1SBit(MI, InITBlock); 721 return Result; 722 } 723 724 Result = 725 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 726 if (Result != MCDisassembler::Fail) { 727 Size = 2; 728 729 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 730 // the Thumb predicate. 731 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 732 Result = MCDisassembler::SoftFail; 733 734 Check(Result, AddThumbPredicate(MI)); 735 736 // If we find an IT instruction, we need to parse its condition 737 // code and mask operands so that we can apply them correctly 738 // to the subsequent instructions. 739 if (MI.getOpcode() == ARM::t2IT) { 740 unsigned Firstcond = MI.getOperand(0).getImm(); 741 unsigned Mask = MI.getOperand(1).getImm(); 742 ITBlock.setITState(Firstcond, Mask); 743 744 // An IT instruction that would give a 'NV' predicate is unpredictable. 745 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 746 CS << "unpredictable IT predicate sequence"; 747 } 748 749 return Result; 750 } 751 752 // We want to read exactly 4 bytes of data. 753 if (Bytes.size() < 4) { 754 Size = 0; 755 return MCDisassembler::Fail; 756 } 757 758 uint32_t Insn32 = 759 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 760 Result = 761 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 762 if (Result != MCDisassembler::Fail) { 763 Size = 4; 764 bool InITBlock = ITBlock.instrInITBlock(); 765 Check(Result, AddThumbPredicate(MI)); 766 AddThumb1SBit(MI, InITBlock); 767 return Result; 768 } 769 770 Result = 771 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 772 if (Result != MCDisassembler::Fail) { 773 Size = 4; 774 Check(Result, AddThumbPredicate(MI)); 775 return Result; 776 } 777 778 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 779 Result = 780 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 781 if (Result != MCDisassembler::Fail) { 782 Size = 4; 783 UpdateThumbVFPPredicate(Result, MI); 784 return Result; 785 } 786 } 787 788 Result = 789 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 790 if (Result != MCDisassembler::Fail) { 791 Size = 4; 792 return Result; 793 } 794 795 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 796 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 797 STI); 798 if (Result != MCDisassembler::Fail) { 799 Size = 4; 800 Check(Result, AddThumbPredicate(MI)); 801 return Result; 802 } 803 } 804 805 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 806 uint32_t NEONLdStInsn = Insn32; 807 NEONLdStInsn &= 0xF0FFFFFF; 808 NEONLdStInsn |= 0x04000000; 809 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 810 Address, this, STI); 811 if (Result != MCDisassembler::Fail) { 812 Size = 4; 813 Check(Result, AddThumbPredicate(MI)); 814 return Result; 815 } 816 } 817 818 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 819 uint32_t NEONDataInsn = Insn32; 820 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 821 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 822 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 823 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 824 Address, this, STI); 825 if (Result != MCDisassembler::Fail) { 826 Size = 4; 827 Check(Result, AddThumbPredicate(MI)); 828 return Result; 829 } 830 831 uint32_t NEONCryptoInsn = Insn32; 832 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 833 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 834 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 835 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 836 Address, this, STI); 837 if (Result != MCDisassembler::Fail) { 838 Size = 4; 839 return Result; 840 } 841 842 uint32_t NEONv8Insn = Insn32; 843 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 844 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 845 this, STI); 846 if (Result != MCDisassembler::Fail) { 847 Size = 4; 848 return Result; 849 } 850 } 851 852 Result = 853 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 854 if (Result != MCDisassembler::Fail) { 855 Size = 4; 856 Check(Result, AddThumbPredicate(MI)); 857 return Result; 858 } 859 860 Size = 0; 861 return MCDisassembler::Fail; 862 } 863 864 extern "C" void LLVMInitializeARMDisassembler() { 865 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 866 createARMDisassembler); 867 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 868 createARMDisassembler); 869 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 870 createThumbDisassembler); 871 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 872 createThumbDisassembler); 873 } 874 875 static const uint16_t GPRDecoderTable[] = { 876 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 877 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 878 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 879 ARM::R12, ARM::SP, ARM::LR, ARM::PC 880 }; 881 882 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 883 uint64_t Address, const void *Decoder) { 884 if (RegNo > 15) 885 return MCDisassembler::Fail; 886 887 unsigned Register = GPRDecoderTable[RegNo]; 888 Inst.addOperand(MCOperand::createReg(Register)); 889 return MCDisassembler::Success; 890 } 891 892 static DecodeStatus 893 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 894 uint64_t Address, const void *Decoder) { 895 DecodeStatus S = MCDisassembler::Success; 896 897 if (RegNo == 15) 898 S = MCDisassembler::SoftFail; 899 900 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 901 902 return S; 903 } 904 905 static DecodeStatus 906 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 907 uint64_t Address, const void *Decoder) { 908 DecodeStatus S = MCDisassembler::Success; 909 910 if (RegNo == 15) 911 { 912 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 913 return MCDisassembler::Success; 914 } 915 916 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 917 return S; 918 } 919 920 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 921 uint64_t Address, const void *Decoder) { 922 if (RegNo > 7) 923 return MCDisassembler::Fail; 924 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 925 } 926 927 static const uint16_t GPRPairDecoderTable[] = { 928 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 929 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 930 }; 931 932 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 933 uint64_t Address, const void *Decoder) { 934 DecodeStatus S = MCDisassembler::Success; 935 936 if (RegNo > 13) 937 return MCDisassembler::Fail; 938 939 if ((RegNo & 1) || RegNo == 0xe) 940 S = MCDisassembler::SoftFail; 941 942 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 943 Inst.addOperand(MCOperand::createReg(RegisterPair)); 944 return S; 945 } 946 947 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 948 uint64_t Address, const void *Decoder) { 949 unsigned Register = 0; 950 switch (RegNo) { 951 case 0: 952 Register = ARM::R0; 953 break; 954 case 1: 955 Register = ARM::R1; 956 break; 957 case 2: 958 Register = ARM::R2; 959 break; 960 case 3: 961 Register = ARM::R3; 962 break; 963 case 9: 964 Register = ARM::R9; 965 break; 966 case 12: 967 Register = ARM::R12; 968 break; 969 default: 970 return MCDisassembler::Fail; 971 } 972 973 Inst.addOperand(MCOperand::createReg(Register)); 974 return MCDisassembler::Success; 975 } 976 977 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 978 uint64_t Address, const void *Decoder) { 979 DecodeStatus S = MCDisassembler::Success; 980 981 const FeatureBitset &featureBits = 982 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 983 984 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 985 S = MCDisassembler::SoftFail; 986 987 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 988 return S; 989 } 990 991 static const uint16_t SPRDecoderTable[] = { 992 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 993 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 994 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 995 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 996 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 997 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 998 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 999 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1000 }; 1001 1002 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1003 uint64_t Address, const void *Decoder) { 1004 if (RegNo > 31) 1005 return MCDisassembler::Fail; 1006 1007 unsigned Register = SPRDecoderTable[RegNo]; 1008 Inst.addOperand(MCOperand::createReg(Register)); 1009 return MCDisassembler::Success; 1010 } 1011 1012 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1013 uint64_t Address, const void *Decoder) { 1014 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1015 } 1016 1017 static const uint16_t DPRDecoderTable[] = { 1018 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1019 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1020 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1021 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1022 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1023 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1024 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1025 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1026 }; 1027 1028 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1029 uint64_t Address, const void *Decoder) { 1030 const FeatureBitset &featureBits = 1031 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1032 1033 bool hasD16 = featureBits[ARM::FeatureD16]; 1034 1035 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1036 return MCDisassembler::Fail; 1037 1038 unsigned Register = DPRDecoderTable[RegNo]; 1039 Inst.addOperand(MCOperand::createReg(Register)); 1040 return MCDisassembler::Success; 1041 } 1042 1043 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1044 uint64_t Address, const void *Decoder) { 1045 if (RegNo > 7) 1046 return MCDisassembler::Fail; 1047 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1048 } 1049 1050 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1051 uint64_t Address, const void *Decoder) { 1052 if (RegNo > 15) 1053 return MCDisassembler::Fail; 1054 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1055 } 1056 1057 static DecodeStatus 1058 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1059 uint64_t Address, const void *Decoder) { 1060 if (RegNo > 15) 1061 return MCDisassembler::Fail; 1062 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1063 } 1064 1065 static const uint16_t QPRDecoderTable[] = { 1066 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1067 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1068 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1069 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1070 }; 1071 1072 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1073 uint64_t Address, const void *Decoder) { 1074 if (RegNo > 31 || (RegNo & 1) != 0) 1075 return MCDisassembler::Fail; 1076 RegNo >>= 1; 1077 1078 unsigned Register = QPRDecoderTable[RegNo]; 1079 Inst.addOperand(MCOperand::createReg(Register)); 1080 return MCDisassembler::Success; 1081 } 1082 1083 static const uint16_t DPairDecoderTable[] = { 1084 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1085 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1086 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1087 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1088 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1089 ARM::Q15 1090 }; 1091 1092 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1093 uint64_t Address, const void *Decoder) { 1094 if (RegNo > 30) 1095 return MCDisassembler::Fail; 1096 1097 unsigned Register = DPairDecoderTable[RegNo]; 1098 Inst.addOperand(MCOperand::createReg(Register)); 1099 return MCDisassembler::Success; 1100 } 1101 1102 static const uint16_t DPairSpacedDecoderTable[] = { 1103 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1104 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1105 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1106 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1107 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1108 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1109 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1110 ARM::D28_D30, ARM::D29_D31 1111 }; 1112 1113 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1114 unsigned RegNo, 1115 uint64_t Address, 1116 const void *Decoder) { 1117 if (RegNo > 29) 1118 return MCDisassembler::Fail; 1119 1120 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1121 Inst.addOperand(MCOperand::createReg(Register)); 1122 return MCDisassembler::Success; 1123 } 1124 1125 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1126 uint64_t Address, const void *Decoder) { 1127 DecodeStatus S = MCDisassembler::Success; 1128 if (Val == 0xF) return MCDisassembler::Fail; 1129 // AL predicate is not allowed on Thumb1 branches. 1130 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1131 return MCDisassembler::Fail; 1132 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1133 Check(S, MCDisassembler::SoftFail); 1134 Inst.addOperand(MCOperand::createImm(Val)); 1135 if (Val == ARMCC::AL) { 1136 Inst.addOperand(MCOperand::createReg(0)); 1137 } else 1138 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1139 return S; 1140 } 1141 1142 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1143 uint64_t Address, const void *Decoder) { 1144 if (Val) 1145 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1146 else 1147 Inst.addOperand(MCOperand::createReg(0)); 1148 return MCDisassembler::Success; 1149 } 1150 1151 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1152 uint64_t Address, const void *Decoder) { 1153 DecodeStatus S = MCDisassembler::Success; 1154 1155 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1156 unsigned type = fieldFromInstruction(Val, 5, 2); 1157 unsigned imm = fieldFromInstruction(Val, 7, 5); 1158 1159 // Register-immediate 1160 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1161 return MCDisassembler::Fail; 1162 1163 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1164 switch (type) { 1165 case 0: 1166 Shift = ARM_AM::lsl; 1167 break; 1168 case 1: 1169 Shift = ARM_AM::lsr; 1170 break; 1171 case 2: 1172 Shift = ARM_AM::asr; 1173 break; 1174 case 3: 1175 Shift = ARM_AM::ror; 1176 break; 1177 } 1178 1179 if (Shift == ARM_AM::ror && imm == 0) 1180 Shift = ARM_AM::rrx; 1181 1182 unsigned Op = Shift | (imm << 3); 1183 Inst.addOperand(MCOperand::createImm(Op)); 1184 1185 return S; 1186 } 1187 1188 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1189 uint64_t Address, const void *Decoder) { 1190 DecodeStatus S = MCDisassembler::Success; 1191 1192 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1193 unsigned type = fieldFromInstruction(Val, 5, 2); 1194 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1195 1196 // Register-register 1197 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1198 return MCDisassembler::Fail; 1199 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1200 return MCDisassembler::Fail; 1201 1202 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1203 switch (type) { 1204 case 0: 1205 Shift = ARM_AM::lsl; 1206 break; 1207 case 1: 1208 Shift = ARM_AM::lsr; 1209 break; 1210 case 2: 1211 Shift = ARM_AM::asr; 1212 break; 1213 case 3: 1214 Shift = ARM_AM::ror; 1215 break; 1216 } 1217 1218 Inst.addOperand(MCOperand::createImm(Shift)); 1219 1220 return S; 1221 } 1222 1223 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1224 uint64_t Address, const void *Decoder) { 1225 DecodeStatus S = MCDisassembler::Success; 1226 1227 bool NeedDisjointWriteback = false; 1228 unsigned WritebackReg = 0; 1229 switch (Inst.getOpcode()) { 1230 default: 1231 break; 1232 case ARM::LDMIA_UPD: 1233 case ARM::LDMDB_UPD: 1234 case ARM::LDMIB_UPD: 1235 case ARM::LDMDA_UPD: 1236 case ARM::t2LDMIA_UPD: 1237 case ARM::t2LDMDB_UPD: 1238 case ARM::t2STMIA_UPD: 1239 case ARM::t2STMDB_UPD: 1240 NeedDisjointWriteback = true; 1241 WritebackReg = Inst.getOperand(0).getReg(); 1242 break; 1243 } 1244 1245 // Empty register lists are not allowed. 1246 if (Val == 0) return MCDisassembler::Fail; 1247 for (unsigned i = 0; i < 16; ++i) { 1248 if (Val & (1 << i)) { 1249 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1250 return MCDisassembler::Fail; 1251 // Writeback not allowed if Rn is in the target list. 1252 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1253 Check(S, MCDisassembler::SoftFail); 1254 } 1255 } 1256 1257 return S; 1258 } 1259 1260 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1261 uint64_t Address, const void *Decoder) { 1262 DecodeStatus S = MCDisassembler::Success; 1263 1264 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1265 unsigned regs = fieldFromInstruction(Val, 0, 8); 1266 1267 // In case of unpredictable encoding, tweak the operands. 1268 if (regs == 0 || (Vd + regs) > 32) { 1269 regs = Vd + regs > 32 ? 32 - Vd : regs; 1270 regs = std::max( 1u, regs); 1271 S = MCDisassembler::SoftFail; 1272 } 1273 1274 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1275 return MCDisassembler::Fail; 1276 for (unsigned i = 0; i < (regs - 1); ++i) { 1277 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1278 return MCDisassembler::Fail; 1279 } 1280 1281 return S; 1282 } 1283 1284 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1285 uint64_t Address, const void *Decoder) { 1286 DecodeStatus S = MCDisassembler::Success; 1287 1288 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1289 unsigned regs = fieldFromInstruction(Val, 1, 7); 1290 1291 // In case of unpredictable encoding, tweak the operands. 1292 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1293 regs = Vd + regs > 32 ? 32 - Vd : regs; 1294 regs = std::max( 1u, regs); 1295 regs = std::min(16u, regs); 1296 S = MCDisassembler::SoftFail; 1297 } 1298 1299 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1300 return MCDisassembler::Fail; 1301 for (unsigned i = 0; i < (regs - 1); ++i) { 1302 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1303 return MCDisassembler::Fail; 1304 } 1305 1306 return S; 1307 } 1308 1309 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1310 uint64_t Address, const void *Decoder) { 1311 // This operand encodes a mask of contiguous zeros between a specified MSB 1312 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1313 // the mask of all bits LSB-and-lower, and then xor them to create 1314 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1315 // create the final mask. 1316 unsigned msb = fieldFromInstruction(Val, 5, 5); 1317 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1318 1319 DecodeStatus S = MCDisassembler::Success; 1320 if (lsb > msb) { 1321 Check(S, MCDisassembler::SoftFail); 1322 // The check above will cause the warning for the "potentially undefined 1323 // instruction encoding" but we can't build a bad MCOperand value here 1324 // with a lsb > msb or else printing the MCInst will cause a crash. 1325 lsb = msb; 1326 } 1327 1328 uint32_t msb_mask = 0xFFFFFFFF; 1329 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1330 uint32_t lsb_mask = (1U << lsb) - 1; 1331 1332 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1333 return S; 1334 } 1335 1336 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1337 uint64_t Address, const void *Decoder) { 1338 DecodeStatus S = MCDisassembler::Success; 1339 1340 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1341 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1342 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1343 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1344 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1345 unsigned U = fieldFromInstruction(Insn, 23, 1); 1346 1347 switch (Inst.getOpcode()) { 1348 case ARM::LDC_OFFSET: 1349 case ARM::LDC_PRE: 1350 case ARM::LDC_POST: 1351 case ARM::LDC_OPTION: 1352 case ARM::LDCL_OFFSET: 1353 case ARM::LDCL_PRE: 1354 case ARM::LDCL_POST: 1355 case ARM::LDCL_OPTION: 1356 case ARM::STC_OFFSET: 1357 case ARM::STC_PRE: 1358 case ARM::STC_POST: 1359 case ARM::STC_OPTION: 1360 case ARM::STCL_OFFSET: 1361 case ARM::STCL_PRE: 1362 case ARM::STCL_POST: 1363 case ARM::STCL_OPTION: 1364 case ARM::t2LDC_OFFSET: 1365 case ARM::t2LDC_PRE: 1366 case ARM::t2LDC_POST: 1367 case ARM::t2LDC_OPTION: 1368 case ARM::t2LDCL_OFFSET: 1369 case ARM::t2LDCL_PRE: 1370 case ARM::t2LDCL_POST: 1371 case ARM::t2LDCL_OPTION: 1372 case ARM::t2STC_OFFSET: 1373 case ARM::t2STC_PRE: 1374 case ARM::t2STC_POST: 1375 case ARM::t2STC_OPTION: 1376 case ARM::t2STCL_OFFSET: 1377 case ARM::t2STCL_PRE: 1378 case ARM::t2STCL_POST: 1379 case ARM::t2STCL_OPTION: 1380 if (coproc == 0xA || coproc == 0xB) 1381 return MCDisassembler::Fail; 1382 break; 1383 default: 1384 break; 1385 } 1386 1387 const FeatureBitset &featureBits = 1388 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1389 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1390 return MCDisassembler::Fail; 1391 1392 Inst.addOperand(MCOperand::createImm(coproc)); 1393 Inst.addOperand(MCOperand::createImm(CRd)); 1394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1395 return MCDisassembler::Fail; 1396 1397 switch (Inst.getOpcode()) { 1398 case ARM::t2LDC2_OFFSET: 1399 case ARM::t2LDC2L_OFFSET: 1400 case ARM::t2LDC2_PRE: 1401 case ARM::t2LDC2L_PRE: 1402 case ARM::t2STC2_OFFSET: 1403 case ARM::t2STC2L_OFFSET: 1404 case ARM::t2STC2_PRE: 1405 case ARM::t2STC2L_PRE: 1406 case ARM::LDC2_OFFSET: 1407 case ARM::LDC2L_OFFSET: 1408 case ARM::LDC2_PRE: 1409 case ARM::LDC2L_PRE: 1410 case ARM::STC2_OFFSET: 1411 case ARM::STC2L_OFFSET: 1412 case ARM::STC2_PRE: 1413 case ARM::STC2L_PRE: 1414 case ARM::t2LDC_OFFSET: 1415 case ARM::t2LDCL_OFFSET: 1416 case ARM::t2LDC_PRE: 1417 case ARM::t2LDCL_PRE: 1418 case ARM::t2STC_OFFSET: 1419 case ARM::t2STCL_OFFSET: 1420 case ARM::t2STC_PRE: 1421 case ARM::t2STCL_PRE: 1422 case ARM::LDC_OFFSET: 1423 case ARM::LDCL_OFFSET: 1424 case ARM::LDC_PRE: 1425 case ARM::LDCL_PRE: 1426 case ARM::STC_OFFSET: 1427 case ARM::STCL_OFFSET: 1428 case ARM::STC_PRE: 1429 case ARM::STCL_PRE: 1430 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1431 Inst.addOperand(MCOperand::createImm(imm)); 1432 break; 1433 case ARM::t2LDC2_POST: 1434 case ARM::t2LDC2L_POST: 1435 case ARM::t2STC2_POST: 1436 case ARM::t2STC2L_POST: 1437 case ARM::LDC2_POST: 1438 case ARM::LDC2L_POST: 1439 case ARM::STC2_POST: 1440 case ARM::STC2L_POST: 1441 case ARM::t2LDC_POST: 1442 case ARM::t2LDCL_POST: 1443 case ARM::t2STC_POST: 1444 case ARM::t2STCL_POST: 1445 case ARM::LDC_POST: 1446 case ARM::LDCL_POST: 1447 case ARM::STC_POST: 1448 case ARM::STCL_POST: 1449 imm |= U << 8; 1450 LLVM_FALLTHROUGH; 1451 default: 1452 // The 'option' variant doesn't encode 'U' in the immediate since 1453 // the immediate is unsigned [0,255]. 1454 Inst.addOperand(MCOperand::createImm(imm)); 1455 break; 1456 } 1457 1458 switch (Inst.getOpcode()) { 1459 case ARM::LDC_OFFSET: 1460 case ARM::LDC_PRE: 1461 case ARM::LDC_POST: 1462 case ARM::LDC_OPTION: 1463 case ARM::LDCL_OFFSET: 1464 case ARM::LDCL_PRE: 1465 case ARM::LDCL_POST: 1466 case ARM::LDCL_OPTION: 1467 case ARM::STC_OFFSET: 1468 case ARM::STC_PRE: 1469 case ARM::STC_POST: 1470 case ARM::STC_OPTION: 1471 case ARM::STCL_OFFSET: 1472 case ARM::STCL_PRE: 1473 case ARM::STCL_POST: 1474 case ARM::STCL_OPTION: 1475 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1476 return MCDisassembler::Fail; 1477 break; 1478 default: 1479 break; 1480 } 1481 1482 return S; 1483 } 1484 1485 static DecodeStatus 1486 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1487 uint64_t Address, const void *Decoder) { 1488 DecodeStatus S = MCDisassembler::Success; 1489 1490 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1491 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1492 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1493 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1494 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1495 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1496 unsigned P = fieldFromInstruction(Insn, 24, 1); 1497 unsigned W = fieldFromInstruction(Insn, 21, 1); 1498 1499 // On stores, the writeback operand precedes Rt. 1500 switch (Inst.getOpcode()) { 1501 case ARM::STR_POST_IMM: 1502 case ARM::STR_POST_REG: 1503 case ARM::STRB_POST_IMM: 1504 case ARM::STRB_POST_REG: 1505 case ARM::STRT_POST_REG: 1506 case ARM::STRT_POST_IMM: 1507 case ARM::STRBT_POST_REG: 1508 case ARM::STRBT_POST_IMM: 1509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1510 return MCDisassembler::Fail; 1511 break; 1512 default: 1513 break; 1514 } 1515 1516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1517 return MCDisassembler::Fail; 1518 1519 // On loads, the writeback operand comes after Rt. 1520 switch (Inst.getOpcode()) { 1521 case ARM::LDR_POST_IMM: 1522 case ARM::LDR_POST_REG: 1523 case ARM::LDRB_POST_IMM: 1524 case ARM::LDRB_POST_REG: 1525 case ARM::LDRBT_POST_REG: 1526 case ARM::LDRBT_POST_IMM: 1527 case ARM::LDRT_POST_REG: 1528 case ARM::LDRT_POST_IMM: 1529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1530 return MCDisassembler::Fail; 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1537 return MCDisassembler::Fail; 1538 1539 ARM_AM::AddrOpc Op = ARM_AM::add; 1540 if (!fieldFromInstruction(Insn, 23, 1)) 1541 Op = ARM_AM::sub; 1542 1543 bool writeback = (P == 0) || (W == 1); 1544 unsigned idx_mode = 0; 1545 if (P && writeback) 1546 idx_mode = ARMII::IndexModePre; 1547 else if (!P && writeback) 1548 idx_mode = ARMII::IndexModePost; 1549 1550 if (writeback && (Rn == 15 || Rn == Rt)) 1551 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1552 1553 if (reg) { 1554 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1555 return MCDisassembler::Fail; 1556 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1557 switch( fieldFromInstruction(Insn, 5, 2)) { 1558 case 0: 1559 Opc = ARM_AM::lsl; 1560 break; 1561 case 1: 1562 Opc = ARM_AM::lsr; 1563 break; 1564 case 2: 1565 Opc = ARM_AM::asr; 1566 break; 1567 case 3: 1568 Opc = ARM_AM::ror; 1569 break; 1570 default: 1571 return MCDisassembler::Fail; 1572 } 1573 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1574 if (Opc == ARM_AM::ror && amt == 0) 1575 Opc = ARM_AM::rrx; 1576 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1577 1578 Inst.addOperand(MCOperand::createImm(imm)); 1579 } else { 1580 Inst.addOperand(MCOperand::createReg(0)); 1581 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1582 Inst.addOperand(MCOperand::createImm(tmp)); 1583 } 1584 1585 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1586 return MCDisassembler::Fail; 1587 1588 return S; 1589 } 1590 1591 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1592 uint64_t Address, const void *Decoder) { 1593 DecodeStatus S = MCDisassembler::Success; 1594 1595 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1596 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1597 unsigned type = fieldFromInstruction(Val, 5, 2); 1598 unsigned imm = fieldFromInstruction(Val, 7, 5); 1599 unsigned U = fieldFromInstruction(Val, 12, 1); 1600 1601 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1602 switch (type) { 1603 case 0: 1604 ShOp = ARM_AM::lsl; 1605 break; 1606 case 1: 1607 ShOp = ARM_AM::lsr; 1608 break; 1609 case 2: 1610 ShOp = ARM_AM::asr; 1611 break; 1612 case 3: 1613 ShOp = ARM_AM::ror; 1614 break; 1615 } 1616 1617 if (ShOp == ARM_AM::ror && imm == 0) 1618 ShOp = ARM_AM::rrx; 1619 1620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1621 return MCDisassembler::Fail; 1622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1623 return MCDisassembler::Fail; 1624 unsigned shift; 1625 if (U) 1626 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1627 else 1628 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1629 Inst.addOperand(MCOperand::createImm(shift)); 1630 1631 return S; 1632 } 1633 1634 static DecodeStatus 1635 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1636 uint64_t Address, const void *Decoder) { 1637 DecodeStatus S = MCDisassembler::Success; 1638 1639 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1640 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1641 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1642 unsigned type = fieldFromInstruction(Insn, 22, 1); 1643 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1644 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1645 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1646 unsigned W = fieldFromInstruction(Insn, 21, 1); 1647 unsigned P = fieldFromInstruction(Insn, 24, 1); 1648 unsigned Rt2 = Rt + 1; 1649 1650 bool writeback = (W == 1) | (P == 0); 1651 1652 // For {LD,ST}RD, Rt must be even, else undefined. 1653 switch (Inst.getOpcode()) { 1654 case ARM::STRD: 1655 case ARM::STRD_PRE: 1656 case ARM::STRD_POST: 1657 case ARM::LDRD: 1658 case ARM::LDRD_PRE: 1659 case ARM::LDRD_POST: 1660 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1661 break; 1662 default: 1663 break; 1664 } 1665 switch (Inst.getOpcode()) { 1666 case ARM::STRD: 1667 case ARM::STRD_PRE: 1668 case ARM::STRD_POST: 1669 if (P == 0 && W == 1) 1670 S = MCDisassembler::SoftFail; 1671 1672 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1673 S = MCDisassembler::SoftFail; 1674 if (type && Rm == 15) 1675 S = MCDisassembler::SoftFail; 1676 if (Rt2 == 15) 1677 S = MCDisassembler::SoftFail; 1678 if (!type && fieldFromInstruction(Insn, 8, 4)) 1679 S = MCDisassembler::SoftFail; 1680 break; 1681 case ARM::STRH: 1682 case ARM::STRH_PRE: 1683 case ARM::STRH_POST: 1684 if (Rt == 15) 1685 S = MCDisassembler::SoftFail; 1686 if (writeback && (Rn == 15 || Rn == Rt)) 1687 S = MCDisassembler::SoftFail; 1688 if (!type && Rm == 15) 1689 S = MCDisassembler::SoftFail; 1690 break; 1691 case ARM::LDRD: 1692 case ARM::LDRD_PRE: 1693 case ARM::LDRD_POST: 1694 if (type && Rn == 15) { 1695 if (Rt2 == 15) 1696 S = MCDisassembler::SoftFail; 1697 break; 1698 } 1699 if (P == 0 && W == 1) 1700 S = MCDisassembler::SoftFail; 1701 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1702 S = MCDisassembler::SoftFail; 1703 if (!type && writeback && Rn == 15) 1704 S = MCDisassembler::SoftFail; 1705 if (writeback && (Rn == Rt || Rn == Rt2)) 1706 S = MCDisassembler::SoftFail; 1707 break; 1708 case ARM::LDRH: 1709 case ARM::LDRH_PRE: 1710 case ARM::LDRH_POST: 1711 if (type && Rn == 15) { 1712 if (Rt == 15) 1713 S = MCDisassembler::SoftFail; 1714 break; 1715 } 1716 if (Rt == 15) 1717 S = MCDisassembler::SoftFail; 1718 if (!type && Rm == 15) 1719 S = MCDisassembler::SoftFail; 1720 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1721 S = MCDisassembler::SoftFail; 1722 break; 1723 case ARM::LDRSH: 1724 case ARM::LDRSH_PRE: 1725 case ARM::LDRSH_POST: 1726 case ARM::LDRSB: 1727 case ARM::LDRSB_PRE: 1728 case ARM::LDRSB_POST: 1729 if (type && Rn == 15) { 1730 if (Rt == 15) 1731 S = MCDisassembler::SoftFail; 1732 break; 1733 } 1734 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1735 S = MCDisassembler::SoftFail; 1736 if (!type && (Rt == 15 || Rm == 15)) 1737 S = MCDisassembler::SoftFail; 1738 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1739 S = MCDisassembler::SoftFail; 1740 break; 1741 default: 1742 break; 1743 } 1744 1745 if (writeback) { // Writeback 1746 if (P) 1747 U |= ARMII::IndexModePre << 9; 1748 else 1749 U |= ARMII::IndexModePost << 9; 1750 1751 // On stores, the writeback operand precedes Rt. 1752 switch (Inst.getOpcode()) { 1753 case ARM::STRD: 1754 case ARM::STRD_PRE: 1755 case ARM::STRD_POST: 1756 case ARM::STRH: 1757 case ARM::STRH_PRE: 1758 case ARM::STRH_POST: 1759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1760 return MCDisassembler::Fail; 1761 break; 1762 default: 1763 break; 1764 } 1765 } 1766 1767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1768 return MCDisassembler::Fail; 1769 switch (Inst.getOpcode()) { 1770 case ARM::STRD: 1771 case ARM::STRD_PRE: 1772 case ARM::STRD_POST: 1773 case ARM::LDRD: 1774 case ARM::LDRD_PRE: 1775 case ARM::LDRD_POST: 1776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1777 return MCDisassembler::Fail; 1778 break; 1779 default: 1780 break; 1781 } 1782 1783 if (writeback) { 1784 // On loads, the writeback operand comes after Rt. 1785 switch (Inst.getOpcode()) { 1786 case ARM::LDRD: 1787 case ARM::LDRD_PRE: 1788 case ARM::LDRD_POST: 1789 case ARM::LDRH: 1790 case ARM::LDRH_PRE: 1791 case ARM::LDRH_POST: 1792 case ARM::LDRSH: 1793 case ARM::LDRSH_PRE: 1794 case ARM::LDRSH_POST: 1795 case ARM::LDRSB: 1796 case ARM::LDRSB_PRE: 1797 case ARM::LDRSB_POST: 1798 case ARM::LDRHTr: 1799 case ARM::LDRSBTr: 1800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1801 return MCDisassembler::Fail; 1802 break; 1803 default: 1804 break; 1805 } 1806 } 1807 1808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1809 return MCDisassembler::Fail; 1810 1811 if (type) { 1812 Inst.addOperand(MCOperand::createReg(0)); 1813 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1814 } else { 1815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1816 return MCDisassembler::Fail; 1817 Inst.addOperand(MCOperand::createImm(U)); 1818 } 1819 1820 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1821 return MCDisassembler::Fail; 1822 1823 return S; 1824 } 1825 1826 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1827 uint64_t Address, const void *Decoder) { 1828 DecodeStatus S = MCDisassembler::Success; 1829 1830 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1831 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1832 1833 switch (mode) { 1834 case 0: 1835 mode = ARM_AM::da; 1836 break; 1837 case 1: 1838 mode = ARM_AM::ia; 1839 break; 1840 case 2: 1841 mode = ARM_AM::db; 1842 break; 1843 case 3: 1844 mode = ARM_AM::ib; 1845 break; 1846 } 1847 1848 Inst.addOperand(MCOperand::createImm(mode)); 1849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1850 return MCDisassembler::Fail; 1851 1852 return S; 1853 } 1854 1855 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1856 uint64_t Address, const void *Decoder) { 1857 DecodeStatus S = MCDisassembler::Success; 1858 1859 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1860 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1861 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1862 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1863 1864 if (pred == 0xF) 1865 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1866 1867 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1868 return MCDisassembler::Fail; 1869 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1870 return MCDisassembler::Fail; 1871 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1872 return MCDisassembler::Fail; 1873 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1874 return MCDisassembler::Fail; 1875 return S; 1876 } 1877 1878 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1879 unsigned Insn, 1880 uint64_t Address, const void *Decoder) { 1881 DecodeStatus S = MCDisassembler::Success; 1882 1883 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1884 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1885 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1886 1887 if (pred == 0xF) { 1888 // Ambiguous with RFE and SRS 1889 switch (Inst.getOpcode()) { 1890 case ARM::LDMDA: 1891 Inst.setOpcode(ARM::RFEDA); 1892 break; 1893 case ARM::LDMDA_UPD: 1894 Inst.setOpcode(ARM::RFEDA_UPD); 1895 break; 1896 case ARM::LDMDB: 1897 Inst.setOpcode(ARM::RFEDB); 1898 break; 1899 case ARM::LDMDB_UPD: 1900 Inst.setOpcode(ARM::RFEDB_UPD); 1901 break; 1902 case ARM::LDMIA: 1903 Inst.setOpcode(ARM::RFEIA); 1904 break; 1905 case ARM::LDMIA_UPD: 1906 Inst.setOpcode(ARM::RFEIA_UPD); 1907 break; 1908 case ARM::LDMIB: 1909 Inst.setOpcode(ARM::RFEIB); 1910 break; 1911 case ARM::LDMIB_UPD: 1912 Inst.setOpcode(ARM::RFEIB_UPD); 1913 break; 1914 case ARM::STMDA: 1915 Inst.setOpcode(ARM::SRSDA); 1916 break; 1917 case ARM::STMDA_UPD: 1918 Inst.setOpcode(ARM::SRSDA_UPD); 1919 break; 1920 case ARM::STMDB: 1921 Inst.setOpcode(ARM::SRSDB); 1922 break; 1923 case ARM::STMDB_UPD: 1924 Inst.setOpcode(ARM::SRSDB_UPD); 1925 break; 1926 case ARM::STMIA: 1927 Inst.setOpcode(ARM::SRSIA); 1928 break; 1929 case ARM::STMIA_UPD: 1930 Inst.setOpcode(ARM::SRSIA_UPD); 1931 break; 1932 case ARM::STMIB: 1933 Inst.setOpcode(ARM::SRSIB); 1934 break; 1935 case ARM::STMIB_UPD: 1936 Inst.setOpcode(ARM::SRSIB_UPD); 1937 break; 1938 default: 1939 return MCDisassembler::Fail; 1940 } 1941 1942 // For stores (which become SRS's, the only operand is the mode. 1943 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1944 // Check SRS encoding constraints 1945 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1946 fieldFromInstruction(Insn, 20, 1) == 0)) 1947 return MCDisassembler::Fail; 1948 1949 Inst.addOperand( 1950 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 1951 return S; 1952 } 1953 1954 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1955 } 1956 1957 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1958 return MCDisassembler::Fail; 1959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1960 return MCDisassembler::Fail; // Tied 1961 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1962 return MCDisassembler::Fail; 1963 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1964 return MCDisassembler::Fail; 1965 1966 return S; 1967 } 1968 1969 // Check for UNPREDICTABLE predicated ESB instruction 1970 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 1971 uint64_t Address, const void *Decoder) { 1972 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1973 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 1974 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 1975 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 1976 1977 DecodeStatus S = MCDisassembler::Success; 1978 1979 Inst.addOperand(MCOperand::createImm(imm8)); 1980 1981 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1982 return MCDisassembler::Fail; 1983 1984 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 1985 // so all predicates should be allowed. 1986 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 1987 S = MCDisassembler::SoftFail; 1988 1989 return S; 1990 } 1991 1992 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1993 uint64_t Address, const void *Decoder) { 1994 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1995 unsigned M = fieldFromInstruction(Insn, 17, 1); 1996 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1997 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1998 1999 DecodeStatus S = MCDisassembler::Success; 2000 2001 // This decoder is called from multiple location that do not check 2002 // the full encoding is valid before they do. 2003 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2004 fieldFromInstruction(Insn, 16, 1) != 0 || 2005 fieldFromInstruction(Insn, 20, 8) != 0x10) 2006 return MCDisassembler::Fail; 2007 2008 // imod == '01' --> UNPREDICTABLE 2009 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2010 // return failure here. The '01' imod value is unprintable, so there's 2011 // nothing useful we could do even if we returned UNPREDICTABLE. 2012 2013 if (imod == 1) return MCDisassembler::Fail; 2014 2015 if (imod && M) { 2016 Inst.setOpcode(ARM::CPS3p); 2017 Inst.addOperand(MCOperand::createImm(imod)); 2018 Inst.addOperand(MCOperand::createImm(iflags)); 2019 Inst.addOperand(MCOperand::createImm(mode)); 2020 } else if (imod && !M) { 2021 Inst.setOpcode(ARM::CPS2p); 2022 Inst.addOperand(MCOperand::createImm(imod)); 2023 Inst.addOperand(MCOperand::createImm(iflags)); 2024 if (mode) S = MCDisassembler::SoftFail; 2025 } else if (!imod && M) { 2026 Inst.setOpcode(ARM::CPS1p); 2027 Inst.addOperand(MCOperand::createImm(mode)); 2028 if (iflags) S = MCDisassembler::SoftFail; 2029 } else { 2030 // imod == '00' && M == '0' --> UNPREDICTABLE 2031 Inst.setOpcode(ARM::CPS1p); 2032 Inst.addOperand(MCOperand::createImm(mode)); 2033 S = MCDisassembler::SoftFail; 2034 } 2035 2036 return S; 2037 } 2038 2039 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2040 uint64_t Address, const void *Decoder) { 2041 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2042 unsigned M = fieldFromInstruction(Insn, 8, 1); 2043 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2044 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2045 2046 DecodeStatus S = MCDisassembler::Success; 2047 2048 // imod == '01' --> UNPREDICTABLE 2049 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2050 // return failure here. The '01' imod value is unprintable, so there's 2051 // nothing useful we could do even if we returned UNPREDICTABLE. 2052 2053 if (imod == 1) return MCDisassembler::Fail; 2054 2055 if (imod && M) { 2056 Inst.setOpcode(ARM::t2CPS3p); 2057 Inst.addOperand(MCOperand::createImm(imod)); 2058 Inst.addOperand(MCOperand::createImm(iflags)); 2059 Inst.addOperand(MCOperand::createImm(mode)); 2060 } else if (imod && !M) { 2061 Inst.setOpcode(ARM::t2CPS2p); 2062 Inst.addOperand(MCOperand::createImm(imod)); 2063 Inst.addOperand(MCOperand::createImm(iflags)); 2064 if (mode) S = MCDisassembler::SoftFail; 2065 } else if (!imod && M) { 2066 Inst.setOpcode(ARM::t2CPS1p); 2067 Inst.addOperand(MCOperand::createImm(mode)); 2068 if (iflags) S = MCDisassembler::SoftFail; 2069 } else { 2070 // imod == '00' && M == '0' --> this is a HINT instruction 2071 int imm = fieldFromInstruction(Insn, 0, 8); 2072 // HINT are defined only for immediate in [0..4] 2073 if(imm > 4) return MCDisassembler::Fail; 2074 Inst.setOpcode(ARM::t2HINT); 2075 Inst.addOperand(MCOperand::createImm(imm)); 2076 } 2077 2078 return S; 2079 } 2080 2081 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2082 uint64_t Address, const void *Decoder) { 2083 DecodeStatus S = MCDisassembler::Success; 2084 2085 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2086 unsigned imm = 0; 2087 2088 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2089 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2090 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2091 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2092 2093 if (Inst.getOpcode() == ARM::t2MOVTi16) 2094 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2095 return MCDisassembler::Fail; 2096 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2097 return MCDisassembler::Fail; 2098 2099 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2100 Inst.addOperand(MCOperand::createImm(imm)); 2101 2102 return S; 2103 } 2104 2105 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2106 uint64_t Address, const void *Decoder) { 2107 DecodeStatus S = MCDisassembler::Success; 2108 2109 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2110 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2111 unsigned imm = 0; 2112 2113 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2114 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2115 2116 if (Inst.getOpcode() == ARM::MOVTi16) 2117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2118 return MCDisassembler::Fail; 2119 2120 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2121 return MCDisassembler::Fail; 2122 2123 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2124 Inst.addOperand(MCOperand::createImm(imm)); 2125 2126 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2127 return MCDisassembler::Fail; 2128 2129 return S; 2130 } 2131 2132 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2133 uint64_t Address, const void *Decoder) { 2134 DecodeStatus S = MCDisassembler::Success; 2135 2136 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2137 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2138 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2139 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2140 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2141 2142 if (pred == 0xF) 2143 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2144 2145 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2146 return MCDisassembler::Fail; 2147 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2148 return MCDisassembler::Fail; 2149 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2150 return MCDisassembler::Fail; 2151 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2152 return MCDisassembler::Fail; 2153 2154 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2155 return MCDisassembler::Fail; 2156 2157 return S; 2158 } 2159 2160 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2161 uint64_t Address, const void *Decoder) { 2162 DecodeStatus S = MCDisassembler::Success; 2163 2164 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2165 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2166 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2167 2168 if (Pred == 0xF) 2169 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2170 2171 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2172 return MCDisassembler::Fail; 2173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2174 return MCDisassembler::Fail; 2175 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2176 return MCDisassembler::Fail; 2177 2178 return S; 2179 } 2180 2181 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2182 uint64_t Address, const void *Decoder) { 2183 DecodeStatus S = MCDisassembler::Success; 2184 2185 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2186 2187 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2188 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2189 2190 if (!FeatureBits[ARM::HasV8_1aOps] || 2191 !FeatureBits[ARM::HasV8Ops]) 2192 return MCDisassembler::Fail; 2193 2194 // Decoder can be called from DecodeTST, which does not check the full 2195 // encoding is valid. 2196 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2197 fieldFromInstruction(Insn, 4,4) != 0) 2198 return MCDisassembler::Fail; 2199 if (fieldFromInstruction(Insn, 10,10) != 0 || 2200 fieldFromInstruction(Insn, 0,4) != 0) 2201 S = MCDisassembler::SoftFail; 2202 2203 Inst.setOpcode(ARM::SETPAN); 2204 Inst.addOperand(MCOperand::createImm(Imm)); 2205 2206 return S; 2207 } 2208 2209 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2210 uint64_t Address, const void *Decoder) { 2211 DecodeStatus S = MCDisassembler::Success; 2212 2213 unsigned add = fieldFromInstruction(Val, 12, 1); 2214 unsigned imm = fieldFromInstruction(Val, 0, 12); 2215 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2216 2217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2218 return MCDisassembler::Fail; 2219 2220 if (!add) imm *= -1; 2221 if (imm == 0 && !add) imm = INT32_MIN; 2222 Inst.addOperand(MCOperand::createImm(imm)); 2223 if (Rn == 15) 2224 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2225 2226 return S; 2227 } 2228 2229 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2230 uint64_t Address, const void *Decoder) { 2231 DecodeStatus S = MCDisassembler::Success; 2232 2233 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2234 // U == 1 to add imm, 0 to subtract it. 2235 unsigned U = fieldFromInstruction(Val, 8, 1); 2236 unsigned imm = fieldFromInstruction(Val, 0, 8); 2237 2238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2239 return MCDisassembler::Fail; 2240 2241 if (U) 2242 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2243 else 2244 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2245 2246 return S; 2247 } 2248 2249 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2250 uint64_t Address, const void *Decoder) { 2251 DecodeStatus S = MCDisassembler::Success; 2252 2253 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2254 // U == 1 to add imm, 0 to subtract it. 2255 unsigned U = fieldFromInstruction(Val, 8, 1); 2256 unsigned imm = fieldFromInstruction(Val, 0, 8); 2257 2258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2259 return MCDisassembler::Fail; 2260 2261 if (U) 2262 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2263 else 2264 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2265 2266 return S; 2267 } 2268 2269 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2270 uint64_t Address, const void *Decoder) { 2271 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2272 } 2273 2274 static DecodeStatus 2275 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2276 uint64_t Address, const void *Decoder) { 2277 DecodeStatus Status = MCDisassembler::Success; 2278 2279 // Note the J1 and J2 values are from the encoded instruction. So here 2280 // change them to I1 and I2 values via as documented: 2281 // I1 = NOT(J1 EOR S); 2282 // I2 = NOT(J2 EOR S); 2283 // and build the imm32 with one trailing zero as documented: 2284 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2285 unsigned S = fieldFromInstruction(Insn, 26, 1); 2286 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2287 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2288 unsigned I1 = !(J1 ^ S); 2289 unsigned I2 = !(J2 ^ S); 2290 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2291 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2292 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2293 int imm32 = SignExtend32<25>(tmp << 1); 2294 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2295 true, 4, Inst, Decoder)) 2296 Inst.addOperand(MCOperand::createImm(imm32)); 2297 2298 return Status; 2299 } 2300 2301 static DecodeStatus 2302 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2303 uint64_t Address, const void *Decoder) { 2304 DecodeStatus S = MCDisassembler::Success; 2305 2306 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2307 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2308 2309 if (pred == 0xF) { 2310 Inst.setOpcode(ARM::BLXi); 2311 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2312 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2313 true, 4, Inst, Decoder)) 2314 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2315 return S; 2316 } 2317 2318 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2319 true, 4, Inst, Decoder)) 2320 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2321 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2322 return MCDisassembler::Fail; 2323 2324 return S; 2325 } 2326 2327 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2328 uint64_t Address, const void *Decoder) { 2329 DecodeStatus S = MCDisassembler::Success; 2330 2331 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2332 unsigned align = fieldFromInstruction(Val, 4, 2); 2333 2334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2335 return MCDisassembler::Fail; 2336 if (!align) 2337 Inst.addOperand(MCOperand::createImm(0)); 2338 else 2339 Inst.addOperand(MCOperand::createImm(4 << align)); 2340 2341 return S; 2342 } 2343 2344 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2345 uint64_t Address, const void *Decoder) { 2346 DecodeStatus S = MCDisassembler::Success; 2347 2348 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2349 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2350 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2351 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2352 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2353 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2354 2355 // First output register 2356 switch (Inst.getOpcode()) { 2357 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2358 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2359 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2360 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2361 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2362 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2363 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2364 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2365 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2366 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2367 return MCDisassembler::Fail; 2368 break; 2369 case ARM::VLD2b16: 2370 case ARM::VLD2b32: 2371 case ARM::VLD2b8: 2372 case ARM::VLD2b16wb_fixed: 2373 case ARM::VLD2b16wb_register: 2374 case ARM::VLD2b32wb_fixed: 2375 case ARM::VLD2b32wb_register: 2376 case ARM::VLD2b8wb_fixed: 2377 case ARM::VLD2b8wb_register: 2378 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2379 return MCDisassembler::Fail; 2380 break; 2381 default: 2382 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2383 return MCDisassembler::Fail; 2384 } 2385 2386 // Second output register 2387 switch (Inst.getOpcode()) { 2388 case ARM::VLD3d8: 2389 case ARM::VLD3d16: 2390 case ARM::VLD3d32: 2391 case ARM::VLD3d8_UPD: 2392 case ARM::VLD3d16_UPD: 2393 case ARM::VLD3d32_UPD: 2394 case ARM::VLD4d8: 2395 case ARM::VLD4d16: 2396 case ARM::VLD4d32: 2397 case ARM::VLD4d8_UPD: 2398 case ARM::VLD4d16_UPD: 2399 case ARM::VLD4d32_UPD: 2400 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2401 return MCDisassembler::Fail; 2402 break; 2403 case ARM::VLD3q8: 2404 case ARM::VLD3q16: 2405 case ARM::VLD3q32: 2406 case ARM::VLD3q8_UPD: 2407 case ARM::VLD3q16_UPD: 2408 case ARM::VLD3q32_UPD: 2409 case ARM::VLD4q8: 2410 case ARM::VLD4q16: 2411 case ARM::VLD4q32: 2412 case ARM::VLD4q8_UPD: 2413 case ARM::VLD4q16_UPD: 2414 case ARM::VLD4q32_UPD: 2415 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2416 return MCDisassembler::Fail; 2417 break; 2418 default: 2419 break; 2420 } 2421 2422 // Third output register 2423 switch(Inst.getOpcode()) { 2424 case ARM::VLD3d8: 2425 case ARM::VLD3d16: 2426 case ARM::VLD3d32: 2427 case ARM::VLD3d8_UPD: 2428 case ARM::VLD3d16_UPD: 2429 case ARM::VLD3d32_UPD: 2430 case ARM::VLD4d8: 2431 case ARM::VLD4d16: 2432 case ARM::VLD4d32: 2433 case ARM::VLD4d8_UPD: 2434 case ARM::VLD4d16_UPD: 2435 case ARM::VLD4d32_UPD: 2436 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2437 return MCDisassembler::Fail; 2438 break; 2439 case ARM::VLD3q8: 2440 case ARM::VLD3q16: 2441 case ARM::VLD3q32: 2442 case ARM::VLD3q8_UPD: 2443 case ARM::VLD3q16_UPD: 2444 case ARM::VLD3q32_UPD: 2445 case ARM::VLD4q8: 2446 case ARM::VLD4q16: 2447 case ARM::VLD4q32: 2448 case ARM::VLD4q8_UPD: 2449 case ARM::VLD4q16_UPD: 2450 case ARM::VLD4q32_UPD: 2451 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2452 return MCDisassembler::Fail; 2453 break; 2454 default: 2455 break; 2456 } 2457 2458 // Fourth output register 2459 switch (Inst.getOpcode()) { 2460 case ARM::VLD4d8: 2461 case ARM::VLD4d16: 2462 case ARM::VLD4d32: 2463 case ARM::VLD4d8_UPD: 2464 case ARM::VLD4d16_UPD: 2465 case ARM::VLD4d32_UPD: 2466 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2467 return MCDisassembler::Fail; 2468 break; 2469 case ARM::VLD4q8: 2470 case ARM::VLD4q16: 2471 case ARM::VLD4q32: 2472 case ARM::VLD4q8_UPD: 2473 case ARM::VLD4q16_UPD: 2474 case ARM::VLD4q32_UPD: 2475 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2476 return MCDisassembler::Fail; 2477 break; 2478 default: 2479 break; 2480 } 2481 2482 // Writeback operand 2483 switch (Inst.getOpcode()) { 2484 case ARM::VLD1d8wb_fixed: 2485 case ARM::VLD1d16wb_fixed: 2486 case ARM::VLD1d32wb_fixed: 2487 case ARM::VLD1d64wb_fixed: 2488 case ARM::VLD1d8wb_register: 2489 case ARM::VLD1d16wb_register: 2490 case ARM::VLD1d32wb_register: 2491 case ARM::VLD1d64wb_register: 2492 case ARM::VLD1q8wb_fixed: 2493 case ARM::VLD1q16wb_fixed: 2494 case ARM::VLD1q32wb_fixed: 2495 case ARM::VLD1q64wb_fixed: 2496 case ARM::VLD1q8wb_register: 2497 case ARM::VLD1q16wb_register: 2498 case ARM::VLD1q32wb_register: 2499 case ARM::VLD1q64wb_register: 2500 case ARM::VLD1d8Twb_fixed: 2501 case ARM::VLD1d8Twb_register: 2502 case ARM::VLD1d16Twb_fixed: 2503 case ARM::VLD1d16Twb_register: 2504 case ARM::VLD1d32Twb_fixed: 2505 case ARM::VLD1d32Twb_register: 2506 case ARM::VLD1d64Twb_fixed: 2507 case ARM::VLD1d64Twb_register: 2508 case ARM::VLD1d8Qwb_fixed: 2509 case ARM::VLD1d8Qwb_register: 2510 case ARM::VLD1d16Qwb_fixed: 2511 case ARM::VLD1d16Qwb_register: 2512 case ARM::VLD1d32Qwb_fixed: 2513 case ARM::VLD1d32Qwb_register: 2514 case ARM::VLD1d64Qwb_fixed: 2515 case ARM::VLD1d64Qwb_register: 2516 case ARM::VLD2d8wb_fixed: 2517 case ARM::VLD2d16wb_fixed: 2518 case ARM::VLD2d32wb_fixed: 2519 case ARM::VLD2q8wb_fixed: 2520 case ARM::VLD2q16wb_fixed: 2521 case ARM::VLD2q32wb_fixed: 2522 case ARM::VLD2d8wb_register: 2523 case ARM::VLD2d16wb_register: 2524 case ARM::VLD2d32wb_register: 2525 case ARM::VLD2q8wb_register: 2526 case ARM::VLD2q16wb_register: 2527 case ARM::VLD2q32wb_register: 2528 case ARM::VLD2b8wb_fixed: 2529 case ARM::VLD2b16wb_fixed: 2530 case ARM::VLD2b32wb_fixed: 2531 case ARM::VLD2b8wb_register: 2532 case ARM::VLD2b16wb_register: 2533 case ARM::VLD2b32wb_register: 2534 Inst.addOperand(MCOperand::createImm(0)); 2535 break; 2536 case ARM::VLD3d8_UPD: 2537 case ARM::VLD3d16_UPD: 2538 case ARM::VLD3d32_UPD: 2539 case ARM::VLD3q8_UPD: 2540 case ARM::VLD3q16_UPD: 2541 case ARM::VLD3q32_UPD: 2542 case ARM::VLD4d8_UPD: 2543 case ARM::VLD4d16_UPD: 2544 case ARM::VLD4d32_UPD: 2545 case ARM::VLD4q8_UPD: 2546 case ARM::VLD4q16_UPD: 2547 case ARM::VLD4q32_UPD: 2548 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2549 return MCDisassembler::Fail; 2550 break; 2551 default: 2552 break; 2553 } 2554 2555 // AddrMode6 Base (register+alignment) 2556 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2557 return MCDisassembler::Fail; 2558 2559 // AddrMode6 Offset (register) 2560 switch (Inst.getOpcode()) { 2561 default: 2562 // The below have been updated to have explicit am6offset split 2563 // between fixed and register offset. For those instructions not 2564 // yet updated, we need to add an additional reg0 operand for the 2565 // fixed variant. 2566 // 2567 // The fixed offset encodes as Rm == 0xd, so we check for that. 2568 if (Rm == 0xd) { 2569 Inst.addOperand(MCOperand::createReg(0)); 2570 break; 2571 } 2572 // Fall through to handle the register offset variant. 2573 LLVM_FALLTHROUGH; 2574 case ARM::VLD1d8wb_fixed: 2575 case ARM::VLD1d16wb_fixed: 2576 case ARM::VLD1d32wb_fixed: 2577 case ARM::VLD1d64wb_fixed: 2578 case ARM::VLD1d8Twb_fixed: 2579 case ARM::VLD1d16Twb_fixed: 2580 case ARM::VLD1d32Twb_fixed: 2581 case ARM::VLD1d64Twb_fixed: 2582 case ARM::VLD1d8Qwb_fixed: 2583 case ARM::VLD1d16Qwb_fixed: 2584 case ARM::VLD1d32Qwb_fixed: 2585 case ARM::VLD1d64Qwb_fixed: 2586 case ARM::VLD1d8wb_register: 2587 case ARM::VLD1d16wb_register: 2588 case ARM::VLD1d32wb_register: 2589 case ARM::VLD1d64wb_register: 2590 case ARM::VLD1q8wb_fixed: 2591 case ARM::VLD1q16wb_fixed: 2592 case ARM::VLD1q32wb_fixed: 2593 case ARM::VLD1q64wb_fixed: 2594 case ARM::VLD1q8wb_register: 2595 case ARM::VLD1q16wb_register: 2596 case ARM::VLD1q32wb_register: 2597 case ARM::VLD1q64wb_register: 2598 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2599 // variant encodes Rm == 0xf. Anything else is a register offset post- 2600 // increment and we need to add the register operand to the instruction. 2601 if (Rm != 0xD && Rm != 0xF && 2602 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2603 return MCDisassembler::Fail; 2604 break; 2605 case ARM::VLD2d8wb_fixed: 2606 case ARM::VLD2d16wb_fixed: 2607 case ARM::VLD2d32wb_fixed: 2608 case ARM::VLD2b8wb_fixed: 2609 case ARM::VLD2b16wb_fixed: 2610 case ARM::VLD2b32wb_fixed: 2611 case ARM::VLD2q8wb_fixed: 2612 case ARM::VLD2q16wb_fixed: 2613 case ARM::VLD2q32wb_fixed: 2614 break; 2615 } 2616 2617 return S; 2618 } 2619 2620 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2621 uint64_t Address, const void *Decoder) { 2622 unsigned type = fieldFromInstruction(Insn, 8, 4); 2623 unsigned align = fieldFromInstruction(Insn, 4, 2); 2624 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2625 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2626 if (type == 10 && align == 3) return MCDisassembler::Fail; 2627 2628 unsigned load = fieldFromInstruction(Insn, 21, 1); 2629 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2630 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2631 } 2632 2633 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2634 uint64_t Address, const void *Decoder) { 2635 unsigned size = fieldFromInstruction(Insn, 6, 2); 2636 if (size == 3) return MCDisassembler::Fail; 2637 2638 unsigned type = fieldFromInstruction(Insn, 8, 4); 2639 unsigned align = fieldFromInstruction(Insn, 4, 2); 2640 if (type == 8 && align == 3) return MCDisassembler::Fail; 2641 if (type == 9 && align == 3) return MCDisassembler::Fail; 2642 2643 unsigned load = fieldFromInstruction(Insn, 21, 1); 2644 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2645 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2646 } 2647 2648 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2649 uint64_t Address, const void *Decoder) { 2650 unsigned size = fieldFromInstruction(Insn, 6, 2); 2651 if (size == 3) return MCDisassembler::Fail; 2652 2653 unsigned align = fieldFromInstruction(Insn, 4, 2); 2654 if (align & 2) return MCDisassembler::Fail; 2655 2656 unsigned load = fieldFromInstruction(Insn, 21, 1); 2657 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2658 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2659 } 2660 2661 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2662 uint64_t Address, const void *Decoder) { 2663 unsigned size = fieldFromInstruction(Insn, 6, 2); 2664 if (size == 3) return MCDisassembler::Fail; 2665 2666 unsigned load = fieldFromInstruction(Insn, 21, 1); 2667 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2668 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2669 } 2670 2671 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2672 uint64_t Address, const void *Decoder) { 2673 DecodeStatus S = MCDisassembler::Success; 2674 2675 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2676 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2677 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2678 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2679 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2680 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2681 2682 // Writeback Operand 2683 switch (Inst.getOpcode()) { 2684 case ARM::VST1d8wb_fixed: 2685 case ARM::VST1d16wb_fixed: 2686 case ARM::VST1d32wb_fixed: 2687 case ARM::VST1d64wb_fixed: 2688 case ARM::VST1d8wb_register: 2689 case ARM::VST1d16wb_register: 2690 case ARM::VST1d32wb_register: 2691 case ARM::VST1d64wb_register: 2692 case ARM::VST1q8wb_fixed: 2693 case ARM::VST1q16wb_fixed: 2694 case ARM::VST1q32wb_fixed: 2695 case ARM::VST1q64wb_fixed: 2696 case ARM::VST1q8wb_register: 2697 case ARM::VST1q16wb_register: 2698 case ARM::VST1q32wb_register: 2699 case ARM::VST1q64wb_register: 2700 case ARM::VST1d8Twb_fixed: 2701 case ARM::VST1d16Twb_fixed: 2702 case ARM::VST1d32Twb_fixed: 2703 case ARM::VST1d64Twb_fixed: 2704 case ARM::VST1d8Twb_register: 2705 case ARM::VST1d16Twb_register: 2706 case ARM::VST1d32Twb_register: 2707 case ARM::VST1d64Twb_register: 2708 case ARM::VST1d8Qwb_fixed: 2709 case ARM::VST1d16Qwb_fixed: 2710 case ARM::VST1d32Qwb_fixed: 2711 case ARM::VST1d64Qwb_fixed: 2712 case ARM::VST1d8Qwb_register: 2713 case ARM::VST1d16Qwb_register: 2714 case ARM::VST1d32Qwb_register: 2715 case ARM::VST1d64Qwb_register: 2716 case ARM::VST2d8wb_fixed: 2717 case ARM::VST2d16wb_fixed: 2718 case ARM::VST2d32wb_fixed: 2719 case ARM::VST2d8wb_register: 2720 case ARM::VST2d16wb_register: 2721 case ARM::VST2d32wb_register: 2722 case ARM::VST2q8wb_fixed: 2723 case ARM::VST2q16wb_fixed: 2724 case ARM::VST2q32wb_fixed: 2725 case ARM::VST2q8wb_register: 2726 case ARM::VST2q16wb_register: 2727 case ARM::VST2q32wb_register: 2728 case ARM::VST2b8wb_fixed: 2729 case ARM::VST2b16wb_fixed: 2730 case ARM::VST2b32wb_fixed: 2731 case ARM::VST2b8wb_register: 2732 case ARM::VST2b16wb_register: 2733 case ARM::VST2b32wb_register: 2734 if (Rm == 0xF) 2735 return MCDisassembler::Fail; 2736 Inst.addOperand(MCOperand::createImm(0)); 2737 break; 2738 case ARM::VST3d8_UPD: 2739 case ARM::VST3d16_UPD: 2740 case ARM::VST3d32_UPD: 2741 case ARM::VST3q8_UPD: 2742 case ARM::VST3q16_UPD: 2743 case ARM::VST3q32_UPD: 2744 case ARM::VST4d8_UPD: 2745 case ARM::VST4d16_UPD: 2746 case ARM::VST4d32_UPD: 2747 case ARM::VST4q8_UPD: 2748 case ARM::VST4q16_UPD: 2749 case ARM::VST4q32_UPD: 2750 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2751 return MCDisassembler::Fail; 2752 break; 2753 default: 2754 break; 2755 } 2756 2757 // AddrMode6 Base (register+alignment) 2758 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2759 return MCDisassembler::Fail; 2760 2761 // AddrMode6 Offset (register) 2762 switch (Inst.getOpcode()) { 2763 default: 2764 if (Rm == 0xD) 2765 Inst.addOperand(MCOperand::createReg(0)); 2766 else if (Rm != 0xF) { 2767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2768 return MCDisassembler::Fail; 2769 } 2770 break; 2771 case ARM::VST1d8wb_fixed: 2772 case ARM::VST1d16wb_fixed: 2773 case ARM::VST1d32wb_fixed: 2774 case ARM::VST1d64wb_fixed: 2775 case ARM::VST1q8wb_fixed: 2776 case ARM::VST1q16wb_fixed: 2777 case ARM::VST1q32wb_fixed: 2778 case ARM::VST1q64wb_fixed: 2779 case ARM::VST1d8Twb_fixed: 2780 case ARM::VST1d16Twb_fixed: 2781 case ARM::VST1d32Twb_fixed: 2782 case ARM::VST1d64Twb_fixed: 2783 case ARM::VST1d8Qwb_fixed: 2784 case ARM::VST1d16Qwb_fixed: 2785 case ARM::VST1d32Qwb_fixed: 2786 case ARM::VST1d64Qwb_fixed: 2787 case ARM::VST2d8wb_fixed: 2788 case ARM::VST2d16wb_fixed: 2789 case ARM::VST2d32wb_fixed: 2790 case ARM::VST2q8wb_fixed: 2791 case ARM::VST2q16wb_fixed: 2792 case ARM::VST2q32wb_fixed: 2793 case ARM::VST2b8wb_fixed: 2794 case ARM::VST2b16wb_fixed: 2795 case ARM::VST2b32wb_fixed: 2796 break; 2797 } 2798 2799 // First input register 2800 switch (Inst.getOpcode()) { 2801 case ARM::VST1q16: 2802 case ARM::VST1q32: 2803 case ARM::VST1q64: 2804 case ARM::VST1q8: 2805 case ARM::VST1q16wb_fixed: 2806 case ARM::VST1q16wb_register: 2807 case ARM::VST1q32wb_fixed: 2808 case ARM::VST1q32wb_register: 2809 case ARM::VST1q64wb_fixed: 2810 case ARM::VST1q64wb_register: 2811 case ARM::VST1q8wb_fixed: 2812 case ARM::VST1q8wb_register: 2813 case ARM::VST2d16: 2814 case ARM::VST2d32: 2815 case ARM::VST2d8: 2816 case ARM::VST2d16wb_fixed: 2817 case ARM::VST2d16wb_register: 2818 case ARM::VST2d32wb_fixed: 2819 case ARM::VST2d32wb_register: 2820 case ARM::VST2d8wb_fixed: 2821 case ARM::VST2d8wb_register: 2822 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2823 return MCDisassembler::Fail; 2824 break; 2825 case ARM::VST2b16: 2826 case ARM::VST2b32: 2827 case ARM::VST2b8: 2828 case ARM::VST2b16wb_fixed: 2829 case ARM::VST2b16wb_register: 2830 case ARM::VST2b32wb_fixed: 2831 case ARM::VST2b32wb_register: 2832 case ARM::VST2b8wb_fixed: 2833 case ARM::VST2b8wb_register: 2834 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2835 return MCDisassembler::Fail; 2836 break; 2837 default: 2838 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2839 return MCDisassembler::Fail; 2840 } 2841 2842 // Second input register 2843 switch (Inst.getOpcode()) { 2844 case ARM::VST3d8: 2845 case ARM::VST3d16: 2846 case ARM::VST3d32: 2847 case ARM::VST3d8_UPD: 2848 case ARM::VST3d16_UPD: 2849 case ARM::VST3d32_UPD: 2850 case ARM::VST4d8: 2851 case ARM::VST4d16: 2852 case ARM::VST4d32: 2853 case ARM::VST4d8_UPD: 2854 case ARM::VST4d16_UPD: 2855 case ARM::VST4d32_UPD: 2856 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2857 return MCDisassembler::Fail; 2858 break; 2859 case ARM::VST3q8: 2860 case ARM::VST3q16: 2861 case ARM::VST3q32: 2862 case ARM::VST3q8_UPD: 2863 case ARM::VST3q16_UPD: 2864 case ARM::VST3q32_UPD: 2865 case ARM::VST4q8: 2866 case ARM::VST4q16: 2867 case ARM::VST4q32: 2868 case ARM::VST4q8_UPD: 2869 case ARM::VST4q16_UPD: 2870 case ARM::VST4q32_UPD: 2871 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2872 return MCDisassembler::Fail; 2873 break; 2874 default: 2875 break; 2876 } 2877 2878 // Third input register 2879 switch (Inst.getOpcode()) { 2880 case ARM::VST3d8: 2881 case ARM::VST3d16: 2882 case ARM::VST3d32: 2883 case ARM::VST3d8_UPD: 2884 case ARM::VST3d16_UPD: 2885 case ARM::VST3d32_UPD: 2886 case ARM::VST4d8: 2887 case ARM::VST4d16: 2888 case ARM::VST4d32: 2889 case ARM::VST4d8_UPD: 2890 case ARM::VST4d16_UPD: 2891 case ARM::VST4d32_UPD: 2892 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2893 return MCDisassembler::Fail; 2894 break; 2895 case ARM::VST3q8: 2896 case ARM::VST3q16: 2897 case ARM::VST3q32: 2898 case ARM::VST3q8_UPD: 2899 case ARM::VST3q16_UPD: 2900 case ARM::VST3q32_UPD: 2901 case ARM::VST4q8: 2902 case ARM::VST4q16: 2903 case ARM::VST4q32: 2904 case ARM::VST4q8_UPD: 2905 case ARM::VST4q16_UPD: 2906 case ARM::VST4q32_UPD: 2907 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2908 return MCDisassembler::Fail; 2909 break; 2910 default: 2911 break; 2912 } 2913 2914 // Fourth input register 2915 switch (Inst.getOpcode()) { 2916 case ARM::VST4d8: 2917 case ARM::VST4d16: 2918 case ARM::VST4d32: 2919 case ARM::VST4d8_UPD: 2920 case ARM::VST4d16_UPD: 2921 case ARM::VST4d32_UPD: 2922 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2923 return MCDisassembler::Fail; 2924 break; 2925 case ARM::VST4q8: 2926 case ARM::VST4q16: 2927 case ARM::VST4q32: 2928 case ARM::VST4q8_UPD: 2929 case ARM::VST4q16_UPD: 2930 case ARM::VST4q32_UPD: 2931 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2932 return MCDisassembler::Fail; 2933 break; 2934 default: 2935 break; 2936 } 2937 2938 return S; 2939 } 2940 2941 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2942 uint64_t Address, const void *Decoder) { 2943 DecodeStatus S = MCDisassembler::Success; 2944 2945 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2946 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2947 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2948 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2949 unsigned align = fieldFromInstruction(Insn, 4, 1); 2950 unsigned size = fieldFromInstruction(Insn, 6, 2); 2951 2952 if (size == 0 && align == 1) 2953 return MCDisassembler::Fail; 2954 align *= (1 << size); 2955 2956 switch (Inst.getOpcode()) { 2957 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2958 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2959 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2960 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2961 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2962 return MCDisassembler::Fail; 2963 break; 2964 default: 2965 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2966 return MCDisassembler::Fail; 2967 break; 2968 } 2969 if (Rm != 0xF) { 2970 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2971 return MCDisassembler::Fail; 2972 } 2973 2974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2975 return MCDisassembler::Fail; 2976 Inst.addOperand(MCOperand::createImm(align)); 2977 2978 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2979 // variant encodes Rm == 0xf. Anything else is a register offset post- 2980 // increment and we need to add the register operand to the instruction. 2981 if (Rm != 0xD && Rm != 0xF && 2982 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2983 return MCDisassembler::Fail; 2984 2985 return S; 2986 } 2987 2988 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2989 uint64_t Address, const void *Decoder) { 2990 DecodeStatus S = MCDisassembler::Success; 2991 2992 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2993 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2994 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2995 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2996 unsigned align = fieldFromInstruction(Insn, 4, 1); 2997 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2998 align *= 2*size; 2999 3000 switch (Inst.getOpcode()) { 3001 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3002 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3003 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3004 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3005 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3006 return MCDisassembler::Fail; 3007 break; 3008 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3009 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3010 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3011 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3012 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3013 return MCDisassembler::Fail; 3014 break; 3015 default: 3016 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3017 return MCDisassembler::Fail; 3018 break; 3019 } 3020 3021 if (Rm != 0xF) 3022 Inst.addOperand(MCOperand::createImm(0)); 3023 3024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3025 return MCDisassembler::Fail; 3026 Inst.addOperand(MCOperand::createImm(align)); 3027 3028 if (Rm != 0xD && Rm != 0xF) { 3029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3030 return MCDisassembler::Fail; 3031 } 3032 3033 return S; 3034 } 3035 3036 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3037 uint64_t Address, const void *Decoder) { 3038 DecodeStatus S = MCDisassembler::Success; 3039 3040 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3041 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3042 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3043 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3044 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3045 3046 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3047 return MCDisassembler::Fail; 3048 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3049 return MCDisassembler::Fail; 3050 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 if (Rm != 0xF) { 3053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3054 return MCDisassembler::Fail; 3055 } 3056 3057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3058 return MCDisassembler::Fail; 3059 Inst.addOperand(MCOperand::createImm(0)); 3060 3061 if (Rm == 0xD) 3062 Inst.addOperand(MCOperand::createReg(0)); 3063 else if (Rm != 0xF) { 3064 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3065 return MCDisassembler::Fail; 3066 } 3067 3068 return S; 3069 } 3070 3071 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3072 uint64_t Address, const void *Decoder) { 3073 DecodeStatus S = MCDisassembler::Success; 3074 3075 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3076 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3077 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3078 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3079 unsigned size = fieldFromInstruction(Insn, 6, 2); 3080 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3081 unsigned align = fieldFromInstruction(Insn, 4, 1); 3082 3083 if (size == 0x3) { 3084 if (align == 0) 3085 return MCDisassembler::Fail; 3086 align = 16; 3087 } else { 3088 if (size == 2) { 3089 align *= 8; 3090 } else { 3091 size = 1 << size; 3092 align *= 4*size; 3093 } 3094 } 3095 3096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3097 return MCDisassembler::Fail; 3098 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3099 return MCDisassembler::Fail; 3100 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3101 return MCDisassembler::Fail; 3102 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3103 return MCDisassembler::Fail; 3104 if (Rm != 0xF) { 3105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 } 3108 3109 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3110 return MCDisassembler::Fail; 3111 Inst.addOperand(MCOperand::createImm(align)); 3112 3113 if (Rm == 0xD) 3114 Inst.addOperand(MCOperand::createReg(0)); 3115 else if (Rm != 0xF) { 3116 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3117 return MCDisassembler::Fail; 3118 } 3119 3120 return S; 3121 } 3122 3123 static DecodeStatus 3124 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3125 uint64_t Address, const void *Decoder) { 3126 DecodeStatus S = MCDisassembler::Success; 3127 3128 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3129 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3130 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3131 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3132 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3133 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3134 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3135 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3136 3137 if (Q) { 3138 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3139 return MCDisassembler::Fail; 3140 } else { 3141 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3142 return MCDisassembler::Fail; 3143 } 3144 3145 Inst.addOperand(MCOperand::createImm(imm)); 3146 3147 switch (Inst.getOpcode()) { 3148 case ARM::VORRiv4i16: 3149 case ARM::VORRiv2i32: 3150 case ARM::VBICiv4i16: 3151 case ARM::VBICiv2i32: 3152 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3153 return MCDisassembler::Fail; 3154 break; 3155 case ARM::VORRiv8i16: 3156 case ARM::VORRiv4i32: 3157 case ARM::VBICiv8i16: 3158 case ARM::VBICiv4i32: 3159 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3160 return MCDisassembler::Fail; 3161 break; 3162 default: 3163 break; 3164 } 3165 3166 return S; 3167 } 3168 3169 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3170 uint64_t Address, const void *Decoder) { 3171 DecodeStatus S = MCDisassembler::Success; 3172 3173 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3174 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3175 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3176 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3177 unsigned size = fieldFromInstruction(Insn, 18, 2); 3178 3179 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3180 return MCDisassembler::Fail; 3181 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3182 return MCDisassembler::Fail; 3183 Inst.addOperand(MCOperand::createImm(8 << size)); 3184 3185 return S; 3186 } 3187 3188 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3189 uint64_t Address, const void *Decoder) { 3190 Inst.addOperand(MCOperand::createImm(8 - Val)); 3191 return MCDisassembler::Success; 3192 } 3193 3194 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3195 uint64_t Address, const void *Decoder) { 3196 Inst.addOperand(MCOperand::createImm(16 - Val)); 3197 return MCDisassembler::Success; 3198 } 3199 3200 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3201 uint64_t Address, const void *Decoder) { 3202 Inst.addOperand(MCOperand::createImm(32 - Val)); 3203 return MCDisassembler::Success; 3204 } 3205 3206 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3207 uint64_t Address, const void *Decoder) { 3208 Inst.addOperand(MCOperand::createImm(64 - Val)); 3209 return MCDisassembler::Success; 3210 } 3211 3212 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3213 uint64_t Address, const void *Decoder) { 3214 DecodeStatus S = MCDisassembler::Success; 3215 3216 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3217 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3218 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3219 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3220 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3221 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3222 unsigned op = fieldFromInstruction(Insn, 6, 1); 3223 3224 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3225 return MCDisassembler::Fail; 3226 if (op) { 3227 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3228 return MCDisassembler::Fail; // Writeback 3229 } 3230 3231 switch (Inst.getOpcode()) { 3232 case ARM::VTBL2: 3233 case ARM::VTBX2: 3234 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3235 return MCDisassembler::Fail; 3236 break; 3237 default: 3238 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3239 return MCDisassembler::Fail; 3240 } 3241 3242 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3243 return MCDisassembler::Fail; 3244 3245 return S; 3246 } 3247 3248 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3249 uint64_t Address, const void *Decoder) { 3250 DecodeStatus S = MCDisassembler::Success; 3251 3252 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3253 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3254 3255 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3256 return MCDisassembler::Fail; 3257 3258 switch(Inst.getOpcode()) { 3259 default: 3260 return MCDisassembler::Fail; 3261 case ARM::tADR: 3262 break; // tADR does not explicitly represent the PC as an operand. 3263 case ARM::tADDrSPi: 3264 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3265 break; 3266 } 3267 3268 Inst.addOperand(MCOperand::createImm(imm)); 3269 return S; 3270 } 3271 3272 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3273 uint64_t Address, const void *Decoder) { 3274 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3275 true, 2, Inst, Decoder)) 3276 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3277 return MCDisassembler::Success; 3278 } 3279 3280 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3281 uint64_t Address, const void *Decoder) { 3282 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3283 true, 4, Inst, Decoder)) 3284 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3285 return MCDisassembler::Success; 3286 } 3287 3288 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3289 uint64_t Address, const void *Decoder) { 3290 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3291 true, 2, Inst, Decoder)) 3292 Inst.addOperand(MCOperand::createImm(Val << 1)); 3293 return MCDisassembler::Success; 3294 } 3295 3296 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3297 uint64_t Address, const void *Decoder) { 3298 DecodeStatus S = MCDisassembler::Success; 3299 3300 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3301 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3302 3303 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3304 return MCDisassembler::Fail; 3305 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 3308 return S; 3309 } 3310 3311 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3312 uint64_t Address, const void *Decoder) { 3313 DecodeStatus S = MCDisassembler::Success; 3314 3315 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3316 unsigned imm = fieldFromInstruction(Val, 3, 5); 3317 3318 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3319 return MCDisassembler::Fail; 3320 Inst.addOperand(MCOperand::createImm(imm)); 3321 3322 return S; 3323 } 3324 3325 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3326 uint64_t Address, const void *Decoder) { 3327 unsigned imm = Val << 2; 3328 3329 Inst.addOperand(MCOperand::createImm(imm)); 3330 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3331 3332 return MCDisassembler::Success; 3333 } 3334 3335 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3336 uint64_t Address, const void *Decoder) { 3337 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3338 Inst.addOperand(MCOperand::createImm(Val)); 3339 3340 return MCDisassembler::Success; 3341 } 3342 3343 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3344 uint64_t Address, const void *Decoder) { 3345 DecodeStatus S = MCDisassembler::Success; 3346 3347 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3348 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3349 unsigned imm = fieldFromInstruction(Val, 0, 2); 3350 3351 // Thumb stores cannot use PC as dest register. 3352 switch (Inst.getOpcode()) { 3353 case ARM::t2STRHs: 3354 case ARM::t2STRBs: 3355 case ARM::t2STRs: 3356 if (Rn == 15) 3357 return MCDisassembler::Fail; 3358 break; 3359 default: 3360 break; 3361 } 3362 3363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3364 return MCDisassembler::Fail; 3365 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 Inst.addOperand(MCOperand::createImm(imm)); 3368 3369 return S; 3370 } 3371 3372 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3373 uint64_t Address, const void *Decoder) { 3374 DecodeStatus S = MCDisassembler::Success; 3375 3376 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3377 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3378 3379 const FeatureBitset &featureBits = 3380 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3381 3382 bool hasMP = featureBits[ARM::FeatureMP]; 3383 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3384 3385 if (Rn == 15) { 3386 switch (Inst.getOpcode()) { 3387 case ARM::t2LDRBs: 3388 Inst.setOpcode(ARM::t2LDRBpci); 3389 break; 3390 case ARM::t2LDRHs: 3391 Inst.setOpcode(ARM::t2LDRHpci); 3392 break; 3393 case ARM::t2LDRSHs: 3394 Inst.setOpcode(ARM::t2LDRSHpci); 3395 break; 3396 case ARM::t2LDRSBs: 3397 Inst.setOpcode(ARM::t2LDRSBpci); 3398 break; 3399 case ARM::t2LDRs: 3400 Inst.setOpcode(ARM::t2LDRpci); 3401 break; 3402 case ARM::t2PLDs: 3403 Inst.setOpcode(ARM::t2PLDpci); 3404 break; 3405 case ARM::t2PLIs: 3406 Inst.setOpcode(ARM::t2PLIpci); 3407 break; 3408 default: 3409 return MCDisassembler::Fail; 3410 } 3411 3412 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3413 } 3414 3415 if (Rt == 15) { 3416 switch (Inst.getOpcode()) { 3417 case ARM::t2LDRSHs: 3418 return MCDisassembler::Fail; 3419 case ARM::t2LDRHs: 3420 Inst.setOpcode(ARM::t2PLDWs); 3421 break; 3422 case ARM::t2LDRSBs: 3423 Inst.setOpcode(ARM::t2PLIs); 3424 break; 3425 default: 3426 break; 3427 } 3428 } 3429 3430 switch (Inst.getOpcode()) { 3431 case ARM::t2PLDs: 3432 break; 3433 case ARM::t2PLIs: 3434 if (!hasV7Ops) 3435 return MCDisassembler::Fail; 3436 break; 3437 case ARM::t2PLDWs: 3438 if (!hasV7Ops || !hasMP) 3439 return MCDisassembler::Fail; 3440 break; 3441 default: 3442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3443 return MCDisassembler::Fail; 3444 } 3445 3446 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3447 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3448 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3449 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3450 return MCDisassembler::Fail; 3451 3452 return S; 3453 } 3454 3455 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3456 uint64_t Address, const void* Decoder) { 3457 DecodeStatus S = MCDisassembler::Success; 3458 3459 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3460 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3461 unsigned U = fieldFromInstruction(Insn, 9, 1); 3462 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3463 imm |= (U << 8); 3464 imm |= (Rn << 9); 3465 unsigned add = fieldFromInstruction(Insn, 9, 1); 3466 3467 const FeatureBitset &featureBits = 3468 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3469 3470 bool hasMP = featureBits[ARM::FeatureMP]; 3471 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3472 3473 if (Rn == 15) { 3474 switch (Inst.getOpcode()) { 3475 case ARM::t2LDRi8: 3476 Inst.setOpcode(ARM::t2LDRpci); 3477 break; 3478 case ARM::t2LDRBi8: 3479 Inst.setOpcode(ARM::t2LDRBpci); 3480 break; 3481 case ARM::t2LDRSBi8: 3482 Inst.setOpcode(ARM::t2LDRSBpci); 3483 break; 3484 case ARM::t2LDRHi8: 3485 Inst.setOpcode(ARM::t2LDRHpci); 3486 break; 3487 case ARM::t2LDRSHi8: 3488 Inst.setOpcode(ARM::t2LDRSHpci); 3489 break; 3490 case ARM::t2PLDi8: 3491 Inst.setOpcode(ARM::t2PLDpci); 3492 break; 3493 case ARM::t2PLIi8: 3494 Inst.setOpcode(ARM::t2PLIpci); 3495 break; 3496 default: 3497 return MCDisassembler::Fail; 3498 } 3499 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3500 } 3501 3502 if (Rt == 15) { 3503 switch (Inst.getOpcode()) { 3504 case ARM::t2LDRSHi8: 3505 return MCDisassembler::Fail; 3506 case ARM::t2LDRHi8: 3507 if (!add) 3508 Inst.setOpcode(ARM::t2PLDWi8); 3509 break; 3510 case ARM::t2LDRSBi8: 3511 Inst.setOpcode(ARM::t2PLIi8); 3512 break; 3513 default: 3514 break; 3515 } 3516 } 3517 3518 switch (Inst.getOpcode()) { 3519 case ARM::t2PLDi8: 3520 break; 3521 case ARM::t2PLIi8: 3522 if (!hasV7Ops) 3523 return MCDisassembler::Fail; 3524 break; 3525 case ARM::t2PLDWi8: 3526 if (!hasV7Ops || !hasMP) 3527 return MCDisassembler::Fail; 3528 break; 3529 default: 3530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 } 3533 3534 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3535 return MCDisassembler::Fail; 3536 return S; 3537 } 3538 3539 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3540 uint64_t Address, const void* Decoder) { 3541 DecodeStatus S = MCDisassembler::Success; 3542 3543 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3544 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3545 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3546 imm |= (Rn << 13); 3547 3548 const FeatureBitset &featureBits = 3549 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3550 3551 bool hasMP = featureBits[ARM::FeatureMP]; 3552 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3553 3554 if (Rn == 15) { 3555 switch (Inst.getOpcode()) { 3556 case ARM::t2LDRi12: 3557 Inst.setOpcode(ARM::t2LDRpci); 3558 break; 3559 case ARM::t2LDRHi12: 3560 Inst.setOpcode(ARM::t2LDRHpci); 3561 break; 3562 case ARM::t2LDRSHi12: 3563 Inst.setOpcode(ARM::t2LDRSHpci); 3564 break; 3565 case ARM::t2LDRBi12: 3566 Inst.setOpcode(ARM::t2LDRBpci); 3567 break; 3568 case ARM::t2LDRSBi12: 3569 Inst.setOpcode(ARM::t2LDRSBpci); 3570 break; 3571 case ARM::t2PLDi12: 3572 Inst.setOpcode(ARM::t2PLDpci); 3573 break; 3574 case ARM::t2PLIi12: 3575 Inst.setOpcode(ARM::t2PLIpci); 3576 break; 3577 default: 3578 return MCDisassembler::Fail; 3579 } 3580 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3581 } 3582 3583 if (Rt == 15) { 3584 switch (Inst.getOpcode()) { 3585 case ARM::t2LDRSHi12: 3586 return MCDisassembler::Fail; 3587 case ARM::t2LDRHi12: 3588 Inst.setOpcode(ARM::t2PLDWi12); 3589 break; 3590 case ARM::t2LDRSBi12: 3591 Inst.setOpcode(ARM::t2PLIi12); 3592 break; 3593 default: 3594 break; 3595 } 3596 } 3597 3598 switch (Inst.getOpcode()) { 3599 case ARM::t2PLDi12: 3600 break; 3601 case ARM::t2PLIi12: 3602 if (!hasV7Ops) 3603 return MCDisassembler::Fail; 3604 break; 3605 case ARM::t2PLDWi12: 3606 if (!hasV7Ops || !hasMP) 3607 return MCDisassembler::Fail; 3608 break; 3609 default: 3610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3611 return MCDisassembler::Fail; 3612 } 3613 3614 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3615 return MCDisassembler::Fail; 3616 return S; 3617 } 3618 3619 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3620 uint64_t Address, const void* Decoder) { 3621 DecodeStatus S = MCDisassembler::Success; 3622 3623 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3624 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3625 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3626 imm |= (Rn << 9); 3627 3628 if (Rn == 15) { 3629 switch (Inst.getOpcode()) { 3630 case ARM::t2LDRT: 3631 Inst.setOpcode(ARM::t2LDRpci); 3632 break; 3633 case ARM::t2LDRBT: 3634 Inst.setOpcode(ARM::t2LDRBpci); 3635 break; 3636 case ARM::t2LDRHT: 3637 Inst.setOpcode(ARM::t2LDRHpci); 3638 break; 3639 case ARM::t2LDRSBT: 3640 Inst.setOpcode(ARM::t2LDRSBpci); 3641 break; 3642 case ARM::t2LDRSHT: 3643 Inst.setOpcode(ARM::t2LDRSHpci); 3644 break; 3645 default: 3646 return MCDisassembler::Fail; 3647 } 3648 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3649 } 3650 3651 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3652 return MCDisassembler::Fail; 3653 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3654 return MCDisassembler::Fail; 3655 return S; 3656 } 3657 3658 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3659 uint64_t Address, const void* Decoder) { 3660 DecodeStatus S = MCDisassembler::Success; 3661 3662 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3663 unsigned U = fieldFromInstruction(Insn, 23, 1); 3664 int imm = fieldFromInstruction(Insn, 0, 12); 3665 3666 const FeatureBitset &featureBits = 3667 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3668 3669 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3670 3671 if (Rt == 15) { 3672 switch (Inst.getOpcode()) { 3673 case ARM::t2LDRBpci: 3674 case ARM::t2LDRHpci: 3675 Inst.setOpcode(ARM::t2PLDpci); 3676 break; 3677 case ARM::t2LDRSBpci: 3678 Inst.setOpcode(ARM::t2PLIpci); 3679 break; 3680 case ARM::t2LDRSHpci: 3681 return MCDisassembler::Fail; 3682 default: 3683 break; 3684 } 3685 } 3686 3687 switch(Inst.getOpcode()) { 3688 case ARM::t2PLDpci: 3689 break; 3690 case ARM::t2PLIpci: 3691 if (!hasV7Ops) 3692 return MCDisassembler::Fail; 3693 break; 3694 default: 3695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3696 return MCDisassembler::Fail; 3697 } 3698 3699 if (!U) { 3700 // Special case for #-0. 3701 if (imm == 0) 3702 imm = INT32_MIN; 3703 else 3704 imm = -imm; 3705 } 3706 Inst.addOperand(MCOperand::createImm(imm)); 3707 3708 return S; 3709 } 3710 3711 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3712 uint64_t Address, const void *Decoder) { 3713 if (Val == 0) 3714 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3715 else { 3716 int imm = Val & 0xFF; 3717 3718 if (!(Val & 0x100)) imm *= -1; 3719 Inst.addOperand(MCOperand::createImm(imm * 4)); 3720 } 3721 3722 return MCDisassembler::Success; 3723 } 3724 3725 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3726 uint64_t Address, const void *Decoder) { 3727 DecodeStatus S = MCDisassembler::Success; 3728 3729 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3730 unsigned imm = fieldFromInstruction(Val, 0, 9); 3731 3732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3733 return MCDisassembler::Fail; 3734 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3735 return MCDisassembler::Fail; 3736 3737 return S; 3738 } 3739 3740 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3741 uint64_t Address, const void *Decoder) { 3742 DecodeStatus S = MCDisassembler::Success; 3743 3744 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3745 unsigned imm = fieldFromInstruction(Val, 0, 8); 3746 3747 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3748 return MCDisassembler::Fail; 3749 3750 Inst.addOperand(MCOperand::createImm(imm)); 3751 3752 return S; 3753 } 3754 3755 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3756 uint64_t Address, const void *Decoder) { 3757 int imm = Val & 0xFF; 3758 if (Val == 0) 3759 imm = INT32_MIN; 3760 else if (!(Val & 0x100)) 3761 imm *= -1; 3762 Inst.addOperand(MCOperand::createImm(imm)); 3763 3764 return MCDisassembler::Success; 3765 } 3766 3767 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3768 uint64_t Address, const void *Decoder) { 3769 DecodeStatus S = MCDisassembler::Success; 3770 3771 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3772 unsigned imm = fieldFromInstruction(Val, 0, 9); 3773 3774 // Thumb stores cannot use PC as dest register. 3775 switch (Inst.getOpcode()) { 3776 case ARM::t2STRT: 3777 case ARM::t2STRBT: 3778 case ARM::t2STRHT: 3779 case ARM::t2STRi8: 3780 case ARM::t2STRHi8: 3781 case ARM::t2STRBi8: 3782 if (Rn == 15) 3783 return MCDisassembler::Fail; 3784 break; 3785 default: 3786 break; 3787 } 3788 3789 // Some instructions always use an additive offset. 3790 switch (Inst.getOpcode()) { 3791 case ARM::t2LDRT: 3792 case ARM::t2LDRBT: 3793 case ARM::t2LDRHT: 3794 case ARM::t2LDRSBT: 3795 case ARM::t2LDRSHT: 3796 case ARM::t2STRT: 3797 case ARM::t2STRBT: 3798 case ARM::t2STRHT: 3799 imm |= 0x100; 3800 break; 3801 default: 3802 break; 3803 } 3804 3805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3806 return MCDisassembler::Fail; 3807 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3808 return MCDisassembler::Fail; 3809 3810 return S; 3811 } 3812 3813 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3814 uint64_t Address, const void *Decoder) { 3815 DecodeStatus S = MCDisassembler::Success; 3816 3817 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3818 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3819 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3820 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3821 addr |= Rn << 9; 3822 unsigned load = fieldFromInstruction(Insn, 20, 1); 3823 3824 if (Rn == 15) { 3825 switch (Inst.getOpcode()) { 3826 case ARM::t2LDR_PRE: 3827 case ARM::t2LDR_POST: 3828 Inst.setOpcode(ARM::t2LDRpci); 3829 break; 3830 case ARM::t2LDRB_PRE: 3831 case ARM::t2LDRB_POST: 3832 Inst.setOpcode(ARM::t2LDRBpci); 3833 break; 3834 case ARM::t2LDRH_PRE: 3835 case ARM::t2LDRH_POST: 3836 Inst.setOpcode(ARM::t2LDRHpci); 3837 break; 3838 case ARM::t2LDRSB_PRE: 3839 case ARM::t2LDRSB_POST: 3840 if (Rt == 15) 3841 Inst.setOpcode(ARM::t2PLIpci); 3842 else 3843 Inst.setOpcode(ARM::t2LDRSBpci); 3844 break; 3845 case ARM::t2LDRSH_PRE: 3846 case ARM::t2LDRSH_POST: 3847 Inst.setOpcode(ARM::t2LDRSHpci); 3848 break; 3849 default: 3850 return MCDisassembler::Fail; 3851 } 3852 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3853 } 3854 3855 if (!load) { 3856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3857 return MCDisassembler::Fail; 3858 } 3859 3860 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3861 return MCDisassembler::Fail; 3862 3863 if (load) { 3864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3865 return MCDisassembler::Fail; 3866 } 3867 3868 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3869 return MCDisassembler::Fail; 3870 3871 return S; 3872 } 3873 3874 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3875 uint64_t Address, const void *Decoder) { 3876 DecodeStatus S = MCDisassembler::Success; 3877 3878 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3879 unsigned imm = fieldFromInstruction(Val, 0, 12); 3880 3881 // Thumb stores cannot use PC as dest register. 3882 switch (Inst.getOpcode()) { 3883 case ARM::t2STRi12: 3884 case ARM::t2STRBi12: 3885 case ARM::t2STRHi12: 3886 if (Rn == 15) 3887 return MCDisassembler::Fail; 3888 break; 3889 default: 3890 break; 3891 } 3892 3893 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3894 return MCDisassembler::Fail; 3895 Inst.addOperand(MCOperand::createImm(imm)); 3896 3897 return S; 3898 } 3899 3900 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3901 uint64_t Address, const void *Decoder) { 3902 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3903 3904 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3905 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3906 Inst.addOperand(MCOperand::createImm(imm)); 3907 3908 return MCDisassembler::Success; 3909 } 3910 3911 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3912 uint64_t Address, const void *Decoder) { 3913 DecodeStatus S = MCDisassembler::Success; 3914 3915 if (Inst.getOpcode() == ARM::tADDrSP) { 3916 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3917 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3918 3919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3920 return MCDisassembler::Fail; 3921 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3923 return MCDisassembler::Fail; 3924 } else if (Inst.getOpcode() == ARM::tADDspr) { 3925 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3926 3927 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3928 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3930 return MCDisassembler::Fail; 3931 } 3932 3933 return S; 3934 } 3935 3936 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3937 uint64_t Address, const void *Decoder) { 3938 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3939 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3940 3941 Inst.addOperand(MCOperand::createImm(imod)); 3942 Inst.addOperand(MCOperand::createImm(flags)); 3943 3944 return MCDisassembler::Success; 3945 } 3946 3947 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3948 uint64_t Address, const void *Decoder) { 3949 DecodeStatus S = MCDisassembler::Success; 3950 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3951 unsigned add = fieldFromInstruction(Insn, 4, 1); 3952 3953 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3954 return MCDisassembler::Fail; 3955 Inst.addOperand(MCOperand::createImm(add)); 3956 3957 return S; 3958 } 3959 3960 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3961 uint64_t Address, const void *Decoder) { 3962 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3963 // Note only one trailing zero not two. Also the J1 and J2 values are from 3964 // the encoded instruction. So here change to I1 and I2 values via: 3965 // I1 = NOT(J1 EOR S); 3966 // I2 = NOT(J2 EOR S); 3967 // and build the imm32 with two trailing zeros as documented: 3968 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3969 unsigned S = (Val >> 23) & 1; 3970 unsigned J1 = (Val >> 22) & 1; 3971 unsigned J2 = (Val >> 21) & 1; 3972 unsigned I1 = !(J1 ^ S); 3973 unsigned I2 = !(J2 ^ S); 3974 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3975 int imm32 = SignExtend32<25>(tmp << 1); 3976 3977 if (!tryAddingSymbolicOperand(Address, 3978 (Address & ~2u) + imm32 + 4, 3979 true, 4, Inst, Decoder)) 3980 Inst.addOperand(MCOperand::createImm(imm32)); 3981 return MCDisassembler::Success; 3982 } 3983 3984 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3985 uint64_t Address, const void *Decoder) { 3986 if (Val == 0xA || Val == 0xB) 3987 return MCDisassembler::Fail; 3988 3989 const FeatureBitset &featureBits = 3990 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3991 3992 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 3993 return MCDisassembler::Fail; 3994 3995 Inst.addOperand(MCOperand::createImm(Val)); 3996 return MCDisassembler::Success; 3997 } 3998 3999 static DecodeStatus 4000 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4001 uint64_t Address, const void *Decoder) { 4002 DecodeStatus S = MCDisassembler::Success; 4003 4004 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4005 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4006 4007 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4009 return MCDisassembler::Fail; 4010 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4011 return MCDisassembler::Fail; 4012 return S; 4013 } 4014 4015 static DecodeStatus 4016 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4017 uint64_t Address, const void *Decoder) { 4018 DecodeStatus S = MCDisassembler::Success; 4019 4020 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4021 if (pred == 0xE || pred == 0xF) { 4022 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4023 switch (opc) { 4024 default: 4025 return MCDisassembler::Fail; 4026 case 0xf3bf8f4: 4027 Inst.setOpcode(ARM::t2DSB); 4028 break; 4029 case 0xf3bf8f5: 4030 Inst.setOpcode(ARM::t2DMB); 4031 break; 4032 case 0xf3bf8f6: 4033 Inst.setOpcode(ARM::t2ISB); 4034 break; 4035 } 4036 4037 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4038 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4039 } 4040 4041 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4042 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4043 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4044 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4045 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4046 4047 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4048 return MCDisassembler::Fail; 4049 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4050 return MCDisassembler::Fail; 4051 4052 return S; 4053 } 4054 4055 // Decode a shifted immediate operand. These basically consist 4056 // of an 8-bit value, and a 4-bit directive that specifies either 4057 // a splat operation or a rotation. 4058 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4059 uint64_t Address, const void *Decoder) { 4060 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4061 if (ctrl == 0) { 4062 unsigned byte = fieldFromInstruction(Val, 8, 2); 4063 unsigned imm = fieldFromInstruction(Val, 0, 8); 4064 switch (byte) { 4065 case 0: 4066 Inst.addOperand(MCOperand::createImm(imm)); 4067 break; 4068 case 1: 4069 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4070 break; 4071 case 2: 4072 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4073 break; 4074 case 3: 4075 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4076 (imm << 8) | imm)); 4077 break; 4078 } 4079 } else { 4080 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4081 unsigned rot = fieldFromInstruction(Val, 7, 5); 4082 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4083 Inst.addOperand(MCOperand::createImm(imm)); 4084 } 4085 4086 return MCDisassembler::Success; 4087 } 4088 4089 static DecodeStatus 4090 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4091 uint64_t Address, const void *Decoder) { 4092 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4093 true, 2, Inst, Decoder)) 4094 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4095 return MCDisassembler::Success; 4096 } 4097 4098 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4099 uint64_t Address, 4100 const void *Decoder) { 4101 // Val is passed in as S:J1:J2:imm10:imm11 4102 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4103 // the encoded instruction. So here change to I1 and I2 values via: 4104 // I1 = NOT(J1 EOR S); 4105 // I2 = NOT(J2 EOR S); 4106 // and build the imm32 with one trailing zero as documented: 4107 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4108 unsigned S = (Val >> 23) & 1; 4109 unsigned J1 = (Val >> 22) & 1; 4110 unsigned J2 = (Val >> 21) & 1; 4111 unsigned I1 = !(J1 ^ S); 4112 unsigned I2 = !(J2 ^ S); 4113 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4114 int imm32 = SignExtend32<25>(tmp << 1); 4115 4116 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4117 true, 4, Inst, Decoder)) 4118 Inst.addOperand(MCOperand::createImm(imm32)); 4119 return MCDisassembler::Success; 4120 } 4121 4122 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4123 uint64_t Address, const void *Decoder) { 4124 if (Val & ~0xf) 4125 return MCDisassembler::Fail; 4126 4127 Inst.addOperand(MCOperand::createImm(Val)); 4128 return MCDisassembler::Success; 4129 } 4130 4131 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4132 uint64_t Address, const void *Decoder) { 4133 if (Val & ~0xf) 4134 return MCDisassembler::Fail; 4135 4136 Inst.addOperand(MCOperand::createImm(Val)); 4137 return MCDisassembler::Success; 4138 } 4139 4140 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4141 uint64_t Address, const void *Decoder) { 4142 DecodeStatus S = MCDisassembler::Success; 4143 const FeatureBitset &FeatureBits = 4144 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4145 4146 if (FeatureBits[ARM::FeatureMClass]) { 4147 unsigned ValLow = Val & 0xff; 4148 4149 // Validate the SYSm value first. 4150 switch (ValLow) { 4151 case 0: // apsr 4152 case 1: // iapsr 4153 case 2: // eapsr 4154 case 3: // xpsr 4155 case 5: // ipsr 4156 case 6: // epsr 4157 case 7: // iepsr 4158 case 8: // msp 4159 case 9: // psp 4160 case 16: // primask 4161 case 20: // control 4162 break; 4163 case 17: // basepri 4164 case 18: // basepri_max 4165 case 19: // faultmask 4166 if (!(FeatureBits[ARM::HasV7Ops])) 4167 // Values basepri, basepri_max and faultmask are only valid for v7m. 4168 return MCDisassembler::Fail; 4169 break; 4170 case 0x8a: // msplim_ns 4171 case 0x8b: // psplim_ns 4172 case 0x91: // basepri_ns 4173 case 0x93: // faultmask_ns 4174 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4175 return MCDisassembler::Fail; 4176 LLVM_FALLTHROUGH; 4177 case 10: // msplim 4178 case 11: // psplim 4179 case 0x88: // msp_ns 4180 case 0x89: // psp_ns 4181 case 0x90: // primask_ns 4182 case 0x94: // control_ns 4183 case 0x98: // sp_ns 4184 if (!(FeatureBits[ARM::Feature8MSecExt])) 4185 return MCDisassembler::Fail; 4186 break; 4187 default: 4188 // Architecturally defined as unpredictable 4189 S = MCDisassembler::SoftFail; 4190 break; 4191 } 4192 4193 if (Inst.getOpcode() == ARM::t2MSR_M) { 4194 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4195 if (!(FeatureBits[ARM::HasV7Ops])) { 4196 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4197 // unpredictable. 4198 if (Mask != 2) 4199 S = MCDisassembler::SoftFail; 4200 } 4201 else { 4202 // The ARMv7-M architecture stores an additional 2-bit mask value in 4203 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4204 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4205 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4206 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4207 // only if the processor includes the DSP extension. 4208 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4209 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4210 S = MCDisassembler::SoftFail; 4211 } 4212 } 4213 } else { 4214 // A/R class 4215 if (Val == 0) 4216 return MCDisassembler::Fail; 4217 } 4218 Inst.addOperand(MCOperand::createImm(Val)); 4219 return S; 4220 } 4221 4222 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4223 uint64_t Address, const void *Decoder) { 4224 unsigned R = fieldFromInstruction(Val, 5, 1); 4225 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4226 4227 // The table of encodings for these banked registers comes from B9.2.3 of the 4228 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4229 // neater. So by fiat, these values are UNPREDICTABLE: 4230 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4231 return MCDisassembler::Fail; 4232 4233 Inst.addOperand(MCOperand::createImm(Val)); 4234 return MCDisassembler::Success; 4235 } 4236 4237 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4238 uint64_t Address, const void *Decoder) { 4239 DecodeStatus S = MCDisassembler::Success; 4240 4241 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4242 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4243 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4244 4245 if (Rn == 0xF) 4246 S = MCDisassembler::SoftFail; 4247 4248 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4249 return MCDisassembler::Fail; 4250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4251 return MCDisassembler::Fail; 4252 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4253 return MCDisassembler::Fail; 4254 4255 return S; 4256 } 4257 4258 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4259 uint64_t Address, 4260 const void *Decoder) { 4261 DecodeStatus S = MCDisassembler::Success; 4262 4263 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4264 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4265 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4266 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4267 4268 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4269 return MCDisassembler::Fail; 4270 4271 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4272 S = MCDisassembler::SoftFail; 4273 4274 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4275 return MCDisassembler::Fail; 4276 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4277 return MCDisassembler::Fail; 4278 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4279 return MCDisassembler::Fail; 4280 4281 return S; 4282 } 4283 4284 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4285 uint64_t Address, const void *Decoder) { 4286 DecodeStatus S = MCDisassembler::Success; 4287 4288 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4289 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4290 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4291 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4292 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4293 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4294 4295 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4296 4297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4298 return MCDisassembler::Fail; 4299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4302 return MCDisassembler::Fail; 4303 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 4306 return S; 4307 } 4308 4309 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4310 uint64_t Address, const void *Decoder) { 4311 DecodeStatus S = MCDisassembler::Success; 4312 4313 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4314 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4315 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4316 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4317 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4318 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4319 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4320 4321 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4322 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4323 4324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4325 return MCDisassembler::Fail; 4326 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4327 return MCDisassembler::Fail; 4328 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4329 return MCDisassembler::Fail; 4330 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4331 return MCDisassembler::Fail; 4332 4333 return S; 4334 } 4335 4336 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4337 uint64_t Address, const void *Decoder) { 4338 DecodeStatus S = MCDisassembler::Success; 4339 4340 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4341 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4342 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4343 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4344 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4345 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4346 4347 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4348 4349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4350 return MCDisassembler::Fail; 4351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4352 return MCDisassembler::Fail; 4353 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4354 return MCDisassembler::Fail; 4355 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4356 return MCDisassembler::Fail; 4357 4358 return S; 4359 } 4360 4361 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4362 uint64_t Address, const void *Decoder) { 4363 DecodeStatus S = MCDisassembler::Success; 4364 4365 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4366 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4367 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4368 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4369 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4370 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4371 4372 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4373 4374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4375 return MCDisassembler::Fail; 4376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4377 return MCDisassembler::Fail; 4378 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4379 return MCDisassembler::Fail; 4380 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4381 return MCDisassembler::Fail; 4382 4383 return S; 4384 } 4385 4386 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4387 uint64_t Address, const void *Decoder) { 4388 DecodeStatus S = MCDisassembler::Success; 4389 4390 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4391 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4392 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4393 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4394 unsigned size = fieldFromInstruction(Insn, 10, 2); 4395 4396 unsigned align = 0; 4397 unsigned index = 0; 4398 switch (size) { 4399 default: 4400 return MCDisassembler::Fail; 4401 case 0: 4402 if (fieldFromInstruction(Insn, 4, 1)) 4403 return MCDisassembler::Fail; // UNDEFINED 4404 index = fieldFromInstruction(Insn, 5, 3); 4405 break; 4406 case 1: 4407 if (fieldFromInstruction(Insn, 5, 1)) 4408 return MCDisassembler::Fail; // UNDEFINED 4409 index = fieldFromInstruction(Insn, 6, 2); 4410 if (fieldFromInstruction(Insn, 4, 1)) 4411 align = 2; 4412 break; 4413 case 2: 4414 if (fieldFromInstruction(Insn, 6, 1)) 4415 return MCDisassembler::Fail; // UNDEFINED 4416 index = fieldFromInstruction(Insn, 7, 1); 4417 4418 switch (fieldFromInstruction(Insn, 4, 2)) { 4419 case 0 : 4420 align = 0; break; 4421 case 3: 4422 align = 4; break; 4423 default: 4424 return MCDisassembler::Fail; 4425 } 4426 break; 4427 } 4428 4429 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4430 return MCDisassembler::Fail; 4431 if (Rm != 0xF) { // Writeback 4432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4433 return MCDisassembler::Fail; 4434 } 4435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4436 return MCDisassembler::Fail; 4437 Inst.addOperand(MCOperand::createImm(align)); 4438 if (Rm != 0xF) { 4439 if (Rm != 0xD) { 4440 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4441 return MCDisassembler::Fail; 4442 } else 4443 Inst.addOperand(MCOperand::createReg(0)); 4444 } 4445 4446 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4447 return MCDisassembler::Fail; 4448 Inst.addOperand(MCOperand::createImm(index)); 4449 4450 return S; 4451 } 4452 4453 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4454 uint64_t Address, const void *Decoder) { 4455 DecodeStatus S = MCDisassembler::Success; 4456 4457 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4458 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4459 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4460 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4461 unsigned size = fieldFromInstruction(Insn, 10, 2); 4462 4463 unsigned align = 0; 4464 unsigned index = 0; 4465 switch (size) { 4466 default: 4467 return MCDisassembler::Fail; 4468 case 0: 4469 if (fieldFromInstruction(Insn, 4, 1)) 4470 return MCDisassembler::Fail; // UNDEFINED 4471 index = fieldFromInstruction(Insn, 5, 3); 4472 break; 4473 case 1: 4474 if (fieldFromInstruction(Insn, 5, 1)) 4475 return MCDisassembler::Fail; // UNDEFINED 4476 index = fieldFromInstruction(Insn, 6, 2); 4477 if (fieldFromInstruction(Insn, 4, 1)) 4478 align = 2; 4479 break; 4480 case 2: 4481 if (fieldFromInstruction(Insn, 6, 1)) 4482 return MCDisassembler::Fail; // UNDEFINED 4483 index = fieldFromInstruction(Insn, 7, 1); 4484 4485 switch (fieldFromInstruction(Insn, 4, 2)) { 4486 case 0: 4487 align = 0; break; 4488 case 3: 4489 align = 4; break; 4490 default: 4491 return MCDisassembler::Fail; 4492 } 4493 break; 4494 } 4495 4496 if (Rm != 0xF) { // Writeback 4497 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4498 return MCDisassembler::Fail; 4499 } 4500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4501 return MCDisassembler::Fail; 4502 Inst.addOperand(MCOperand::createImm(align)); 4503 if (Rm != 0xF) { 4504 if (Rm != 0xD) { 4505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4506 return MCDisassembler::Fail; 4507 } else 4508 Inst.addOperand(MCOperand::createReg(0)); 4509 } 4510 4511 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4512 return MCDisassembler::Fail; 4513 Inst.addOperand(MCOperand::createImm(index)); 4514 4515 return S; 4516 } 4517 4518 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4519 uint64_t Address, const void *Decoder) { 4520 DecodeStatus S = MCDisassembler::Success; 4521 4522 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4523 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4524 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4525 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4526 unsigned size = fieldFromInstruction(Insn, 10, 2); 4527 4528 unsigned align = 0; 4529 unsigned index = 0; 4530 unsigned inc = 1; 4531 switch (size) { 4532 default: 4533 return MCDisassembler::Fail; 4534 case 0: 4535 index = fieldFromInstruction(Insn, 5, 3); 4536 if (fieldFromInstruction(Insn, 4, 1)) 4537 align = 2; 4538 break; 4539 case 1: 4540 index = fieldFromInstruction(Insn, 6, 2); 4541 if (fieldFromInstruction(Insn, 4, 1)) 4542 align = 4; 4543 if (fieldFromInstruction(Insn, 5, 1)) 4544 inc = 2; 4545 break; 4546 case 2: 4547 if (fieldFromInstruction(Insn, 5, 1)) 4548 return MCDisassembler::Fail; // UNDEFINED 4549 index = fieldFromInstruction(Insn, 7, 1); 4550 if (fieldFromInstruction(Insn, 4, 1) != 0) 4551 align = 8; 4552 if (fieldFromInstruction(Insn, 6, 1)) 4553 inc = 2; 4554 break; 4555 } 4556 4557 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4558 return MCDisassembler::Fail; 4559 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4560 return MCDisassembler::Fail; 4561 if (Rm != 0xF) { // Writeback 4562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4563 return MCDisassembler::Fail; 4564 } 4565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4566 return MCDisassembler::Fail; 4567 Inst.addOperand(MCOperand::createImm(align)); 4568 if (Rm != 0xF) { 4569 if (Rm != 0xD) { 4570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4571 return MCDisassembler::Fail; 4572 } else 4573 Inst.addOperand(MCOperand::createReg(0)); 4574 } 4575 4576 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4577 return MCDisassembler::Fail; 4578 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4579 return MCDisassembler::Fail; 4580 Inst.addOperand(MCOperand::createImm(index)); 4581 4582 return S; 4583 } 4584 4585 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4586 uint64_t Address, const void *Decoder) { 4587 DecodeStatus S = MCDisassembler::Success; 4588 4589 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4590 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4591 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4592 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4593 unsigned size = fieldFromInstruction(Insn, 10, 2); 4594 4595 unsigned align = 0; 4596 unsigned index = 0; 4597 unsigned inc = 1; 4598 switch (size) { 4599 default: 4600 return MCDisassembler::Fail; 4601 case 0: 4602 index = fieldFromInstruction(Insn, 5, 3); 4603 if (fieldFromInstruction(Insn, 4, 1)) 4604 align = 2; 4605 break; 4606 case 1: 4607 index = fieldFromInstruction(Insn, 6, 2); 4608 if (fieldFromInstruction(Insn, 4, 1)) 4609 align = 4; 4610 if (fieldFromInstruction(Insn, 5, 1)) 4611 inc = 2; 4612 break; 4613 case 2: 4614 if (fieldFromInstruction(Insn, 5, 1)) 4615 return MCDisassembler::Fail; // UNDEFINED 4616 index = fieldFromInstruction(Insn, 7, 1); 4617 if (fieldFromInstruction(Insn, 4, 1) != 0) 4618 align = 8; 4619 if (fieldFromInstruction(Insn, 6, 1)) 4620 inc = 2; 4621 break; 4622 } 4623 4624 if (Rm != 0xF) { // Writeback 4625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4626 return MCDisassembler::Fail; 4627 } 4628 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4629 return MCDisassembler::Fail; 4630 Inst.addOperand(MCOperand::createImm(align)); 4631 if (Rm != 0xF) { 4632 if (Rm != 0xD) { 4633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4634 return MCDisassembler::Fail; 4635 } else 4636 Inst.addOperand(MCOperand::createReg(0)); 4637 } 4638 4639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4640 return MCDisassembler::Fail; 4641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4642 return MCDisassembler::Fail; 4643 Inst.addOperand(MCOperand::createImm(index)); 4644 4645 return S; 4646 } 4647 4648 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4649 uint64_t Address, const void *Decoder) { 4650 DecodeStatus S = MCDisassembler::Success; 4651 4652 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4653 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4654 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4655 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4656 unsigned size = fieldFromInstruction(Insn, 10, 2); 4657 4658 unsigned align = 0; 4659 unsigned index = 0; 4660 unsigned inc = 1; 4661 switch (size) { 4662 default: 4663 return MCDisassembler::Fail; 4664 case 0: 4665 if (fieldFromInstruction(Insn, 4, 1)) 4666 return MCDisassembler::Fail; // UNDEFINED 4667 index = fieldFromInstruction(Insn, 5, 3); 4668 break; 4669 case 1: 4670 if (fieldFromInstruction(Insn, 4, 1)) 4671 return MCDisassembler::Fail; // UNDEFINED 4672 index = fieldFromInstruction(Insn, 6, 2); 4673 if (fieldFromInstruction(Insn, 5, 1)) 4674 inc = 2; 4675 break; 4676 case 2: 4677 if (fieldFromInstruction(Insn, 4, 2)) 4678 return MCDisassembler::Fail; // UNDEFINED 4679 index = fieldFromInstruction(Insn, 7, 1); 4680 if (fieldFromInstruction(Insn, 6, 1)) 4681 inc = 2; 4682 break; 4683 } 4684 4685 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4686 return MCDisassembler::Fail; 4687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4688 return MCDisassembler::Fail; 4689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4690 return MCDisassembler::Fail; 4691 4692 if (Rm != 0xF) { // Writeback 4693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4694 return MCDisassembler::Fail; 4695 } 4696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4697 return MCDisassembler::Fail; 4698 Inst.addOperand(MCOperand::createImm(align)); 4699 if (Rm != 0xF) { 4700 if (Rm != 0xD) { 4701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4702 return MCDisassembler::Fail; 4703 } else 4704 Inst.addOperand(MCOperand::createReg(0)); 4705 } 4706 4707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4708 return MCDisassembler::Fail; 4709 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4710 return MCDisassembler::Fail; 4711 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4712 return MCDisassembler::Fail; 4713 Inst.addOperand(MCOperand::createImm(index)); 4714 4715 return S; 4716 } 4717 4718 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4719 uint64_t Address, const void *Decoder) { 4720 DecodeStatus S = MCDisassembler::Success; 4721 4722 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4723 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4724 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4725 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4726 unsigned size = fieldFromInstruction(Insn, 10, 2); 4727 4728 unsigned align = 0; 4729 unsigned index = 0; 4730 unsigned inc = 1; 4731 switch (size) { 4732 default: 4733 return MCDisassembler::Fail; 4734 case 0: 4735 if (fieldFromInstruction(Insn, 4, 1)) 4736 return MCDisassembler::Fail; // UNDEFINED 4737 index = fieldFromInstruction(Insn, 5, 3); 4738 break; 4739 case 1: 4740 if (fieldFromInstruction(Insn, 4, 1)) 4741 return MCDisassembler::Fail; // UNDEFINED 4742 index = fieldFromInstruction(Insn, 6, 2); 4743 if (fieldFromInstruction(Insn, 5, 1)) 4744 inc = 2; 4745 break; 4746 case 2: 4747 if (fieldFromInstruction(Insn, 4, 2)) 4748 return MCDisassembler::Fail; // UNDEFINED 4749 index = fieldFromInstruction(Insn, 7, 1); 4750 if (fieldFromInstruction(Insn, 6, 1)) 4751 inc = 2; 4752 break; 4753 } 4754 4755 if (Rm != 0xF) { // Writeback 4756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4757 return MCDisassembler::Fail; 4758 } 4759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4760 return MCDisassembler::Fail; 4761 Inst.addOperand(MCOperand::createImm(align)); 4762 if (Rm != 0xF) { 4763 if (Rm != 0xD) { 4764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4765 return MCDisassembler::Fail; 4766 } else 4767 Inst.addOperand(MCOperand::createReg(0)); 4768 } 4769 4770 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4771 return MCDisassembler::Fail; 4772 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4773 return MCDisassembler::Fail; 4774 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4775 return MCDisassembler::Fail; 4776 Inst.addOperand(MCOperand::createImm(index)); 4777 4778 return S; 4779 } 4780 4781 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4782 uint64_t Address, const void *Decoder) { 4783 DecodeStatus S = MCDisassembler::Success; 4784 4785 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4786 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4787 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4788 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4789 unsigned size = fieldFromInstruction(Insn, 10, 2); 4790 4791 unsigned align = 0; 4792 unsigned index = 0; 4793 unsigned inc = 1; 4794 switch (size) { 4795 default: 4796 return MCDisassembler::Fail; 4797 case 0: 4798 if (fieldFromInstruction(Insn, 4, 1)) 4799 align = 4; 4800 index = fieldFromInstruction(Insn, 5, 3); 4801 break; 4802 case 1: 4803 if (fieldFromInstruction(Insn, 4, 1)) 4804 align = 8; 4805 index = fieldFromInstruction(Insn, 6, 2); 4806 if (fieldFromInstruction(Insn, 5, 1)) 4807 inc = 2; 4808 break; 4809 case 2: 4810 switch (fieldFromInstruction(Insn, 4, 2)) { 4811 case 0: 4812 align = 0; break; 4813 case 3: 4814 return MCDisassembler::Fail; 4815 default: 4816 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4817 } 4818 4819 index = fieldFromInstruction(Insn, 7, 1); 4820 if (fieldFromInstruction(Insn, 6, 1)) 4821 inc = 2; 4822 break; 4823 } 4824 4825 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4826 return MCDisassembler::Fail; 4827 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4828 return MCDisassembler::Fail; 4829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4830 return MCDisassembler::Fail; 4831 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4832 return MCDisassembler::Fail; 4833 4834 if (Rm != 0xF) { // Writeback 4835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4836 return MCDisassembler::Fail; 4837 } 4838 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4839 return MCDisassembler::Fail; 4840 Inst.addOperand(MCOperand::createImm(align)); 4841 if (Rm != 0xF) { 4842 if (Rm != 0xD) { 4843 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4844 return MCDisassembler::Fail; 4845 } else 4846 Inst.addOperand(MCOperand::createReg(0)); 4847 } 4848 4849 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4850 return MCDisassembler::Fail; 4851 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4852 return MCDisassembler::Fail; 4853 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4854 return MCDisassembler::Fail; 4855 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4856 return MCDisassembler::Fail; 4857 Inst.addOperand(MCOperand::createImm(index)); 4858 4859 return S; 4860 } 4861 4862 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4863 uint64_t Address, const void *Decoder) { 4864 DecodeStatus S = MCDisassembler::Success; 4865 4866 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4867 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4868 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4869 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4870 unsigned size = fieldFromInstruction(Insn, 10, 2); 4871 4872 unsigned align = 0; 4873 unsigned index = 0; 4874 unsigned inc = 1; 4875 switch (size) { 4876 default: 4877 return MCDisassembler::Fail; 4878 case 0: 4879 if (fieldFromInstruction(Insn, 4, 1)) 4880 align = 4; 4881 index = fieldFromInstruction(Insn, 5, 3); 4882 break; 4883 case 1: 4884 if (fieldFromInstruction(Insn, 4, 1)) 4885 align = 8; 4886 index = fieldFromInstruction(Insn, 6, 2); 4887 if (fieldFromInstruction(Insn, 5, 1)) 4888 inc = 2; 4889 break; 4890 case 2: 4891 switch (fieldFromInstruction(Insn, 4, 2)) { 4892 case 0: 4893 align = 0; break; 4894 case 3: 4895 return MCDisassembler::Fail; 4896 default: 4897 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4898 } 4899 4900 index = fieldFromInstruction(Insn, 7, 1); 4901 if (fieldFromInstruction(Insn, 6, 1)) 4902 inc = 2; 4903 break; 4904 } 4905 4906 if (Rm != 0xF) { // Writeback 4907 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4908 return MCDisassembler::Fail; 4909 } 4910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4911 return MCDisassembler::Fail; 4912 Inst.addOperand(MCOperand::createImm(align)); 4913 if (Rm != 0xF) { 4914 if (Rm != 0xD) { 4915 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4916 return MCDisassembler::Fail; 4917 } else 4918 Inst.addOperand(MCOperand::createReg(0)); 4919 } 4920 4921 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4922 return MCDisassembler::Fail; 4923 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4924 return MCDisassembler::Fail; 4925 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4926 return MCDisassembler::Fail; 4927 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4928 return MCDisassembler::Fail; 4929 Inst.addOperand(MCOperand::createImm(index)); 4930 4931 return S; 4932 } 4933 4934 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4935 uint64_t Address, const void *Decoder) { 4936 DecodeStatus S = MCDisassembler::Success; 4937 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4938 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4939 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4940 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4941 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4942 4943 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4944 S = MCDisassembler::SoftFail; 4945 4946 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4947 return MCDisassembler::Fail; 4948 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4949 return MCDisassembler::Fail; 4950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4951 return MCDisassembler::Fail; 4952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4953 return MCDisassembler::Fail; 4954 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4955 return MCDisassembler::Fail; 4956 4957 return S; 4958 } 4959 4960 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4961 uint64_t Address, const void *Decoder) { 4962 DecodeStatus S = MCDisassembler::Success; 4963 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4964 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4965 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4966 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4967 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4968 4969 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4970 S = MCDisassembler::SoftFail; 4971 4972 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4973 return MCDisassembler::Fail; 4974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4975 return MCDisassembler::Fail; 4976 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4977 return MCDisassembler::Fail; 4978 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4979 return MCDisassembler::Fail; 4980 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4981 return MCDisassembler::Fail; 4982 4983 return S; 4984 } 4985 4986 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4987 uint64_t Address, const void *Decoder) { 4988 DecodeStatus S = MCDisassembler::Success; 4989 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4990 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4991 4992 if (pred == 0xF) { 4993 pred = 0xE; 4994 S = MCDisassembler::SoftFail; 4995 } 4996 4997 if (mask == 0x0) 4998 return MCDisassembler::Fail; 4999 5000 Inst.addOperand(MCOperand::createImm(pred)); 5001 Inst.addOperand(MCOperand::createImm(mask)); 5002 return S; 5003 } 5004 5005 static DecodeStatus 5006 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5007 uint64_t Address, const void *Decoder) { 5008 DecodeStatus S = MCDisassembler::Success; 5009 5010 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5011 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5012 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5013 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5014 unsigned W = fieldFromInstruction(Insn, 21, 1); 5015 unsigned U = fieldFromInstruction(Insn, 23, 1); 5016 unsigned P = fieldFromInstruction(Insn, 24, 1); 5017 bool writeback = (W == 1) | (P == 0); 5018 5019 addr |= (U << 8) | (Rn << 9); 5020 5021 if (writeback && (Rn == Rt || Rn == Rt2)) 5022 Check(S, MCDisassembler::SoftFail); 5023 if (Rt == Rt2) 5024 Check(S, MCDisassembler::SoftFail); 5025 5026 // Rt 5027 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5028 return MCDisassembler::Fail; 5029 // Rt2 5030 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5031 return MCDisassembler::Fail; 5032 // Writeback operand 5033 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5034 return MCDisassembler::Fail; 5035 // addr 5036 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5037 return MCDisassembler::Fail; 5038 5039 return S; 5040 } 5041 5042 static DecodeStatus 5043 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5044 uint64_t Address, const void *Decoder) { 5045 DecodeStatus S = MCDisassembler::Success; 5046 5047 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5048 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5049 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5050 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5051 unsigned W = fieldFromInstruction(Insn, 21, 1); 5052 unsigned U = fieldFromInstruction(Insn, 23, 1); 5053 unsigned P = fieldFromInstruction(Insn, 24, 1); 5054 bool writeback = (W == 1) | (P == 0); 5055 5056 addr |= (U << 8) | (Rn << 9); 5057 5058 if (writeback && (Rn == Rt || Rn == Rt2)) 5059 Check(S, MCDisassembler::SoftFail); 5060 5061 // Writeback operand 5062 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5063 return MCDisassembler::Fail; 5064 // Rt 5065 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5066 return MCDisassembler::Fail; 5067 // Rt2 5068 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5069 return MCDisassembler::Fail; 5070 // addr 5071 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5072 return MCDisassembler::Fail; 5073 5074 return S; 5075 } 5076 5077 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5078 uint64_t Address, const void *Decoder) { 5079 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5080 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5081 if (sign1 != sign2) return MCDisassembler::Fail; 5082 5083 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5084 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5085 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5086 Val |= sign1 << 12; 5087 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5088 5089 return MCDisassembler::Success; 5090 } 5091 5092 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5093 uint64_t Address, 5094 const void *Decoder) { 5095 DecodeStatus S = MCDisassembler::Success; 5096 5097 // Shift of "asr #32" is not allowed in Thumb2 mode. 5098 if (Val == 0x20) S = MCDisassembler::Fail; 5099 Inst.addOperand(MCOperand::createImm(Val)); 5100 return S; 5101 } 5102 5103 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5104 uint64_t Address, const void *Decoder) { 5105 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5106 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5107 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5108 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5109 5110 if (pred == 0xF) 5111 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5112 5113 DecodeStatus S = MCDisassembler::Success; 5114 5115 if (Rt == Rn || Rn == Rt2) 5116 S = MCDisassembler::SoftFail; 5117 5118 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5119 return MCDisassembler::Fail; 5120 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5121 return MCDisassembler::Fail; 5122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5123 return MCDisassembler::Fail; 5124 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5125 return MCDisassembler::Fail; 5126 5127 return S; 5128 } 5129 5130 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5131 uint64_t Address, const void *Decoder) { 5132 const FeatureBitset &featureBits = 5133 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5134 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5135 5136 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5137 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5138 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5139 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5140 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5141 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5142 unsigned op = fieldFromInstruction(Insn, 5, 1); 5143 5144 DecodeStatus S = MCDisassembler::Success; 5145 5146 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5147 if (!(imm & 0x38)) { 5148 if (cmode == 0xF) { 5149 if (op == 1) return MCDisassembler::Fail; 5150 Inst.setOpcode(ARM::VMOVv2f32); 5151 } 5152 if (hasFullFP16) { 5153 if (cmode == 0xE) { 5154 if (op == 1) { 5155 Inst.setOpcode(ARM::VMOVv1i64); 5156 } else { 5157 Inst.setOpcode(ARM::VMOVv8i8); 5158 } 5159 } 5160 if (cmode == 0xD) { 5161 if (op == 1) { 5162 Inst.setOpcode(ARM::VMVNv2i32); 5163 } else { 5164 Inst.setOpcode(ARM::VMOVv2i32); 5165 } 5166 } 5167 if (cmode == 0xC) { 5168 if (op == 1) { 5169 Inst.setOpcode(ARM::VMVNv2i32); 5170 } else { 5171 Inst.setOpcode(ARM::VMOVv2i32); 5172 } 5173 } 5174 } 5175 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5176 } 5177 5178 if (!(imm & 0x20)) return MCDisassembler::Fail; 5179 5180 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5181 return MCDisassembler::Fail; 5182 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5183 return MCDisassembler::Fail; 5184 Inst.addOperand(MCOperand::createImm(64 - imm)); 5185 5186 return S; 5187 } 5188 5189 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5190 uint64_t Address, const void *Decoder) { 5191 const FeatureBitset &featureBits = 5192 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5193 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5194 5195 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5196 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5197 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5198 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5199 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5200 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5201 unsigned op = fieldFromInstruction(Insn, 5, 1); 5202 5203 DecodeStatus S = MCDisassembler::Success; 5204 5205 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5206 if (!(imm & 0x38)) { 5207 if (cmode == 0xF) { 5208 if (op == 1) return MCDisassembler::Fail; 5209 Inst.setOpcode(ARM::VMOVv4f32); 5210 } 5211 if (hasFullFP16) { 5212 if (cmode == 0xE) { 5213 if (op == 1) { 5214 Inst.setOpcode(ARM::VMOVv2i64); 5215 } else { 5216 Inst.setOpcode(ARM::VMOVv16i8); 5217 } 5218 } 5219 if (cmode == 0xD) { 5220 if (op == 1) { 5221 Inst.setOpcode(ARM::VMVNv4i32); 5222 } else { 5223 Inst.setOpcode(ARM::VMOVv4i32); 5224 } 5225 } 5226 if (cmode == 0xC) { 5227 if (op == 1) { 5228 Inst.setOpcode(ARM::VMVNv4i32); 5229 } else { 5230 Inst.setOpcode(ARM::VMOVv4i32); 5231 } 5232 } 5233 } 5234 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5235 } 5236 5237 if (!(imm & 0x20)) return MCDisassembler::Fail; 5238 5239 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5240 return MCDisassembler::Fail; 5241 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5242 return MCDisassembler::Fail; 5243 Inst.addOperand(MCOperand::createImm(64 - imm)); 5244 5245 return S; 5246 } 5247 5248 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5249 unsigned Insn, 5250 uint64_t Address, 5251 const void *Decoder) { 5252 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5253 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5254 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5255 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5256 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5257 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5258 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5259 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5260 5261 DecodeStatus S = MCDisassembler::Success; 5262 5263 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5264 5265 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5266 return MCDisassembler::Fail; 5267 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5268 return MCDisassembler::Fail; 5269 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5270 return MCDisassembler::Fail; 5271 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5272 return MCDisassembler::Fail; 5273 // The lane index does not have any bits in the encoding, because it can only 5274 // be 0. 5275 Inst.addOperand(MCOperand::createImm(0)); 5276 Inst.addOperand(MCOperand::createImm(rotate)); 5277 5278 return S; 5279 } 5280 5281 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5282 uint64_t Address, const void *Decoder) { 5283 DecodeStatus S = MCDisassembler::Success; 5284 5285 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5286 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5287 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5288 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5289 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5290 5291 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5292 S = MCDisassembler::SoftFail; 5293 5294 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5295 return MCDisassembler::Fail; 5296 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5297 return MCDisassembler::Fail; 5298 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5299 return MCDisassembler::Fail; 5300 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5301 return MCDisassembler::Fail; 5302 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5303 return MCDisassembler::Fail; 5304 5305 return S; 5306 } 5307 5308 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5309 uint64_t Address, const void *Decoder) { 5310 DecodeStatus S = MCDisassembler::Success; 5311 5312 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5313 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5314 unsigned cop = fieldFromInstruction(Val, 8, 4); 5315 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5316 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5317 5318 if ((cop & ~0x1) == 0xa) 5319 return MCDisassembler::Fail; 5320 5321 if (Rt == Rt2) 5322 S = MCDisassembler::SoftFail; 5323 5324 // We have to check if the instruction is MRRC2 5325 // or MCRR2 when constructing the operands for 5326 // Inst. Reason is because MRRC2 stores to two 5327 // registers so it's tablegen desc has has two 5328 // outputs whereas MCRR doesn't store to any 5329 // registers so all of it's operands are listed 5330 // as inputs, therefore the operand order for 5331 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5332 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5333 5334 if (Inst.getOpcode() == ARM::MRRC2) { 5335 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5336 return MCDisassembler::Fail; 5337 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5338 return MCDisassembler::Fail; 5339 } 5340 Inst.addOperand(MCOperand::createImm(cop)); 5341 Inst.addOperand(MCOperand::createImm(opc1)); 5342 if (Inst.getOpcode() == ARM::MCRR2) { 5343 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5344 return MCDisassembler::Fail; 5345 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5346 return MCDisassembler::Fail; 5347 } 5348 Inst.addOperand(MCOperand::createImm(CRm)); 5349 5350 return S; 5351 } 5352 5353 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5354 uint64_t Address, 5355 const void *Decoder) { 5356 const FeatureBitset &featureBits = 5357 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5358 DecodeStatus S = MCDisassembler::Success; 5359 5360 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5361 5362 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5363 if (Rt == 13 || Rt == 15) 5364 S = MCDisassembler::SoftFail; 5365 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5366 } else 5367 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5368 5369 if (featureBits[ARM::ModeThumb]) { 5370 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5371 Inst.addOperand(MCOperand::createReg(0)); 5372 } else { 5373 unsigned pred = fieldFromInstruction(Val, 28, 4); 5374 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5375 return MCDisassembler::Fail; 5376 } 5377 5378 return S; 5379 } 5380