1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "Utils/ARMBaseInfo.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 16 #include "llvm/MC/MCFixedLenDisassembler.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/MC/SubtargetFeature.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/MathExtras.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <algorithm> 27 #include <cassert> 28 #include <cstdint> 29 #include <vector> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "arm-disassembler" 34 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 namespace { 38 39 // Handles the condition code status of instructions in IT blocks 40 class ITStatus 41 { 42 public: 43 // Returns the condition code for instruction in IT block 44 unsigned getITCC() { 45 unsigned CC = ARMCC::AL; 46 if (instrInITBlock()) 47 CC = ITStates.back(); 48 return CC; 49 } 50 51 // Advances the IT block state to the next T or E 52 void advanceITState() { 53 ITStates.pop_back(); 54 } 55 56 // Returns true if the current instruction is in an IT block 57 bool instrInITBlock() { 58 return !ITStates.empty(); 59 } 60 61 // Returns true if current instruction is the last instruction in an IT block 62 bool instrLastInITBlock() { 63 return ITStates.size() == 1; 64 } 65 66 // Called when decoding an IT instruction. Sets the IT state for the following 67 // instructions that for the IT block. Firstcond and Mask correspond to the 68 // fields in the IT instruction encoding. 69 void setITState(char Firstcond, char Mask) { 70 // (3 - the number of trailing zeros) is the number of then / else. 71 unsigned CondBit0 = Firstcond & 1; 72 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 73 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 74 assert(NumTZ <= 3 && "Invalid IT mask!"); 75 // push condition codes onto the stack the correct order for the pops 76 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 77 bool T = ((Mask >> Pos) & 1) == CondBit0; 78 if (T) 79 ITStates.push_back(CCBits); 80 else 81 ITStates.push_back(CCBits ^ 1); 82 } 83 ITStates.push_back(CCBits); 84 } 85 86 private: 87 std::vector<unsigned char> ITStates; 88 }; 89 90 /// ARM disassembler for all ARM platforms. 91 class ARMDisassembler : public MCDisassembler { 92 public: 93 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 94 MCDisassembler(STI, Ctx) { 95 } 96 97 ~ARMDisassembler() override = default; 98 99 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 100 ArrayRef<uint8_t> Bytes, uint64_t Address, 101 raw_ostream &VStream, 102 raw_ostream &CStream) const override; 103 }; 104 105 /// Thumb disassembler for all Thumb platforms. 106 class ThumbDisassembler : public MCDisassembler { 107 public: 108 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 109 MCDisassembler(STI, Ctx) { 110 } 111 112 ~ThumbDisassembler() override = default; 113 114 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 115 ArrayRef<uint8_t> Bytes, uint64_t Address, 116 raw_ostream &VStream, 117 raw_ostream &CStream) const override; 118 119 private: 120 mutable ITStatus ITBlock; 121 122 DecodeStatus AddThumbPredicate(MCInst&) const; 123 void UpdateThumbVFPPredicate(MCInst&) const; 124 }; 125 126 } // end anonymous namespace 127 128 static bool Check(DecodeStatus &Out, DecodeStatus In) { 129 switch (In) { 130 case MCDisassembler::Success: 131 // Out stays the same. 132 return true; 133 case MCDisassembler::SoftFail: 134 Out = In; 135 return true; 136 case MCDisassembler::Fail: 137 Out = In; 138 return false; 139 } 140 llvm_unreachable("Invalid DecodeStatus!"); 141 } 142 143 // Forward declare these because the autogenerated code will reference them. 144 // Definitions are further down. 145 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 146 uint64_t Address, const void *Decoder); 147 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 148 unsigned RegNo, uint64_t Address, 149 const void *Decoder); 150 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 151 unsigned RegNo, uint64_t Address, 152 const void *Decoder); 153 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 170 unsigned RegNo, 171 uint64_t Address, 172 const void *Decoder); 173 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 178 unsigned RegNo, uint64_t Address, 179 const void *Decoder); 180 181 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 192 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 197 unsigned Insn, 198 uint64_t Address, 199 const void *Decoder); 200 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 207 uint64_t Address, const void *Decoder); 208 209 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 210 unsigned Insn, 211 uint64_t Adddress, 212 const void *Decoder); 213 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 328 unsigned Val, 329 uint64_t Address, 330 const void *Decoder); 331 332 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void* Decoder); 354 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void* Decoder); 356 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void* Decoder); 358 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 359 uint64_t Address, const void* Decoder); 360 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 403 uint64_t Address, const void *Decoder); 404 405 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 408 uint64_t Address, const void *Decoder); 409 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 410 uint64_t Address, const void *Decoder); 411 412 #include "ARMGenDisassemblerTables.inc" 413 414 static MCDisassembler *createARMDisassembler(const Target &T, 415 const MCSubtargetInfo &STI, 416 MCContext &Ctx) { 417 return new ARMDisassembler(STI, Ctx); 418 } 419 420 static MCDisassembler *createThumbDisassembler(const Target &T, 421 const MCSubtargetInfo &STI, 422 MCContext &Ctx) { 423 return new ThumbDisassembler(STI, Ctx); 424 } 425 426 // Post-decoding checks 427 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 428 uint64_t Address, raw_ostream &OS, 429 raw_ostream &CS, 430 uint32_t Insn, 431 DecodeStatus Result) { 432 switch (MI.getOpcode()) { 433 case ARM::HVC: { 434 // HVC is undefined if condition = 0xf otherwise upredictable 435 // if condition != 0xe 436 uint32_t Cond = (Insn >> 28) & 0xF; 437 if (Cond == 0xF) 438 return MCDisassembler::Fail; 439 if (Cond != 0xE) 440 return MCDisassembler::SoftFail; 441 return Result; 442 } 443 default: return Result; 444 } 445 } 446 447 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 448 ArrayRef<uint8_t> Bytes, 449 uint64_t Address, raw_ostream &OS, 450 raw_ostream &CS) const { 451 CommentStream = &CS; 452 453 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 454 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 455 "mode!"); 456 457 // We want to read exactly 4 bytes of data. 458 if (Bytes.size() < 4) { 459 Size = 0; 460 return MCDisassembler::Fail; 461 } 462 463 // Encoded as a small-endian 32-bit word in the stream. 464 uint32_t Insn = 465 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 466 467 // Calling the auto-generated decoder function. 468 DecodeStatus Result = 469 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 470 if (Result != MCDisassembler::Fail) { 471 Size = 4; 472 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 473 } 474 475 struct DecodeTable { 476 const uint8_t *P; 477 bool DecodePred; 478 }; 479 480 const DecodeTable Tables[] = { 481 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 482 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 483 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 484 {DecoderTablev8Crypto32, false}, 485 }; 486 487 for (auto Table : Tables) { 488 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 489 if (Result != MCDisassembler::Fail) { 490 Size = 4; 491 // Add a fake predicate operand, because we share these instruction 492 // definitions with Thumb2 where these instructions are predicable. 493 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 494 return MCDisassembler::Fail; 495 return Result; 496 } 497 } 498 499 Result = 500 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 501 if (Result != MCDisassembler::Fail) { 502 Size = 4; 503 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 504 } 505 506 Size = 4; 507 return MCDisassembler::Fail; 508 } 509 510 namespace llvm { 511 512 extern const MCInstrDesc ARMInsts[]; 513 514 } // end namespace llvm 515 516 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 517 /// immediate Value in the MCInst. The immediate Value has had any PC 518 /// adjustment made by the caller. If the instruction is a branch instruction 519 /// then isBranch is true, else false. If the getOpInfo() function was set as 520 /// part of the setupForSymbolicDisassembly() call then that function is called 521 /// to get any symbolic information at the Address for this instruction. If 522 /// that returns non-zero then the symbolic information it returns is used to 523 /// create an MCExpr and that is added as an operand to the MCInst. If 524 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 525 /// Value is done and if a symbol is found an MCExpr is created with that, else 526 /// an MCExpr with Value is created. This function returns true if it adds an 527 /// operand to the MCInst and false otherwise. 528 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 529 bool isBranch, uint64_t InstSize, 530 MCInst &MI, const void *Decoder) { 531 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 532 // FIXME: Does it make sense for value to be negative? 533 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 534 /* Offset */ 0, InstSize); 535 } 536 537 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 538 /// referenced by a load instruction with the base register that is the Pc. 539 /// These can often be values in a literal pool near the Address of the 540 /// instruction. The Address of the instruction and its immediate Value are 541 /// used as a possible literal pool entry. The SymbolLookUp call back will 542 /// return the name of a symbol referenced by the literal pool's entry if 543 /// the referenced address is that of a symbol. Or it will return a pointer to 544 /// a literal 'C' string if the referenced address of the literal pool's entry 545 /// is an address into a section with 'C' string literals. 546 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 547 const void *Decoder) { 548 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 549 Dis->tryAddingPcLoadReferenceComment(Value, Address); 550 } 551 552 // Thumb1 instructions don't have explicit S bits. Rather, they 553 // implicitly set CPSR. Since it's not represented in the encoding, the 554 // auto-generated decoder won't inject the CPSR operand. We need to fix 555 // that as a post-pass. 556 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 557 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 558 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 559 MCInst::iterator I = MI.begin(); 560 for (unsigned i = 0; i < NumOps; ++i, ++I) { 561 if (I == MI.end()) break; 562 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 563 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 564 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 565 return; 566 } 567 } 568 569 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 570 } 571 572 // Most Thumb instructions don't have explicit predicates in the 573 // encoding, but rather get their predicates from IT context. We need 574 // to fix up the predicate operands using this context information as a 575 // post-pass. 576 MCDisassembler::DecodeStatus 577 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 578 MCDisassembler::DecodeStatus S = Success; 579 580 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 581 582 // A few instructions actually have predicates encoded in them. Don't 583 // try to overwrite it if we're seeing one of those. 584 switch (MI.getOpcode()) { 585 case ARM::tBcc: 586 case ARM::t2Bcc: 587 case ARM::tCBZ: 588 case ARM::tCBNZ: 589 case ARM::tCPS: 590 case ARM::t2CPS3p: 591 case ARM::t2CPS2p: 592 case ARM::t2CPS1p: 593 case ARM::tMOVSr: 594 case ARM::tSETEND: 595 // Some instructions (mostly conditional branches) are not 596 // allowed in IT blocks. 597 if (ITBlock.instrInITBlock()) 598 S = SoftFail; 599 else 600 return Success; 601 break; 602 case ARM::t2HINT: 603 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 604 S = SoftFail; 605 break; 606 case ARM::tB: 607 case ARM::t2B: 608 case ARM::t2TBB: 609 case ARM::t2TBH: 610 // Some instructions (mostly unconditional branches) can 611 // only appears at the end of, or outside of, an IT. 612 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 613 S = SoftFail; 614 break; 615 default: 616 break; 617 } 618 619 // If we're in an IT block, base the predicate on that. Otherwise, 620 // assume a predicate of AL. 621 unsigned CC; 622 CC = ITBlock.getITCC(); 623 if (CC == 0xF) 624 CC = ARMCC::AL; 625 if (ITBlock.instrInITBlock()) 626 ITBlock.advanceITState(); 627 628 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 629 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 630 MCInst::iterator I = MI.begin(); 631 for (unsigned i = 0; i < NumOps; ++i, ++I) { 632 if (I == MI.end()) break; 633 if (OpInfo[i].isPredicate()) { 634 I = MI.insert(I, MCOperand::createImm(CC)); 635 ++I; 636 if (CC == ARMCC::AL) 637 MI.insert(I, MCOperand::createReg(0)); 638 else 639 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 640 return S; 641 } 642 } 643 644 I = MI.insert(I, MCOperand::createImm(CC)); 645 ++I; 646 if (CC == ARMCC::AL) 647 MI.insert(I, MCOperand::createReg(0)); 648 else 649 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 650 651 return S; 652 } 653 654 // Thumb VFP instructions are a special case. Because we share their 655 // encodings between ARM and Thumb modes, and they are predicable in ARM 656 // mode, the auto-generated decoder will give them an (incorrect) 657 // predicate operand. We need to rewrite these operands based on the IT 658 // context as a post-pass. 659 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 660 unsigned CC; 661 CC = ITBlock.getITCC(); 662 if (ITBlock.instrInITBlock()) 663 ITBlock.advanceITState(); 664 665 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 666 MCInst::iterator I = MI.begin(); 667 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 668 for (unsigned i = 0; i < NumOps; ++i, ++I) { 669 if (OpInfo[i].isPredicate() ) { 670 I->setImm(CC); 671 ++I; 672 if (CC == ARMCC::AL) 673 I->setReg(0); 674 else 675 I->setReg(ARM::CPSR); 676 return; 677 } 678 } 679 } 680 681 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 682 ArrayRef<uint8_t> Bytes, 683 uint64_t Address, 684 raw_ostream &OS, 685 raw_ostream &CS) const { 686 CommentStream = &CS; 687 688 assert(STI.getFeatureBits()[ARM::ModeThumb] && 689 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 690 691 // We want to read exactly 2 bytes of data. 692 if (Bytes.size() < 2) { 693 Size = 0; 694 return MCDisassembler::Fail; 695 } 696 697 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 698 DecodeStatus Result = 699 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 700 if (Result != MCDisassembler::Fail) { 701 Size = 2; 702 Check(Result, AddThumbPredicate(MI)); 703 return Result; 704 } 705 706 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 707 STI); 708 if (Result) { 709 Size = 2; 710 bool InITBlock = ITBlock.instrInITBlock(); 711 Check(Result, AddThumbPredicate(MI)); 712 AddThumb1SBit(MI, InITBlock); 713 return Result; 714 } 715 716 Result = 717 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 718 if (Result != MCDisassembler::Fail) { 719 Size = 2; 720 721 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 722 // the Thumb predicate. 723 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 724 Result = MCDisassembler::SoftFail; 725 726 Check(Result, AddThumbPredicate(MI)); 727 728 // If we find an IT instruction, we need to parse its condition 729 // code and mask operands so that we can apply them correctly 730 // to the subsequent instructions. 731 if (MI.getOpcode() == ARM::t2IT) { 732 unsigned Firstcond = MI.getOperand(0).getImm(); 733 unsigned Mask = MI.getOperand(1).getImm(); 734 ITBlock.setITState(Firstcond, Mask); 735 736 // An IT instruction that would give a 'NV' predicate is unpredictable. 737 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 738 CS << "unpredictable IT predicate sequence"; 739 } 740 741 return Result; 742 } 743 744 // We want to read exactly 4 bytes of data. 745 if (Bytes.size() < 4) { 746 Size = 0; 747 return MCDisassembler::Fail; 748 } 749 750 uint32_t Insn32 = 751 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 752 Result = 753 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 754 if (Result != MCDisassembler::Fail) { 755 Size = 4; 756 bool InITBlock = ITBlock.instrInITBlock(); 757 Check(Result, AddThumbPredicate(MI)); 758 AddThumb1SBit(MI, InITBlock); 759 return Result; 760 } 761 762 Result = 763 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 764 if (Result != MCDisassembler::Fail) { 765 Size = 4; 766 Check(Result, AddThumbPredicate(MI)); 767 return Result; 768 } 769 770 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 771 Result = 772 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 773 if (Result != MCDisassembler::Fail) { 774 Size = 4; 775 UpdateThumbVFPPredicate(MI); 776 return Result; 777 } 778 } 779 780 Result = 781 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 782 if (Result != MCDisassembler::Fail) { 783 Size = 4; 784 return Result; 785 } 786 787 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 788 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 789 STI); 790 if (Result != MCDisassembler::Fail) { 791 Size = 4; 792 Check(Result, AddThumbPredicate(MI)); 793 return Result; 794 } 795 } 796 797 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 798 uint32_t NEONLdStInsn = Insn32; 799 NEONLdStInsn &= 0xF0FFFFFF; 800 NEONLdStInsn |= 0x04000000; 801 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 802 Address, this, STI); 803 if (Result != MCDisassembler::Fail) { 804 Size = 4; 805 Check(Result, AddThumbPredicate(MI)); 806 return Result; 807 } 808 } 809 810 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 811 uint32_t NEONDataInsn = Insn32; 812 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 813 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 814 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 815 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 816 Address, this, STI); 817 if (Result != MCDisassembler::Fail) { 818 Size = 4; 819 Check(Result, AddThumbPredicate(MI)); 820 return Result; 821 } 822 823 uint32_t NEONCryptoInsn = Insn32; 824 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 825 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 826 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 827 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 828 Address, this, STI); 829 if (Result != MCDisassembler::Fail) { 830 Size = 4; 831 return Result; 832 } 833 834 uint32_t NEONv8Insn = Insn32; 835 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 836 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 837 this, STI); 838 if (Result != MCDisassembler::Fail) { 839 Size = 4; 840 return Result; 841 } 842 } 843 844 Result = 845 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 846 if (Result != MCDisassembler::Fail) { 847 Size = 4; 848 Check(Result, AddThumbPredicate(MI)); 849 return Result; 850 } 851 852 Size = 0; 853 return MCDisassembler::Fail; 854 } 855 856 extern "C" void LLVMInitializeARMDisassembler() { 857 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 858 createARMDisassembler); 859 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 860 createARMDisassembler); 861 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 862 createThumbDisassembler); 863 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 864 createThumbDisassembler); 865 } 866 867 static const uint16_t GPRDecoderTable[] = { 868 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 869 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 870 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 871 ARM::R12, ARM::SP, ARM::LR, ARM::PC 872 }; 873 874 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 875 uint64_t Address, const void *Decoder) { 876 if (RegNo > 15) 877 return MCDisassembler::Fail; 878 879 unsigned Register = GPRDecoderTable[RegNo]; 880 Inst.addOperand(MCOperand::createReg(Register)); 881 return MCDisassembler::Success; 882 } 883 884 static DecodeStatus 885 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 886 uint64_t Address, const void *Decoder) { 887 DecodeStatus S = MCDisassembler::Success; 888 889 if (RegNo == 15) 890 S = MCDisassembler::SoftFail; 891 892 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 893 894 return S; 895 } 896 897 static DecodeStatus 898 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 899 uint64_t Address, const void *Decoder) { 900 DecodeStatus S = MCDisassembler::Success; 901 902 if (RegNo == 15) 903 { 904 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 905 return MCDisassembler::Success; 906 } 907 908 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 909 return S; 910 } 911 912 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 913 uint64_t Address, const void *Decoder) { 914 if (RegNo > 7) 915 return MCDisassembler::Fail; 916 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 917 } 918 919 static const uint16_t GPRPairDecoderTable[] = { 920 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 921 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 922 }; 923 924 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 925 uint64_t Address, const void *Decoder) { 926 DecodeStatus S = MCDisassembler::Success; 927 928 if (RegNo > 13) 929 return MCDisassembler::Fail; 930 931 if ((RegNo & 1) || RegNo == 0xe) 932 S = MCDisassembler::SoftFail; 933 934 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 935 Inst.addOperand(MCOperand::createReg(RegisterPair)); 936 return S; 937 } 938 939 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 940 uint64_t Address, const void *Decoder) { 941 unsigned Register = 0; 942 switch (RegNo) { 943 case 0: 944 Register = ARM::R0; 945 break; 946 case 1: 947 Register = ARM::R1; 948 break; 949 case 2: 950 Register = ARM::R2; 951 break; 952 case 3: 953 Register = ARM::R3; 954 break; 955 case 9: 956 Register = ARM::R9; 957 break; 958 case 12: 959 Register = ARM::R12; 960 break; 961 default: 962 return MCDisassembler::Fail; 963 } 964 965 Inst.addOperand(MCOperand::createReg(Register)); 966 return MCDisassembler::Success; 967 } 968 969 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 970 uint64_t Address, const void *Decoder) { 971 DecodeStatus S = MCDisassembler::Success; 972 973 const FeatureBitset &featureBits = 974 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 975 976 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 977 S = MCDisassembler::SoftFail; 978 979 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 980 return S; 981 } 982 983 static const uint16_t SPRDecoderTable[] = { 984 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 985 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 986 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 987 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 988 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 989 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 990 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 991 ARM::S28, ARM::S29, ARM::S30, ARM::S31 992 }; 993 994 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 995 uint64_t Address, const void *Decoder) { 996 if (RegNo > 31) 997 return MCDisassembler::Fail; 998 999 unsigned Register = SPRDecoderTable[RegNo]; 1000 Inst.addOperand(MCOperand::createReg(Register)); 1001 return MCDisassembler::Success; 1002 } 1003 1004 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1005 uint64_t Address, const void *Decoder) { 1006 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1007 } 1008 1009 static const uint16_t DPRDecoderTable[] = { 1010 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1011 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1012 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1013 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1014 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1015 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1016 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1017 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1018 }; 1019 1020 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1021 uint64_t Address, const void *Decoder) { 1022 const FeatureBitset &featureBits = 1023 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1024 1025 bool hasD16 = featureBits[ARM::FeatureD16]; 1026 1027 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1028 return MCDisassembler::Fail; 1029 1030 unsigned Register = DPRDecoderTable[RegNo]; 1031 Inst.addOperand(MCOperand::createReg(Register)); 1032 return MCDisassembler::Success; 1033 } 1034 1035 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1036 uint64_t Address, const void *Decoder) { 1037 if (RegNo > 7) 1038 return MCDisassembler::Fail; 1039 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1040 } 1041 1042 static DecodeStatus 1043 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1044 uint64_t Address, const void *Decoder) { 1045 if (RegNo > 15) 1046 return MCDisassembler::Fail; 1047 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1048 } 1049 1050 static const uint16_t QPRDecoderTable[] = { 1051 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1052 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1053 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1054 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1055 }; 1056 1057 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1058 uint64_t Address, const void *Decoder) { 1059 if (RegNo > 31 || (RegNo & 1) != 0) 1060 return MCDisassembler::Fail; 1061 RegNo >>= 1; 1062 1063 unsigned Register = QPRDecoderTable[RegNo]; 1064 Inst.addOperand(MCOperand::createReg(Register)); 1065 return MCDisassembler::Success; 1066 } 1067 1068 static const uint16_t DPairDecoderTable[] = { 1069 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1070 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1071 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1072 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1073 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1074 ARM::Q15 1075 }; 1076 1077 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1078 uint64_t Address, const void *Decoder) { 1079 if (RegNo > 30) 1080 return MCDisassembler::Fail; 1081 1082 unsigned Register = DPairDecoderTable[RegNo]; 1083 Inst.addOperand(MCOperand::createReg(Register)); 1084 return MCDisassembler::Success; 1085 } 1086 1087 static const uint16_t DPairSpacedDecoderTable[] = { 1088 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1089 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1090 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1091 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1092 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1093 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1094 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1095 ARM::D28_D30, ARM::D29_D31 1096 }; 1097 1098 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1099 unsigned RegNo, 1100 uint64_t Address, 1101 const void *Decoder) { 1102 if (RegNo > 29) 1103 return MCDisassembler::Fail; 1104 1105 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1106 Inst.addOperand(MCOperand::createReg(Register)); 1107 return MCDisassembler::Success; 1108 } 1109 1110 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1111 uint64_t Address, const void *Decoder) { 1112 if (Val == 0xF) return MCDisassembler::Fail; 1113 // AL predicate is not allowed on Thumb1 branches. 1114 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1115 return MCDisassembler::Fail; 1116 Inst.addOperand(MCOperand::createImm(Val)); 1117 if (Val == ARMCC::AL) { 1118 Inst.addOperand(MCOperand::createReg(0)); 1119 } else 1120 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1121 return MCDisassembler::Success; 1122 } 1123 1124 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1125 uint64_t Address, const void *Decoder) { 1126 if (Val) 1127 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1128 else 1129 Inst.addOperand(MCOperand::createReg(0)); 1130 return MCDisassembler::Success; 1131 } 1132 1133 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1134 uint64_t Address, const void *Decoder) { 1135 DecodeStatus S = MCDisassembler::Success; 1136 1137 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1138 unsigned type = fieldFromInstruction(Val, 5, 2); 1139 unsigned imm = fieldFromInstruction(Val, 7, 5); 1140 1141 // Register-immediate 1142 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1143 return MCDisassembler::Fail; 1144 1145 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1146 switch (type) { 1147 case 0: 1148 Shift = ARM_AM::lsl; 1149 break; 1150 case 1: 1151 Shift = ARM_AM::lsr; 1152 break; 1153 case 2: 1154 Shift = ARM_AM::asr; 1155 break; 1156 case 3: 1157 Shift = ARM_AM::ror; 1158 break; 1159 } 1160 1161 if (Shift == ARM_AM::ror && imm == 0) 1162 Shift = ARM_AM::rrx; 1163 1164 unsigned Op = Shift | (imm << 3); 1165 Inst.addOperand(MCOperand::createImm(Op)); 1166 1167 return S; 1168 } 1169 1170 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1171 uint64_t Address, const void *Decoder) { 1172 DecodeStatus S = MCDisassembler::Success; 1173 1174 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1175 unsigned type = fieldFromInstruction(Val, 5, 2); 1176 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1177 1178 // Register-register 1179 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1180 return MCDisassembler::Fail; 1181 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1182 return MCDisassembler::Fail; 1183 1184 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1185 switch (type) { 1186 case 0: 1187 Shift = ARM_AM::lsl; 1188 break; 1189 case 1: 1190 Shift = ARM_AM::lsr; 1191 break; 1192 case 2: 1193 Shift = ARM_AM::asr; 1194 break; 1195 case 3: 1196 Shift = ARM_AM::ror; 1197 break; 1198 } 1199 1200 Inst.addOperand(MCOperand::createImm(Shift)); 1201 1202 return S; 1203 } 1204 1205 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1206 uint64_t Address, const void *Decoder) { 1207 DecodeStatus S = MCDisassembler::Success; 1208 1209 bool NeedDisjointWriteback = false; 1210 unsigned WritebackReg = 0; 1211 switch (Inst.getOpcode()) { 1212 default: 1213 break; 1214 case ARM::LDMIA_UPD: 1215 case ARM::LDMDB_UPD: 1216 case ARM::LDMIB_UPD: 1217 case ARM::LDMDA_UPD: 1218 case ARM::t2LDMIA_UPD: 1219 case ARM::t2LDMDB_UPD: 1220 case ARM::t2STMIA_UPD: 1221 case ARM::t2STMDB_UPD: 1222 NeedDisjointWriteback = true; 1223 WritebackReg = Inst.getOperand(0).getReg(); 1224 break; 1225 } 1226 1227 // Empty register lists are not allowed. 1228 if (Val == 0) return MCDisassembler::Fail; 1229 for (unsigned i = 0; i < 16; ++i) { 1230 if (Val & (1 << i)) { 1231 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1232 return MCDisassembler::Fail; 1233 // Writeback not allowed if Rn is in the target list. 1234 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1235 Check(S, MCDisassembler::SoftFail); 1236 } 1237 } 1238 1239 return S; 1240 } 1241 1242 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1243 uint64_t Address, const void *Decoder) { 1244 DecodeStatus S = MCDisassembler::Success; 1245 1246 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1247 unsigned regs = fieldFromInstruction(Val, 0, 8); 1248 1249 // In case of unpredictable encoding, tweak the operands. 1250 if (regs == 0 || (Vd + regs) > 32) { 1251 regs = Vd + regs > 32 ? 32 - Vd : regs; 1252 regs = std::max( 1u, regs); 1253 S = MCDisassembler::SoftFail; 1254 } 1255 1256 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1257 return MCDisassembler::Fail; 1258 for (unsigned i = 0; i < (regs - 1); ++i) { 1259 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1260 return MCDisassembler::Fail; 1261 } 1262 1263 return S; 1264 } 1265 1266 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1267 uint64_t Address, const void *Decoder) { 1268 DecodeStatus S = MCDisassembler::Success; 1269 1270 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1271 unsigned regs = fieldFromInstruction(Val, 1, 7); 1272 1273 // In case of unpredictable encoding, tweak the operands. 1274 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1275 regs = Vd + regs > 32 ? 32 - Vd : regs; 1276 regs = std::max( 1u, regs); 1277 regs = std::min(16u, regs); 1278 S = MCDisassembler::SoftFail; 1279 } 1280 1281 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1282 return MCDisassembler::Fail; 1283 for (unsigned i = 0; i < (regs - 1); ++i) { 1284 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1285 return MCDisassembler::Fail; 1286 } 1287 1288 return S; 1289 } 1290 1291 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1292 uint64_t Address, const void *Decoder) { 1293 // This operand encodes a mask of contiguous zeros between a specified MSB 1294 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1295 // the mask of all bits LSB-and-lower, and then xor them to create 1296 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1297 // create the final mask. 1298 unsigned msb = fieldFromInstruction(Val, 5, 5); 1299 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1300 1301 DecodeStatus S = MCDisassembler::Success; 1302 if (lsb > msb) { 1303 Check(S, MCDisassembler::SoftFail); 1304 // The check above will cause the warning for the "potentially undefined 1305 // instruction encoding" but we can't build a bad MCOperand value here 1306 // with a lsb > msb or else printing the MCInst will cause a crash. 1307 lsb = msb; 1308 } 1309 1310 uint32_t msb_mask = 0xFFFFFFFF; 1311 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1312 uint32_t lsb_mask = (1U << lsb) - 1; 1313 1314 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1315 return S; 1316 } 1317 1318 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1319 uint64_t Address, const void *Decoder) { 1320 DecodeStatus S = MCDisassembler::Success; 1321 1322 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1323 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1324 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1325 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1326 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1327 unsigned U = fieldFromInstruction(Insn, 23, 1); 1328 1329 switch (Inst.getOpcode()) { 1330 case ARM::LDC_OFFSET: 1331 case ARM::LDC_PRE: 1332 case ARM::LDC_POST: 1333 case ARM::LDC_OPTION: 1334 case ARM::LDCL_OFFSET: 1335 case ARM::LDCL_PRE: 1336 case ARM::LDCL_POST: 1337 case ARM::LDCL_OPTION: 1338 case ARM::STC_OFFSET: 1339 case ARM::STC_PRE: 1340 case ARM::STC_POST: 1341 case ARM::STC_OPTION: 1342 case ARM::STCL_OFFSET: 1343 case ARM::STCL_PRE: 1344 case ARM::STCL_POST: 1345 case ARM::STCL_OPTION: 1346 case ARM::t2LDC_OFFSET: 1347 case ARM::t2LDC_PRE: 1348 case ARM::t2LDC_POST: 1349 case ARM::t2LDC_OPTION: 1350 case ARM::t2LDCL_OFFSET: 1351 case ARM::t2LDCL_PRE: 1352 case ARM::t2LDCL_POST: 1353 case ARM::t2LDCL_OPTION: 1354 case ARM::t2STC_OFFSET: 1355 case ARM::t2STC_PRE: 1356 case ARM::t2STC_POST: 1357 case ARM::t2STC_OPTION: 1358 case ARM::t2STCL_OFFSET: 1359 case ARM::t2STCL_PRE: 1360 case ARM::t2STCL_POST: 1361 case ARM::t2STCL_OPTION: 1362 if (coproc == 0xA || coproc == 0xB) 1363 return MCDisassembler::Fail; 1364 break; 1365 default: 1366 break; 1367 } 1368 1369 const FeatureBitset &featureBits = 1370 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1371 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1372 return MCDisassembler::Fail; 1373 1374 Inst.addOperand(MCOperand::createImm(coproc)); 1375 Inst.addOperand(MCOperand::createImm(CRd)); 1376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1377 return MCDisassembler::Fail; 1378 1379 switch (Inst.getOpcode()) { 1380 case ARM::t2LDC2_OFFSET: 1381 case ARM::t2LDC2L_OFFSET: 1382 case ARM::t2LDC2_PRE: 1383 case ARM::t2LDC2L_PRE: 1384 case ARM::t2STC2_OFFSET: 1385 case ARM::t2STC2L_OFFSET: 1386 case ARM::t2STC2_PRE: 1387 case ARM::t2STC2L_PRE: 1388 case ARM::LDC2_OFFSET: 1389 case ARM::LDC2L_OFFSET: 1390 case ARM::LDC2_PRE: 1391 case ARM::LDC2L_PRE: 1392 case ARM::STC2_OFFSET: 1393 case ARM::STC2L_OFFSET: 1394 case ARM::STC2_PRE: 1395 case ARM::STC2L_PRE: 1396 case ARM::t2LDC_OFFSET: 1397 case ARM::t2LDCL_OFFSET: 1398 case ARM::t2LDC_PRE: 1399 case ARM::t2LDCL_PRE: 1400 case ARM::t2STC_OFFSET: 1401 case ARM::t2STCL_OFFSET: 1402 case ARM::t2STC_PRE: 1403 case ARM::t2STCL_PRE: 1404 case ARM::LDC_OFFSET: 1405 case ARM::LDCL_OFFSET: 1406 case ARM::LDC_PRE: 1407 case ARM::LDCL_PRE: 1408 case ARM::STC_OFFSET: 1409 case ARM::STCL_OFFSET: 1410 case ARM::STC_PRE: 1411 case ARM::STCL_PRE: 1412 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1413 Inst.addOperand(MCOperand::createImm(imm)); 1414 break; 1415 case ARM::t2LDC2_POST: 1416 case ARM::t2LDC2L_POST: 1417 case ARM::t2STC2_POST: 1418 case ARM::t2STC2L_POST: 1419 case ARM::LDC2_POST: 1420 case ARM::LDC2L_POST: 1421 case ARM::STC2_POST: 1422 case ARM::STC2L_POST: 1423 case ARM::t2LDC_POST: 1424 case ARM::t2LDCL_POST: 1425 case ARM::t2STC_POST: 1426 case ARM::t2STCL_POST: 1427 case ARM::LDC_POST: 1428 case ARM::LDCL_POST: 1429 case ARM::STC_POST: 1430 case ARM::STCL_POST: 1431 imm |= U << 8; 1432 LLVM_FALLTHROUGH; 1433 default: 1434 // The 'option' variant doesn't encode 'U' in the immediate since 1435 // the immediate is unsigned [0,255]. 1436 Inst.addOperand(MCOperand::createImm(imm)); 1437 break; 1438 } 1439 1440 switch (Inst.getOpcode()) { 1441 case ARM::LDC_OFFSET: 1442 case ARM::LDC_PRE: 1443 case ARM::LDC_POST: 1444 case ARM::LDC_OPTION: 1445 case ARM::LDCL_OFFSET: 1446 case ARM::LDCL_PRE: 1447 case ARM::LDCL_POST: 1448 case ARM::LDCL_OPTION: 1449 case ARM::STC_OFFSET: 1450 case ARM::STC_PRE: 1451 case ARM::STC_POST: 1452 case ARM::STC_OPTION: 1453 case ARM::STCL_OFFSET: 1454 case ARM::STCL_PRE: 1455 case ARM::STCL_POST: 1456 case ARM::STCL_OPTION: 1457 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1458 return MCDisassembler::Fail; 1459 break; 1460 default: 1461 break; 1462 } 1463 1464 return S; 1465 } 1466 1467 static DecodeStatus 1468 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1469 uint64_t Address, const void *Decoder) { 1470 DecodeStatus S = MCDisassembler::Success; 1471 1472 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1473 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1474 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1475 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1476 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1477 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1478 unsigned P = fieldFromInstruction(Insn, 24, 1); 1479 unsigned W = fieldFromInstruction(Insn, 21, 1); 1480 1481 // On stores, the writeback operand precedes Rt. 1482 switch (Inst.getOpcode()) { 1483 case ARM::STR_POST_IMM: 1484 case ARM::STR_POST_REG: 1485 case ARM::STRB_POST_IMM: 1486 case ARM::STRB_POST_REG: 1487 case ARM::STRT_POST_REG: 1488 case ARM::STRT_POST_IMM: 1489 case ARM::STRBT_POST_REG: 1490 case ARM::STRBT_POST_IMM: 1491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1492 return MCDisassembler::Fail; 1493 break; 1494 default: 1495 break; 1496 } 1497 1498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1499 return MCDisassembler::Fail; 1500 1501 // On loads, the writeback operand comes after Rt. 1502 switch (Inst.getOpcode()) { 1503 case ARM::LDR_POST_IMM: 1504 case ARM::LDR_POST_REG: 1505 case ARM::LDRB_POST_IMM: 1506 case ARM::LDRB_POST_REG: 1507 case ARM::LDRBT_POST_REG: 1508 case ARM::LDRBT_POST_IMM: 1509 case ARM::LDRT_POST_REG: 1510 case ARM::LDRT_POST_IMM: 1511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1512 return MCDisassembler::Fail; 1513 break; 1514 default: 1515 break; 1516 } 1517 1518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1519 return MCDisassembler::Fail; 1520 1521 ARM_AM::AddrOpc Op = ARM_AM::add; 1522 if (!fieldFromInstruction(Insn, 23, 1)) 1523 Op = ARM_AM::sub; 1524 1525 bool writeback = (P == 0) || (W == 1); 1526 unsigned idx_mode = 0; 1527 if (P && writeback) 1528 idx_mode = ARMII::IndexModePre; 1529 else if (!P && writeback) 1530 idx_mode = ARMII::IndexModePost; 1531 1532 if (writeback && (Rn == 15 || Rn == Rt)) 1533 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1534 1535 if (reg) { 1536 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1537 return MCDisassembler::Fail; 1538 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1539 switch( fieldFromInstruction(Insn, 5, 2)) { 1540 case 0: 1541 Opc = ARM_AM::lsl; 1542 break; 1543 case 1: 1544 Opc = ARM_AM::lsr; 1545 break; 1546 case 2: 1547 Opc = ARM_AM::asr; 1548 break; 1549 case 3: 1550 Opc = ARM_AM::ror; 1551 break; 1552 default: 1553 return MCDisassembler::Fail; 1554 } 1555 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1556 if (Opc == ARM_AM::ror && amt == 0) 1557 Opc = ARM_AM::rrx; 1558 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1559 1560 Inst.addOperand(MCOperand::createImm(imm)); 1561 } else { 1562 Inst.addOperand(MCOperand::createReg(0)); 1563 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1564 Inst.addOperand(MCOperand::createImm(tmp)); 1565 } 1566 1567 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1568 return MCDisassembler::Fail; 1569 1570 return S; 1571 } 1572 1573 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1574 uint64_t Address, const void *Decoder) { 1575 DecodeStatus S = MCDisassembler::Success; 1576 1577 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1578 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1579 unsigned type = fieldFromInstruction(Val, 5, 2); 1580 unsigned imm = fieldFromInstruction(Val, 7, 5); 1581 unsigned U = fieldFromInstruction(Val, 12, 1); 1582 1583 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1584 switch (type) { 1585 case 0: 1586 ShOp = ARM_AM::lsl; 1587 break; 1588 case 1: 1589 ShOp = ARM_AM::lsr; 1590 break; 1591 case 2: 1592 ShOp = ARM_AM::asr; 1593 break; 1594 case 3: 1595 ShOp = ARM_AM::ror; 1596 break; 1597 } 1598 1599 if (ShOp == ARM_AM::ror && imm == 0) 1600 ShOp = ARM_AM::rrx; 1601 1602 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1603 return MCDisassembler::Fail; 1604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1605 return MCDisassembler::Fail; 1606 unsigned shift; 1607 if (U) 1608 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1609 else 1610 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1611 Inst.addOperand(MCOperand::createImm(shift)); 1612 1613 return S; 1614 } 1615 1616 static DecodeStatus 1617 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1618 uint64_t Address, const void *Decoder) { 1619 DecodeStatus S = MCDisassembler::Success; 1620 1621 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1622 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1623 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1624 unsigned type = fieldFromInstruction(Insn, 22, 1); 1625 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1626 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1627 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1628 unsigned W = fieldFromInstruction(Insn, 21, 1); 1629 unsigned P = fieldFromInstruction(Insn, 24, 1); 1630 unsigned Rt2 = Rt + 1; 1631 1632 bool writeback = (W == 1) | (P == 0); 1633 1634 // For {LD,ST}RD, Rt must be even, else undefined. 1635 switch (Inst.getOpcode()) { 1636 case ARM::STRD: 1637 case ARM::STRD_PRE: 1638 case ARM::STRD_POST: 1639 case ARM::LDRD: 1640 case ARM::LDRD_PRE: 1641 case ARM::LDRD_POST: 1642 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1643 break; 1644 default: 1645 break; 1646 } 1647 switch (Inst.getOpcode()) { 1648 case ARM::STRD: 1649 case ARM::STRD_PRE: 1650 case ARM::STRD_POST: 1651 if (P == 0 && W == 1) 1652 S = MCDisassembler::SoftFail; 1653 1654 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1655 S = MCDisassembler::SoftFail; 1656 if (type && Rm == 15) 1657 S = MCDisassembler::SoftFail; 1658 if (Rt2 == 15) 1659 S = MCDisassembler::SoftFail; 1660 if (!type && fieldFromInstruction(Insn, 8, 4)) 1661 S = MCDisassembler::SoftFail; 1662 break; 1663 case ARM::STRH: 1664 case ARM::STRH_PRE: 1665 case ARM::STRH_POST: 1666 if (Rt == 15) 1667 S = MCDisassembler::SoftFail; 1668 if (writeback && (Rn == 15 || Rn == Rt)) 1669 S = MCDisassembler::SoftFail; 1670 if (!type && Rm == 15) 1671 S = MCDisassembler::SoftFail; 1672 break; 1673 case ARM::LDRD: 1674 case ARM::LDRD_PRE: 1675 case ARM::LDRD_POST: 1676 if (type && Rn == 15) { 1677 if (Rt2 == 15) 1678 S = MCDisassembler::SoftFail; 1679 break; 1680 } 1681 if (P == 0 && W == 1) 1682 S = MCDisassembler::SoftFail; 1683 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1684 S = MCDisassembler::SoftFail; 1685 if (!type && writeback && Rn == 15) 1686 S = MCDisassembler::SoftFail; 1687 if (writeback && (Rn == Rt || Rn == Rt2)) 1688 S = MCDisassembler::SoftFail; 1689 break; 1690 case ARM::LDRH: 1691 case ARM::LDRH_PRE: 1692 case ARM::LDRH_POST: 1693 if (type && Rn == 15) { 1694 if (Rt == 15) 1695 S = MCDisassembler::SoftFail; 1696 break; 1697 } 1698 if (Rt == 15) 1699 S = MCDisassembler::SoftFail; 1700 if (!type && Rm == 15) 1701 S = MCDisassembler::SoftFail; 1702 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1703 S = MCDisassembler::SoftFail; 1704 break; 1705 case ARM::LDRSH: 1706 case ARM::LDRSH_PRE: 1707 case ARM::LDRSH_POST: 1708 case ARM::LDRSB: 1709 case ARM::LDRSB_PRE: 1710 case ARM::LDRSB_POST: 1711 if (type && Rn == 15) { 1712 if (Rt == 15) 1713 S = MCDisassembler::SoftFail; 1714 break; 1715 } 1716 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1717 S = MCDisassembler::SoftFail; 1718 if (!type && (Rt == 15 || Rm == 15)) 1719 S = MCDisassembler::SoftFail; 1720 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1721 S = MCDisassembler::SoftFail; 1722 break; 1723 default: 1724 break; 1725 } 1726 1727 if (writeback) { // Writeback 1728 if (P) 1729 U |= ARMII::IndexModePre << 9; 1730 else 1731 U |= ARMII::IndexModePost << 9; 1732 1733 // On stores, the writeback operand precedes Rt. 1734 switch (Inst.getOpcode()) { 1735 case ARM::STRD: 1736 case ARM::STRD_PRE: 1737 case ARM::STRD_POST: 1738 case ARM::STRH: 1739 case ARM::STRH_PRE: 1740 case ARM::STRH_POST: 1741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1742 return MCDisassembler::Fail; 1743 break; 1744 default: 1745 break; 1746 } 1747 } 1748 1749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1750 return MCDisassembler::Fail; 1751 switch (Inst.getOpcode()) { 1752 case ARM::STRD: 1753 case ARM::STRD_PRE: 1754 case ARM::STRD_POST: 1755 case ARM::LDRD: 1756 case ARM::LDRD_PRE: 1757 case ARM::LDRD_POST: 1758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1759 return MCDisassembler::Fail; 1760 break; 1761 default: 1762 break; 1763 } 1764 1765 if (writeback) { 1766 // On loads, the writeback operand comes after Rt. 1767 switch (Inst.getOpcode()) { 1768 case ARM::LDRD: 1769 case ARM::LDRD_PRE: 1770 case ARM::LDRD_POST: 1771 case ARM::LDRH: 1772 case ARM::LDRH_PRE: 1773 case ARM::LDRH_POST: 1774 case ARM::LDRSH: 1775 case ARM::LDRSH_PRE: 1776 case ARM::LDRSH_POST: 1777 case ARM::LDRSB: 1778 case ARM::LDRSB_PRE: 1779 case ARM::LDRSB_POST: 1780 case ARM::LDRHTr: 1781 case ARM::LDRSBTr: 1782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1783 return MCDisassembler::Fail; 1784 break; 1785 default: 1786 break; 1787 } 1788 } 1789 1790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1791 return MCDisassembler::Fail; 1792 1793 if (type) { 1794 Inst.addOperand(MCOperand::createReg(0)); 1795 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1796 } else { 1797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1798 return MCDisassembler::Fail; 1799 Inst.addOperand(MCOperand::createImm(U)); 1800 } 1801 1802 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1803 return MCDisassembler::Fail; 1804 1805 return S; 1806 } 1807 1808 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1809 uint64_t Address, const void *Decoder) { 1810 DecodeStatus S = MCDisassembler::Success; 1811 1812 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1813 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1814 1815 switch (mode) { 1816 case 0: 1817 mode = ARM_AM::da; 1818 break; 1819 case 1: 1820 mode = ARM_AM::ia; 1821 break; 1822 case 2: 1823 mode = ARM_AM::db; 1824 break; 1825 case 3: 1826 mode = ARM_AM::ib; 1827 break; 1828 } 1829 1830 Inst.addOperand(MCOperand::createImm(mode)); 1831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1832 return MCDisassembler::Fail; 1833 1834 return S; 1835 } 1836 1837 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1838 uint64_t Address, const void *Decoder) { 1839 DecodeStatus S = MCDisassembler::Success; 1840 1841 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1842 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1843 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1844 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1845 1846 if (pred == 0xF) 1847 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1848 1849 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1850 return MCDisassembler::Fail; 1851 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1852 return MCDisassembler::Fail; 1853 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1854 return MCDisassembler::Fail; 1855 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1856 return MCDisassembler::Fail; 1857 return S; 1858 } 1859 1860 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1861 unsigned Insn, 1862 uint64_t Address, const void *Decoder) { 1863 DecodeStatus S = MCDisassembler::Success; 1864 1865 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1866 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1867 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1868 1869 if (pred == 0xF) { 1870 // Ambiguous with RFE and SRS 1871 switch (Inst.getOpcode()) { 1872 case ARM::LDMDA: 1873 Inst.setOpcode(ARM::RFEDA); 1874 break; 1875 case ARM::LDMDA_UPD: 1876 Inst.setOpcode(ARM::RFEDA_UPD); 1877 break; 1878 case ARM::LDMDB: 1879 Inst.setOpcode(ARM::RFEDB); 1880 break; 1881 case ARM::LDMDB_UPD: 1882 Inst.setOpcode(ARM::RFEDB_UPD); 1883 break; 1884 case ARM::LDMIA: 1885 Inst.setOpcode(ARM::RFEIA); 1886 break; 1887 case ARM::LDMIA_UPD: 1888 Inst.setOpcode(ARM::RFEIA_UPD); 1889 break; 1890 case ARM::LDMIB: 1891 Inst.setOpcode(ARM::RFEIB); 1892 break; 1893 case ARM::LDMIB_UPD: 1894 Inst.setOpcode(ARM::RFEIB_UPD); 1895 break; 1896 case ARM::STMDA: 1897 Inst.setOpcode(ARM::SRSDA); 1898 break; 1899 case ARM::STMDA_UPD: 1900 Inst.setOpcode(ARM::SRSDA_UPD); 1901 break; 1902 case ARM::STMDB: 1903 Inst.setOpcode(ARM::SRSDB); 1904 break; 1905 case ARM::STMDB_UPD: 1906 Inst.setOpcode(ARM::SRSDB_UPD); 1907 break; 1908 case ARM::STMIA: 1909 Inst.setOpcode(ARM::SRSIA); 1910 break; 1911 case ARM::STMIA_UPD: 1912 Inst.setOpcode(ARM::SRSIA_UPD); 1913 break; 1914 case ARM::STMIB: 1915 Inst.setOpcode(ARM::SRSIB); 1916 break; 1917 case ARM::STMIB_UPD: 1918 Inst.setOpcode(ARM::SRSIB_UPD); 1919 break; 1920 default: 1921 return MCDisassembler::Fail; 1922 } 1923 1924 // For stores (which become SRS's, the only operand is the mode. 1925 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1926 // Check SRS encoding constraints 1927 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1928 fieldFromInstruction(Insn, 20, 1) == 0)) 1929 return MCDisassembler::Fail; 1930 1931 Inst.addOperand( 1932 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 1933 return S; 1934 } 1935 1936 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1937 } 1938 1939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1940 return MCDisassembler::Fail; 1941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1942 return MCDisassembler::Fail; // Tied 1943 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1944 return MCDisassembler::Fail; 1945 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1946 return MCDisassembler::Fail; 1947 1948 return S; 1949 } 1950 1951 // Check for UNPREDICTABLE predicated ESB instruction 1952 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 1953 uint64_t Address, const void *Decoder) { 1954 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1955 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 1956 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 1957 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 1958 1959 DecodeStatus S = MCDisassembler::Success; 1960 1961 Inst.addOperand(MCOperand::createImm(imm8)); 1962 1963 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1964 return MCDisassembler::Fail; 1965 1966 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 1967 // so all predicates should be allowed. 1968 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 1969 S = MCDisassembler::SoftFail; 1970 1971 return S; 1972 } 1973 1974 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1975 uint64_t Address, const void *Decoder) { 1976 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1977 unsigned M = fieldFromInstruction(Insn, 17, 1); 1978 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1979 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1980 1981 DecodeStatus S = MCDisassembler::Success; 1982 1983 // This decoder is called from multiple location that do not check 1984 // the full encoding is valid before they do. 1985 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1986 fieldFromInstruction(Insn, 16, 1) != 0 || 1987 fieldFromInstruction(Insn, 20, 8) != 0x10) 1988 return MCDisassembler::Fail; 1989 1990 // imod == '01' --> UNPREDICTABLE 1991 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1992 // return failure here. The '01' imod value is unprintable, so there's 1993 // nothing useful we could do even if we returned UNPREDICTABLE. 1994 1995 if (imod == 1) return MCDisassembler::Fail; 1996 1997 if (imod && M) { 1998 Inst.setOpcode(ARM::CPS3p); 1999 Inst.addOperand(MCOperand::createImm(imod)); 2000 Inst.addOperand(MCOperand::createImm(iflags)); 2001 Inst.addOperand(MCOperand::createImm(mode)); 2002 } else if (imod && !M) { 2003 Inst.setOpcode(ARM::CPS2p); 2004 Inst.addOperand(MCOperand::createImm(imod)); 2005 Inst.addOperand(MCOperand::createImm(iflags)); 2006 if (mode) S = MCDisassembler::SoftFail; 2007 } else if (!imod && M) { 2008 Inst.setOpcode(ARM::CPS1p); 2009 Inst.addOperand(MCOperand::createImm(mode)); 2010 if (iflags) S = MCDisassembler::SoftFail; 2011 } else { 2012 // imod == '00' && M == '0' --> UNPREDICTABLE 2013 Inst.setOpcode(ARM::CPS1p); 2014 Inst.addOperand(MCOperand::createImm(mode)); 2015 S = MCDisassembler::SoftFail; 2016 } 2017 2018 return S; 2019 } 2020 2021 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2022 uint64_t Address, const void *Decoder) { 2023 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2024 unsigned M = fieldFromInstruction(Insn, 8, 1); 2025 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2026 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2027 2028 DecodeStatus S = MCDisassembler::Success; 2029 2030 // imod == '01' --> UNPREDICTABLE 2031 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2032 // return failure here. The '01' imod value is unprintable, so there's 2033 // nothing useful we could do even if we returned UNPREDICTABLE. 2034 2035 if (imod == 1) return MCDisassembler::Fail; 2036 2037 if (imod && M) { 2038 Inst.setOpcode(ARM::t2CPS3p); 2039 Inst.addOperand(MCOperand::createImm(imod)); 2040 Inst.addOperand(MCOperand::createImm(iflags)); 2041 Inst.addOperand(MCOperand::createImm(mode)); 2042 } else if (imod && !M) { 2043 Inst.setOpcode(ARM::t2CPS2p); 2044 Inst.addOperand(MCOperand::createImm(imod)); 2045 Inst.addOperand(MCOperand::createImm(iflags)); 2046 if (mode) S = MCDisassembler::SoftFail; 2047 } else if (!imod && M) { 2048 Inst.setOpcode(ARM::t2CPS1p); 2049 Inst.addOperand(MCOperand::createImm(mode)); 2050 if (iflags) S = MCDisassembler::SoftFail; 2051 } else { 2052 // imod == '00' && M == '0' --> this is a HINT instruction 2053 int imm = fieldFromInstruction(Insn, 0, 8); 2054 // HINT are defined only for immediate in [0..4] 2055 if(imm > 4) return MCDisassembler::Fail; 2056 Inst.setOpcode(ARM::t2HINT); 2057 Inst.addOperand(MCOperand::createImm(imm)); 2058 } 2059 2060 return S; 2061 } 2062 2063 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2064 uint64_t Address, const void *Decoder) { 2065 DecodeStatus S = MCDisassembler::Success; 2066 2067 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2068 unsigned imm = 0; 2069 2070 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2071 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2072 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2073 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2074 2075 if (Inst.getOpcode() == ARM::t2MOVTi16) 2076 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2077 return MCDisassembler::Fail; 2078 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2079 return MCDisassembler::Fail; 2080 2081 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2082 Inst.addOperand(MCOperand::createImm(imm)); 2083 2084 return S; 2085 } 2086 2087 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2088 uint64_t Address, const void *Decoder) { 2089 DecodeStatus S = MCDisassembler::Success; 2090 2091 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2092 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2093 unsigned imm = 0; 2094 2095 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2096 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2097 2098 if (Inst.getOpcode() == ARM::MOVTi16) 2099 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2100 return MCDisassembler::Fail; 2101 2102 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2103 return MCDisassembler::Fail; 2104 2105 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2106 Inst.addOperand(MCOperand::createImm(imm)); 2107 2108 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2109 return MCDisassembler::Fail; 2110 2111 return S; 2112 } 2113 2114 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2115 uint64_t Address, const void *Decoder) { 2116 DecodeStatus S = MCDisassembler::Success; 2117 2118 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2119 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2120 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2121 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2122 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2123 2124 if (pred == 0xF) 2125 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2126 2127 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2128 return MCDisassembler::Fail; 2129 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2130 return MCDisassembler::Fail; 2131 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2132 return MCDisassembler::Fail; 2133 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2134 return MCDisassembler::Fail; 2135 2136 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2137 return MCDisassembler::Fail; 2138 2139 return S; 2140 } 2141 2142 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2143 uint64_t Address, const void *Decoder) { 2144 DecodeStatus S = MCDisassembler::Success; 2145 2146 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2147 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2148 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2149 2150 if (Pred == 0xF) 2151 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2152 2153 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2154 return MCDisassembler::Fail; 2155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2156 return MCDisassembler::Fail; 2157 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2158 return MCDisassembler::Fail; 2159 2160 return S; 2161 } 2162 2163 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2164 uint64_t Address, const void *Decoder) { 2165 DecodeStatus S = MCDisassembler::Success; 2166 2167 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2168 2169 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2170 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2171 2172 if (!FeatureBits[ARM::HasV8_1aOps] || 2173 !FeatureBits[ARM::HasV8Ops]) 2174 return MCDisassembler::Fail; 2175 2176 // Decoder can be called from DecodeTST, which does not check the full 2177 // encoding is valid. 2178 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2179 fieldFromInstruction(Insn, 4,4) != 0) 2180 return MCDisassembler::Fail; 2181 if (fieldFromInstruction(Insn, 10,10) != 0 || 2182 fieldFromInstruction(Insn, 0,4) != 0) 2183 S = MCDisassembler::SoftFail; 2184 2185 Inst.setOpcode(ARM::SETPAN); 2186 Inst.addOperand(MCOperand::createImm(Imm)); 2187 2188 return S; 2189 } 2190 2191 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2192 uint64_t Address, const void *Decoder) { 2193 DecodeStatus S = MCDisassembler::Success; 2194 2195 unsigned add = fieldFromInstruction(Val, 12, 1); 2196 unsigned imm = fieldFromInstruction(Val, 0, 12); 2197 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2198 2199 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2200 return MCDisassembler::Fail; 2201 2202 if (!add) imm *= -1; 2203 if (imm == 0 && !add) imm = INT32_MIN; 2204 Inst.addOperand(MCOperand::createImm(imm)); 2205 if (Rn == 15) 2206 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2207 2208 return S; 2209 } 2210 2211 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2212 uint64_t Address, const void *Decoder) { 2213 DecodeStatus S = MCDisassembler::Success; 2214 2215 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2216 // U == 1 to add imm, 0 to subtract it. 2217 unsigned U = fieldFromInstruction(Val, 8, 1); 2218 unsigned imm = fieldFromInstruction(Val, 0, 8); 2219 2220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2221 return MCDisassembler::Fail; 2222 2223 if (U) 2224 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2225 else 2226 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2227 2228 return S; 2229 } 2230 2231 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2232 uint64_t Address, const void *Decoder) { 2233 DecodeStatus S = MCDisassembler::Success; 2234 2235 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2236 // U == 1 to add imm, 0 to subtract it. 2237 unsigned U = fieldFromInstruction(Val, 8, 1); 2238 unsigned imm = fieldFromInstruction(Val, 0, 8); 2239 2240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2241 return MCDisassembler::Fail; 2242 2243 if (U) 2244 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2245 else 2246 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2247 2248 return S; 2249 } 2250 2251 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2252 uint64_t Address, const void *Decoder) { 2253 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2254 } 2255 2256 static DecodeStatus 2257 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2258 uint64_t Address, const void *Decoder) { 2259 DecodeStatus Status = MCDisassembler::Success; 2260 2261 // Note the J1 and J2 values are from the encoded instruction. So here 2262 // change them to I1 and I2 values via as documented: 2263 // I1 = NOT(J1 EOR S); 2264 // I2 = NOT(J2 EOR S); 2265 // and build the imm32 with one trailing zero as documented: 2266 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2267 unsigned S = fieldFromInstruction(Insn, 26, 1); 2268 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2269 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2270 unsigned I1 = !(J1 ^ S); 2271 unsigned I2 = !(J2 ^ S); 2272 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2273 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2274 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2275 int imm32 = SignExtend32<25>(tmp << 1); 2276 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2277 true, 4, Inst, Decoder)) 2278 Inst.addOperand(MCOperand::createImm(imm32)); 2279 2280 return Status; 2281 } 2282 2283 static DecodeStatus 2284 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2285 uint64_t Address, const void *Decoder) { 2286 DecodeStatus S = MCDisassembler::Success; 2287 2288 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2289 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2290 2291 if (pred == 0xF) { 2292 Inst.setOpcode(ARM::BLXi); 2293 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2294 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2295 true, 4, Inst, Decoder)) 2296 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2297 return S; 2298 } 2299 2300 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2301 true, 4, Inst, Decoder)) 2302 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2303 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2304 return MCDisassembler::Fail; 2305 2306 return S; 2307 } 2308 2309 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2310 uint64_t Address, const void *Decoder) { 2311 DecodeStatus S = MCDisassembler::Success; 2312 2313 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2314 unsigned align = fieldFromInstruction(Val, 4, 2); 2315 2316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2317 return MCDisassembler::Fail; 2318 if (!align) 2319 Inst.addOperand(MCOperand::createImm(0)); 2320 else 2321 Inst.addOperand(MCOperand::createImm(4 << align)); 2322 2323 return S; 2324 } 2325 2326 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2327 uint64_t Address, const void *Decoder) { 2328 DecodeStatus S = MCDisassembler::Success; 2329 2330 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2331 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2332 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2333 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2334 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2335 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2336 2337 // First output register 2338 switch (Inst.getOpcode()) { 2339 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2340 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2341 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2342 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2343 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2344 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2345 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2346 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2347 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2348 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2349 return MCDisassembler::Fail; 2350 break; 2351 case ARM::VLD2b16: 2352 case ARM::VLD2b32: 2353 case ARM::VLD2b8: 2354 case ARM::VLD2b16wb_fixed: 2355 case ARM::VLD2b16wb_register: 2356 case ARM::VLD2b32wb_fixed: 2357 case ARM::VLD2b32wb_register: 2358 case ARM::VLD2b8wb_fixed: 2359 case ARM::VLD2b8wb_register: 2360 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2361 return MCDisassembler::Fail; 2362 break; 2363 default: 2364 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2365 return MCDisassembler::Fail; 2366 } 2367 2368 // Second output register 2369 switch (Inst.getOpcode()) { 2370 case ARM::VLD3d8: 2371 case ARM::VLD3d16: 2372 case ARM::VLD3d32: 2373 case ARM::VLD3d8_UPD: 2374 case ARM::VLD3d16_UPD: 2375 case ARM::VLD3d32_UPD: 2376 case ARM::VLD4d8: 2377 case ARM::VLD4d16: 2378 case ARM::VLD4d32: 2379 case ARM::VLD4d8_UPD: 2380 case ARM::VLD4d16_UPD: 2381 case ARM::VLD4d32_UPD: 2382 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2383 return MCDisassembler::Fail; 2384 break; 2385 case ARM::VLD3q8: 2386 case ARM::VLD3q16: 2387 case ARM::VLD3q32: 2388 case ARM::VLD3q8_UPD: 2389 case ARM::VLD3q16_UPD: 2390 case ARM::VLD3q32_UPD: 2391 case ARM::VLD4q8: 2392 case ARM::VLD4q16: 2393 case ARM::VLD4q32: 2394 case ARM::VLD4q8_UPD: 2395 case ARM::VLD4q16_UPD: 2396 case ARM::VLD4q32_UPD: 2397 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2398 return MCDisassembler::Fail; 2399 break; 2400 default: 2401 break; 2402 } 2403 2404 // Third output register 2405 switch(Inst.getOpcode()) { 2406 case ARM::VLD3d8: 2407 case ARM::VLD3d16: 2408 case ARM::VLD3d32: 2409 case ARM::VLD3d8_UPD: 2410 case ARM::VLD3d16_UPD: 2411 case ARM::VLD3d32_UPD: 2412 case ARM::VLD4d8: 2413 case ARM::VLD4d16: 2414 case ARM::VLD4d32: 2415 case ARM::VLD4d8_UPD: 2416 case ARM::VLD4d16_UPD: 2417 case ARM::VLD4d32_UPD: 2418 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2419 return MCDisassembler::Fail; 2420 break; 2421 case ARM::VLD3q8: 2422 case ARM::VLD3q16: 2423 case ARM::VLD3q32: 2424 case ARM::VLD3q8_UPD: 2425 case ARM::VLD3q16_UPD: 2426 case ARM::VLD3q32_UPD: 2427 case ARM::VLD4q8: 2428 case ARM::VLD4q16: 2429 case ARM::VLD4q32: 2430 case ARM::VLD4q8_UPD: 2431 case ARM::VLD4q16_UPD: 2432 case ARM::VLD4q32_UPD: 2433 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2434 return MCDisassembler::Fail; 2435 break; 2436 default: 2437 break; 2438 } 2439 2440 // Fourth output register 2441 switch (Inst.getOpcode()) { 2442 case ARM::VLD4d8: 2443 case ARM::VLD4d16: 2444 case ARM::VLD4d32: 2445 case ARM::VLD4d8_UPD: 2446 case ARM::VLD4d16_UPD: 2447 case ARM::VLD4d32_UPD: 2448 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2449 return MCDisassembler::Fail; 2450 break; 2451 case ARM::VLD4q8: 2452 case ARM::VLD4q16: 2453 case ARM::VLD4q32: 2454 case ARM::VLD4q8_UPD: 2455 case ARM::VLD4q16_UPD: 2456 case ARM::VLD4q32_UPD: 2457 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2458 return MCDisassembler::Fail; 2459 break; 2460 default: 2461 break; 2462 } 2463 2464 // Writeback operand 2465 switch (Inst.getOpcode()) { 2466 case ARM::VLD1d8wb_fixed: 2467 case ARM::VLD1d16wb_fixed: 2468 case ARM::VLD1d32wb_fixed: 2469 case ARM::VLD1d64wb_fixed: 2470 case ARM::VLD1d8wb_register: 2471 case ARM::VLD1d16wb_register: 2472 case ARM::VLD1d32wb_register: 2473 case ARM::VLD1d64wb_register: 2474 case ARM::VLD1q8wb_fixed: 2475 case ARM::VLD1q16wb_fixed: 2476 case ARM::VLD1q32wb_fixed: 2477 case ARM::VLD1q64wb_fixed: 2478 case ARM::VLD1q8wb_register: 2479 case ARM::VLD1q16wb_register: 2480 case ARM::VLD1q32wb_register: 2481 case ARM::VLD1q64wb_register: 2482 case ARM::VLD1d8Twb_fixed: 2483 case ARM::VLD1d8Twb_register: 2484 case ARM::VLD1d16Twb_fixed: 2485 case ARM::VLD1d16Twb_register: 2486 case ARM::VLD1d32Twb_fixed: 2487 case ARM::VLD1d32Twb_register: 2488 case ARM::VLD1d64Twb_fixed: 2489 case ARM::VLD1d64Twb_register: 2490 case ARM::VLD1d8Qwb_fixed: 2491 case ARM::VLD1d8Qwb_register: 2492 case ARM::VLD1d16Qwb_fixed: 2493 case ARM::VLD1d16Qwb_register: 2494 case ARM::VLD1d32Qwb_fixed: 2495 case ARM::VLD1d32Qwb_register: 2496 case ARM::VLD1d64Qwb_fixed: 2497 case ARM::VLD1d64Qwb_register: 2498 case ARM::VLD2d8wb_fixed: 2499 case ARM::VLD2d16wb_fixed: 2500 case ARM::VLD2d32wb_fixed: 2501 case ARM::VLD2q8wb_fixed: 2502 case ARM::VLD2q16wb_fixed: 2503 case ARM::VLD2q32wb_fixed: 2504 case ARM::VLD2d8wb_register: 2505 case ARM::VLD2d16wb_register: 2506 case ARM::VLD2d32wb_register: 2507 case ARM::VLD2q8wb_register: 2508 case ARM::VLD2q16wb_register: 2509 case ARM::VLD2q32wb_register: 2510 case ARM::VLD2b8wb_fixed: 2511 case ARM::VLD2b16wb_fixed: 2512 case ARM::VLD2b32wb_fixed: 2513 case ARM::VLD2b8wb_register: 2514 case ARM::VLD2b16wb_register: 2515 case ARM::VLD2b32wb_register: 2516 Inst.addOperand(MCOperand::createImm(0)); 2517 break; 2518 case ARM::VLD3d8_UPD: 2519 case ARM::VLD3d16_UPD: 2520 case ARM::VLD3d32_UPD: 2521 case ARM::VLD3q8_UPD: 2522 case ARM::VLD3q16_UPD: 2523 case ARM::VLD3q32_UPD: 2524 case ARM::VLD4d8_UPD: 2525 case ARM::VLD4d16_UPD: 2526 case ARM::VLD4d32_UPD: 2527 case ARM::VLD4q8_UPD: 2528 case ARM::VLD4q16_UPD: 2529 case ARM::VLD4q32_UPD: 2530 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2531 return MCDisassembler::Fail; 2532 break; 2533 default: 2534 break; 2535 } 2536 2537 // AddrMode6 Base (register+alignment) 2538 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2539 return MCDisassembler::Fail; 2540 2541 // AddrMode6 Offset (register) 2542 switch (Inst.getOpcode()) { 2543 default: 2544 // The below have been updated to have explicit am6offset split 2545 // between fixed and register offset. For those instructions not 2546 // yet updated, we need to add an additional reg0 operand for the 2547 // fixed variant. 2548 // 2549 // The fixed offset encodes as Rm == 0xd, so we check for that. 2550 if (Rm == 0xd) { 2551 Inst.addOperand(MCOperand::createReg(0)); 2552 break; 2553 } 2554 // Fall through to handle the register offset variant. 2555 LLVM_FALLTHROUGH; 2556 case ARM::VLD1d8wb_fixed: 2557 case ARM::VLD1d16wb_fixed: 2558 case ARM::VLD1d32wb_fixed: 2559 case ARM::VLD1d64wb_fixed: 2560 case ARM::VLD1d8Twb_fixed: 2561 case ARM::VLD1d16Twb_fixed: 2562 case ARM::VLD1d32Twb_fixed: 2563 case ARM::VLD1d64Twb_fixed: 2564 case ARM::VLD1d8Qwb_fixed: 2565 case ARM::VLD1d16Qwb_fixed: 2566 case ARM::VLD1d32Qwb_fixed: 2567 case ARM::VLD1d64Qwb_fixed: 2568 case ARM::VLD1d8wb_register: 2569 case ARM::VLD1d16wb_register: 2570 case ARM::VLD1d32wb_register: 2571 case ARM::VLD1d64wb_register: 2572 case ARM::VLD1q8wb_fixed: 2573 case ARM::VLD1q16wb_fixed: 2574 case ARM::VLD1q32wb_fixed: 2575 case ARM::VLD1q64wb_fixed: 2576 case ARM::VLD1q8wb_register: 2577 case ARM::VLD1q16wb_register: 2578 case ARM::VLD1q32wb_register: 2579 case ARM::VLD1q64wb_register: 2580 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2581 // variant encodes Rm == 0xf. Anything else is a register offset post- 2582 // increment and we need to add the register operand to the instruction. 2583 if (Rm != 0xD && Rm != 0xF && 2584 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2585 return MCDisassembler::Fail; 2586 break; 2587 case ARM::VLD2d8wb_fixed: 2588 case ARM::VLD2d16wb_fixed: 2589 case ARM::VLD2d32wb_fixed: 2590 case ARM::VLD2b8wb_fixed: 2591 case ARM::VLD2b16wb_fixed: 2592 case ARM::VLD2b32wb_fixed: 2593 case ARM::VLD2q8wb_fixed: 2594 case ARM::VLD2q16wb_fixed: 2595 case ARM::VLD2q32wb_fixed: 2596 break; 2597 } 2598 2599 return S; 2600 } 2601 2602 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2603 uint64_t Address, const void *Decoder) { 2604 unsigned type = fieldFromInstruction(Insn, 8, 4); 2605 unsigned align = fieldFromInstruction(Insn, 4, 2); 2606 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2607 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2608 if (type == 10 && align == 3) return MCDisassembler::Fail; 2609 2610 unsigned load = fieldFromInstruction(Insn, 21, 1); 2611 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2612 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2613 } 2614 2615 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2616 uint64_t Address, const void *Decoder) { 2617 unsigned size = fieldFromInstruction(Insn, 6, 2); 2618 if (size == 3) return MCDisassembler::Fail; 2619 2620 unsigned type = fieldFromInstruction(Insn, 8, 4); 2621 unsigned align = fieldFromInstruction(Insn, 4, 2); 2622 if (type == 8 && align == 3) return MCDisassembler::Fail; 2623 if (type == 9 && align == 3) return MCDisassembler::Fail; 2624 2625 unsigned load = fieldFromInstruction(Insn, 21, 1); 2626 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2627 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2628 } 2629 2630 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2631 uint64_t Address, const void *Decoder) { 2632 unsigned size = fieldFromInstruction(Insn, 6, 2); 2633 if (size == 3) return MCDisassembler::Fail; 2634 2635 unsigned align = fieldFromInstruction(Insn, 4, 2); 2636 if (align & 2) return MCDisassembler::Fail; 2637 2638 unsigned load = fieldFromInstruction(Insn, 21, 1); 2639 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2640 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2641 } 2642 2643 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2644 uint64_t Address, const void *Decoder) { 2645 unsigned size = fieldFromInstruction(Insn, 6, 2); 2646 if (size == 3) return MCDisassembler::Fail; 2647 2648 unsigned load = fieldFromInstruction(Insn, 21, 1); 2649 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2650 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2651 } 2652 2653 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2654 uint64_t Address, const void *Decoder) { 2655 DecodeStatus S = MCDisassembler::Success; 2656 2657 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2658 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2659 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2660 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2661 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2662 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2663 2664 // Writeback Operand 2665 switch (Inst.getOpcode()) { 2666 case ARM::VST1d8wb_fixed: 2667 case ARM::VST1d16wb_fixed: 2668 case ARM::VST1d32wb_fixed: 2669 case ARM::VST1d64wb_fixed: 2670 case ARM::VST1d8wb_register: 2671 case ARM::VST1d16wb_register: 2672 case ARM::VST1d32wb_register: 2673 case ARM::VST1d64wb_register: 2674 case ARM::VST1q8wb_fixed: 2675 case ARM::VST1q16wb_fixed: 2676 case ARM::VST1q32wb_fixed: 2677 case ARM::VST1q64wb_fixed: 2678 case ARM::VST1q8wb_register: 2679 case ARM::VST1q16wb_register: 2680 case ARM::VST1q32wb_register: 2681 case ARM::VST1q64wb_register: 2682 case ARM::VST1d8Twb_fixed: 2683 case ARM::VST1d16Twb_fixed: 2684 case ARM::VST1d32Twb_fixed: 2685 case ARM::VST1d64Twb_fixed: 2686 case ARM::VST1d8Twb_register: 2687 case ARM::VST1d16Twb_register: 2688 case ARM::VST1d32Twb_register: 2689 case ARM::VST1d64Twb_register: 2690 case ARM::VST1d8Qwb_fixed: 2691 case ARM::VST1d16Qwb_fixed: 2692 case ARM::VST1d32Qwb_fixed: 2693 case ARM::VST1d64Qwb_fixed: 2694 case ARM::VST1d8Qwb_register: 2695 case ARM::VST1d16Qwb_register: 2696 case ARM::VST1d32Qwb_register: 2697 case ARM::VST1d64Qwb_register: 2698 case ARM::VST2d8wb_fixed: 2699 case ARM::VST2d16wb_fixed: 2700 case ARM::VST2d32wb_fixed: 2701 case ARM::VST2d8wb_register: 2702 case ARM::VST2d16wb_register: 2703 case ARM::VST2d32wb_register: 2704 case ARM::VST2q8wb_fixed: 2705 case ARM::VST2q16wb_fixed: 2706 case ARM::VST2q32wb_fixed: 2707 case ARM::VST2q8wb_register: 2708 case ARM::VST2q16wb_register: 2709 case ARM::VST2q32wb_register: 2710 case ARM::VST2b8wb_fixed: 2711 case ARM::VST2b16wb_fixed: 2712 case ARM::VST2b32wb_fixed: 2713 case ARM::VST2b8wb_register: 2714 case ARM::VST2b16wb_register: 2715 case ARM::VST2b32wb_register: 2716 if (Rm == 0xF) 2717 return MCDisassembler::Fail; 2718 Inst.addOperand(MCOperand::createImm(0)); 2719 break; 2720 case ARM::VST3d8_UPD: 2721 case ARM::VST3d16_UPD: 2722 case ARM::VST3d32_UPD: 2723 case ARM::VST3q8_UPD: 2724 case ARM::VST3q16_UPD: 2725 case ARM::VST3q32_UPD: 2726 case ARM::VST4d8_UPD: 2727 case ARM::VST4d16_UPD: 2728 case ARM::VST4d32_UPD: 2729 case ARM::VST4q8_UPD: 2730 case ARM::VST4q16_UPD: 2731 case ARM::VST4q32_UPD: 2732 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2733 return MCDisassembler::Fail; 2734 break; 2735 default: 2736 break; 2737 } 2738 2739 // AddrMode6 Base (register+alignment) 2740 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2741 return MCDisassembler::Fail; 2742 2743 // AddrMode6 Offset (register) 2744 switch (Inst.getOpcode()) { 2745 default: 2746 if (Rm == 0xD) 2747 Inst.addOperand(MCOperand::createReg(0)); 2748 else if (Rm != 0xF) { 2749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2750 return MCDisassembler::Fail; 2751 } 2752 break; 2753 case ARM::VST1d8wb_fixed: 2754 case ARM::VST1d16wb_fixed: 2755 case ARM::VST1d32wb_fixed: 2756 case ARM::VST1d64wb_fixed: 2757 case ARM::VST1q8wb_fixed: 2758 case ARM::VST1q16wb_fixed: 2759 case ARM::VST1q32wb_fixed: 2760 case ARM::VST1q64wb_fixed: 2761 case ARM::VST1d8Twb_fixed: 2762 case ARM::VST1d16Twb_fixed: 2763 case ARM::VST1d32Twb_fixed: 2764 case ARM::VST1d64Twb_fixed: 2765 case ARM::VST1d8Qwb_fixed: 2766 case ARM::VST1d16Qwb_fixed: 2767 case ARM::VST1d32Qwb_fixed: 2768 case ARM::VST1d64Qwb_fixed: 2769 case ARM::VST2d8wb_fixed: 2770 case ARM::VST2d16wb_fixed: 2771 case ARM::VST2d32wb_fixed: 2772 case ARM::VST2q8wb_fixed: 2773 case ARM::VST2q16wb_fixed: 2774 case ARM::VST2q32wb_fixed: 2775 case ARM::VST2b8wb_fixed: 2776 case ARM::VST2b16wb_fixed: 2777 case ARM::VST2b32wb_fixed: 2778 break; 2779 } 2780 2781 // First input register 2782 switch (Inst.getOpcode()) { 2783 case ARM::VST1q16: 2784 case ARM::VST1q32: 2785 case ARM::VST1q64: 2786 case ARM::VST1q8: 2787 case ARM::VST1q16wb_fixed: 2788 case ARM::VST1q16wb_register: 2789 case ARM::VST1q32wb_fixed: 2790 case ARM::VST1q32wb_register: 2791 case ARM::VST1q64wb_fixed: 2792 case ARM::VST1q64wb_register: 2793 case ARM::VST1q8wb_fixed: 2794 case ARM::VST1q8wb_register: 2795 case ARM::VST2d16: 2796 case ARM::VST2d32: 2797 case ARM::VST2d8: 2798 case ARM::VST2d16wb_fixed: 2799 case ARM::VST2d16wb_register: 2800 case ARM::VST2d32wb_fixed: 2801 case ARM::VST2d32wb_register: 2802 case ARM::VST2d8wb_fixed: 2803 case ARM::VST2d8wb_register: 2804 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2805 return MCDisassembler::Fail; 2806 break; 2807 case ARM::VST2b16: 2808 case ARM::VST2b32: 2809 case ARM::VST2b8: 2810 case ARM::VST2b16wb_fixed: 2811 case ARM::VST2b16wb_register: 2812 case ARM::VST2b32wb_fixed: 2813 case ARM::VST2b32wb_register: 2814 case ARM::VST2b8wb_fixed: 2815 case ARM::VST2b8wb_register: 2816 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2817 return MCDisassembler::Fail; 2818 break; 2819 default: 2820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2821 return MCDisassembler::Fail; 2822 } 2823 2824 // Second input register 2825 switch (Inst.getOpcode()) { 2826 case ARM::VST3d8: 2827 case ARM::VST3d16: 2828 case ARM::VST3d32: 2829 case ARM::VST3d8_UPD: 2830 case ARM::VST3d16_UPD: 2831 case ARM::VST3d32_UPD: 2832 case ARM::VST4d8: 2833 case ARM::VST4d16: 2834 case ARM::VST4d32: 2835 case ARM::VST4d8_UPD: 2836 case ARM::VST4d16_UPD: 2837 case ARM::VST4d32_UPD: 2838 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2839 return MCDisassembler::Fail; 2840 break; 2841 case ARM::VST3q8: 2842 case ARM::VST3q16: 2843 case ARM::VST3q32: 2844 case ARM::VST3q8_UPD: 2845 case ARM::VST3q16_UPD: 2846 case ARM::VST3q32_UPD: 2847 case ARM::VST4q8: 2848 case ARM::VST4q16: 2849 case ARM::VST4q32: 2850 case ARM::VST4q8_UPD: 2851 case ARM::VST4q16_UPD: 2852 case ARM::VST4q32_UPD: 2853 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2854 return MCDisassembler::Fail; 2855 break; 2856 default: 2857 break; 2858 } 2859 2860 // Third input register 2861 switch (Inst.getOpcode()) { 2862 case ARM::VST3d8: 2863 case ARM::VST3d16: 2864 case ARM::VST3d32: 2865 case ARM::VST3d8_UPD: 2866 case ARM::VST3d16_UPD: 2867 case ARM::VST3d32_UPD: 2868 case ARM::VST4d8: 2869 case ARM::VST4d16: 2870 case ARM::VST4d32: 2871 case ARM::VST4d8_UPD: 2872 case ARM::VST4d16_UPD: 2873 case ARM::VST4d32_UPD: 2874 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 break; 2877 case ARM::VST3q8: 2878 case ARM::VST3q16: 2879 case ARM::VST3q32: 2880 case ARM::VST3q8_UPD: 2881 case ARM::VST3q16_UPD: 2882 case ARM::VST3q32_UPD: 2883 case ARM::VST4q8: 2884 case ARM::VST4q16: 2885 case ARM::VST4q32: 2886 case ARM::VST4q8_UPD: 2887 case ARM::VST4q16_UPD: 2888 case ARM::VST4q32_UPD: 2889 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2890 return MCDisassembler::Fail; 2891 break; 2892 default: 2893 break; 2894 } 2895 2896 // Fourth input register 2897 switch (Inst.getOpcode()) { 2898 case ARM::VST4d8: 2899 case ARM::VST4d16: 2900 case ARM::VST4d32: 2901 case ARM::VST4d8_UPD: 2902 case ARM::VST4d16_UPD: 2903 case ARM::VST4d32_UPD: 2904 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2905 return MCDisassembler::Fail; 2906 break; 2907 case ARM::VST4q8: 2908 case ARM::VST4q16: 2909 case ARM::VST4q32: 2910 case ARM::VST4q8_UPD: 2911 case ARM::VST4q16_UPD: 2912 case ARM::VST4q32_UPD: 2913 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2914 return MCDisassembler::Fail; 2915 break; 2916 default: 2917 break; 2918 } 2919 2920 return S; 2921 } 2922 2923 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2924 uint64_t Address, const void *Decoder) { 2925 DecodeStatus S = MCDisassembler::Success; 2926 2927 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2928 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2929 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2930 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2931 unsigned align = fieldFromInstruction(Insn, 4, 1); 2932 unsigned size = fieldFromInstruction(Insn, 6, 2); 2933 2934 if (size == 0 && align == 1) 2935 return MCDisassembler::Fail; 2936 align *= (1 << size); 2937 2938 switch (Inst.getOpcode()) { 2939 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2940 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2941 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2942 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2943 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2944 return MCDisassembler::Fail; 2945 break; 2946 default: 2947 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2948 return MCDisassembler::Fail; 2949 break; 2950 } 2951 if (Rm != 0xF) { 2952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2953 return MCDisassembler::Fail; 2954 } 2955 2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 Inst.addOperand(MCOperand::createImm(align)); 2959 2960 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2961 // variant encodes Rm == 0xf. Anything else is a register offset post- 2962 // increment and we need to add the register operand to the instruction. 2963 if (Rm != 0xD && Rm != 0xF && 2964 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2965 return MCDisassembler::Fail; 2966 2967 return S; 2968 } 2969 2970 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2971 uint64_t Address, const void *Decoder) { 2972 DecodeStatus S = MCDisassembler::Success; 2973 2974 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2975 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2976 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2977 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2978 unsigned align = fieldFromInstruction(Insn, 4, 1); 2979 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2980 align *= 2*size; 2981 2982 switch (Inst.getOpcode()) { 2983 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2984 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2985 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2986 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2987 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2988 return MCDisassembler::Fail; 2989 break; 2990 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2991 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2992 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2993 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2994 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2995 return MCDisassembler::Fail; 2996 break; 2997 default: 2998 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2999 return MCDisassembler::Fail; 3000 break; 3001 } 3002 3003 if (Rm != 0xF) 3004 Inst.addOperand(MCOperand::createImm(0)); 3005 3006 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3007 return MCDisassembler::Fail; 3008 Inst.addOperand(MCOperand::createImm(align)); 3009 3010 if (Rm != 0xD && Rm != 0xF) { 3011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3012 return MCDisassembler::Fail; 3013 } 3014 3015 return S; 3016 } 3017 3018 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3019 uint64_t Address, const void *Decoder) { 3020 DecodeStatus S = MCDisassembler::Success; 3021 3022 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3023 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3024 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3025 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3026 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3027 3028 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3029 return MCDisassembler::Fail; 3030 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3031 return MCDisassembler::Fail; 3032 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3033 return MCDisassembler::Fail; 3034 if (Rm != 0xF) { 3035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3036 return MCDisassembler::Fail; 3037 } 3038 3039 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3040 return MCDisassembler::Fail; 3041 Inst.addOperand(MCOperand::createImm(0)); 3042 3043 if (Rm == 0xD) 3044 Inst.addOperand(MCOperand::createReg(0)); 3045 else if (Rm != 0xF) { 3046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3047 return MCDisassembler::Fail; 3048 } 3049 3050 return S; 3051 } 3052 3053 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3054 uint64_t Address, const void *Decoder) { 3055 DecodeStatus S = MCDisassembler::Success; 3056 3057 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3058 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3059 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3060 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3061 unsigned size = fieldFromInstruction(Insn, 6, 2); 3062 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3063 unsigned align = fieldFromInstruction(Insn, 4, 1); 3064 3065 if (size == 0x3) { 3066 if (align == 0) 3067 return MCDisassembler::Fail; 3068 align = 16; 3069 } else { 3070 if (size == 2) { 3071 align *= 8; 3072 } else { 3073 size = 1 << size; 3074 align *= 4*size; 3075 } 3076 } 3077 3078 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3079 return MCDisassembler::Fail; 3080 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3081 return MCDisassembler::Fail; 3082 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3083 return MCDisassembler::Fail; 3084 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3085 return MCDisassembler::Fail; 3086 if (Rm != 0xF) { 3087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 } 3090 3091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3092 return MCDisassembler::Fail; 3093 Inst.addOperand(MCOperand::createImm(align)); 3094 3095 if (Rm == 0xD) 3096 Inst.addOperand(MCOperand::createReg(0)); 3097 else if (Rm != 0xF) { 3098 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3099 return MCDisassembler::Fail; 3100 } 3101 3102 return S; 3103 } 3104 3105 static DecodeStatus 3106 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3107 uint64_t Address, const void *Decoder) { 3108 DecodeStatus S = MCDisassembler::Success; 3109 3110 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3111 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3112 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3113 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3114 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3115 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3116 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3117 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3118 3119 if (Q) { 3120 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3121 return MCDisassembler::Fail; 3122 } else { 3123 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3124 return MCDisassembler::Fail; 3125 } 3126 3127 Inst.addOperand(MCOperand::createImm(imm)); 3128 3129 switch (Inst.getOpcode()) { 3130 case ARM::VORRiv4i16: 3131 case ARM::VORRiv2i32: 3132 case ARM::VBICiv4i16: 3133 case ARM::VBICiv2i32: 3134 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3135 return MCDisassembler::Fail; 3136 break; 3137 case ARM::VORRiv8i16: 3138 case ARM::VORRiv4i32: 3139 case ARM::VBICiv8i16: 3140 case ARM::VBICiv4i32: 3141 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3142 return MCDisassembler::Fail; 3143 break; 3144 default: 3145 break; 3146 } 3147 3148 return S; 3149 } 3150 3151 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3152 uint64_t Address, const void *Decoder) { 3153 DecodeStatus S = MCDisassembler::Success; 3154 3155 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3156 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3157 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3158 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3159 unsigned size = fieldFromInstruction(Insn, 18, 2); 3160 3161 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3162 return MCDisassembler::Fail; 3163 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3164 return MCDisassembler::Fail; 3165 Inst.addOperand(MCOperand::createImm(8 << size)); 3166 3167 return S; 3168 } 3169 3170 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3171 uint64_t Address, const void *Decoder) { 3172 Inst.addOperand(MCOperand::createImm(8 - Val)); 3173 return MCDisassembler::Success; 3174 } 3175 3176 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3177 uint64_t Address, const void *Decoder) { 3178 Inst.addOperand(MCOperand::createImm(16 - Val)); 3179 return MCDisassembler::Success; 3180 } 3181 3182 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3183 uint64_t Address, const void *Decoder) { 3184 Inst.addOperand(MCOperand::createImm(32 - Val)); 3185 return MCDisassembler::Success; 3186 } 3187 3188 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3189 uint64_t Address, const void *Decoder) { 3190 Inst.addOperand(MCOperand::createImm(64 - Val)); 3191 return MCDisassembler::Success; 3192 } 3193 3194 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3195 uint64_t Address, const void *Decoder) { 3196 DecodeStatus S = MCDisassembler::Success; 3197 3198 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3199 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3200 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3201 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3202 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3203 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3204 unsigned op = fieldFromInstruction(Insn, 6, 1); 3205 3206 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3207 return MCDisassembler::Fail; 3208 if (op) { 3209 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3210 return MCDisassembler::Fail; // Writeback 3211 } 3212 3213 switch (Inst.getOpcode()) { 3214 case ARM::VTBL2: 3215 case ARM::VTBX2: 3216 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3217 return MCDisassembler::Fail; 3218 break; 3219 default: 3220 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3221 return MCDisassembler::Fail; 3222 } 3223 3224 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3225 return MCDisassembler::Fail; 3226 3227 return S; 3228 } 3229 3230 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3231 uint64_t Address, const void *Decoder) { 3232 DecodeStatus S = MCDisassembler::Success; 3233 3234 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3235 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3236 3237 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3238 return MCDisassembler::Fail; 3239 3240 switch(Inst.getOpcode()) { 3241 default: 3242 return MCDisassembler::Fail; 3243 case ARM::tADR: 3244 break; // tADR does not explicitly represent the PC as an operand. 3245 case ARM::tADDrSPi: 3246 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3247 break; 3248 } 3249 3250 Inst.addOperand(MCOperand::createImm(imm)); 3251 return S; 3252 } 3253 3254 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3255 uint64_t Address, const void *Decoder) { 3256 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3257 true, 2, Inst, Decoder)) 3258 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3259 return MCDisassembler::Success; 3260 } 3261 3262 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3263 uint64_t Address, const void *Decoder) { 3264 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3265 true, 4, Inst, Decoder)) 3266 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3267 return MCDisassembler::Success; 3268 } 3269 3270 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3271 uint64_t Address, const void *Decoder) { 3272 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3273 true, 2, Inst, Decoder)) 3274 Inst.addOperand(MCOperand::createImm(Val << 1)); 3275 return MCDisassembler::Success; 3276 } 3277 3278 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3279 uint64_t Address, const void *Decoder) { 3280 DecodeStatus S = MCDisassembler::Success; 3281 3282 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3283 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3284 3285 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3286 return MCDisassembler::Fail; 3287 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3288 return MCDisassembler::Fail; 3289 3290 return S; 3291 } 3292 3293 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3294 uint64_t Address, const void *Decoder) { 3295 DecodeStatus S = MCDisassembler::Success; 3296 3297 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3298 unsigned imm = fieldFromInstruction(Val, 3, 5); 3299 3300 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3301 return MCDisassembler::Fail; 3302 Inst.addOperand(MCOperand::createImm(imm)); 3303 3304 return S; 3305 } 3306 3307 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3308 uint64_t Address, const void *Decoder) { 3309 unsigned imm = Val << 2; 3310 3311 Inst.addOperand(MCOperand::createImm(imm)); 3312 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3313 3314 return MCDisassembler::Success; 3315 } 3316 3317 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3318 uint64_t Address, const void *Decoder) { 3319 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3320 Inst.addOperand(MCOperand::createImm(Val)); 3321 3322 return MCDisassembler::Success; 3323 } 3324 3325 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3326 uint64_t Address, const void *Decoder) { 3327 DecodeStatus S = MCDisassembler::Success; 3328 3329 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3330 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3331 unsigned imm = fieldFromInstruction(Val, 0, 2); 3332 3333 // Thumb stores cannot use PC as dest register. 3334 switch (Inst.getOpcode()) { 3335 case ARM::t2STRHs: 3336 case ARM::t2STRBs: 3337 case ARM::t2STRs: 3338 if (Rn == 15) 3339 return MCDisassembler::Fail; 3340 break; 3341 default: 3342 break; 3343 } 3344 3345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3346 return MCDisassembler::Fail; 3347 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3348 return MCDisassembler::Fail; 3349 Inst.addOperand(MCOperand::createImm(imm)); 3350 3351 return S; 3352 } 3353 3354 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3355 uint64_t Address, const void *Decoder) { 3356 DecodeStatus S = MCDisassembler::Success; 3357 3358 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3359 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3360 3361 const FeatureBitset &featureBits = 3362 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3363 3364 bool hasMP = featureBits[ARM::FeatureMP]; 3365 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3366 3367 if (Rn == 15) { 3368 switch (Inst.getOpcode()) { 3369 case ARM::t2LDRBs: 3370 Inst.setOpcode(ARM::t2LDRBpci); 3371 break; 3372 case ARM::t2LDRHs: 3373 Inst.setOpcode(ARM::t2LDRHpci); 3374 break; 3375 case ARM::t2LDRSHs: 3376 Inst.setOpcode(ARM::t2LDRSHpci); 3377 break; 3378 case ARM::t2LDRSBs: 3379 Inst.setOpcode(ARM::t2LDRSBpci); 3380 break; 3381 case ARM::t2LDRs: 3382 Inst.setOpcode(ARM::t2LDRpci); 3383 break; 3384 case ARM::t2PLDs: 3385 Inst.setOpcode(ARM::t2PLDpci); 3386 break; 3387 case ARM::t2PLIs: 3388 Inst.setOpcode(ARM::t2PLIpci); 3389 break; 3390 default: 3391 return MCDisassembler::Fail; 3392 } 3393 3394 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3395 } 3396 3397 if (Rt == 15) { 3398 switch (Inst.getOpcode()) { 3399 case ARM::t2LDRSHs: 3400 return MCDisassembler::Fail; 3401 case ARM::t2LDRHs: 3402 Inst.setOpcode(ARM::t2PLDWs); 3403 break; 3404 case ARM::t2LDRSBs: 3405 Inst.setOpcode(ARM::t2PLIs); 3406 break; 3407 default: 3408 break; 3409 } 3410 } 3411 3412 switch (Inst.getOpcode()) { 3413 case ARM::t2PLDs: 3414 break; 3415 case ARM::t2PLIs: 3416 if (!hasV7Ops) 3417 return MCDisassembler::Fail; 3418 break; 3419 case ARM::t2PLDWs: 3420 if (!hasV7Ops || !hasMP) 3421 return MCDisassembler::Fail; 3422 break; 3423 default: 3424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3425 return MCDisassembler::Fail; 3426 } 3427 3428 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3429 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3430 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3431 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3432 return MCDisassembler::Fail; 3433 3434 return S; 3435 } 3436 3437 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3438 uint64_t Address, const void* Decoder) { 3439 DecodeStatus S = MCDisassembler::Success; 3440 3441 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3442 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3443 unsigned U = fieldFromInstruction(Insn, 9, 1); 3444 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3445 imm |= (U << 8); 3446 imm |= (Rn << 9); 3447 unsigned add = fieldFromInstruction(Insn, 9, 1); 3448 3449 const FeatureBitset &featureBits = 3450 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3451 3452 bool hasMP = featureBits[ARM::FeatureMP]; 3453 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3454 3455 if (Rn == 15) { 3456 switch (Inst.getOpcode()) { 3457 case ARM::t2LDRi8: 3458 Inst.setOpcode(ARM::t2LDRpci); 3459 break; 3460 case ARM::t2LDRBi8: 3461 Inst.setOpcode(ARM::t2LDRBpci); 3462 break; 3463 case ARM::t2LDRSBi8: 3464 Inst.setOpcode(ARM::t2LDRSBpci); 3465 break; 3466 case ARM::t2LDRHi8: 3467 Inst.setOpcode(ARM::t2LDRHpci); 3468 break; 3469 case ARM::t2LDRSHi8: 3470 Inst.setOpcode(ARM::t2LDRSHpci); 3471 break; 3472 case ARM::t2PLDi8: 3473 Inst.setOpcode(ARM::t2PLDpci); 3474 break; 3475 case ARM::t2PLIi8: 3476 Inst.setOpcode(ARM::t2PLIpci); 3477 break; 3478 default: 3479 return MCDisassembler::Fail; 3480 } 3481 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3482 } 3483 3484 if (Rt == 15) { 3485 switch (Inst.getOpcode()) { 3486 case ARM::t2LDRSHi8: 3487 return MCDisassembler::Fail; 3488 case ARM::t2LDRHi8: 3489 if (!add) 3490 Inst.setOpcode(ARM::t2PLDWi8); 3491 break; 3492 case ARM::t2LDRSBi8: 3493 Inst.setOpcode(ARM::t2PLIi8); 3494 break; 3495 default: 3496 break; 3497 } 3498 } 3499 3500 switch (Inst.getOpcode()) { 3501 case ARM::t2PLDi8: 3502 break; 3503 case ARM::t2PLIi8: 3504 if (!hasV7Ops) 3505 return MCDisassembler::Fail; 3506 break; 3507 case ARM::t2PLDWi8: 3508 if (!hasV7Ops || !hasMP) 3509 return MCDisassembler::Fail; 3510 break; 3511 default: 3512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3513 return MCDisassembler::Fail; 3514 } 3515 3516 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3517 return MCDisassembler::Fail; 3518 return S; 3519 } 3520 3521 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3522 uint64_t Address, const void* Decoder) { 3523 DecodeStatus S = MCDisassembler::Success; 3524 3525 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3526 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3527 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3528 imm |= (Rn << 13); 3529 3530 const FeatureBitset &featureBits = 3531 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3532 3533 bool hasMP = featureBits[ARM::FeatureMP]; 3534 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3535 3536 if (Rn == 15) { 3537 switch (Inst.getOpcode()) { 3538 case ARM::t2LDRi12: 3539 Inst.setOpcode(ARM::t2LDRpci); 3540 break; 3541 case ARM::t2LDRHi12: 3542 Inst.setOpcode(ARM::t2LDRHpci); 3543 break; 3544 case ARM::t2LDRSHi12: 3545 Inst.setOpcode(ARM::t2LDRSHpci); 3546 break; 3547 case ARM::t2LDRBi12: 3548 Inst.setOpcode(ARM::t2LDRBpci); 3549 break; 3550 case ARM::t2LDRSBi12: 3551 Inst.setOpcode(ARM::t2LDRSBpci); 3552 break; 3553 case ARM::t2PLDi12: 3554 Inst.setOpcode(ARM::t2PLDpci); 3555 break; 3556 case ARM::t2PLIi12: 3557 Inst.setOpcode(ARM::t2PLIpci); 3558 break; 3559 default: 3560 return MCDisassembler::Fail; 3561 } 3562 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3563 } 3564 3565 if (Rt == 15) { 3566 switch (Inst.getOpcode()) { 3567 case ARM::t2LDRSHi12: 3568 return MCDisassembler::Fail; 3569 case ARM::t2LDRHi12: 3570 Inst.setOpcode(ARM::t2PLDWi12); 3571 break; 3572 case ARM::t2LDRSBi12: 3573 Inst.setOpcode(ARM::t2PLIi12); 3574 break; 3575 default: 3576 break; 3577 } 3578 } 3579 3580 switch (Inst.getOpcode()) { 3581 case ARM::t2PLDi12: 3582 break; 3583 case ARM::t2PLIi12: 3584 if (!hasV7Ops) 3585 return MCDisassembler::Fail; 3586 break; 3587 case ARM::t2PLDWi12: 3588 if (!hasV7Ops || !hasMP) 3589 return MCDisassembler::Fail; 3590 break; 3591 default: 3592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3593 return MCDisassembler::Fail; 3594 } 3595 3596 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3597 return MCDisassembler::Fail; 3598 return S; 3599 } 3600 3601 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3602 uint64_t Address, const void* Decoder) { 3603 DecodeStatus S = MCDisassembler::Success; 3604 3605 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3606 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3607 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3608 imm |= (Rn << 9); 3609 3610 if (Rn == 15) { 3611 switch (Inst.getOpcode()) { 3612 case ARM::t2LDRT: 3613 Inst.setOpcode(ARM::t2LDRpci); 3614 break; 3615 case ARM::t2LDRBT: 3616 Inst.setOpcode(ARM::t2LDRBpci); 3617 break; 3618 case ARM::t2LDRHT: 3619 Inst.setOpcode(ARM::t2LDRHpci); 3620 break; 3621 case ARM::t2LDRSBT: 3622 Inst.setOpcode(ARM::t2LDRSBpci); 3623 break; 3624 case ARM::t2LDRSHT: 3625 Inst.setOpcode(ARM::t2LDRSHpci); 3626 break; 3627 default: 3628 return MCDisassembler::Fail; 3629 } 3630 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3631 } 3632 3633 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 return S; 3638 } 3639 3640 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3641 uint64_t Address, const void* Decoder) { 3642 DecodeStatus S = MCDisassembler::Success; 3643 3644 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3645 unsigned U = fieldFromInstruction(Insn, 23, 1); 3646 int imm = fieldFromInstruction(Insn, 0, 12); 3647 3648 const FeatureBitset &featureBits = 3649 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3650 3651 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3652 3653 if (Rt == 15) { 3654 switch (Inst.getOpcode()) { 3655 case ARM::t2LDRBpci: 3656 case ARM::t2LDRHpci: 3657 Inst.setOpcode(ARM::t2PLDpci); 3658 break; 3659 case ARM::t2LDRSBpci: 3660 Inst.setOpcode(ARM::t2PLIpci); 3661 break; 3662 case ARM::t2LDRSHpci: 3663 return MCDisassembler::Fail; 3664 default: 3665 break; 3666 } 3667 } 3668 3669 switch(Inst.getOpcode()) { 3670 case ARM::t2PLDpci: 3671 break; 3672 case ARM::t2PLIpci: 3673 if (!hasV7Ops) 3674 return MCDisassembler::Fail; 3675 break; 3676 default: 3677 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3678 return MCDisassembler::Fail; 3679 } 3680 3681 if (!U) { 3682 // Special case for #-0. 3683 if (imm == 0) 3684 imm = INT32_MIN; 3685 else 3686 imm = -imm; 3687 } 3688 Inst.addOperand(MCOperand::createImm(imm)); 3689 3690 return S; 3691 } 3692 3693 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3694 uint64_t Address, const void *Decoder) { 3695 if (Val == 0) 3696 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3697 else { 3698 int imm = Val & 0xFF; 3699 3700 if (!(Val & 0x100)) imm *= -1; 3701 Inst.addOperand(MCOperand::createImm(imm * 4)); 3702 } 3703 3704 return MCDisassembler::Success; 3705 } 3706 3707 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3708 uint64_t Address, const void *Decoder) { 3709 DecodeStatus S = MCDisassembler::Success; 3710 3711 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3712 unsigned imm = fieldFromInstruction(Val, 0, 9); 3713 3714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3715 return MCDisassembler::Fail; 3716 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3717 return MCDisassembler::Fail; 3718 3719 return S; 3720 } 3721 3722 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3723 uint64_t Address, const void *Decoder) { 3724 DecodeStatus S = MCDisassembler::Success; 3725 3726 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3727 unsigned imm = fieldFromInstruction(Val, 0, 8); 3728 3729 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3730 return MCDisassembler::Fail; 3731 3732 Inst.addOperand(MCOperand::createImm(imm)); 3733 3734 return S; 3735 } 3736 3737 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3738 uint64_t Address, const void *Decoder) { 3739 int imm = Val & 0xFF; 3740 if (Val == 0) 3741 imm = INT32_MIN; 3742 else if (!(Val & 0x100)) 3743 imm *= -1; 3744 Inst.addOperand(MCOperand::createImm(imm)); 3745 3746 return MCDisassembler::Success; 3747 } 3748 3749 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3750 uint64_t Address, const void *Decoder) { 3751 DecodeStatus S = MCDisassembler::Success; 3752 3753 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3754 unsigned imm = fieldFromInstruction(Val, 0, 9); 3755 3756 // Thumb stores cannot use PC as dest register. 3757 switch (Inst.getOpcode()) { 3758 case ARM::t2STRT: 3759 case ARM::t2STRBT: 3760 case ARM::t2STRHT: 3761 case ARM::t2STRi8: 3762 case ARM::t2STRHi8: 3763 case ARM::t2STRBi8: 3764 if (Rn == 15) 3765 return MCDisassembler::Fail; 3766 break; 3767 default: 3768 break; 3769 } 3770 3771 // Some instructions always use an additive offset. 3772 switch (Inst.getOpcode()) { 3773 case ARM::t2LDRT: 3774 case ARM::t2LDRBT: 3775 case ARM::t2LDRHT: 3776 case ARM::t2LDRSBT: 3777 case ARM::t2LDRSHT: 3778 case ARM::t2STRT: 3779 case ARM::t2STRBT: 3780 case ARM::t2STRHT: 3781 imm |= 0x100; 3782 break; 3783 default: 3784 break; 3785 } 3786 3787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3788 return MCDisassembler::Fail; 3789 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3790 return MCDisassembler::Fail; 3791 3792 return S; 3793 } 3794 3795 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3796 uint64_t Address, const void *Decoder) { 3797 DecodeStatus S = MCDisassembler::Success; 3798 3799 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3800 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3801 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3802 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3803 addr |= Rn << 9; 3804 unsigned load = fieldFromInstruction(Insn, 20, 1); 3805 3806 if (Rn == 15) { 3807 switch (Inst.getOpcode()) { 3808 case ARM::t2LDR_PRE: 3809 case ARM::t2LDR_POST: 3810 Inst.setOpcode(ARM::t2LDRpci); 3811 break; 3812 case ARM::t2LDRB_PRE: 3813 case ARM::t2LDRB_POST: 3814 Inst.setOpcode(ARM::t2LDRBpci); 3815 break; 3816 case ARM::t2LDRH_PRE: 3817 case ARM::t2LDRH_POST: 3818 Inst.setOpcode(ARM::t2LDRHpci); 3819 break; 3820 case ARM::t2LDRSB_PRE: 3821 case ARM::t2LDRSB_POST: 3822 if (Rt == 15) 3823 Inst.setOpcode(ARM::t2PLIpci); 3824 else 3825 Inst.setOpcode(ARM::t2LDRSBpci); 3826 break; 3827 case ARM::t2LDRSH_PRE: 3828 case ARM::t2LDRSH_POST: 3829 Inst.setOpcode(ARM::t2LDRSHpci); 3830 break; 3831 default: 3832 return MCDisassembler::Fail; 3833 } 3834 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3835 } 3836 3837 if (!load) { 3838 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3839 return MCDisassembler::Fail; 3840 } 3841 3842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3843 return MCDisassembler::Fail; 3844 3845 if (load) { 3846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3847 return MCDisassembler::Fail; 3848 } 3849 3850 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3851 return MCDisassembler::Fail; 3852 3853 return S; 3854 } 3855 3856 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3857 uint64_t Address, const void *Decoder) { 3858 DecodeStatus S = MCDisassembler::Success; 3859 3860 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3861 unsigned imm = fieldFromInstruction(Val, 0, 12); 3862 3863 // Thumb stores cannot use PC as dest register. 3864 switch (Inst.getOpcode()) { 3865 case ARM::t2STRi12: 3866 case ARM::t2STRBi12: 3867 case ARM::t2STRHi12: 3868 if (Rn == 15) 3869 return MCDisassembler::Fail; 3870 break; 3871 default: 3872 break; 3873 } 3874 3875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3876 return MCDisassembler::Fail; 3877 Inst.addOperand(MCOperand::createImm(imm)); 3878 3879 return S; 3880 } 3881 3882 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3883 uint64_t Address, const void *Decoder) { 3884 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3885 3886 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3887 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3888 Inst.addOperand(MCOperand::createImm(imm)); 3889 3890 return MCDisassembler::Success; 3891 } 3892 3893 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3894 uint64_t Address, const void *Decoder) { 3895 DecodeStatus S = MCDisassembler::Success; 3896 3897 if (Inst.getOpcode() == ARM::tADDrSP) { 3898 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3899 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3900 3901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3902 return MCDisassembler::Fail; 3903 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3905 return MCDisassembler::Fail; 3906 } else if (Inst.getOpcode() == ARM::tADDspr) { 3907 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3908 3909 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3910 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3911 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3912 return MCDisassembler::Fail; 3913 } 3914 3915 return S; 3916 } 3917 3918 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3919 uint64_t Address, const void *Decoder) { 3920 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3921 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3922 3923 Inst.addOperand(MCOperand::createImm(imod)); 3924 Inst.addOperand(MCOperand::createImm(flags)); 3925 3926 return MCDisassembler::Success; 3927 } 3928 3929 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3930 uint64_t Address, const void *Decoder) { 3931 DecodeStatus S = MCDisassembler::Success; 3932 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3933 unsigned add = fieldFromInstruction(Insn, 4, 1); 3934 3935 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3936 return MCDisassembler::Fail; 3937 Inst.addOperand(MCOperand::createImm(add)); 3938 3939 return S; 3940 } 3941 3942 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3943 uint64_t Address, const void *Decoder) { 3944 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3945 // Note only one trailing zero not two. Also the J1 and J2 values are from 3946 // the encoded instruction. So here change to I1 and I2 values via: 3947 // I1 = NOT(J1 EOR S); 3948 // I2 = NOT(J2 EOR S); 3949 // and build the imm32 with two trailing zeros as documented: 3950 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3951 unsigned S = (Val >> 23) & 1; 3952 unsigned J1 = (Val >> 22) & 1; 3953 unsigned J2 = (Val >> 21) & 1; 3954 unsigned I1 = !(J1 ^ S); 3955 unsigned I2 = !(J2 ^ S); 3956 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3957 int imm32 = SignExtend32<25>(tmp << 1); 3958 3959 if (!tryAddingSymbolicOperand(Address, 3960 (Address & ~2u) + imm32 + 4, 3961 true, 4, Inst, Decoder)) 3962 Inst.addOperand(MCOperand::createImm(imm32)); 3963 return MCDisassembler::Success; 3964 } 3965 3966 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3967 uint64_t Address, const void *Decoder) { 3968 if (Val == 0xA || Val == 0xB) 3969 return MCDisassembler::Fail; 3970 3971 const FeatureBitset &featureBits = 3972 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3973 3974 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 3975 return MCDisassembler::Fail; 3976 3977 Inst.addOperand(MCOperand::createImm(Val)); 3978 return MCDisassembler::Success; 3979 } 3980 3981 static DecodeStatus 3982 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3983 uint64_t Address, const void *Decoder) { 3984 DecodeStatus S = MCDisassembler::Success; 3985 3986 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3987 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3988 3989 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3991 return MCDisassembler::Fail; 3992 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3993 return MCDisassembler::Fail; 3994 return S; 3995 } 3996 3997 static DecodeStatus 3998 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3999 uint64_t Address, const void *Decoder) { 4000 DecodeStatus S = MCDisassembler::Success; 4001 4002 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4003 if (pred == 0xE || pred == 0xF) { 4004 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4005 switch (opc) { 4006 default: 4007 return MCDisassembler::Fail; 4008 case 0xf3bf8f4: 4009 Inst.setOpcode(ARM::t2DSB); 4010 break; 4011 case 0xf3bf8f5: 4012 Inst.setOpcode(ARM::t2DMB); 4013 break; 4014 case 0xf3bf8f6: 4015 Inst.setOpcode(ARM::t2ISB); 4016 break; 4017 } 4018 4019 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4020 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4021 } 4022 4023 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4024 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4025 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4026 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4027 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4028 4029 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4030 return MCDisassembler::Fail; 4031 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 4034 return S; 4035 } 4036 4037 // Decode a shifted immediate operand. These basically consist 4038 // of an 8-bit value, and a 4-bit directive that specifies either 4039 // a splat operation or a rotation. 4040 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4041 uint64_t Address, const void *Decoder) { 4042 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4043 if (ctrl == 0) { 4044 unsigned byte = fieldFromInstruction(Val, 8, 2); 4045 unsigned imm = fieldFromInstruction(Val, 0, 8); 4046 switch (byte) { 4047 case 0: 4048 Inst.addOperand(MCOperand::createImm(imm)); 4049 break; 4050 case 1: 4051 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4052 break; 4053 case 2: 4054 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4055 break; 4056 case 3: 4057 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4058 (imm << 8) | imm)); 4059 break; 4060 } 4061 } else { 4062 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4063 unsigned rot = fieldFromInstruction(Val, 7, 5); 4064 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4065 Inst.addOperand(MCOperand::createImm(imm)); 4066 } 4067 4068 return MCDisassembler::Success; 4069 } 4070 4071 static DecodeStatus 4072 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4073 uint64_t Address, const void *Decoder) { 4074 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4075 true, 2, Inst, Decoder)) 4076 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4077 return MCDisassembler::Success; 4078 } 4079 4080 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4081 uint64_t Address, 4082 const void *Decoder) { 4083 // Val is passed in as S:J1:J2:imm10:imm11 4084 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4085 // the encoded instruction. So here change to I1 and I2 values via: 4086 // I1 = NOT(J1 EOR S); 4087 // I2 = NOT(J2 EOR S); 4088 // and build the imm32 with one trailing zero as documented: 4089 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4090 unsigned S = (Val >> 23) & 1; 4091 unsigned J1 = (Val >> 22) & 1; 4092 unsigned J2 = (Val >> 21) & 1; 4093 unsigned I1 = !(J1 ^ S); 4094 unsigned I2 = !(J2 ^ S); 4095 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4096 int imm32 = SignExtend32<25>(tmp << 1); 4097 4098 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4099 true, 4, Inst, Decoder)) 4100 Inst.addOperand(MCOperand::createImm(imm32)); 4101 return MCDisassembler::Success; 4102 } 4103 4104 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4105 uint64_t Address, const void *Decoder) { 4106 if (Val & ~0xf) 4107 return MCDisassembler::Fail; 4108 4109 Inst.addOperand(MCOperand::createImm(Val)); 4110 return MCDisassembler::Success; 4111 } 4112 4113 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4114 uint64_t Address, const void *Decoder) { 4115 if (Val & ~0xf) 4116 return MCDisassembler::Fail; 4117 4118 Inst.addOperand(MCOperand::createImm(Val)); 4119 return MCDisassembler::Success; 4120 } 4121 4122 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4123 uint64_t Address, const void *Decoder) { 4124 DecodeStatus S = MCDisassembler::Success; 4125 const FeatureBitset &FeatureBits = 4126 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4127 4128 if (FeatureBits[ARM::FeatureMClass]) { 4129 unsigned ValLow = Val & 0xff; 4130 4131 // Validate the SYSm value first. 4132 switch (ValLow) { 4133 case 0: // apsr 4134 case 1: // iapsr 4135 case 2: // eapsr 4136 case 3: // xpsr 4137 case 5: // ipsr 4138 case 6: // epsr 4139 case 7: // iepsr 4140 case 8: // msp 4141 case 9: // psp 4142 case 16: // primask 4143 case 20: // control 4144 break; 4145 case 17: // basepri 4146 case 18: // basepri_max 4147 case 19: // faultmask 4148 if (!(FeatureBits[ARM::HasV7Ops])) 4149 // Values basepri, basepri_max and faultmask are only valid for v7m. 4150 return MCDisassembler::Fail; 4151 break; 4152 case 0x8a: // msplim_ns 4153 case 0x8b: // psplim_ns 4154 case 0x91: // basepri_ns 4155 case 0x93: // faultmask_ns 4156 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4157 return MCDisassembler::Fail; 4158 LLVM_FALLTHROUGH; 4159 case 10: // msplim 4160 case 11: // psplim 4161 case 0x88: // msp_ns 4162 case 0x89: // psp_ns 4163 case 0x90: // primask_ns 4164 case 0x94: // control_ns 4165 case 0x98: // sp_ns 4166 if (!(FeatureBits[ARM::Feature8MSecExt])) 4167 return MCDisassembler::Fail; 4168 break; 4169 default: 4170 // Architecturally defined as unpredictable 4171 S = MCDisassembler::SoftFail; 4172 break; 4173 } 4174 4175 if (Inst.getOpcode() == ARM::t2MSR_M) { 4176 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4177 if (!(FeatureBits[ARM::HasV7Ops])) { 4178 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4179 // unpredictable. 4180 if (Mask != 2) 4181 S = MCDisassembler::SoftFail; 4182 } 4183 else { 4184 // The ARMv7-M architecture stores an additional 2-bit mask value in 4185 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4186 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4187 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4188 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4189 // only if the processor includes the DSP extension. 4190 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4191 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4192 S = MCDisassembler::SoftFail; 4193 } 4194 } 4195 } else { 4196 // A/R class 4197 if (Val == 0) 4198 return MCDisassembler::Fail; 4199 } 4200 Inst.addOperand(MCOperand::createImm(Val)); 4201 return S; 4202 } 4203 4204 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4205 uint64_t Address, const void *Decoder) { 4206 unsigned R = fieldFromInstruction(Val, 5, 1); 4207 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4208 4209 // The table of encodings for these banked registers comes from B9.2.3 of the 4210 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4211 // neater. So by fiat, these values are UNPREDICTABLE: 4212 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4213 return MCDisassembler::Fail; 4214 4215 Inst.addOperand(MCOperand::createImm(Val)); 4216 return MCDisassembler::Success; 4217 } 4218 4219 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4220 uint64_t Address, const void *Decoder) { 4221 DecodeStatus S = MCDisassembler::Success; 4222 4223 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4224 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4225 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4226 4227 if (Rn == 0xF) 4228 S = MCDisassembler::SoftFail; 4229 4230 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4231 return MCDisassembler::Fail; 4232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4233 return MCDisassembler::Fail; 4234 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 4237 return S; 4238 } 4239 4240 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4241 uint64_t Address, 4242 const void *Decoder) { 4243 DecodeStatus S = MCDisassembler::Success; 4244 4245 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4246 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4247 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4248 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4249 4250 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4251 return MCDisassembler::Fail; 4252 4253 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4254 S = MCDisassembler::SoftFail; 4255 4256 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4257 return MCDisassembler::Fail; 4258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4259 return MCDisassembler::Fail; 4260 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4261 return MCDisassembler::Fail; 4262 4263 return S; 4264 } 4265 4266 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4267 uint64_t Address, const void *Decoder) { 4268 DecodeStatus S = MCDisassembler::Success; 4269 4270 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4271 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4272 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4273 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4274 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4275 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4276 4277 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4278 4279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4280 return MCDisassembler::Fail; 4281 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4282 return MCDisassembler::Fail; 4283 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4284 return MCDisassembler::Fail; 4285 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4286 return MCDisassembler::Fail; 4287 4288 return S; 4289 } 4290 4291 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4292 uint64_t Address, const void *Decoder) { 4293 DecodeStatus S = MCDisassembler::Success; 4294 4295 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4296 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4297 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4298 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4299 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4300 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4301 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4302 4303 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4304 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4305 4306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4307 return MCDisassembler::Fail; 4308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4309 return MCDisassembler::Fail; 4310 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4313 return MCDisassembler::Fail; 4314 4315 return S; 4316 } 4317 4318 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4319 uint64_t Address, const void *Decoder) { 4320 DecodeStatus S = MCDisassembler::Success; 4321 4322 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4323 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4324 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4325 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4326 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4327 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4328 4329 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4330 4331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4332 return MCDisassembler::Fail; 4333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4334 return MCDisassembler::Fail; 4335 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4336 return MCDisassembler::Fail; 4337 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4338 return MCDisassembler::Fail; 4339 4340 return S; 4341 } 4342 4343 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4344 uint64_t Address, const void *Decoder) { 4345 DecodeStatus S = MCDisassembler::Success; 4346 4347 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4348 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4349 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4350 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4351 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4352 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4353 4354 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4355 4356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4357 return MCDisassembler::Fail; 4358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4359 return MCDisassembler::Fail; 4360 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4361 return MCDisassembler::Fail; 4362 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 4365 return S; 4366 } 4367 4368 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4369 uint64_t Address, const void *Decoder) { 4370 DecodeStatus S = MCDisassembler::Success; 4371 4372 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4373 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4374 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4375 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4376 unsigned size = fieldFromInstruction(Insn, 10, 2); 4377 4378 unsigned align = 0; 4379 unsigned index = 0; 4380 switch (size) { 4381 default: 4382 return MCDisassembler::Fail; 4383 case 0: 4384 if (fieldFromInstruction(Insn, 4, 1)) 4385 return MCDisassembler::Fail; // UNDEFINED 4386 index = fieldFromInstruction(Insn, 5, 3); 4387 break; 4388 case 1: 4389 if (fieldFromInstruction(Insn, 5, 1)) 4390 return MCDisassembler::Fail; // UNDEFINED 4391 index = fieldFromInstruction(Insn, 6, 2); 4392 if (fieldFromInstruction(Insn, 4, 1)) 4393 align = 2; 4394 break; 4395 case 2: 4396 if (fieldFromInstruction(Insn, 6, 1)) 4397 return MCDisassembler::Fail; // UNDEFINED 4398 index = fieldFromInstruction(Insn, 7, 1); 4399 4400 switch (fieldFromInstruction(Insn, 4, 2)) { 4401 case 0 : 4402 align = 0; break; 4403 case 3: 4404 align = 4; break; 4405 default: 4406 return MCDisassembler::Fail; 4407 } 4408 break; 4409 } 4410 4411 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4412 return MCDisassembler::Fail; 4413 if (Rm != 0xF) { // Writeback 4414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4415 return MCDisassembler::Fail; 4416 } 4417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4418 return MCDisassembler::Fail; 4419 Inst.addOperand(MCOperand::createImm(align)); 4420 if (Rm != 0xF) { 4421 if (Rm != 0xD) { 4422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4423 return MCDisassembler::Fail; 4424 } else 4425 Inst.addOperand(MCOperand::createReg(0)); 4426 } 4427 4428 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4429 return MCDisassembler::Fail; 4430 Inst.addOperand(MCOperand::createImm(index)); 4431 4432 return S; 4433 } 4434 4435 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4436 uint64_t Address, const void *Decoder) { 4437 DecodeStatus S = MCDisassembler::Success; 4438 4439 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4440 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4441 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4442 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4443 unsigned size = fieldFromInstruction(Insn, 10, 2); 4444 4445 unsigned align = 0; 4446 unsigned index = 0; 4447 switch (size) { 4448 default: 4449 return MCDisassembler::Fail; 4450 case 0: 4451 if (fieldFromInstruction(Insn, 4, 1)) 4452 return MCDisassembler::Fail; // UNDEFINED 4453 index = fieldFromInstruction(Insn, 5, 3); 4454 break; 4455 case 1: 4456 if (fieldFromInstruction(Insn, 5, 1)) 4457 return MCDisassembler::Fail; // UNDEFINED 4458 index = fieldFromInstruction(Insn, 6, 2); 4459 if (fieldFromInstruction(Insn, 4, 1)) 4460 align = 2; 4461 break; 4462 case 2: 4463 if (fieldFromInstruction(Insn, 6, 1)) 4464 return MCDisassembler::Fail; // UNDEFINED 4465 index = fieldFromInstruction(Insn, 7, 1); 4466 4467 switch (fieldFromInstruction(Insn, 4, 2)) { 4468 case 0: 4469 align = 0; break; 4470 case 3: 4471 align = 4; break; 4472 default: 4473 return MCDisassembler::Fail; 4474 } 4475 break; 4476 } 4477 4478 if (Rm != 0xF) { // Writeback 4479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4480 return MCDisassembler::Fail; 4481 } 4482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4483 return MCDisassembler::Fail; 4484 Inst.addOperand(MCOperand::createImm(align)); 4485 if (Rm != 0xF) { 4486 if (Rm != 0xD) { 4487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4488 return MCDisassembler::Fail; 4489 } else 4490 Inst.addOperand(MCOperand::createReg(0)); 4491 } 4492 4493 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4494 return MCDisassembler::Fail; 4495 Inst.addOperand(MCOperand::createImm(index)); 4496 4497 return S; 4498 } 4499 4500 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4501 uint64_t Address, const void *Decoder) { 4502 DecodeStatus S = MCDisassembler::Success; 4503 4504 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4505 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4506 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4507 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4508 unsigned size = fieldFromInstruction(Insn, 10, 2); 4509 4510 unsigned align = 0; 4511 unsigned index = 0; 4512 unsigned inc = 1; 4513 switch (size) { 4514 default: 4515 return MCDisassembler::Fail; 4516 case 0: 4517 index = fieldFromInstruction(Insn, 5, 3); 4518 if (fieldFromInstruction(Insn, 4, 1)) 4519 align = 2; 4520 break; 4521 case 1: 4522 index = fieldFromInstruction(Insn, 6, 2); 4523 if (fieldFromInstruction(Insn, 4, 1)) 4524 align = 4; 4525 if (fieldFromInstruction(Insn, 5, 1)) 4526 inc = 2; 4527 break; 4528 case 2: 4529 if (fieldFromInstruction(Insn, 5, 1)) 4530 return MCDisassembler::Fail; // UNDEFINED 4531 index = fieldFromInstruction(Insn, 7, 1); 4532 if (fieldFromInstruction(Insn, 4, 1) != 0) 4533 align = 8; 4534 if (fieldFromInstruction(Insn, 6, 1)) 4535 inc = 2; 4536 break; 4537 } 4538 4539 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4540 return MCDisassembler::Fail; 4541 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4542 return MCDisassembler::Fail; 4543 if (Rm != 0xF) { // Writeback 4544 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4545 return MCDisassembler::Fail; 4546 } 4547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4548 return MCDisassembler::Fail; 4549 Inst.addOperand(MCOperand::createImm(align)); 4550 if (Rm != 0xF) { 4551 if (Rm != 0xD) { 4552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4553 return MCDisassembler::Fail; 4554 } else 4555 Inst.addOperand(MCOperand::createReg(0)); 4556 } 4557 4558 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4559 return MCDisassembler::Fail; 4560 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4561 return MCDisassembler::Fail; 4562 Inst.addOperand(MCOperand::createImm(index)); 4563 4564 return S; 4565 } 4566 4567 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4568 uint64_t Address, const void *Decoder) { 4569 DecodeStatus S = MCDisassembler::Success; 4570 4571 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4572 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4573 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4574 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4575 unsigned size = fieldFromInstruction(Insn, 10, 2); 4576 4577 unsigned align = 0; 4578 unsigned index = 0; 4579 unsigned inc = 1; 4580 switch (size) { 4581 default: 4582 return MCDisassembler::Fail; 4583 case 0: 4584 index = fieldFromInstruction(Insn, 5, 3); 4585 if (fieldFromInstruction(Insn, 4, 1)) 4586 align = 2; 4587 break; 4588 case 1: 4589 index = fieldFromInstruction(Insn, 6, 2); 4590 if (fieldFromInstruction(Insn, 4, 1)) 4591 align = 4; 4592 if (fieldFromInstruction(Insn, 5, 1)) 4593 inc = 2; 4594 break; 4595 case 2: 4596 if (fieldFromInstruction(Insn, 5, 1)) 4597 return MCDisassembler::Fail; // UNDEFINED 4598 index = fieldFromInstruction(Insn, 7, 1); 4599 if (fieldFromInstruction(Insn, 4, 1) != 0) 4600 align = 8; 4601 if (fieldFromInstruction(Insn, 6, 1)) 4602 inc = 2; 4603 break; 4604 } 4605 4606 if (Rm != 0xF) { // Writeback 4607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4608 return MCDisassembler::Fail; 4609 } 4610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4611 return MCDisassembler::Fail; 4612 Inst.addOperand(MCOperand::createImm(align)); 4613 if (Rm != 0xF) { 4614 if (Rm != 0xD) { 4615 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4616 return MCDisassembler::Fail; 4617 } else 4618 Inst.addOperand(MCOperand::createReg(0)); 4619 } 4620 4621 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4622 return MCDisassembler::Fail; 4623 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4624 return MCDisassembler::Fail; 4625 Inst.addOperand(MCOperand::createImm(index)); 4626 4627 return S; 4628 } 4629 4630 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4631 uint64_t Address, const void *Decoder) { 4632 DecodeStatus S = MCDisassembler::Success; 4633 4634 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4635 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4636 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4637 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4638 unsigned size = fieldFromInstruction(Insn, 10, 2); 4639 4640 unsigned align = 0; 4641 unsigned index = 0; 4642 unsigned inc = 1; 4643 switch (size) { 4644 default: 4645 return MCDisassembler::Fail; 4646 case 0: 4647 if (fieldFromInstruction(Insn, 4, 1)) 4648 return MCDisassembler::Fail; // UNDEFINED 4649 index = fieldFromInstruction(Insn, 5, 3); 4650 break; 4651 case 1: 4652 if (fieldFromInstruction(Insn, 4, 1)) 4653 return MCDisassembler::Fail; // UNDEFINED 4654 index = fieldFromInstruction(Insn, 6, 2); 4655 if (fieldFromInstruction(Insn, 5, 1)) 4656 inc = 2; 4657 break; 4658 case 2: 4659 if (fieldFromInstruction(Insn, 4, 2)) 4660 return MCDisassembler::Fail; // UNDEFINED 4661 index = fieldFromInstruction(Insn, 7, 1); 4662 if (fieldFromInstruction(Insn, 6, 1)) 4663 inc = 2; 4664 break; 4665 } 4666 4667 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4668 return MCDisassembler::Fail; 4669 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4670 return MCDisassembler::Fail; 4671 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4672 return MCDisassembler::Fail; 4673 4674 if (Rm != 0xF) { // Writeback 4675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4676 return MCDisassembler::Fail; 4677 } 4678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 Inst.addOperand(MCOperand::createImm(align)); 4681 if (Rm != 0xF) { 4682 if (Rm != 0xD) { 4683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4684 return MCDisassembler::Fail; 4685 } else 4686 Inst.addOperand(MCOperand::createReg(0)); 4687 } 4688 4689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4690 return MCDisassembler::Fail; 4691 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4692 return MCDisassembler::Fail; 4693 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4694 return MCDisassembler::Fail; 4695 Inst.addOperand(MCOperand::createImm(index)); 4696 4697 return S; 4698 } 4699 4700 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4701 uint64_t Address, const void *Decoder) { 4702 DecodeStatus S = MCDisassembler::Success; 4703 4704 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4705 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4706 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4707 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4708 unsigned size = fieldFromInstruction(Insn, 10, 2); 4709 4710 unsigned align = 0; 4711 unsigned index = 0; 4712 unsigned inc = 1; 4713 switch (size) { 4714 default: 4715 return MCDisassembler::Fail; 4716 case 0: 4717 if (fieldFromInstruction(Insn, 4, 1)) 4718 return MCDisassembler::Fail; // UNDEFINED 4719 index = fieldFromInstruction(Insn, 5, 3); 4720 break; 4721 case 1: 4722 if (fieldFromInstruction(Insn, 4, 1)) 4723 return MCDisassembler::Fail; // UNDEFINED 4724 index = fieldFromInstruction(Insn, 6, 2); 4725 if (fieldFromInstruction(Insn, 5, 1)) 4726 inc = 2; 4727 break; 4728 case 2: 4729 if (fieldFromInstruction(Insn, 4, 2)) 4730 return MCDisassembler::Fail; // UNDEFINED 4731 index = fieldFromInstruction(Insn, 7, 1); 4732 if (fieldFromInstruction(Insn, 6, 1)) 4733 inc = 2; 4734 break; 4735 } 4736 4737 if (Rm != 0xF) { // Writeback 4738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4739 return MCDisassembler::Fail; 4740 } 4741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4742 return MCDisassembler::Fail; 4743 Inst.addOperand(MCOperand::createImm(align)); 4744 if (Rm != 0xF) { 4745 if (Rm != 0xD) { 4746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4747 return MCDisassembler::Fail; 4748 } else 4749 Inst.addOperand(MCOperand::createReg(0)); 4750 } 4751 4752 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4753 return MCDisassembler::Fail; 4754 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4755 return MCDisassembler::Fail; 4756 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4757 return MCDisassembler::Fail; 4758 Inst.addOperand(MCOperand::createImm(index)); 4759 4760 return S; 4761 } 4762 4763 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4764 uint64_t Address, const void *Decoder) { 4765 DecodeStatus S = MCDisassembler::Success; 4766 4767 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4768 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4769 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4770 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4771 unsigned size = fieldFromInstruction(Insn, 10, 2); 4772 4773 unsigned align = 0; 4774 unsigned index = 0; 4775 unsigned inc = 1; 4776 switch (size) { 4777 default: 4778 return MCDisassembler::Fail; 4779 case 0: 4780 if (fieldFromInstruction(Insn, 4, 1)) 4781 align = 4; 4782 index = fieldFromInstruction(Insn, 5, 3); 4783 break; 4784 case 1: 4785 if (fieldFromInstruction(Insn, 4, 1)) 4786 align = 8; 4787 index = fieldFromInstruction(Insn, 6, 2); 4788 if (fieldFromInstruction(Insn, 5, 1)) 4789 inc = 2; 4790 break; 4791 case 2: 4792 switch (fieldFromInstruction(Insn, 4, 2)) { 4793 case 0: 4794 align = 0; break; 4795 case 3: 4796 return MCDisassembler::Fail; 4797 default: 4798 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4799 } 4800 4801 index = fieldFromInstruction(Insn, 7, 1); 4802 if (fieldFromInstruction(Insn, 6, 1)) 4803 inc = 2; 4804 break; 4805 } 4806 4807 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4808 return MCDisassembler::Fail; 4809 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4810 return MCDisassembler::Fail; 4811 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4812 return MCDisassembler::Fail; 4813 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4814 return MCDisassembler::Fail; 4815 4816 if (Rm != 0xF) { // Writeback 4817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4818 return MCDisassembler::Fail; 4819 } 4820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4821 return MCDisassembler::Fail; 4822 Inst.addOperand(MCOperand::createImm(align)); 4823 if (Rm != 0xF) { 4824 if (Rm != 0xD) { 4825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4826 return MCDisassembler::Fail; 4827 } else 4828 Inst.addOperand(MCOperand::createReg(0)); 4829 } 4830 4831 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4832 return MCDisassembler::Fail; 4833 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4834 return MCDisassembler::Fail; 4835 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4836 return MCDisassembler::Fail; 4837 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4838 return MCDisassembler::Fail; 4839 Inst.addOperand(MCOperand::createImm(index)); 4840 4841 return S; 4842 } 4843 4844 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4845 uint64_t Address, const void *Decoder) { 4846 DecodeStatus S = MCDisassembler::Success; 4847 4848 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4849 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4850 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4851 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4852 unsigned size = fieldFromInstruction(Insn, 10, 2); 4853 4854 unsigned align = 0; 4855 unsigned index = 0; 4856 unsigned inc = 1; 4857 switch (size) { 4858 default: 4859 return MCDisassembler::Fail; 4860 case 0: 4861 if (fieldFromInstruction(Insn, 4, 1)) 4862 align = 4; 4863 index = fieldFromInstruction(Insn, 5, 3); 4864 break; 4865 case 1: 4866 if (fieldFromInstruction(Insn, 4, 1)) 4867 align = 8; 4868 index = fieldFromInstruction(Insn, 6, 2); 4869 if (fieldFromInstruction(Insn, 5, 1)) 4870 inc = 2; 4871 break; 4872 case 2: 4873 switch (fieldFromInstruction(Insn, 4, 2)) { 4874 case 0: 4875 align = 0; break; 4876 case 3: 4877 return MCDisassembler::Fail; 4878 default: 4879 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4880 } 4881 4882 index = fieldFromInstruction(Insn, 7, 1); 4883 if (fieldFromInstruction(Insn, 6, 1)) 4884 inc = 2; 4885 break; 4886 } 4887 4888 if (Rm != 0xF) { // Writeback 4889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4890 return MCDisassembler::Fail; 4891 } 4892 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4893 return MCDisassembler::Fail; 4894 Inst.addOperand(MCOperand::createImm(align)); 4895 if (Rm != 0xF) { 4896 if (Rm != 0xD) { 4897 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4898 return MCDisassembler::Fail; 4899 } else 4900 Inst.addOperand(MCOperand::createReg(0)); 4901 } 4902 4903 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4904 return MCDisassembler::Fail; 4905 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4906 return MCDisassembler::Fail; 4907 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4908 return MCDisassembler::Fail; 4909 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4910 return MCDisassembler::Fail; 4911 Inst.addOperand(MCOperand::createImm(index)); 4912 4913 return S; 4914 } 4915 4916 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4917 uint64_t Address, const void *Decoder) { 4918 DecodeStatus S = MCDisassembler::Success; 4919 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4920 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4921 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4922 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4923 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4924 4925 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4926 S = MCDisassembler::SoftFail; 4927 4928 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4929 return MCDisassembler::Fail; 4930 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4931 return MCDisassembler::Fail; 4932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4933 return MCDisassembler::Fail; 4934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4935 return MCDisassembler::Fail; 4936 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4937 return MCDisassembler::Fail; 4938 4939 return S; 4940 } 4941 4942 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4943 uint64_t Address, const void *Decoder) { 4944 DecodeStatus S = MCDisassembler::Success; 4945 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4946 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4947 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4948 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4949 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4950 4951 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4952 S = MCDisassembler::SoftFail; 4953 4954 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4955 return MCDisassembler::Fail; 4956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4957 return MCDisassembler::Fail; 4958 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4959 return MCDisassembler::Fail; 4960 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4961 return MCDisassembler::Fail; 4962 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4963 return MCDisassembler::Fail; 4964 4965 return S; 4966 } 4967 4968 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4969 uint64_t Address, const void *Decoder) { 4970 DecodeStatus S = MCDisassembler::Success; 4971 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4972 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4973 4974 if (pred == 0xF) { 4975 pred = 0xE; 4976 S = MCDisassembler::SoftFail; 4977 } 4978 4979 if (mask == 0x0) 4980 return MCDisassembler::Fail; 4981 4982 Inst.addOperand(MCOperand::createImm(pred)); 4983 Inst.addOperand(MCOperand::createImm(mask)); 4984 return S; 4985 } 4986 4987 static DecodeStatus 4988 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4989 uint64_t Address, const void *Decoder) { 4990 DecodeStatus S = MCDisassembler::Success; 4991 4992 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4993 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4994 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4995 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4996 unsigned W = fieldFromInstruction(Insn, 21, 1); 4997 unsigned U = fieldFromInstruction(Insn, 23, 1); 4998 unsigned P = fieldFromInstruction(Insn, 24, 1); 4999 bool writeback = (W == 1) | (P == 0); 5000 5001 addr |= (U << 8) | (Rn << 9); 5002 5003 if (writeback && (Rn == Rt || Rn == Rt2)) 5004 Check(S, MCDisassembler::SoftFail); 5005 if (Rt == Rt2) 5006 Check(S, MCDisassembler::SoftFail); 5007 5008 // Rt 5009 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5010 return MCDisassembler::Fail; 5011 // Rt2 5012 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5013 return MCDisassembler::Fail; 5014 // Writeback operand 5015 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5016 return MCDisassembler::Fail; 5017 // addr 5018 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5019 return MCDisassembler::Fail; 5020 5021 return S; 5022 } 5023 5024 static DecodeStatus 5025 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5026 uint64_t Address, const void *Decoder) { 5027 DecodeStatus S = MCDisassembler::Success; 5028 5029 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5030 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5031 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5032 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5033 unsigned W = fieldFromInstruction(Insn, 21, 1); 5034 unsigned U = fieldFromInstruction(Insn, 23, 1); 5035 unsigned P = fieldFromInstruction(Insn, 24, 1); 5036 bool writeback = (W == 1) | (P == 0); 5037 5038 addr |= (U << 8) | (Rn << 9); 5039 5040 if (writeback && (Rn == Rt || Rn == Rt2)) 5041 Check(S, MCDisassembler::SoftFail); 5042 5043 // Writeback operand 5044 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5045 return MCDisassembler::Fail; 5046 // Rt 5047 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5048 return MCDisassembler::Fail; 5049 // Rt2 5050 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5051 return MCDisassembler::Fail; 5052 // addr 5053 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5054 return MCDisassembler::Fail; 5055 5056 return S; 5057 } 5058 5059 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5060 uint64_t Address, const void *Decoder) { 5061 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5062 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5063 if (sign1 != sign2) return MCDisassembler::Fail; 5064 5065 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5066 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5067 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5068 Val |= sign1 << 12; 5069 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5070 5071 return MCDisassembler::Success; 5072 } 5073 5074 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5075 uint64_t Address, 5076 const void *Decoder) { 5077 DecodeStatus S = MCDisassembler::Success; 5078 5079 // Shift of "asr #32" is not allowed in Thumb2 mode. 5080 if (Val == 0x20) S = MCDisassembler::Fail; 5081 Inst.addOperand(MCOperand::createImm(Val)); 5082 return S; 5083 } 5084 5085 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5086 uint64_t Address, const void *Decoder) { 5087 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5088 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5089 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5090 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5091 5092 if (pred == 0xF) 5093 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5094 5095 DecodeStatus S = MCDisassembler::Success; 5096 5097 if (Rt == Rn || Rn == Rt2) 5098 S = MCDisassembler::SoftFail; 5099 5100 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5101 return MCDisassembler::Fail; 5102 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5103 return MCDisassembler::Fail; 5104 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5105 return MCDisassembler::Fail; 5106 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5107 return MCDisassembler::Fail; 5108 5109 return S; 5110 } 5111 5112 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5113 uint64_t Address, const void *Decoder) { 5114 const FeatureBitset &featureBits = 5115 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5116 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5117 5118 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5119 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5120 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5121 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5122 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5123 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5124 unsigned op = fieldFromInstruction(Insn, 5, 1); 5125 5126 DecodeStatus S = MCDisassembler::Success; 5127 5128 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5129 if (!(imm & 0x38)) { 5130 if (cmode == 0xF) { 5131 if (op == 1) return MCDisassembler::Fail; 5132 Inst.setOpcode(ARM::VMOVv2f32); 5133 } 5134 if (hasFullFP16) { 5135 if (cmode == 0xE) { 5136 if (op == 1) { 5137 Inst.setOpcode(ARM::VMOVv1i64); 5138 } else { 5139 Inst.setOpcode(ARM::VMOVv8i8); 5140 } 5141 } 5142 if (cmode == 0xD) { 5143 if (op == 1) { 5144 Inst.setOpcode(ARM::VMVNv2i32); 5145 } else { 5146 Inst.setOpcode(ARM::VMOVv2i32); 5147 } 5148 } 5149 if (cmode == 0xC) { 5150 if (op == 1) { 5151 Inst.setOpcode(ARM::VMVNv2i32); 5152 } else { 5153 Inst.setOpcode(ARM::VMOVv2i32); 5154 } 5155 } 5156 } 5157 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5158 } 5159 5160 if (!(imm & 0x20)) return MCDisassembler::Fail; 5161 5162 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5163 return MCDisassembler::Fail; 5164 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5165 return MCDisassembler::Fail; 5166 Inst.addOperand(MCOperand::createImm(64 - imm)); 5167 5168 return S; 5169 } 5170 5171 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5172 uint64_t Address, const void *Decoder) { 5173 const FeatureBitset &featureBits = 5174 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5175 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5176 5177 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5178 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5179 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5180 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5181 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5182 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5183 unsigned op = fieldFromInstruction(Insn, 5, 1); 5184 5185 DecodeStatus S = MCDisassembler::Success; 5186 5187 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5188 if (!(imm & 0x38)) { 5189 if (cmode == 0xF) { 5190 if (op == 1) return MCDisassembler::Fail; 5191 Inst.setOpcode(ARM::VMOVv4f32); 5192 } 5193 if (hasFullFP16) { 5194 if (cmode == 0xE) { 5195 if (op == 1) { 5196 Inst.setOpcode(ARM::VMOVv2i64); 5197 } else { 5198 Inst.setOpcode(ARM::VMOVv16i8); 5199 } 5200 } 5201 if (cmode == 0xD) { 5202 if (op == 1) { 5203 Inst.setOpcode(ARM::VMVNv4i32); 5204 } else { 5205 Inst.setOpcode(ARM::VMOVv4i32); 5206 } 5207 } 5208 if (cmode == 0xC) { 5209 if (op == 1) { 5210 Inst.setOpcode(ARM::VMVNv4i32); 5211 } else { 5212 Inst.setOpcode(ARM::VMOVv4i32); 5213 } 5214 } 5215 } 5216 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5217 } 5218 5219 if (!(imm & 0x20)) return MCDisassembler::Fail; 5220 5221 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5222 return MCDisassembler::Fail; 5223 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5224 return MCDisassembler::Fail; 5225 Inst.addOperand(MCOperand::createImm(64 - imm)); 5226 5227 return S; 5228 } 5229 5230 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5231 unsigned Insn, 5232 uint64_t Address, 5233 const void *Decoder) { 5234 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5235 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5236 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5237 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5238 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5239 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5240 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5241 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5242 5243 DecodeStatus S = MCDisassembler::Success; 5244 5245 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5246 5247 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5248 return MCDisassembler::Fail; 5249 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5250 return MCDisassembler::Fail; 5251 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5252 return MCDisassembler::Fail; 5253 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5254 return MCDisassembler::Fail; 5255 // The lane index does not have any bits in the encoding, because it can only 5256 // be 0. 5257 Inst.addOperand(MCOperand::createImm(0)); 5258 Inst.addOperand(MCOperand::createImm(rotate)); 5259 5260 return S; 5261 } 5262 5263 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5264 uint64_t Address, const void *Decoder) { 5265 DecodeStatus S = MCDisassembler::Success; 5266 5267 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5268 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5269 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5270 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5271 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5272 5273 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5274 S = MCDisassembler::SoftFail; 5275 5276 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5277 return MCDisassembler::Fail; 5278 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5279 return MCDisassembler::Fail; 5280 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5281 return MCDisassembler::Fail; 5282 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5283 return MCDisassembler::Fail; 5284 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5285 return MCDisassembler::Fail; 5286 5287 return S; 5288 } 5289 5290 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5291 uint64_t Address, const void *Decoder) { 5292 DecodeStatus S = MCDisassembler::Success; 5293 5294 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5295 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5296 unsigned cop = fieldFromInstruction(Val, 8, 4); 5297 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5298 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5299 5300 if ((cop & ~0x1) == 0xa) 5301 return MCDisassembler::Fail; 5302 5303 if (Rt == Rt2) 5304 S = MCDisassembler::SoftFail; 5305 5306 // We have to check if the instruction is MRRC2 5307 // or MCRR2 when constructing the operands for 5308 // Inst. Reason is because MRRC2 stores to two 5309 // registers so it's tablegen desc has has two 5310 // outputs whereas MCRR doesn't store to any 5311 // registers so all of it's operands are listed 5312 // as inputs, therefore the operand order for 5313 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5314 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5315 5316 if (Inst.getOpcode() == ARM::MRRC2) { 5317 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5318 return MCDisassembler::Fail; 5319 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5320 return MCDisassembler::Fail; 5321 } 5322 Inst.addOperand(MCOperand::createImm(cop)); 5323 Inst.addOperand(MCOperand::createImm(opc1)); 5324 if (Inst.getOpcode() == ARM::MCRR2) { 5325 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5326 return MCDisassembler::Fail; 5327 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5328 return MCDisassembler::Fail; 5329 } 5330 Inst.addOperand(MCOperand::createImm(CRm)); 5331 5332 return S; 5333 } 5334 5335 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5336 uint64_t Address, 5337 const void *Decoder) { 5338 const FeatureBitset &featureBits = 5339 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5340 DecodeStatus S = MCDisassembler::Success; 5341 5342 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5343 5344 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5345 if (Rt == 13 || Rt == 15) 5346 S = MCDisassembler::SoftFail; 5347 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5348 } else 5349 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5350 5351 if (featureBits[ARM::ModeThumb]) { 5352 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5353 Inst.addOperand(MCOperand::createReg(0)); 5354 } else { 5355 unsigned pred = fieldFromInstruction(Val, 28, 4); 5356 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5357 return MCDisassembler::Fail; 5358 } 5359 5360 return S; 5361 } 5362