1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &VStream, 141 raw_ostream &CStream) const override; 142 143 private: 144 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 145 ArrayRef<uint8_t> Bytes, uint64_t Address, 146 raw_ostream &VStream, 147 raw_ostream &CStream) const; 148 149 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 150 ArrayRef<uint8_t> Bytes, uint64_t Address, 151 raw_ostream &VStream, 152 raw_ostream &CStream) const; 153 154 mutable ITStatus ITBlock; 155 mutable VPTStatus VPTBlock; 156 157 DecodeStatus AddThumbPredicate(MCInst&) const; 158 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 159 }; 160 161 } // end anonymous namespace 162 163 static bool Check(DecodeStatus &Out, DecodeStatus In) { 164 switch (In) { 165 case MCDisassembler::Success: 166 // Out stays the same. 167 return true; 168 case MCDisassembler::SoftFail: 169 Out = In; 170 return true; 171 case MCDisassembler::Fail: 172 Out = In; 173 return false; 174 } 175 llvm_unreachable("Invalid DecodeStatus!"); 176 } 177 178 // Forward declare these because the autogenerated code will reference them. 179 // Definitions are further down. 180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 216 unsigned RegNo, 217 uint64_t Address, 218 const void *Decoder); 219 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 226 unsigned RegNo, uint64_t Address, 227 const void *Decoder); 228 229 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 240 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 245 unsigned Insn, 246 uint64_t Address, 247 const void *Decoder); 248 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 257 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 258 unsigned Insn, 259 uint64_t Adddress, 260 const void *Decoder); 261 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 382 unsigned Val, 383 uint64_t Address, 384 const void *Decoder); 385 386 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 403 uint64_t Address, const void *Decoder); 404 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 407 uint64_t Address, const void* Decoder); 408 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 409 uint64_t Address, const void* Decoder); 410 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 411 uint64_t Address, const void* Decoder); 412 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 413 uint64_t Address, const void* Decoder); 414 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 417 uint64_t Address, const void *Decoder); 418 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 419 uint64_t Address, const void *Decoder); 420 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 421 uint64_t Address, 422 const void *Decoder); 423 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 424 uint64_t Address, const void *Decoder); 425 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 426 uint64_t Address, const void *Decoder); 427 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 428 uint64_t Address, const void *Decoder); 429 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 430 uint64_t Address, const void *Decoder); 431 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 432 uint64_t Address, const void *Decoder); 433 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 434 uint64_t Address, const void *Decoder); 435 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 436 uint64_t Address, const void *Decoder); 437 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 438 uint64_t Address, const void *Decoder); 439 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 440 uint64_t Address, const void *Decoder); 441 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 442 uint64_t Address, const void *Decoder); 443 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 444 uint64_t Address, const void *Decoder); 445 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 446 uint64_t Address, const void *Decoder); 447 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 448 uint64_t Address, const void *Decoder); 449 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 450 uint64_t Address, const void *Decoder); 451 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 452 uint64_t Address, const void *Decoder); 453 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 454 uint64_t Address, const void *Decoder); 455 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 456 uint64_t Address, const void *Decoder); 457 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 458 uint64_t Address, const void *Decoder); 459 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 460 uint64_t Address, const void *Decoder); 461 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 462 uint64_t Address, const void *Decoder); 463 464 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 465 uint64_t Address, const void *Decoder); 466 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 467 uint64_t Address, const void *Decoder); 468 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 469 uint64_t Address, const void *Decoder); 470 471 template <bool isSigned, bool isNeg, int size> 472 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 473 uint64_t Address, const void *Decoder); 474 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 475 uint64_t Address, 476 const void *Decoder); 477 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 478 uint64_t Address, 479 const void *Decoder); 480 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 481 const void *Decoder); 482 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 483 uint64_t Address, 484 const void *Decoder); 485 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 486 const void *Decoder); 487 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 488 uint64_t Address, const void *Decoder); 489 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 490 uint64_t Address, const void *Decoder); 491 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 492 uint64_t Address, 493 const void *Decoder); 494 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 495 uint64_t Address, 496 const void *Decoder); 497 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 498 uint64_t Address, 499 const void *Decoder); 500 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 501 unsigned Val, 502 uint64_t Address, 503 const void *Decoder); 504 template<bool Writeback> 505 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 506 uint64_t Address, 507 const void *Decoder); 508 template<unsigned MinLog, unsigned MaxLog> 509 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 510 uint64_t Address, 511 const void *Decoder); 512 template <int shift> 513 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 514 uint64_t Address, 515 const void *Decoder); 516 template<unsigned start> 517 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 518 uint64_t Address, 519 const void *Decoder); 520 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 521 uint64_t Address, 522 const void *Decoder); 523 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 524 uint64_t Address, 525 const void *Decoder); 526 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 527 uint64_t Address, const void *Decoder); 528 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 529 uint64_t Address, const void *Decoder); 530 template<bool scalar, OperandDecoder predicate_decoder> 531 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 532 uint64_t Address, const void *Decoder); 533 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 534 uint64_t Address, const void *Decoder); 535 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 536 uint64_t Address, 537 const void *Decoder); 538 #include "ARMGenDisassemblerTables.inc" 539 540 static MCDisassembler *createARMDisassembler(const Target &T, 541 const MCSubtargetInfo &STI, 542 MCContext &Ctx) { 543 return new ARMDisassembler(STI, Ctx); 544 } 545 546 // Post-decoding checks 547 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 548 uint64_t Address, raw_ostream &OS, 549 raw_ostream &CS, 550 uint32_t Insn, 551 DecodeStatus Result) { 552 switch (MI.getOpcode()) { 553 case ARM::HVC: { 554 // HVC is undefined if condition = 0xf otherwise upredictable 555 // if condition != 0xe 556 uint32_t Cond = (Insn >> 28) & 0xF; 557 if (Cond == 0xF) 558 return MCDisassembler::Fail; 559 if (Cond != 0xE) 560 return MCDisassembler::SoftFail; 561 return Result; 562 } 563 case ARM::t2ADDri: 564 case ARM::t2ADDri12: 565 case ARM::t2ADDrr: 566 case ARM::t2ADDrs: 567 case ARM::t2SUBri: 568 case ARM::t2SUBri12: 569 case ARM::t2SUBrr: 570 case ARM::t2SUBrs: 571 if (MI.getOperand(0).getReg() == ARM::SP && 572 MI.getOperand(1).getReg() != ARM::SP) 573 return MCDisassembler::SoftFail; 574 return Result; 575 default: return Result; 576 } 577 } 578 579 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 580 ArrayRef<uint8_t> Bytes, 581 uint64_t Address, raw_ostream &OS, 582 raw_ostream &CS) const { 583 if (STI.getFeatureBits()[ARM::ModeThumb]) 584 return getThumbInstruction(MI, Size, Bytes, Address, OS, CS); 585 return getARMInstruction(MI, Size, Bytes, Address, OS, CS); 586 } 587 588 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 589 ArrayRef<uint8_t> Bytes, 590 uint64_t Address, 591 raw_ostream &OS, 592 raw_ostream &CS) const { 593 CommentStream = &CS; 594 595 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 596 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 597 "mode!"); 598 599 // We want to read exactly 4 bytes of data. 600 if (Bytes.size() < 4) { 601 Size = 0; 602 return MCDisassembler::Fail; 603 } 604 605 // Encoded as a small-endian 32-bit word in the stream. 606 uint32_t Insn = 607 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 608 609 // Calling the auto-generated decoder function. 610 DecodeStatus Result = 611 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 612 if (Result != MCDisassembler::Fail) { 613 Size = 4; 614 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 615 } 616 617 struct DecodeTable { 618 const uint8_t *P; 619 bool DecodePred; 620 }; 621 622 const DecodeTable Tables[] = { 623 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 624 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 625 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 626 {DecoderTablev8Crypto32, false}, 627 }; 628 629 for (auto Table : Tables) { 630 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 631 if (Result != MCDisassembler::Fail) { 632 Size = 4; 633 // Add a fake predicate operand, because we share these instruction 634 // definitions with Thumb2 where these instructions are predicable. 635 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 636 return MCDisassembler::Fail; 637 return Result; 638 } 639 } 640 641 Result = 642 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 643 if (Result != MCDisassembler::Fail) { 644 Size = 4; 645 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 646 } 647 648 Size = 4; 649 return MCDisassembler::Fail; 650 } 651 652 namespace llvm { 653 654 extern const MCInstrDesc ARMInsts[]; 655 656 } // end namespace llvm 657 658 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 659 /// immediate Value in the MCInst. The immediate Value has had any PC 660 /// adjustment made by the caller. If the instruction is a branch instruction 661 /// then isBranch is true, else false. If the getOpInfo() function was set as 662 /// part of the setupForSymbolicDisassembly() call then that function is called 663 /// to get any symbolic information at the Address for this instruction. If 664 /// that returns non-zero then the symbolic information it returns is used to 665 /// create an MCExpr and that is added as an operand to the MCInst. If 666 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 667 /// Value is done and if a symbol is found an MCExpr is created with that, else 668 /// an MCExpr with Value is created. This function returns true if it adds an 669 /// operand to the MCInst and false otherwise. 670 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 671 bool isBranch, uint64_t InstSize, 672 MCInst &MI, const void *Decoder) { 673 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 674 // FIXME: Does it make sense for value to be negative? 675 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 676 /* Offset */ 0, InstSize); 677 } 678 679 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 680 /// referenced by a load instruction with the base register that is the Pc. 681 /// These can often be values in a literal pool near the Address of the 682 /// instruction. The Address of the instruction and its immediate Value are 683 /// used as a possible literal pool entry. The SymbolLookUp call back will 684 /// return the name of a symbol referenced by the literal pool's entry if 685 /// the referenced address is that of a symbol. Or it will return a pointer to 686 /// a literal 'C' string if the referenced address of the literal pool's entry 687 /// is an address into a section with 'C' string literals. 688 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 689 const void *Decoder) { 690 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 691 Dis->tryAddingPcLoadReferenceComment(Value, Address); 692 } 693 694 // Thumb1 instructions don't have explicit S bits. Rather, they 695 // implicitly set CPSR. Since it's not represented in the encoding, the 696 // auto-generated decoder won't inject the CPSR operand. We need to fix 697 // that as a post-pass. 698 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 699 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 700 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 701 MCInst::iterator I = MI.begin(); 702 for (unsigned i = 0; i < NumOps; ++i, ++I) { 703 if (I == MI.end()) break; 704 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 705 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 706 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 707 return; 708 } 709 } 710 711 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 712 } 713 714 static bool isVectorPredicable(unsigned Opcode) { 715 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 716 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 717 for (unsigned i = 0; i < NumOps; ++i) { 718 if (ARM::isVpred(OpInfo[i].OperandType)) 719 return true; 720 } 721 return false; 722 } 723 724 // Most Thumb instructions don't have explicit predicates in the 725 // encoding, but rather get their predicates from IT context. We need 726 // to fix up the predicate operands using this context information as a 727 // post-pass. 728 MCDisassembler::DecodeStatus 729 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 730 MCDisassembler::DecodeStatus S = Success; 731 732 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 733 734 // A few instructions actually have predicates encoded in them. Don't 735 // try to overwrite it if we're seeing one of those. 736 switch (MI.getOpcode()) { 737 case ARM::tBcc: 738 case ARM::t2Bcc: 739 case ARM::tCBZ: 740 case ARM::tCBNZ: 741 case ARM::tCPS: 742 case ARM::t2CPS3p: 743 case ARM::t2CPS2p: 744 case ARM::t2CPS1p: 745 case ARM::t2CSEL: 746 case ARM::t2CSINC: 747 case ARM::t2CSINV: 748 case ARM::t2CSNEG: 749 case ARM::tMOVSr: 750 case ARM::tSETEND: 751 // Some instructions (mostly conditional branches) are not 752 // allowed in IT blocks. 753 if (ITBlock.instrInITBlock()) 754 S = SoftFail; 755 else 756 return Success; 757 break; 758 case ARM::t2HINT: 759 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 760 S = SoftFail; 761 break; 762 case ARM::tB: 763 case ARM::t2B: 764 case ARM::t2TBB: 765 case ARM::t2TBH: 766 // Some instructions (mostly unconditional branches) can 767 // only appears at the end of, or outside of, an IT. 768 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 769 S = SoftFail; 770 break; 771 default: 772 break; 773 } 774 775 // Warn on non-VPT predicable instruction in a VPT block and a VPT 776 // predicable instruction in an IT block 777 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 778 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 779 S = SoftFail; 780 781 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 782 // assume a predicate of AL. 783 unsigned CC = ARMCC::AL; 784 unsigned VCC = ARMVCC::None; 785 if (ITBlock.instrInITBlock()) { 786 CC = ITBlock.getITCC(); 787 ITBlock.advanceITState(); 788 } else if (VPTBlock.instrInVPTBlock()) { 789 VCC = VPTBlock.getVPTPred(); 790 VPTBlock.advanceVPTState(); 791 } 792 793 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 794 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 795 796 MCInst::iterator CCI = MI.begin(); 797 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 798 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 799 } 800 801 if (ARMInsts[MI.getOpcode()].isPredicable()) { 802 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 803 ++CCI; 804 if (CC == ARMCC::AL) 805 MI.insert(CCI, MCOperand::createReg(0)); 806 else 807 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 808 } else if (CC != ARMCC::AL) { 809 Check(S, SoftFail); 810 } 811 812 MCInst::iterator VCCI = MI.begin(); 813 unsigned VCCPos; 814 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 815 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 816 } 817 818 if (isVectorPredicable(MI.getOpcode())) { 819 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 820 ++VCCI; 821 if (VCC == ARMVCC::None) 822 MI.insert(VCCI, MCOperand::createReg(0)); 823 else 824 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 825 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 826 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 827 VCCPos + 2, MCOI::TIED_TO); 828 assert(TiedOp >= 0 && 829 "Inactive register in vpred_r is not tied to an output!"); 830 MI.insert(VCCI, MI.getOperand(TiedOp)); 831 } 832 } else if (VCC != ARMVCC::None) { 833 Check(S, SoftFail); 834 } 835 836 return S; 837 } 838 839 // Thumb VFP instructions are a special case. Because we share their 840 // encodings between ARM and Thumb modes, and they are predicable in ARM 841 // mode, the auto-generated decoder will give them an (incorrect) 842 // predicate operand. We need to rewrite these operands based on the IT 843 // context as a post-pass. 844 void ARMDisassembler::UpdateThumbVFPPredicate( 845 DecodeStatus &S, MCInst &MI) const { 846 unsigned CC; 847 CC = ITBlock.getITCC(); 848 if (CC == 0xF) 849 CC = ARMCC::AL; 850 if (ITBlock.instrInITBlock()) 851 ITBlock.advanceITState(); 852 else if (VPTBlock.instrInVPTBlock()) { 853 CC = VPTBlock.getVPTPred(); 854 VPTBlock.advanceVPTState(); 855 } 856 857 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 858 MCInst::iterator I = MI.begin(); 859 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 860 for (unsigned i = 0; i < NumOps; ++i, ++I) { 861 if (OpInfo[i].isPredicate() ) { 862 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 863 Check(S, SoftFail); 864 I->setImm(CC); 865 ++I; 866 if (CC == ARMCC::AL) 867 I->setReg(0); 868 else 869 I->setReg(ARM::CPSR); 870 return; 871 } 872 } 873 } 874 875 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 876 ArrayRef<uint8_t> Bytes, 877 uint64_t Address, 878 raw_ostream &OS, 879 raw_ostream &CS) const { 880 CommentStream = &CS; 881 882 assert(STI.getFeatureBits()[ARM::ModeThumb] && 883 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 884 885 // We want to read exactly 2 bytes of data. 886 if (Bytes.size() < 2) { 887 Size = 0; 888 return MCDisassembler::Fail; 889 } 890 891 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 892 DecodeStatus Result = 893 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 894 if (Result != MCDisassembler::Fail) { 895 Size = 2; 896 Check(Result, AddThumbPredicate(MI)); 897 return Result; 898 } 899 900 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 901 STI); 902 if (Result) { 903 Size = 2; 904 bool InITBlock = ITBlock.instrInITBlock(); 905 Check(Result, AddThumbPredicate(MI)); 906 AddThumb1SBit(MI, InITBlock); 907 return Result; 908 } 909 910 Result = 911 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 912 if (Result != MCDisassembler::Fail) { 913 Size = 2; 914 915 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 916 // the Thumb predicate. 917 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 918 Result = MCDisassembler::SoftFail; 919 920 Check(Result, AddThumbPredicate(MI)); 921 922 // If we find an IT instruction, we need to parse its condition 923 // code and mask operands so that we can apply them correctly 924 // to the subsequent instructions. 925 if (MI.getOpcode() == ARM::t2IT) { 926 unsigned Firstcond = MI.getOperand(0).getImm(); 927 unsigned Mask = MI.getOperand(1).getImm(); 928 ITBlock.setITState(Firstcond, Mask); 929 930 // An IT instruction that would give a 'NV' predicate is unpredictable. 931 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 932 CS << "unpredictable IT predicate sequence"; 933 } 934 935 return Result; 936 } 937 938 // We want to read exactly 4 bytes of data. 939 if (Bytes.size() < 4) { 940 Size = 0; 941 return MCDisassembler::Fail; 942 } 943 944 uint32_t Insn32 = 945 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 946 947 Result = 948 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 949 if (Result != MCDisassembler::Fail) { 950 Size = 4; 951 952 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 953 // the VPT predicate. 954 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 955 Result = MCDisassembler::SoftFail; 956 957 Check(Result, AddThumbPredicate(MI)); 958 959 if (isVPTOpcode(MI.getOpcode())) { 960 unsigned Mask = MI.getOperand(0).getImm(); 961 VPTBlock.setVPTState(Mask); 962 } 963 964 return Result; 965 } 966 967 Result = 968 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 969 if (Result != MCDisassembler::Fail) { 970 Size = 4; 971 bool InITBlock = ITBlock.instrInITBlock(); 972 Check(Result, AddThumbPredicate(MI)); 973 AddThumb1SBit(MI, InITBlock); 974 return Result; 975 } 976 977 Result = 978 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 979 if (Result != MCDisassembler::Fail) { 980 Size = 4; 981 Check(Result, AddThumbPredicate(MI)); 982 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 983 } 984 985 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 986 Result = 987 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 988 if (Result != MCDisassembler::Fail) { 989 Size = 4; 990 UpdateThumbVFPPredicate(Result, MI); 991 return Result; 992 } 993 } 994 995 Result = 996 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 997 if (Result != MCDisassembler::Fail) { 998 Size = 4; 999 return Result; 1000 } 1001 1002 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1003 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1004 STI); 1005 if (Result != MCDisassembler::Fail) { 1006 Size = 4; 1007 Check(Result, AddThumbPredicate(MI)); 1008 return Result; 1009 } 1010 } 1011 1012 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1013 uint32_t NEONLdStInsn = Insn32; 1014 NEONLdStInsn &= 0xF0FFFFFF; 1015 NEONLdStInsn |= 0x04000000; 1016 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1017 Address, this, STI); 1018 if (Result != MCDisassembler::Fail) { 1019 Size = 4; 1020 Check(Result, AddThumbPredicate(MI)); 1021 return Result; 1022 } 1023 } 1024 1025 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1026 uint32_t NEONDataInsn = Insn32; 1027 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1028 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1029 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1030 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1031 Address, this, STI); 1032 if (Result != MCDisassembler::Fail) { 1033 Size = 4; 1034 Check(Result, AddThumbPredicate(MI)); 1035 return Result; 1036 } 1037 1038 uint32_t NEONCryptoInsn = Insn32; 1039 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1040 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1041 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1042 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1043 Address, this, STI); 1044 if (Result != MCDisassembler::Fail) { 1045 Size = 4; 1046 return Result; 1047 } 1048 1049 uint32_t NEONv8Insn = Insn32; 1050 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1051 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1052 this, STI); 1053 if (Result != MCDisassembler::Fail) { 1054 Size = 4; 1055 return Result; 1056 } 1057 } 1058 1059 Result = 1060 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1061 if (Result != MCDisassembler::Fail) { 1062 Size = 4; 1063 Check(Result, AddThumbPredicate(MI)); 1064 return Result; 1065 } 1066 1067 Size = 0; 1068 return MCDisassembler::Fail; 1069 } 1070 1071 extern "C" void LLVMInitializeARMDisassembler() { 1072 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1073 createARMDisassembler); 1074 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1075 createARMDisassembler); 1076 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1077 createARMDisassembler); 1078 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1079 createARMDisassembler); 1080 } 1081 1082 static const uint16_t GPRDecoderTable[] = { 1083 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1084 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1085 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1086 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1087 }; 1088 1089 static const uint16_t CLRMGPRDecoderTable[] = { 1090 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1091 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1092 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1093 ARM::R12, 0, ARM::LR, ARM::APSR 1094 }; 1095 1096 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1097 uint64_t Address, const void *Decoder) { 1098 if (RegNo > 15) 1099 return MCDisassembler::Fail; 1100 1101 unsigned Register = GPRDecoderTable[RegNo]; 1102 Inst.addOperand(MCOperand::createReg(Register)); 1103 return MCDisassembler::Success; 1104 } 1105 1106 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1107 uint64_t Address, 1108 const void *Decoder) { 1109 if (RegNo > 15) 1110 return MCDisassembler::Fail; 1111 1112 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1113 if (Register == 0) 1114 return MCDisassembler::Fail; 1115 1116 Inst.addOperand(MCOperand::createReg(Register)); 1117 return MCDisassembler::Success; 1118 } 1119 1120 static DecodeStatus 1121 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1122 uint64_t Address, const void *Decoder) { 1123 DecodeStatus S = MCDisassembler::Success; 1124 1125 if (RegNo == 15) 1126 S = MCDisassembler::SoftFail; 1127 1128 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1129 1130 return S; 1131 } 1132 1133 static DecodeStatus 1134 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1135 uint64_t Address, const void *Decoder) { 1136 DecodeStatus S = MCDisassembler::Success; 1137 1138 if (RegNo == 15) 1139 { 1140 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1141 return MCDisassembler::Success; 1142 } 1143 1144 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1145 return S; 1146 } 1147 1148 static DecodeStatus 1149 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1150 uint64_t Address, const void *Decoder) { 1151 DecodeStatus S = MCDisassembler::Success; 1152 1153 if (RegNo == 15) 1154 { 1155 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1156 return MCDisassembler::Success; 1157 } 1158 1159 if (RegNo == 13) 1160 S = MCDisassembler::SoftFail; 1161 1162 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1163 return S; 1164 } 1165 1166 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1167 uint64_t Address, const void *Decoder) { 1168 if (RegNo > 7) 1169 return MCDisassembler::Fail; 1170 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1171 } 1172 1173 static const uint16_t GPRPairDecoderTable[] = { 1174 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1175 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1176 }; 1177 1178 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1179 uint64_t Address, const void *Decoder) { 1180 DecodeStatus S = MCDisassembler::Success; 1181 1182 if (RegNo > 13) 1183 return MCDisassembler::Fail; 1184 1185 if ((RegNo & 1) || RegNo == 0xe) 1186 S = MCDisassembler::SoftFail; 1187 1188 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1189 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1190 return S; 1191 } 1192 1193 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1194 uint64_t Address, const void *Decoder) { 1195 unsigned Register = 0; 1196 switch (RegNo) { 1197 case 0: 1198 Register = ARM::R0; 1199 break; 1200 case 1: 1201 Register = ARM::R1; 1202 break; 1203 case 2: 1204 Register = ARM::R2; 1205 break; 1206 case 3: 1207 Register = ARM::R3; 1208 break; 1209 case 9: 1210 Register = ARM::R9; 1211 break; 1212 case 12: 1213 Register = ARM::R12; 1214 break; 1215 default: 1216 return MCDisassembler::Fail; 1217 } 1218 1219 Inst.addOperand(MCOperand::createReg(Register)); 1220 return MCDisassembler::Success; 1221 } 1222 1223 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1224 uint64_t Address, const void *Decoder) { 1225 DecodeStatus S = MCDisassembler::Success; 1226 1227 const FeatureBitset &featureBits = 1228 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1229 1230 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1231 S = MCDisassembler::SoftFail; 1232 1233 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1234 return S; 1235 } 1236 1237 static const uint16_t SPRDecoderTable[] = { 1238 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1239 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1240 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1241 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1242 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1243 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1244 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1245 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1246 }; 1247 1248 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1249 uint64_t Address, const void *Decoder) { 1250 if (RegNo > 31) 1251 return MCDisassembler::Fail; 1252 1253 unsigned Register = SPRDecoderTable[RegNo]; 1254 Inst.addOperand(MCOperand::createReg(Register)); 1255 return MCDisassembler::Success; 1256 } 1257 1258 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1259 uint64_t Address, const void *Decoder) { 1260 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1261 } 1262 1263 static const uint16_t DPRDecoderTable[] = { 1264 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1265 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1266 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1267 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1268 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1269 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1270 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1271 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1272 }; 1273 1274 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1275 uint64_t Address, const void *Decoder) { 1276 const FeatureBitset &featureBits = 1277 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1278 1279 bool hasD32 = featureBits[ARM::FeatureD32]; 1280 1281 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1282 return MCDisassembler::Fail; 1283 1284 unsigned Register = DPRDecoderTable[RegNo]; 1285 Inst.addOperand(MCOperand::createReg(Register)); 1286 return MCDisassembler::Success; 1287 } 1288 1289 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1290 uint64_t Address, const void *Decoder) { 1291 if (RegNo > 7) 1292 return MCDisassembler::Fail; 1293 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1294 } 1295 1296 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1297 uint64_t Address, const void *Decoder) { 1298 if (RegNo > 15) 1299 return MCDisassembler::Fail; 1300 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1301 } 1302 1303 static DecodeStatus 1304 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1305 uint64_t Address, const void *Decoder) { 1306 if (RegNo > 15) 1307 return MCDisassembler::Fail; 1308 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1309 } 1310 1311 static const uint16_t QPRDecoderTable[] = { 1312 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1313 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1314 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1315 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1316 }; 1317 1318 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1319 uint64_t Address, const void *Decoder) { 1320 if (RegNo > 31 || (RegNo & 1) != 0) 1321 return MCDisassembler::Fail; 1322 RegNo >>= 1; 1323 1324 unsigned Register = QPRDecoderTable[RegNo]; 1325 Inst.addOperand(MCOperand::createReg(Register)); 1326 return MCDisassembler::Success; 1327 } 1328 1329 static const uint16_t DPairDecoderTable[] = { 1330 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1331 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1332 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1333 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1334 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1335 ARM::Q15 1336 }; 1337 1338 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1339 uint64_t Address, const void *Decoder) { 1340 if (RegNo > 30) 1341 return MCDisassembler::Fail; 1342 1343 unsigned Register = DPairDecoderTable[RegNo]; 1344 Inst.addOperand(MCOperand::createReg(Register)); 1345 return MCDisassembler::Success; 1346 } 1347 1348 static const uint16_t DPairSpacedDecoderTable[] = { 1349 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1350 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1351 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1352 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1353 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1354 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1355 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1356 ARM::D28_D30, ARM::D29_D31 1357 }; 1358 1359 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1360 unsigned RegNo, 1361 uint64_t Address, 1362 const void *Decoder) { 1363 if (RegNo > 29) 1364 return MCDisassembler::Fail; 1365 1366 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1367 Inst.addOperand(MCOperand::createReg(Register)); 1368 return MCDisassembler::Success; 1369 } 1370 1371 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1372 uint64_t Address, const void *Decoder) { 1373 DecodeStatus S = MCDisassembler::Success; 1374 if (Val == 0xF) return MCDisassembler::Fail; 1375 // AL predicate is not allowed on Thumb1 branches. 1376 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1377 return MCDisassembler::Fail; 1378 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1379 Check(S, MCDisassembler::SoftFail); 1380 Inst.addOperand(MCOperand::createImm(Val)); 1381 if (Val == ARMCC::AL) { 1382 Inst.addOperand(MCOperand::createReg(0)); 1383 } else 1384 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1385 return S; 1386 } 1387 1388 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1389 uint64_t Address, const void *Decoder) { 1390 if (Val) 1391 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1392 else 1393 Inst.addOperand(MCOperand::createReg(0)); 1394 return MCDisassembler::Success; 1395 } 1396 1397 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1398 uint64_t Address, const void *Decoder) { 1399 DecodeStatus S = MCDisassembler::Success; 1400 1401 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1402 unsigned type = fieldFromInstruction(Val, 5, 2); 1403 unsigned imm = fieldFromInstruction(Val, 7, 5); 1404 1405 // Register-immediate 1406 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1407 return MCDisassembler::Fail; 1408 1409 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1410 switch (type) { 1411 case 0: 1412 Shift = ARM_AM::lsl; 1413 break; 1414 case 1: 1415 Shift = ARM_AM::lsr; 1416 break; 1417 case 2: 1418 Shift = ARM_AM::asr; 1419 break; 1420 case 3: 1421 Shift = ARM_AM::ror; 1422 break; 1423 } 1424 1425 if (Shift == ARM_AM::ror && imm == 0) 1426 Shift = ARM_AM::rrx; 1427 1428 unsigned Op = Shift | (imm << 3); 1429 Inst.addOperand(MCOperand::createImm(Op)); 1430 1431 return S; 1432 } 1433 1434 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1435 uint64_t Address, const void *Decoder) { 1436 DecodeStatus S = MCDisassembler::Success; 1437 1438 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1439 unsigned type = fieldFromInstruction(Val, 5, 2); 1440 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1441 1442 // Register-register 1443 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1444 return MCDisassembler::Fail; 1445 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1446 return MCDisassembler::Fail; 1447 1448 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1449 switch (type) { 1450 case 0: 1451 Shift = ARM_AM::lsl; 1452 break; 1453 case 1: 1454 Shift = ARM_AM::lsr; 1455 break; 1456 case 2: 1457 Shift = ARM_AM::asr; 1458 break; 1459 case 3: 1460 Shift = ARM_AM::ror; 1461 break; 1462 } 1463 1464 Inst.addOperand(MCOperand::createImm(Shift)); 1465 1466 return S; 1467 } 1468 1469 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1470 uint64_t Address, const void *Decoder) { 1471 DecodeStatus S = MCDisassembler::Success; 1472 1473 bool NeedDisjointWriteback = false; 1474 unsigned WritebackReg = 0; 1475 bool CLRM = false; 1476 switch (Inst.getOpcode()) { 1477 default: 1478 break; 1479 case ARM::LDMIA_UPD: 1480 case ARM::LDMDB_UPD: 1481 case ARM::LDMIB_UPD: 1482 case ARM::LDMDA_UPD: 1483 case ARM::t2LDMIA_UPD: 1484 case ARM::t2LDMDB_UPD: 1485 case ARM::t2STMIA_UPD: 1486 case ARM::t2STMDB_UPD: 1487 NeedDisjointWriteback = true; 1488 WritebackReg = Inst.getOperand(0).getReg(); 1489 break; 1490 case ARM::t2CLRM: 1491 CLRM = true; 1492 break; 1493 } 1494 1495 // Empty register lists are not allowed. 1496 if (Val == 0) return MCDisassembler::Fail; 1497 for (unsigned i = 0; i < 16; ++i) { 1498 if (Val & (1 << i)) { 1499 if (CLRM) { 1500 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1501 return MCDisassembler::Fail; 1502 } 1503 } else { 1504 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1505 return MCDisassembler::Fail; 1506 // Writeback not allowed if Rn is in the target list. 1507 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1508 Check(S, MCDisassembler::SoftFail); 1509 } 1510 } 1511 } 1512 1513 return S; 1514 } 1515 1516 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1517 uint64_t Address, const void *Decoder) { 1518 DecodeStatus S = MCDisassembler::Success; 1519 1520 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1521 unsigned regs = fieldFromInstruction(Val, 0, 8); 1522 1523 // In case of unpredictable encoding, tweak the operands. 1524 if (regs == 0 || (Vd + regs) > 32) { 1525 regs = Vd + regs > 32 ? 32 - Vd : regs; 1526 regs = std::max( 1u, regs); 1527 S = MCDisassembler::SoftFail; 1528 } 1529 1530 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1531 return MCDisassembler::Fail; 1532 for (unsigned i = 0; i < (regs - 1); ++i) { 1533 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1534 return MCDisassembler::Fail; 1535 } 1536 1537 return S; 1538 } 1539 1540 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1541 uint64_t Address, const void *Decoder) { 1542 DecodeStatus S = MCDisassembler::Success; 1543 1544 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1545 unsigned regs = fieldFromInstruction(Val, 1, 7); 1546 1547 // In case of unpredictable encoding, tweak the operands. 1548 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1549 regs = Vd + regs > 32 ? 32 - Vd : regs; 1550 regs = std::max( 1u, regs); 1551 regs = std::min(16u, regs); 1552 S = MCDisassembler::SoftFail; 1553 } 1554 1555 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1556 return MCDisassembler::Fail; 1557 for (unsigned i = 0; i < (regs - 1); ++i) { 1558 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1559 return MCDisassembler::Fail; 1560 } 1561 1562 return S; 1563 } 1564 1565 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1566 uint64_t Address, const void *Decoder) { 1567 // This operand encodes a mask of contiguous zeros between a specified MSB 1568 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1569 // the mask of all bits LSB-and-lower, and then xor them to create 1570 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1571 // create the final mask. 1572 unsigned msb = fieldFromInstruction(Val, 5, 5); 1573 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1574 1575 DecodeStatus S = MCDisassembler::Success; 1576 if (lsb > msb) { 1577 Check(S, MCDisassembler::SoftFail); 1578 // The check above will cause the warning for the "potentially undefined 1579 // instruction encoding" but we can't build a bad MCOperand value here 1580 // with a lsb > msb or else printing the MCInst will cause a crash. 1581 lsb = msb; 1582 } 1583 1584 uint32_t msb_mask = 0xFFFFFFFF; 1585 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1586 uint32_t lsb_mask = (1U << lsb) - 1; 1587 1588 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1589 return S; 1590 } 1591 1592 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1593 uint64_t Address, const void *Decoder) { 1594 DecodeStatus S = MCDisassembler::Success; 1595 1596 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1597 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1598 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1599 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1600 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1601 unsigned U = fieldFromInstruction(Insn, 23, 1); 1602 const FeatureBitset &featureBits = 1603 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1604 1605 switch (Inst.getOpcode()) { 1606 case ARM::LDC_OFFSET: 1607 case ARM::LDC_PRE: 1608 case ARM::LDC_POST: 1609 case ARM::LDC_OPTION: 1610 case ARM::LDCL_OFFSET: 1611 case ARM::LDCL_PRE: 1612 case ARM::LDCL_POST: 1613 case ARM::LDCL_OPTION: 1614 case ARM::STC_OFFSET: 1615 case ARM::STC_PRE: 1616 case ARM::STC_POST: 1617 case ARM::STC_OPTION: 1618 case ARM::STCL_OFFSET: 1619 case ARM::STCL_PRE: 1620 case ARM::STCL_POST: 1621 case ARM::STCL_OPTION: 1622 case ARM::t2LDC_OFFSET: 1623 case ARM::t2LDC_PRE: 1624 case ARM::t2LDC_POST: 1625 case ARM::t2LDC_OPTION: 1626 case ARM::t2LDCL_OFFSET: 1627 case ARM::t2LDCL_PRE: 1628 case ARM::t2LDCL_POST: 1629 case ARM::t2LDCL_OPTION: 1630 case ARM::t2STC_OFFSET: 1631 case ARM::t2STC_PRE: 1632 case ARM::t2STC_POST: 1633 case ARM::t2STC_OPTION: 1634 case ARM::t2STCL_OFFSET: 1635 case ARM::t2STCL_PRE: 1636 case ARM::t2STCL_POST: 1637 case ARM::t2STCL_OPTION: 1638 case ARM::t2LDC2_OFFSET: 1639 case ARM::t2LDC2L_OFFSET: 1640 case ARM::t2LDC2_PRE: 1641 case ARM::t2LDC2L_PRE: 1642 case ARM::t2STC2_OFFSET: 1643 case ARM::t2STC2L_OFFSET: 1644 case ARM::t2STC2_PRE: 1645 case ARM::t2STC2L_PRE: 1646 case ARM::LDC2_OFFSET: 1647 case ARM::LDC2L_OFFSET: 1648 case ARM::LDC2_PRE: 1649 case ARM::LDC2L_PRE: 1650 case ARM::STC2_OFFSET: 1651 case ARM::STC2L_OFFSET: 1652 case ARM::STC2_PRE: 1653 case ARM::STC2L_PRE: 1654 case ARM::t2LDC2_OPTION: 1655 case ARM::t2STC2_OPTION: 1656 case ARM::t2LDC2_POST: 1657 case ARM::t2LDC2L_POST: 1658 case ARM::t2STC2_POST: 1659 case ARM::t2STC2L_POST: 1660 case ARM::LDC2_POST: 1661 case ARM::LDC2L_POST: 1662 case ARM::STC2_POST: 1663 case ARM::STC2L_POST: 1664 if (coproc == 0xA || coproc == 0xB || 1665 (featureBits[ARM::HasV8_1MMainlineOps] && 1666 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1667 coproc == 0xE || coproc == 0xF))) 1668 return MCDisassembler::Fail; 1669 break; 1670 default: 1671 break; 1672 } 1673 1674 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1675 return MCDisassembler::Fail; 1676 1677 Inst.addOperand(MCOperand::createImm(coproc)); 1678 Inst.addOperand(MCOperand::createImm(CRd)); 1679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1680 return MCDisassembler::Fail; 1681 1682 switch (Inst.getOpcode()) { 1683 case ARM::t2LDC2_OFFSET: 1684 case ARM::t2LDC2L_OFFSET: 1685 case ARM::t2LDC2_PRE: 1686 case ARM::t2LDC2L_PRE: 1687 case ARM::t2STC2_OFFSET: 1688 case ARM::t2STC2L_OFFSET: 1689 case ARM::t2STC2_PRE: 1690 case ARM::t2STC2L_PRE: 1691 case ARM::LDC2_OFFSET: 1692 case ARM::LDC2L_OFFSET: 1693 case ARM::LDC2_PRE: 1694 case ARM::LDC2L_PRE: 1695 case ARM::STC2_OFFSET: 1696 case ARM::STC2L_OFFSET: 1697 case ARM::STC2_PRE: 1698 case ARM::STC2L_PRE: 1699 case ARM::t2LDC_OFFSET: 1700 case ARM::t2LDCL_OFFSET: 1701 case ARM::t2LDC_PRE: 1702 case ARM::t2LDCL_PRE: 1703 case ARM::t2STC_OFFSET: 1704 case ARM::t2STCL_OFFSET: 1705 case ARM::t2STC_PRE: 1706 case ARM::t2STCL_PRE: 1707 case ARM::LDC_OFFSET: 1708 case ARM::LDCL_OFFSET: 1709 case ARM::LDC_PRE: 1710 case ARM::LDCL_PRE: 1711 case ARM::STC_OFFSET: 1712 case ARM::STCL_OFFSET: 1713 case ARM::STC_PRE: 1714 case ARM::STCL_PRE: 1715 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1716 Inst.addOperand(MCOperand::createImm(imm)); 1717 break; 1718 case ARM::t2LDC2_POST: 1719 case ARM::t2LDC2L_POST: 1720 case ARM::t2STC2_POST: 1721 case ARM::t2STC2L_POST: 1722 case ARM::LDC2_POST: 1723 case ARM::LDC2L_POST: 1724 case ARM::STC2_POST: 1725 case ARM::STC2L_POST: 1726 case ARM::t2LDC_POST: 1727 case ARM::t2LDCL_POST: 1728 case ARM::t2STC_POST: 1729 case ARM::t2STCL_POST: 1730 case ARM::LDC_POST: 1731 case ARM::LDCL_POST: 1732 case ARM::STC_POST: 1733 case ARM::STCL_POST: 1734 imm |= U << 8; 1735 LLVM_FALLTHROUGH; 1736 default: 1737 // The 'option' variant doesn't encode 'U' in the immediate since 1738 // the immediate is unsigned [0,255]. 1739 Inst.addOperand(MCOperand::createImm(imm)); 1740 break; 1741 } 1742 1743 switch (Inst.getOpcode()) { 1744 case ARM::LDC_OFFSET: 1745 case ARM::LDC_PRE: 1746 case ARM::LDC_POST: 1747 case ARM::LDC_OPTION: 1748 case ARM::LDCL_OFFSET: 1749 case ARM::LDCL_PRE: 1750 case ARM::LDCL_POST: 1751 case ARM::LDCL_OPTION: 1752 case ARM::STC_OFFSET: 1753 case ARM::STC_PRE: 1754 case ARM::STC_POST: 1755 case ARM::STC_OPTION: 1756 case ARM::STCL_OFFSET: 1757 case ARM::STCL_PRE: 1758 case ARM::STCL_POST: 1759 case ARM::STCL_OPTION: 1760 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1761 return MCDisassembler::Fail; 1762 break; 1763 default: 1764 break; 1765 } 1766 1767 return S; 1768 } 1769 1770 static DecodeStatus 1771 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1772 uint64_t Address, const void *Decoder) { 1773 DecodeStatus S = MCDisassembler::Success; 1774 1775 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1776 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1777 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1778 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1779 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1780 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1781 unsigned P = fieldFromInstruction(Insn, 24, 1); 1782 unsigned W = fieldFromInstruction(Insn, 21, 1); 1783 1784 // On stores, the writeback operand precedes Rt. 1785 switch (Inst.getOpcode()) { 1786 case ARM::STR_POST_IMM: 1787 case ARM::STR_POST_REG: 1788 case ARM::STRB_POST_IMM: 1789 case ARM::STRB_POST_REG: 1790 case ARM::STRT_POST_REG: 1791 case ARM::STRT_POST_IMM: 1792 case ARM::STRBT_POST_REG: 1793 case ARM::STRBT_POST_IMM: 1794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1795 return MCDisassembler::Fail; 1796 break; 1797 default: 1798 break; 1799 } 1800 1801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1802 return MCDisassembler::Fail; 1803 1804 // On loads, the writeback operand comes after Rt. 1805 switch (Inst.getOpcode()) { 1806 case ARM::LDR_POST_IMM: 1807 case ARM::LDR_POST_REG: 1808 case ARM::LDRB_POST_IMM: 1809 case ARM::LDRB_POST_REG: 1810 case ARM::LDRBT_POST_REG: 1811 case ARM::LDRBT_POST_IMM: 1812 case ARM::LDRT_POST_REG: 1813 case ARM::LDRT_POST_IMM: 1814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1815 return MCDisassembler::Fail; 1816 break; 1817 default: 1818 break; 1819 } 1820 1821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1822 return MCDisassembler::Fail; 1823 1824 ARM_AM::AddrOpc Op = ARM_AM::add; 1825 if (!fieldFromInstruction(Insn, 23, 1)) 1826 Op = ARM_AM::sub; 1827 1828 bool writeback = (P == 0) || (W == 1); 1829 unsigned idx_mode = 0; 1830 if (P && writeback) 1831 idx_mode = ARMII::IndexModePre; 1832 else if (!P && writeback) 1833 idx_mode = ARMII::IndexModePost; 1834 1835 if (writeback && (Rn == 15 || Rn == Rt)) 1836 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1837 1838 if (reg) { 1839 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1840 return MCDisassembler::Fail; 1841 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1842 switch( fieldFromInstruction(Insn, 5, 2)) { 1843 case 0: 1844 Opc = ARM_AM::lsl; 1845 break; 1846 case 1: 1847 Opc = ARM_AM::lsr; 1848 break; 1849 case 2: 1850 Opc = ARM_AM::asr; 1851 break; 1852 case 3: 1853 Opc = ARM_AM::ror; 1854 break; 1855 default: 1856 return MCDisassembler::Fail; 1857 } 1858 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1859 if (Opc == ARM_AM::ror && amt == 0) 1860 Opc = ARM_AM::rrx; 1861 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1862 1863 Inst.addOperand(MCOperand::createImm(imm)); 1864 } else { 1865 Inst.addOperand(MCOperand::createReg(0)); 1866 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1867 Inst.addOperand(MCOperand::createImm(tmp)); 1868 } 1869 1870 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1871 return MCDisassembler::Fail; 1872 1873 return S; 1874 } 1875 1876 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1877 uint64_t Address, const void *Decoder) { 1878 DecodeStatus S = MCDisassembler::Success; 1879 1880 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1881 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1882 unsigned type = fieldFromInstruction(Val, 5, 2); 1883 unsigned imm = fieldFromInstruction(Val, 7, 5); 1884 unsigned U = fieldFromInstruction(Val, 12, 1); 1885 1886 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1887 switch (type) { 1888 case 0: 1889 ShOp = ARM_AM::lsl; 1890 break; 1891 case 1: 1892 ShOp = ARM_AM::lsr; 1893 break; 1894 case 2: 1895 ShOp = ARM_AM::asr; 1896 break; 1897 case 3: 1898 ShOp = ARM_AM::ror; 1899 break; 1900 } 1901 1902 if (ShOp == ARM_AM::ror && imm == 0) 1903 ShOp = ARM_AM::rrx; 1904 1905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1906 return MCDisassembler::Fail; 1907 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1908 return MCDisassembler::Fail; 1909 unsigned shift; 1910 if (U) 1911 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1912 else 1913 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1914 Inst.addOperand(MCOperand::createImm(shift)); 1915 1916 return S; 1917 } 1918 1919 static DecodeStatus 1920 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1921 uint64_t Address, const void *Decoder) { 1922 DecodeStatus S = MCDisassembler::Success; 1923 1924 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1925 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1926 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1927 unsigned type = fieldFromInstruction(Insn, 22, 1); 1928 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1929 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1930 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1931 unsigned W = fieldFromInstruction(Insn, 21, 1); 1932 unsigned P = fieldFromInstruction(Insn, 24, 1); 1933 unsigned Rt2 = Rt + 1; 1934 1935 bool writeback = (W == 1) | (P == 0); 1936 1937 // For {LD,ST}RD, Rt must be even, else undefined. 1938 switch (Inst.getOpcode()) { 1939 case ARM::STRD: 1940 case ARM::STRD_PRE: 1941 case ARM::STRD_POST: 1942 case ARM::LDRD: 1943 case ARM::LDRD_PRE: 1944 case ARM::LDRD_POST: 1945 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1946 break; 1947 default: 1948 break; 1949 } 1950 switch (Inst.getOpcode()) { 1951 case ARM::STRD: 1952 case ARM::STRD_PRE: 1953 case ARM::STRD_POST: 1954 if (P == 0 && W == 1) 1955 S = MCDisassembler::SoftFail; 1956 1957 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1958 S = MCDisassembler::SoftFail; 1959 if (type && Rm == 15) 1960 S = MCDisassembler::SoftFail; 1961 if (Rt2 == 15) 1962 S = MCDisassembler::SoftFail; 1963 if (!type && fieldFromInstruction(Insn, 8, 4)) 1964 S = MCDisassembler::SoftFail; 1965 break; 1966 case ARM::STRH: 1967 case ARM::STRH_PRE: 1968 case ARM::STRH_POST: 1969 if (Rt == 15) 1970 S = MCDisassembler::SoftFail; 1971 if (writeback && (Rn == 15 || Rn == Rt)) 1972 S = MCDisassembler::SoftFail; 1973 if (!type && Rm == 15) 1974 S = MCDisassembler::SoftFail; 1975 break; 1976 case ARM::LDRD: 1977 case ARM::LDRD_PRE: 1978 case ARM::LDRD_POST: 1979 if (type && Rn == 15) { 1980 if (Rt2 == 15) 1981 S = MCDisassembler::SoftFail; 1982 break; 1983 } 1984 if (P == 0 && W == 1) 1985 S = MCDisassembler::SoftFail; 1986 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1987 S = MCDisassembler::SoftFail; 1988 if (!type && writeback && Rn == 15) 1989 S = MCDisassembler::SoftFail; 1990 if (writeback && (Rn == Rt || Rn == Rt2)) 1991 S = MCDisassembler::SoftFail; 1992 break; 1993 case ARM::LDRH: 1994 case ARM::LDRH_PRE: 1995 case ARM::LDRH_POST: 1996 if (type && Rn == 15) { 1997 if (Rt == 15) 1998 S = MCDisassembler::SoftFail; 1999 break; 2000 } 2001 if (Rt == 15) 2002 S = MCDisassembler::SoftFail; 2003 if (!type && Rm == 15) 2004 S = MCDisassembler::SoftFail; 2005 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2006 S = MCDisassembler::SoftFail; 2007 break; 2008 case ARM::LDRSH: 2009 case ARM::LDRSH_PRE: 2010 case ARM::LDRSH_POST: 2011 case ARM::LDRSB: 2012 case ARM::LDRSB_PRE: 2013 case ARM::LDRSB_POST: 2014 if (type && Rn == 15) { 2015 if (Rt == 15) 2016 S = MCDisassembler::SoftFail; 2017 break; 2018 } 2019 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2020 S = MCDisassembler::SoftFail; 2021 if (!type && (Rt == 15 || Rm == 15)) 2022 S = MCDisassembler::SoftFail; 2023 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2024 S = MCDisassembler::SoftFail; 2025 break; 2026 default: 2027 break; 2028 } 2029 2030 if (writeback) { // Writeback 2031 if (P) 2032 U |= ARMII::IndexModePre << 9; 2033 else 2034 U |= ARMII::IndexModePost << 9; 2035 2036 // On stores, the writeback operand precedes Rt. 2037 switch (Inst.getOpcode()) { 2038 case ARM::STRD: 2039 case ARM::STRD_PRE: 2040 case ARM::STRD_POST: 2041 case ARM::STRH: 2042 case ARM::STRH_PRE: 2043 case ARM::STRH_POST: 2044 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2045 return MCDisassembler::Fail; 2046 break; 2047 default: 2048 break; 2049 } 2050 } 2051 2052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2053 return MCDisassembler::Fail; 2054 switch (Inst.getOpcode()) { 2055 case ARM::STRD: 2056 case ARM::STRD_PRE: 2057 case ARM::STRD_POST: 2058 case ARM::LDRD: 2059 case ARM::LDRD_PRE: 2060 case ARM::LDRD_POST: 2061 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2062 return MCDisassembler::Fail; 2063 break; 2064 default: 2065 break; 2066 } 2067 2068 if (writeback) { 2069 // On loads, the writeback operand comes after Rt. 2070 switch (Inst.getOpcode()) { 2071 case ARM::LDRD: 2072 case ARM::LDRD_PRE: 2073 case ARM::LDRD_POST: 2074 case ARM::LDRH: 2075 case ARM::LDRH_PRE: 2076 case ARM::LDRH_POST: 2077 case ARM::LDRSH: 2078 case ARM::LDRSH_PRE: 2079 case ARM::LDRSH_POST: 2080 case ARM::LDRSB: 2081 case ARM::LDRSB_PRE: 2082 case ARM::LDRSB_POST: 2083 case ARM::LDRHTr: 2084 case ARM::LDRSBTr: 2085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2086 return MCDisassembler::Fail; 2087 break; 2088 default: 2089 break; 2090 } 2091 } 2092 2093 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2094 return MCDisassembler::Fail; 2095 2096 if (type) { 2097 Inst.addOperand(MCOperand::createReg(0)); 2098 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2099 } else { 2100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2101 return MCDisassembler::Fail; 2102 Inst.addOperand(MCOperand::createImm(U)); 2103 } 2104 2105 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2106 return MCDisassembler::Fail; 2107 2108 return S; 2109 } 2110 2111 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2112 uint64_t Address, const void *Decoder) { 2113 DecodeStatus S = MCDisassembler::Success; 2114 2115 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2116 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2117 2118 switch (mode) { 2119 case 0: 2120 mode = ARM_AM::da; 2121 break; 2122 case 1: 2123 mode = ARM_AM::ia; 2124 break; 2125 case 2: 2126 mode = ARM_AM::db; 2127 break; 2128 case 3: 2129 mode = ARM_AM::ib; 2130 break; 2131 } 2132 2133 Inst.addOperand(MCOperand::createImm(mode)); 2134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2135 return MCDisassembler::Fail; 2136 2137 return S; 2138 } 2139 2140 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2141 uint64_t Address, const void *Decoder) { 2142 DecodeStatus S = MCDisassembler::Success; 2143 2144 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2145 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2146 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2147 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2148 2149 if (pred == 0xF) 2150 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2151 2152 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2153 return MCDisassembler::Fail; 2154 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2155 return MCDisassembler::Fail; 2156 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2157 return MCDisassembler::Fail; 2158 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2159 return MCDisassembler::Fail; 2160 return S; 2161 } 2162 2163 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2164 unsigned Insn, 2165 uint64_t Address, const void *Decoder) { 2166 DecodeStatus S = MCDisassembler::Success; 2167 2168 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2169 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2170 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2171 2172 if (pred == 0xF) { 2173 // Ambiguous with RFE and SRS 2174 switch (Inst.getOpcode()) { 2175 case ARM::LDMDA: 2176 Inst.setOpcode(ARM::RFEDA); 2177 break; 2178 case ARM::LDMDA_UPD: 2179 Inst.setOpcode(ARM::RFEDA_UPD); 2180 break; 2181 case ARM::LDMDB: 2182 Inst.setOpcode(ARM::RFEDB); 2183 break; 2184 case ARM::LDMDB_UPD: 2185 Inst.setOpcode(ARM::RFEDB_UPD); 2186 break; 2187 case ARM::LDMIA: 2188 Inst.setOpcode(ARM::RFEIA); 2189 break; 2190 case ARM::LDMIA_UPD: 2191 Inst.setOpcode(ARM::RFEIA_UPD); 2192 break; 2193 case ARM::LDMIB: 2194 Inst.setOpcode(ARM::RFEIB); 2195 break; 2196 case ARM::LDMIB_UPD: 2197 Inst.setOpcode(ARM::RFEIB_UPD); 2198 break; 2199 case ARM::STMDA: 2200 Inst.setOpcode(ARM::SRSDA); 2201 break; 2202 case ARM::STMDA_UPD: 2203 Inst.setOpcode(ARM::SRSDA_UPD); 2204 break; 2205 case ARM::STMDB: 2206 Inst.setOpcode(ARM::SRSDB); 2207 break; 2208 case ARM::STMDB_UPD: 2209 Inst.setOpcode(ARM::SRSDB_UPD); 2210 break; 2211 case ARM::STMIA: 2212 Inst.setOpcode(ARM::SRSIA); 2213 break; 2214 case ARM::STMIA_UPD: 2215 Inst.setOpcode(ARM::SRSIA_UPD); 2216 break; 2217 case ARM::STMIB: 2218 Inst.setOpcode(ARM::SRSIB); 2219 break; 2220 case ARM::STMIB_UPD: 2221 Inst.setOpcode(ARM::SRSIB_UPD); 2222 break; 2223 default: 2224 return MCDisassembler::Fail; 2225 } 2226 2227 // For stores (which become SRS's, the only operand is the mode. 2228 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2229 // Check SRS encoding constraints 2230 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2231 fieldFromInstruction(Insn, 20, 1) == 0)) 2232 return MCDisassembler::Fail; 2233 2234 Inst.addOperand( 2235 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2236 return S; 2237 } 2238 2239 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2240 } 2241 2242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2243 return MCDisassembler::Fail; 2244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2245 return MCDisassembler::Fail; // Tied 2246 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2247 return MCDisassembler::Fail; 2248 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2249 return MCDisassembler::Fail; 2250 2251 return S; 2252 } 2253 2254 // Check for UNPREDICTABLE predicated ESB instruction 2255 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2256 uint64_t Address, const void *Decoder) { 2257 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2258 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2259 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2260 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2261 2262 DecodeStatus S = MCDisassembler::Success; 2263 2264 Inst.addOperand(MCOperand::createImm(imm8)); 2265 2266 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2267 return MCDisassembler::Fail; 2268 2269 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2270 // so all predicates should be allowed. 2271 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2272 S = MCDisassembler::SoftFail; 2273 2274 return S; 2275 } 2276 2277 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2278 uint64_t Address, const void *Decoder) { 2279 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2280 unsigned M = fieldFromInstruction(Insn, 17, 1); 2281 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2282 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2283 2284 DecodeStatus S = MCDisassembler::Success; 2285 2286 // This decoder is called from multiple location that do not check 2287 // the full encoding is valid before they do. 2288 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2289 fieldFromInstruction(Insn, 16, 1) != 0 || 2290 fieldFromInstruction(Insn, 20, 8) != 0x10) 2291 return MCDisassembler::Fail; 2292 2293 // imod == '01' --> UNPREDICTABLE 2294 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2295 // return failure here. The '01' imod value is unprintable, so there's 2296 // nothing useful we could do even if we returned UNPREDICTABLE. 2297 2298 if (imod == 1) return MCDisassembler::Fail; 2299 2300 if (imod && M) { 2301 Inst.setOpcode(ARM::CPS3p); 2302 Inst.addOperand(MCOperand::createImm(imod)); 2303 Inst.addOperand(MCOperand::createImm(iflags)); 2304 Inst.addOperand(MCOperand::createImm(mode)); 2305 } else if (imod && !M) { 2306 Inst.setOpcode(ARM::CPS2p); 2307 Inst.addOperand(MCOperand::createImm(imod)); 2308 Inst.addOperand(MCOperand::createImm(iflags)); 2309 if (mode) S = MCDisassembler::SoftFail; 2310 } else if (!imod && M) { 2311 Inst.setOpcode(ARM::CPS1p); 2312 Inst.addOperand(MCOperand::createImm(mode)); 2313 if (iflags) S = MCDisassembler::SoftFail; 2314 } else { 2315 // imod == '00' && M == '0' --> UNPREDICTABLE 2316 Inst.setOpcode(ARM::CPS1p); 2317 Inst.addOperand(MCOperand::createImm(mode)); 2318 S = MCDisassembler::SoftFail; 2319 } 2320 2321 return S; 2322 } 2323 2324 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2325 uint64_t Address, const void *Decoder) { 2326 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2327 unsigned M = fieldFromInstruction(Insn, 8, 1); 2328 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2329 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2330 2331 DecodeStatus S = MCDisassembler::Success; 2332 2333 // imod == '01' --> UNPREDICTABLE 2334 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2335 // return failure here. The '01' imod value is unprintable, so there's 2336 // nothing useful we could do even if we returned UNPREDICTABLE. 2337 2338 if (imod == 1) return MCDisassembler::Fail; 2339 2340 if (imod && M) { 2341 Inst.setOpcode(ARM::t2CPS3p); 2342 Inst.addOperand(MCOperand::createImm(imod)); 2343 Inst.addOperand(MCOperand::createImm(iflags)); 2344 Inst.addOperand(MCOperand::createImm(mode)); 2345 } else if (imod && !M) { 2346 Inst.setOpcode(ARM::t2CPS2p); 2347 Inst.addOperand(MCOperand::createImm(imod)); 2348 Inst.addOperand(MCOperand::createImm(iflags)); 2349 if (mode) S = MCDisassembler::SoftFail; 2350 } else if (!imod && M) { 2351 Inst.setOpcode(ARM::t2CPS1p); 2352 Inst.addOperand(MCOperand::createImm(mode)); 2353 if (iflags) S = MCDisassembler::SoftFail; 2354 } else { 2355 // imod == '00' && M == '0' --> this is a HINT instruction 2356 int imm = fieldFromInstruction(Insn, 0, 8); 2357 // HINT are defined only for immediate in [0..4] 2358 if(imm > 4) return MCDisassembler::Fail; 2359 Inst.setOpcode(ARM::t2HINT); 2360 Inst.addOperand(MCOperand::createImm(imm)); 2361 } 2362 2363 return S; 2364 } 2365 2366 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2367 uint64_t Address, const void *Decoder) { 2368 DecodeStatus S = MCDisassembler::Success; 2369 2370 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2371 unsigned imm = 0; 2372 2373 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2374 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2375 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2376 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2377 2378 if (Inst.getOpcode() == ARM::t2MOVTi16) 2379 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2380 return MCDisassembler::Fail; 2381 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2382 return MCDisassembler::Fail; 2383 2384 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2385 Inst.addOperand(MCOperand::createImm(imm)); 2386 2387 return S; 2388 } 2389 2390 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2391 uint64_t Address, const void *Decoder) { 2392 DecodeStatus S = MCDisassembler::Success; 2393 2394 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2395 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2396 unsigned imm = 0; 2397 2398 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2399 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2400 2401 if (Inst.getOpcode() == ARM::MOVTi16) 2402 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2403 return MCDisassembler::Fail; 2404 2405 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2406 return MCDisassembler::Fail; 2407 2408 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2409 Inst.addOperand(MCOperand::createImm(imm)); 2410 2411 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2412 return MCDisassembler::Fail; 2413 2414 return S; 2415 } 2416 2417 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2418 uint64_t Address, const void *Decoder) { 2419 DecodeStatus S = MCDisassembler::Success; 2420 2421 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2422 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2423 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2424 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2425 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2426 2427 if (pred == 0xF) 2428 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2429 2430 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2431 return MCDisassembler::Fail; 2432 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2433 return MCDisassembler::Fail; 2434 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2435 return MCDisassembler::Fail; 2436 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2437 return MCDisassembler::Fail; 2438 2439 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2440 return MCDisassembler::Fail; 2441 2442 return S; 2443 } 2444 2445 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2446 uint64_t Address, const void *Decoder) { 2447 DecodeStatus S = MCDisassembler::Success; 2448 2449 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2450 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2451 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2452 2453 if (Pred == 0xF) 2454 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2455 2456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2457 return MCDisassembler::Fail; 2458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2459 return MCDisassembler::Fail; 2460 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2461 return MCDisassembler::Fail; 2462 2463 return S; 2464 } 2465 2466 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2467 uint64_t Address, const void *Decoder) { 2468 DecodeStatus S = MCDisassembler::Success; 2469 2470 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2471 2472 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2473 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2474 2475 if (!FeatureBits[ARM::HasV8_1aOps] || 2476 !FeatureBits[ARM::HasV8Ops]) 2477 return MCDisassembler::Fail; 2478 2479 // Decoder can be called from DecodeTST, which does not check the full 2480 // encoding is valid. 2481 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2482 fieldFromInstruction(Insn, 4,4) != 0) 2483 return MCDisassembler::Fail; 2484 if (fieldFromInstruction(Insn, 10,10) != 0 || 2485 fieldFromInstruction(Insn, 0,4) != 0) 2486 S = MCDisassembler::SoftFail; 2487 2488 Inst.setOpcode(ARM::SETPAN); 2489 Inst.addOperand(MCOperand::createImm(Imm)); 2490 2491 return S; 2492 } 2493 2494 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2495 uint64_t Address, const void *Decoder) { 2496 DecodeStatus S = MCDisassembler::Success; 2497 2498 unsigned add = fieldFromInstruction(Val, 12, 1); 2499 unsigned imm = fieldFromInstruction(Val, 0, 12); 2500 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2501 2502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2503 return MCDisassembler::Fail; 2504 2505 if (!add) imm *= -1; 2506 if (imm == 0 && !add) imm = INT32_MIN; 2507 Inst.addOperand(MCOperand::createImm(imm)); 2508 if (Rn == 15) 2509 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2510 2511 return S; 2512 } 2513 2514 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2515 uint64_t Address, const void *Decoder) { 2516 DecodeStatus S = MCDisassembler::Success; 2517 2518 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2519 // U == 1 to add imm, 0 to subtract it. 2520 unsigned U = fieldFromInstruction(Val, 8, 1); 2521 unsigned imm = fieldFromInstruction(Val, 0, 8); 2522 2523 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2524 return MCDisassembler::Fail; 2525 2526 if (U) 2527 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2528 else 2529 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2530 2531 return S; 2532 } 2533 2534 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2535 uint64_t Address, const void *Decoder) { 2536 DecodeStatus S = MCDisassembler::Success; 2537 2538 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2539 // U == 1 to add imm, 0 to subtract it. 2540 unsigned U = fieldFromInstruction(Val, 8, 1); 2541 unsigned imm = fieldFromInstruction(Val, 0, 8); 2542 2543 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2544 return MCDisassembler::Fail; 2545 2546 if (U) 2547 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2548 else 2549 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2550 2551 return S; 2552 } 2553 2554 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2555 uint64_t Address, const void *Decoder) { 2556 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2557 } 2558 2559 static DecodeStatus 2560 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2561 uint64_t Address, const void *Decoder) { 2562 DecodeStatus Status = MCDisassembler::Success; 2563 2564 // Note the J1 and J2 values are from the encoded instruction. So here 2565 // change them to I1 and I2 values via as documented: 2566 // I1 = NOT(J1 EOR S); 2567 // I2 = NOT(J2 EOR S); 2568 // and build the imm32 with one trailing zero as documented: 2569 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2570 unsigned S = fieldFromInstruction(Insn, 26, 1); 2571 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2572 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2573 unsigned I1 = !(J1 ^ S); 2574 unsigned I2 = !(J2 ^ S); 2575 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2576 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2577 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2578 int imm32 = SignExtend32<25>(tmp << 1); 2579 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2580 true, 4, Inst, Decoder)) 2581 Inst.addOperand(MCOperand::createImm(imm32)); 2582 2583 return Status; 2584 } 2585 2586 static DecodeStatus 2587 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2588 uint64_t Address, const void *Decoder) { 2589 DecodeStatus S = MCDisassembler::Success; 2590 2591 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2592 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2593 2594 if (pred == 0xF) { 2595 Inst.setOpcode(ARM::BLXi); 2596 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2597 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2598 true, 4, Inst, Decoder)) 2599 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2600 return S; 2601 } 2602 2603 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2604 true, 4, Inst, Decoder)) 2605 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2606 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2607 return MCDisassembler::Fail; 2608 2609 return S; 2610 } 2611 2612 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2613 uint64_t Address, const void *Decoder) { 2614 DecodeStatus S = MCDisassembler::Success; 2615 2616 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2617 unsigned align = fieldFromInstruction(Val, 4, 2); 2618 2619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2620 return MCDisassembler::Fail; 2621 if (!align) 2622 Inst.addOperand(MCOperand::createImm(0)); 2623 else 2624 Inst.addOperand(MCOperand::createImm(4 << align)); 2625 2626 return S; 2627 } 2628 2629 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2630 uint64_t Address, const void *Decoder) { 2631 DecodeStatus S = MCDisassembler::Success; 2632 2633 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2634 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2635 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2636 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2637 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2638 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2639 2640 // First output register 2641 switch (Inst.getOpcode()) { 2642 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2643 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2644 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2645 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2646 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2647 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2648 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2649 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2650 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2651 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2652 return MCDisassembler::Fail; 2653 break; 2654 case ARM::VLD2b16: 2655 case ARM::VLD2b32: 2656 case ARM::VLD2b8: 2657 case ARM::VLD2b16wb_fixed: 2658 case ARM::VLD2b16wb_register: 2659 case ARM::VLD2b32wb_fixed: 2660 case ARM::VLD2b32wb_register: 2661 case ARM::VLD2b8wb_fixed: 2662 case ARM::VLD2b8wb_register: 2663 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2664 return MCDisassembler::Fail; 2665 break; 2666 default: 2667 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2668 return MCDisassembler::Fail; 2669 } 2670 2671 // Second output register 2672 switch (Inst.getOpcode()) { 2673 case ARM::VLD3d8: 2674 case ARM::VLD3d16: 2675 case ARM::VLD3d32: 2676 case ARM::VLD3d8_UPD: 2677 case ARM::VLD3d16_UPD: 2678 case ARM::VLD3d32_UPD: 2679 case ARM::VLD4d8: 2680 case ARM::VLD4d16: 2681 case ARM::VLD4d32: 2682 case ARM::VLD4d8_UPD: 2683 case ARM::VLD4d16_UPD: 2684 case ARM::VLD4d32_UPD: 2685 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2686 return MCDisassembler::Fail; 2687 break; 2688 case ARM::VLD3q8: 2689 case ARM::VLD3q16: 2690 case ARM::VLD3q32: 2691 case ARM::VLD3q8_UPD: 2692 case ARM::VLD3q16_UPD: 2693 case ARM::VLD3q32_UPD: 2694 case ARM::VLD4q8: 2695 case ARM::VLD4q16: 2696 case ARM::VLD4q32: 2697 case ARM::VLD4q8_UPD: 2698 case ARM::VLD4q16_UPD: 2699 case ARM::VLD4q32_UPD: 2700 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2701 return MCDisassembler::Fail; 2702 break; 2703 default: 2704 break; 2705 } 2706 2707 // Third output register 2708 switch(Inst.getOpcode()) { 2709 case ARM::VLD3d8: 2710 case ARM::VLD3d16: 2711 case ARM::VLD3d32: 2712 case ARM::VLD3d8_UPD: 2713 case ARM::VLD3d16_UPD: 2714 case ARM::VLD3d32_UPD: 2715 case ARM::VLD4d8: 2716 case ARM::VLD4d16: 2717 case ARM::VLD4d32: 2718 case ARM::VLD4d8_UPD: 2719 case ARM::VLD4d16_UPD: 2720 case ARM::VLD4d32_UPD: 2721 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 break; 2724 case ARM::VLD3q8: 2725 case ARM::VLD3q16: 2726 case ARM::VLD3q32: 2727 case ARM::VLD3q8_UPD: 2728 case ARM::VLD3q16_UPD: 2729 case ARM::VLD3q32_UPD: 2730 case ARM::VLD4q8: 2731 case ARM::VLD4q16: 2732 case ARM::VLD4q32: 2733 case ARM::VLD4q8_UPD: 2734 case ARM::VLD4q16_UPD: 2735 case ARM::VLD4q32_UPD: 2736 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2737 return MCDisassembler::Fail; 2738 break; 2739 default: 2740 break; 2741 } 2742 2743 // Fourth output register 2744 switch (Inst.getOpcode()) { 2745 case ARM::VLD4d8: 2746 case ARM::VLD4d16: 2747 case ARM::VLD4d32: 2748 case ARM::VLD4d8_UPD: 2749 case ARM::VLD4d16_UPD: 2750 case ARM::VLD4d32_UPD: 2751 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2752 return MCDisassembler::Fail; 2753 break; 2754 case ARM::VLD4q8: 2755 case ARM::VLD4q16: 2756 case ARM::VLD4q32: 2757 case ARM::VLD4q8_UPD: 2758 case ARM::VLD4q16_UPD: 2759 case ARM::VLD4q32_UPD: 2760 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2761 return MCDisassembler::Fail; 2762 break; 2763 default: 2764 break; 2765 } 2766 2767 // Writeback operand 2768 switch (Inst.getOpcode()) { 2769 case ARM::VLD1d8wb_fixed: 2770 case ARM::VLD1d16wb_fixed: 2771 case ARM::VLD1d32wb_fixed: 2772 case ARM::VLD1d64wb_fixed: 2773 case ARM::VLD1d8wb_register: 2774 case ARM::VLD1d16wb_register: 2775 case ARM::VLD1d32wb_register: 2776 case ARM::VLD1d64wb_register: 2777 case ARM::VLD1q8wb_fixed: 2778 case ARM::VLD1q16wb_fixed: 2779 case ARM::VLD1q32wb_fixed: 2780 case ARM::VLD1q64wb_fixed: 2781 case ARM::VLD1q8wb_register: 2782 case ARM::VLD1q16wb_register: 2783 case ARM::VLD1q32wb_register: 2784 case ARM::VLD1q64wb_register: 2785 case ARM::VLD1d8Twb_fixed: 2786 case ARM::VLD1d8Twb_register: 2787 case ARM::VLD1d16Twb_fixed: 2788 case ARM::VLD1d16Twb_register: 2789 case ARM::VLD1d32Twb_fixed: 2790 case ARM::VLD1d32Twb_register: 2791 case ARM::VLD1d64Twb_fixed: 2792 case ARM::VLD1d64Twb_register: 2793 case ARM::VLD1d8Qwb_fixed: 2794 case ARM::VLD1d8Qwb_register: 2795 case ARM::VLD1d16Qwb_fixed: 2796 case ARM::VLD1d16Qwb_register: 2797 case ARM::VLD1d32Qwb_fixed: 2798 case ARM::VLD1d32Qwb_register: 2799 case ARM::VLD1d64Qwb_fixed: 2800 case ARM::VLD1d64Qwb_register: 2801 case ARM::VLD2d8wb_fixed: 2802 case ARM::VLD2d16wb_fixed: 2803 case ARM::VLD2d32wb_fixed: 2804 case ARM::VLD2q8wb_fixed: 2805 case ARM::VLD2q16wb_fixed: 2806 case ARM::VLD2q32wb_fixed: 2807 case ARM::VLD2d8wb_register: 2808 case ARM::VLD2d16wb_register: 2809 case ARM::VLD2d32wb_register: 2810 case ARM::VLD2q8wb_register: 2811 case ARM::VLD2q16wb_register: 2812 case ARM::VLD2q32wb_register: 2813 case ARM::VLD2b8wb_fixed: 2814 case ARM::VLD2b16wb_fixed: 2815 case ARM::VLD2b32wb_fixed: 2816 case ARM::VLD2b8wb_register: 2817 case ARM::VLD2b16wb_register: 2818 case ARM::VLD2b32wb_register: 2819 Inst.addOperand(MCOperand::createImm(0)); 2820 break; 2821 case ARM::VLD3d8_UPD: 2822 case ARM::VLD3d16_UPD: 2823 case ARM::VLD3d32_UPD: 2824 case ARM::VLD3q8_UPD: 2825 case ARM::VLD3q16_UPD: 2826 case ARM::VLD3q32_UPD: 2827 case ARM::VLD4d8_UPD: 2828 case ARM::VLD4d16_UPD: 2829 case ARM::VLD4d32_UPD: 2830 case ARM::VLD4q8_UPD: 2831 case ARM::VLD4q16_UPD: 2832 case ARM::VLD4q32_UPD: 2833 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 break; 2836 default: 2837 break; 2838 } 2839 2840 // AddrMode6 Base (register+alignment) 2841 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2842 return MCDisassembler::Fail; 2843 2844 // AddrMode6 Offset (register) 2845 switch (Inst.getOpcode()) { 2846 default: 2847 // The below have been updated to have explicit am6offset split 2848 // between fixed and register offset. For those instructions not 2849 // yet updated, we need to add an additional reg0 operand for the 2850 // fixed variant. 2851 // 2852 // The fixed offset encodes as Rm == 0xd, so we check for that. 2853 if (Rm == 0xd) { 2854 Inst.addOperand(MCOperand::createReg(0)); 2855 break; 2856 } 2857 // Fall through to handle the register offset variant. 2858 LLVM_FALLTHROUGH; 2859 case ARM::VLD1d8wb_fixed: 2860 case ARM::VLD1d16wb_fixed: 2861 case ARM::VLD1d32wb_fixed: 2862 case ARM::VLD1d64wb_fixed: 2863 case ARM::VLD1d8Twb_fixed: 2864 case ARM::VLD1d16Twb_fixed: 2865 case ARM::VLD1d32Twb_fixed: 2866 case ARM::VLD1d64Twb_fixed: 2867 case ARM::VLD1d8Qwb_fixed: 2868 case ARM::VLD1d16Qwb_fixed: 2869 case ARM::VLD1d32Qwb_fixed: 2870 case ARM::VLD1d64Qwb_fixed: 2871 case ARM::VLD1d8wb_register: 2872 case ARM::VLD1d16wb_register: 2873 case ARM::VLD1d32wb_register: 2874 case ARM::VLD1d64wb_register: 2875 case ARM::VLD1q8wb_fixed: 2876 case ARM::VLD1q16wb_fixed: 2877 case ARM::VLD1q32wb_fixed: 2878 case ARM::VLD1q64wb_fixed: 2879 case ARM::VLD1q8wb_register: 2880 case ARM::VLD1q16wb_register: 2881 case ARM::VLD1q32wb_register: 2882 case ARM::VLD1q64wb_register: 2883 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2884 // variant encodes Rm == 0xf. Anything else is a register offset post- 2885 // increment and we need to add the register operand to the instruction. 2886 if (Rm != 0xD && Rm != 0xF && 2887 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2888 return MCDisassembler::Fail; 2889 break; 2890 case ARM::VLD2d8wb_fixed: 2891 case ARM::VLD2d16wb_fixed: 2892 case ARM::VLD2d32wb_fixed: 2893 case ARM::VLD2b8wb_fixed: 2894 case ARM::VLD2b16wb_fixed: 2895 case ARM::VLD2b32wb_fixed: 2896 case ARM::VLD2q8wb_fixed: 2897 case ARM::VLD2q16wb_fixed: 2898 case ARM::VLD2q32wb_fixed: 2899 break; 2900 } 2901 2902 return S; 2903 } 2904 2905 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2906 uint64_t Address, const void *Decoder) { 2907 unsigned type = fieldFromInstruction(Insn, 8, 4); 2908 unsigned align = fieldFromInstruction(Insn, 4, 2); 2909 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2910 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2911 if (type == 10 && align == 3) return MCDisassembler::Fail; 2912 2913 unsigned load = fieldFromInstruction(Insn, 21, 1); 2914 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2915 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2916 } 2917 2918 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2919 uint64_t Address, const void *Decoder) { 2920 unsigned size = fieldFromInstruction(Insn, 6, 2); 2921 if (size == 3) return MCDisassembler::Fail; 2922 2923 unsigned type = fieldFromInstruction(Insn, 8, 4); 2924 unsigned align = fieldFromInstruction(Insn, 4, 2); 2925 if (type == 8 && align == 3) return MCDisassembler::Fail; 2926 if (type == 9 && align == 3) return MCDisassembler::Fail; 2927 2928 unsigned load = fieldFromInstruction(Insn, 21, 1); 2929 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2930 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2931 } 2932 2933 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2934 uint64_t Address, const void *Decoder) { 2935 unsigned size = fieldFromInstruction(Insn, 6, 2); 2936 if (size == 3) return MCDisassembler::Fail; 2937 2938 unsigned align = fieldFromInstruction(Insn, 4, 2); 2939 if (align & 2) return MCDisassembler::Fail; 2940 2941 unsigned load = fieldFromInstruction(Insn, 21, 1); 2942 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2943 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2944 } 2945 2946 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2947 uint64_t Address, const void *Decoder) { 2948 unsigned size = fieldFromInstruction(Insn, 6, 2); 2949 if (size == 3) return MCDisassembler::Fail; 2950 2951 unsigned load = fieldFromInstruction(Insn, 21, 1); 2952 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2953 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2954 } 2955 2956 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2957 uint64_t Address, const void *Decoder) { 2958 DecodeStatus S = MCDisassembler::Success; 2959 2960 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2961 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2962 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2963 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2964 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2965 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2966 2967 // Writeback Operand 2968 switch (Inst.getOpcode()) { 2969 case ARM::VST1d8wb_fixed: 2970 case ARM::VST1d16wb_fixed: 2971 case ARM::VST1d32wb_fixed: 2972 case ARM::VST1d64wb_fixed: 2973 case ARM::VST1d8wb_register: 2974 case ARM::VST1d16wb_register: 2975 case ARM::VST1d32wb_register: 2976 case ARM::VST1d64wb_register: 2977 case ARM::VST1q8wb_fixed: 2978 case ARM::VST1q16wb_fixed: 2979 case ARM::VST1q32wb_fixed: 2980 case ARM::VST1q64wb_fixed: 2981 case ARM::VST1q8wb_register: 2982 case ARM::VST1q16wb_register: 2983 case ARM::VST1q32wb_register: 2984 case ARM::VST1q64wb_register: 2985 case ARM::VST1d8Twb_fixed: 2986 case ARM::VST1d16Twb_fixed: 2987 case ARM::VST1d32Twb_fixed: 2988 case ARM::VST1d64Twb_fixed: 2989 case ARM::VST1d8Twb_register: 2990 case ARM::VST1d16Twb_register: 2991 case ARM::VST1d32Twb_register: 2992 case ARM::VST1d64Twb_register: 2993 case ARM::VST1d8Qwb_fixed: 2994 case ARM::VST1d16Qwb_fixed: 2995 case ARM::VST1d32Qwb_fixed: 2996 case ARM::VST1d64Qwb_fixed: 2997 case ARM::VST1d8Qwb_register: 2998 case ARM::VST1d16Qwb_register: 2999 case ARM::VST1d32Qwb_register: 3000 case ARM::VST1d64Qwb_register: 3001 case ARM::VST2d8wb_fixed: 3002 case ARM::VST2d16wb_fixed: 3003 case ARM::VST2d32wb_fixed: 3004 case ARM::VST2d8wb_register: 3005 case ARM::VST2d16wb_register: 3006 case ARM::VST2d32wb_register: 3007 case ARM::VST2q8wb_fixed: 3008 case ARM::VST2q16wb_fixed: 3009 case ARM::VST2q32wb_fixed: 3010 case ARM::VST2q8wb_register: 3011 case ARM::VST2q16wb_register: 3012 case ARM::VST2q32wb_register: 3013 case ARM::VST2b8wb_fixed: 3014 case ARM::VST2b16wb_fixed: 3015 case ARM::VST2b32wb_fixed: 3016 case ARM::VST2b8wb_register: 3017 case ARM::VST2b16wb_register: 3018 case ARM::VST2b32wb_register: 3019 if (Rm == 0xF) 3020 return MCDisassembler::Fail; 3021 Inst.addOperand(MCOperand::createImm(0)); 3022 break; 3023 case ARM::VST3d8_UPD: 3024 case ARM::VST3d16_UPD: 3025 case ARM::VST3d32_UPD: 3026 case ARM::VST3q8_UPD: 3027 case ARM::VST3q16_UPD: 3028 case ARM::VST3q32_UPD: 3029 case ARM::VST4d8_UPD: 3030 case ARM::VST4d16_UPD: 3031 case ARM::VST4d32_UPD: 3032 case ARM::VST4q8_UPD: 3033 case ARM::VST4q16_UPD: 3034 case ARM::VST4q32_UPD: 3035 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3036 return MCDisassembler::Fail; 3037 break; 3038 default: 3039 break; 3040 } 3041 3042 // AddrMode6 Base (register+alignment) 3043 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3044 return MCDisassembler::Fail; 3045 3046 // AddrMode6 Offset (register) 3047 switch (Inst.getOpcode()) { 3048 default: 3049 if (Rm == 0xD) 3050 Inst.addOperand(MCOperand::createReg(0)); 3051 else if (Rm != 0xF) { 3052 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3053 return MCDisassembler::Fail; 3054 } 3055 break; 3056 case ARM::VST1d8wb_fixed: 3057 case ARM::VST1d16wb_fixed: 3058 case ARM::VST1d32wb_fixed: 3059 case ARM::VST1d64wb_fixed: 3060 case ARM::VST1q8wb_fixed: 3061 case ARM::VST1q16wb_fixed: 3062 case ARM::VST1q32wb_fixed: 3063 case ARM::VST1q64wb_fixed: 3064 case ARM::VST1d8Twb_fixed: 3065 case ARM::VST1d16Twb_fixed: 3066 case ARM::VST1d32Twb_fixed: 3067 case ARM::VST1d64Twb_fixed: 3068 case ARM::VST1d8Qwb_fixed: 3069 case ARM::VST1d16Qwb_fixed: 3070 case ARM::VST1d32Qwb_fixed: 3071 case ARM::VST1d64Qwb_fixed: 3072 case ARM::VST2d8wb_fixed: 3073 case ARM::VST2d16wb_fixed: 3074 case ARM::VST2d32wb_fixed: 3075 case ARM::VST2q8wb_fixed: 3076 case ARM::VST2q16wb_fixed: 3077 case ARM::VST2q32wb_fixed: 3078 case ARM::VST2b8wb_fixed: 3079 case ARM::VST2b16wb_fixed: 3080 case ARM::VST2b32wb_fixed: 3081 break; 3082 } 3083 3084 // First input register 3085 switch (Inst.getOpcode()) { 3086 case ARM::VST1q16: 3087 case ARM::VST1q32: 3088 case ARM::VST1q64: 3089 case ARM::VST1q8: 3090 case ARM::VST1q16wb_fixed: 3091 case ARM::VST1q16wb_register: 3092 case ARM::VST1q32wb_fixed: 3093 case ARM::VST1q32wb_register: 3094 case ARM::VST1q64wb_fixed: 3095 case ARM::VST1q64wb_register: 3096 case ARM::VST1q8wb_fixed: 3097 case ARM::VST1q8wb_register: 3098 case ARM::VST2d16: 3099 case ARM::VST2d32: 3100 case ARM::VST2d8: 3101 case ARM::VST2d16wb_fixed: 3102 case ARM::VST2d16wb_register: 3103 case ARM::VST2d32wb_fixed: 3104 case ARM::VST2d32wb_register: 3105 case ARM::VST2d8wb_fixed: 3106 case ARM::VST2d8wb_register: 3107 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3108 return MCDisassembler::Fail; 3109 break; 3110 case ARM::VST2b16: 3111 case ARM::VST2b32: 3112 case ARM::VST2b8: 3113 case ARM::VST2b16wb_fixed: 3114 case ARM::VST2b16wb_register: 3115 case ARM::VST2b32wb_fixed: 3116 case ARM::VST2b32wb_register: 3117 case ARM::VST2b8wb_fixed: 3118 case ARM::VST2b8wb_register: 3119 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3120 return MCDisassembler::Fail; 3121 break; 3122 default: 3123 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3124 return MCDisassembler::Fail; 3125 } 3126 3127 // Second input register 3128 switch (Inst.getOpcode()) { 3129 case ARM::VST3d8: 3130 case ARM::VST3d16: 3131 case ARM::VST3d32: 3132 case ARM::VST3d8_UPD: 3133 case ARM::VST3d16_UPD: 3134 case ARM::VST3d32_UPD: 3135 case ARM::VST4d8: 3136 case ARM::VST4d16: 3137 case ARM::VST4d32: 3138 case ARM::VST4d8_UPD: 3139 case ARM::VST4d16_UPD: 3140 case ARM::VST4d32_UPD: 3141 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3142 return MCDisassembler::Fail; 3143 break; 3144 case ARM::VST3q8: 3145 case ARM::VST3q16: 3146 case ARM::VST3q32: 3147 case ARM::VST3q8_UPD: 3148 case ARM::VST3q16_UPD: 3149 case ARM::VST3q32_UPD: 3150 case ARM::VST4q8: 3151 case ARM::VST4q16: 3152 case ARM::VST4q32: 3153 case ARM::VST4q8_UPD: 3154 case ARM::VST4q16_UPD: 3155 case ARM::VST4q32_UPD: 3156 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3157 return MCDisassembler::Fail; 3158 break; 3159 default: 3160 break; 3161 } 3162 3163 // Third input register 3164 switch (Inst.getOpcode()) { 3165 case ARM::VST3d8: 3166 case ARM::VST3d16: 3167 case ARM::VST3d32: 3168 case ARM::VST3d8_UPD: 3169 case ARM::VST3d16_UPD: 3170 case ARM::VST3d32_UPD: 3171 case ARM::VST4d8: 3172 case ARM::VST4d16: 3173 case ARM::VST4d32: 3174 case ARM::VST4d8_UPD: 3175 case ARM::VST4d16_UPD: 3176 case ARM::VST4d32_UPD: 3177 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3178 return MCDisassembler::Fail; 3179 break; 3180 case ARM::VST3q8: 3181 case ARM::VST3q16: 3182 case ARM::VST3q32: 3183 case ARM::VST3q8_UPD: 3184 case ARM::VST3q16_UPD: 3185 case ARM::VST3q32_UPD: 3186 case ARM::VST4q8: 3187 case ARM::VST4q16: 3188 case ARM::VST4q32: 3189 case ARM::VST4q8_UPD: 3190 case ARM::VST4q16_UPD: 3191 case ARM::VST4q32_UPD: 3192 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3193 return MCDisassembler::Fail; 3194 break; 3195 default: 3196 break; 3197 } 3198 3199 // Fourth input register 3200 switch (Inst.getOpcode()) { 3201 case ARM::VST4d8: 3202 case ARM::VST4d16: 3203 case ARM::VST4d32: 3204 case ARM::VST4d8_UPD: 3205 case ARM::VST4d16_UPD: 3206 case ARM::VST4d32_UPD: 3207 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3208 return MCDisassembler::Fail; 3209 break; 3210 case ARM::VST4q8: 3211 case ARM::VST4q16: 3212 case ARM::VST4q32: 3213 case ARM::VST4q8_UPD: 3214 case ARM::VST4q16_UPD: 3215 case ARM::VST4q32_UPD: 3216 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3217 return MCDisassembler::Fail; 3218 break; 3219 default: 3220 break; 3221 } 3222 3223 return S; 3224 } 3225 3226 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3227 uint64_t Address, const void *Decoder) { 3228 DecodeStatus S = MCDisassembler::Success; 3229 3230 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3231 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3232 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3233 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3234 unsigned align = fieldFromInstruction(Insn, 4, 1); 3235 unsigned size = fieldFromInstruction(Insn, 6, 2); 3236 3237 if (size == 0 && align == 1) 3238 return MCDisassembler::Fail; 3239 align *= (1 << size); 3240 3241 switch (Inst.getOpcode()) { 3242 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3243 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3244 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3245 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3246 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3247 return MCDisassembler::Fail; 3248 break; 3249 default: 3250 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3251 return MCDisassembler::Fail; 3252 break; 3253 } 3254 if (Rm != 0xF) { 3255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3256 return MCDisassembler::Fail; 3257 } 3258 3259 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 Inst.addOperand(MCOperand::createImm(align)); 3262 3263 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3264 // variant encodes Rm == 0xf. Anything else is a register offset post- 3265 // increment and we need to add the register operand to the instruction. 3266 if (Rm != 0xD && Rm != 0xF && 3267 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3268 return MCDisassembler::Fail; 3269 3270 return S; 3271 } 3272 3273 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3274 uint64_t Address, const void *Decoder) { 3275 DecodeStatus S = MCDisassembler::Success; 3276 3277 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3278 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3279 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3280 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3281 unsigned align = fieldFromInstruction(Insn, 4, 1); 3282 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3283 align *= 2*size; 3284 3285 switch (Inst.getOpcode()) { 3286 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3287 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3288 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3289 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3290 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3291 return MCDisassembler::Fail; 3292 break; 3293 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3294 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3295 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3296 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3297 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3298 return MCDisassembler::Fail; 3299 break; 3300 default: 3301 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3302 return MCDisassembler::Fail; 3303 break; 3304 } 3305 3306 if (Rm != 0xF) 3307 Inst.addOperand(MCOperand::createImm(0)); 3308 3309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3310 return MCDisassembler::Fail; 3311 Inst.addOperand(MCOperand::createImm(align)); 3312 3313 if (Rm != 0xD && Rm != 0xF) { 3314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3315 return MCDisassembler::Fail; 3316 } 3317 3318 return S; 3319 } 3320 3321 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3322 uint64_t Address, const void *Decoder) { 3323 DecodeStatus S = MCDisassembler::Success; 3324 3325 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3326 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3327 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3328 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3329 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3330 3331 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3334 return MCDisassembler::Fail; 3335 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3336 return MCDisassembler::Fail; 3337 if (Rm != 0xF) { 3338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3339 return MCDisassembler::Fail; 3340 } 3341 3342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3343 return MCDisassembler::Fail; 3344 Inst.addOperand(MCOperand::createImm(0)); 3345 3346 if (Rm == 0xD) 3347 Inst.addOperand(MCOperand::createReg(0)); 3348 else if (Rm != 0xF) { 3349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3350 return MCDisassembler::Fail; 3351 } 3352 3353 return S; 3354 } 3355 3356 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3357 uint64_t Address, const void *Decoder) { 3358 DecodeStatus S = MCDisassembler::Success; 3359 3360 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3361 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3362 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3363 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3364 unsigned size = fieldFromInstruction(Insn, 6, 2); 3365 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3366 unsigned align = fieldFromInstruction(Insn, 4, 1); 3367 3368 if (size == 0x3) { 3369 if (align == 0) 3370 return MCDisassembler::Fail; 3371 align = 16; 3372 } else { 3373 if (size == 2) { 3374 align *= 8; 3375 } else { 3376 size = 1 << size; 3377 align *= 4*size; 3378 } 3379 } 3380 3381 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3382 return MCDisassembler::Fail; 3383 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3384 return MCDisassembler::Fail; 3385 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3386 return MCDisassembler::Fail; 3387 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3388 return MCDisassembler::Fail; 3389 if (Rm != 0xF) { 3390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3391 return MCDisassembler::Fail; 3392 } 3393 3394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3395 return MCDisassembler::Fail; 3396 Inst.addOperand(MCOperand::createImm(align)); 3397 3398 if (Rm == 0xD) 3399 Inst.addOperand(MCOperand::createReg(0)); 3400 else if (Rm != 0xF) { 3401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3402 return MCDisassembler::Fail; 3403 } 3404 3405 return S; 3406 } 3407 3408 static DecodeStatus 3409 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3410 uint64_t Address, const void *Decoder) { 3411 DecodeStatus S = MCDisassembler::Success; 3412 3413 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3414 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3415 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3416 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3417 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3418 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3419 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3420 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3421 3422 if (Q) { 3423 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3424 return MCDisassembler::Fail; 3425 } else { 3426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3427 return MCDisassembler::Fail; 3428 } 3429 3430 Inst.addOperand(MCOperand::createImm(imm)); 3431 3432 switch (Inst.getOpcode()) { 3433 case ARM::VORRiv4i16: 3434 case ARM::VORRiv2i32: 3435 case ARM::VBICiv4i16: 3436 case ARM::VBICiv2i32: 3437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3438 return MCDisassembler::Fail; 3439 break; 3440 case ARM::VORRiv8i16: 3441 case ARM::VORRiv4i32: 3442 case ARM::VBICiv8i16: 3443 case ARM::VBICiv4i32: 3444 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3445 return MCDisassembler::Fail; 3446 break; 3447 default: 3448 break; 3449 } 3450 3451 return S; 3452 } 3453 3454 static DecodeStatus 3455 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3456 uint64_t Address, const void *Decoder) { 3457 DecodeStatus S = MCDisassembler::Success; 3458 3459 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3460 fieldFromInstruction(Insn, 13, 3)); 3461 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3462 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3463 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3464 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3465 imm |= cmode << 8; 3466 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3467 3468 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3469 return MCDisassembler::Fail; 3470 3471 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3472 return MCDisassembler::Fail; 3473 3474 Inst.addOperand(MCOperand::createImm(imm)); 3475 3476 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3477 Inst.addOperand(MCOperand::createReg(0)); 3478 Inst.addOperand(MCOperand::createImm(0)); 3479 3480 return S; 3481 } 3482 3483 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3484 uint64_t Address, const void *Decoder) { 3485 DecodeStatus S = MCDisassembler::Success; 3486 3487 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3488 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3489 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3490 return MCDisassembler::Fail; 3491 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3492 3493 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3494 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3495 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3496 return MCDisassembler::Fail; 3497 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3498 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3499 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3502 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3503 Inst.addOperand(MCOperand::createImm(Qd)); 3504 3505 return S; 3506 } 3507 3508 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3509 uint64_t Address, const void *Decoder) { 3510 DecodeStatus S = MCDisassembler::Success; 3511 3512 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3513 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3514 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3515 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3516 unsigned size = fieldFromInstruction(Insn, 18, 2); 3517 3518 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3519 return MCDisassembler::Fail; 3520 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3521 return MCDisassembler::Fail; 3522 Inst.addOperand(MCOperand::createImm(8 << size)); 3523 3524 return S; 3525 } 3526 3527 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3528 uint64_t Address, const void *Decoder) { 3529 Inst.addOperand(MCOperand::createImm(8 - Val)); 3530 return MCDisassembler::Success; 3531 } 3532 3533 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3534 uint64_t Address, const void *Decoder) { 3535 Inst.addOperand(MCOperand::createImm(16 - Val)); 3536 return MCDisassembler::Success; 3537 } 3538 3539 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3540 uint64_t Address, const void *Decoder) { 3541 Inst.addOperand(MCOperand::createImm(32 - Val)); 3542 return MCDisassembler::Success; 3543 } 3544 3545 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3546 uint64_t Address, const void *Decoder) { 3547 Inst.addOperand(MCOperand::createImm(64 - Val)); 3548 return MCDisassembler::Success; 3549 } 3550 3551 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3552 uint64_t Address, const void *Decoder) { 3553 DecodeStatus S = MCDisassembler::Success; 3554 3555 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3556 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3557 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3558 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3559 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3560 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3561 unsigned op = fieldFromInstruction(Insn, 6, 1); 3562 3563 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3564 return MCDisassembler::Fail; 3565 if (op) { 3566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3567 return MCDisassembler::Fail; // Writeback 3568 } 3569 3570 switch (Inst.getOpcode()) { 3571 case ARM::VTBL2: 3572 case ARM::VTBX2: 3573 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3574 return MCDisassembler::Fail; 3575 break; 3576 default: 3577 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3578 return MCDisassembler::Fail; 3579 } 3580 3581 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 3584 return S; 3585 } 3586 3587 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3588 uint64_t Address, const void *Decoder) { 3589 DecodeStatus S = MCDisassembler::Success; 3590 3591 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3592 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3593 3594 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3595 return MCDisassembler::Fail; 3596 3597 switch(Inst.getOpcode()) { 3598 default: 3599 return MCDisassembler::Fail; 3600 case ARM::tADR: 3601 break; // tADR does not explicitly represent the PC as an operand. 3602 case ARM::tADDrSPi: 3603 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3604 break; 3605 } 3606 3607 Inst.addOperand(MCOperand::createImm(imm)); 3608 return S; 3609 } 3610 3611 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3612 uint64_t Address, const void *Decoder) { 3613 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3614 true, 2, Inst, Decoder)) 3615 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3616 return MCDisassembler::Success; 3617 } 3618 3619 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3620 uint64_t Address, const void *Decoder) { 3621 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3622 true, 4, Inst, Decoder)) 3623 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3624 return MCDisassembler::Success; 3625 } 3626 3627 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3628 uint64_t Address, const void *Decoder) { 3629 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3630 true, 2, Inst, Decoder)) 3631 Inst.addOperand(MCOperand::createImm(Val << 1)); 3632 return MCDisassembler::Success; 3633 } 3634 3635 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3636 uint64_t Address, const void *Decoder) { 3637 DecodeStatus S = MCDisassembler::Success; 3638 3639 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3640 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3641 3642 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3645 return MCDisassembler::Fail; 3646 3647 return S; 3648 } 3649 3650 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3651 uint64_t Address, const void *Decoder) { 3652 DecodeStatus S = MCDisassembler::Success; 3653 3654 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3655 unsigned imm = fieldFromInstruction(Val, 3, 5); 3656 3657 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3658 return MCDisassembler::Fail; 3659 Inst.addOperand(MCOperand::createImm(imm)); 3660 3661 return S; 3662 } 3663 3664 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3665 uint64_t Address, const void *Decoder) { 3666 unsigned imm = Val << 2; 3667 3668 Inst.addOperand(MCOperand::createImm(imm)); 3669 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3670 3671 return MCDisassembler::Success; 3672 } 3673 3674 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3675 uint64_t Address, const void *Decoder) { 3676 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3677 Inst.addOperand(MCOperand::createImm(Val)); 3678 3679 return MCDisassembler::Success; 3680 } 3681 3682 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3683 uint64_t Address, const void *Decoder) { 3684 DecodeStatus S = MCDisassembler::Success; 3685 3686 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3687 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3688 unsigned imm = fieldFromInstruction(Val, 0, 2); 3689 3690 // Thumb stores cannot use PC as dest register. 3691 switch (Inst.getOpcode()) { 3692 case ARM::t2STRHs: 3693 case ARM::t2STRBs: 3694 case ARM::t2STRs: 3695 if (Rn == 15) 3696 return MCDisassembler::Fail; 3697 break; 3698 default: 3699 break; 3700 } 3701 3702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3703 return MCDisassembler::Fail; 3704 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3705 return MCDisassembler::Fail; 3706 Inst.addOperand(MCOperand::createImm(imm)); 3707 3708 return S; 3709 } 3710 3711 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3712 uint64_t Address, const void *Decoder) { 3713 DecodeStatus S = MCDisassembler::Success; 3714 3715 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3716 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3717 3718 const FeatureBitset &featureBits = 3719 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3720 3721 bool hasMP = featureBits[ARM::FeatureMP]; 3722 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3723 3724 if (Rn == 15) { 3725 switch (Inst.getOpcode()) { 3726 case ARM::t2LDRBs: 3727 Inst.setOpcode(ARM::t2LDRBpci); 3728 break; 3729 case ARM::t2LDRHs: 3730 Inst.setOpcode(ARM::t2LDRHpci); 3731 break; 3732 case ARM::t2LDRSHs: 3733 Inst.setOpcode(ARM::t2LDRSHpci); 3734 break; 3735 case ARM::t2LDRSBs: 3736 Inst.setOpcode(ARM::t2LDRSBpci); 3737 break; 3738 case ARM::t2LDRs: 3739 Inst.setOpcode(ARM::t2LDRpci); 3740 break; 3741 case ARM::t2PLDs: 3742 Inst.setOpcode(ARM::t2PLDpci); 3743 break; 3744 case ARM::t2PLIs: 3745 Inst.setOpcode(ARM::t2PLIpci); 3746 break; 3747 default: 3748 return MCDisassembler::Fail; 3749 } 3750 3751 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3752 } 3753 3754 if (Rt == 15) { 3755 switch (Inst.getOpcode()) { 3756 case ARM::t2LDRSHs: 3757 return MCDisassembler::Fail; 3758 case ARM::t2LDRHs: 3759 Inst.setOpcode(ARM::t2PLDWs); 3760 break; 3761 case ARM::t2LDRSBs: 3762 Inst.setOpcode(ARM::t2PLIs); 3763 break; 3764 default: 3765 break; 3766 } 3767 } 3768 3769 switch (Inst.getOpcode()) { 3770 case ARM::t2PLDs: 3771 break; 3772 case ARM::t2PLIs: 3773 if (!hasV7Ops) 3774 return MCDisassembler::Fail; 3775 break; 3776 case ARM::t2PLDWs: 3777 if (!hasV7Ops || !hasMP) 3778 return MCDisassembler::Fail; 3779 break; 3780 default: 3781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3782 return MCDisassembler::Fail; 3783 } 3784 3785 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3786 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3787 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3788 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3789 return MCDisassembler::Fail; 3790 3791 return S; 3792 } 3793 3794 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3795 uint64_t Address, const void* Decoder) { 3796 DecodeStatus S = MCDisassembler::Success; 3797 3798 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3799 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3800 unsigned U = fieldFromInstruction(Insn, 9, 1); 3801 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3802 imm |= (U << 8); 3803 imm |= (Rn << 9); 3804 unsigned add = fieldFromInstruction(Insn, 9, 1); 3805 3806 const FeatureBitset &featureBits = 3807 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3808 3809 bool hasMP = featureBits[ARM::FeatureMP]; 3810 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3811 3812 if (Rn == 15) { 3813 switch (Inst.getOpcode()) { 3814 case ARM::t2LDRi8: 3815 Inst.setOpcode(ARM::t2LDRpci); 3816 break; 3817 case ARM::t2LDRBi8: 3818 Inst.setOpcode(ARM::t2LDRBpci); 3819 break; 3820 case ARM::t2LDRSBi8: 3821 Inst.setOpcode(ARM::t2LDRSBpci); 3822 break; 3823 case ARM::t2LDRHi8: 3824 Inst.setOpcode(ARM::t2LDRHpci); 3825 break; 3826 case ARM::t2LDRSHi8: 3827 Inst.setOpcode(ARM::t2LDRSHpci); 3828 break; 3829 case ARM::t2PLDi8: 3830 Inst.setOpcode(ARM::t2PLDpci); 3831 break; 3832 case ARM::t2PLIi8: 3833 Inst.setOpcode(ARM::t2PLIpci); 3834 break; 3835 default: 3836 return MCDisassembler::Fail; 3837 } 3838 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3839 } 3840 3841 if (Rt == 15) { 3842 switch (Inst.getOpcode()) { 3843 case ARM::t2LDRSHi8: 3844 return MCDisassembler::Fail; 3845 case ARM::t2LDRHi8: 3846 if (!add) 3847 Inst.setOpcode(ARM::t2PLDWi8); 3848 break; 3849 case ARM::t2LDRSBi8: 3850 Inst.setOpcode(ARM::t2PLIi8); 3851 break; 3852 default: 3853 break; 3854 } 3855 } 3856 3857 switch (Inst.getOpcode()) { 3858 case ARM::t2PLDi8: 3859 break; 3860 case ARM::t2PLIi8: 3861 if (!hasV7Ops) 3862 return MCDisassembler::Fail; 3863 break; 3864 case ARM::t2PLDWi8: 3865 if (!hasV7Ops || !hasMP) 3866 return MCDisassembler::Fail; 3867 break; 3868 default: 3869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3870 return MCDisassembler::Fail; 3871 } 3872 3873 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3874 return MCDisassembler::Fail; 3875 return S; 3876 } 3877 3878 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3879 uint64_t Address, const void* Decoder) { 3880 DecodeStatus S = MCDisassembler::Success; 3881 3882 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3883 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3884 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3885 imm |= (Rn << 13); 3886 3887 const FeatureBitset &featureBits = 3888 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3889 3890 bool hasMP = featureBits[ARM::FeatureMP]; 3891 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3892 3893 if (Rn == 15) { 3894 switch (Inst.getOpcode()) { 3895 case ARM::t2LDRi12: 3896 Inst.setOpcode(ARM::t2LDRpci); 3897 break; 3898 case ARM::t2LDRHi12: 3899 Inst.setOpcode(ARM::t2LDRHpci); 3900 break; 3901 case ARM::t2LDRSHi12: 3902 Inst.setOpcode(ARM::t2LDRSHpci); 3903 break; 3904 case ARM::t2LDRBi12: 3905 Inst.setOpcode(ARM::t2LDRBpci); 3906 break; 3907 case ARM::t2LDRSBi12: 3908 Inst.setOpcode(ARM::t2LDRSBpci); 3909 break; 3910 case ARM::t2PLDi12: 3911 Inst.setOpcode(ARM::t2PLDpci); 3912 break; 3913 case ARM::t2PLIi12: 3914 Inst.setOpcode(ARM::t2PLIpci); 3915 break; 3916 default: 3917 return MCDisassembler::Fail; 3918 } 3919 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3920 } 3921 3922 if (Rt == 15) { 3923 switch (Inst.getOpcode()) { 3924 case ARM::t2LDRSHi12: 3925 return MCDisassembler::Fail; 3926 case ARM::t2LDRHi12: 3927 Inst.setOpcode(ARM::t2PLDWi12); 3928 break; 3929 case ARM::t2LDRSBi12: 3930 Inst.setOpcode(ARM::t2PLIi12); 3931 break; 3932 default: 3933 break; 3934 } 3935 } 3936 3937 switch (Inst.getOpcode()) { 3938 case ARM::t2PLDi12: 3939 break; 3940 case ARM::t2PLIi12: 3941 if (!hasV7Ops) 3942 return MCDisassembler::Fail; 3943 break; 3944 case ARM::t2PLDWi12: 3945 if (!hasV7Ops || !hasMP) 3946 return MCDisassembler::Fail; 3947 break; 3948 default: 3949 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3950 return MCDisassembler::Fail; 3951 } 3952 3953 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3954 return MCDisassembler::Fail; 3955 return S; 3956 } 3957 3958 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3959 uint64_t Address, const void* Decoder) { 3960 DecodeStatus S = MCDisassembler::Success; 3961 3962 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3963 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3964 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3965 imm |= (Rn << 9); 3966 3967 if (Rn == 15) { 3968 switch (Inst.getOpcode()) { 3969 case ARM::t2LDRT: 3970 Inst.setOpcode(ARM::t2LDRpci); 3971 break; 3972 case ARM::t2LDRBT: 3973 Inst.setOpcode(ARM::t2LDRBpci); 3974 break; 3975 case ARM::t2LDRHT: 3976 Inst.setOpcode(ARM::t2LDRHpci); 3977 break; 3978 case ARM::t2LDRSBT: 3979 Inst.setOpcode(ARM::t2LDRSBpci); 3980 break; 3981 case ARM::t2LDRSHT: 3982 Inst.setOpcode(ARM::t2LDRSHpci); 3983 break; 3984 default: 3985 return MCDisassembler::Fail; 3986 } 3987 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3988 } 3989 3990 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3991 return MCDisassembler::Fail; 3992 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3993 return MCDisassembler::Fail; 3994 return S; 3995 } 3996 3997 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3998 uint64_t Address, const void* Decoder) { 3999 DecodeStatus S = MCDisassembler::Success; 4000 4001 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4002 unsigned U = fieldFromInstruction(Insn, 23, 1); 4003 int imm = fieldFromInstruction(Insn, 0, 12); 4004 4005 const FeatureBitset &featureBits = 4006 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4007 4008 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4009 4010 if (Rt == 15) { 4011 switch (Inst.getOpcode()) { 4012 case ARM::t2LDRBpci: 4013 case ARM::t2LDRHpci: 4014 Inst.setOpcode(ARM::t2PLDpci); 4015 break; 4016 case ARM::t2LDRSBpci: 4017 Inst.setOpcode(ARM::t2PLIpci); 4018 break; 4019 case ARM::t2LDRSHpci: 4020 return MCDisassembler::Fail; 4021 default: 4022 break; 4023 } 4024 } 4025 4026 switch(Inst.getOpcode()) { 4027 case ARM::t2PLDpci: 4028 break; 4029 case ARM::t2PLIpci: 4030 if (!hasV7Ops) 4031 return MCDisassembler::Fail; 4032 break; 4033 default: 4034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4035 return MCDisassembler::Fail; 4036 } 4037 4038 if (!U) { 4039 // Special case for #-0. 4040 if (imm == 0) 4041 imm = INT32_MIN; 4042 else 4043 imm = -imm; 4044 } 4045 Inst.addOperand(MCOperand::createImm(imm)); 4046 4047 return S; 4048 } 4049 4050 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4051 uint64_t Address, const void *Decoder) { 4052 if (Val == 0) 4053 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4054 else { 4055 int imm = Val & 0xFF; 4056 4057 if (!(Val & 0x100)) imm *= -1; 4058 Inst.addOperand(MCOperand::createImm(imm * 4)); 4059 } 4060 4061 return MCDisassembler::Success; 4062 } 4063 4064 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4065 const void *Decoder) { 4066 if (Val == 0) 4067 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4068 else { 4069 int imm = Val & 0x7F; 4070 4071 if (!(Val & 0x80)) 4072 imm *= -1; 4073 Inst.addOperand(MCOperand::createImm(imm * 4)); 4074 } 4075 4076 return MCDisassembler::Success; 4077 } 4078 4079 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4080 uint64_t Address, const void *Decoder) { 4081 DecodeStatus S = MCDisassembler::Success; 4082 4083 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4084 unsigned imm = fieldFromInstruction(Val, 0, 9); 4085 4086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4087 return MCDisassembler::Fail; 4088 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4089 return MCDisassembler::Fail; 4090 4091 return S; 4092 } 4093 4094 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4095 uint64_t Address, 4096 const void *Decoder) { 4097 DecodeStatus S = MCDisassembler::Success; 4098 4099 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4100 unsigned imm = fieldFromInstruction(Val, 0, 8); 4101 4102 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4103 return MCDisassembler::Fail; 4104 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4105 return MCDisassembler::Fail; 4106 4107 return S; 4108 } 4109 4110 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4111 uint64_t Address, const void *Decoder) { 4112 DecodeStatus S = MCDisassembler::Success; 4113 4114 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4115 unsigned imm = fieldFromInstruction(Val, 0, 8); 4116 4117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4118 return MCDisassembler::Fail; 4119 4120 Inst.addOperand(MCOperand::createImm(imm)); 4121 4122 return S; 4123 } 4124 4125 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4126 uint64_t Address, const void *Decoder) { 4127 int imm = Val & 0xFF; 4128 if (Val == 0) 4129 imm = INT32_MIN; 4130 else if (!(Val & 0x100)) 4131 imm *= -1; 4132 Inst.addOperand(MCOperand::createImm(imm)); 4133 4134 return MCDisassembler::Success; 4135 } 4136 4137 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4138 uint64_t Address, const void *Decoder) { 4139 DecodeStatus S = MCDisassembler::Success; 4140 4141 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4142 unsigned imm = fieldFromInstruction(Val, 0, 9); 4143 4144 // Thumb stores cannot use PC as dest register. 4145 switch (Inst.getOpcode()) { 4146 case ARM::t2STRT: 4147 case ARM::t2STRBT: 4148 case ARM::t2STRHT: 4149 case ARM::t2STRi8: 4150 case ARM::t2STRHi8: 4151 case ARM::t2STRBi8: 4152 if (Rn == 15) 4153 return MCDisassembler::Fail; 4154 break; 4155 default: 4156 break; 4157 } 4158 4159 // Some instructions always use an additive offset. 4160 switch (Inst.getOpcode()) { 4161 case ARM::t2LDRT: 4162 case ARM::t2LDRBT: 4163 case ARM::t2LDRHT: 4164 case ARM::t2LDRSBT: 4165 case ARM::t2LDRSHT: 4166 case ARM::t2STRT: 4167 case ARM::t2STRBT: 4168 case ARM::t2STRHT: 4169 imm |= 0x100; 4170 break; 4171 default: 4172 break; 4173 } 4174 4175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4176 return MCDisassembler::Fail; 4177 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4178 return MCDisassembler::Fail; 4179 4180 return S; 4181 } 4182 4183 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4184 uint64_t Address, const void *Decoder) { 4185 DecodeStatus S = MCDisassembler::Success; 4186 4187 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4188 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4189 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4190 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4191 addr |= Rn << 9; 4192 unsigned load = fieldFromInstruction(Insn, 20, 1); 4193 4194 if (Rn == 15) { 4195 switch (Inst.getOpcode()) { 4196 case ARM::t2LDR_PRE: 4197 case ARM::t2LDR_POST: 4198 Inst.setOpcode(ARM::t2LDRpci); 4199 break; 4200 case ARM::t2LDRB_PRE: 4201 case ARM::t2LDRB_POST: 4202 Inst.setOpcode(ARM::t2LDRBpci); 4203 break; 4204 case ARM::t2LDRH_PRE: 4205 case ARM::t2LDRH_POST: 4206 Inst.setOpcode(ARM::t2LDRHpci); 4207 break; 4208 case ARM::t2LDRSB_PRE: 4209 case ARM::t2LDRSB_POST: 4210 if (Rt == 15) 4211 Inst.setOpcode(ARM::t2PLIpci); 4212 else 4213 Inst.setOpcode(ARM::t2LDRSBpci); 4214 break; 4215 case ARM::t2LDRSH_PRE: 4216 case ARM::t2LDRSH_POST: 4217 Inst.setOpcode(ARM::t2LDRSHpci); 4218 break; 4219 default: 4220 return MCDisassembler::Fail; 4221 } 4222 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4223 } 4224 4225 if (!load) { 4226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4227 return MCDisassembler::Fail; 4228 } 4229 4230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4231 return MCDisassembler::Fail; 4232 4233 if (load) { 4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 } 4237 4238 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4239 return MCDisassembler::Fail; 4240 4241 return S; 4242 } 4243 4244 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4245 uint64_t Address, const void *Decoder) { 4246 DecodeStatus S = MCDisassembler::Success; 4247 4248 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4249 unsigned imm = fieldFromInstruction(Val, 0, 12); 4250 4251 // Thumb stores cannot use PC as dest register. 4252 switch (Inst.getOpcode()) { 4253 case ARM::t2STRi12: 4254 case ARM::t2STRBi12: 4255 case ARM::t2STRHi12: 4256 if (Rn == 15) 4257 return MCDisassembler::Fail; 4258 break; 4259 default: 4260 break; 4261 } 4262 4263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4264 return MCDisassembler::Fail; 4265 Inst.addOperand(MCOperand::createImm(imm)); 4266 4267 return S; 4268 } 4269 4270 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4271 uint64_t Address, const void *Decoder) { 4272 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4273 4274 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4275 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4276 Inst.addOperand(MCOperand::createImm(imm)); 4277 4278 return MCDisassembler::Success; 4279 } 4280 4281 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4282 uint64_t Address, const void *Decoder) { 4283 DecodeStatus S = MCDisassembler::Success; 4284 4285 if (Inst.getOpcode() == ARM::tADDrSP) { 4286 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4287 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4288 4289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4290 return MCDisassembler::Fail; 4291 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4293 return MCDisassembler::Fail; 4294 } else if (Inst.getOpcode() == ARM::tADDspr) { 4295 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4296 4297 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4298 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 } 4302 4303 return S; 4304 } 4305 4306 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4307 uint64_t Address, const void *Decoder) { 4308 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4309 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4310 4311 Inst.addOperand(MCOperand::createImm(imod)); 4312 Inst.addOperand(MCOperand::createImm(flags)); 4313 4314 return MCDisassembler::Success; 4315 } 4316 4317 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4318 uint64_t Address, const void *Decoder) { 4319 DecodeStatus S = MCDisassembler::Success; 4320 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4321 unsigned add = fieldFromInstruction(Insn, 4, 1); 4322 4323 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4324 return MCDisassembler::Fail; 4325 Inst.addOperand(MCOperand::createImm(add)); 4326 4327 return S; 4328 } 4329 4330 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4331 uint64_t Address, const void *Decoder) { 4332 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4333 // Note only one trailing zero not two. Also the J1 and J2 values are from 4334 // the encoded instruction. So here change to I1 and I2 values via: 4335 // I1 = NOT(J1 EOR S); 4336 // I2 = NOT(J2 EOR S); 4337 // and build the imm32 with two trailing zeros as documented: 4338 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4339 unsigned S = (Val >> 23) & 1; 4340 unsigned J1 = (Val >> 22) & 1; 4341 unsigned J2 = (Val >> 21) & 1; 4342 unsigned I1 = !(J1 ^ S); 4343 unsigned I2 = !(J2 ^ S); 4344 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4345 int imm32 = SignExtend32<25>(tmp << 1); 4346 4347 if (!tryAddingSymbolicOperand(Address, 4348 (Address & ~2u) + imm32 + 4, 4349 true, 4, Inst, Decoder)) 4350 Inst.addOperand(MCOperand::createImm(imm32)); 4351 return MCDisassembler::Success; 4352 } 4353 4354 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4355 uint64_t Address, const void *Decoder) { 4356 if (Val == 0xA || Val == 0xB) 4357 return MCDisassembler::Fail; 4358 4359 const FeatureBitset &featureBits = 4360 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4361 4362 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4363 return MCDisassembler::Fail; 4364 4365 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should 4366 // decode as VFP/MVE instructions. 4367 if (featureBits[ARM::HasV8_1MMainlineOps] && 4368 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || 4369 (Val & 0xE) == 0xE)) 4370 return MCDisassembler::Fail; 4371 4372 Inst.addOperand(MCOperand::createImm(Val)); 4373 return MCDisassembler::Success; 4374 } 4375 4376 static DecodeStatus 4377 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4378 uint64_t Address, const void *Decoder) { 4379 DecodeStatus S = MCDisassembler::Success; 4380 4381 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4382 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4383 4384 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4386 return MCDisassembler::Fail; 4387 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4388 return MCDisassembler::Fail; 4389 return S; 4390 } 4391 4392 static DecodeStatus 4393 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4394 uint64_t Address, const void *Decoder) { 4395 DecodeStatus S = MCDisassembler::Success; 4396 4397 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4398 if (pred == 0xE || pred == 0xF) { 4399 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4400 switch (opc) { 4401 default: 4402 return MCDisassembler::Fail; 4403 case 0xf3bf8f4: 4404 Inst.setOpcode(ARM::t2DSB); 4405 break; 4406 case 0xf3bf8f5: 4407 Inst.setOpcode(ARM::t2DMB); 4408 break; 4409 case 0xf3bf8f6: 4410 Inst.setOpcode(ARM::t2ISB); 4411 break; 4412 } 4413 4414 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4415 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4416 } 4417 4418 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4419 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4420 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4421 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4422 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4423 4424 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4425 return MCDisassembler::Fail; 4426 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4427 return MCDisassembler::Fail; 4428 4429 return S; 4430 } 4431 4432 // Decode a shifted immediate operand. These basically consist 4433 // of an 8-bit value, and a 4-bit directive that specifies either 4434 // a splat operation or a rotation. 4435 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4436 uint64_t Address, const void *Decoder) { 4437 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4438 if (ctrl == 0) { 4439 unsigned byte = fieldFromInstruction(Val, 8, 2); 4440 unsigned imm = fieldFromInstruction(Val, 0, 8); 4441 switch (byte) { 4442 case 0: 4443 Inst.addOperand(MCOperand::createImm(imm)); 4444 break; 4445 case 1: 4446 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4447 break; 4448 case 2: 4449 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4450 break; 4451 case 3: 4452 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4453 (imm << 8) | imm)); 4454 break; 4455 } 4456 } else { 4457 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4458 unsigned rot = fieldFromInstruction(Val, 7, 5); 4459 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4460 Inst.addOperand(MCOperand::createImm(imm)); 4461 } 4462 4463 return MCDisassembler::Success; 4464 } 4465 4466 static DecodeStatus 4467 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4468 uint64_t Address, const void *Decoder) { 4469 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4470 true, 2, Inst, Decoder)) 4471 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4472 return MCDisassembler::Success; 4473 } 4474 4475 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4476 uint64_t Address, 4477 const void *Decoder) { 4478 // Val is passed in as S:J1:J2:imm10:imm11 4479 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4480 // the encoded instruction. So here change to I1 and I2 values via: 4481 // I1 = NOT(J1 EOR S); 4482 // I2 = NOT(J2 EOR S); 4483 // and build the imm32 with one trailing zero as documented: 4484 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4485 unsigned S = (Val >> 23) & 1; 4486 unsigned J1 = (Val >> 22) & 1; 4487 unsigned J2 = (Val >> 21) & 1; 4488 unsigned I1 = !(J1 ^ S); 4489 unsigned I2 = !(J2 ^ S); 4490 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4491 int imm32 = SignExtend32<25>(tmp << 1); 4492 4493 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4494 true, 4, Inst, Decoder)) 4495 Inst.addOperand(MCOperand::createImm(imm32)); 4496 return MCDisassembler::Success; 4497 } 4498 4499 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4500 uint64_t Address, const void *Decoder) { 4501 if (Val & ~0xf) 4502 return MCDisassembler::Fail; 4503 4504 Inst.addOperand(MCOperand::createImm(Val)); 4505 return MCDisassembler::Success; 4506 } 4507 4508 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4509 uint64_t Address, const void *Decoder) { 4510 if (Val & ~0xf) 4511 return MCDisassembler::Fail; 4512 4513 Inst.addOperand(MCOperand::createImm(Val)); 4514 return MCDisassembler::Success; 4515 } 4516 4517 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4518 uint64_t Address, const void *Decoder) { 4519 DecodeStatus S = MCDisassembler::Success; 4520 const FeatureBitset &FeatureBits = 4521 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4522 4523 if (FeatureBits[ARM::FeatureMClass]) { 4524 unsigned ValLow = Val & 0xff; 4525 4526 // Validate the SYSm value first. 4527 switch (ValLow) { 4528 case 0: // apsr 4529 case 1: // iapsr 4530 case 2: // eapsr 4531 case 3: // xpsr 4532 case 5: // ipsr 4533 case 6: // epsr 4534 case 7: // iepsr 4535 case 8: // msp 4536 case 9: // psp 4537 case 16: // primask 4538 case 20: // control 4539 break; 4540 case 17: // basepri 4541 case 18: // basepri_max 4542 case 19: // faultmask 4543 if (!(FeatureBits[ARM::HasV7Ops])) 4544 // Values basepri, basepri_max and faultmask are only valid for v7m. 4545 return MCDisassembler::Fail; 4546 break; 4547 case 0x8a: // msplim_ns 4548 case 0x8b: // psplim_ns 4549 case 0x91: // basepri_ns 4550 case 0x93: // faultmask_ns 4551 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4552 return MCDisassembler::Fail; 4553 LLVM_FALLTHROUGH; 4554 case 10: // msplim 4555 case 11: // psplim 4556 case 0x88: // msp_ns 4557 case 0x89: // psp_ns 4558 case 0x90: // primask_ns 4559 case 0x94: // control_ns 4560 case 0x98: // sp_ns 4561 if (!(FeatureBits[ARM::Feature8MSecExt])) 4562 return MCDisassembler::Fail; 4563 break; 4564 default: 4565 // Architecturally defined as unpredictable 4566 S = MCDisassembler::SoftFail; 4567 break; 4568 } 4569 4570 if (Inst.getOpcode() == ARM::t2MSR_M) { 4571 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4572 if (!(FeatureBits[ARM::HasV7Ops])) { 4573 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4574 // unpredictable. 4575 if (Mask != 2) 4576 S = MCDisassembler::SoftFail; 4577 } 4578 else { 4579 // The ARMv7-M architecture stores an additional 2-bit mask value in 4580 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4581 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4582 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4583 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4584 // only if the processor includes the DSP extension. 4585 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4586 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4587 S = MCDisassembler::SoftFail; 4588 } 4589 } 4590 } else { 4591 // A/R class 4592 if (Val == 0) 4593 return MCDisassembler::Fail; 4594 } 4595 Inst.addOperand(MCOperand::createImm(Val)); 4596 return S; 4597 } 4598 4599 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4600 uint64_t Address, const void *Decoder) { 4601 unsigned R = fieldFromInstruction(Val, 5, 1); 4602 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4603 4604 // The table of encodings for these banked registers comes from B9.2.3 of the 4605 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4606 // neater. So by fiat, these values are UNPREDICTABLE: 4607 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4608 return MCDisassembler::Fail; 4609 4610 Inst.addOperand(MCOperand::createImm(Val)); 4611 return MCDisassembler::Success; 4612 } 4613 4614 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4615 uint64_t Address, const void *Decoder) { 4616 DecodeStatus S = MCDisassembler::Success; 4617 4618 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4619 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4620 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4621 4622 if (Rn == 0xF) 4623 S = MCDisassembler::SoftFail; 4624 4625 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4626 return MCDisassembler::Fail; 4627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4628 return MCDisassembler::Fail; 4629 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4630 return MCDisassembler::Fail; 4631 4632 return S; 4633 } 4634 4635 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4636 uint64_t Address, 4637 const void *Decoder) { 4638 DecodeStatus S = MCDisassembler::Success; 4639 4640 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4641 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4642 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4643 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4644 4645 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4646 return MCDisassembler::Fail; 4647 4648 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4649 S = MCDisassembler::SoftFail; 4650 4651 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4652 return MCDisassembler::Fail; 4653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4654 return MCDisassembler::Fail; 4655 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4656 return MCDisassembler::Fail; 4657 4658 return S; 4659 } 4660 4661 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4662 uint64_t Address, const void *Decoder) { 4663 DecodeStatus S = MCDisassembler::Success; 4664 4665 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4666 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4667 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4668 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4669 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4670 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4671 4672 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4673 4674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4675 return MCDisassembler::Fail; 4676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4677 return MCDisassembler::Fail; 4678 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4681 return MCDisassembler::Fail; 4682 4683 return S; 4684 } 4685 4686 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4687 uint64_t Address, const void *Decoder) { 4688 DecodeStatus S = MCDisassembler::Success; 4689 4690 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4691 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4692 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4693 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4694 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4695 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4696 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4697 4698 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4699 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4700 4701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4702 return MCDisassembler::Fail; 4703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4704 return MCDisassembler::Fail; 4705 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4706 return MCDisassembler::Fail; 4707 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4708 return MCDisassembler::Fail; 4709 4710 return S; 4711 } 4712 4713 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4714 uint64_t Address, const void *Decoder) { 4715 DecodeStatus S = MCDisassembler::Success; 4716 4717 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4718 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4719 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4720 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4721 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4722 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4723 4724 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4725 4726 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4727 return MCDisassembler::Fail; 4728 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4729 return MCDisassembler::Fail; 4730 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4731 return MCDisassembler::Fail; 4732 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4733 return MCDisassembler::Fail; 4734 4735 return S; 4736 } 4737 4738 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4739 uint64_t Address, const void *Decoder) { 4740 DecodeStatus S = MCDisassembler::Success; 4741 4742 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4743 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4744 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4745 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4746 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4747 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4748 4749 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4750 4751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4752 return MCDisassembler::Fail; 4753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4754 return MCDisassembler::Fail; 4755 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4756 return MCDisassembler::Fail; 4757 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4758 return MCDisassembler::Fail; 4759 4760 return S; 4761 } 4762 4763 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4764 uint64_t Address, const void *Decoder) { 4765 DecodeStatus S = MCDisassembler::Success; 4766 4767 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4768 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4769 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4770 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4771 unsigned size = fieldFromInstruction(Insn, 10, 2); 4772 4773 unsigned align = 0; 4774 unsigned index = 0; 4775 switch (size) { 4776 default: 4777 return MCDisassembler::Fail; 4778 case 0: 4779 if (fieldFromInstruction(Insn, 4, 1)) 4780 return MCDisassembler::Fail; // UNDEFINED 4781 index = fieldFromInstruction(Insn, 5, 3); 4782 break; 4783 case 1: 4784 if (fieldFromInstruction(Insn, 5, 1)) 4785 return MCDisassembler::Fail; // UNDEFINED 4786 index = fieldFromInstruction(Insn, 6, 2); 4787 if (fieldFromInstruction(Insn, 4, 1)) 4788 align = 2; 4789 break; 4790 case 2: 4791 if (fieldFromInstruction(Insn, 6, 1)) 4792 return MCDisassembler::Fail; // UNDEFINED 4793 index = fieldFromInstruction(Insn, 7, 1); 4794 4795 switch (fieldFromInstruction(Insn, 4, 2)) { 4796 case 0 : 4797 align = 0; break; 4798 case 3: 4799 align = 4; break; 4800 default: 4801 return MCDisassembler::Fail; 4802 } 4803 break; 4804 } 4805 4806 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4807 return MCDisassembler::Fail; 4808 if (Rm != 0xF) { // Writeback 4809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4810 return MCDisassembler::Fail; 4811 } 4812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4813 return MCDisassembler::Fail; 4814 Inst.addOperand(MCOperand::createImm(align)); 4815 if (Rm != 0xF) { 4816 if (Rm != 0xD) { 4817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4818 return MCDisassembler::Fail; 4819 } else 4820 Inst.addOperand(MCOperand::createReg(0)); 4821 } 4822 4823 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4824 return MCDisassembler::Fail; 4825 Inst.addOperand(MCOperand::createImm(index)); 4826 4827 return S; 4828 } 4829 4830 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4831 uint64_t Address, const void *Decoder) { 4832 DecodeStatus S = MCDisassembler::Success; 4833 4834 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4835 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4836 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4837 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4838 unsigned size = fieldFromInstruction(Insn, 10, 2); 4839 4840 unsigned align = 0; 4841 unsigned index = 0; 4842 switch (size) { 4843 default: 4844 return MCDisassembler::Fail; 4845 case 0: 4846 if (fieldFromInstruction(Insn, 4, 1)) 4847 return MCDisassembler::Fail; // UNDEFINED 4848 index = fieldFromInstruction(Insn, 5, 3); 4849 break; 4850 case 1: 4851 if (fieldFromInstruction(Insn, 5, 1)) 4852 return MCDisassembler::Fail; // UNDEFINED 4853 index = fieldFromInstruction(Insn, 6, 2); 4854 if (fieldFromInstruction(Insn, 4, 1)) 4855 align = 2; 4856 break; 4857 case 2: 4858 if (fieldFromInstruction(Insn, 6, 1)) 4859 return MCDisassembler::Fail; // UNDEFINED 4860 index = fieldFromInstruction(Insn, 7, 1); 4861 4862 switch (fieldFromInstruction(Insn, 4, 2)) { 4863 case 0: 4864 align = 0; break; 4865 case 3: 4866 align = 4; break; 4867 default: 4868 return MCDisassembler::Fail; 4869 } 4870 break; 4871 } 4872 4873 if (Rm != 0xF) { // Writeback 4874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4875 return MCDisassembler::Fail; 4876 } 4877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4878 return MCDisassembler::Fail; 4879 Inst.addOperand(MCOperand::createImm(align)); 4880 if (Rm != 0xF) { 4881 if (Rm != 0xD) { 4882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4883 return MCDisassembler::Fail; 4884 } else 4885 Inst.addOperand(MCOperand::createReg(0)); 4886 } 4887 4888 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4889 return MCDisassembler::Fail; 4890 Inst.addOperand(MCOperand::createImm(index)); 4891 4892 return S; 4893 } 4894 4895 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4896 uint64_t Address, const void *Decoder) { 4897 DecodeStatus S = MCDisassembler::Success; 4898 4899 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4900 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4901 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4902 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4903 unsigned size = fieldFromInstruction(Insn, 10, 2); 4904 4905 unsigned align = 0; 4906 unsigned index = 0; 4907 unsigned inc = 1; 4908 switch (size) { 4909 default: 4910 return MCDisassembler::Fail; 4911 case 0: 4912 index = fieldFromInstruction(Insn, 5, 3); 4913 if (fieldFromInstruction(Insn, 4, 1)) 4914 align = 2; 4915 break; 4916 case 1: 4917 index = fieldFromInstruction(Insn, 6, 2); 4918 if (fieldFromInstruction(Insn, 4, 1)) 4919 align = 4; 4920 if (fieldFromInstruction(Insn, 5, 1)) 4921 inc = 2; 4922 break; 4923 case 2: 4924 if (fieldFromInstruction(Insn, 5, 1)) 4925 return MCDisassembler::Fail; // UNDEFINED 4926 index = fieldFromInstruction(Insn, 7, 1); 4927 if (fieldFromInstruction(Insn, 4, 1) != 0) 4928 align = 8; 4929 if (fieldFromInstruction(Insn, 6, 1)) 4930 inc = 2; 4931 break; 4932 } 4933 4934 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4935 return MCDisassembler::Fail; 4936 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4937 return MCDisassembler::Fail; 4938 if (Rm != 0xF) { // Writeback 4939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4940 return MCDisassembler::Fail; 4941 } 4942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4943 return MCDisassembler::Fail; 4944 Inst.addOperand(MCOperand::createImm(align)); 4945 if (Rm != 0xF) { 4946 if (Rm != 0xD) { 4947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4948 return MCDisassembler::Fail; 4949 } else 4950 Inst.addOperand(MCOperand::createReg(0)); 4951 } 4952 4953 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4954 return MCDisassembler::Fail; 4955 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4956 return MCDisassembler::Fail; 4957 Inst.addOperand(MCOperand::createImm(index)); 4958 4959 return S; 4960 } 4961 4962 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4963 uint64_t Address, const void *Decoder) { 4964 DecodeStatus S = MCDisassembler::Success; 4965 4966 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4967 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4968 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4969 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4970 unsigned size = fieldFromInstruction(Insn, 10, 2); 4971 4972 unsigned align = 0; 4973 unsigned index = 0; 4974 unsigned inc = 1; 4975 switch (size) { 4976 default: 4977 return MCDisassembler::Fail; 4978 case 0: 4979 index = fieldFromInstruction(Insn, 5, 3); 4980 if (fieldFromInstruction(Insn, 4, 1)) 4981 align = 2; 4982 break; 4983 case 1: 4984 index = fieldFromInstruction(Insn, 6, 2); 4985 if (fieldFromInstruction(Insn, 4, 1)) 4986 align = 4; 4987 if (fieldFromInstruction(Insn, 5, 1)) 4988 inc = 2; 4989 break; 4990 case 2: 4991 if (fieldFromInstruction(Insn, 5, 1)) 4992 return MCDisassembler::Fail; // UNDEFINED 4993 index = fieldFromInstruction(Insn, 7, 1); 4994 if (fieldFromInstruction(Insn, 4, 1) != 0) 4995 align = 8; 4996 if (fieldFromInstruction(Insn, 6, 1)) 4997 inc = 2; 4998 break; 4999 } 5000 5001 if (Rm != 0xF) { // Writeback 5002 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5003 return MCDisassembler::Fail; 5004 } 5005 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5006 return MCDisassembler::Fail; 5007 Inst.addOperand(MCOperand::createImm(align)); 5008 if (Rm != 0xF) { 5009 if (Rm != 0xD) { 5010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5011 return MCDisassembler::Fail; 5012 } else 5013 Inst.addOperand(MCOperand::createReg(0)); 5014 } 5015 5016 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5017 return MCDisassembler::Fail; 5018 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5019 return MCDisassembler::Fail; 5020 Inst.addOperand(MCOperand::createImm(index)); 5021 5022 return S; 5023 } 5024 5025 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5026 uint64_t Address, const void *Decoder) { 5027 DecodeStatus S = MCDisassembler::Success; 5028 5029 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5030 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5031 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5032 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5033 unsigned size = fieldFromInstruction(Insn, 10, 2); 5034 5035 unsigned align = 0; 5036 unsigned index = 0; 5037 unsigned inc = 1; 5038 switch (size) { 5039 default: 5040 return MCDisassembler::Fail; 5041 case 0: 5042 if (fieldFromInstruction(Insn, 4, 1)) 5043 return MCDisassembler::Fail; // UNDEFINED 5044 index = fieldFromInstruction(Insn, 5, 3); 5045 break; 5046 case 1: 5047 if (fieldFromInstruction(Insn, 4, 1)) 5048 return MCDisassembler::Fail; // UNDEFINED 5049 index = fieldFromInstruction(Insn, 6, 2); 5050 if (fieldFromInstruction(Insn, 5, 1)) 5051 inc = 2; 5052 break; 5053 case 2: 5054 if (fieldFromInstruction(Insn, 4, 2)) 5055 return MCDisassembler::Fail; // UNDEFINED 5056 index = fieldFromInstruction(Insn, 7, 1); 5057 if (fieldFromInstruction(Insn, 6, 1)) 5058 inc = 2; 5059 break; 5060 } 5061 5062 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5063 return MCDisassembler::Fail; 5064 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5065 return MCDisassembler::Fail; 5066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5067 return MCDisassembler::Fail; 5068 5069 if (Rm != 0xF) { // Writeback 5070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5071 return MCDisassembler::Fail; 5072 } 5073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5074 return MCDisassembler::Fail; 5075 Inst.addOperand(MCOperand::createImm(align)); 5076 if (Rm != 0xF) { 5077 if (Rm != 0xD) { 5078 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5079 return MCDisassembler::Fail; 5080 } else 5081 Inst.addOperand(MCOperand::createReg(0)); 5082 } 5083 5084 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5085 return MCDisassembler::Fail; 5086 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5087 return MCDisassembler::Fail; 5088 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5089 return MCDisassembler::Fail; 5090 Inst.addOperand(MCOperand::createImm(index)); 5091 5092 return S; 5093 } 5094 5095 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5096 uint64_t Address, const void *Decoder) { 5097 DecodeStatus S = MCDisassembler::Success; 5098 5099 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5100 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5101 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5102 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5103 unsigned size = fieldFromInstruction(Insn, 10, 2); 5104 5105 unsigned align = 0; 5106 unsigned index = 0; 5107 unsigned inc = 1; 5108 switch (size) { 5109 default: 5110 return MCDisassembler::Fail; 5111 case 0: 5112 if (fieldFromInstruction(Insn, 4, 1)) 5113 return MCDisassembler::Fail; // UNDEFINED 5114 index = fieldFromInstruction(Insn, 5, 3); 5115 break; 5116 case 1: 5117 if (fieldFromInstruction(Insn, 4, 1)) 5118 return MCDisassembler::Fail; // UNDEFINED 5119 index = fieldFromInstruction(Insn, 6, 2); 5120 if (fieldFromInstruction(Insn, 5, 1)) 5121 inc = 2; 5122 break; 5123 case 2: 5124 if (fieldFromInstruction(Insn, 4, 2)) 5125 return MCDisassembler::Fail; // UNDEFINED 5126 index = fieldFromInstruction(Insn, 7, 1); 5127 if (fieldFromInstruction(Insn, 6, 1)) 5128 inc = 2; 5129 break; 5130 } 5131 5132 if (Rm != 0xF) { // Writeback 5133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5134 return MCDisassembler::Fail; 5135 } 5136 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5137 return MCDisassembler::Fail; 5138 Inst.addOperand(MCOperand::createImm(align)); 5139 if (Rm != 0xF) { 5140 if (Rm != 0xD) { 5141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5142 return MCDisassembler::Fail; 5143 } else 5144 Inst.addOperand(MCOperand::createReg(0)); 5145 } 5146 5147 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5148 return MCDisassembler::Fail; 5149 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5150 return MCDisassembler::Fail; 5151 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5152 return MCDisassembler::Fail; 5153 Inst.addOperand(MCOperand::createImm(index)); 5154 5155 return S; 5156 } 5157 5158 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5159 uint64_t Address, const void *Decoder) { 5160 DecodeStatus S = MCDisassembler::Success; 5161 5162 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5163 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5164 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5165 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5166 unsigned size = fieldFromInstruction(Insn, 10, 2); 5167 5168 unsigned align = 0; 5169 unsigned index = 0; 5170 unsigned inc = 1; 5171 switch (size) { 5172 default: 5173 return MCDisassembler::Fail; 5174 case 0: 5175 if (fieldFromInstruction(Insn, 4, 1)) 5176 align = 4; 5177 index = fieldFromInstruction(Insn, 5, 3); 5178 break; 5179 case 1: 5180 if (fieldFromInstruction(Insn, 4, 1)) 5181 align = 8; 5182 index = fieldFromInstruction(Insn, 6, 2); 5183 if (fieldFromInstruction(Insn, 5, 1)) 5184 inc = 2; 5185 break; 5186 case 2: 5187 switch (fieldFromInstruction(Insn, 4, 2)) { 5188 case 0: 5189 align = 0; break; 5190 case 3: 5191 return MCDisassembler::Fail; 5192 default: 5193 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5194 } 5195 5196 index = fieldFromInstruction(Insn, 7, 1); 5197 if (fieldFromInstruction(Insn, 6, 1)) 5198 inc = 2; 5199 break; 5200 } 5201 5202 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5203 return MCDisassembler::Fail; 5204 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5205 return MCDisassembler::Fail; 5206 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5207 return MCDisassembler::Fail; 5208 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5209 return MCDisassembler::Fail; 5210 5211 if (Rm != 0xF) { // Writeback 5212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5213 return MCDisassembler::Fail; 5214 } 5215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5216 return MCDisassembler::Fail; 5217 Inst.addOperand(MCOperand::createImm(align)); 5218 if (Rm != 0xF) { 5219 if (Rm != 0xD) { 5220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5221 return MCDisassembler::Fail; 5222 } else 5223 Inst.addOperand(MCOperand::createReg(0)); 5224 } 5225 5226 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5227 return MCDisassembler::Fail; 5228 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5229 return MCDisassembler::Fail; 5230 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5231 return MCDisassembler::Fail; 5232 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5233 return MCDisassembler::Fail; 5234 Inst.addOperand(MCOperand::createImm(index)); 5235 5236 return S; 5237 } 5238 5239 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5240 uint64_t Address, const void *Decoder) { 5241 DecodeStatus S = MCDisassembler::Success; 5242 5243 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5244 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5245 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5246 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5247 unsigned size = fieldFromInstruction(Insn, 10, 2); 5248 5249 unsigned align = 0; 5250 unsigned index = 0; 5251 unsigned inc = 1; 5252 switch (size) { 5253 default: 5254 return MCDisassembler::Fail; 5255 case 0: 5256 if (fieldFromInstruction(Insn, 4, 1)) 5257 align = 4; 5258 index = fieldFromInstruction(Insn, 5, 3); 5259 break; 5260 case 1: 5261 if (fieldFromInstruction(Insn, 4, 1)) 5262 align = 8; 5263 index = fieldFromInstruction(Insn, 6, 2); 5264 if (fieldFromInstruction(Insn, 5, 1)) 5265 inc = 2; 5266 break; 5267 case 2: 5268 switch (fieldFromInstruction(Insn, 4, 2)) { 5269 case 0: 5270 align = 0; break; 5271 case 3: 5272 return MCDisassembler::Fail; 5273 default: 5274 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5275 } 5276 5277 index = fieldFromInstruction(Insn, 7, 1); 5278 if (fieldFromInstruction(Insn, 6, 1)) 5279 inc = 2; 5280 break; 5281 } 5282 5283 if (Rm != 0xF) { // Writeback 5284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5285 return MCDisassembler::Fail; 5286 } 5287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5288 return MCDisassembler::Fail; 5289 Inst.addOperand(MCOperand::createImm(align)); 5290 if (Rm != 0xF) { 5291 if (Rm != 0xD) { 5292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5293 return MCDisassembler::Fail; 5294 } else 5295 Inst.addOperand(MCOperand::createReg(0)); 5296 } 5297 5298 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5299 return MCDisassembler::Fail; 5300 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5301 return MCDisassembler::Fail; 5302 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5303 return MCDisassembler::Fail; 5304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5305 return MCDisassembler::Fail; 5306 Inst.addOperand(MCOperand::createImm(index)); 5307 5308 return S; 5309 } 5310 5311 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5312 uint64_t Address, const void *Decoder) { 5313 DecodeStatus S = MCDisassembler::Success; 5314 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5315 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5316 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5317 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5318 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5319 5320 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5321 S = MCDisassembler::SoftFail; 5322 5323 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5324 return MCDisassembler::Fail; 5325 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5326 return MCDisassembler::Fail; 5327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5328 return MCDisassembler::Fail; 5329 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5330 return MCDisassembler::Fail; 5331 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5332 return MCDisassembler::Fail; 5333 5334 return S; 5335 } 5336 5337 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5338 uint64_t Address, const void *Decoder) { 5339 DecodeStatus S = MCDisassembler::Success; 5340 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5341 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5342 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5343 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5344 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5345 5346 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5347 S = MCDisassembler::SoftFail; 5348 5349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5350 return MCDisassembler::Fail; 5351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5352 return MCDisassembler::Fail; 5353 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5354 return MCDisassembler::Fail; 5355 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5356 return MCDisassembler::Fail; 5357 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5358 return MCDisassembler::Fail; 5359 5360 return S; 5361 } 5362 5363 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5364 uint64_t Address, const void *Decoder) { 5365 DecodeStatus S = MCDisassembler::Success; 5366 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5367 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5368 5369 if (pred == 0xF) { 5370 pred = 0xE; 5371 S = MCDisassembler::SoftFail; 5372 } 5373 5374 if (mask == 0x0) 5375 return MCDisassembler::Fail; 5376 5377 // IT masks are encoded as a sequence of replacement low-order bits 5378 // for the condition code. So if the low bit of the starting 5379 // condition code is 1, then we have to flip all the bits above the 5380 // terminating bit (which is the lowest 1 bit). 5381 if (pred & 1) { 5382 unsigned LowBit = mask & -mask; 5383 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5384 mask ^= BitsAboveLowBit; 5385 } 5386 5387 Inst.addOperand(MCOperand::createImm(pred)); 5388 Inst.addOperand(MCOperand::createImm(mask)); 5389 return S; 5390 } 5391 5392 static DecodeStatus 5393 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5394 uint64_t Address, const void *Decoder) { 5395 DecodeStatus S = MCDisassembler::Success; 5396 5397 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5398 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5399 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5400 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5401 unsigned W = fieldFromInstruction(Insn, 21, 1); 5402 unsigned U = fieldFromInstruction(Insn, 23, 1); 5403 unsigned P = fieldFromInstruction(Insn, 24, 1); 5404 bool writeback = (W == 1) | (P == 0); 5405 5406 addr |= (U << 8) | (Rn << 9); 5407 5408 if (writeback && (Rn == Rt || Rn == Rt2)) 5409 Check(S, MCDisassembler::SoftFail); 5410 if (Rt == Rt2) 5411 Check(S, MCDisassembler::SoftFail); 5412 5413 // Rt 5414 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5415 return MCDisassembler::Fail; 5416 // Rt2 5417 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5418 return MCDisassembler::Fail; 5419 // Writeback operand 5420 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5421 return MCDisassembler::Fail; 5422 // addr 5423 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5424 return MCDisassembler::Fail; 5425 5426 return S; 5427 } 5428 5429 static DecodeStatus 5430 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5431 uint64_t Address, const void *Decoder) { 5432 DecodeStatus S = MCDisassembler::Success; 5433 5434 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5435 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5436 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5437 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5438 unsigned W = fieldFromInstruction(Insn, 21, 1); 5439 unsigned U = fieldFromInstruction(Insn, 23, 1); 5440 unsigned P = fieldFromInstruction(Insn, 24, 1); 5441 bool writeback = (W == 1) | (P == 0); 5442 5443 addr |= (U << 8) | (Rn << 9); 5444 5445 if (writeback && (Rn == Rt || Rn == Rt2)) 5446 Check(S, MCDisassembler::SoftFail); 5447 5448 // Writeback operand 5449 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5450 return MCDisassembler::Fail; 5451 // Rt 5452 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5453 return MCDisassembler::Fail; 5454 // Rt2 5455 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5456 return MCDisassembler::Fail; 5457 // addr 5458 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5459 return MCDisassembler::Fail; 5460 5461 return S; 5462 } 5463 5464 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5465 uint64_t Address, const void *Decoder) { 5466 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5467 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5468 if (sign1 != sign2) return MCDisassembler::Fail; 5469 5470 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5471 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5472 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5473 Val |= sign1 << 12; 5474 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5475 5476 return MCDisassembler::Success; 5477 } 5478 5479 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5480 uint64_t Address, 5481 const void *Decoder) { 5482 DecodeStatus S = MCDisassembler::Success; 5483 5484 // Shift of "asr #32" is not allowed in Thumb2 mode. 5485 if (Val == 0x20) S = MCDisassembler::Fail; 5486 Inst.addOperand(MCOperand::createImm(Val)); 5487 return S; 5488 } 5489 5490 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5491 uint64_t Address, const void *Decoder) { 5492 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5493 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5494 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5495 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5496 5497 if (pred == 0xF) 5498 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5499 5500 DecodeStatus S = MCDisassembler::Success; 5501 5502 if (Rt == Rn || Rn == Rt2) 5503 S = MCDisassembler::SoftFail; 5504 5505 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5506 return MCDisassembler::Fail; 5507 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5508 return MCDisassembler::Fail; 5509 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5510 return MCDisassembler::Fail; 5511 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5512 return MCDisassembler::Fail; 5513 5514 return S; 5515 } 5516 5517 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5518 uint64_t Address, const void *Decoder) { 5519 const FeatureBitset &featureBits = 5520 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5521 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5522 5523 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5524 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5525 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5526 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5527 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5528 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5529 unsigned op = fieldFromInstruction(Insn, 5, 1); 5530 5531 DecodeStatus S = MCDisassembler::Success; 5532 5533 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5534 if (!(imm & 0x38)) { 5535 if (cmode == 0xF) { 5536 if (op == 1) return MCDisassembler::Fail; 5537 Inst.setOpcode(ARM::VMOVv2f32); 5538 } 5539 if (hasFullFP16) { 5540 if (cmode == 0xE) { 5541 if (op == 1) { 5542 Inst.setOpcode(ARM::VMOVv1i64); 5543 } else { 5544 Inst.setOpcode(ARM::VMOVv8i8); 5545 } 5546 } 5547 if (cmode == 0xD) { 5548 if (op == 1) { 5549 Inst.setOpcode(ARM::VMVNv2i32); 5550 } else { 5551 Inst.setOpcode(ARM::VMOVv2i32); 5552 } 5553 } 5554 if (cmode == 0xC) { 5555 if (op == 1) { 5556 Inst.setOpcode(ARM::VMVNv2i32); 5557 } else { 5558 Inst.setOpcode(ARM::VMOVv2i32); 5559 } 5560 } 5561 } 5562 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5563 } 5564 5565 if (!(imm & 0x20)) return MCDisassembler::Fail; 5566 5567 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5568 return MCDisassembler::Fail; 5569 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5570 return MCDisassembler::Fail; 5571 Inst.addOperand(MCOperand::createImm(64 - imm)); 5572 5573 return S; 5574 } 5575 5576 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5577 uint64_t Address, const void *Decoder) { 5578 const FeatureBitset &featureBits = 5579 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5580 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5581 5582 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5583 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5584 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5585 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5586 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5587 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5588 unsigned op = fieldFromInstruction(Insn, 5, 1); 5589 5590 DecodeStatus S = MCDisassembler::Success; 5591 5592 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5593 if (!(imm & 0x38)) { 5594 if (cmode == 0xF) { 5595 if (op == 1) return MCDisassembler::Fail; 5596 Inst.setOpcode(ARM::VMOVv4f32); 5597 } 5598 if (hasFullFP16) { 5599 if (cmode == 0xE) { 5600 if (op == 1) { 5601 Inst.setOpcode(ARM::VMOVv2i64); 5602 } else { 5603 Inst.setOpcode(ARM::VMOVv16i8); 5604 } 5605 } 5606 if (cmode == 0xD) { 5607 if (op == 1) { 5608 Inst.setOpcode(ARM::VMVNv4i32); 5609 } else { 5610 Inst.setOpcode(ARM::VMOVv4i32); 5611 } 5612 } 5613 if (cmode == 0xC) { 5614 if (op == 1) { 5615 Inst.setOpcode(ARM::VMVNv4i32); 5616 } else { 5617 Inst.setOpcode(ARM::VMOVv4i32); 5618 } 5619 } 5620 } 5621 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5622 } 5623 5624 if (!(imm & 0x20)) return MCDisassembler::Fail; 5625 5626 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5627 return MCDisassembler::Fail; 5628 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5629 return MCDisassembler::Fail; 5630 Inst.addOperand(MCOperand::createImm(64 - imm)); 5631 5632 return S; 5633 } 5634 5635 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5636 unsigned Insn, 5637 uint64_t Address, 5638 const void *Decoder) { 5639 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5640 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5641 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5642 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5643 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5644 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5645 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5646 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5647 5648 DecodeStatus S = MCDisassembler::Success; 5649 5650 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5651 5652 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5653 return MCDisassembler::Fail; 5654 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5655 return MCDisassembler::Fail; 5656 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5657 return MCDisassembler::Fail; 5658 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5659 return MCDisassembler::Fail; 5660 // The lane index does not have any bits in the encoding, because it can only 5661 // be 0. 5662 Inst.addOperand(MCOperand::createImm(0)); 5663 Inst.addOperand(MCOperand::createImm(rotate)); 5664 5665 return S; 5666 } 5667 5668 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5669 uint64_t Address, const void *Decoder) { 5670 DecodeStatus S = MCDisassembler::Success; 5671 5672 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5673 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5674 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5675 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5676 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5677 5678 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5679 S = MCDisassembler::SoftFail; 5680 5681 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5682 return MCDisassembler::Fail; 5683 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5684 return MCDisassembler::Fail; 5685 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5686 return MCDisassembler::Fail; 5687 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5688 return MCDisassembler::Fail; 5689 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5690 return MCDisassembler::Fail; 5691 5692 return S; 5693 } 5694 5695 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5696 uint64_t Address, const void *Decoder) { 5697 DecodeStatus S = MCDisassembler::Success; 5698 5699 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5700 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5701 unsigned cop = fieldFromInstruction(Val, 8, 4); 5702 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5703 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5704 5705 if ((cop & ~0x1) == 0xa) 5706 return MCDisassembler::Fail; 5707 5708 if (Rt == Rt2) 5709 S = MCDisassembler::SoftFail; 5710 5711 // We have to check if the instruction is MRRC2 5712 // or MCRR2 when constructing the operands for 5713 // Inst. Reason is because MRRC2 stores to two 5714 // registers so it's tablegen desc has has two 5715 // outputs whereas MCRR doesn't store to any 5716 // registers so all of it's operands are listed 5717 // as inputs, therefore the operand order for 5718 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5719 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5720 5721 if (Inst.getOpcode() == ARM::MRRC2) { 5722 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5723 return MCDisassembler::Fail; 5724 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5725 return MCDisassembler::Fail; 5726 } 5727 Inst.addOperand(MCOperand::createImm(cop)); 5728 Inst.addOperand(MCOperand::createImm(opc1)); 5729 if (Inst.getOpcode() == ARM::MCRR2) { 5730 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5731 return MCDisassembler::Fail; 5732 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5733 return MCDisassembler::Fail; 5734 } 5735 Inst.addOperand(MCOperand::createImm(CRm)); 5736 5737 return S; 5738 } 5739 5740 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5741 uint64_t Address, 5742 const void *Decoder) { 5743 const FeatureBitset &featureBits = 5744 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5745 DecodeStatus S = MCDisassembler::Success; 5746 5747 // Add explicit operand for the destination sysreg, for cases where 5748 // we have to model it for code generation purposes. 5749 switch (Inst.getOpcode()) { 5750 case ARM::VMSR_FPSCR_NZCVQC: 5751 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5752 break; 5753 case ARM::VMSR_P0: 5754 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5755 break; 5756 } 5757 5758 if (Inst.getOpcode() != ARM::FMSTAT) { 5759 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5760 5761 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5762 if (Rt == 13 || Rt == 15) 5763 S = MCDisassembler::SoftFail; 5764 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5765 } else 5766 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5767 } 5768 5769 // Add explicit operand for the source sysreg, similarly to above. 5770 switch (Inst.getOpcode()) { 5771 case ARM::VMRS_FPSCR_NZCVQC: 5772 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5773 break; 5774 case ARM::VMRS_P0: 5775 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5776 break; 5777 } 5778 5779 if (featureBits[ARM::ModeThumb]) { 5780 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5781 Inst.addOperand(MCOperand::createReg(0)); 5782 } else { 5783 unsigned pred = fieldFromInstruction(Val, 28, 4); 5784 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5785 return MCDisassembler::Fail; 5786 } 5787 5788 return S; 5789 } 5790 5791 template <bool isSigned, bool isNeg, int size> 5792 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5793 uint64_t Address, 5794 const void *Decoder) { 5795 DecodeStatus S = MCDisassembler::Success; 5796 if (Val == 0) 5797 S = MCDisassembler::SoftFail; 5798 5799 uint64_t DecVal; 5800 if (isSigned) 5801 DecVal = SignExtend32<size + 1>(Val << 1); 5802 else 5803 DecVal = (Val << 1); 5804 5805 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5806 Decoder)) 5807 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5808 return S; 5809 } 5810 5811 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5812 uint64_t Address, 5813 const void *Decoder) { 5814 5815 uint64_t LocImm = Inst.getOperand(0).getImm(); 5816 Val = LocImm + (2 << Val); 5817 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5818 Decoder)) 5819 Inst.addOperand(MCOperand::createImm(Val)); 5820 return MCDisassembler::Success; 5821 } 5822 5823 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5824 uint64_t Address, 5825 const void *Decoder) { 5826 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5827 return MCDisassembler::Fail; 5828 Inst.addOperand(MCOperand::createImm(Val)); 5829 return MCDisassembler::Success; 5830 } 5831 5832 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5833 const void *Decoder) { 5834 DecodeStatus S = MCDisassembler::Success; 5835 5836 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5837 fieldFromInstruction(Insn, 1, 10) << 1; 5838 switch (Inst.getOpcode()) { 5839 case ARM::t2LEUpdate: 5840 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5841 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5842 LLVM_FALLTHROUGH; 5843 case ARM::t2LE: 5844 if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address, 5845 Decoder))) 5846 return MCDisassembler::Fail; 5847 break; 5848 case ARM::t2WLS: 5849 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5850 if (!Check(S, 5851 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5852 Address, Decoder)) || 5853 !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address, 5854 Decoder))) 5855 return MCDisassembler::Fail; 5856 break; 5857 case ARM::t2DLS: 5858 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5859 if (Rn == 0xF) { 5860 return MCDisassembler::Fail; 5861 } else { 5862 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5863 if (!Check(S, DecoderGPRRegisterClass(Inst, 5864 fieldFromInstruction(Insn, 16, 4), 5865 Address, Decoder))) 5866 return MCDisassembler::Fail; 5867 } 5868 break; 5869 } 5870 return S; 5871 } 5872 5873 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 5874 uint64_t Address, 5875 const void *Decoder) { 5876 DecodeStatus S = MCDisassembler::Success; 5877 5878 if (Val == 0) 5879 Val = 32; 5880 5881 Inst.addOperand(MCOperand::createImm(Val)); 5882 5883 return S; 5884 } 5885 5886 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 5887 uint64_t Address, const void *Decoder) { 5888 if ((RegNo) + 1 > 11) 5889 return MCDisassembler::Fail; 5890 5891 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 5892 Inst.addOperand(MCOperand::createReg(Register)); 5893 return MCDisassembler::Success; 5894 } 5895 5896 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 5897 uint64_t Address, const void *Decoder) { 5898 if ((RegNo) > 14) 5899 return MCDisassembler::Fail; 5900 5901 unsigned Register = GPRDecoderTable[(RegNo)]; 5902 Inst.addOperand(MCOperand::createReg(Register)); 5903 return MCDisassembler::Success; 5904 } 5905 5906 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 5907 const void *Decoder) { 5908 DecodeStatus S = MCDisassembler::Success; 5909 5910 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5911 Inst.addOperand(MCOperand::createReg(0)); 5912 if (Inst.getOpcode() == ARM::VSCCLRMD) { 5913 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 5914 (fieldFromInstruction(Insn, 12, 4) << 8) | 5915 (fieldFromInstruction(Insn, 22, 1) << 12); 5916 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 5917 return MCDisassembler::Fail; 5918 } 5919 } else { 5920 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 5921 (fieldFromInstruction(Insn, 22, 1) << 8) | 5922 (fieldFromInstruction(Insn, 12, 4) << 9); 5923 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 5924 return MCDisassembler::Fail; 5925 } 5926 } 5927 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5928 5929 return S; 5930 } 5931 5932 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 5933 uint64_t Address, 5934 const void *Decoder) { 5935 if (RegNo > 7) 5936 return MCDisassembler::Fail; 5937 5938 unsigned Register = QPRDecoderTable[RegNo]; 5939 Inst.addOperand(MCOperand::createReg(Register)); 5940 return MCDisassembler::Success; 5941 } 5942 5943 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 5944 uint64_t Address, 5945 const void *Decoder) { 5946 DecodeStatus S = MCDisassembler::Success; 5947 5948 // Parse VPT mask and encode it in the MCInst as an immediate with the same 5949 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 5950 // 't' as 0 and finish with a 1. 5951 unsigned Imm = 0; 5952 // We always start with a 't'. 5953 unsigned CurBit = 0; 5954 for (int i = 3; i >= 0; --i) { 5955 // If the bit we are looking at is not the same as last one, invert the 5956 // CurBit, if it is the same leave it as is. 5957 CurBit ^= (Val >> i) & 1U; 5958 5959 // Encode the CurBit at the right place in the immediate. 5960 Imm |= (CurBit << i); 5961 5962 // If we are done, finish the encoding with a 1. 5963 if ((Val & ~(~0U << i)) == 0) { 5964 Imm |= 1U << i; 5965 break; 5966 } 5967 } 5968 5969 Inst.addOperand(MCOperand::createImm(Imm)); 5970 5971 return S; 5972 } 5973 5974 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 5975 uint64_t Address, const void *Decoder) { 5976 // The vpred_r operand type includes an MQPR register field derived 5977 // from the encoding. But we don't actually want to add an operand 5978 // to the MCInst at this stage, because AddThumbPredicate will do it 5979 // later, and will infer the register number from the TIED_TO 5980 // constraint. So this is a deliberately empty decoder method that 5981 // will inhibit the auto-generated disassembly code from adding an 5982 // operand at all. 5983 return MCDisassembler::Success; 5984 } 5985 5986 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 5987 unsigned Val, 5988 uint64_t Address, 5989 const void *Decoder) { 5990 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 5991 return MCDisassembler::Success; 5992 } 5993 5994 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 5995 unsigned Val, 5996 uint64_t Address, 5997 const void *Decoder) { 5998 unsigned Code; 5999 switch (Val & 0x3) { 6000 case 0: 6001 Code = ARMCC::GE; 6002 break; 6003 case 1: 6004 Code = ARMCC::LT; 6005 break; 6006 case 2: 6007 Code = ARMCC::GT; 6008 break; 6009 case 3: 6010 Code = ARMCC::LE; 6011 break; 6012 } 6013 Inst.addOperand(MCOperand::createImm(Code)); 6014 return MCDisassembler::Success; 6015 } 6016 6017 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6018 unsigned Val, 6019 uint64_t Address, 6020 const void *Decoder) { 6021 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6022 return MCDisassembler::Success; 6023 } 6024 6025 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6026 uint64_t Address, 6027 const void *Decoder) { 6028 unsigned Code; 6029 switch (Val) { 6030 default: 6031 return MCDisassembler::Fail; 6032 case 0: 6033 Code = ARMCC::EQ; 6034 break; 6035 case 1: 6036 Code = ARMCC::NE; 6037 break; 6038 case 4: 6039 Code = ARMCC::GE; 6040 break; 6041 case 5: 6042 Code = ARMCC::LT; 6043 break; 6044 case 6: 6045 Code = ARMCC::GT; 6046 break; 6047 case 7: 6048 Code = ARMCC::LE; 6049 break; 6050 } 6051 6052 Inst.addOperand(MCOperand::createImm(Code)); 6053 return MCDisassembler::Success; 6054 } 6055 6056 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6057 uint64_t Address, const void *Decoder) { 6058 DecodeStatus S = MCDisassembler::Success; 6059 6060 unsigned DecodedVal = 64 - Val; 6061 6062 switch (Inst.getOpcode()) { 6063 case ARM::MVE_VCVTf16s16_fix: 6064 case ARM::MVE_VCVTs16f16_fix: 6065 case ARM::MVE_VCVTf16u16_fix: 6066 case ARM::MVE_VCVTu16f16_fix: 6067 if (DecodedVal > 16) 6068 return MCDisassembler::Fail; 6069 break; 6070 case ARM::MVE_VCVTf32s32_fix: 6071 case ARM::MVE_VCVTs32f32_fix: 6072 case ARM::MVE_VCVTf32u32_fix: 6073 case ARM::MVE_VCVTu32f32_fix: 6074 if (DecodedVal > 32) 6075 return MCDisassembler::Fail; 6076 break; 6077 } 6078 6079 Inst.addOperand(MCOperand::createImm(64 - Val)); 6080 6081 return S; 6082 } 6083 6084 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6085 switch (Opcode) { 6086 case ARM::VSTR_P0_off: 6087 case ARM::VSTR_P0_pre: 6088 case ARM::VSTR_P0_post: 6089 case ARM::VLDR_P0_off: 6090 case ARM::VLDR_P0_pre: 6091 case ARM::VLDR_P0_post: 6092 return ARM::P0; 6093 default: 6094 return 0; 6095 } 6096 } 6097 6098 template<bool Writeback> 6099 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6100 uint64_t Address, 6101 const void *Decoder) { 6102 switch (Inst.getOpcode()) { 6103 case ARM::VSTR_FPSCR_pre: 6104 case ARM::VSTR_FPSCR_NZCVQC_pre: 6105 case ARM::VLDR_FPSCR_pre: 6106 case ARM::VLDR_FPSCR_NZCVQC_pre: 6107 case ARM::VSTR_FPSCR_off: 6108 case ARM::VSTR_FPSCR_NZCVQC_off: 6109 case ARM::VLDR_FPSCR_off: 6110 case ARM::VLDR_FPSCR_NZCVQC_off: 6111 case ARM::VSTR_FPSCR_post: 6112 case ARM::VSTR_FPSCR_NZCVQC_post: 6113 case ARM::VLDR_FPSCR_post: 6114 case ARM::VLDR_FPSCR_NZCVQC_post: 6115 const FeatureBitset &featureBits = 6116 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6117 6118 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6119 return MCDisassembler::Fail; 6120 } 6121 6122 DecodeStatus S = MCDisassembler::Success; 6123 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6124 Inst.addOperand(MCOperand::createReg(Sysreg)); 6125 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6126 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6127 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6128 6129 if (Writeback) { 6130 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6131 return MCDisassembler::Fail; 6132 } 6133 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6134 return MCDisassembler::Fail; 6135 6136 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6137 Inst.addOperand(MCOperand::createReg(0)); 6138 6139 return S; 6140 } 6141 6142 template<unsigned MinLog, unsigned MaxLog> 6143 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6144 uint64_t Address, 6145 const void *Decoder) { 6146 DecodeStatus S = MCDisassembler::Success; 6147 6148 if (Val < MinLog || Val > MaxLog) 6149 return MCDisassembler::Fail; 6150 6151 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6152 return S; 6153 } 6154 6155 template <int shift> 6156 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6157 uint64_t Address, 6158 const void *Decoder) { 6159 Val <<= shift; 6160 6161 Inst.addOperand(MCOperand::createImm(Val)); 6162 return MCDisassembler::Success; 6163 } 6164 6165 template<unsigned start> 6166 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6167 uint64_t Address, 6168 const void *Decoder) { 6169 DecodeStatus S = MCDisassembler::Success; 6170 6171 Inst.addOperand(MCOperand::createImm(start + Val)); 6172 6173 return S; 6174 } 6175 6176 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6177 uint64_t Address, const void *Decoder) { 6178 DecodeStatus S = MCDisassembler::Success; 6179 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6180 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6181 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6182 fieldFromInstruction(Insn, 13, 3)); 6183 unsigned index = fieldFromInstruction(Insn, 4, 1); 6184 6185 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6186 return MCDisassembler::Fail; 6187 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6188 return MCDisassembler::Fail; 6189 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6190 return MCDisassembler::Fail; 6191 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6192 return MCDisassembler::Fail; 6193 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6194 return MCDisassembler::Fail; 6195 6196 return S; 6197 } 6198 6199 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6200 uint64_t Address, const void *Decoder) { 6201 DecodeStatus S = MCDisassembler::Success; 6202 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6203 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6204 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6205 fieldFromInstruction(Insn, 13, 3)); 6206 unsigned index = fieldFromInstruction(Insn, 4, 1); 6207 6208 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6209 return MCDisassembler::Fail; 6210 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6211 return MCDisassembler::Fail; 6212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6213 return MCDisassembler::Fail; 6214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6215 return MCDisassembler::Fail; 6216 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6217 return MCDisassembler::Fail; 6218 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6219 return MCDisassembler::Fail; 6220 6221 return S; 6222 } 6223 6224 static DecodeStatus DecodeMVEOverlappingLongShift( 6225 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6226 DecodeStatus S = MCDisassembler::Success; 6227 6228 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6229 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6230 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6231 6232 if (RdaHi == 14) { 6233 // This value of RdaHi (really indicating pc, because RdaHi has to 6234 // be an odd-numbered register, so the low bit will be set by the 6235 // decode function below) indicates that we must decode as SQRSHR 6236 // or UQRSHL, which both have a single Rda register field with all 6237 // four bits. 6238 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6239 6240 switch (Inst.getOpcode()) { 6241 case ARM::MVE_ASRLr: 6242 case ARM::MVE_SQRSHRL: 6243 Inst.setOpcode(ARM::MVE_SQRSHR); 6244 break; 6245 case ARM::MVE_LSLLr: 6246 case ARM::MVE_UQRSHLL: 6247 Inst.setOpcode(ARM::MVE_UQRSHL); 6248 break; 6249 default: 6250 llvm_unreachable("Unexpected starting opcode!"); 6251 } 6252 6253 // Rda as output parameter 6254 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6255 return MCDisassembler::Fail; 6256 6257 // Rda again as input parameter 6258 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6259 return MCDisassembler::Fail; 6260 6261 // Rm, the amount to shift by 6262 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6263 return MCDisassembler::Fail; 6264 6265 return S; 6266 } 6267 6268 // Otherwise, we decode as whichever opcode our caller has already 6269 // put into Inst. Those all look the same: 6270 6271 // RdaLo,RdaHi as output parameters 6272 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6273 return MCDisassembler::Fail; 6274 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6275 return MCDisassembler::Fail; 6276 6277 // RdaLo,RdaHi again as input parameters 6278 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6279 return MCDisassembler::Fail; 6280 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6281 return MCDisassembler::Fail; 6282 6283 // Rm, the amount to shift by 6284 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6285 return MCDisassembler::Fail; 6286 6287 return S; 6288 } 6289 6290 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6291 const void *Decoder) { 6292 DecodeStatus S = MCDisassembler::Success; 6293 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6294 fieldFromInstruction(Insn, 13, 3)); 6295 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6296 fieldFromInstruction(Insn, 1, 3)); 6297 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6298 6299 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6300 return MCDisassembler::Fail; 6301 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6302 return MCDisassembler::Fail; 6303 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6304 return MCDisassembler::Fail; 6305 6306 return S; 6307 } 6308 6309 template<bool scalar, OperandDecoder predicate_decoder> 6310 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6311 const void *Decoder) { 6312 DecodeStatus S = MCDisassembler::Success; 6313 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6314 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6315 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6316 return MCDisassembler::Fail; 6317 6318 unsigned fc; 6319 6320 if (scalar) { 6321 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6322 fieldFromInstruction(Insn, 7, 1) | 6323 fieldFromInstruction(Insn, 5, 1) << 1; 6324 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6325 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6326 return MCDisassembler::Fail; 6327 } else { 6328 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6329 fieldFromInstruction(Insn, 7, 1) | 6330 fieldFromInstruction(Insn, 0, 1) << 1; 6331 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6332 fieldFromInstruction(Insn, 1, 3); 6333 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6334 return MCDisassembler::Fail; 6335 } 6336 6337 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6338 return MCDisassembler::Fail; 6339 6340 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6341 Inst.addOperand(MCOperand::createReg(0)); 6342 Inst.addOperand(MCOperand::createImm(0)); 6343 6344 return S; 6345 } 6346 6347 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6348 const void *Decoder) { 6349 DecodeStatus S = MCDisassembler::Success; 6350 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6351 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6352 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6353 return MCDisassembler::Fail; 6354 return S; 6355 } 6356