1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/ARMAddressingModes.h" 10 #include "MCTargetDesc/ARMBaseInfo.h" 11 #include "MCTargetDesc/ARMMCTargetDesc.h" 12 #include "Utils/ARMBaseInfo.h" 13 #include "llvm/MC/MCContext.h" 14 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 15 #include "llvm/MC/MCFixedLenDisassembler.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCSubtargetInfo.h" 19 #include "llvm/MC/SubtargetFeature.h" 20 #include "llvm/Support/Compiler.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <algorithm> 26 #include <cassert> 27 #include <cstdint> 28 #include <vector> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "arm-disassembler" 33 34 using DecodeStatus = MCDisassembler::DecodeStatus; 35 36 namespace { 37 38 // Handles the condition code status of instructions in IT blocks 39 class ITStatus 40 { 41 public: 42 // Returns the condition code for instruction in IT block 43 unsigned getITCC() { 44 unsigned CC = ARMCC::AL; 45 if (instrInITBlock()) 46 CC = ITStates.back(); 47 return CC; 48 } 49 50 // Advances the IT block state to the next T or E 51 void advanceITState() { 52 ITStates.pop_back(); 53 } 54 55 // Returns true if the current instruction is in an IT block 56 bool instrInITBlock() { 57 return !ITStates.empty(); 58 } 59 60 // Returns true if current instruction is the last instruction in an IT block 61 bool instrLastInITBlock() { 62 return ITStates.size() == 1; 63 } 64 65 // Called when decoding an IT instruction. Sets the IT state for the following 66 // instructions that for the IT block. Firstcond and Mask correspond to the 67 // fields in the IT instruction encoding. 68 void setITState(char Firstcond, char Mask) { 69 // (3 - the number of trailing zeros) is the number of then / else. 70 unsigned CondBit0 = Firstcond & 1; 71 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 72 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 73 assert(NumTZ <= 3 && "Invalid IT mask!"); 74 // push condition codes onto the stack the correct order for the pops 75 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 76 bool T = ((Mask >> Pos) & 1) == CondBit0; 77 if (T) 78 ITStates.push_back(CCBits); 79 else 80 ITStates.push_back(CCBits ^ 1); 81 } 82 ITStates.push_back(CCBits); 83 } 84 85 private: 86 std::vector<unsigned char> ITStates; 87 }; 88 89 /// ARM disassembler for all ARM platforms. 90 class ARMDisassembler : public MCDisassembler { 91 public: 92 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 93 MCDisassembler(STI, Ctx) { 94 } 95 96 ~ARMDisassembler() override = default; 97 98 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 99 ArrayRef<uint8_t> Bytes, uint64_t Address, 100 raw_ostream &VStream, 101 raw_ostream &CStream) const override; 102 }; 103 104 /// Thumb disassembler for all Thumb platforms. 105 class ThumbDisassembler : public MCDisassembler { 106 public: 107 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 108 MCDisassembler(STI, Ctx) { 109 } 110 111 ~ThumbDisassembler() override = default; 112 113 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 114 ArrayRef<uint8_t> Bytes, uint64_t Address, 115 raw_ostream &VStream, 116 raw_ostream &CStream) const override; 117 118 private: 119 mutable ITStatus ITBlock; 120 121 DecodeStatus AddThumbPredicate(MCInst&) const; 122 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 123 }; 124 125 } // end anonymous namespace 126 127 static bool Check(DecodeStatus &Out, DecodeStatus In) { 128 switch (In) { 129 case MCDisassembler::Success: 130 // Out stays the same. 131 return true; 132 case MCDisassembler::SoftFail: 133 Out = In; 134 return true; 135 case MCDisassembler::Fail: 136 Out = In; 137 return false; 138 } 139 llvm_unreachable("Invalid DecodeStatus!"); 140 } 141 142 // Forward declare these because the autogenerated code will reference them. 143 // Definitions are further down. 144 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 147 unsigned RegNo, uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 150 unsigned RegNo, uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 169 unsigned RegNo, 170 uint64_t Address, 171 const void *Decoder); 172 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 177 unsigned RegNo, uint64_t Address, 178 const void *Decoder); 179 180 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 191 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 196 unsigned Insn, 197 uint64_t Address, 198 const void *Decoder); 199 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207 208 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 209 unsigned Insn, 210 uint64_t Adddress, 211 const void *Decoder); 212 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 327 unsigned Val, 328 uint64_t Address, 329 const void *Decoder); 330 331 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void* Decoder); 353 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void* Decoder); 355 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void* Decoder); 357 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void* Decoder); 359 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 404 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 411 #include "ARMGenDisassemblerTables.inc" 412 413 static MCDisassembler *createARMDisassembler(const Target &T, 414 const MCSubtargetInfo &STI, 415 MCContext &Ctx) { 416 return new ARMDisassembler(STI, Ctx); 417 } 418 419 static MCDisassembler *createThumbDisassembler(const Target &T, 420 const MCSubtargetInfo &STI, 421 MCContext &Ctx) { 422 return new ThumbDisassembler(STI, Ctx); 423 } 424 425 // Post-decoding checks 426 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 427 uint64_t Address, raw_ostream &OS, 428 raw_ostream &CS, 429 uint32_t Insn, 430 DecodeStatus Result) { 431 switch (MI.getOpcode()) { 432 case ARM::HVC: { 433 // HVC is undefined if condition = 0xf otherwise upredictable 434 // if condition != 0xe 435 uint32_t Cond = (Insn >> 28) & 0xF; 436 if (Cond == 0xF) 437 return MCDisassembler::Fail; 438 if (Cond != 0xE) 439 return MCDisassembler::SoftFail; 440 return Result; 441 } 442 default: return Result; 443 } 444 } 445 446 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 447 ArrayRef<uint8_t> Bytes, 448 uint64_t Address, raw_ostream &OS, 449 raw_ostream &CS) const { 450 CommentStream = &CS; 451 452 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 453 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 454 "mode!"); 455 456 // We want to read exactly 4 bytes of data. 457 if (Bytes.size() < 4) { 458 Size = 0; 459 return MCDisassembler::Fail; 460 } 461 462 // Encoded as a small-endian 32-bit word in the stream. 463 uint32_t Insn = 464 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 465 466 // Calling the auto-generated decoder function. 467 DecodeStatus Result = 468 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 469 if (Result != MCDisassembler::Fail) { 470 Size = 4; 471 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 472 } 473 474 struct DecodeTable { 475 const uint8_t *P; 476 bool DecodePred; 477 }; 478 479 const DecodeTable Tables[] = { 480 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 481 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 482 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 483 {DecoderTablev8Crypto32, false}, 484 }; 485 486 for (auto Table : Tables) { 487 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 488 if (Result != MCDisassembler::Fail) { 489 Size = 4; 490 // Add a fake predicate operand, because we share these instruction 491 // definitions with Thumb2 where these instructions are predicable. 492 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 493 return MCDisassembler::Fail; 494 return Result; 495 } 496 } 497 498 Result = 499 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 500 if (Result != MCDisassembler::Fail) { 501 Size = 4; 502 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 503 } 504 505 Size = 4; 506 return MCDisassembler::Fail; 507 } 508 509 namespace llvm { 510 511 extern const MCInstrDesc ARMInsts[]; 512 513 } // end namespace llvm 514 515 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 516 /// immediate Value in the MCInst. The immediate Value has had any PC 517 /// adjustment made by the caller. If the instruction is a branch instruction 518 /// then isBranch is true, else false. If the getOpInfo() function was set as 519 /// part of the setupForSymbolicDisassembly() call then that function is called 520 /// to get any symbolic information at the Address for this instruction. If 521 /// that returns non-zero then the symbolic information it returns is used to 522 /// create an MCExpr and that is added as an operand to the MCInst. If 523 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 524 /// Value is done and if a symbol is found an MCExpr is created with that, else 525 /// an MCExpr with Value is created. This function returns true if it adds an 526 /// operand to the MCInst and false otherwise. 527 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 528 bool isBranch, uint64_t InstSize, 529 MCInst &MI, const void *Decoder) { 530 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 531 // FIXME: Does it make sense for value to be negative? 532 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 533 /* Offset */ 0, InstSize); 534 } 535 536 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 537 /// referenced by a load instruction with the base register that is the Pc. 538 /// These can often be values in a literal pool near the Address of the 539 /// instruction. The Address of the instruction and its immediate Value are 540 /// used as a possible literal pool entry. The SymbolLookUp call back will 541 /// return the name of a symbol referenced by the literal pool's entry if 542 /// the referenced address is that of a symbol. Or it will return a pointer to 543 /// a literal 'C' string if the referenced address of the literal pool's entry 544 /// is an address into a section with 'C' string literals. 545 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 546 const void *Decoder) { 547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 548 Dis->tryAddingPcLoadReferenceComment(Value, Address); 549 } 550 551 // Thumb1 instructions don't have explicit S bits. Rather, they 552 // implicitly set CPSR. Since it's not represented in the encoding, the 553 // auto-generated decoder won't inject the CPSR operand. We need to fix 554 // that as a post-pass. 555 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 556 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 557 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 558 MCInst::iterator I = MI.begin(); 559 for (unsigned i = 0; i < NumOps; ++i, ++I) { 560 if (I == MI.end()) break; 561 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 562 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 563 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 564 return; 565 } 566 } 567 568 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 569 } 570 571 // Most Thumb instructions don't have explicit predicates in the 572 // encoding, but rather get their predicates from IT context. We need 573 // to fix up the predicate operands using this context information as a 574 // post-pass. 575 MCDisassembler::DecodeStatus 576 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 577 MCDisassembler::DecodeStatus S = Success; 578 579 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 580 581 // A few instructions actually have predicates encoded in them. Don't 582 // try to overwrite it if we're seeing one of those. 583 switch (MI.getOpcode()) { 584 case ARM::tBcc: 585 case ARM::t2Bcc: 586 case ARM::tCBZ: 587 case ARM::tCBNZ: 588 case ARM::tCPS: 589 case ARM::t2CPS3p: 590 case ARM::t2CPS2p: 591 case ARM::t2CPS1p: 592 case ARM::tMOVSr: 593 case ARM::tSETEND: 594 // Some instructions (mostly conditional branches) are not 595 // allowed in IT blocks. 596 if (ITBlock.instrInITBlock()) 597 S = SoftFail; 598 else 599 return Success; 600 break; 601 case ARM::t2HINT: 602 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 603 S = SoftFail; 604 break; 605 case ARM::tB: 606 case ARM::t2B: 607 case ARM::t2TBB: 608 case ARM::t2TBH: 609 // Some instructions (mostly unconditional branches) can 610 // only appears at the end of, or outside of, an IT. 611 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 612 S = SoftFail; 613 break; 614 default: 615 break; 616 } 617 618 // If we're in an IT block, base the predicate on that. Otherwise, 619 // assume a predicate of AL. 620 unsigned CC; 621 CC = ITBlock.getITCC(); 622 if (CC == 0xF) 623 CC = ARMCC::AL; 624 if (ITBlock.instrInITBlock()) 625 ITBlock.advanceITState(); 626 627 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 628 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 629 MCInst::iterator I = MI.begin(); 630 for (unsigned i = 0; i < NumOps; ++i, ++I) { 631 if (I == MI.end()) break; 632 if (OpInfo[i].isPredicate()) { 633 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 634 Check(S, SoftFail); 635 I = MI.insert(I, MCOperand::createImm(CC)); 636 ++I; 637 if (CC == ARMCC::AL) 638 MI.insert(I, MCOperand::createReg(0)); 639 else 640 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 641 return S; 642 } 643 } 644 645 I = MI.insert(I, MCOperand::createImm(CC)); 646 ++I; 647 if (CC == ARMCC::AL) 648 MI.insert(I, MCOperand::createReg(0)); 649 else 650 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 651 652 return S; 653 } 654 655 // Thumb VFP instructions are a special case. Because we share their 656 // encodings between ARM and Thumb modes, and they are predicable in ARM 657 // mode, the auto-generated decoder will give them an (incorrect) 658 // predicate operand. We need to rewrite these operands based on the IT 659 // context as a post-pass. 660 void ThumbDisassembler::UpdateThumbVFPPredicate( 661 DecodeStatus &S, MCInst &MI) const { 662 unsigned CC; 663 CC = ITBlock.getITCC(); 664 if (CC == 0xF) 665 CC = ARMCC::AL; 666 if (ITBlock.instrInITBlock()) 667 ITBlock.advanceITState(); 668 669 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 670 MCInst::iterator I = MI.begin(); 671 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 672 for (unsigned i = 0; i < NumOps; ++i, ++I) { 673 if (OpInfo[i].isPredicate() ) { 674 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 675 Check(S, SoftFail); 676 I->setImm(CC); 677 ++I; 678 if (CC == ARMCC::AL) 679 I->setReg(0); 680 else 681 I->setReg(ARM::CPSR); 682 return; 683 } 684 } 685 } 686 687 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 688 ArrayRef<uint8_t> Bytes, 689 uint64_t Address, 690 raw_ostream &OS, 691 raw_ostream &CS) const { 692 CommentStream = &CS; 693 694 assert(STI.getFeatureBits()[ARM::ModeThumb] && 695 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 696 697 // We want to read exactly 2 bytes of data. 698 if (Bytes.size() < 2) { 699 Size = 0; 700 return MCDisassembler::Fail; 701 } 702 703 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 704 DecodeStatus Result = 705 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 706 if (Result != MCDisassembler::Fail) { 707 Size = 2; 708 Check(Result, AddThumbPredicate(MI)); 709 return Result; 710 } 711 712 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 713 STI); 714 if (Result) { 715 Size = 2; 716 bool InITBlock = ITBlock.instrInITBlock(); 717 Check(Result, AddThumbPredicate(MI)); 718 AddThumb1SBit(MI, InITBlock); 719 return Result; 720 } 721 722 Result = 723 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 724 if (Result != MCDisassembler::Fail) { 725 Size = 2; 726 727 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 728 // the Thumb predicate. 729 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 730 Result = MCDisassembler::SoftFail; 731 732 Check(Result, AddThumbPredicate(MI)); 733 734 // If we find an IT instruction, we need to parse its condition 735 // code and mask operands so that we can apply them correctly 736 // to the subsequent instructions. 737 if (MI.getOpcode() == ARM::t2IT) { 738 unsigned Firstcond = MI.getOperand(0).getImm(); 739 unsigned Mask = MI.getOperand(1).getImm(); 740 ITBlock.setITState(Firstcond, Mask); 741 742 // An IT instruction that would give a 'NV' predicate is unpredictable. 743 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 744 CS << "unpredictable IT predicate sequence"; 745 } 746 747 return Result; 748 } 749 750 // We want to read exactly 4 bytes of data. 751 if (Bytes.size() < 4) { 752 Size = 0; 753 return MCDisassembler::Fail; 754 } 755 756 uint32_t Insn32 = 757 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 758 Result = 759 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 760 if (Result != MCDisassembler::Fail) { 761 Size = 4; 762 bool InITBlock = ITBlock.instrInITBlock(); 763 Check(Result, AddThumbPredicate(MI)); 764 AddThumb1SBit(MI, InITBlock); 765 return Result; 766 } 767 768 Result = 769 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 770 if (Result != MCDisassembler::Fail) { 771 Size = 4; 772 Check(Result, AddThumbPredicate(MI)); 773 return Result; 774 } 775 776 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 777 Result = 778 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 779 if (Result != MCDisassembler::Fail) { 780 Size = 4; 781 UpdateThumbVFPPredicate(Result, MI); 782 return Result; 783 } 784 } 785 786 Result = 787 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 788 if (Result != MCDisassembler::Fail) { 789 Size = 4; 790 return Result; 791 } 792 793 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 794 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 795 STI); 796 if (Result != MCDisassembler::Fail) { 797 Size = 4; 798 Check(Result, AddThumbPredicate(MI)); 799 return Result; 800 } 801 } 802 803 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 804 uint32_t NEONLdStInsn = Insn32; 805 NEONLdStInsn &= 0xF0FFFFFF; 806 NEONLdStInsn |= 0x04000000; 807 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 808 Address, this, STI); 809 if (Result != MCDisassembler::Fail) { 810 Size = 4; 811 Check(Result, AddThumbPredicate(MI)); 812 return Result; 813 } 814 } 815 816 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 817 uint32_t NEONDataInsn = Insn32; 818 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 819 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 820 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 821 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 822 Address, this, STI); 823 if (Result != MCDisassembler::Fail) { 824 Size = 4; 825 Check(Result, AddThumbPredicate(MI)); 826 return Result; 827 } 828 829 uint32_t NEONCryptoInsn = Insn32; 830 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 831 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 832 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 833 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 834 Address, this, STI); 835 if (Result != MCDisassembler::Fail) { 836 Size = 4; 837 return Result; 838 } 839 840 uint32_t NEONv8Insn = Insn32; 841 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 842 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 843 this, STI); 844 if (Result != MCDisassembler::Fail) { 845 Size = 4; 846 return Result; 847 } 848 } 849 850 Result = 851 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 852 if (Result != MCDisassembler::Fail) { 853 Size = 4; 854 Check(Result, AddThumbPredicate(MI)); 855 return Result; 856 } 857 858 Size = 0; 859 return MCDisassembler::Fail; 860 } 861 862 extern "C" void LLVMInitializeARMDisassembler() { 863 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 864 createARMDisassembler); 865 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 866 createARMDisassembler); 867 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 868 createThumbDisassembler); 869 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 870 createThumbDisassembler); 871 } 872 873 static const uint16_t GPRDecoderTable[] = { 874 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 875 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 876 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 877 ARM::R12, ARM::SP, ARM::LR, ARM::PC 878 }; 879 880 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 881 uint64_t Address, const void *Decoder) { 882 if (RegNo > 15) 883 return MCDisassembler::Fail; 884 885 unsigned Register = GPRDecoderTable[RegNo]; 886 Inst.addOperand(MCOperand::createReg(Register)); 887 return MCDisassembler::Success; 888 } 889 890 static DecodeStatus 891 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 892 uint64_t Address, const void *Decoder) { 893 DecodeStatus S = MCDisassembler::Success; 894 895 if (RegNo == 15) 896 S = MCDisassembler::SoftFail; 897 898 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 899 900 return S; 901 } 902 903 static DecodeStatus 904 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 905 uint64_t Address, const void *Decoder) { 906 DecodeStatus S = MCDisassembler::Success; 907 908 if (RegNo == 15) 909 { 910 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 911 return MCDisassembler::Success; 912 } 913 914 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 915 return S; 916 } 917 918 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 919 uint64_t Address, const void *Decoder) { 920 if (RegNo > 7) 921 return MCDisassembler::Fail; 922 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 923 } 924 925 static const uint16_t GPRPairDecoderTable[] = { 926 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 927 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 928 }; 929 930 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 931 uint64_t Address, const void *Decoder) { 932 DecodeStatus S = MCDisassembler::Success; 933 934 if (RegNo > 13) 935 return MCDisassembler::Fail; 936 937 if ((RegNo & 1) || RegNo == 0xe) 938 S = MCDisassembler::SoftFail; 939 940 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 941 Inst.addOperand(MCOperand::createReg(RegisterPair)); 942 return S; 943 } 944 945 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 946 uint64_t Address, const void *Decoder) { 947 unsigned Register = 0; 948 switch (RegNo) { 949 case 0: 950 Register = ARM::R0; 951 break; 952 case 1: 953 Register = ARM::R1; 954 break; 955 case 2: 956 Register = ARM::R2; 957 break; 958 case 3: 959 Register = ARM::R3; 960 break; 961 case 9: 962 Register = ARM::R9; 963 break; 964 case 12: 965 Register = ARM::R12; 966 break; 967 default: 968 return MCDisassembler::Fail; 969 } 970 971 Inst.addOperand(MCOperand::createReg(Register)); 972 return MCDisassembler::Success; 973 } 974 975 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 976 uint64_t Address, const void *Decoder) { 977 DecodeStatus S = MCDisassembler::Success; 978 979 const FeatureBitset &featureBits = 980 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 981 982 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 983 S = MCDisassembler::SoftFail; 984 985 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 986 return S; 987 } 988 989 static const uint16_t SPRDecoderTable[] = { 990 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 991 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 992 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 993 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 994 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 995 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 996 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 997 ARM::S28, ARM::S29, ARM::S30, ARM::S31 998 }; 999 1000 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1001 uint64_t Address, const void *Decoder) { 1002 if (RegNo > 31) 1003 return MCDisassembler::Fail; 1004 1005 unsigned Register = SPRDecoderTable[RegNo]; 1006 Inst.addOperand(MCOperand::createReg(Register)); 1007 return MCDisassembler::Success; 1008 } 1009 1010 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1011 uint64_t Address, const void *Decoder) { 1012 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1013 } 1014 1015 static const uint16_t DPRDecoderTable[] = { 1016 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1017 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1018 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1019 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1020 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1021 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1022 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1023 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1024 }; 1025 1026 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1027 uint64_t Address, const void *Decoder) { 1028 const FeatureBitset &featureBits = 1029 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1030 1031 bool hasD16 = featureBits[ARM::FeatureD16]; 1032 1033 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1034 return MCDisassembler::Fail; 1035 1036 unsigned Register = DPRDecoderTable[RegNo]; 1037 Inst.addOperand(MCOperand::createReg(Register)); 1038 return MCDisassembler::Success; 1039 } 1040 1041 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1042 uint64_t Address, const void *Decoder) { 1043 if (RegNo > 7) 1044 return MCDisassembler::Fail; 1045 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1046 } 1047 1048 static DecodeStatus 1049 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1050 uint64_t Address, const void *Decoder) { 1051 if (RegNo > 15) 1052 return MCDisassembler::Fail; 1053 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1054 } 1055 1056 static const uint16_t QPRDecoderTable[] = { 1057 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1058 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1059 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1060 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1061 }; 1062 1063 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1064 uint64_t Address, const void *Decoder) { 1065 if (RegNo > 31 || (RegNo & 1) != 0) 1066 return MCDisassembler::Fail; 1067 RegNo >>= 1; 1068 1069 unsigned Register = QPRDecoderTable[RegNo]; 1070 Inst.addOperand(MCOperand::createReg(Register)); 1071 return MCDisassembler::Success; 1072 } 1073 1074 static const uint16_t DPairDecoderTable[] = { 1075 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1076 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1077 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1078 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1079 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1080 ARM::Q15 1081 }; 1082 1083 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1084 uint64_t Address, const void *Decoder) { 1085 if (RegNo > 30) 1086 return MCDisassembler::Fail; 1087 1088 unsigned Register = DPairDecoderTable[RegNo]; 1089 Inst.addOperand(MCOperand::createReg(Register)); 1090 return MCDisassembler::Success; 1091 } 1092 1093 static const uint16_t DPairSpacedDecoderTable[] = { 1094 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1095 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1096 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1097 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1098 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1099 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1100 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1101 ARM::D28_D30, ARM::D29_D31 1102 }; 1103 1104 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1105 unsigned RegNo, 1106 uint64_t Address, 1107 const void *Decoder) { 1108 if (RegNo > 29) 1109 return MCDisassembler::Fail; 1110 1111 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1112 Inst.addOperand(MCOperand::createReg(Register)); 1113 return MCDisassembler::Success; 1114 } 1115 1116 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1117 uint64_t Address, const void *Decoder) { 1118 DecodeStatus S = MCDisassembler::Success; 1119 if (Val == 0xF) return MCDisassembler::Fail; 1120 // AL predicate is not allowed on Thumb1 branches. 1121 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1122 return MCDisassembler::Fail; 1123 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1124 Check(S, MCDisassembler::SoftFail); 1125 Inst.addOperand(MCOperand::createImm(Val)); 1126 if (Val == ARMCC::AL) { 1127 Inst.addOperand(MCOperand::createReg(0)); 1128 } else 1129 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1130 return S; 1131 } 1132 1133 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1134 uint64_t Address, const void *Decoder) { 1135 if (Val) 1136 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1137 else 1138 Inst.addOperand(MCOperand::createReg(0)); 1139 return MCDisassembler::Success; 1140 } 1141 1142 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1143 uint64_t Address, const void *Decoder) { 1144 DecodeStatus S = MCDisassembler::Success; 1145 1146 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1147 unsigned type = fieldFromInstruction(Val, 5, 2); 1148 unsigned imm = fieldFromInstruction(Val, 7, 5); 1149 1150 // Register-immediate 1151 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1152 return MCDisassembler::Fail; 1153 1154 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1155 switch (type) { 1156 case 0: 1157 Shift = ARM_AM::lsl; 1158 break; 1159 case 1: 1160 Shift = ARM_AM::lsr; 1161 break; 1162 case 2: 1163 Shift = ARM_AM::asr; 1164 break; 1165 case 3: 1166 Shift = ARM_AM::ror; 1167 break; 1168 } 1169 1170 if (Shift == ARM_AM::ror && imm == 0) 1171 Shift = ARM_AM::rrx; 1172 1173 unsigned Op = Shift | (imm << 3); 1174 Inst.addOperand(MCOperand::createImm(Op)); 1175 1176 return S; 1177 } 1178 1179 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1180 uint64_t Address, const void *Decoder) { 1181 DecodeStatus S = MCDisassembler::Success; 1182 1183 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1184 unsigned type = fieldFromInstruction(Val, 5, 2); 1185 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1186 1187 // Register-register 1188 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1189 return MCDisassembler::Fail; 1190 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1191 return MCDisassembler::Fail; 1192 1193 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1194 switch (type) { 1195 case 0: 1196 Shift = ARM_AM::lsl; 1197 break; 1198 case 1: 1199 Shift = ARM_AM::lsr; 1200 break; 1201 case 2: 1202 Shift = ARM_AM::asr; 1203 break; 1204 case 3: 1205 Shift = ARM_AM::ror; 1206 break; 1207 } 1208 1209 Inst.addOperand(MCOperand::createImm(Shift)); 1210 1211 return S; 1212 } 1213 1214 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1215 uint64_t Address, const void *Decoder) { 1216 DecodeStatus S = MCDisassembler::Success; 1217 1218 bool NeedDisjointWriteback = false; 1219 unsigned WritebackReg = 0; 1220 switch (Inst.getOpcode()) { 1221 default: 1222 break; 1223 case ARM::LDMIA_UPD: 1224 case ARM::LDMDB_UPD: 1225 case ARM::LDMIB_UPD: 1226 case ARM::LDMDA_UPD: 1227 case ARM::t2LDMIA_UPD: 1228 case ARM::t2LDMDB_UPD: 1229 case ARM::t2STMIA_UPD: 1230 case ARM::t2STMDB_UPD: 1231 NeedDisjointWriteback = true; 1232 WritebackReg = Inst.getOperand(0).getReg(); 1233 break; 1234 } 1235 1236 // Empty register lists are not allowed. 1237 if (Val == 0) return MCDisassembler::Fail; 1238 for (unsigned i = 0; i < 16; ++i) { 1239 if (Val & (1 << i)) { 1240 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1241 return MCDisassembler::Fail; 1242 // Writeback not allowed if Rn is in the target list. 1243 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1244 Check(S, MCDisassembler::SoftFail); 1245 } 1246 } 1247 1248 return S; 1249 } 1250 1251 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1252 uint64_t Address, const void *Decoder) { 1253 DecodeStatus S = MCDisassembler::Success; 1254 1255 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1256 unsigned regs = fieldFromInstruction(Val, 0, 8); 1257 1258 // In case of unpredictable encoding, tweak the operands. 1259 if (regs == 0 || (Vd + regs) > 32) { 1260 regs = Vd + regs > 32 ? 32 - Vd : regs; 1261 regs = std::max( 1u, regs); 1262 S = MCDisassembler::SoftFail; 1263 } 1264 1265 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1266 return MCDisassembler::Fail; 1267 for (unsigned i = 0; i < (regs - 1); ++i) { 1268 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1269 return MCDisassembler::Fail; 1270 } 1271 1272 return S; 1273 } 1274 1275 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1276 uint64_t Address, const void *Decoder) { 1277 DecodeStatus S = MCDisassembler::Success; 1278 1279 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1280 unsigned regs = fieldFromInstruction(Val, 1, 7); 1281 1282 // In case of unpredictable encoding, tweak the operands. 1283 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1284 regs = Vd + regs > 32 ? 32 - Vd : regs; 1285 regs = std::max( 1u, regs); 1286 regs = std::min(16u, regs); 1287 S = MCDisassembler::SoftFail; 1288 } 1289 1290 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1291 return MCDisassembler::Fail; 1292 for (unsigned i = 0; i < (regs - 1); ++i) { 1293 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1294 return MCDisassembler::Fail; 1295 } 1296 1297 return S; 1298 } 1299 1300 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1301 uint64_t Address, const void *Decoder) { 1302 // This operand encodes a mask of contiguous zeros between a specified MSB 1303 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1304 // the mask of all bits LSB-and-lower, and then xor them to create 1305 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1306 // create the final mask. 1307 unsigned msb = fieldFromInstruction(Val, 5, 5); 1308 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1309 1310 DecodeStatus S = MCDisassembler::Success; 1311 if (lsb > msb) { 1312 Check(S, MCDisassembler::SoftFail); 1313 // The check above will cause the warning for the "potentially undefined 1314 // instruction encoding" but we can't build a bad MCOperand value here 1315 // with a lsb > msb or else printing the MCInst will cause a crash. 1316 lsb = msb; 1317 } 1318 1319 uint32_t msb_mask = 0xFFFFFFFF; 1320 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1321 uint32_t lsb_mask = (1U << lsb) - 1; 1322 1323 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1324 return S; 1325 } 1326 1327 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1328 uint64_t Address, const void *Decoder) { 1329 DecodeStatus S = MCDisassembler::Success; 1330 1331 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1332 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1333 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1334 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1335 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1336 unsigned U = fieldFromInstruction(Insn, 23, 1); 1337 1338 switch (Inst.getOpcode()) { 1339 case ARM::LDC_OFFSET: 1340 case ARM::LDC_PRE: 1341 case ARM::LDC_POST: 1342 case ARM::LDC_OPTION: 1343 case ARM::LDCL_OFFSET: 1344 case ARM::LDCL_PRE: 1345 case ARM::LDCL_POST: 1346 case ARM::LDCL_OPTION: 1347 case ARM::STC_OFFSET: 1348 case ARM::STC_PRE: 1349 case ARM::STC_POST: 1350 case ARM::STC_OPTION: 1351 case ARM::STCL_OFFSET: 1352 case ARM::STCL_PRE: 1353 case ARM::STCL_POST: 1354 case ARM::STCL_OPTION: 1355 case ARM::t2LDC_OFFSET: 1356 case ARM::t2LDC_PRE: 1357 case ARM::t2LDC_POST: 1358 case ARM::t2LDC_OPTION: 1359 case ARM::t2LDCL_OFFSET: 1360 case ARM::t2LDCL_PRE: 1361 case ARM::t2LDCL_POST: 1362 case ARM::t2LDCL_OPTION: 1363 case ARM::t2STC_OFFSET: 1364 case ARM::t2STC_PRE: 1365 case ARM::t2STC_POST: 1366 case ARM::t2STC_OPTION: 1367 case ARM::t2STCL_OFFSET: 1368 case ARM::t2STCL_PRE: 1369 case ARM::t2STCL_POST: 1370 case ARM::t2STCL_OPTION: 1371 if (coproc == 0xA || coproc == 0xB) 1372 return MCDisassembler::Fail; 1373 break; 1374 default: 1375 break; 1376 } 1377 1378 const FeatureBitset &featureBits = 1379 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1380 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1381 return MCDisassembler::Fail; 1382 1383 Inst.addOperand(MCOperand::createImm(coproc)); 1384 Inst.addOperand(MCOperand::createImm(CRd)); 1385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1386 return MCDisassembler::Fail; 1387 1388 switch (Inst.getOpcode()) { 1389 case ARM::t2LDC2_OFFSET: 1390 case ARM::t2LDC2L_OFFSET: 1391 case ARM::t2LDC2_PRE: 1392 case ARM::t2LDC2L_PRE: 1393 case ARM::t2STC2_OFFSET: 1394 case ARM::t2STC2L_OFFSET: 1395 case ARM::t2STC2_PRE: 1396 case ARM::t2STC2L_PRE: 1397 case ARM::LDC2_OFFSET: 1398 case ARM::LDC2L_OFFSET: 1399 case ARM::LDC2_PRE: 1400 case ARM::LDC2L_PRE: 1401 case ARM::STC2_OFFSET: 1402 case ARM::STC2L_OFFSET: 1403 case ARM::STC2_PRE: 1404 case ARM::STC2L_PRE: 1405 case ARM::t2LDC_OFFSET: 1406 case ARM::t2LDCL_OFFSET: 1407 case ARM::t2LDC_PRE: 1408 case ARM::t2LDCL_PRE: 1409 case ARM::t2STC_OFFSET: 1410 case ARM::t2STCL_OFFSET: 1411 case ARM::t2STC_PRE: 1412 case ARM::t2STCL_PRE: 1413 case ARM::LDC_OFFSET: 1414 case ARM::LDCL_OFFSET: 1415 case ARM::LDC_PRE: 1416 case ARM::LDCL_PRE: 1417 case ARM::STC_OFFSET: 1418 case ARM::STCL_OFFSET: 1419 case ARM::STC_PRE: 1420 case ARM::STCL_PRE: 1421 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1422 Inst.addOperand(MCOperand::createImm(imm)); 1423 break; 1424 case ARM::t2LDC2_POST: 1425 case ARM::t2LDC2L_POST: 1426 case ARM::t2STC2_POST: 1427 case ARM::t2STC2L_POST: 1428 case ARM::LDC2_POST: 1429 case ARM::LDC2L_POST: 1430 case ARM::STC2_POST: 1431 case ARM::STC2L_POST: 1432 case ARM::t2LDC_POST: 1433 case ARM::t2LDCL_POST: 1434 case ARM::t2STC_POST: 1435 case ARM::t2STCL_POST: 1436 case ARM::LDC_POST: 1437 case ARM::LDCL_POST: 1438 case ARM::STC_POST: 1439 case ARM::STCL_POST: 1440 imm |= U << 8; 1441 LLVM_FALLTHROUGH; 1442 default: 1443 // The 'option' variant doesn't encode 'U' in the immediate since 1444 // the immediate is unsigned [0,255]. 1445 Inst.addOperand(MCOperand::createImm(imm)); 1446 break; 1447 } 1448 1449 switch (Inst.getOpcode()) { 1450 case ARM::LDC_OFFSET: 1451 case ARM::LDC_PRE: 1452 case ARM::LDC_POST: 1453 case ARM::LDC_OPTION: 1454 case ARM::LDCL_OFFSET: 1455 case ARM::LDCL_PRE: 1456 case ARM::LDCL_POST: 1457 case ARM::LDCL_OPTION: 1458 case ARM::STC_OFFSET: 1459 case ARM::STC_PRE: 1460 case ARM::STC_POST: 1461 case ARM::STC_OPTION: 1462 case ARM::STCL_OFFSET: 1463 case ARM::STCL_PRE: 1464 case ARM::STCL_POST: 1465 case ARM::STCL_OPTION: 1466 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1467 return MCDisassembler::Fail; 1468 break; 1469 default: 1470 break; 1471 } 1472 1473 return S; 1474 } 1475 1476 static DecodeStatus 1477 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1478 uint64_t Address, const void *Decoder) { 1479 DecodeStatus S = MCDisassembler::Success; 1480 1481 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1482 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1483 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1484 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1485 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1486 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1487 unsigned P = fieldFromInstruction(Insn, 24, 1); 1488 unsigned W = fieldFromInstruction(Insn, 21, 1); 1489 1490 // On stores, the writeback operand precedes Rt. 1491 switch (Inst.getOpcode()) { 1492 case ARM::STR_POST_IMM: 1493 case ARM::STR_POST_REG: 1494 case ARM::STRB_POST_IMM: 1495 case ARM::STRB_POST_REG: 1496 case ARM::STRT_POST_REG: 1497 case ARM::STRT_POST_IMM: 1498 case ARM::STRBT_POST_REG: 1499 case ARM::STRBT_POST_IMM: 1500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1501 return MCDisassembler::Fail; 1502 break; 1503 default: 1504 break; 1505 } 1506 1507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1508 return MCDisassembler::Fail; 1509 1510 // On loads, the writeback operand comes after Rt. 1511 switch (Inst.getOpcode()) { 1512 case ARM::LDR_POST_IMM: 1513 case ARM::LDR_POST_REG: 1514 case ARM::LDRB_POST_IMM: 1515 case ARM::LDRB_POST_REG: 1516 case ARM::LDRBT_POST_REG: 1517 case ARM::LDRBT_POST_IMM: 1518 case ARM::LDRT_POST_REG: 1519 case ARM::LDRT_POST_IMM: 1520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1521 return MCDisassembler::Fail; 1522 break; 1523 default: 1524 break; 1525 } 1526 1527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1528 return MCDisassembler::Fail; 1529 1530 ARM_AM::AddrOpc Op = ARM_AM::add; 1531 if (!fieldFromInstruction(Insn, 23, 1)) 1532 Op = ARM_AM::sub; 1533 1534 bool writeback = (P == 0) || (W == 1); 1535 unsigned idx_mode = 0; 1536 if (P && writeback) 1537 idx_mode = ARMII::IndexModePre; 1538 else if (!P && writeback) 1539 idx_mode = ARMII::IndexModePost; 1540 1541 if (writeback && (Rn == 15 || Rn == Rt)) 1542 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1543 1544 if (reg) { 1545 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1546 return MCDisassembler::Fail; 1547 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1548 switch( fieldFromInstruction(Insn, 5, 2)) { 1549 case 0: 1550 Opc = ARM_AM::lsl; 1551 break; 1552 case 1: 1553 Opc = ARM_AM::lsr; 1554 break; 1555 case 2: 1556 Opc = ARM_AM::asr; 1557 break; 1558 case 3: 1559 Opc = ARM_AM::ror; 1560 break; 1561 default: 1562 return MCDisassembler::Fail; 1563 } 1564 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1565 if (Opc == ARM_AM::ror && amt == 0) 1566 Opc = ARM_AM::rrx; 1567 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1568 1569 Inst.addOperand(MCOperand::createImm(imm)); 1570 } else { 1571 Inst.addOperand(MCOperand::createReg(0)); 1572 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1573 Inst.addOperand(MCOperand::createImm(tmp)); 1574 } 1575 1576 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1577 return MCDisassembler::Fail; 1578 1579 return S; 1580 } 1581 1582 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1583 uint64_t Address, const void *Decoder) { 1584 DecodeStatus S = MCDisassembler::Success; 1585 1586 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1587 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1588 unsigned type = fieldFromInstruction(Val, 5, 2); 1589 unsigned imm = fieldFromInstruction(Val, 7, 5); 1590 unsigned U = fieldFromInstruction(Val, 12, 1); 1591 1592 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1593 switch (type) { 1594 case 0: 1595 ShOp = ARM_AM::lsl; 1596 break; 1597 case 1: 1598 ShOp = ARM_AM::lsr; 1599 break; 1600 case 2: 1601 ShOp = ARM_AM::asr; 1602 break; 1603 case 3: 1604 ShOp = ARM_AM::ror; 1605 break; 1606 } 1607 1608 if (ShOp == ARM_AM::ror && imm == 0) 1609 ShOp = ARM_AM::rrx; 1610 1611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1612 return MCDisassembler::Fail; 1613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1614 return MCDisassembler::Fail; 1615 unsigned shift; 1616 if (U) 1617 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1618 else 1619 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1620 Inst.addOperand(MCOperand::createImm(shift)); 1621 1622 return S; 1623 } 1624 1625 static DecodeStatus 1626 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1627 uint64_t Address, const void *Decoder) { 1628 DecodeStatus S = MCDisassembler::Success; 1629 1630 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1631 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1632 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1633 unsigned type = fieldFromInstruction(Insn, 22, 1); 1634 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1635 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1636 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1637 unsigned W = fieldFromInstruction(Insn, 21, 1); 1638 unsigned P = fieldFromInstruction(Insn, 24, 1); 1639 unsigned Rt2 = Rt + 1; 1640 1641 bool writeback = (W == 1) | (P == 0); 1642 1643 // For {LD,ST}RD, Rt must be even, else undefined. 1644 switch (Inst.getOpcode()) { 1645 case ARM::STRD: 1646 case ARM::STRD_PRE: 1647 case ARM::STRD_POST: 1648 case ARM::LDRD: 1649 case ARM::LDRD_PRE: 1650 case ARM::LDRD_POST: 1651 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1652 break; 1653 default: 1654 break; 1655 } 1656 switch (Inst.getOpcode()) { 1657 case ARM::STRD: 1658 case ARM::STRD_PRE: 1659 case ARM::STRD_POST: 1660 if (P == 0 && W == 1) 1661 S = MCDisassembler::SoftFail; 1662 1663 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1664 S = MCDisassembler::SoftFail; 1665 if (type && Rm == 15) 1666 S = MCDisassembler::SoftFail; 1667 if (Rt2 == 15) 1668 S = MCDisassembler::SoftFail; 1669 if (!type && fieldFromInstruction(Insn, 8, 4)) 1670 S = MCDisassembler::SoftFail; 1671 break; 1672 case ARM::STRH: 1673 case ARM::STRH_PRE: 1674 case ARM::STRH_POST: 1675 if (Rt == 15) 1676 S = MCDisassembler::SoftFail; 1677 if (writeback && (Rn == 15 || Rn == Rt)) 1678 S = MCDisassembler::SoftFail; 1679 if (!type && Rm == 15) 1680 S = MCDisassembler::SoftFail; 1681 break; 1682 case ARM::LDRD: 1683 case ARM::LDRD_PRE: 1684 case ARM::LDRD_POST: 1685 if (type && Rn == 15) { 1686 if (Rt2 == 15) 1687 S = MCDisassembler::SoftFail; 1688 break; 1689 } 1690 if (P == 0 && W == 1) 1691 S = MCDisassembler::SoftFail; 1692 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1693 S = MCDisassembler::SoftFail; 1694 if (!type && writeback && Rn == 15) 1695 S = MCDisassembler::SoftFail; 1696 if (writeback && (Rn == Rt || Rn == Rt2)) 1697 S = MCDisassembler::SoftFail; 1698 break; 1699 case ARM::LDRH: 1700 case ARM::LDRH_PRE: 1701 case ARM::LDRH_POST: 1702 if (type && Rn == 15) { 1703 if (Rt == 15) 1704 S = MCDisassembler::SoftFail; 1705 break; 1706 } 1707 if (Rt == 15) 1708 S = MCDisassembler::SoftFail; 1709 if (!type && Rm == 15) 1710 S = MCDisassembler::SoftFail; 1711 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1712 S = MCDisassembler::SoftFail; 1713 break; 1714 case ARM::LDRSH: 1715 case ARM::LDRSH_PRE: 1716 case ARM::LDRSH_POST: 1717 case ARM::LDRSB: 1718 case ARM::LDRSB_PRE: 1719 case ARM::LDRSB_POST: 1720 if (type && Rn == 15) { 1721 if (Rt == 15) 1722 S = MCDisassembler::SoftFail; 1723 break; 1724 } 1725 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1726 S = MCDisassembler::SoftFail; 1727 if (!type && (Rt == 15 || Rm == 15)) 1728 S = MCDisassembler::SoftFail; 1729 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1730 S = MCDisassembler::SoftFail; 1731 break; 1732 default: 1733 break; 1734 } 1735 1736 if (writeback) { // Writeback 1737 if (P) 1738 U |= ARMII::IndexModePre << 9; 1739 else 1740 U |= ARMII::IndexModePost << 9; 1741 1742 // On stores, the writeback operand precedes Rt. 1743 switch (Inst.getOpcode()) { 1744 case ARM::STRD: 1745 case ARM::STRD_PRE: 1746 case ARM::STRD_POST: 1747 case ARM::STRH: 1748 case ARM::STRH_PRE: 1749 case ARM::STRH_POST: 1750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1751 return MCDisassembler::Fail; 1752 break; 1753 default: 1754 break; 1755 } 1756 } 1757 1758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1759 return MCDisassembler::Fail; 1760 switch (Inst.getOpcode()) { 1761 case ARM::STRD: 1762 case ARM::STRD_PRE: 1763 case ARM::STRD_POST: 1764 case ARM::LDRD: 1765 case ARM::LDRD_PRE: 1766 case ARM::LDRD_POST: 1767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1768 return MCDisassembler::Fail; 1769 break; 1770 default: 1771 break; 1772 } 1773 1774 if (writeback) { 1775 // On loads, the writeback operand comes after Rt. 1776 switch (Inst.getOpcode()) { 1777 case ARM::LDRD: 1778 case ARM::LDRD_PRE: 1779 case ARM::LDRD_POST: 1780 case ARM::LDRH: 1781 case ARM::LDRH_PRE: 1782 case ARM::LDRH_POST: 1783 case ARM::LDRSH: 1784 case ARM::LDRSH_PRE: 1785 case ARM::LDRSH_POST: 1786 case ARM::LDRSB: 1787 case ARM::LDRSB_PRE: 1788 case ARM::LDRSB_POST: 1789 case ARM::LDRHTr: 1790 case ARM::LDRSBTr: 1791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1792 return MCDisassembler::Fail; 1793 break; 1794 default: 1795 break; 1796 } 1797 } 1798 1799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1800 return MCDisassembler::Fail; 1801 1802 if (type) { 1803 Inst.addOperand(MCOperand::createReg(0)); 1804 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1805 } else { 1806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1807 return MCDisassembler::Fail; 1808 Inst.addOperand(MCOperand::createImm(U)); 1809 } 1810 1811 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1812 return MCDisassembler::Fail; 1813 1814 return S; 1815 } 1816 1817 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1818 uint64_t Address, const void *Decoder) { 1819 DecodeStatus S = MCDisassembler::Success; 1820 1821 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1822 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1823 1824 switch (mode) { 1825 case 0: 1826 mode = ARM_AM::da; 1827 break; 1828 case 1: 1829 mode = ARM_AM::ia; 1830 break; 1831 case 2: 1832 mode = ARM_AM::db; 1833 break; 1834 case 3: 1835 mode = ARM_AM::ib; 1836 break; 1837 } 1838 1839 Inst.addOperand(MCOperand::createImm(mode)); 1840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1841 return MCDisassembler::Fail; 1842 1843 return S; 1844 } 1845 1846 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1847 uint64_t Address, const void *Decoder) { 1848 DecodeStatus S = MCDisassembler::Success; 1849 1850 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1851 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1852 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1853 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1854 1855 if (pred == 0xF) 1856 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1857 1858 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1859 return MCDisassembler::Fail; 1860 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1861 return MCDisassembler::Fail; 1862 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1863 return MCDisassembler::Fail; 1864 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1865 return MCDisassembler::Fail; 1866 return S; 1867 } 1868 1869 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1870 unsigned Insn, 1871 uint64_t Address, const void *Decoder) { 1872 DecodeStatus S = MCDisassembler::Success; 1873 1874 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1875 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1876 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1877 1878 if (pred == 0xF) { 1879 // Ambiguous with RFE and SRS 1880 switch (Inst.getOpcode()) { 1881 case ARM::LDMDA: 1882 Inst.setOpcode(ARM::RFEDA); 1883 break; 1884 case ARM::LDMDA_UPD: 1885 Inst.setOpcode(ARM::RFEDA_UPD); 1886 break; 1887 case ARM::LDMDB: 1888 Inst.setOpcode(ARM::RFEDB); 1889 break; 1890 case ARM::LDMDB_UPD: 1891 Inst.setOpcode(ARM::RFEDB_UPD); 1892 break; 1893 case ARM::LDMIA: 1894 Inst.setOpcode(ARM::RFEIA); 1895 break; 1896 case ARM::LDMIA_UPD: 1897 Inst.setOpcode(ARM::RFEIA_UPD); 1898 break; 1899 case ARM::LDMIB: 1900 Inst.setOpcode(ARM::RFEIB); 1901 break; 1902 case ARM::LDMIB_UPD: 1903 Inst.setOpcode(ARM::RFEIB_UPD); 1904 break; 1905 case ARM::STMDA: 1906 Inst.setOpcode(ARM::SRSDA); 1907 break; 1908 case ARM::STMDA_UPD: 1909 Inst.setOpcode(ARM::SRSDA_UPD); 1910 break; 1911 case ARM::STMDB: 1912 Inst.setOpcode(ARM::SRSDB); 1913 break; 1914 case ARM::STMDB_UPD: 1915 Inst.setOpcode(ARM::SRSDB_UPD); 1916 break; 1917 case ARM::STMIA: 1918 Inst.setOpcode(ARM::SRSIA); 1919 break; 1920 case ARM::STMIA_UPD: 1921 Inst.setOpcode(ARM::SRSIA_UPD); 1922 break; 1923 case ARM::STMIB: 1924 Inst.setOpcode(ARM::SRSIB); 1925 break; 1926 case ARM::STMIB_UPD: 1927 Inst.setOpcode(ARM::SRSIB_UPD); 1928 break; 1929 default: 1930 return MCDisassembler::Fail; 1931 } 1932 1933 // For stores (which become SRS's, the only operand is the mode. 1934 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1935 // Check SRS encoding constraints 1936 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1937 fieldFromInstruction(Insn, 20, 1) == 0)) 1938 return MCDisassembler::Fail; 1939 1940 Inst.addOperand( 1941 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 1942 return S; 1943 } 1944 1945 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1946 } 1947 1948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1951 return MCDisassembler::Fail; // Tied 1952 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1953 return MCDisassembler::Fail; 1954 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1955 return MCDisassembler::Fail; 1956 1957 return S; 1958 } 1959 1960 // Check for UNPREDICTABLE predicated ESB instruction 1961 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 1962 uint64_t Address, const void *Decoder) { 1963 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1964 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 1965 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 1966 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 1967 1968 DecodeStatus S = MCDisassembler::Success; 1969 1970 Inst.addOperand(MCOperand::createImm(imm8)); 1971 1972 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1973 return MCDisassembler::Fail; 1974 1975 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 1976 // so all predicates should be allowed. 1977 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 1978 S = MCDisassembler::SoftFail; 1979 1980 return S; 1981 } 1982 1983 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1984 uint64_t Address, const void *Decoder) { 1985 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1986 unsigned M = fieldFromInstruction(Insn, 17, 1); 1987 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1988 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1989 1990 DecodeStatus S = MCDisassembler::Success; 1991 1992 // This decoder is called from multiple location that do not check 1993 // the full encoding is valid before they do. 1994 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1995 fieldFromInstruction(Insn, 16, 1) != 0 || 1996 fieldFromInstruction(Insn, 20, 8) != 0x10) 1997 return MCDisassembler::Fail; 1998 1999 // imod == '01' --> UNPREDICTABLE 2000 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2001 // return failure here. The '01' imod value is unprintable, so there's 2002 // nothing useful we could do even if we returned UNPREDICTABLE. 2003 2004 if (imod == 1) return MCDisassembler::Fail; 2005 2006 if (imod && M) { 2007 Inst.setOpcode(ARM::CPS3p); 2008 Inst.addOperand(MCOperand::createImm(imod)); 2009 Inst.addOperand(MCOperand::createImm(iflags)); 2010 Inst.addOperand(MCOperand::createImm(mode)); 2011 } else if (imod && !M) { 2012 Inst.setOpcode(ARM::CPS2p); 2013 Inst.addOperand(MCOperand::createImm(imod)); 2014 Inst.addOperand(MCOperand::createImm(iflags)); 2015 if (mode) S = MCDisassembler::SoftFail; 2016 } else if (!imod && M) { 2017 Inst.setOpcode(ARM::CPS1p); 2018 Inst.addOperand(MCOperand::createImm(mode)); 2019 if (iflags) S = MCDisassembler::SoftFail; 2020 } else { 2021 // imod == '00' && M == '0' --> UNPREDICTABLE 2022 Inst.setOpcode(ARM::CPS1p); 2023 Inst.addOperand(MCOperand::createImm(mode)); 2024 S = MCDisassembler::SoftFail; 2025 } 2026 2027 return S; 2028 } 2029 2030 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2031 uint64_t Address, const void *Decoder) { 2032 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2033 unsigned M = fieldFromInstruction(Insn, 8, 1); 2034 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2035 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2036 2037 DecodeStatus S = MCDisassembler::Success; 2038 2039 // imod == '01' --> UNPREDICTABLE 2040 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2041 // return failure here. The '01' imod value is unprintable, so there's 2042 // nothing useful we could do even if we returned UNPREDICTABLE. 2043 2044 if (imod == 1) return MCDisassembler::Fail; 2045 2046 if (imod && M) { 2047 Inst.setOpcode(ARM::t2CPS3p); 2048 Inst.addOperand(MCOperand::createImm(imod)); 2049 Inst.addOperand(MCOperand::createImm(iflags)); 2050 Inst.addOperand(MCOperand::createImm(mode)); 2051 } else if (imod && !M) { 2052 Inst.setOpcode(ARM::t2CPS2p); 2053 Inst.addOperand(MCOperand::createImm(imod)); 2054 Inst.addOperand(MCOperand::createImm(iflags)); 2055 if (mode) S = MCDisassembler::SoftFail; 2056 } else if (!imod && M) { 2057 Inst.setOpcode(ARM::t2CPS1p); 2058 Inst.addOperand(MCOperand::createImm(mode)); 2059 if (iflags) S = MCDisassembler::SoftFail; 2060 } else { 2061 // imod == '00' && M == '0' --> this is a HINT instruction 2062 int imm = fieldFromInstruction(Insn, 0, 8); 2063 // HINT are defined only for immediate in [0..4] 2064 if(imm > 4) return MCDisassembler::Fail; 2065 Inst.setOpcode(ARM::t2HINT); 2066 Inst.addOperand(MCOperand::createImm(imm)); 2067 } 2068 2069 return S; 2070 } 2071 2072 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2073 uint64_t Address, const void *Decoder) { 2074 DecodeStatus S = MCDisassembler::Success; 2075 2076 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2077 unsigned imm = 0; 2078 2079 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2080 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2081 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2082 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2083 2084 if (Inst.getOpcode() == ARM::t2MOVTi16) 2085 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2086 return MCDisassembler::Fail; 2087 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2088 return MCDisassembler::Fail; 2089 2090 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2091 Inst.addOperand(MCOperand::createImm(imm)); 2092 2093 return S; 2094 } 2095 2096 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2097 uint64_t Address, const void *Decoder) { 2098 DecodeStatus S = MCDisassembler::Success; 2099 2100 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2101 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2102 unsigned imm = 0; 2103 2104 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2105 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2106 2107 if (Inst.getOpcode() == ARM::MOVTi16) 2108 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2109 return MCDisassembler::Fail; 2110 2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 2114 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2115 Inst.addOperand(MCOperand::createImm(imm)); 2116 2117 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2118 return MCDisassembler::Fail; 2119 2120 return S; 2121 } 2122 2123 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2124 uint64_t Address, const void *Decoder) { 2125 DecodeStatus S = MCDisassembler::Success; 2126 2127 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2128 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2129 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2130 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2131 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2132 2133 if (pred == 0xF) 2134 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2135 2136 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2137 return MCDisassembler::Fail; 2138 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2139 return MCDisassembler::Fail; 2140 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2141 return MCDisassembler::Fail; 2142 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2143 return MCDisassembler::Fail; 2144 2145 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2146 return MCDisassembler::Fail; 2147 2148 return S; 2149 } 2150 2151 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2152 uint64_t Address, const void *Decoder) { 2153 DecodeStatus S = MCDisassembler::Success; 2154 2155 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2156 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2157 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2158 2159 if (Pred == 0xF) 2160 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2161 2162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2163 return MCDisassembler::Fail; 2164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2165 return MCDisassembler::Fail; 2166 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2167 return MCDisassembler::Fail; 2168 2169 return S; 2170 } 2171 2172 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2173 uint64_t Address, const void *Decoder) { 2174 DecodeStatus S = MCDisassembler::Success; 2175 2176 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2177 2178 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2179 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2180 2181 if (!FeatureBits[ARM::HasV8_1aOps] || 2182 !FeatureBits[ARM::HasV8Ops]) 2183 return MCDisassembler::Fail; 2184 2185 // Decoder can be called from DecodeTST, which does not check the full 2186 // encoding is valid. 2187 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2188 fieldFromInstruction(Insn, 4,4) != 0) 2189 return MCDisassembler::Fail; 2190 if (fieldFromInstruction(Insn, 10,10) != 0 || 2191 fieldFromInstruction(Insn, 0,4) != 0) 2192 S = MCDisassembler::SoftFail; 2193 2194 Inst.setOpcode(ARM::SETPAN); 2195 Inst.addOperand(MCOperand::createImm(Imm)); 2196 2197 return S; 2198 } 2199 2200 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2201 uint64_t Address, const void *Decoder) { 2202 DecodeStatus S = MCDisassembler::Success; 2203 2204 unsigned add = fieldFromInstruction(Val, 12, 1); 2205 unsigned imm = fieldFromInstruction(Val, 0, 12); 2206 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2207 2208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2209 return MCDisassembler::Fail; 2210 2211 if (!add) imm *= -1; 2212 if (imm == 0 && !add) imm = INT32_MIN; 2213 Inst.addOperand(MCOperand::createImm(imm)); 2214 if (Rn == 15) 2215 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2216 2217 return S; 2218 } 2219 2220 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2221 uint64_t Address, const void *Decoder) { 2222 DecodeStatus S = MCDisassembler::Success; 2223 2224 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2225 // U == 1 to add imm, 0 to subtract it. 2226 unsigned U = fieldFromInstruction(Val, 8, 1); 2227 unsigned imm = fieldFromInstruction(Val, 0, 8); 2228 2229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2230 return MCDisassembler::Fail; 2231 2232 if (U) 2233 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2234 else 2235 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2236 2237 return S; 2238 } 2239 2240 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2241 uint64_t Address, const void *Decoder) { 2242 DecodeStatus S = MCDisassembler::Success; 2243 2244 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2245 // U == 1 to add imm, 0 to subtract it. 2246 unsigned U = fieldFromInstruction(Val, 8, 1); 2247 unsigned imm = fieldFromInstruction(Val, 0, 8); 2248 2249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2250 return MCDisassembler::Fail; 2251 2252 if (U) 2253 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2254 else 2255 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2256 2257 return S; 2258 } 2259 2260 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2261 uint64_t Address, const void *Decoder) { 2262 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2263 } 2264 2265 static DecodeStatus 2266 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2267 uint64_t Address, const void *Decoder) { 2268 DecodeStatus Status = MCDisassembler::Success; 2269 2270 // Note the J1 and J2 values are from the encoded instruction. So here 2271 // change them to I1 and I2 values via as documented: 2272 // I1 = NOT(J1 EOR S); 2273 // I2 = NOT(J2 EOR S); 2274 // and build the imm32 with one trailing zero as documented: 2275 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2276 unsigned S = fieldFromInstruction(Insn, 26, 1); 2277 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2278 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2279 unsigned I1 = !(J1 ^ S); 2280 unsigned I2 = !(J2 ^ S); 2281 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2282 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2283 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2284 int imm32 = SignExtend32<25>(tmp << 1); 2285 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2286 true, 4, Inst, Decoder)) 2287 Inst.addOperand(MCOperand::createImm(imm32)); 2288 2289 return Status; 2290 } 2291 2292 static DecodeStatus 2293 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2294 uint64_t Address, const void *Decoder) { 2295 DecodeStatus S = MCDisassembler::Success; 2296 2297 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2298 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2299 2300 if (pred == 0xF) { 2301 Inst.setOpcode(ARM::BLXi); 2302 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2303 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2304 true, 4, Inst, Decoder)) 2305 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2306 return S; 2307 } 2308 2309 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2310 true, 4, Inst, Decoder)) 2311 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2312 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2313 return MCDisassembler::Fail; 2314 2315 return S; 2316 } 2317 2318 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2319 uint64_t Address, const void *Decoder) { 2320 DecodeStatus S = MCDisassembler::Success; 2321 2322 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2323 unsigned align = fieldFromInstruction(Val, 4, 2); 2324 2325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2326 return MCDisassembler::Fail; 2327 if (!align) 2328 Inst.addOperand(MCOperand::createImm(0)); 2329 else 2330 Inst.addOperand(MCOperand::createImm(4 << align)); 2331 2332 return S; 2333 } 2334 2335 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2336 uint64_t Address, const void *Decoder) { 2337 DecodeStatus S = MCDisassembler::Success; 2338 2339 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2340 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2341 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2342 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2343 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2344 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2345 2346 // First output register 2347 switch (Inst.getOpcode()) { 2348 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2349 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2350 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2351 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2352 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2353 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2354 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2355 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2356 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2357 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2358 return MCDisassembler::Fail; 2359 break; 2360 case ARM::VLD2b16: 2361 case ARM::VLD2b32: 2362 case ARM::VLD2b8: 2363 case ARM::VLD2b16wb_fixed: 2364 case ARM::VLD2b16wb_register: 2365 case ARM::VLD2b32wb_fixed: 2366 case ARM::VLD2b32wb_register: 2367 case ARM::VLD2b8wb_fixed: 2368 case ARM::VLD2b8wb_register: 2369 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2370 return MCDisassembler::Fail; 2371 break; 2372 default: 2373 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2374 return MCDisassembler::Fail; 2375 } 2376 2377 // Second output register 2378 switch (Inst.getOpcode()) { 2379 case ARM::VLD3d8: 2380 case ARM::VLD3d16: 2381 case ARM::VLD3d32: 2382 case ARM::VLD3d8_UPD: 2383 case ARM::VLD3d16_UPD: 2384 case ARM::VLD3d32_UPD: 2385 case ARM::VLD4d8: 2386 case ARM::VLD4d16: 2387 case ARM::VLD4d32: 2388 case ARM::VLD4d8_UPD: 2389 case ARM::VLD4d16_UPD: 2390 case ARM::VLD4d32_UPD: 2391 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2392 return MCDisassembler::Fail; 2393 break; 2394 case ARM::VLD3q8: 2395 case ARM::VLD3q16: 2396 case ARM::VLD3q32: 2397 case ARM::VLD3q8_UPD: 2398 case ARM::VLD3q16_UPD: 2399 case ARM::VLD3q32_UPD: 2400 case ARM::VLD4q8: 2401 case ARM::VLD4q16: 2402 case ARM::VLD4q32: 2403 case ARM::VLD4q8_UPD: 2404 case ARM::VLD4q16_UPD: 2405 case ARM::VLD4q32_UPD: 2406 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2407 return MCDisassembler::Fail; 2408 break; 2409 default: 2410 break; 2411 } 2412 2413 // Third output register 2414 switch(Inst.getOpcode()) { 2415 case ARM::VLD3d8: 2416 case ARM::VLD3d16: 2417 case ARM::VLD3d32: 2418 case ARM::VLD3d8_UPD: 2419 case ARM::VLD3d16_UPD: 2420 case ARM::VLD3d32_UPD: 2421 case ARM::VLD4d8: 2422 case ARM::VLD4d16: 2423 case ARM::VLD4d32: 2424 case ARM::VLD4d8_UPD: 2425 case ARM::VLD4d16_UPD: 2426 case ARM::VLD4d32_UPD: 2427 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2428 return MCDisassembler::Fail; 2429 break; 2430 case ARM::VLD3q8: 2431 case ARM::VLD3q16: 2432 case ARM::VLD3q32: 2433 case ARM::VLD3q8_UPD: 2434 case ARM::VLD3q16_UPD: 2435 case ARM::VLD3q32_UPD: 2436 case ARM::VLD4q8: 2437 case ARM::VLD4q16: 2438 case ARM::VLD4q32: 2439 case ARM::VLD4q8_UPD: 2440 case ARM::VLD4q16_UPD: 2441 case ARM::VLD4q32_UPD: 2442 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2443 return MCDisassembler::Fail; 2444 break; 2445 default: 2446 break; 2447 } 2448 2449 // Fourth output register 2450 switch (Inst.getOpcode()) { 2451 case ARM::VLD4d8: 2452 case ARM::VLD4d16: 2453 case ARM::VLD4d32: 2454 case ARM::VLD4d8_UPD: 2455 case ARM::VLD4d16_UPD: 2456 case ARM::VLD4d32_UPD: 2457 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2458 return MCDisassembler::Fail; 2459 break; 2460 case ARM::VLD4q8: 2461 case ARM::VLD4q16: 2462 case ARM::VLD4q32: 2463 case ARM::VLD4q8_UPD: 2464 case ARM::VLD4q16_UPD: 2465 case ARM::VLD4q32_UPD: 2466 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2467 return MCDisassembler::Fail; 2468 break; 2469 default: 2470 break; 2471 } 2472 2473 // Writeback operand 2474 switch (Inst.getOpcode()) { 2475 case ARM::VLD1d8wb_fixed: 2476 case ARM::VLD1d16wb_fixed: 2477 case ARM::VLD1d32wb_fixed: 2478 case ARM::VLD1d64wb_fixed: 2479 case ARM::VLD1d8wb_register: 2480 case ARM::VLD1d16wb_register: 2481 case ARM::VLD1d32wb_register: 2482 case ARM::VLD1d64wb_register: 2483 case ARM::VLD1q8wb_fixed: 2484 case ARM::VLD1q16wb_fixed: 2485 case ARM::VLD1q32wb_fixed: 2486 case ARM::VLD1q64wb_fixed: 2487 case ARM::VLD1q8wb_register: 2488 case ARM::VLD1q16wb_register: 2489 case ARM::VLD1q32wb_register: 2490 case ARM::VLD1q64wb_register: 2491 case ARM::VLD1d8Twb_fixed: 2492 case ARM::VLD1d8Twb_register: 2493 case ARM::VLD1d16Twb_fixed: 2494 case ARM::VLD1d16Twb_register: 2495 case ARM::VLD1d32Twb_fixed: 2496 case ARM::VLD1d32Twb_register: 2497 case ARM::VLD1d64Twb_fixed: 2498 case ARM::VLD1d64Twb_register: 2499 case ARM::VLD1d8Qwb_fixed: 2500 case ARM::VLD1d8Qwb_register: 2501 case ARM::VLD1d16Qwb_fixed: 2502 case ARM::VLD1d16Qwb_register: 2503 case ARM::VLD1d32Qwb_fixed: 2504 case ARM::VLD1d32Qwb_register: 2505 case ARM::VLD1d64Qwb_fixed: 2506 case ARM::VLD1d64Qwb_register: 2507 case ARM::VLD2d8wb_fixed: 2508 case ARM::VLD2d16wb_fixed: 2509 case ARM::VLD2d32wb_fixed: 2510 case ARM::VLD2q8wb_fixed: 2511 case ARM::VLD2q16wb_fixed: 2512 case ARM::VLD2q32wb_fixed: 2513 case ARM::VLD2d8wb_register: 2514 case ARM::VLD2d16wb_register: 2515 case ARM::VLD2d32wb_register: 2516 case ARM::VLD2q8wb_register: 2517 case ARM::VLD2q16wb_register: 2518 case ARM::VLD2q32wb_register: 2519 case ARM::VLD2b8wb_fixed: 2520 case ARM::VLD2b16wb_fixed: 2521 case ARM::VLD2b32wb_fixed: 2522 case ARM::VLD2b8wb_register: 2523 case ARM::VLD2b16wb_register: 2524 case ARM::VLD2b32wb_register: 2525 Inst.addOperand(MCOperand::createImm(0)); 2526 break; 2527 case ARM::VLD3d8_UPD: 2528 case ARM::VLD3d16_UPD: 2529 case ARM::VLD3d32_UPD: 2530 case ARM::VLD3q8_UPD: 2531 case ARM::VLD3q16_UPD: 2532 case ARM::VLD3q32_UPD: 2533 case ARM::VLD4d8_UPD: 2534 case ARM::VLD4d16_UPD: 2535 case ARM::VLD4d32_UPD: 2536 case ARM::VLD4q8_UPD: 2537 case ARM::VLD4q16_UPD: 2538 case ARM::VLD4q32_UPD: 2539 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2540 return MCDisassembler::Fail; 2541 break; 2542 default: 2543 break; 2544 } 2545 2546 // AddrMode6 Base (register+alignment) 2547 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2548 return MCDisassembler::Fail; 2549 2550 // AddrMode6 Offset (register) 2551 switch (Inst.getOpcode()) { 2552 default: 2553 // The below have been updated to have explicit am6offset split 2554 // between fixed and register offset. For those instructions not 2555 // yet updated, we need to add an additional reg0 operand for the 2556 // fixed variant. 2557 // 2558 // The fixed offset encodes as Rm == 0xd, so we check for that. 2559 if (Rm == 0xd) { 2560 Inst.addOperand(MCOperand::createReg(0)); 2561 break; 2562 } 2563 // Fall through to handle the register offset variant. 2564 LLVM_FALLTHROUGH; 2565 case ARM::VLD1d8wb_fixed: 2566 case ARM::VLD1d16wb_fixed: 2567 case ARM::VLD1d32wb_fixed: 2568 case ARM::VLD1d64wb_fixed: 2569 case ARM::VLD1d8Twb_fixed: 2570 case ARM::VLD1d16Twb_fixed: 2571 case ARM::VLD1d32Twb_fixed: 2572 case ARM::VLD1d64Twb_fixed: 2573 case ARM::VLD1d8Qwb_fixed: 2574 case ARM::VLD1d16Qwb_fixed: 2575 case ARM::VLD1d32Qwb_fixed: 2576 case ARM::VLD1d64Qwb_fixed: 2577 case ARM::VLD1d8wb_register: 2578 case ARM::VLD1d16wb_register: 2579 case ARM::VLD1d32wb_register: 2580 case ARM::VLD1d64wb_register: 2581 case ARM::VLD1q8wb_fixed: 2582 case ARM::VLD1q16wb_fixed: 2583 case ARM::VLD1q32wb_fixed: 2584 case ARM::VLD1q64wb_fixed: 2585 case ARM::VLD1q8wb_register: 2586 case ARM::VLD1q16wb_register: 2587 case ARM::VLD1q32wb_register: 2588 case ARM::VLD1q64wb_register: 2589 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2590 // variant encodes Rm == 0xf. Anything else is a register offset post- 2591 // increment and we need to add the register operand to the instruction. 2592 if (Rm != 0xD && Rm != 0xF && 2593 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2594 return MCDisassembler::Fail; 2595 break; 2596 case ARM::VLD2d8wb_fixed: 2597 case ARM::VLD2d16wb_fixed: 2598 case ARM::VLD2d32wb_fixed: 2599 case ARM::VLD2b8wb_fixed: 2600 case ARM::VLD2b16wb_fixed: 2601 case ARM::VLD2b32wb_fixed: 2602 case ARM::VLD2q8wb_fixed: 2603 case ARM::VLD2q16wb_fixed: 2604 case ARM::VLD2q32wb_fixed: 2605 break; 2606 } 2607 2608 return S; 2609 } 2610 2611 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2612 uint64_t Address, const void *Decoder) { 2613 unsigned type = fieldFromInstruction(Insn, 8, 4); 2614 unsigned align = fieldFromInstruction(Insn, 4, 2); 2615 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2616 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2617 if (type == 10 && align == 3) return MCDisassembler::Fail; 2618 2619 unsigned load = fieldFromInstruction(Insn, 21, 1); 2620 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2621 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2622 } 2623 2624 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2625 uint64_t Address, const void *Decoder) { 2626 unsigned size = fieldFromInstruction(Insn, 6, 2); 2627 if (size == 3) return MCDisassembler::Fail; 2628 2629 unsigned type = fieldFromInstruction(Insn, 8, 4); 2630 unsigned align = fieldFromInstruction(Insn, 4, 2); 2631 if (type == 8 && align == 3) return MCDisassembler::Fail; 2632 if (type == 9 && align == 3) return MCDisassembler::Fail; 2633 2634 unsigned load = fieldFromInstruction(Insn, 21, 1); 2635 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2636 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2637 } 2638 2639 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2640 uint64_t Address, const void *Decoder) { 2641 unsigned size = fieldFromInstruction(Insn, 6, 2); 2642 if (size == 3) return MCDisassembler::Fail; 2643 2644 unsigned align = fieldFromInstruction(Insn, 4, 2); 2645 if (align & 2) return MCDisassembler::Fail; 2646 2647 unsigned load = fieldFromInstruction(Insn, 21, 1); 2648 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2649 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2650 } 2651 2652 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2653 uint64_t Address, const void *Decoder) { 2654 unsigned size = fieldFromInstruction(Insn, 6, 2); 2655 if (size == 3) return MCDisassembler::Fail; 2656 2657 unsigned load = fieldFromInstruction(Insn, 21, 1); 2658 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2659 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2660 } 2661 2662 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2663 uint64_t Address, const void *Decoder) { 2664 DecodeStatus S = MCDisassembler::Success; 2665 2666 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2667 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2668 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2669 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2670 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2671 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2672 2673 // Writeback Operand 2674 switch (Inst.getOpcode()) { 2675 case ARM::VST1d8wb_fixed: 2676 case ARM::VST1d16wb_fixed: 2677 case ARM::VST1d32wb_fixed: 2678 case ARM::VST1d64wb_fixed: 2679 case ARM::VST1d8wb_register: 2680 case ARM::VST1d16wb_register: 2681 case ARM::VST1d32wb_register: 2682 case ARM::VST1d64wb_register: 2683 case ARM::VST1q8wb_fixed: 2684 case ARM::VST1q16wb_fixed: 2685 case ARM::VST1q32wb_fixed: 2686 case ARM::VST1q64wb_fixed: 2687 case ARM::VST1q8wb_register: 2688 case ARM::VST1q16wb_register: 2689 case ARM::VST1q32wb_register: 2690 case ARM::VST1q64wb_register: 2691 case ARM::VST1d8Twb_fixed: 2692 case ARM::VST1d16Twb_fixed: 2693 case ARM::VST1d32Twb_fixed: 2694 case ARM::VST1d64Twb_fixed: 2695 case ARM::VST1d8Twb_register: 2696 case ARM::VST1d16Twb_register: 2697 case ARM::VST1d32Twb_register: 2698 case ARM::VST1d64Twb_register: 2699 case ARM::VST1d8Qwb_fixed: 2700 case ARM::VST1d16Qwb_fixed: 2701 case ARM::VST1d32Qwb_fixed: 2702 case ARM::VST1d64Qwb_fixed: 2703 case ARM::VST1d8Qwb_register: 2704 case ARM::VST1d16Qwb_register: 2705 case ARM::VST1d32Qwb_register: 2706 case ARM::VST1d64Qwb_register: 2707 case ARM::VST2d8wb_fixed: 2708 case ARM::VST2d16wb_fixed: 2709 case ARM::VST2d32wb_fixed: 2710 case ARM::VST2d8wb_register: 2711 case ARM::VST2d16wb_register: 2712 case ARM::VST2d32wb_register: 2713 case ARM::VST2q8wb_fixed: 2714 case ARM::VST2q16wb_fixed: 2715 case ARM::VST2q32wb_fixed: 2716 case ARM::VST2q8wb_register: 2717 case ARM::VST2q16wb_register: 2718 case ARM::VST2q32wb_register: 2719 case ARM::VST2b8wb_fixed: 2720 case ARM::VST2b16wb_fixed: 2721 case ARM::VST2b32wb_fixed: 2722 case ARM::VST2b8wb_register: 2723 case ARM::VST2b16wb_register: 2724 case ARM::VST2b32wb_register: 2725 if (Rm == 0xF) 2726 return MCDisassembler::Fail; 2727 Inst.addOperand(MCOperand::createImm(0)); 2728 break; 2729 case ARM::VST3d8_UPD: 2730 case ARM::VST3d16_UPD: 2731 case ARM::VST3d32_UPD: 2732 case ARM::VST3q8_UPD: 2733 case ARM::VST3q16_UPD: 2734 case ARM::VST3q32_UPD: 2735 case ARM::VST4d8_UPD: 2736 case ARM::VST4d16_UPD: 2737 case ARM::VST4d32_UPD: 2738 case ARM::VST4q8_UPD: 2739 case ARM::VST4q16_UPD: 2740 case ARM::VST4q32_UPD: 2741 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2742 return MCDisassembler::Fail; 2743 break; 2744 default: 2745 break; 2746 } 2747 2748 // AddrMode6 Base (register+alignment) 2749 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2750 return MCDisassembler::Fail; 2751 2752 // AddrMode6 Offset (register) 2753 switch (Inst.getOpcode()) { 2754 default: 2755 if (Rm == 0xD) 2756 Inst.addOperand(MCOperand::createReg(0)); 2757 else if (Rm != 0xF) { 2758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2759 return MCDisassembler::Fail; 2760 } 2761 break; 2762 case ARM::VST1d8wb_fixed: 2763 case ARM::VST1d16wb_fixed: 2764 case ARM::VST1d32wb_fixed: 2765 case ARM::VST1d64wb_fixed: 2766 case ARM::VST1q8wb_fixed: 2767 case ARM::VST1q16wb_fixed: 2768 case ARM::VST1q32wb_fixed: 2769 case ARM::VST1q64wb_fixed: 2770 case ARM::VST1d8Twb_fixed: 2771 case ARM::VST1d16Twb_fixed: 2772 case ARM::VST1d32Twb_fixed: 2773 case ARM::VST1d64Twb_fixed: 2774 case ARM::VST1d8Qwb_fixed: 2775 case ARM::VST1d16Qwb_fixed: 2776 case ARM::VST1d32Qwb_fixed: 2777 case ARM::VST1d64Qwb_fixed: 2778 case ARM::VST2d8wb_fixed: 2779 case ARM::VST2d16wb_fixed: 2780 case ARM::VST2d32wb_fixed: 2781 case ARM::VST2q8wb_fixed: 2782 case ARM::VST2q16wb_fixed: 2783 case ARM::VST2q32wb_fixed: 2784 case ARM::VST2b8wb_fixed: 2785 case ARM::VST2b16wb_fixed: 2786 case ARM::VST2b32wb_fixed: 2787 break; 2788 } 2789 2790 // First input register 2791 switch (Inst.getOpcode()) { 2792 case ARM::VST1q16: 2793 case ARM::VST1q32: 2794 case ARM::VST1q64: 2795 case ARM::VST1q8: 2796 case ARM::VST1q16wb_fixed: 2797 case ARM::VST1q16wb_register: 2798 case ARM::VST1q32wb_fixed: 2799 case ARM::VST1q32wb_register: 2800 case ARM::VST1q64wb_fixed: 2801 case ARM::VST1q64wb_register: 2802 case ARM::VST1q8wb_fixed: 2803 case ARM::VST1q8wb_register: 2804 case ARM::VST2d16: 2805 case ARM::VST2d32: 2806 case ARM::VST2d8: 2807 case ARM::VST2d16wb_fixed: 2808 case ARM::VST2d16wb_register: 2809 case ARM::VST2d32wb_fixed: 2810 case ARM::VST2d32wb_register: 2811 case ARM::VST2d8wb_fixed: 2812 case ARM::VST2d8wb_register: 2813 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2814 return MCDisassembler::Fail; 2815 break; 2816 case ARM::VST2b16: 2817 case ARM::VST2b32: 2818 case ARM::VST2b8: 2819 case ARM::VST2b16wb_fixed: 2820 case ARM::VST2b16wb_register: 2821 case ARM::VST2b32wb_fixed: 2822 case ARM::VST2b32wb_register: 2823 case ARM::VST2b8wb_fixed: 2824 case ARM::VST2b8wb_register: 2825 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2826 return MCDisassembler::Fail; 2827 break; 2828 default: 2829 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2830 return MCDisassembler::Fail; 2831 } 2832 2833 // Second input register 2834 switch (Inst.getOpcode()) { 2835 case ARM::VST3d8: 2836 case ARM::VST3d16: 2837 case ARM::VST3d32: 2838 case ARM::VST3d8_UPD: 2839 case ARM::VST3d16_UPD: 2840 case ARM::VST3d32_UPD: 2841 case ARM::VST4d8: 2842 case ARM::VST4d16: 2843 case ARM::VST4d32: 2844 case ARM::VST4d8_UPD: 2845 case ARM::VST4d16_UPD: 2846 case ARM::VST4d32_UPD: 2847 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2848 return MCDisassembler::Fail; 2849 break; 2850 case ARM::VST3q8: 2851 case ARM::VST3q16: 2852 case ARM::VST3q32: 2853 case ARM::VST3q8_UPD: 2854 case ARM::VST3q16_UPD: 2855 case ARM::VST3q32_UPD: 2856 case ARM::VST4q8: 2857 case ARM::VST4q16: 2858 case ARM::VST4q32: 2859 case ARM::VST4q8_UPD: 2860 case ARM::VST4q16_UPD: 2861 case ARM::VST4q32_UPD: 2862 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2863 return MCDisassembler::Fail; 2864 break; 2865 default: 2866 break; 2867 } 2868 2869 // Third input register 2870 switch (Inst.getOpcode()) { 2871 case ARM::VST3d8: 2872 case ARM::VST3d16: 2873 case ARM::VST3d32: 2874 case ARM::VST3d8_UPD: 2875 case ARM::VST3d16_UPD: 2876 case ARM::VST3d32_UPD: 2877 case ARM::VST4d8: 2878 case ARM::VST4d16: 2879 case ARM::VST4d32: 2880 case ARM::VST4d8_UPD: 2881 case ARM::VST4d16_UPD: 2882 case ARM::VST4d32_UPD: 2883 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2884 return MCDisassembler::Fail; 2885 break; 2886 case ARM::VST3q8: 2887 case ARM::VST3q16: 2888 case ARM::VST3q32: 2889 case ARM::VST3q8_UPD: 2890 case ARM::VST3q16_UPD: 2891 case ARM::VST3q32_UPD: 2892 case ARM::VST4q8: 2893 case ARM::VST4q16: 2894 case ARM::VST4q32: 2895 case ARM::VST4q8_UPD: 2896 case ARM::VST4q16_UPD: 2897 case ARM::VST4q32_UPD: 2898 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2899 return MCDisassembler::Fail; 2900 break; 2901 default: 2902 break; 2903 } 2904 2905 // Fourth input register 2906 switch (Inst.getOpcode()) { 2907 case ARM::VST4d8: 2908 case ARM::VST4d16: 2909 case ARM::VST4d32: 2910 case ARM::VST4d8_UPD: 2911 case ARM::VST4d16_UPD: 2912 case ARM::VST4d32_UPD: 2913 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2914 return MCDisassembler::Fail; 2915 break; 2916 case ARM::VST4q8: 2917 case ARM::VST4q16: 2918 case ARM::VST4q32: 2919 case ARM::VST4q8_UPD: 2920 case ARM::VST4q16_UPD: 2921 case ARM::VST4q32_UPD: 2922 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2923 return MCDisassembler::Fail; 2924 break; 2925 default: 2926 break; 2927 } 2928 2929 return S; 2930 } 2931 2932 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2933 uint64_t Address, const void *Decoder) { 2934 DecodeStatus S = MCDisassembler::Success; 2935 2936 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2937 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2938 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2939 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2940 unsigned align = fieldFromInstruction(Insn, 4, 1); 2941 unsigned size = fieldFromInstruction(Insn, 6, 2); 2942 2943 if (size == 0 && align == 1) 2944 return MCDisassembler::Fail; 2945 align *= (1 << size); 2946 2947 switch (Inst.getOpcode()) { 2948 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2949 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2950 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2951 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2952 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2953 return MCDisassembler::Fail; 2954 break; 2955 default: 2956 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 break; 2959 } 2960 if (Rm != 0xF) { 2961 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2962 return MCDisassembler::Fail; 2963 } 2964 2965 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2966 return MCDisassembler::Fail; 2967 Inst.addOperand(MCOperand::createImm(align)); 2968 2969 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2970 // variant encodes Rm == 0xf. Anything else is a register offset post- 2971 // increment and we need to add the register operand to the instruction. 2972 if (Rm != 0xD && Rm != 0xF && 2973 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2974 return MCDisassembler::Fail; 2975 2976 return S; 2977 } 2978 2979 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2980 uint64_t Address, const void *Decoder) { 2981 DecodeStatus S = MCDisassembler::Success; 2982 2983 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2984 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2985 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2986 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2987 unsigned align = fieldFromInstruction(Insn, 4, 1); 2988 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2989 align *= 2*size; 2990 2991 switch (Inst.getOpcode()) { 2992 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2993 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2994 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2995 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2996 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2997 return MCDisassembler::Fail; 2998 break; 2999 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3000 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3001 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3002 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3003 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3004 return MCDisassembler::Fail; 3005 break; 3006 default: 3007 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3008 return MCDisassembler::Fail; 3009 break; 3010 } 3011 3012 if (Rm != 0xF) 3013 Inst.addOperand(MCOperand::createImm(0)); 3014 3015 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3016 return MCDisassembler::Fail; 3017 Inst.addOperand(MCOperand::createImm(align)); 3018 3019 if (Rm != 0xD && Rm != 0xF) { 3020 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3021 return MCDisassembler::Fail; 3022 } 3023 3024 return S; 3025 } 3026 3027 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3028 uint64_t Address, const void *Decoder) { 3029 DecodeStatus S = MCDisassembler::Success; 3030 3031 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3032 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3033 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3034 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3035 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3036 3037 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3038 return MCDisassembler::Fail; 3039 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3040 return MCDisassembler::Fail; 3041 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3042 return MCDisassembler::Fail; 3043 if (Rm != 0xF) { 3044 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3045 return MCDisassembler::Fail; 3046 } 3047 3048 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3049 return MCDisassembler::Fail; 3050 Inst.addOperand(MCOperand::createImm(0)); 3051 3052 if (Rm == 0xD) 3053 Inst.addOperand(MCOperand::createReg(0)); 3054 else if (Rm != 0xF) { 3055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3056 return MCDisassembler::Fail; 3057 } 3058 3059 return S; 3060 } 3061 3062 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3063 uint64_t Address, const void *Decoder) { 3064 DecodeStatus S = MCDisassembler::Success; 3065 3066 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3067 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3068 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3069 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3070 unsigned size = fieldFromInstruction(Insn, 6, 2); 3071 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3072 unsigned align = fieldFromInstruction(Insn, 4, 1); 3073 3074 if (size == 0x3) { 3075 if (align == 0) 3076 return MCDisassembler::Fail; 3077 align = 16; 3078 } else { 3079 if (size == 2) { 3080 align *= 8; 3081 } else { 3082 size = 1 << size; 3083 align *= 4*size; 3084 } 3085 } 3086 3087 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3090 return MCDisassembler::Fail; 3091 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3092 return MCDisassembler::Fail; 3093 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3094 return MCDisassembler::Fail; 3095 if (Rm != 0xF) { 3096 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3097 return MCDisassembler::Fail; 3098 } 3099 3100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3101 return MCDisassembler::Fail; 3102 Inst.addOperand(MCOperand::createImm(align)); 3103 3104 if (Rm == 0xD) 3105 Inst.addOperand(MCOperand::createReg(0)); 3106 else if (Rm != 0xF) { 3107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3108 return MCDisassembler::Fail; 3109 } 3110 3111 return S; 3112 } 3113 3114 static DecodeStatus 3115 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3116 uint64_t Address, const void *Decoder) { 3117 DecodeStatus S = MCDisassembler::Success; 3118 3119 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3120 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3121 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3122 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3123 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3124 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3125 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3126 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3127 3128 if (Q) { 3129 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3130 return MCDisassembler::Fail; 3131 } else { 3132 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3133 return MCDisassembler::Fail; 3134 } 3135 3136 Inst.addOperand(MCOperand::createImm(imm)); 3137 3138 switch (Inst.getOpcode()) { 3139 case ARM::VORRiv4i16: 3140 case ARM::VORRiv2i32: 3141 case ARM::VBICiv4i16: 3142 case ARM::VBICiv2i32: 3143 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3144 return MCDisassembler::Fail; 3145 break; 3146 case ARM::VORRiv8i16: 3147 case ARM::VORRiv4i32: 3148 case ARM::VBICiv8i16: 3149 case ARM::VBICiv4i32: 3150 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3151 return MCDisassembler::Fail; 3152 break; 3153 default: 3154 break; 3155 } 3156 3157 return S; 3158 } 3159 3160 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3161 uint64_t Address, const void *Decoder) { 3162 DecodeStatus S = MCDisassembler::Success; 3163 3164 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3165 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3166 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3167 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3168 unsigned size = fieldFromInstruction(Insn, 18, 2); 3169 3170 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3171 return MCDisassembler::Fail; 3172 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3173 return MCDisassembler::Fail; 3174 Inst.addOperand(MCOperand::createImm(8 << size)); 3175 3176 return S; 3177 } 3178 3179 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3180 uint64_t Address, const void *Decoder) { 3181 Inst.addOperand(MCOperand::createImm(8 - Val)); 3182 return MCDisassembler::Success; 3183 } 3184 3185 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3186 uint64_t Address, const void *Decoder) { 3187 Inst.addOperand(MCOperand::createImm(16 - Val)); 3188 return MCDisassembler::Success; 3189 } 3190 3191 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3192 uint64_t Address, const void *Decoder) { 3193 Inst.addOperand(MCOperand::createImm(32 - Val)); 3194 return MCDisassembler::Success; 3195 } 3196 3197 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3198 uint64_t Address, const void *Decoder) { 3199 Inst.addOperand(MCOperand::createImm(64 - Val)); 3200 return MCDisassembler::Success; 3201 } 3202 3203 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3204 uint64_t Address, const void *Decoder) { 3205 DecodeStatus S = MCDisassembler::Success; 3206 3207 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3208 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3209 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3210 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3211 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3212 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3213 unsigned op = fieldFromInstruction(Insn, 6, 1); 3214 3215 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3216 return MCDisassembler::Fail; 3217 if (op) { 3218 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3219 return MCDisassembler::Fail; // Writeback 3220 } 3221 3222 switch (Inst.getOpcode()) { 3223 case ARM::VTBL2: 3224 case ARM::VTBX2: 3225 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3226 return MCDisassembler::Fail; 3227 break; 3228 default: 3229 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 } 3232 3233 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3234 return MCDisassembler::Fail; 3235 3236 return S; 3237 } 3238 3239 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3240 uint64_t Address, const void *Decoder) { 3241 DecodeStatus S = MCDisassembler::Success; 3242 3243 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3244 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3245 3246 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3247 return MCDisassembler::Fail; 3248 3249 switch(Inst.getOpcode()) { 3250 default: 3251 return MCDisassembler::Fail; 3252 case ARM::tADR: 3253 break; // tADR does not explicitly represent the PC as an operand. 3254 case ARM::tADDrSPi: 3255 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3256 break; 3257 } 3258 3259 Inst.addOperand(MCOperand::createImm(imm)); 3260 return S; 3261 } 3262 3263 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3264 uint64_t Address, const void *Decoder) { 3265 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3266 true, 2, Inst, Decoder)) 3267 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3268 return MCDisassembler::Success; 3269 } 3270 3271 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3272 uint64_t Address, const void *Decoder) { 3273 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3274 true, 4, Inst, Decoder)) 3275 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3276 return MCDisassembler::Success; 3277 } 3278 3279 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3280 uint64_t Address, const void *Decoder) { 3281 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3282 true, 2, Inst, Decoder)) 3283 Inst.addOperand(MCOperand::createImm(Val << 1)); 3284 return MCDisassembler::Success; 3285 } 3286 3287 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3288 uint64_t Address, const void *Decoder) { 3289 DecodeStatus S = MCDisassembler::Success; 3290 3291 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3292 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3293 3294 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3295 return MCDisassembler::Fail; 3296 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3297 return MCDisassembler::Fail; 3298 3299 return S; 3300 } 3301 3302 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3303 uint64_t Address, const void *Decoder) { 3304 DecodeStatus S = MCDisassembler::Success; 3305 3306 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3307 unsigned imm = fieldFromInstruction(Val, 3, 5); 3308 3309 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3310 return MCDisassembler::Fail; 3311 Inst.addOperand(MCOperand::createImm(imm)); 3312 3313 return S; 3314 } 3315 3316 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3317 uint64_t Address, const void *Decoder) { 3318 unsigned imm = Val << 2; 3319 3320 Inst.addOperand(MCOperand::createImm(imm)); 3321 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3322 3323 return MCDisassembler::Success; 3324 } 3325 3326 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3327 uint64_t Address, const void *Decoder) { 3328 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3329 Inst.addOperand(MCOperand::createImm(Val)); 3330 3331 return MCDisassembler::Success; 3332 } 3333 3334 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3335 uint64_t Address, const void *Decoder) { 3336 DecodeStatus S = MCDisassembler::Success; 3337 3338 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3339 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3340 unsigned imm = fieldFromInstruction(Val, 0, 2); 3341 3342 // Thumb stores cannot use PC as dest register. 3343 switch (Inst.getOpcode()) { 3344 case ARM::t2STRHs: 3345 case ARM::t2STRBs: 3346 case ARM::t2STRs: 3347 if (Rn == 15) 3348 return MCDisassembler::Fail; 3349 break; 3350 default: 3351 break; 3352 } 3353 3354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3357 return MCDisassembler::Fail; 3358 Inst.addOperand(MCOperand::createImm(imm)); 3359 3360 return S; 3361 } 3362 3363 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3364 uint64_t Address, const void *Decoder) { 3365 DecodeStatus S = MCDisassembler::Success; 3366 3367 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3368 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3369 3370 const FeatureBitset &featureBits = 3371 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3372 3373 bool hasMP = featureBits[ARM::FeatureMP]; 3374 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3375 3376 if (Rn == 15) { 3377 switch (Inst.getOpcode()) { 3378 case ARM::t2LDRBs: 3379 Inst.setOpcode(ARM::t2LDRBpci); 3380 break; 3381 case ARM::t2LDRHs: 3382 Inst.setOpcode(ARM::t2LDRHpci); 3383 break; 3384 case ARM::t2LDRSHs: 3385 Inst.setOpcode(ARM::t2LDRSHpci); 3386 break; 3387 case ARM::t2LDRSBs: 3388 Inst.setOpcode(ARM::t2LDRSBpci); 3389 break; 3390 case ARM::t2LDRs: 3391 Inst.setOpcode(ARM::t2LDRpci); 3392 break; 3393 case ARM::t2PLDs: 3394 Inst.setOpcode(ARM::t2PLDpci); 3395 break; 3396 case ARM::t2PLIs: 3397 Inst.setOpcode(ARM::t2PLIpci); 3398 break; 3399 default: 3400 return MCDisassembler::Fail; 3401 } 3402 3403 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3404 } 3405 3406 if (Rt == 15) { 3407 switch (Inst.getOpcode()) { 3408 case ARM::t2LDRSHs: 3409 return MCDisassembler::Fail; 3410 case ARM::t2LDRHs: 3411 Inst.setOpcode(ARM::t2PLDWs); 3412 break; 3413 case ARM::t2LDRSBs: 3414 Inst.setOpcode(ARM::t2PLIs); 3415 break; 3416 default: 3417 break; 3418 } 3419 } 3420 3421 switch (Inst.getOpcode()) { 3422 case ARM::t2PLDs: 3423 break; 3424 case ARM::t2PLIs: 3425 if (!hasV7Ops) 3426 return MCDisassembler::Fail; 3427 break; 3428 case ARM::t2PLDWs: 3429 if (!hasV7Ops || !hasMP) 3430 return MCDisassembler::Fail; 3431 break; 3432 default: 3433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 } 3436 3437 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3438 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3439 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3440 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3441 return MCDisassembler::Fail; 3442 3443 return S; 3444 } 3445 3446 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3447 uint64_t Address, const void* Decoder) { 3448 DecodeStatus S = MCDisassembler::Success; 3449 3450 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3451 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3452 unsigned U = fieldFromInstruction(Insn, 9, 1); 3453 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3454 imm |= (U << 8); 3455 imm |= (Rn << 9); 3456 unsigned add = fieldFromInstruction(Insn, 9, 1); 3457 3458 const FeatureBitset &featureBits = 3459 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3460 3461 bool hasMP = featureBits[ARM::FeatureMP]; 3462 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3463 3464 if (Rn == 15) { 3465 switch (Inst.getOpcode()) { 3466 case ARM::t2LDRi8: 3467 Inst.setOpcode(ARM::t2LDRpci); 3468 break; 3469 case ARM::t2LDRBi8: 3470 Inst.setOpcode(ARM::t2LDRBpci); 3471 break; 3472 case ARM::t2LDRSBi8: 3473 Inst.setOpcode(ARM::t2LDRSBpci); 3474 break; 3475 case ARM::t2LDRHi8: 3476 Inst.setOpcode(ARM::t2LDRHpci); 3477 break; 3478 case ARM::t2LDRSHi8: 3479 Inst.setOpcode(ARM::t2LDRSHpci); 3480 break; 3481 case ARM::t2PLDi8: 3482 Inst.setOpcode(ARM::t2PLDpci); 3483 break; 3484 case ARM::t2PLIi8: 3485 Inst.setOpcode(ARM::t2PLIpci); 3486 break; 3487 default: 3488 return MCDisassembler::Fail; 3489 } 3490 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3491 } 3492 3493 if (Rt == 15) { 3494 switch (Inst.getOpcode()) { 3495 case ARM::t2LDRSHi8: 3496 return MCDisassembler::Fail; 3497 case ARM::t2LDRHi8: 3498 if (!add) 3499 Inst.setOpcode(ARM::t2PLDWi8); 3500 break; 3501 case ARM::t2LDRSBi8: 3502 Inst.setOpcode(ARM::t2PLIi8); 3503 break; 3504 default: 3505 break; 3506 } 3507 } 3508 3509 switch (Inst.getOpcode()) { 3510 case ARM::t2PLDi8: 3511 break; 3512 case ARM::t2PLIi8: 3513 if (!hasV7Ops) 3514 return MCDisassembler::Fail; 3515 break; 3516 case ARM::t2PLDWi8: 3517 if (!hasV7Ops || !hasMP) 3518 return MCDisassembler::Fail; 3519 break; 3520 default: 3521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3522 return MCDisassembler::Fail; 3523 } 3524 3525 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3526 return MCDisassembler::Fail; 3527 return S; 3528 } 3529 3530 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3531 uint64_t Address, const void* Decoder) { 3532 DecodeStatus S = MCDisassembler::Success; 3533 3534 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3535 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3536 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3537 imm |= (Rn << 13); 3538 3539 const FeatureBitset &featureBits = 3540 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3541 3542 bool hasMP = featureBits[ARM::FeatureMP]; 3543 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3544 3545 if (Rn == 15) { 3546 switch (Inst.getOpcode()) { 3547 case ARM::t2LDRi12: 3548 Inst.setOpcode(ARM::t2LDRpci); 3549 break; 3550 case ARM::t2LDRHi12: 3551 Inst.setOpcode(ARM::t2LDRHpci); 3552 break; 3553 case ARM::t2LDRSHi12: 3554 Inst.setOpcode(ARM::t2LDRSHpci); 3555 break; 3556 case ARM::t2LDRBi12: 3557 Inst.setOpcode(ARM::t2LDRBpci); 3558 break; 3559 case ARM::t2LDRSBi12: 3560 Inst.setOpcode(ARM::t2LDRSBpci); 3561 break; 3562 case ARM::t2PLDi12: 3563 Inst.setOpcode(ARM::t2PLDpci); 3564 break; 3565 case ARM::t2PLIi12: 3566 Inst.setOpcode(ARM::t2PLIpci); 3567 break; 3568 default: 3569 return MCDisassembler::Fail; 3570 } 3571 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3572 } 3573 3574 if (Rt == 15) { 3575 switch (Inst.getOpcode()) { 3576 case ARM::t2LDRSHi12: 3577 return MCDisassembler::Fail; 3578 case ARM::t2LDRHi12: 3579 Inst.setOpcode(ARM::t2PLDWi12); 3580 break; 3581 case ARM::t2LDRSBi12: 3582 Inst.setOpcode(ARM::t2PLIi12); 3583 break; 3584 default: 3585 break; 3586 } 3587 } 3588 3589 switch (Inst.getOpcode()) { 3590 case ARM::t2PLDi12: 3591 break; 3592 case ARM::t2PLIi12: 3593 if (!hasV7Ops) 3594 return MCDisassembler::Fail; 3595 break; 3596 case ARM::t2PLDWi12: 3597 if (!hasV7Ops || !hasMP) 3598 return MCDisassembler::Fail; 3599 break; 3600 default: 3601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3602 return MCDisassembler::Fail; 3603 } 3604 3605 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3606 return MCDisassembler::Fail; 3607 return S; 3608 } 3609 3610 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3611 uint64_t Address, const void* Decoder) { 3612 DecodeStatus S = MCDisassembler::Success; 3613 3614 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3615 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3616 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3617 imm |= (Rn << 9); 3618 3619 if (Rn == 15) { 3620 switch (Inst.getOpcode()) { 3621 case ARM::t2LDRT: 3622 Inst.setOpcode(ARM::t2LDRpci); 3623 break; 3624 case ARM::t2LDRBT: 3625 Inst.setOpcode(ARM::t2LDRBpci); 3626 break; 3627 case ARM::t2LDRHT: 3628 Inst.setOpcode(ARM::t2LDRHpci); 3629 break; 3630 case ARM::t2LDRSBT: 3631 Inst.setOpcode(ARM::t2LDRSBpci); 3632 break; 3633 case ARM::t2LDRSHT: 3634 Inst.setOpcode(ARM::t2LDRSHpci); 3635 break; 3636 default: 3637 return MCDisassembler::Fail; 3638 } 3639 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3640 } 3641 3642 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3645 return MCDisassembler::Fail; 3646 return S; 3647 } 3648 3649 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3650 uint64_t Address, const void* Decoder) { 3651 DecodeStatus S = MCDisassembler::Success; 3652 3653 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3654 unsigned U = fieldFromInstruction(Insn, 23, 1); 3655 int imm = fieldFromInstruction(Insn, 0, 12); 3656 3657 const FeatureBitset &featureBits = 3658 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3659 3660 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3661 3662 if (Rt == 15) { 3663 switch (Inst.getOpcode()) { 3664 case ARM::t2LDRBpci: 3665 case ARM::t2LDRHpci: 3666 Inst.setOpcode(ARM::t2PLDpci); 3667 break; 3668 case ARM::t2LDRSBpci: 3669 Inst.setOpcode(ARM::t2PLIpci); 3670 break; 3671 case ARM::t2LDRSHpci: 3672 return MCDisassembler::Fail; 3673 default: 3674 break; 3675 } 3676 } 3677 3678 switch(Inst.getOpcode()) { 3679 case ARM::t2PLDpci: 3680 break; 3681 case ARM::t2PLIpci: 3682 if (!hasV7Ops) 3683 return MCDisassembler::Fail; 3684 break; 3685 default: 3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 } 3689 3690 if (!U) { 3691 // Special case for #-0. 3692 if (imm == 0) 3693 imm = INT32_MIN; 3694 else 3695 imm = -imm; 3696 } 3697 Inst.addOperand(MCOperand::createImm(imm)); 3698 3699 return S; 3700 } 3701 3702 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3703 uint64_t Address, const void *Decoder) { 3704 if (Val == 0) 3705 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3706 else { 3707 int imm = Val & 0xFF; 3708 3709 if (!(Val & 0x100)) imm *= -1; 3710 Inst.addOperand(MCOperand::createImm(imm * 4)); 3711 } 3712 3713 return MCDisassembler::Success; 3714 } 3715 3716 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3717 uint64_t Address, const void *Decoder) { 3718 DecodeStatus S = MCDisassembler::Success; 3719 3720 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3721 unsigned imm = fieldFromInstruction(Val, 0, 9); 3722 3723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3724 return MCDisassembler::Fail; 3725 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3726 return MCDisassembler::Fail; 3727 3728 return S; 3729 } 3730 3731 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3732 uint64_t Address, const void *Decoder) { 3733 DecodeStatus S = MCDisassembler::Success; 3734 3735 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3736 unsigned imm = fieldFromInstruction(Val, 0, 8); 3737 3738 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3739 return MCDisassembler::Fail; 3740 3741 Inst.addOperand(MCOperand::createImm(imm)); 3742 3743 return S; 3744 } 3745 3746 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3747 uint64_t Address, const void *Decoder) { 3748 int imm = Val & 0xFF; 3749 if (Val == 0) 3750 imm = INT32_MIN; 3751 else if (!(Val & 0x100)) 3752 imm *= -1; 3753 Inst.addOperand(MCOperand::createImm(imm)); 3754 3755 return MCDisassembler::Success; 3756 } 3757 3758 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3759 uint64_t Address, const void *Decoder) { 3760 DecodeStatus S = MCDisassembler::Success; 3761 3762 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3763 unsigned imm = fieldFromInstruction(Val, 0, 9); 3764 3765 // Thumb stores cannot use PC as dest register. 3766 switch (Inst.getOpcode()) { 3767 case ARM::t2STRT: 3768 case ARM::t2STRBT: 3769 case ARM::t2STRHT: 3770 case ARM::t2STRi8: 3771 case ARM::t2STRHi8: 3772 case ARM::t2STRBi8: 3773 if (Rn == 15) 3774 return MCDisassembler::Fail; 3775 break; 3776 default: 3777 break; 3778 } 3779 3780 // Some instructions always use an additive offset. 3781 switch (Inst.getOpcode()) { 3782 case ARM::t2LDRT: 3783 case ARM::t2LDRBT: 3784 case ARM::t2LDRHT: 3785 case ARM::t2LDRSBT: 3786 case ARM::t2LDRSHT: 3787 case ARM::t2STRT: 3788 case ARM::t2STRBT: 3789 case ARM::t2STRHT: 3790 imm |= 0x100; 3791 break; 3792 default: 3793 break; 3794 } 3795 3796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3797 return MCDisassembler::Fail; 3798 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3799 return MCDisassembler::Fail; 3800 3801 return S; 3802 } 3803 3804 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3805 uint64_t Address, const void *Decoder) { 3806 DecodeStatus S = MCDisassembler::Success; 3807 3808 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3809 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3810 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3811 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3812 addr |= Rn << 9; 3813 unsigned load = fieldFromInstruction(Insn, 20, 1); 3814 3815 if (Rn == 15) { 3816 switch (Inst.getOpcode()) { 3817 case ARM::t2LDR_PRE: 3818 case ARM::t2LDR_POST: 3819 Inst.setOpcode(ARM::t2LDRpci); 3820 break; 3821 case ARM::t2LDRB_PRE: 3822 case ARM::t2LDRB_POST: 3823 Inst.setOpcode(ARM::t2LDRBpci); 3824 break; 3825 case ARM::t2LDRH_PRE: 3826 case ARM::t2LDRH_POST: 3827 Inst.setOpcode(ARM::t2LDRHpci); 3828 break; 3829 case ARM::t2LDRSB_PRE: 3830 case ARM::t2LDRSB_POST: 3831 if (Rt == 15) 3832 Inst.setOpcode(ARM::t2PLIpci); 3833 else 3834 Inst.setOpcode(ARM::t2LDRSBpci); 3835 break; 3836 case ARM::t2LDRSH_PRE: 3837 case ARM::t2LDRSH_POST: 3838 Inst.setOpcode(ARM::t2LDRSHpci); 3839 break; 3840 default: 3841 return MCDisassembler::Fail; 3842 } 3843 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3844 } 3845 3846 if (!load) { 3847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3848 return MCDisassembler::Fail; 3849 } 3850 3851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3852 return MCDisassembler::Fail; 3853 3854 if (load) { 3855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3856 return MCDisassembler::Fail; 3857 } 3858 3859 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3860 return MCDisassembler::Fail; 3861 3862 return S; 3863 } 3864 3865 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3866 uint64_t Address, const void *Decoder) { 3867 DecodeStatus S = MCDisassembler::Success; 3868 3869 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3870 unsigned imm = fieldFromInstruction(Val, 0, 12); 3871 3872 // Thumb stores cannot use PC as dest register. 3873 switch (Inst.getOpcode()) { 3874 case ARM::t2STRi12: 3875 case ARM::t2STRBi12: 3876 case ARM::t2STRHi12: 3877 if (Rn == 15) 3878 return MCDisassembler::Fail; 3879 break; 3880 default: 3881 break; 3882 } 3883 3884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3885 return MCDisassembler::Fail; 3886 Inst.addOperand(MCOperand::createImm(imm)); 3887 3888 return S; 3889 } 3890 3891 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3892 uint64_t Address, const void *Decoder) { 3893 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3894 3895 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3896 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3897 Inst.addOperand(MCOperand::createImm(imm)); 3898 3899 return MCDisassembler::Success; 3900 } 3901 3902 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3903 uint64_t Address, const void *Decoder) { 3904 DecodeStatus S = MCDisassembler::Success; 3905 3906 if (Inst.getOpcode() == ARM::tADDrSP) { 3907 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3908 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3909 3910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3911 return MCDisassembler::Fail; 3912 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3914 return MCDisassembler::Fail; 3915 } else if (Inst.getOpcode() == ARM::tADDspr) { 3916 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3917 3918 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3919 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3921 return MCDisassembler::Fail; 3922 } 3923 3924 return S; 3925 } 3926 3927 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3928 uint64_t Address, const void *Decoder) { 3929 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3930 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3931 3932 Inst.addOperand(MCOperand::createImm(imod)); 3933 Inst.addOperand(MCOperand::createImm(flags)); 3934 3935 return MCDisassembler::Success; 3936 } 3937 3938 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3939 uint64_t Address, const void *Decoder) { 3940 DecodeStatus S = MCDisassembler::Success; 3941 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3942 unsigned add = fieldFromInstruction(Insn, 4, 1); 3943 3944 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3945 return MCDisassembler::Fail; 3946 Inst.addOperand(MCOperand::createImm(add)); 3947 3948 return S; 3949 } 3950 3951 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3952 uint64_t Address, const void *Decoder) { 3953 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3954 // Note only one trailing zero not two. Also the J1 and J2 values are from 3955 // the encoded instruction. So here change to I1 and I2 values via: 3956 // I1 = NOT(J1 EOR S); 3957 // I2 = NOT(J2 EOR S); 3958 // and build the imm32 with two trailing zeros as documented: 3959 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3960 unsigned S = (Val >> 23) & 1; 3961 unsigned J1 = (Val >> 22) & 1; 3962 unsigned J2 = (Val >> 21) & 1; 3963 unsigned I1 = !(J1 ^ S); 3964 unsigned I2 = !(J2 ^ S); 3965 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3966 int imm32 = SignExtend32<25>(tmp << 1); 3967 3968 if (!tryAddingSymbolicOperand(Address, 3969 (Address & ~2u) + imm32 + 4, 3970 true, 4, Inst, Decoder)) 3971 Inst.addOperand(MCOperand::createImm(imm32)); 3972 return MCDisassembler::Success; 3973 } 3974 3975 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3976 uint64_t Address, const void *Decoder) { 3977 if (Val == 0xA || Val == 0xB) 3978 return MCDisassembler::Fail; 3979 3980 const FeatureBitset &featureBits = 3981 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3982 3983 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 3984 return MCDisassembler::Fail; 3985 3986 Inst.addOperand(MCOperand::createImm(Val)); 3987 return MCDisassembler::Success; 3988 } 3989 3990 static DecodeStatus 3991 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3992 uint64_t Address, const void *Decoder) { 3993 DecodeStatus S = MCDisassembler::Success; 3994 3995 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3996 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3997 3998 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4000 return MCDisassembler::Fail; 4001 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4002 return MCDisassembler::Fail; 4003 return S; 4004 } 4005 4006 static DecodeStatus 4007 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4008 uint64_t Address, const void *Decoder) { 4009 DecodeStatus S = MCDisassembler::Success; 4010 4011 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4012 if (pred == 0xE || pred == 0xF) { 4013 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4014 switch (opc) { 4015 default: 4016 return MCDisassembler::Fail; 4017 case 0xf3bf8f4: 4018 Inst.setOpcode(ARM::t2DSB); 4019 break; 4020 case 0xf3bf8f5: 4021 Inst.setOpcode(ARM::t2DMB); 4022 break; 4023 case 0xf3bf8f6: 4024 Inst.setOpcode(ARM::t2ISB); 4025 break; 4026 } 4027 4028 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4029 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4030 } 4031 4032 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4033 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4034 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4035 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4036 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4037 4038 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4039 return MCDisassembler::Fail; 4040 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4041 return MCDisassembler::Fail; 4042 4043 return S; 4044 } 4045 4046 // Decode a shifted immediate operand. These basically consist 4047 // of an 8-bit value, and a 4-bit directive that specifies either 4048 // a splat operation or a rotation. 4049 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4050 uint64_t Address, const void *Decoder) { 4051 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4052 if (ctrl == 0) { 4053 unsigned byte = fieldFromInstruction(Val, 8, 2); 4054 unsigned imm = fieldFromInstruction(Val, 0, 8); 4055 switch (byte) { 4056 case 0: 4057 Inst.addOperand(MCOperand::createImm(imm)); 4058 break; 4059 case 1: 4060 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4061 break; 4062 case 2: 4063 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4064 break; 4065 case 3: 4066 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4067 (imm << 8) | imm)); 4068 break; 4069 } 4070 } else { 4071 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4072 unsigned rot = fieldFromInstruction(Val, 7, 5); 4073 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4074 Inst.addOperand(MCOperand::createImm(imm)); 4075 } 4076 4077 return MCDisassembler::Success; 4078 } 4079 4080 static DecodeStatus 4081 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4082 uint64_t Address, const void *Decoder) { 4083 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4084 true, 2, Inst, Decoder)) 4085 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4086 return MCDisassembler::Success; 4087 } 4088 4089 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4090 uint64_t Address, 4091 const void *Decoder) { 4092 // Val is passed in as S:J1:J2:imm10:imm11 4093 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4094 // the encoded instruction. So here change to I1 and I2 values via: 4095 // I1 = NOT(J1 EOR S); 4096 // I2 = NOT(J2 EOR S); 4097 // and build the imm32 with one trailing zero as documented: 4098 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4099 unsigned S = (Val >> 23) & 1; 4100 unsigned J1 = (Val >> 22) & 1; 4101 unsigned J2 = (Val >> 21) & 1; 4102 unsigned I1 = !(J1 ^ S); 4103 unsigned I2 = !(J2 ^ S); 4104 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4105 int imm32 = SignExtend32<25>(tmp << 1); 4106 4107 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4108 true, 4, Inst, Decoder)) 4109 Inst.addOperand(MCOperand::createImm(imm32)); 4110 return MCDisassembler::Success; 4111 } 4112 4113 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4114 uint64_t Address, const void *Decoder) { 4115 if (Val & ~0xf) 4116 return MCDisassembler::Fail; 4117 4118 Inst.addOperand(MCOperand::createImm(Val)); 4119 return MCDisassembler::Success; 4120 } 4121 4122 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4123 uint64_t Address, const void *Decoder) { 4124 if (Val & ~0xf) 4125 return MCDisassembler::Fail; 4126 4127 Inst.addOperand(MCOperand::createImm(Val)); 4128 return MCDisassembler::Success; 4129 } 4130 4131 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4132 uint64_t Address, const void *Decoder) { 4133 DecodeStatus S = MCDisassembler::Success; 4134 const FeatureBitset &FeatureBits = 4135 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4136 4137 if (FeatureBits[ARM::FeatureMClass]) { 4138 unsigned ValLow = Val & 0xff; 4139 4140 // Validate the SYSm value first. 4141 switch (ValLow) { 4142 case 0: // apsr 4143 case 1: // iapsr 4144 case 2: // eapsr 4145 case 3: // xpsr 4146 case 5: // ipsr 4147 case 6: // epsr 4148 case 7: // iepsr 4149 case 8: // msp 4150 case 9: // psp 4151 case 16: // primask 4152 case 20: // control 4153 break; 4154 case 17: // basepri 4155 case 18: // basepri_max 4156 case 19: // faultmask 4157 if (!(FeatureBits[ARM::HasV7Ops])) 4158 // Values basepri, basepri_max and faultmask are only valid for v7m. 4159 return MCDisassembler::Fail; 4160 break; 4161 case 0x8a: // msplim_ns 4162 case 0x8b: // psplim_ns 4163 case 0x91: // basepri_ns 4164 case 0x93: // faultmask_ns 4165 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4166 return MCDisassembler::Fail; 4167 LLVM_FALLTHROUGH; 4168 case 10: // msplim 4169 case 11: // psplim 4170 case 0x88: // msp_ns 4171 case 0x89: // psp_ns 4172 case 0x90: // primask_ns 4173 case 0x94: // control_ns 4174 case 0x98: // sp_ns 4175 if (!(FeatureBits[ARM::Feature8MSecExt])) 4176 return MCDisassembler::Fail; 4177 break; 4178 default: 4179 // Architecturally defined as unpredictable 4180 S = MCDisassembler::SoftFail; 4181 break; 4182 } 4183 4184 if (Inst.getOpcode() == ARM::t2MSR_M) { 4185 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4186 if (!(FeatureBits[ARM::HasV7Ops])) { 4187 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4188 // unpredictable. 4189 if (Mask != 2) 4190 S = MCDisassembler::SoftFail; 4191 } 4192 else { 4193 // The ARMv7-M architecture stores an additional 2-bit mask value in 4194 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4195 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4196 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4197 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4198 // only if the processor includes the DSP extension. 4199 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4200 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4201 S = MCDisassembler::SoftFail; 4202 } 4203 } 4204 } else { 4205 // A/R class 4206 if (Val == 0) 4207 return MCDisassembler::Fail; 4208 } 4209 Inst.addOperand(MCOperand::createImm(Val)); 4210 return S; 4211 } 4212 4213 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4214 uint64_t Address, const void *Decoder) { 4215 unsigned R = fieldFromInstruction(Val, 5, 1); 4216 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4217 4218 // The table of encodings for these banked registers comes from B9.2.3 of the 4219 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4220 // neater. So by fiat, these values are UNPREDICTABLE: 4221 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4222 return MCDisassembler::Fail; 4223 4224 Inst.addOperand(MCOperand::createImm(Val)); 4225 return MCDisassembler::Success; 4226 } 4227 4228 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4229 uint64_t Address, const void *Decoder) { 4230 DecodeStatus S = MCDisassembler::Success; 4231 4232 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4233 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4234 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4235 4236 if (Rn == 0xF) 4237 S = MCDisassembler::SoftFail; 4238 4239 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4240 return MCDisassembler::Fail; 4241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4244 return MCDisassembler::Fail; 4245 4246 return S; 4247 } 4248 4249 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4250 uint64_t Address, 4251 const void *Decoder) { 4252 DecodeStatus S = MCDisassembler::Success; 4253 4254 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4255 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4256 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4257 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4258 4259 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4260 return MCDisassembler::Fail; 4261 4262 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4263 S = MCDisassembler::SoftFail; 4264 4265 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4266 return MCDisassembler::Fail; 4267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4270 return MCDisassembler::Fail; 4271 4272 return S; 4273 } 4274 4275 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4276 uint64_t Address, const void *Decoder) { 4277 DecodeStatus S = MCDisassembler::Success; 4278 4279 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4280 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4281 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4282 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4283 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4284 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4285 4286 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4287 4288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4289 return MCDisassembler::Fail; 4290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4291 return MCDisassembler::Fail; 4292 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4293 return MCDisassembler::Fail; 4294 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4295 return MCDisassembler::Fail; 4296 4297 return S; 4298 } 4299 4300 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4301 uint64_t Address, const void *Decoder) { 4302 DecodeStatus S = MCDisassembler::Success; 4303 4304 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4305 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4306 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4307 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4308 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4309 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4310 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4311 4312 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4313 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4314 4315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4316 return MCDisassembler::Fail; 4317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4318 return MCDisassembler::Fail; 4319 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4320 return MCDisassembler::Fail; 4321 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4322 return MCDisassembler::Fail; 4323 4324 return S; 4325 } 4326 4327 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4328 uint64_t Address, const void *Decoder) { 4329 DecodeStatus S = MCDisassembler::Success; 4330 4331 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4332 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4333 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4334 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4335 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4336 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4337 4338 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4339 4340 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4341 return MCDisassembler::Fail; 4342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4345 return MCDisassembler::Fail; 4346 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4347 return MCDisassembler::Fail; 4348 4349 return S; 4350 } 4351 4352 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4353 uint64_t Address, const void *Decoder) { 4354 DecodeStatus S = MCDisassembler::Success; 4355 4356 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4357 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4358 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4359 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4360 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4361 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4362 4363 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4364 4365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4368 return MCDisassembler::Fail; 4369 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4370 return MCDisassembler::Fail; 4371 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4372 return MCDisassembler::Fail; 4373 4374 return S; 4375 } 4376 4377 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4378 uint64_t Address, const void *Decoder) { 4379 DecodeStatus S = MCDisassembler::Success; 4380 4381 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4382 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4383 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4384 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4385 unsigned size = fieldFromInstruction(Insn, 10, 2); 4386 4387 unsigned align = 0; 4388 unsigned index = 0; 4389 switch (size) { 4390 default: 4391 return MCDisassembler::Fail; 4392 case 0: 4393 if (fieldFromInstruction(Insn, 4, 1)) 4394 return MCDisassembler::Fail; // UNDEFINED 4395 index = fieldFromInstruction(Insn, 5, 3); 4396 break; 4397 case 1: 4398 if (fieldFromInstruction(Insn, 5, 1)) 4399 return MCDisassembler::Fail; // UNDEFINED 4400 index = fieldFromInstruction(Insn, 6, 2); 4401 if (fieldFromInstruction(Insn, 4, 1)) 4402 align = 2; 4403 break; 4404 case 2: 4405 if (fieldFromInstruction(Insn, 6, 1)) 4406 return MCDisassembler::Fail; // UNDEFINED 4407 index = fieldFromInstruction(Insn, 7, 1); 4408 4409 switch (fieldFromInstruction(Insn, 4, 2)) { 4410 case 0 : 4411 align = 0; break; 4412 case 3: 4413 align = 4; break; 4414 default: 4415 return MCDisassembler::Fail; 4416 } 4417 break; 4418 } 4419 4420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4421 return MCDisassembler::Fail; 4422 if (Rm != 0xF) { // Writeback 4423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4424 return MCDisassembler::Fail; 4425 } 4426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4427 return MCDisassembler::Fail; 4428 Inst.addOperand(MCOperand::createImm(align)); 4429 if (Rm != 0xF) { 4430 if (Rm != 0xD) { 4431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4432 return MCDisassembler::Fail; 4433 } else 4434 Inst.addOperand(MCOperand::createReg(0)); 4435 } 4436 4437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4438 return MCDisassembler::Fail; 4439 Inst.addOperand(MCOperand::createImm(index)); 4440 4441 return S; 4442 } 4443 4444 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4445 uint64_t Address, const void *Decoder) { 4446 DecodeStatus S = MCDisassembler::Success; 4447 4448 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4449 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4450 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4451 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4452 unsigned size = fieldFromInstruction(Insn, 10, 2); 4453 4454 unsigned align = 0; 4455 unsigned index = 0; 4456 switch (size) { 4457 default: 4458 return MCDisassembler::Fail; 4459 case 0: 4460 if (fieldFromInstruction(Insn, 4, 1)) 4461 return MCDisassembler::Fail; // UNDEFINED 4462 index = fieldFromInstruction(Insn, 5, 3); 4463 break; 4464 case 1: 4465 if (fieldFromInstruction(Insn, 5, 1)) 4466 return MCDisassembler::Fail; // UNDEFINED 4467 index = fieldFromInstruction(Insn, 6, 2); 4468 if (fieldFromInstruction(Insn, 4, 1)) 4469 align = 2; 4470 break; 4471 case 2: 4472 if (fieldFromInstruction(Insn, 6, 1)) 4473 return MCDisassembler::Fail; // UNDEFINED 4474 index = fieldFromInstruction(Insn, 7, 1); 4475 4476 switch (fieldFromInstruction(Insn, 4, 2)) { 4477 case 0: 4478 align = 0; break; 4479 case 3: 4480 align = 4; break; 4481 default: 4482 return MCDisassembler::Fail; 4483 } 4484 break; 4485 } 4486 4487 if (Rm != 0xF) { // Writeback 4488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4489 return MCDisassembler::Fail; 4490 } 4491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4492 return MCDisassembler::Fail; 4493 Inst.addOperand(MCOperand::createImm(align)); 4494 if (Rm != 0xF) { 4495 if (Rm != 0xD) { 4496 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4497 return MCDisassembler::Fail; 4498 } else 4499 Inst.addOperand(MCOperand::createReg(0)); 4500 } 4501 4502 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4503 return MCDisassembler::Fail; 4504 Inst.addOperand(MCOperand::createImm(index)); 4505 4506 return S; 4507 } 4508 4509 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4510 uint64_t Address, const void *Decoder) { 4511 DecodeStatus S = MCDisassembler::Success; 4512 4513 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4514 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4515 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4516 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4517 unsigned size = fieldFromInstruction(Insn, 10, 2); 4518 4519 unsigned align = 0; 4520 unsigned index = 0; 4521 unsigned inc = 1; 4522 switch (size) { 4523 default: 4524 return MCDisassembler::Fail; 4525 case 0: 4526 index = fieldFromInstruction(Insn, 5, 3); 4527 if (fieldFromInstruction(Insn, 4, 1)) 4528 align = 2; 4529 break; 4530 case 1: 4531 index = fieldFromInstruction(Insn, 6, 2); 4532 if (fieldFromInstruction(Insn, 4, 1)) 4533 align = 4; 4534 if (fieldFromInstruction(Insn, 5, 1)) 4535 inc = 2; 4536 break; 4537 case 2: 4538 if (fieldFromInstruction(Insn, 5, 1)) 4539 return MCDisassembler::Fail; // UNDEFINED 4540 index = fieldFromInstruction(Insn, 7, 1); 4541 if (fieldFromInstruction(Insn, 4, 1) != 0) 4542 align = 8; 4543 if (fieldFromInstruction(Insn, 6, 1)) 4544 inc = 2; 4545 break; 4546 } 4547 4548 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4549 return MCDisassembler::Fail; 4550 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4551 return MCDisassembler::Fail; 4552 if (Rm != 0xF) { // Writeback 4553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4554 return MCDisassembler::Fail; 4555 } 4556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4557 return MCDisassembler::Fail; 4558 Inst.addOperand(MCOperand::createImm(align)); 4559 if (Rm != 0xF) { 4560 if (Rm != 0xD) { 4561 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4562 return MCDisassembler::Fail; 4563 } else 4564 Inst.addOperand(MCOperand::createReg(0)); 4565 } 4566 4567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4568 return MCDisassembler::Fail; 4569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4570 return MCDisassembler::Fail; 4571 Inst.addOperand(MCOperand::createImm(index)); 4572 4573 return S; 4574 } 4575 4576 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4577 uint64_t Address, const void *Decoder) { 4578 DecodeStatus S = MCDisassembler::Success; 4579 4580 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4581 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4582 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4583 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4584 unsigned size = fieldFromInstruction(Insn, 10, 2); 4585 4586 unsigned align = 0; 4587 unsigned index = 0; 4588 unsigned inc = 1; 4589 switch (size) { 4590 default: 4591 return MCDisassembler::Fail; 4592 case 0: 4593 index = fieldFromInstruction(Insn, 5, 3); 4594 if (fieldFromInstruction(Insn, 4, 1)) 4595 align = 2; 4596 break; 4597 case 1: 4598 index = fieldFromInstruction(Insn, 6, 2); 4599 if (fieldFromInstruction(Insn, 4, 1)) 4600 align = 4; 4601 if (fieldFromInstruction(Insn, 5, 1)) 4602 inc = 2; 4603 break; 4604 case 2: 4605 if (fieldFromInstruction(Insn, 5, 1)) 4606 return MCDisassembler::Fail; // UNDEFINED 4607 index = fieldFromInstruction(Insn, 7, 1); 4608 if (fieldFromInstruction(Insn, 4, 1) != 0) 4609 align = 8; 4610 if (fieldFromInstruction(Insn, 6, 1)) 4611 inc = 2; 4612 break; 4613 } 4614 4615 if (Rm != 0xF) { // Writeback 4616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4617 return MCDisassembler::Fail; 4618 } 4619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4620 return MCDisassembler::Fail; 4621 Inst.addOperand(MCOperand::createImm(align)); 4622 if (Rm != 0xF) { 4623 if (Rm != 0xD) { 4624 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4625 return MCDisassembler::Fail; 4626 } else 4627 Inst.addOperand(MCOperand::createReg(0)); 4628 } 4629 4630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4631 return MCDisassembler::Fail; 4632 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4633 return MCDisassembler::Fail; 4634 Inst.addOperand(MCOperand::createImm(index)); 4635 4636 return S; 4637 } 4638 4639 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4640 uint64_t Address, const void *Decoder) { 4641 DecodeStatus S = MCDisassembler::Success; 4642 4643 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4644 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4645 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4646 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4647 unsigned size = fieldFromInstruction(Insn, 10, 2); 4648 4649 unsigned align = 0; 4650 unsigned index = 0; 4651 unsigned inc = 1; 4652 switch (size) { 4653 default: 4654 return MCDisassembler::Fail; 4655 case 0: 4656 if (fieldFromInstruction(Insn, 4, 1)) 4657 return MCDisassembler::Fail; // UNDEFINED 4658 index = fieldFromInstruction(Insn, 5, 3); 4659 break; 4660 case 1: 4661 if (fieldFromInstruction(Insn, 4, 1)) 4662 return MCDisassembler::Fail; // UNDEFINED 4663 index = fieldFromInstruction(Insn, 6, 2); 4664 if (fieldFromInstruction(Insn, 5, 1)) 4665 inc = 2; 4666 break; 4667 case 2: 4668 if (fieldFromInstruction(Insn, 4, 2)) 4669 return MCDisassembler::Fail; // UNDEFINED 4670 index = fieldFromInstruction(Insn, 7, 1); 4671 if (fieldFromInstruction(Insn, 6, 1)) 4672 inc = 2; 4673 break; 4674 } 4675 4676 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4677 return MCDisassembler::Fail; 4678 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4681 return MCDisassembler::Fail; 4682 4683 if (Rm != 0xF) { // Writeback 4684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4685 return MCDisassembler::Fail; 4686 } 4687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4688 return MCDisassembler::Fail; 4689 Inst.addOperand(MCOperand::createImm(align)); 4690 if (Rm != 0xF) { 4691 if (Rm != 0xD) { 4692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4693 return MCDisassembler::Fail; 4694 } else 4695 Inst.addOperand(MCOperand::createReg(0)); 4696 } 4697 4698 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4699 return MCDisassembler::Fail; 4700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4701 return MCDisassembler::Fail; 4702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4703 return MCDisassembler::Fail; 4704 Inst.addOperand(MCOperand::createImm(index)); 4705 4706 return S; 4707 } 4708 4709 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4710 uint64_t Address, const void *Decoder) { 4711 DecodeStatus S = MCDisassembler::Success; 4712 4713 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4714 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4715 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4716 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4717 unsigned size = fieldFromInstruction(Insn, 10, 2); 4718 4719 unsigned align = 0; 4720 unsigned index = 0; 4721 unsigned inc = 1; 4722 switch (size) { 4723 default: 4724 return MCDisassembler::Fail; 4725 case 0: 4726 if (fieldFromInstruction(Insn, 4, 1)) 4727 return MCDisassembler::Fail; // UNDEFINED 4728 index = fieldFromInstruction(Insn, 5, 3); 4729 break; 4730 case 1: 4731 if (fieldFromInstruction(Insn, 4, 1)) 4732 return MCDisassembler::Fail; // UNDEFINED 4733 index = fieldFromInstruction(Insn, 6, 2); 4734 if (fieldFromInstruction(Insn, 5, 1)) 4735 inc = 2; 4736 break; 4737 case 2: 4738 if (fieldFromInstruction(Insn, 4, 2)) 4739 return MCDisassembler::Fail; // UNDEFINED 4740 index = fieldFromInstruction(Insn, 7, 1); 4741 if (fieldFromInstruction(Insn, 6, 1)) 4742 inc = 2; 4743 break; 4744 } 4745 4746 if (Rm != 0xF) { // Writeback 4747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4748 return MCDisassembler::Fail; 4749 } 4750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4751 return MCDisassembler::Fail; 4752 Inst.addOperand(MCOperand::createImm(align)); 4753 if (Rm != 0xF) { 4754 if (Rm != 0xD) { 4755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4756 return MCDisassembler::Fail; 4757 } else 4758 Inst.addOperand(MCOperand::createReg(0)); 4759 } 4760 4761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4762 return MCDisassembler::Fail; 4763 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4764 return MCDisassembler::Fail; 4765 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4766 return MCDisassembler::Fail; 4767 Inst.addOperand(MCOperand::createImm(index)); 4768 4769 return S; 4770 } 4771 4772 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4773 uint64_t Address, const void *Decoder) { 4774 DecodeStatus S = MCDisassembler::Success; 4775 4776 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4777 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4778 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4779 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4780 unsigned size = fieldFromInstruction(Insn, 10, 2); 4781 4782 unsigned align = 0; 4783 unsigned index = 0; 4784 unsigned inc = 1; 4785 switch (size) { 4786 default: 4787 return MCDisassembler::Fail; 4788 case 0: 4789 if (fieldFromInstruction(Insn, 4, 1)) 4790 align = 4; 4791 index = fieldFromInstruction(Insn, 5, 3); 4792 break; 4793 case 1: 4794 if (fieldFromInstruction(Insn, 4, 1)) 4795 align = 8; 4796 index = fieldFromInstruction(Insn, 6, 2); 4797 if (fieldFromInstruction(Insn, 5, 1)) 4798 inc = 2; 4799 break; 4800 case 2: 4801 switch (fieldFromInstruction(Insn, 4, 2)) { 4802 case 0: 4803 align = 0; break; 4804 case 3: 4805 return MCDisassembler::Fail; 4806 default: 4807 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4808 } 4809 4810 index = fieldFromInstruction(Insn, 7, 1); 4811 if (fieldFromInstruction(Insn, 6, 1)) 4812 inc = 2; 4813 break; 4814 } 4815 4816 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4817 return MCDisassembler::Fail; 4818 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4819 return MCDisassembler::Fail; 4820 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4821 return MCDisassembler::Fail; 4822 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4823 return MCDisassembler::Fail; 4824 4825 if (Rm != 0xF) { // Writeback 4826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4827 return MCDisassembler::Fail; 4828 } 4829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4830 return MCDisassembler::Fail; 4831 Inst.addOperand(MCOperand::createImm(align)); 4832 if (Rm != 0xF) { 4833 if (Rm != 0xD) { 4834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4835 return MCDisassembler::Fail; 4836 } else 4837 Inst.addOperand(MCOperand::createReg(0)); 4838 } 4839 4840 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4841 return MCDisassembler::Fail; 4842 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4843 return MCDisassembler::Fail; 4844 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4845 return MCDisassembler::Fail; 4846 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4847 return MCDisassembler::Fail; 4848 Inst.addOperand(MCOperand::createImm(index)); 4849 4850 return S; 4851 } 4852 4853 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4854 uint64_t Address, const void *Decoder) { 4855 DecodeStatus S = MCDisassembler::Success; 4856 4857 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4858 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4859 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4860 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4861 unsigned size = fieldFromInstruction(Insn, 10, 2); 4862 4863 unsigned align = 0; 4864 unsigned index = 0; 4865 unsigned inc = 1; 4866 switch (size) { 4867 default: 4868 return MCDisassembler::Fail; 4869 case 0: 4870 if (fieldFromInstruction(Insn, 4, 1)) 4871 align = 4; 4872 index = fieldFromInstruction(Insn, 5, 3); 4873 break; 4874 case 1: 4875 if (fieldFromInstruction(Insn, 4, 1)) 4876 align = 8; 4877 index = fieldFromInstruction(Insn, 6, 2); 4878 if (fieldFromInstruction(Insn, 5, 1)) 4879 inc = 2; 4880 break; 4881 case 2: 4882 switch (fieldFromInstruction(Insn, 4, 2)) { 4883 case 0: 4884 align = 0; break; 4885 case 3: 4886 return MCDisassembler::Fail; 4887 default: 4888 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4889 } 4890 4891 index = fieldFromInstruction(Insn, 7, 1); 4892 if (fieldFromInstruction(Insn, 6, 1)) 4893 inc = 2; 4894 break; 4895 } 4896 4897 if (Rm != 0xF) { // Writeback 4898 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4899 return MCDisassembler::Fail; 4900 } 4901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4902 return MCDisassembler::Fail; 4903 Inst.addOperand(MCOperand::createImm(align)); 4904 if (Rm != 0xF) { 4905 if (Rm != 0xD) { 4906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4907 return MCDisassembler::Fail; 4908 } else 4909 Inst.addOperand(MCOperand::createReg(0)); 4910 } 4911 4912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4913 return MCDisassembler::Fail; 4914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4915 return MCDisassembler::Fail; 4916 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4917 return MCDisassembler::Fail; 4918 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4919 return MCDisassembler::Fail; 4920 Inst.addOperand(MCOperand::createImm(index)); 4921 4922 return S; 4923 } 4924 4925 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4926 uint64_t Address, const void *Decoder) { 4927 DecodeStatus S = MCDisassembler::Success; 4928 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4929 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4930 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4931 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4932 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4933 4934 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4935 S = MCDisassembler::SoftFail; 4936 4937 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4938 return MCDisassembler::Fail; 4939 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4940 return MCDisassembler::Fail; 4941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4942 return MCDisassembler::Fail; 4943 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4944 return MCDisassembler::Fail; 4945 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4946 return MCDisassembler::Fail; 4947 4948 return S; 4949 } 4950 4951 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4952 uint64_t Address, const void *Decoder) { 4953 DecodeStatus S = MCDisassembler::Success; 4954 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4955 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4956 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4957 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4958 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4959 4960 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4961 S = MCDisassembler::SoftFail; 4962 4963 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4964 return MCDisassembler::Fail; 4965 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4966 return MCDisassembler::Fail; 4967 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4968 return MCDisassembler::Fail; 4969 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4970 return MCDisassembler::Fail; 4971 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4972 return MCDisassembler::Fail; 4973 4974 return S; 4975 } 4976 4977 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4978 uint64_t Address, const void *Decoder) { 4979 DecodeStatus S = MCDisassembler::Success; 4980 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4981 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4982 4983 if (pred == 0xF) { 4984 pred = 0xE; 4985 S = MCDisassembler::SoftFail; 4986 } 4987 4988 if (mask == 0x0) 4989 return MCDisassembler::Fail; 4990 4991 Inst.addOperand(MCOperand::createImm(pred)); 4992 Inst.addOperand(MCOperand::createImm(mask)); 4993 return S; 4994 } 4995 4996 static DecodeStatus 4997 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4998 uint64_t Address, const void *Decoder) { 4999 DecodeStatus S = MCDisassembler::Success; 5000 5001 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5002 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5003 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5004 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5005 unsigned W = fieldFromInstruction(Insn, 21, 1); 5006 unsigned U = fieldFromInstruction(Insn, 23, 1); 5007 unsigned P = fieldFromInstruction(Insn, 24, 1); 5008 bool writeback = (W == 1) | (P == 0); 5009 5010 addr |= (U << 8) | (Rn << 9); 5011 5012 if (writeback && (Rn == Rt || Rn == Rt2)) 5013 Check(S, MCDisassembler::SoftFail); 5014 if (Rt == Rt2) 5015 Check(S, MCDisassembler::SoftFail); 5016 5017 // Rt 5018 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5019 return MCDisassembler::Fail; 5020 // Rt2 5021 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5022 return MCDisassembler::Fail; 5023 // Writeback operand 5024 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5025 return MCDisassembler::Fail; 5026 // addr 5027 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5028 return MCDisassembler::Fail; 5029 5030 return S; 5031 } 5032 5033 static DecodeStatus 5034 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5035 uint64_t Address, const void *Decoder) { 5036 DecodeStatus S = MCDisassembler::Success; 5037 5038 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5039 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5040 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5041 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5042 unsigned W = fieldFromInstruction(Insn, 21, 1); 5043 unsigned U = fieldFromInstruction(Insn, 23, 1); 5044 unsigned P = fieldFromInstruction(Insn, 24, 1); 5045 bool writeback = (W == 1) | (P == 0); 5046 5047 addr |= (U << 8) | (Rn << 9); 5048 5049 if (writeback && (Rn == Rt || Rn == Rt2)) 5050 Check(S, MCDisassembler::SoftFail); 5051 5052 // Writeback operand 5053 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5054 return MCDisassembler::Fail; 5055 // Rt 5056 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5057 return MCDisassembler::Fail; 5058 // Rt2 5059 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5060 return MCDisassembler::Fail; 5061 // addr 5062 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5063 return MCDisassembler::Fail; 5064 5065 return S; 5066 } 5067 5068 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5069 uint64_t Address, const void *Decoder) { 5070 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5071 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5072 if (sign1 != sign2) return MCDisassembler::Fail; 5073 5074 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5075 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5076 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5077 Val |= sign1 << 12; 5078 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5079 5080 return MCDisassembler::Success; 5081 } 5082 5083 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5084 uint64_t Address, 5085 const void *Decoder) { 5086 DecodeStatus S = MCDisassembler::Success; 5087 5088 // Shift of "asr #32" is not allowed in Thumb2 mode. 5089 if (Val == 0x20) S = MCDisassembler::Fail; 5090 Inst.addOperand(MCOperand::createImm(Val)); 5091 return S; 5092 } 5093 5094 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5095 uint64_t Address, const void *Decoder) { 5096 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5097 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5098 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5099 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5100 5101 if (pred == 0xF) 5102 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5103 5104 DecodeStatus S = MCDisassembler::Success; 5105 5106 if (Rt == Rn || Rn == Rt2) 5107 S = MCDisassembler::SoftFail; 5108 5109 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5110 return MCDisassembler::Fail; 5111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5112 return MCDisassembler::Fail; 5113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5114 return MCDisassembler::Fail; 5115 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5116 return MCDisassembler::Fail; 5117 5118 return S; 5119 } 5120 5121 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5122 uint64_t Address, const void *Decoder) { 5123 const FeatureBitset &featureBits = 5124 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5125 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5126 5127 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5128 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5129 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5130 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5131 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5132 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5133 unsigned op = fieldFromInstruction(Insn, 5, 1); 5134 5135 DecodeStatus S = MCDisassembler::Success; 5136 5137 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5138 if (!(imm & 0x38)) { 5139 if (cmode == 0xF) { 5140 if (op == 1) return MCDisassembler::Fail; 5141 Inst.setOpcode(ARM::VMOVv2f32); 5142 } 5143 if (hasFullFP16) { 5144 if (cmode == 0xE) { 5145 if (op == 1) { 5146 Inst.setOpcode(ARM::VMOVv1i64); 5147 } else { 5148 Inst.setOpcode(ARM::VMOVv8i8); 5149 } 5150 } 5151 if (cmode == 0xD) { 5152 if (op == 1) { 5153 Inst.setOpcode(ARM::VMVNv2i32); 5154 } else { 5155 Inst.setOpcode(ARM::VMOVv2i32); 5156 } 5157 } 5158 if (cmode == 0xC) { 5159 if (op == 1) { 5160 Inst.setOpcode(ARM::VMVNv2i32); 5161 } else { 5162 Inst.setOpcode(ARM::VMOVv2i32); 5163 } 5164 } 5165 } 5166 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5167 } 5168 5169 if (!(imm & 0x20)) return MCDisassembler::Fail; 5170 5171 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5172 return MCDisassembler::Fail; 5173 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5174 return MCDisassembler::Fail; 5175 Inst.addOperand(MCOperand::createImm(64 - imm)); 5176 5177 return S; 5178 } 5179 5180 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5181 uint64_t Address, const void *Decoder) { 5182 const FeatureBitset &featureBits = 5183 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5184 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5185 5186 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5187 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5188 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5189 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5190 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5191 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5192 unsigned op = fieldFromInstruction(Insn, 5, 1); 5193 5194 DecodeStatus S = MCDisassembler::Success; 5195 5196 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5197 if (!(imm & 0x38)) { 5198 if (cmode == 0xF) { 5199 if (op == 1) return MCDisassembler::Fail; 5200 Inst.setOpcode(ARM::VMOVv4f32); 5201 } 5202 if (hasFullFP16) { 5203 if (cmode == 0xE) { 5204 if (op == 1) { 5205 Inst.setOpcode(ARM::VMOVv2i64); 5206 } else { 5207 Inst.setOpcode(ARM::VMOVv16i8); 5208 } 5209 } 5210 if (cmode == 0xD) { 5211 if (op == 1) { 5212 Inst.setOpcode(ARM::VMVNv4i32); 5213 } else { 5214 Inst.setOpcode(ARM::VMOVv4i32); 5215 } 5216 } 5217 if (cmode == 0xC) { 5218 if (op == 1) { 5219 Inst.setOpcode(ARM::VMVNv4i32); 5220 } else { 5221 Inst.setOpcode(ARM::VMOVv4i32); 5222 } 5223 } 5224 } 5225 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5226 } 5227 5228 if (!(imm & 0x20)) return MCDisassembler::Fail; 5229 5230 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5231 return MCDisassembler::Fail; 5232 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5233 return MCDisassembler::Fail; 5234 Inst.addOperand(MCOperand::createImm(64 - imm)); 5235 5236 return S; 5237 } 5238 5239 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5240 unsigned Insn, 5241 uint64_t Address, 5242 const void *Decoder) { 5243 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5244 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5245 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5246 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5247 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5248 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5249 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5250 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5251 5252 DecodeStatus S = MCDisassembler::Success; 5253 5254 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5255 5256 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5257 return MCDisassembler::Fail; 5258 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5259 return MCDisassembler::Fail; 5260 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5261 return MCDisassembler::Fail; 5262 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5263 return MCDisassembler::Fail; 5264 // The lane index does not have any bits in the encoding, because it can only 5265 // be 0. 5266 Inst.addOperand(MCOperand::createImm(0)); 5267 Inst.addOperand(MCOperand::createImm(rotate)); 5268 5269 return S; 5270 } 5271 5272 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5273 uint64_t Address, const void *Decoder) { 5274 DecodeStatus S = MCDisassembler::Success; 5275 5276 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5277 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5278 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5279 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5280 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5281 5282 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5283 S = MCDisassembler::SoftFail; 5284 5285 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5286 return MCDisassembler::Fail; 5287 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5288 return MCDisassembler::Fail; 5289 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5290 return MCDisassembler::Fail; 5291 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5292 return MCDisassembler::Fail; 5293 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5294 return MCDisassembler::Fail; 5295 5296 return S; 5297 } 5298 5299 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5300 uint64_t Address, const void *Decoder) { 5301 DecodeStatus S = MCDisassembler::Success; 5302 5303 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5304 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5305 unsigned cop = fieldFromInstruction(Val, 8, 4); 5306 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5307 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5308 5309 if ((cop & ~0x1) == 0xa) 5310 return MCDisassembler::Fail; 5311 5312 if (Rt == Rt2) 5313 S = MCDisassembler::SoftFail; 5314 5315 // We have to check if the instruction is MRRC2 5316 // or MCRR2 when constructing the operands for 5317 // Inst. Reason is because MRRC2 stores to two 5318 // registers so it's tablegen desc has has two 5319 // outputs whereas MCRR doesn't store to any 5320 // registers so all of it's operands are listed 5321 // as inputs, therefore the operand order for 5322 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5323 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5324 5325 if (Inst.getOpcode() == ARM::MRRC2) { 5326 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5327 return MCDisassembler::Fail; 5328 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5329 return MCDisassembler::Fail; 5330 } 5331 Inst.addOperand(MCOperand::createImm(cop)); 5332 Inst.addOperand(MCOperand::createImm(opc1)); 5333 if (Inst.getOpcode() == ARM::MCRR2) { 5334 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5335 return MCDisassembler::Fail; 5336 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5337 return MCDisassembler::Fail; 5338 } 5339 Inst.addOperand(MCOperand::createImm(CRm)); 5340 5341 return S; 5342 } 5343 5344 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5345 uint64_t Address, 5346 const void *Decoder) { 5347 const FeatureBitset &featureBits = 5348 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5349 DecodeStatus S = MCDisassembler::Success; 5350 5351 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5352 5353 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5354 if (Rt == 13 || Rt == 15) 5355 S = MCDisassembler::SoftFail; 5356 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5357 } else 5358 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5359 5360 if (featureBits[ARM::ModeThumb]) { 5361 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5362 Inst.addOperand(MCOperand::createReg(0)); 5363 } else { 5364 unsigned pred = fieldFromInstruction(Val, 28, 4); 5365 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5366 return MCDisassembler::Fail; 5367 } 5368 5369 return S; 5370 } 5371