1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Pull DecodeStatus and its enum values into the global namespace. 28 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 29 #define Success llvm::MCDisassembler::Success 30 #define Unpredictable llvm::MCDisassembler::SoftFail 31 #define Fail llvm::MCDisassembler::Fail 32 33 // Helper macro to perform setwise reduction of the current running status 34 // and another status, and return if the new status is Fail. 35 #define CHECK(S,X) do { \ 36 S = (DecodeStatus) ((int)S & (X)); \ 37 if (S == Fail) return Fail; \ 38 } while(0) 39 40 // Forward declare these because the autogenerated code will reference them. 41 // Definitions are further down. 42 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 43 uint64_t Address, const void *Decoder); 44 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 45 unsigned RegNo, uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 50 uint64_t Address, const void *Decoder); 51 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 52 uint64_t Address, const void *Decoder); 53 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 54 uint64_t Address, const void *Decoder); 55 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 56 uint64_t Address, const void *Decoder); 57 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 58 uint64_t Address, const void *Decoder); 59 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 60 unsigned RegNo, 61 uint64_t Address, 62 const void *Decoder); 63 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 64 uint64_t Address, const void *Decoder); 65 66 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 67 uint64_t Address, const void *Decoder); 68 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 69 uint64_t Address, const void *Decoder); 70 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 71 uint64_t Address, const void *Decoder); 72 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 73 uint64_t Address, const void *Decoder); 74 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 75 uint64_t Address, const void *Decoder); 76 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 77 uint64_t Address, const void *Decoder); 78 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 79 uint64_t Address, const void *Decoder); 80 81 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 82 uint64_t Address, const void *Decoder); 83 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 84 uint64_t Address, const void *Decoder); 85 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 86 unsigned Insn, 87 uint64_t Address, 88 const void *Decoder); 89 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 90 uint64_t Address, const void *Decoder); 91 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 92 uint64_t Address, const void *Decoder); 93 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 94 uint64_t Address, const void *Decoder); 95 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 96 uint64_t Address, const void *Decoder); 97 98 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 99 unsigned Insn, 100 uint64_t Adddress, 101 const void *Decoder); 102 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 103 uint64_t Address, const void *Decoder); 104 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 105 uint64_t Address, const void *Decoder); 106 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 125 uint64_t Address, const void *Decoder); 126 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 129 uint64_t Address, const void *Decoder); 130 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 147 uint64_t Address, const void *Decoder); 148 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178 179 180 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 225 uint64_t Address, const void *Decoder); 226 227 #include "ARMGenDisassemblerTables.inc" 228 #include "ARMGenInstrInfo.inc" 229 #include "ARMGenEDInfo.inc" 230 231 using namespace llvm; 232 233 static MCDisassembler *createARMDisassembler(const Target &T) { 234 return new ARMDisassembler; 235 } 236 237 static MCDisassembler *createThumbDisassembler(const Target &T) { 238 return new ThumbDisassembler; 239 } 240 241 EDInstInfo *ARMDisassembler::getEDInfo() const { 242 return instInfoARM; 243 } 244 245 EDInstInfo *ThumbDisassembler::getEDInfo() const { 246 return instInfoARM; 247 } 248 249 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 250 const MemoryObject &Region, 251 uint64_t Address, 252 raw_ostream &os) const { 253 uint8_t bytes[4]; 254 255 // We want to read exactly 4 bytes of data. 256 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 257 return Fail; 258 259 // Encoded as a small-endian 32-bit word in the stream. 260 uint32_t insn = (bytes[3] << 24) | 261 (bytes[2] << 16) | 262 (bytes[1] << 8) | 263 (bytes[0] << 0); 264 265 // Calling the auto-generated decoder function. 266 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); 267 if (result != Fail) { 268 Size = 4; 269 return result; 270 } 271 272 // Instructions that are shared between ARM and Thumb modes. 273 // FIXME: This shouldn't really exist. It's an artifact of the 274 // fact that we fail to encode a few instructions properly for Thumb. 275 MI.clear(); 276 result = decodeCommonInstruction32(MI, insn, Address, this); 277 if (result != Fail) { 278 Size = 4; 279 return result; 280 } 281 282 // VFP and NEON instructions, similarly, are shared between ARM 283 // and Thumb modes. 284 MI.clear(); 285 result = decodeVFPInstruction32(MI, insn, Address, this); 286 if (result != Fail) { 287 Size = 4; 288 return result; 289 } 290 291 MI.clear(); 292 result = decodeNEONDataInstruction32(MI, insn, Address, this); 293 if (result != Fail) { 294 Size = 4; 295 // Add a fake predicate operand, because we share these instruction 296 // definitions with Thumb2 where these instructions are predicable. 297 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 298 return result; 299 } 300 301 MI.clear(); 302 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 303 if (result != Fail) { 304 Size = 4; 305 // Add a fake predicate operand, because we share these instruction 306 // definitions with Thumb2 where these instructions are predicable. 307 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 308 return result; 309 } 310 311 MI.clear(); 312 result = decodeNEONDupInstruction32(MI, insn, Address, this); 313 if (result != Fail) { 314 Size = 4; 315 // Add a fake predicate operand, because we share these instruction 316 // definitions with Thumb2 where these instructions are predicable. 317 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 318 return result; 319 } 320 321 MI.clear(); 322 323 return Fail; 324 } 325 326 namespace llvm { 327 extern MCInstrDesc ARMInsts[]; 328 } 329 330 // Thumb1 instructions don't have explicit S bits. Rather, they 331 // implicitly set CPSR. Since it's not represented in the encoding, the 332 // auto-generated decoder won't inject the CPSR operand. We need to fix 333 // that as a post-pass. 334 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 335 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 336 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 337 MCInst::iterator I = MI.begin(); 338 for (unsigned i = 0; i < NumOps; ++i, ++I) { 339 if (I == MI.end()) break; 340 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 341 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 342 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 343 return; 344 } 345 } 346 347 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 348 } 349 350 // Most Thumb instructions don't have explicit predicates in the 351 // encoding, but rather get their predicates from IT context. We need 352 // to fix up the predicate operands using this context information as a 353 // post-pass. 354 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 355 // A few instructions actually have predicates encoded in them. Don't 356 // try to overwrite it if we're seeing one of those. 357 switch (MI.getOpcode()) { 358 case ARM::tBcc: 359 case ARM::t2Bcc: 360 return; 361 default: 362 break; 363 } 364 365 // If we're in an IT block, base the predicate on that. Otherwise, 366 // assume a predicate of AL. 367 unsigned CC; 368 if (!ITBlock.empty()) { 369 CC = ITBlock.back(); 370 ITBlock.pop_back(); 371 } else 372 CC = ARMCC::AL; 373 374 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 375 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 376 MCInst::iterator I = MI.begin(); 377 for (unsigned i = 0; i < NumOps; ++i, ++I) { 378 if (I == MI.end()) break; 379 if (OpInfo[i].isPredicate()) { 380 I = MI.insert(I, MCOperand::CreateImm(CC)); 381 ++I; 382 if (CC == ARMCC::AL) 383 MI.insert(I, MCOperand::CreateReg(0)); 384 else 385 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 386 return; 387 } 388 } 389 390 I = MI.insert(I, MCOperand::CreateImm(CC)); 391 ++I; 392 if (CC == ARMCC::AL) 393 MI.insert(I, MCOperand::CreateReg(0)); 394 else 395 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 396 } 397 398 // Thumb VFP instructions are a special case. Because we share their 399 // encodings between ARM and Thumb modes, and they are predicable in ARM 400 // mode, the auto-generated decoder will give them an (incorrect) 401 // predicate operand. We need to rewrite these operands based on the IT 402 // context as a post-pass. 403 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 404 unsigned CC; 405 if (!ITBlock.empty()) { 406 CC = ITBlock.back(); 407 ITBlock.pop_back(); 408 } else 409 CC = ARMCC::AL; 410 411 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 412 MCInst::iterator I = MI.begin(); 413 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 414 if (OpInfo[i].isPredicate() ) { 415 I->setImm(CC); 416 ++I; 417 if (CC == ARMCC::AL) 418 I->setReg(0); 419 else 420 I->setReg(ARM::CPSR); 421 return; 422 } 423 } 424 } 425 426 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 427 const MemoryObject &Region, 428 uint64_t Address, 429 raw_ostream &os) const { 430 uint8_t bytes[4]; 431 432 // We want to read exactly 2 bytes of data. 433 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 434 return Fail; 435 436 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 437 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); 438 if (result != Fail) { 439 Size = 2; 440 AddThumbPredicate(MI); 441 return result; 442 } 443 444 MI.clear(); 445 result = decodeThumbSBitInstruction16(MI, insn16, Address, this); 446 if (result) { 447 Size = 2; 448 bool InITBlock = !ITBlock.empty(); 449 AddThumbPredicate(MI); 450 AddThumb1SBit(MI, InITBlock); 451 return result; 452 } 453 454 MI.clear(); 455 result = decodeThumb2Instruction16(MI, insn16, Address, this); 456 if (result != Fail) { 457 Size = 2; 458 AddThumbPredicate(MI); 459 460 // If we find an IT instruction, we need to parse its condition 461 // code and mask operands so that we can apply them correctly 462 // to the subsequent instructions. 463 if (MI.getOpcode() == ARM::t2IT) { 464 unsigned firstcond = MI.getOperand(0).getImm(); 465 uint32_t mask = MI.getOperand(1).getImm(); 466 unsigned zeros = CountTrailingZeros_32(mask); 467 mask >>= zeros+1; 468 469 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 470 if (firstcond ^ (mask & 1)) 471 ITBlock.push_back(firstcond ^ 1); 472 else 473 ITBlock.push_back(firstcond); 474 mask >>= 1; 475 } 476 ITBlock.push_back(firstcond); 477 } 478 479 return result; 480 } 481 482 // We want to read exactly 4 bytes of data. 483 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 484 return Fail; 485 486 uint32_t insn32 = (bytes[3] << 8) | 487 (bytes[2] << 0) | 488 (bytes[1] << 24) | 489 (bytes[0] << 16); 490 MI.clear(); 491 result = decodeThumbInstruction32(MI, insn32, Address, this); 492 if (result != Fail) { 493 Size = 4; 494 bool InITBlock = ITBlock.size(); 495 AddThumbPredicate(MI); 496 AddThumb1SBit(MI, InITBlock); 497 return result; 498 } 499 500 MI.clear(); 501 result = decodeThumb2Instruction32(MI, insn32, Address, this); 502 if (result != Fail) { 503 Size = 4; 504 AddThumbPredicate(MI); 505 return result; 506 } 507 508 MI.clear(); 509 result = decodeCommonInstruction32(MI, insn32, Address, this); 510 if (result != Fail) { 511 Size = 4; 512 AddThumbPredicate(MI); 513 return result; 514 } 515 516 MI.clear(); 517 result = decodeVFPInstruction32(MI, insn32, Address, this); 518 if (result != Fail) { 519 Size = 4; 520 UpdateThumbVFPPredicate(MI); 521 return result; 522 } 523 524 MI.clear(); 525 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 526 if (result != Fail) { 527 Size = 4; 528 AddThumbPredicate(MI); 529 return result; 530 } 531 532 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 533 MI.clear(); 534 uint32_t NEONLdStInsn = insn32; 535 NEONLdStInsn &= 0xF0FFFFFF; 536 NEONLdStInsn |= 0x04000000; 537 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 538 if (result != Fail) { 539 Size = 4; 540 AddThumbPredicate(MI); 541 return result; 542 } 543 } 544 545 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 546 MI.clear(); 547 uint32_t NEONDataInsn = insn32; 548 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 549 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 550 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 551 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 552 if (result != Fail) { 553 Size = 4; 554 AddThumbPredicate(MI); 555 return result; 556 } 557 } 558 559 return Fail; 560 } 561 562 563 extern "C" void LLVMInitializeARMDisassembler() { 564 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 565 createARMDisassembler); 566 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 567 createThumbDisassembler); 568 } 569 570 static const unsigned GPRDecoderTable[] = { 571 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 572 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 573 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 574 ARM::R12, ARM::SP, ARM::LR, ARM::PC 575 }; 576 577 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 578 uint64_t Address, const void *Decoder) { 579 if (RegNo > 15) 580 return Fail; 581 582 unsigned Register = GPRDecoderTable[RegNo]; 583 Inst.addOperand(MCOperand::CreateReg(Register)); 584 return Success; 585 } 586 587 static DecodeStatus 588 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 589 uint64_t Address, const void *Decoder) { 590 if (RegNo == 15) return Fail; 591 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 592 } 593 594 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 595 uint64_t Address, const void *Decoder) { 596 if (RegNo > 7) 597 return Fail; 598 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 599 } 600 601 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 602 uint64_t Address, const void *Decoder) { 603 unsigned Register = 0; 604 switch (RegNo) { 605 case 0: 606 Register = ARM::R0; 607 break; 608 case 1: 609 Register = ARM::R1; 610 break; 611 case 2: 612 Register = ARM::R2; 613 break; 614 case 3: 615 Register = ARM::R3; 616 break; 617 case 9: 618 Register = ARM::R9; 619 break; 620 case 12: 621 Register = ARM::R12; 622 break; 623 default: 624 return Fail; 625 } 626 627 Inst.addOperand(MCOperand::CreateReg(Register)); 628 return Success; 629 } 630 631 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 632 uint64_t Address, const void *Decoder) { 633 if (RegNo == 13 || RegNo == 15) return Fail; 634 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 635 } 636 637 static const unsigned SPRDecoderTable[] = { 638 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 639 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 640 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 641 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 642 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 643 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 644 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 645 ARM::S28, ARM::S29, ARM::S30, ARM::S31 646 }; 647 648 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 649 uint64_t Address, const void *Decoder) { 650 if (RegNo > 31) 651 return Fail; 652 653 unsigned Register = SPRDecoderTable[RegNo]; 654 Inst.addOperand(MCOperand::CreateReg(Register)); 655 return Success; 656 } 657 658 static const unsigned DPRDecoderTable[] = { 659 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 660 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 661 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 662 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 663 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 664 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 665 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 666 ARM::D28, ARM::D29, ARM::D30, ARM::D31 667 }; 668 669 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 670 uint64_t Address, const void *Decoder) { 671 if (RegNo > 31) 672 return Fail; 673 674 unsigned Register = DPRDecoderTable[RegNo]; 675 Inst.addOperand(MCOperand::CreateReg(Register)); 676 return Success; 677 } 678 679 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 680 uint64_t Address, const void *Decoder) { 681 if (RegNo > 7) 682 return Fail; 683 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 684 } 685 686 static DecodeStatus 687 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 688 uint64_t Address, const void *Decoder) { 689 if (RegNo > 15) 690 return Fail; 691 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 692 } 693 694 static const unsigned QPRDecoderTable[] = { 695 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 696 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 697 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 698 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 699 }; 700 701 702 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 703 uint64_t Address, const void *Decoder) { 704 if (RegNo > 31) 705 return Fail; 706 RegNo >>= 1; 707 708 unsigned Register = QPRDecoderTable[RegNo]; 709 Inst.addOperand(MCOperand::CreateReg(Register)); 710 return Success; 711 } 712 713 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 714 uint64_t Address, const void *Decoder) { 715 if (Val == 0xF) return Fail; 716 // AL predicate is not allowed on Thumb1 branches. 717 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 718 return Fail; 719 Inst.addOperand(MCOperand::CreateImm(Val)); 720 if (Val == ARMCC::AL) { 721 Inst.addOperand(MCOperand::CreateReg(0)); 722 } else 723 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 724 return Success; 725 } 726 727 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 728 uint64_t Address, const void *Decoder) { 729 if (Val) 730 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 731 else 732 Inst.addOperand(MCOperand::CreateReg(0)); 733 return Success; 734 } 735 736 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 737 uint64_t Address, const void *Decoder) { 738 uint32_t imm = Val & 0xFF; 739 uint32_t rot = (Val & 0xF00) >> 7; 740 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 741 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 742 return Success; 743 } 744 745 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 746 uint64_t Address, const void *Decoder) { 747 Val <<= 2; 748 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 749 return Success; 750 } 751 752 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 753 uint64_t Address, const void *Decoder) { 754 DecodeStatus S = Success; 755 756 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 757 unsigned type = fieldFromInstruction32(Val, 5, 2); 758 unsigned imm = fieldFromInstruction32(Val, 7, 5); 759 760 // Register-immediate 761 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 762 763 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 764 switch (type) { 765 case 0: 766 Shift = ARM_AM::lsl; 767 break; 768 case 1: 769 Shift = ARM_AM::lsr; 770 break; 771 case 2: 772 Shift = ARM_AM::asr; 773 break; 774 case 3: 775 Shift = ARM_AM::ror; 776 break; 777 } 778 779 if (Shift == ARM_AM::ror && imm == 0) 780 Shift = ARM_AM::rrx; 781 782 unsigned Op = Shift | (imm << 3); 783 Inst.addOperand(MCOperand::CreateImm(Op)); 784 785 return S; 786 } 787 788 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 789 uint64_t Address, const void *Decoder) { 790 DecodeStatus S = Success; 791 792 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 793 unsigned type = fieldFromInstruction32(Val, 5, 2); 794 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 795 796 // Register-register 797 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 798 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); 799 800 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 801 switch (type) { 802 case 0: 803 Shift = ARM_AM::lsl; 804 break; 805 case 1: 806 Shift = ARM_AM::lsr; 807 break; 808 case 2: 809 Shift = ARM_AM::asr; 810 break; 811 case 3: 812 Shift = ARM_AM::ror; 813 break; 814 } 815 816 Inst.addOperand(MCOperand::CreateImm(Shift)); 817 818 return S; 819 } 820 821 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 822 uint64_t Address, const void *Decoder) { 823 DecodeStatus S = Success; 824 825 // Empty register lists are not allowed. 826 if (CountPopulation_32(Val) == 0) return Fail; 827 for (unsigned i = 0; i < 16; ++i) { 828 if (Val & (1 << i)) { 829 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); 830 } 831 } 832 833 return S; 834 } 835 836 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 837 uint64_t Address, const void *Decoder) { 838 DecodeStatus S = Success; 839 840 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 841 unsigned regs = Val & 0xFF; 842 843 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); 844 for (unsigned i = 0; i < (regs - 1); ++i) { 845 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); 846 } 847 848 return S; 849 } 850 851 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 852 uint64_t Address, const void *Decoder) { 853 DecodeStatus S = Success; 854 855 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 856 unsigned regs = (Val & 0xFF) / 2; 857 858 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); 859 for (unsigned i = 0; i < (regs - 1); ++i) { 860 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); 861 } 862 863 return S; 864 } 865 866 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 867 uint64_t Address, const void *Decoder) { 868 // This operand encodes a mask of contiguous zeros between a specified MSB 869 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 870 // the mask of all bits LSB-and-lower, and then xor them to create 871 // the mask of that's all ones on [msb, lsb]. Finally we not it to 872 // create the final mask. 873 unsigned msb = fieldFromInstruction32(Val, 5, 5); 874 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 875 uint32_t msb_mask = (1 << (msb+1)) - 1; 876 uint32_t lsb_mask = (1 << lsb) - 1; 877 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 878 return Success; 879 } 880 881 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 882 uint64_t Address, const void *Decoder) { 883 DecodeStatus S = Success; 884 885 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 886 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 887 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 888 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 889 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 890 unsigned U = fieldFromInstruction32(Insn, 23, 1); 891 892 switch (Inst.getOpcode()) { 893 case ARM::LDC_OFFSET: 894 case ARM::LDC_PRE: 895 case ARM::LDC_POST: 896 case ARM::LDC_OPTION: 897 case ARM::LDCL_OFFSET: 898 case ARM::LDCL_PRE: 899 case ARM::LDCL_POST: 900 case ARM::LDCL_OPTION: 901 case ARM::STC_OFFSET: 902 case ARM::STC_PRE: 903 case ARM::STC_POST: 904 case ARM::STC_OPTION: 905 case ARM::STCL_OFFSET: 906 case ARM::STCL_PRE: 907 case ARM::STCL_POST: 908 case ARM::STCL_OPTION: 909 if (coproc == 0xA || coproc == 0xB) 910 return Fail; 911 break; 912 default: 913 break; 914 } 915 916 Inst.addOperand(MCOperand::CreateImm(coproc)); 917 Inst.addOperand(MCOperand::CreateImm(CRd)); 918 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 919 switch (Inst.getOpcode()) { 920 case ARM::LDC_OPTION: 921 case ARM::LDCL_OPTION: 922 case ARM::LDC2_OPTION: 923 case ARM::LDC2L_OPTION: 924 case ARM::STC_OPTION: 925 case ARM::STCL_OPTION: 926 case ARM::STC2_OPTION: 927 case ARM::STC2L_OPTION: 928 case ARM::LDCL_POST: 929 case ARM::STCL_POST: 930 case ARM::LDC2L_POST: 931 case ARM::STC2L_POST: 932 break; 933 default: 934 Inst.addOperand(MCOperand::CreateReg(0)); 935 break; 936 } 937 938 unsigned P = fieldFromInstruction32(Insn, 24, 1); 939 unsigned W = fieldFromInstruction32(Insn, 21, 1); 940 941 bool writeback = (P == 0) || (W == 1); 942 unsigned idx_mode = 0; 943 if (P && writeback) 944 idx_mode = ARMII::IndexModePre; 945 else if (!P && writeback) 946 idx_mode = ARMII::IndexModePost; 947 948 switch (Inst.getOpcode()) { 949 case ARM::LDCL_POST: 950 case ARM::STCL_POST: 951 case ARM::LDC2L_POST: 952 case ARM::STC2L_POST: 953 imm |= U << 8; 954 case ARM::LDC_OPTION: 955 case ARM::LDCL_OPTION: 956 case ARM::LDC2_OPTION: 957 case ARM::LDC2L_OPTION: 958 case ARM::STC_OPTION: 959 case ARM::STCL_OPTION: 960 case ARM::STC2_OPTION: 961 case ARM::STC2L_OPTION: 962 Inst.addOperand(MCOperand::CreateImm(imm)); 963 break; 964 default: 965 if (U) 966 Inst.addOperand(MCOperand::CreateImm( 967 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 968 else 969 Inst.addOperand(MCOperand::CreateImm( 970 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 971 break; 972 } 973 974 switch (Inst.getOpcode()) { 975 case ARM::LDC_OFFSET: 976 case ARM::LDC_PRE: 977 case ARM::LDC_POST: 978 case ARM::LDC_OPTION: 979 case ARM::LDCL_OFFSET: 980 case ARM::LDCL_PRE: 981 case ARM::LDCL_POST: 982 case ARM::LDCL_OPTION: 983 case ARM::STC_OFFSET: 984 case ARM::STC_PRE: 985 case ARM::STC_POST: 986 case ARM::STC_OPTION: 987 case ARM::STCL_OFFSET: 988 case ARM::STCL_PRE: 989 case ARM::STCL_POST: 990 case ARM::STCL_OPTION: 991 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 992 break; 993 default: 994 break; 995 } 996 997 return S; 998 } 999 1000 static DecodeStatus 1001 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1002 uint64_t Address, const void *Decoder) { 1003 DecodeStatus S = Success; 1004 1005 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1006 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1007 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1008 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1009 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1010 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1011 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1012 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1013 1014 // On stores, the writeback operand precedes Rt. 1015 switch (Inst.getOpcode()) { 1016 case ARM::STR_POST_IMM: 1017 case ARM::STR_POST_REG: 1018 case ARM::STRB_POST_IMM: 1019 case ARM::STRB_POST_REG: 1020 case ARM::STRT_POST_REG: 1021 case ARM::STRT_POST_IMM: 1022 case ARM::STRBT_POST_REG: 1023 case ARM::STRBT_POST_IMM: 1024 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1025 break; 1026 default: 1027 break; 1028 } 1029 1030 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1031 1032 // On loads, the writeback operand comes after Rt. 1033 switch (Inst.getOpcode()) { 1034 case ARM::LDR_POST_IMM: 1035 case ARM::LDR_POST_REG: 1036 case ARM::LDRB_POST_IMM: 1037 case ARM::LDRB_POST_REG: 1038 case ARM::LDR_PRE: 1039 case ARM::LDRB_PRE: 1040 case ARM::LDRBT_POST_REG: 1041 case ARM::LDRBT_POST_IMM: 1042 case ARM::LDRT_POST_REG: 1043 case ARM::LDRT_POST_IMM: 1044 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1045 break; 1046 default: 1047 break; 1048 } 1049 1050 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1051 1052 ARM_AM::AddrOpc Op = ARM_AM::add; 1053 if (!fieldFromInstruction32(Insn, 23, 1)) 1054 Op = ARM_AM::sub; 1055 1056 bool writeback = (P == 0) || (W == 1); 1057 unsigned idx_mode = 0; 1058 if (P && writeback) 1059 idx_mode = ARMII::IndexModePre; 1060 else if (!P && writeback) 1061 idx_mode = ARMII::IndexModePost; 1062 1063 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE 1064 1065 if (reg) { 1066 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1067 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1068 switch( fieldFromInstruction32(Insn, 5, 2)) { 1069 case 0: 1070 Opc = ARM_AM::lsl; 1071 break; 1072 case 1: 1073 Opc = ARM_AM::lsr; 1074 break; 1075 case 2: 1076 Opc = ARM_AM::asr; 1077 break; 1078 case 3: 1079 Opc = ARM_AM::ror; 1080 break; 1081 default: 1082 return Fail; 1083 } 1084 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1085 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1086 1087 Inst.addOperand(MCOperand::CreateImm(imm)); 1088 } else { 1089 Inst.addOperand(MCOperand::CreateReg(0)); 1090 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1091 Inst.addOperand(MCOperand::CreateImm(tmp)); 1092 } 1093 1094 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1095 1096 return S; 1097 } 1098 1099 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1100 uint64_t Address, const void *Decoder) { 1101 DecodeStatus S = Success; 1102 1103 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1104 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1105 unsigned type = fieldFromInstruction32(Val, 5, 2); 1106 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1107 unsigned U = fieldFromInstruction32(Val, 12, 1); 1108 1109 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1110 switch (type) { 1111 case 0: 1112 ShOp = ARM_AM::lsl; 1113 break; 1114 case 1: 1115 ShOp = ARM_AM::lsr; 1116 break; 1117 case 2: 1118 ShOp = ARM_AM::asr; 1119 break; 1120 case 3: 1121 ShOp = ARM_AM::ror; 1122 break; 1123 } 1124 1125 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1126 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1127 unsigned shift; 1128 if (U) 1129 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1130 else 1131 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1132 Inst.addOperand(MCOperand::CreateImm(shift)); 1133 1134 return S; 1135 } 1136 1137 static DecodeStatus 1138 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1139 uint64_t Address, const void *Decoder) { 1140 DecodeStatus S = Success; 1141 1142 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1143 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1144 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1145 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1146 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1147 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1148 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1149 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1150 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1151 1152 bool writeback = (W == 1) | (P == 0); 1153 1154 // For {LD,ST}RD, Rt must be even, else undefined. 1155 switch (Inst.getOpcode()) { 1156 case ARM::STRD: 1157 case ARM::STRD_PRE: 1158 case ARM::STRD_POST: 1159 case ARM::LDRD: 1160 case ARM::LDRD_PRE: 1161 case ARM::LDRD_POST: 1162 if (Rt & 0x1) return Fail; 1163 break; 1164 default: 1165 break; 1166 } 1167 1168 if (writeback) { // Writeback 1169 if (P) 1170 U |= ARMII::IndexModePre << 9; 1171 else 1172 U |= ARMII::IndexModePost << 9; 1173 1174 // On stores, the writeback operand precedes Rt. 1175 switch (Inst.getOpcode()) { 1176 case ARM::STRD: 1177 case ARM::STRD_PRE: 1178 case ARM::STRD_POST: 1179 case ARM::STRH: 1180 case ARM::STRH_PRE: 1181 case ARM::STRH_POST: 1182 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1183 break; 1184 default: 1185 break; 1186 } 1187 } 1188 1189 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1190 switch (Inst.getOpcode()) { 1191 case ARM::STRD: 1192 case ARM::STRD_PRE: 1193 case ARM::STRD_POST: 1194 case ARM::LDRD: 1195 case ARM::LDRD_PRE: 1196 case ARM::LDRD_POST: 1197 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 1198 break; 1199 default: 1200 break; 1201 } 1202 1203 if (writeback) { 1204 // On loads, the writeback operand comes after Rt. 1205 switch (Inst.getOpcode()) { 1206 case ARM::LDRD: 1207 case ARM::LDRD_PRE: 1208 case ARM::LDRD_POST: 1209 case ARM::LDRH: 1210 case ARM::LDRH_PRE: 1211 case ARM::LDRH_POST: 1212 case ARM::LDRSH: 1213 case ARM::LDRSH_PRE: 1214 case ARM::LDRSH_POST: 1215 case ARM::LDRSB: 1216 case ARM::LDRSB_PRE: 1217 case ARM::LDRSB_POST: 1218 case ARM::LDRHTr: 1219 case ARM::LDRSBTr: 1220 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1221 break; 1222 default: 1223 break; 1224 } 1225 } 1226 1227 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1228 1229 if (type) { 1230 Inst.addOperand(MCOperand::CreateReg(0)); 1231 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1232 } else { 1233 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1234 Inst.addOperand(MCOperand::CreateImm(U)); 1235 } 1236 1237 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1238 1239 return S; 1240 } 1241 1242 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1243 uint64_t Address, const void *Decoder) { 1244 DecodeStatus S = Success; 1245 1246 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1247 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1248 1249 switch (mode) { 1250 case 0: 1251 mode = ARM_AM::da; 1252 break; 1253 case 1: 1254 mode = ARM_AM::ia; 1255 break; 1256 case 2: 1257 mode = ARM_AM::db; 1258 break; 1259 case 3: 1260 mode = ARM_AM::ib; 1261 break; 1262 } 1263 1264 Inst.addOperand(MCOperand::CreateImm(mode)); 1265 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1266 1267 return S; 1268 } 1269 1270 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1271 unsigned Insn, 1272 uint64_t Address, const void *Decoder) { 1273 DecodeStatus S = Success; 1274 1275 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1276 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1277 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1278 1279 if (pred == 0xF) { 1280 switch (Inst.getOpcode()) { 1281 case ARM::LDMDA: 1282 Inst.setOpcode(ARM::RFEDA); 1283 break; 1284 case ARM::LDMDA_UPD: 1285 Inst.setOpcode(ARM::RFEDA_UPD); 1286 break; 1287 case ARM::LDMDB: 1288 Inst.setOpcode(ARM::RFEDB); 1289 break; 1290 case ARM::LDMDB_UPD: 1291 Inst.setOpcode(ARM::RFEDB_UPD); 1292 break; 1293 case ARM::LDMIA: 1294 Inst.setOpcode(ARM::RFEIA); 1295 break; 1296 case ARM::LDMIA_UPD: 1297 Inst.setOpcode(ARM::RFEIA_UPD); 1298 break; 1299 case ARM::LDMIB: 1300 Inst.setOpcode(ARM::RFEIB); 1301 break; 1302 case ARM::LDMIB_UPD: 1303 Inst.setOpcode(ARM::RFEIB_UPD); 1304 break; 1305 case ARM::STMDA: 1306 Inst.setOpcode(ARM::SRSDA); 1307 break; 1308 case ARM::STMDA_UPD: 1309 Inst.setOpcode(ARM::SRSDA_UPD); 1310 break; 1311 case ARM::STMDB: 1312 Inst.setOpcode(ARM::SRSDB); 1313 break; 1314 case ARM::STMDB_UPD: 1315 Inst.setOpcode(ARM::SRSDB_UPD); 1316 break; 1317 case ARM::STMIA: 1318 Inst.setOpcode(ARM::SRSIA); 1319 break; 1320 case ARM::STMIA_UPD: 1321 Inst.setOpcode(ARM::SRSIA_UPD); 1322 break; 1323 case ARM::STMIB: 1324 Inst.setOpcode(ARM::SRSIB); 1325 break; 1326 case ARM::STMIB_UPD: 1327 Inst.setOpcode(ARM::SRSIB_UPD); 1328 break; 1329 default: 1330 CHECK(S, Fail); 1331 } 1332 1333 // For stores (which become SRS's, the only operand is the mode. 1334 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1335 Inst.addOperand( 1336 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1337 return S; 1338 } 1339 1340 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1341 } 1342 1343 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1344 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied 1345 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1346 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); 1347 1348 return S; 1349 } 1350 1351 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1352 uint64_t Address, const void *Decoder) { 1353 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1354 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1355 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1356 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1357 1358 DecodeStatus S = Success; 1359 1360 // imod == '01' --> UNPREDICTABLE 1361 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1362 // return failure here. The '01' imod value is unprintable, so there's 1363 // nothing useful we could do even if we returned UNPREDICTABLE. 1364 1365 if (imod == 1) CHECK(S, Fail); 1366 1367 if (imod && M) { 1368 Inst.setOpcode(ARM::CPS3p); 1369 Inst.addOperand(MCOperand::CreateImm(imod)); 1370 Inst.addOperand(MCOperand::CreateImm(iflags)); 1371 Inst.addOperand(MCOperand::CreateImm(mode)); 1372 } else if (imod && !M) { 1373 Inst.setOpcode(ARM::CPS2p); 1374 Inst.addOperand(MCOperand::CreateImm(imod)); 1375 Inst.addOperand(MCOperand::CreateImm(iflags)); 1376 if (mode) CHECK(S, Unpredictable); 1377 } else if (!imod && M) { 1378 Inst.setOpcode(ARM::CPS1p); 1379 Inst.addOperand(MCOperand::CreateImm(mode)); 1380 if (iflags) CHECK(S, Unpredictable); 1381 } else { 1382 // imod == '00' && M == '0' --> UNPREDICTABLE 1383 Inst.setOpcode(ARM::CPS1p); 1384 Inst.addOperand(MCOperand::CreateImm(mode)); 1385 CHECK(S, Unpredictable); 1386 } 1387 1388 return S; 1389 } 1390 1391 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1392 uint64_t Address, const void *Decoder) { 1393 DecodeStatus S = Success; 1394 1395 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1396 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1397 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1398 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1399 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1400 1401 if (pred == 0xF) 1402 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1403 1404 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); 1405 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); 1406 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1407 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); 1408 1409 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1410 1411 return S; 1412 } 1413 1414 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1415 uint64_t Address, const void *Decoder) { 1416 DecodeStatus S = Success; 1417 1418 unsigned add = fieldFromInstruction32(Val, 12, 1); 1419 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1420 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1421 1422 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1423 1424 if (!add) imm *= -1; 1425 if (imm == 0 && !add) imm = INT32_MIN; 1426 Inst.addOperand(MCOperand::CreateImm(imm)); 1427 1428 return S; 1429 } 1430 1431 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1432 uint64_t Address, const void *Decoder) { 1433 DecodeStatus S = Success; 1434 1435 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1436 unsigned U = fieldFromInstruction32(Val, 8, 1); 1437 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1438 1439 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1440 1441 if (U) 1442 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1443 else 1444 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1445 1446 return S; 1447 } 1448 1449 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1450 uint64_t Address, const void *Decoder) { 1451 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1452 } 1453 1454 static DecodeStatus 1455 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1456 uint64_t Address, const void *Decoder) { 1457 DecodeStatus S = Success; 1458 1459 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1460 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1461 1462 if (pred == 0xF) { 1463 Inst.setOpcode(ARM::BLXi); 1464 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1465 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1466 return S; 1467 } 1468 1469 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1470 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1471 1472 return S; 1473 } 1474 1475 1476 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1477 uint64_t Address, const void *Decoder) { 1478 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1479 return Success; 1480 } 1481 1482 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1483 uint64_t Address, const void *Decoder) { 1484 DecodeStatus S = Success; 1485 1486 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1487 unsigned align = fieldFromInstruction32(Val, 4, 2); 1488 1489 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1490 if (!align) 1491 Inst.addOperand(MCOperand::CreateImm(0)); 1492 else 1493 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1494 1495 return S; 1496 } 1497 1498 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1499 uint64_t Address, const void *Decoder) { 1500 DecodeStatus S = Success; 1501 1502 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1503 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1504 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1505 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1506 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1507 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1508 1509 // First output register 1510 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1511 1512 // Second output register 1513 switch (Inst.getOpcode()) { 1514 case ARM::VLD1q8: 1515 case ARM::VLD1q16: 1516 case ARM::VLD1q32: 1517 case ARM::VLD1q64: 1518 case ARM::VLD1q8_UPD: 1519 case ARM::VLD1q16_UPD: 1520 case ARM::VLD1q32_UPD: 1521 case ARM::VLD1q64_UPD: 1522 case ARM::VLD1d8T: 1523 case ARM::VLD1d16T: 1524 case ARM::VLD1d32T: 1525 case ARM::VLD1d64T: 1526 case ARM::VLD1d8T_UPD: 1527 case ARM::VLD1d16T_UPD: 1528 case ARM::VLD1d32T_UPD: 1529 case ARM::VLD1d64T_UPD: 1530 case ARM::VLD1d8Q: 1531 case ARM::VLD1d16Q: 1532 case ARM::VLD1d32Q: 1533 case ARM::VLD1d64Q: 1534 case ARM::VLD1d8Q_UPD: 1535 case ARM::VLD1d16Q_UPD: 1536 case ARM::VLD1d32Q_UPD: 1537 case ARM::VLD1d64Q_UPD: 1538 case ARM::VLD2d8: 1539 case ARM::VLD2d16: 1540 case ARM::VLD2d32: 1541 case ARM::VLD2d8_UPD: 1542 case ARM::VLD2d16_UPD: 1543 case ARM::VLD2d32_UPD: 1544 case ARM::VLD2q8: 1545 case ARM::VLD2q16: 1546 case ARM::VLD2q32: 1547 case ARM::VLD2q8_UPD: 1548 case ARM::VLD2q16_UPD: 1549 case ARM::VLD2q32_UPD: 1550 case ARM::VLD3d8: 1551 case ARM::VLD3d16: 1552 case ARM::VLD3d32: 1553 case ARM::VLD3d8_UPD: 1554 case ARM::VLD3d16_UPD: 1555 case ARM::VLD3d32_UPD: 1556 case ARM::VLD4d8: 1557 case ARM::VLD4d16: 1558 case ARM::VLD4d32: 1559 case ARM::VLD4d8_UPD: 1560 case ARM::VLD4d16_UPD: 1561 case ARM::VLD4d32_UPD: 1562 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1563 break; 1564 case ARM::VLD2b8: 1565 case ARM::VLD2b16: 1566 case ARM::VLD2b32: 1567 case ARM::VLD2b8_UPD: 1568 case ARM::VLD2b16_UPD: 1569 case ARM::VLD2b32_UPD: 1570 case ARM::VLD3q8: 1571 case ARM::VLD3q16: 1572 case ARM::VLD3q32: 1573 case ARM::VLD3q8_UPD: 1574 case ARM::VLD3q16_UPD: 1575 case ARM::VLD3q32_UPD: 1576 case ARM::VLD4q8: 1577 case ARM::VLD4q16: 1578 case ARM::VLD4q32: 1579 case ARM::VLD4q8_UPD: 1580 case ARM::VLD4q16_UPD: 1581 case ARM::VLD4q32_UPD: 1582 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1583 default: 1584 break; 1585 } 1586 1587 // Third output register 1588 switch(Inst.getOpcode()) { 1589 case ARM::VLD1d8T: 1590 case ARM::VLD1d16T: 1591 case ARM::VLD1d32T: 1592 case ARM::VLD1d64T: 1593 case ARM::VLD1d8T_UPD: 1594 case ARM::VLD1d16T_UPD: 1595 case ARM::VLD1d32T_UPD: 1596 case ARM::VLD1d64T_UPD: 1597 case ARM::VLD1d8Q: 1598 case ARM::VLD1d16Q: 1599 case ARM::VLD1d32Q: 1600 case ARM::VLD1d64Q: 1601 case ARM::VLD1d8Q_UPD: 1602 case ARM::VLD1d16Q_UPD: 1603 case ARM::VLD1d32Q_UPD: 1604 case ARM::VLD1d64Q_UPD: 1605 case ARM::VLD2q8: 1606 case ARM::VLD2q16: 1607 case ARM::VLD2q32: 1608 case ARM::VLD2q8_UPD: 1609 case ARM::VLD2q16_UPD: 1610 case ARM::VLD2q32_UPD: 1611 case ARM::VLD3d8: 1612 case ARM::VLD3d16: 1613 case ARM::VLD3d32: 1614 case ARM::VLD3d8_UPD: 1615 case ARM::VLD3d16_UPD: 1616 case ARM::VLD3d32_UPD: 1617 case ARM::VLD4d8: 1618 case ARM::VLD4d16: 1619 case ARM::VLD4d32: 1620 case ARM::VLD4d8_UPD: 1621 case ARM::VLD4d16_UPD: 1622 case ARM::VLD4d32_UPD: 1623 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1624 break; 1625 case ARM::VLD3q8: 1626 case ARM::VLD3q16: 1627 case ARM::VLD3q32: 1628 case ARM::VLD3q8_UPD: 1629 case ARM::VLD3q16_UPD: 1630 case ARM::VLD3q32_UPD: 1631 case ARM::VLD4q8: 1632 case ARM::VLD4q16: 1633 case ARM::VLD4q32: 1634 case ARM::VLD4q8_UPD: 1635 case ARM::VLD4q16_UPD: 1636 case ARM::VLD4q32_UPD: 1637 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1638 break; 1639 default: 1640 break; 1641 } 1642 1643 // Fourth output register 1644 switch (Inst.getOpcode()) { 1645 case ARM::VLD1d8Q: 1646 case ARM::VLD1d16Q: 1647 case ARM::VLD1d32Q: 1648 case ARM::VLD1d64Q: 1649 case ARM::VLD1d8Q_UPD: 1650 case ARM::VLD1d16Q_UPD: 1651 case ARM::VLD1d32Q_UPD: 1652 case ARM::VLD1d64Q_UPD: 1653 case ARM::VLD2q8: 1654 case ARM::VLD2q16: 1655 case ARM::VLD2q32: 1656 case ARM::VLD2q8_UPD: 1657 case ARM::VLD2q16_UPD: 1658 case ARM::VLD2q32_UPD: 1659 case ARM::VLD4d8: 1660 case ARM::VLD4d16: 1661 case ARM::VLD4d32: 1662 case ARM::VLD4d8_UPD: 1663 case ARM::VLD4d16_UPD: 1664 case ARM::VLD4d32_UPD: 1665 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1666 break; 1667 case ARM::VLD4q8: 1668 case ARM::VLD4q16: 1669 case ARM::VLD4q32: 1670 case ARM::VLD4q8_UPD: 1671 case ARM::VLD4q16_UPD: 1672 case ARM::VLD4q32_UPD: 1673 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1674 break; 1675 default: 1676 break; 1677 } 1678 1679 // Writeback operand 1680 switch (Inst.getOpcode()) { 1681 case ARM::VLD1d8_UPD: 1682 case ARM::VLD1d16_UPD: 1683 case ARM::VLD1d32_UPD: 1684 case ARM::VLD1d64_UPD: 1685 case ARM::VLD1q8_UPD: 1686 case ARM::VLD1q16_UPD: 1687 case ARM::VLD1q32_UPD: 1688 case ARM::VLD1q64_UPD: 1689 case ARM::VLD1d8T_UPD: 1690 case ARM::VLD1d16T_UPD: 1691 case ARM::VLD1d32T_UPD: 1692 case ARM::VLD1d64T_UPD: 1693 case ARM::VLD1d8Q_UPD: 1694 case ARM::VLD1d16Q_UPD: 1695 case ARM::VLD1d32Q_UPD: 1696 case ARM::VLD1d64Q_UPD: 1697 case ARM::VLD2d8_UPD: 1698 case ARM::VLD2d16_UPD: 1699 case ARM::VLD2d32_UPD: 1700 case ARM::VLD2q8_UPD: 1701 case ARM::VLD2q16_UPD: 1702 case ARM::VLD2q32_UPD: 1703 case ARM::VLD2b8_UPD: 1704 case ARM::VLD2b16_UPD: 1705 case ARM::VLD2b32_UPD: 1706 case ARM::VLD3d8_UPD: 1707 case ARM::VLD3d16_UPD: 1708 case ARM::VLD3d32_UPD: 1709 case ARM::VLD3q8_UPD: 1710 case ARM::VLD3q16_UPD: 1711 case ARM::VLD3q32_UPD: 1712 case ARM::VLD4d8_UPD: 1713 case ARM::VLD4d16_UPD: 1714 case ARM::VLD4d32_UPD: 1715 case ARM::VLD4q8_UPD: 1716 case ARM::VLD4q16_UPD: 1717 case ARM::VLD4q32_UPD: 1718 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1719 break; 1720 default: 1721 break; 1722 } 1723 1724 // AddrMode6 Base (register+alignment) 1725 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1726 1727 // AddrMode6 Offset (register) 1728 if (Rm == 0xD) 1729 Inst.addOperand(MCOperand::CreateReg(0)); 1730 else if (Rm != 0xF) { 1731 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1732 } 1733 1734 return S; 1735 } 1736 1737 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1738 uint64_t Address, const void *Decoder) { 1739 DecodeStatus S = Success; 1740 1741 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1742 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1743 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1744 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1745 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1746 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1747 1748 // Writeback Operand 1749 switch (Inst.getOpcode()) { 1750 case ARM::VST1d8_UPD: 1751 case ARM::VST1d16_UPD: 1752 case ARM::VST1d32_UPD: 1753 case ARM::VST1d64_UPD: 1754 case ARM::VST1q8_UPD: 1755 case ARM::VST1q16_UPD: 1756 case ARM::VST1q32_UPD: 1757 case ARM::VST1q64_UPD: 1758 case ARM::VST1d8T_UPD: 1759 case ARM::VST1d16T_UPD: 1760 case ARM::VST1d32T_UPD: 1761 case ARM::VST1d64T_UPD: 1762 case ARM::VST1d8Q_UPD: 1763 case ARM::VST1d16Q_UPD: 1764 case ARM::VST1d32Q_UPD: 1765 case ARM::VST1d64Q_UPD: 1766 case ARM::VST2d8_UPD: 1767 case ARM::VST2d16_UPD: 1768 case ARM::VST2d32_UPD: 1769 case ARM::VST2q8_UPD: 1770 case ARM::VST2q16_UPD: 1771 case ARM::VST2q32_UPD: 1772 case ARM::VST2b8_UPD: 1773 case ARM::VST2b16_UPD: 1774 case ARM::VST2b32_UPD: 1775 case ARM::VST3d8_UPD: 1776 case ARM::VST3d16_UPD: 1777 case ARM::VST3d32_UPD: 1778 case ARM::VST3q8_UPD: 1779 case ARM::VST3q16_UPD: 1780 case ARM::VST3q32_UPD: 1781 case ARM::VST4d8_UPD: 1782 case ARM::VST4d16_UPD: 1783 case ARM::VST4d32_UPD: 1784 case ARM::VST4q8_UPD: 1785 case ARM::VST4q16_UPD: 1786 case ARM::VST4q32_UPD: 1787 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1788 break; 1789 default: 1790 break; 1791 } 1792 1793 // AddrMode6 Base (register+alignment) 1794 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1795 1796 // AddrMode6 Offset (register) 1797 if (Rm == 0xD) 1798 Inst.addOperand(MCOperand::CreateReg(0)); 1799 else if (Rm != 0xF) { 1800 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1801 } 1802 1803 // First input register 1804 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1805 1806 // Second input register 1807 switch (Inst.getOpcode()) { 1808 case ARM::VST1q8: 1809 case ARM::VST1q16: 1810 case ARM::VST1q32: 1811 case ARM::VST1q64: 1812 case ARM::VST1q8_UPD: 1813 case ARM::VST1q16_UPD: 1814 case ARM::VST1q32_UPD: 1815 case ARM::VST1q64_UPD: 1816 case ARM::VST1d8T: 1817 case ARM::VST1d16T: 1818 case ARM::VST1d32T: 1819 case ARM::VST1d64T: 1820 case ARM::VST1d8T_UPD: 1821 case ARM::VST1d16T_UPD: 1822 case ARM::VST1d32T_UPD: 1823 case ARM::VST1d64T_UPD: 1824 case ARM::VST1d8Q: 1825 case ARM::VST1d16Q: 1826 case ARM::VST1d32Q: 1827 case ARM::VST1d64Q: 1828 case ARM::VST1d8Q_UPD: 1829 case ARM::VST1d16Q_UPD: 1830 case ARM::VST1d32Q_UPD: 1831 case ARM::VST1d64Q_UPD: 1832 case ARM::VST2d8: 1833 case ARM::VST2d16: 1834 case ARM::VST2d32: 1835 case ARM::VST2d8_UPD: 1836 case ARM::VST2d16_UPD: 1837 case ARM::VST2d32_UPD: 1838 case ARM::VST2q8: 1839 case ARM::VST2q16: 1840 case ARM::VST2q32: 1841 case ARM::VST2q8_UPD: 1842 case ARM::VST2q16_UPD: 1843 case ARM::VST2q32_UPD: 1844 case ARM::VST3d8: 1845 case ARM::VST3d16: 1846 case ARM::VST3d32: 1847 case ARM::VST3d8_UPD: 1848 case ARM::VST3d16_UPD: 1849 case ARM::VST3d32_UPD: 1850 case ARM::VST4d8: 1851 case ARM::VST4d16: 1852 case ARM::VST4d32: 1853 case ARM::VST4d8_UPD: 1854 case ARM::VST4d16_UPD: 1855 case ARM::VST4d32_UPD: 1856 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1857 break; 1858 case ARM::VST2b8: 1859 case ARM::VST2b16: 1860 case ARM::VST2b32: 1861 case ARM::VST2b8_UPD: 1862 case ARM::VST2b16_UPD: 1863 case ARM::VST2b32_UPD: 1864 case ARM::VST3q8: 1865 case ARM::VST3q16: 1866 case ARM::VST3q32: 1867 case ARM::VST3q8_UPD: 1868 case ARM::VST3q16_UPD: 1869 case ARM::VST3q32_UPD: 1870 case ARM::VST4q8: 1871 case ARM::VST4q16: 1872 case ARM::VST4q32: 1873 case ARM::VST4q8_UPD: 1874 case ARM::VST4q16_UPD: 1875 case ARM::VST4q32_UPD: 1876 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1877 break; 1878 default: 1879 break; 1880 } 1881 1882 // Third input register 1883 switch (Inst.getOpcode()) { 1884 case ARM::VST1d8T: 1885 case ARM::VST1d16T: 1886 case ARM::VST1d32T: 1887 case ARM::VST1d64T: 1888 case ARM::VST1d8T_UPD: 1889 case ARM::VST1d16T_UPD: 1890 case ARM::VST1d32T_UPD: 1891 case ARM::VST1d64T_UPD: 1892 case ARM::VST1d8Q: 1893 case ARM::VST1d16Q: 1894 case ARM::VST1d32Q: 1895 case ARM::VST1d64Q: 1896 case ARM::VST1d8Q_UPD: 1897 case ARM::VST1d16Q_UPD: 1898 case ARM::VST1d32Q_UPD: 1899 case ARM::VST1d64Q_UPD: 1900 case ARM::VST2q8: 1901 case ARM::VST2q16: 1902 case ARM::VST2q32: 1903 case ARM::VST2q8_UPD: 1904 case ARM::VST2q16_UPD: 1905 case ARM::VST2q32_UPD: 1906 case ARM::VST3d8: 1907 case ARM::VST3d16: 1908 case ARM::VST3d32: 1909 case ARM::VST3d8_UPD: 1910 case ARM::VST3d16_UPD: 1911 case ARM::VST3d32_UPD: 1912 case ARM::VST4d8: 1913 case ARM::VST4d16: 1914 case ARM::VST4d32: 1915 case ARM::VST4d8_UPD: 1916 case ARM::VST4d16_UPD: 1917 case ARM::VST4d32_UPD: 1918 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1919 break; 1920 case ARM::VST3q8: 1921 case ARM::VST3q16: 1922 case ARM::VST3q32: 1923 case ARM::VST3q8_UPD: 1924 case ARM::VST3q16_UPD: 1925 case ARM::VST3q32_UPD: 1926 case ARM::VST4q8: 1927 case ARM::VST4q16: 1928 case ARM::VST4q32: 1929 case ARM::VST4q8_UPD: 1930 case ARM::VST4q16_UPD: 1931 case ARM::VST4q32_UPD: 1932 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1933 break; 1934 default: 1935 break; 1936 } 1937 1938 // Fourth input register 1939 switch (Inst.getOpcode()) { 1940 case ARM::VST1d8Q: 1941 case ARM::VST1d16Q: 1942 case ARM::VST1d32Q: 1943 case ARM::VST1d64Q: 1944 case ARM::VST1d8Q_UPD: 1945 case ARM::VST1d16Q_UPD: 1946 case ARM::VST1d32Q_UPD: 1947 case ARM::VST1d64Q_UPD: 1948 case ARM::VST2q8: 1949 case ARM::VST2q16: 1950 case ARM::VST2q32: 1951 case ARM::VST2q8_UPD: 1952 case ARM::VST2q16_UPD: 1953 case ARM::VST2q32_UPD: 1954 case ARM::VST4d8: 1955 case ARM::VST4d16: 1956 case ARM::VST4d32: 1957 case ARM::VST4d8_UPD: 1958 case ARM::VST4d16_UPD: 1959 case ARM::VST4d32_UPD: 1960 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1961 break; 1962 case ARM::VST4q8: 1963 case ARM::VST4q16: 1964 case ARM::VST4q32: 1965 case ARM::VST4q8_UPD: 1966 case ARM::VST4q16_UPD: 1967 case ARM::VST4q32_UPD: 1968 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1969 break; 1970 default: 1971 break; 1972 } 1973 1974 return S; 1975 } 1976 1977 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1978 uint64_t Address, const void *Decoder) { 1979 DecodeStatus S = Success; 1980 1981 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1982 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1983 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1984 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1985 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1986 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1987 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1988 1989 align *= (1 << size); 1990 1991 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1992 if (regs == 2) { 1993 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1994 } 1995 if (Rm != 0xF) { 1996 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1997 } 1998 1999 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2000 Inst.addOperand(MCOperand::CreateImm(align)); 2001 2002 if (Rm == 0xD) 2003 Inst.addOperand(MCOperand::CreateReg(0)); 2004 else if (Rm != 0xF) { 2005 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2006 } 2007 2008 return S; 2009 } 2010 2011 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2012 uint64_t Address, const void *Decoder) { 2013 DecodeStatus S = Success; 2014 2015 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2016 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2017 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2018 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2019 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2020 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2021 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2022 align *= 2*size; 2023 2024 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2025 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2026 if (Rm != 0xF) { 2027 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2028 } 2029 2030 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2031 Inst.addOperand(MCOperand::CreateImm(align)); 2032 2033 if (Rm == 0xD) 2034 Inst.addOperand(MCOperand::CreateReg(0)); 2035 else if (Rm != 0xF) { 2036 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2037 } 2038 2039 return S; 2040 } 2041 2042 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2043 uint64_t Address, const void *Decoder) { 2044 DecodeStatus S = Success; 2045 2046 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2047 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2048 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2049 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2050 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2051 2052 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2053 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2054 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2055 if (Rm != 0xF) { 2056 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2057 } 2058 2059 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2060 Inst.addOperand(MCOperand::CreateImm(0)); 2061 2062 if (Rm == 0xD) 2063 Inst.addOperand(MCOperand::CreateReg(0)); 2064 else if (Rm != 0xF) { 2065 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2066 } 2067 2068 return S; 2069 } 2070 2071 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2072 uint64_t Address, const void *Decoder) { 2073 DecodeStatus S = Success; 2074 2075 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2076 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2077 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2078 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2079 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2080 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2081 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2082 2083 if (size == 0x3) { 2084 size = 4; 2085 align = 16; 2086 } else { 2087 if (size == 2) { 2088 size = 1 << size; 2089 align *= 8; 2090 } else { 2091 size = 1 << size; 2092 align *= 4*size; 2093 } 2094 } 2095 2096 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2097 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2098 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2099 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); 2100 if (Rm != 0xF) { 2101 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2102 } 2103 2104 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2105 Inst.addOperand(MCOperand::CreateImm(align)); 2106 2107 if (Rm == 0xD) 2108 Inst.addOperand(MCOperand::CreateReg(0)); 2109 else if (Rm != 0xF) { 2110 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2111 } 2112 2113 return S; 2114 } 2115 2116 static DecodeStatus 2117 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2118 uint64_t Address, const void *Decoder) { 2119 DecodeStatus S = Success; 2120 2121 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2122 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2123 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2124 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2125 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2126 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2127 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2128 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2129 2130 if (Q) { 2131 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2132 } else { 2133 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2134 } 2135 2136 Inst.addOperand(MCOperand::CreateImm(imm)); 2137 2138 switch (Inst.getOpcode()) { 2139 case ARM::VORRiv4i16: 2140 case ARM::VORRiv2i32: 2141 case ARM::VBICiv4i16: 2142 case ARM::VBICiv2i32: 2143 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2144 break; 2145 case ARM::VORRiv8i16: 2146 case ARM::VORRiv4i32: 2147 case ARM::VBICiv8i16: 2148 case ARM::VBICiv4i32: 2149 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2150 break; 2151 default: 2152 break; 2153 } 2154 2155 return S; 2156 } 2157 2158 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2159 uint64_t Address, const void *Decoder) { 2160 DecodeStatus S = Success; 2161 2162 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2163 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2164 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2165 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2166 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2167 2168 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2169 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2170 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2171 2172 return S; 2173 } 2174 2175 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2176 uint64_t Address, const void *Decoder) { 2177 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2178 return Success; 2179 } 2180 2181 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2182 uint64_t Address, const void *Decoder) { 2183 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2184 return Success; 2185 } 2186 2187 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2188 uint64_t Address, const void *Decoder) { 2189 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2190 return Success; 2191 } 2192 2193 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2194 uint64_t Address, const void *Decoder) { 2195 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2196 return Success; 2197 } 2198 2199 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2200 uint64_t Address, const void *Decoder) { 2201 DecodeStatus S = Success; 2202 2203 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2204 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2205 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2206 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2207 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2208 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2209 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2210 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2211 2212 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2213 if (op) { 2214 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback 2215 } 2216 2217 for (unsigned i = 0; i < length; ++i) { 2218 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)); 2219 } 2220 2221 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2222 2223 return S; 2224 } 2225 2226 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2227 uint64_t Address, const void *Decoder) { 2228 // The immediate needs to be a fully instantiated float. However, the 2229 // auto-generated decoder is only able to fill in some of the bits 2230 // necessary. For instance, the 'b' bit is replicated multiple times, 2231 // and is even present in inverted form in one bit. We do a little 2232 // binary parsing here to fill in those missing bits, and then 2233 // reinterpret it all as a float. 2234 union { 2235 uint32_t integer; 2236 float fp; 2237 } fp_conv; 2238 2239 fp_conv.integer = Val; 2240 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2241 fp_conv.integer |= b << 26; 2242 fp_conv.integer |= b << 27; 2243 fp_conv.integer |= b << 28; 2244 fp_conv.integer |= b << 29; 2245 fp_conv.integer |= (~b & 0x1) << 30; 2246 2247 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2248 return Success; 2249 } 2250 2251 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2252 uint64_t Address, const void *Decoder) { 2253 DecodeStatus S = Success; 2254 2255 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2256 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2257 2258 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); 2259 2260 if (Inst.getOpcode() == ARM::tADR) 2261 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2262 else if (Inst.getOpcode() == ARM::tADDrSPi) 2263 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2264 else 2265 return Fail; 2266 2267 Inst.addOperand(MCOperand::CreateImm(imm)); 2268 return S; 2269 } 2270 2271 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2272 uint64_t Address, const void *Decoder) { 2273 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2274 return Success; 2275 } 2276 2277 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2278 uint64_t Address, const void *Decoder) { 2279 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2280 return Success; 2281 } 2282 2283 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2284 uint64_t Address, const void *Decoder) { 2285 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2286 return Success; 2287 } 2288 2289 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2290 uint64_t Address, const void *Decoder) { 2291 DecodeStatus S = Success; 2292 2293 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2294 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2295 2296 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2297 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); 2298 2299 return S; 2300 } 2301 2302 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2303 uint64_t Address, const void *Decoder) { 2304 DecodeStatus S = Success; 2305 2306 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2307 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2308 2309 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2310 Inst.addOperand(MCOperand::CreateImm(imm)); 2311 2312 return S; 2313 } 2314 2315 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2316 uint64_t Address, const void *Decoder) { 2317 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2318 2319 return Success; 2320 } 2321 2322 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2323 uint64_t Address, const void *Decoder) { 2324 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2325 Inst.addOperand(MCOperand::CreateImm(Val)); 2326 2327 return Success; 2328 } 2329 2330 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2331 uint64_t Address, const void *Decoder) { 2332 DecodeStatus S = Success; 2333 2334 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2335 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2336 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2337 2338 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2339 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); 2340 Inst.addOperand(MCOperand::CreateImm(imm)); 2341 2342 return S; 2343 } 2344 2345 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2346 uint64_t Address, const void *Decoder) { 2347 DecodeStatus S = Success; 2348 2349 if (Inst.getOpcode() != ARM::t2PLDs) { 2350 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2351 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2352 } 2353 2354 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2355 if (Rn == 0xF) { 2356 switch (Inst.getOpcode()) { 2357 case ARM::t2LDRBs: 2358 Inst.setOpcode(ARM::t2LDRBpci); 2359 break; 2360 case ARM::t2LDRHs: 2361 Inst.setOpcode(ARM::t2LDRHpci); 2362 break; 2363 case ARM::t2LDRSHs: 2364 Inst.setOpcode(ARM::t2LDRSHpci); 2365 break; 2366 case ARM::t2LDRSBs: 2367 Inst.setOpcode(ARM::t2LDRSBpci); 2368 break; 2369 case ARM::t2PLDs: 2370 Inst.setOpcode(ARM::t2PLDi12); 2371 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2372 break; 2373 default: 2374 return Fail; 2375 } 2376 2377 int imm = fieldFromInstruction32(Insn, 0, 12); 2378 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2379 Inst.addOperand(MCOperand::CreateImm(imm)); 2380 2381 return S; 2382 } 2383 2384 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2385 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2386 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2387 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); 2388 2389 return S; 2390 } 2391 2392 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2393 uint64_t Address, const void *Decoder) { 2394 int imm = Val & 0xFF; 2395 if (!(Val & 0x100)) imm *= -1; 2396 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2397 2398 return Success; 2399 } 2400 2401 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2402 uint64_t Address, const void *Decoder) { 2403 DecodeStatus S = Success; 2404 2405 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2406 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2407 2408 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2409 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); 2410 2411 return S; 2412 } 2413 2414 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2415 uint64_t Address, const void *Decoder) { 2416 int imm = Val & 0xFF; 2417 if (!(Val & 0x100)) imm *= -1; 2418 Inst.addOperand(MCOperand::CreateImm(imm)); 2419 2420 return Success; 2421 } 2422 2423 2424 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2425 uint64_t Address, const void *Decoder) { 2426 DecodeStatus S = Success; 2427 2428 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2429 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2430 2431 // Some instructions always use an additive offset. 2432 switch (Inst.getOpcode()) { 2433 case ARM::t2LDRT: 2434 case ARM::t2LDRBT: 2435 case ARM::t2LDRHT: 2436 case ARM::t2LDRSBT: 2437 case ARM::t2LDRSHT: 2438 imm |= 0x100; 2439 break; 2440 default: 2441 break; 2442 } 2443 2444 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2445 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); 2446 2447 return S; 2448 } 2449 2450 2451 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2452 uint64_t Address, const void *Decoder) { 2453 DecodeStatus S = Success; 2454 2455 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2456 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2457 2458 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2459 Inst.addOperand(MCOperand::CreateImm(imm)); 2460 2461 return S; 2462 } 2463 2464 2465 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2466 uint64_t Address, const void *Decoder) { 2467 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2468 2469 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2470 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2471 Inst.addOperand(MCOperand::CreateImm(imm)); 2472 2473 return Success; 2474 } 2475 2476 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2477 uint64_t Address, const void *Decoder) { 2478 DecodeStatus S = Success; 2479 2480 if (Inst.getOpcode() == ARM::tADDrSP) { 2481 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2482 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2483 2484 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2485 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2486 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2487 } else if (Inst.getOpcode() == ARM::tADDspr) { 2488 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2489 2490 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2491 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2492 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2493 } 2494 2495 return S; 2496 } 2497 2498 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2499 uint64_t Address, const void *Decoder) { 2500 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2501 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2502 2503 Inst.addOperand(MCOperand::CreateImm(imod)); 2504 Inst.addOperand(MCOperand::CreateImm(flags)); 2505 2506 return Success; 2507 } 2508 2509 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2510 uint64_t Address, const void *Decoder) { 2511 DecodeStatus S = Success; 2512 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2513 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2514 2515 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; 2516 Inst.addOperand(MCOperand::CreateImm(add)); 2517 2518 return S; 2519 } 2520 2521 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2522 uint64_t Address, const void *Decoder) { 2523 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2524 return Success; 2525 } 2526 2527 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2528 uint64_t Address, const void *Decoder) { 2529 if (Val == 0xA || Val == 0xB) 2530 return Fail; 2531 2532 Inst.addOperand(MCOperand::CreateImm(Val)); 2533 return Success; 2534 } 2535 2536 static DecodeStatus 2537 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2538 uint64_t Address, const void *Decoder) { 2539 DecodeStatus S = Success; 2540 2541 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2542 if (pred == 0xE || pred == 0xF) { 2543 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2544 switch (opc) { 2545 default: 2546 return Fail; 2547 case 0: 2548 Inst.setOpcode(ARM::t2DSB); 2549 break; 2550 case 1: 2551 Inst.setOpcode(ARM::t2DMB); 2552 break; 2553 case 2: 2554 Inst.setOpcode(ARM::t2ISB); 2555 return Success; 2556 } 2557 2558 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2559 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2560 } 2561 2562 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2563 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2564 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2565 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2566 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2567 2568 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); 2569 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2570 2571 return S; 2572 } 2573 2574 // Decode a shifted immediate operand. These basically consist 2575 // of an 8-bit value, and a 4-bit directive that specifies either 2576 // a splat operation or a rotation. 2577 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2578 uint64_t Address, const void *Decoder) { 2579 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2580 if (ctrl == 0) { 2581 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2582 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2583 switch (byte) { 2584 case 0: 2585 Inst.addOperand(MCOperand::CreateImm(imm)); 2586 break; 2587 case 1: 2588 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2589 break; 2590 case 2: 2591 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2592 break; 2593 case 3: 2594 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2595 (imm << 8) | imm)); 2596 break; 2597 } 2598 } else { 2599 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2600 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2601 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2602 Inst.addOperand(MCOperand::CreateImm(imm)); 2603 } 2604 2605 return Success; 2606 } 2607 2608 static DecodeStatus 2609 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2610 uint64_t Address, const void *Decoder){ 2611 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2612 return Success; 2613 } 2614 2615 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2616 uint64_t Address, const void *Decoder){ 2617 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2618 return Success; 2619 } 2620 2621 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2622 uint64_t Address, const void *Decoder) { 2623 switch (Val) { 2624 default: 2625 return Fail; 2626 case 0xF: // SY 2627 case 0xE: // ST 2628 case 0xB: // ISH 2629 case 0xA: // ISHST 2630 case 0x7: // NSH 2631 case 0x6: // NSHST 2632 case 0x3: // OSH 2633 case 0x2: // OSHST 2634 break; 2635 } 2636 2637 Inst.addOperand(MCOperand::CreateImm(Val)); 2638 return Success; 2639 } 2640 2641 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2642 uint64_t Address, const void *Decoder) { 2643 if (!Val) return Fail; 2644 Inst.addOperand(MCOperand::CreateImm(Val)); 2645 return Success; 2646 } 2647 2648 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2649 uint64_t Address, const void *Decoder) { 2650 DecodeStatus S = Success; 2651 2652 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2653 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2654 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2655 2656 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2657 2658 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2659 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2660 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2661 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2662 2663 return S; 2664 } 2665 2666 2667 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2668 uint64_t Address, const void *Decoder){ 2669 DecodeStatus S = Success; 2670 2671 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2672 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2673 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2674 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2675 2676 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); 2677 2678 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2679 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; 2680 2681 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2682 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2683 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2684 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2685 2686 return S; 2687 } 2688 2689 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2690 uint64_t Address, const void *Decoder) { 2691 DecodeStatus S = Success; 2692 2693 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2694 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2695 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2696 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2697 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2698 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2699 2700 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2701 2702 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2703 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2704 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); 2705 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2706 2707 return S; 2708 } 2709 2710 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2711 uint64_t Address, const void *Decoder) { 2712 DecodeStatus S = Success; 2713 2714 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2715 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2716 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2717 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2718 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2719 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2720 2721 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2722 2723 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2724 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2725 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); 2726 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2727 2728 return S; 2729 } 2730 2731 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2732 uint64_t Address, const void *Decoder) { 2733 DecodeStatus S = Success; 2734 2735 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2736 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2737 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2738 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2739 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2740 2741 unsigned align = 0; 2742 unsigned index = 0; 2743 switch (size) { 2744 default: 2745 return Fail; 2746 case 0: 2747 if (fieldFromInstruction32(Insn, 4, 1)) 2748 return Fail; // UNDEFINED 2749 index = fieldFromInstruction32(Insn, 5, 3); 2750 break; 2751 case 1: 2752 if (fieldFromInstruction32(Insn, 5, 1)) 2753 return Fail; // UNDEFINED 2754 index = fieldFromInstruction32(Insn, 6, 2); 2755 if (fieldFromInstruction32(Insn, 4, 1)) 2756 align = 2; 2757 break; 2758 case 2: 2759 if (fieldFromInstruction32(Insn, 6, 1)) 2760 return Fail; // UNDEFINED 2761 index = fieldFromInstruction32(Insn, 7, 1); 2762 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2763 align = 4; 2764 } 2765 2766 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2767 if (Rm != 0xF) { // Writeback 2768 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2769 } 2770 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2771 Inst.addOperand(MCOperand::CreateImm(align)); 2772 if (Rm != 0xF && Rm != 0xD) { 2773 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2774 } 2775 2776 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2777 Inst.addOperand(MCOperand::CreateImm(index)); 2778 2779 return S; 2780 } 2781 2782 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2783 uint64_t Address, const void *Decoder) { 2784 DecodeStatus S = Success; 2785 2786 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2787 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2788 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2789 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2790 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2791 2792 unsigned align = 0; 2793 unsigned index = 0; 2794 switch (size) { 2795 default: 2796 return Fail; 2797 case 0: 2798 if (fieldFromInstruction32(Insn, 4, 1)) 2799 return Fail; // UNDEFINED 2800 index = fieldFromInstruction32(Insn, 5, 3); 2801 break; 2802 case 1: 2803 if (fieldFromInstruction32(Insn, 5, 1)) 2804 return Fail; // UNDEFINED 2805 index = fieldFromInstruction32(Insn, 6, 2); 2806 if (fieldFromInstruction32(Insn, 4, 1)) 2807 align = 2; 2808 break; 2809 case 2: 2810 if (fieldFromInstruction32(Insn, 6, 1)) 2811 return Fail; // UNDEFINED 2812 index = fieldFromInstruction32(Insn, 7, 1); 2813 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2814 align = 4; 2815 } 2816 2817 if (Rm != 0xF) { // Writeback 2818 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2819 } 2820 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2821 Inst.addOperand(MCOperand::CreateImm(align)); 2822 if (Rm != 0xF && Rm != 0xD) { 2823 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2824 } 2825 2826 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2827 Inst.addOperand(MCOperand::CreateImm(index)); 2828 2829 return S; 2830 } 2831 2832 2833 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2834 uint64_t Address, const void *Decoder) { 2835 DecodeStatus S = Success; 2836 2837 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2838 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2839 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2840 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2841 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2842 2843 unsigned align = 0; 2844 unsigned index = 0; 2845 unsigned inc = 1; 2846 switch (size) { 2847 default: 2848 return Fail; 2849 case 0: 2850 index = fieldFromInstruction32(Insn, 5, 3); 2851 if (fieldFromInstruction32(Insn, 4, 1)) 2852 align = 2; 2853 break; 2854 case 1: 2855 index = fieldFromInstruction32(Insn, 6, 2); 2856 if (fieldFromInstruction32(Insn, 4, 1)) 2857 align = 4; 2858 if (fieldFromInstruction32(Insn, 5, 1)) 2859 inc = 2; 2860 break; 2861 case 2: 2862 if (fieldFromInstruction32(Insn, 5, 1)) 2863 return Fail; // UNDEFINED 2864 index = fieldFromInstruction32(Insn, 7, 1); 2865 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2866 align = 8; 2867 if (fieldFromInstruction32(Insn, 6, 1)) 2868 inc = 2; 2869 break; 2870 } 2871 2872 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2873 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2874 if (Rm != 0xF) { // Writeback 2875 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2876 } 2877 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2878 Inst.addOperand(MCOperand::CreateImm(align)); 2879 if (Rm != 0xF && Rm != 0xD) { 2880 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2881 } 2882 2883 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2884 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2885 Inst.addOperand(MCOperand::CreateImm(index)); 2886 2887 return S; 2888 } 2889 2890 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2891 uint64_t Address, const void *Decoder) { 2892 DecodeStatus S = Success; 2893 2894 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2895 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2896 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2897 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2898 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2899 2900 unsigned align = 0; 2901 unsigned index = 0; 2902 unsigned inc = 1; 2903 switch (size) { 2904 default: 2905 return Fail; 2906 case 0: 2907 index = fieldFromInstruction32(Insn, 5, 3); 2908 if (fieldFromInstruction32(Insn, 4, 1)) 2909 align = 2; 2910 break; 2911 case 1: 2912 index = fieldFromInstruction32(Insn, 6, 2); 2913 if (fieldFromInstruction32(Insn, 4, 1)) 2914 align = 4; 2915 if (fieldFromInstruction32(Insn, 5, 1)) 2916 inc = 2; 2917 break; 2918 case 2: 2919 if (fieldFromInstruction32(Insn, 5, 1)) 2920 return Fail; // UNDEFINED 2921 index = fieldFromInstruction32(Insn, 7, 1); 2922 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2923 align = 8; 2924 if (fieldFromInstruction32(Insn, 6, 1)) 2925 inc = 2; 2926 break; 2927 } 2928 2929 if (Rm != 0xF) { // Writeback 2930 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2931 } 2932 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2933 Inst.addOperand(MCOperand::CreateImm(align)); 2934 if (Rm != 0xF && Rm != 0xD) { 2935 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2936 } 2937 2938 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2939 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2940 Inst.addOperand(MCOperand::CreateImm(index)); 2941 2942 return S; 2943 } 2944 2945 2946 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 2947 uint64_t Address, const void *Decoder) { 2948 DecodeStatus S = Success; 2949 2950 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2951 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2952 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2953 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2954 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2955 2956 unsigned align = 0; 2957 unsigned index = 0; 2958 unsigned inc = 1; 2959 switch (size) { 2960 default: 2961 return Fail; 2962 case 0: 2963 if (fieldFromInstruction32(Insn, 4, 1)) 2964 return Fail; // UNDEFINED 2965 index = fieldFromInstruction32(Insn, 5, 3); 2966 break; 2967 case 1: 2968 if (fieldFromInstruction32(Insn, 4, 1)) 2969 return Fail; // UNDEFINED 2970 index = fieldFromInstruction32(Insn, 6, 2); 2971 if (fieldFromInstruction32(Insn, 5, 1)) 2972 inc = 2; 2973 break; 2974 case 2: 2975 if (fieldFromInstruction32(Insn, 4, 2)) 2976 return Fail; // UNDEFINED 2977 index = fieldFromInstruction32(Insn, 7, 1); 2978 if (fieldFromInstruction32(Insn, 6, 1)) 2979 inc = 2; 2980 break; 2981 } 2982 2983 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2984 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2985 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2986 2987 if (Rm != 0xF) { // Writeback 2988 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2989 } 2990 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2991 Inst.addOperand(MCOperand::CreateImm(align)); 2992 if (Rm != 0xF && Rm != 0xD) { 2993 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2994 } 2995 2996 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2997 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2998 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2999 Inst.addOperand(MCOperand::CreateImm(index)); 3000 3001 return S; 3002 } 3003 3004 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3005 uint64_t Address, const void *Decoder) { 3006 DecodeStatus S = Success; 3007 3008 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3009 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3010 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3011 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3012 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3013 3014 unsigned align = 0; 3015 unsigned index = 0; 3016 unsigned inc = 1; 3017 switch (size) { 3018 default: 3019 return Fail; 3020 case 0: 3021 if (fieldFromInstruction32(Insn, 4, 1)) 3022 return Fail; // UNDEFINED 3023 index = fieldFromInstruction32(Insn, 5, 3); 3024 break; 3025 case 1: 3026 if (fieldFromInstruction32(Insn, 4, 1)) 3027 return Fail; // UNDEFINED 3028 index = fieldFromInstruction32(Insn, 6, 2); 3029 if (fieldFromInstruction32(Insn, 5, 1)) 3030 inc = 2; 3031 break; 3032 case 2: 3033 if (fieldFromInstruction32(Insn, 4, 2)) 3034 return Fail; // UNDEFINED 3035 index = fieldFromInstruction32(Insn, 7, 1); 3036 if (fieldFromInstruction32(Insn, 6, 1)) 3037 inc = 2; 3038 break; 3039 } 3040 3041 if (Rm != 0xF) { // Writeback 3042 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3043 } 3044 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3045 Inst.addOperand(MCOperand::CreateImm(align)); 3046 if (Rm != 0xF && Rm != 0xD) { 3047 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3048 } 3049 3050 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3051 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3052 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3053 Inst.addOperand(MCOperand::CreateImm(index)); 3054 3055 return S; 3056 } 3057 3058 3059 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3060 uint64_t Address, const void *Decoder) { 3061 DecodeStatus S = Success; 3062 3063 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3064 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3065 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3066 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3067 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3068 3069 unsigned align = 0; 3070 unsigned index = 0; 3071 unsigned inc = 1; 3072 switch (size) { 3073 default: 3074 return Fail; 3075 case 0: 3076 if (fieldFromInstruction32(Insn, 4, 1)) 3077 align = 4; 3078 index = fieldFromInstruction32(Insn, 5, 3); 3079 break; 3080 case 1: 3081 if (fieldFromInstruction32(Insn, 4, 1)) 3082 align = 8; 3083 index = fieldFromInstruction32(Insn, 6, 2); 3084 if (fieldFromInstruction32(Insn, 5, 1)) 3085 inc = 2; 3086 break; 3087 case 2: 3088 if (fieldFromInstruction32(Insn, 4, 2)) 3089 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3090 index = fieldFromInstruction32(Insn, 7, 1); 3091 if (fieldFromInstruction32(Insn, 6, 1)) 3092 inc = 2; 3093 break; 3094 } 3095 3096 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3097 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3098 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3099 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3100 3101 if (Rm != 0xF) { // Writeback 3102 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3103 } 3104 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3105 Inst.addOperand(MCOperand::CreateImm(align)); 3106 if (Rm != 0xF && Rm != 0xD) { 3107 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3108 } 3109 3110 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3111 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3112 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3113 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3114 Inst.addOperand(MCOperand::CreateImm(index)); 3115 3116 return S; 3117 } 3118 3119 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3120 uint64_t Address, const void *Decoder) { 3121 DecodeStatus S = Success; 3122 3123 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3124 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3125 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3126 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3127 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3128 3129 unsigned align = 0; 3130 unsigned index = 0; 3131 unsigned inc = 1; 3132 switch (size) { 3133 default: 3134 return Fail; 3135 case 0: 3136 if (fieldFromInstruction32(Insn, 4, 1)) 3137 align = 4; 3138 index = fieldFromInstruction32(Insn, 5, 3); 3139 break; 3140 case 1: 3141 if (fieldFromInstruction32(Insn, 4, 1)) 3142 align = 8; 3143 index = fieldFromInstruction32(Insn, 6, 2); 3144 if (fieldFromInstruction32(Insn, 5, 1)) 3145 inc = 2; 3146 break; 3147 case 2: 3148 if (fieldFromInstruction32(Insn, 4, 2)) 3149 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3150 index = fieldFromInstruction32(Insn, 7, 1); 3151 if (fieldFromInstruction32(Insn, 6, 1)) 3152 inc = 2; 3153 break; 3154 } 3155 3156 if (Rm != 0xF) { // Writeback 3157 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3158 } 3159 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3160 Inst.addOperand(MCOperand::CreateImm(align)); 3161 if (Rm != 0xF && Rm != 0xD) { 3162 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3163 } 3164 3165 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3166 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3167 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3168 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3169 Inst.addOperand(MCOperand::CreateImm(index)); 3170 3171 return S; 3172 } 3173 3174