1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMSubtarget.h" 14 #include "MCTargetDesc/ARMAddressingModes.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDisassembler.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 /// ARMDisassembler - ARM disassembler for all ARM platforms. 35 class ARMDisassembler : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 EDInstInfo *getEDInfo() const; 56 private: 57 }; 58 59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60 class ThumbDisassembler : public MCDisassembler { 61 public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 EDInstInfo *getEDInfo() const; 81 private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85 }; 86 } 87 88 static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 return false; 101 } 102 103 104 // Forward declare these because the autogenerated code will reference them. 105 // Definitions are further down. 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129 130 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 146 uint64_t Address, const void *Decoder); 147 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 160 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 161 unsigned Insn, 162 uint64_t Adddress, 163 const void *Decoder); 164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 257 258 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 321 322 323 #include "ARMGenDisassemblerTables.inc" 324 #include "ARMGenInstrInfo.inc" 325 #include "ARMGenEDInfo.inc" 326 327 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 328 return new ARMDisassembler(STI); 329 } 330 331 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 332 return new ThumbDisassembler(STI); 333 } 334 335 EDInstInfo *ARMDisassembler::getEDInfo() const { 336 return instInfoARM; 337 } 338 339 EDInstInfo *ThumbDisassembler::getEDInfo() const { 340 return instInfoARM; 341 } 342 343 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 344 const MemoryObject &Region, 345 uint64_t Address, 346 raw_ostream &os, 347 raw_ostream &cs) const { 348 CommentStream = &cs; 349 350 uint8_t bytes[4]; 351 352 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 353 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 354 355 // We want to read exactly 4 bytes of data. 356 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 357 Size = 0; 358 return MCDisassembler::Fail; 359 } 360 361 // Encoded as a small-endian 32-bit word in the stream. 362 uint32_t insn = (bytes[3] << 24) | 363 (bytes[2] << 16) | 364 (bytes[1] << 8) | 365 (bytes[0] << 0); 366 367 // Calling the auto-generated decoder function. 368 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 369 if (result != MCDisassembler::Fail) { 370 Size = 4; 371 return result; 372 } 373 374 // VFP and NEON instructions, similarly, are shared between ARM 375 // and Thumb modes. 376 MI.clear(); 377 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 378 if (result != MCDisassembler::Fail) { 379 Size = 4; 380 return result; 381 } 382 383 MI.clear(); 384 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 385 if (result != MCDisassembler::Fail) { 386 Size = 4; 387 // Add a fake predicate operand, because we share these instruction 388 // definitions with Thumb2 where these instructions are predicable. 389 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 390 return MCDisassembler::Fail; 391 return result; 392 } 393 394 MI.clear(); 395 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 396 if (result != MCDisassembler::Fail) { 397 Size = 4; 398 // Add a fake predicate operand, because we share these instruction 399 // definitions with Thumb2 where these instructions are predicable. 400 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 401 return MCDisassembler::Fail; 402 return result; 403 } 404 405 MI.clear(); 406 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 407 if (result != MCDisassembler::Fail) { 408 Size = 4; 409 // Add a fake predicate operand, because we share these instruction 410 // definitions with Thumb2 where these instructions are predicable. 411 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 412 return MCDisassembler::Fail; 413 return result; 414 } 415 416 MI.clear(); 417 418 Size = 0; 419 return MCDisassembler::Fail; 420 } 421 422 namespace llvm { 423 extern const MCInstrDesc ARMInsts[]; 424 } 425 426 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 427 /// immediate Value in the MCInst. The immediate Value has had any PC 428 /// adjustment made by the caller. If the instruction is a branch instruction 429 /// then isBranch is true, else false. If the getOpInfo() function was set as 430 /// part of the setupForSymbolicDisassembly() call then that function is called 431 /// to get any symbolic information at the Address for this instruction. If 432 /// that returns non-zero then the symbolic information it returns is used to 433 /// create an MCExpr and that is added as an operand to the MCInst. If 434 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 435 /// Value is done and if a symbol is found an MCExpr is created with that, else 436 /// an MCExpr with Value is created. This function returns true if it adds an 437 /// operand to the MCInst and false otherwise. 438 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 439 bool isBranch, uint64_t InstSize, 440 MCInst &MI, const void *Decoder) { 441 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 442 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 443 if (!getOpInfo) 444 return false; 445 446 struct LLVMOpInfo1 SymbolicOp; 447 SymbolicOp.Value = Value; 448 void *DisInfo = Dis->getDisInfoBlock(); 449 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 450 if (isBranch) { 451 LLVMSymbolLookupCallback SymbolLookUp = 452 Dis->getLLVMSymbolLookupCallback(); 453 if (SymbolLookUp) { 454 uint64_t ReferenceType; 455 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 456 const char *ReferenceName; 457 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 458 &ReferenceName); 459 if (Name) { 460 SymbolicOp.AddSymbol.Name = Name; 461 SymbolicOp.AddSymbol.Present = true; 462 SymbolicOp.Value = 0; 463 } 464 else { 465 SymbolicOp.Value = Value; 466 } 467 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 468 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 469 } 470 else { 471 return false; 472 } 473 } 474 else { 475 return false; 476 } 477 } 478 479 MCContext *Ctx = Dis->getMCContext(); 480 const MCExpr *Add = NULL; 481 if (SymbolicOp.AddSymbol.Present) { 482 if (SymbolicOp.AddSymbol.Name) { 483 StringRef Name(SymbolicOp.AddSymbol.Name); 484 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 485 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 486 } else { 487 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 488 } 489 } 490 491 const MCExpr *Sub = NULL; 492 if (SymbolicOp.SubtractSymbol.Present) { 493 if (SymbolicOp.SubtractSymbol.Name) { 494 StringRef Name(SymbolicOp.SubtractSymbol.Name); 495 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 496 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 497 } else { 498 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 499 } 500 } 501 502 const MCExpr *Off = NULL; 503 if (SymbolicOp.Value != 0) 504 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 505 506 const MCExpr *Expr; 507 if (Sub) { 508 const MCExpr *LHS; 509 if (Add) 510 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 511 else 512 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 513 if (Off != 0) 514 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 515 else 516 Expr = LHS; 517 } else if (Add) { 518 if (Off != 0) 519 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 520 else 521 Expr = Add; 522 } else { 523 if (Off != 0) 524 Expr = Off; 525 else 526 Expr = MCConstantExpr::Create(0, *Ctx); 527 } 528 529 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 530 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 531 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 532 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 533 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 534 MI.addOperand(MCOperand::CreateExpr(Expr)); 535 else 536 assert(0 && "bad SymbolicOp.VariantKind"); 537 538 return true; 539 } 540 541 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 542 /// referenced by a load instruction with the base register that is the Pc. 543 /// These can often be values in a literal pool near the Address of the 544 /// instruction. The Address of the instruction and its immediate Value are 545 /// used as a possible literal pool entry. The SymbolLookUp call back will 546 /// return the name of a symbol referenced by the the literal pool's entry if 547 /// the referenced address is that of a symbol. Or it will return a pointer to 548 /// a literal 'C' string if the referenced address of the literal pool's entry 549 /// is an address into a section with 'C' string literals. 550 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 551 const void *Decoder) { 552 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 553 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 554 if (SymbolLookUp) { 555 void *DisInfo = Dis->getDisInfoBlock(); 556 uint64_t ReferenceType; 557 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 558 const char *ReferenceName; 559 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 560 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 561 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 562 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 563 } 564 } 565 566 // Thumb1 instructions don't have explicit S bits. Rather, they 567 // implicitly set CPSR. Since it's not represented in the encoding, the 568 // auto-generated decoder won't inject the CPSR operand. We need to fix 569 // that as a post-pass. 570 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 571 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 572 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 573 MCInst::iterator I = MI.begin(); 574 for (unsigned i = 0; i < NumOps; ++i, ++I) { 575 if (I == MI.end()) break; 576 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 577 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 579 return; 580 } 581 } 582 583 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 584 } 585 586 // Most Thumb instructions don't have explicit predicates in the 587 // encoding, but rather get their predicates from IT context. We need 588 // to fix up the predicate operands using this context information as a 589 // post-pass. 590 MCDisassembler::DecodeStatus 591 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 592 MCDisassembler::DecodeStatus S = Success; 593 594 // A few instructions actually have predicates encoded in them. Don't 595 // try to overwrite it if we're seeing one of those. 596 switch (MI.getOpcode()) { 597 case ARM::tBcc: 598 case ARM::t2Bcc: 599 case ARM::tCBZ: 600 case ARM::tCBNZ: 601 case ARM::tCPS: 602 case ARM::t2CPS3p: 603 case ARM::t2CPS2p: 604 case ARM::t2CPS1p: 605 case ARM::tMOVSr: 606 case ARM::tSETEND: 607 // Some instructions (mostly conditional branches) are not 608 // allowed in IT blocks. 609 if (!ITBlock.empty()) 610 S = SoftFail; 611 else 612 return Success; 613 break; 614 case ARM::tB: 615 case ARM::t2B: 616 case ARM::t2TBB: 617 case ARM::t2TBH: 618 // Some instructions (mostly unconditional branches) can 619 // only appears at the end of, or outside of, an IT. 620 if (ITBlock.size() > 1) 621 S = SoftFail; 622 break; 623 default: 624 break; 625 } 626 627 // If we're in an IT block, base the predicate on that. Otherwise, 628 // assume a predicate of AL. 629 unsigned CC; 630 if (!ITBlock.empty()) { 631 CC = ITBlock.back(); 632 if (CC == 0xF) 633 CC = ARMCC::AL; 634 ITBlock.pop_back(); 635 } else 636 CC = ARMCC::AL; 637 638 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 639 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 640 MCInst::iterator I = MI.begin(); 641 for (unsigned i = 0; i < NumOps; ++i, ++I) { 642 if (I == MI.end()) break; 643 if (OpInfo[i].isPredicate()) { 644 I = MI.insert(I, MCOperand::CreateImm(CC)); 645 ++I; 646 if (CC == ARMCC::AL) 647 MI.insert(I, MCOperand::CreateReg(0)); 648 else 649 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 650 return S; 651 } 652 } 653 654 I = MI.insert(I, MCOperand::CreateImm(CC)); 655 ++I; 656 if (CC == ARMCC::AL) 657 MI.insert(I, MCOperand::CreateReg(0)); 658 else 659 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 660 661 return S; 662 } 663 664 // Thumb VFP instructions are a special case. Because we share their 665 // encodings between ARM and Thumb modes, and they are predicable in ARM 666 // mode, the auto-generated decoder will give them an (incorrect) 667 // predicate operand. We need to rewrite these operands based on the IT 668 // context as a post-pass. 669 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 670 unsigned CC; 671 if (!ITBlock.empty()) { 672 CC = ITBlock.back(); 673 ITBlock.pop_back(); 674 } else 675 CC = ARMCC::AL; 676 677 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 678 MCInst::iterator I = MI.begin(); 679 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 680 for (unsigned i = 0; i < NumOps; ++i, ++I) { 681 if (OpInfo[i].isPredicate() ) { 682 I->setImm(CC); 683 ++I; 684 if (CC == ARMCC::AL) 685 I->setReg(0); 686 else 687 I->setReg(ARM::CPSR); 688 return; 689 } 690 } 691 } 692 693 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 694 const MemoryObject &Region, 695 uint64_t Address, 696 raw_ostream &os, 697 raw_ostream &cs) const { 698 CommentStream = &cs; 699 700 uint8_t bytes[4]; 701 702 assert((STI.getFeatureBits() & ARM::ModeThumb) && 703 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 704 705 // We want to read exactly 2 bytes of data. 706 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 707 Size = 0; 708 return MCDisassembler::Fail; 709 } 710 711 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 712 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 713 if (result != MCDisassembler::Fail) { 714 Size = 2; 715 Check(result, AddThumbPredicate(MI)); 716 return result; 717 } 718 719 MI.clear(); 720 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 721 if (result) { 722 Size = 2; 723 bool InITBlock = !ITBlock.empty(); 724 Check(result, AddThumbPredicate(MI)); 725 AddThumb1SBit(MI, InITBlock); 726 return result; 727 } 728 729 MI.clear(); 730 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 731 if (result != MCDisassembler::Fail) { 732 Size = 2; 733 734 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 735 // the Thumb predicate. 736 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 737 result = MCDisassembler::SoftFail; 738 739 Check(result, AddThumbPredicate(MI)); 740 741 // If we find an IT instruction, we need to parse its condition 742 // code and mask operands so that we can apply them correctly 743 // to the subsequent instructions. 744 if (MI.getOpcode() == ARM::t2IT) { 745 746 // (3 - the number of trailing zeros) is the number of then / else. 747 unsigned firstcond = MI.getOperand(0).getImm(); 748 unsigned Mask = MI.getOperand(1).getImm(); 749 unsigned CondBit0 = Mask >> 4 & 1; 750 unsigned NumTZ = CountTrailingZeros_32(Mask); 751 assert(NumTZ <= 3 && "Invalid IT mask!"); 752 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 753 bool T = ((Mask >> Pos) & 1) == CondBit0; 754 if (T) 755 ITBlock.insert(ITBlock.begin(), firstcond); 756 else 757 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 758 } 759 760 ITBlock.push_back(firstcond); 761 } 762 763 return result; 764 } 765 766 // We want to read exactly 4 bytes of data. 767 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 768 Size = 0; 769 return MCDisassembler::Fail; 770 } 771 772 uint32_t insn32 = (bytes[3] << 8) | 773 (bytes[2] << 0) | 774 (bytes[1] << 24) | 775 (bytes[0] << 16); 776 MI.clear(); 777 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 778 if (result != MCDisassembler::Fail) { 779 Size = 4; 780 bool InITBlock = ITBlock.size(); 781 Check(result, AddThumbPredicate(MI)); 782 AddThumb1SBit(MI, InITBlock); 783 return result; 784 } 785 786 MI.clear(); 787 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 788 if (result != MCDisassembler::Fail) { 789 Size = 4; 790 Check(result, AddThumbPredicate(MI)); 791 return result; 792 } 793 794 MI.clear(); 795 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 796 if (result != MCDisassembler::Fail) { 797 Size = 4; 798 UpdateThumbVFPPredicate(MI); 799 return result; 800 } 801 802 MI.clear(); 803 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 804 if (result != MCDisassembler::Fail) { 805 Size = 4; 806 Check(result, AddThumbPredicate(MI)); 807 return result; 808 } 809 810 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 811 MI.clear(); 812 uint32_t NEONLdStInsn = insn32; 813 NEONLdStInsn &= 0xF0FFFFFF; 814 NEONLdStInsn |= 0x04000000; 815 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 816 if (result != MCDisassembler::Fail) { 817 Size = 4; 818 Check(result, AddThumbPredicate(MI)); 819 return result; 820 } 821 } 822 823 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 824 MI.clear(); 825 uint32_t NEONDataInsn = insn32; 826 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 827 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 828 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 829 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 830 if (result != MCDisassembler::Fail) { 831 Size = 4; 832 Check(result, AddThumbPredicate(MI)); 833 return result; 834 } 835 } 836 837 Size = 0; 838 return MCDisassembler::Fail; 839 } 840 841 842 extern "C" void LLVMInitializeARMDisassembler() { 843 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 844 createARMDisassembler); 845 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 846 createThumbDisassembler); 847 } 848 849 static const unsigned GPRDecoderTable[] = { 850 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 851 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 852 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 853 ARM::R12, ARM::SP, ARM::LR, ARM::PC 854 }; 855 856 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 857 uint64_t Address, const void *Decoder) { 858 if (RegNo > 15) 859 return MCDisassembler::Fail; 860 861 unsigned Register = GPRDecoderTable[RegNo]; 862 Inst.addOperand(MCOperand::CreateReg(Register)); 863 return MCDisassembler::Success; 864 } 865 866 static DecodeStatus 867 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 868 uint64_t Address, const void *Decoder) { 869 if (RegNo == 15) return MCDisassembler::Fail; 870 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 871 } 872 873 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 874 uint64_t Address, const void *Decoder) { 875 if (RegNo > 7) 876 return MCDisassembler::Fail; 877 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 878 } 879 880 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 881 uint64_t Address, const void *Decoder) { 882 unsigned Register = 0; 883 switch (RegNo) { 884 case 0: 885 Register = ARM::R0; 886 break; 887 case 1: 888 Register = ARM::R1; 889 break; 890 case 2: 891 Register = ARM::R2; 892 break; 893 case 3: 894 Register = ARM::R3; 895 break; 896 case 9: 897 Register = ARM::R9; 898 break; 899 case 12: 900 Register = ARM::R12; 901 break; 902 default: 903 return MCDisassembler::Fail; 904 } 905 906 Inst.addOperand(MCOperand::CreateReg(Register)); 907 return MCDisassembler::Success; 908 } 909 910 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 911 uint64_t Address, const void *Decoder) { 912 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 913 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 914 } 915 916 static const unsigned SPRDecoderTable[] = { 917 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 918 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 919 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 920 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 921 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 922 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 923 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 924 ARM::S28, ARM::S29, ARM::S30, ARM::S31 925 }; 926 927 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 928 uint64_t Address, const void *Decoder) { 929 if (RegNo > 31) 930 return MCDisassembler::Fail; 931 932 unsigned Register = SPRDecoderTable[RegNo]; 933 Inst.addOperand(MCOperand::CreateReg(Register)); 934 return MCDisassembler::Success; 935 } 936 937 static const unsigned DPRDecoderTable[] = { 938 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 939 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 940 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 941 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 942 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 943 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 944 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 945 ARM::D28, ARM::D29, ARM::D30, ARM::D31 946 }; 947 948 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 949 uint64_t Address, const void *Decoder) { 950 if (RegNo > 31) 951 return MCDisassembler::Fail; 952 953 unsigned Register = DPRDecoderTable[RegNo]; 954 Inst.addOperand(MCOperand::CreateReg(Register)); 955 return MCDisassembler::Success; 956 } 957 958 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 959 uint64_t Address, const void *Decoder) { 960 if (RegNo > 7) 961 return MCDisassembler::Fail; 962 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 963 } 964 965 static DecodeStatus 966 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 967 uint64_t Address, const void *Decoder) { 968 if (RegNo > 15) 969 return MCDisassembler::Fail; 970 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 971 } 972 973 static const unsigned QPRDecoderTable[] = { 974 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 975 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 976 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 977 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 978 }; 979 980 981 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 982 uint64_t Address, const void *Decoder) { 983 if (RegNo > 31) 984 return MCDisassembler::Fail; 985 RegNo >>= 1; 986 987 unsigned Register = QPRDecoderTable[RegNo]; 988 Inst.addOperand(MCOperand::CreateReg(Register)); 989 return MCDisassembler::Success; 990 } 991 992 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 993 uint64_t Address, const void *Decoder) { 994 if (Val == 0xF) return MCDisassembler::Fail; 995 // AL predicate is not allowed on Thumb1 branches. 996 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 997 return MCDisassembler::Fail; 998 Inst.addOperand(MCOperand::CreateImm(Val)); 999 if (Val == ARMCC::AL) { 1000 Inst.addOperand(MCOperand::CreateReg(0)); 1001 } else 1002 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1003 return MCDisassembler::Success; 1004 } 1005 1006 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1007 uint64_t Address, const void *Decoder) { 1008 if (Val) 1009 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1010 else 1011 Inst.addOperand(MCOperand::CreateReg(0)); 1012 return MCDisassembler::Success; 1013 } 1014 1015 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1016 uint64_t Address, const void *Decoder) { 1017 uint32_t imm = Val & 0xFF; 1018 uint32_t rot = (Val & 0xF00) >> 7; 1019 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1020 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1021 return MCDisassembler::Success; 1022 } 1023 1024 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1025 uint64_t Address, const void *Decoder) { 1026 DecodeStatus S = MCDisassembler::Success; 1027 1028 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1029 unsigned type = fieldFromInstruction32(Val, 5, 2); 1030 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1031 1032 // Register-immediate 1033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1034 return MCDisassembler::Fail; 1035 1036 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1037 switch (type) { 1038 case 0: 1039 Shift = ARM_AM::lsl; 1040 break; 1041 case 1: 1042 Shift = ARM_AM::lsr; 1043 break; 1044 case 2: 1045 Shift = ARM_AM::asr; 1046 break; 1047 case 3: 1048 Shift = ARM_AM::ror; 1049 break; 1050 } 1051 1052 if (Shift == ARM_AM::ror && imm == 0) 1053 Shift = ARM_AM::rrx; 1054 1055 unsigned Op = Shift | (imm << 3); 1056 Inst.addOperand(MCOperand::CreateImm(Op)); 1057 1058 return S; 1059 } 1060 1061 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1062 uint64_t Address, const void *Decoder) { 1063 DecodeStatus S = MCDisassembler::Success; 1064 1065 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1066 unsigned type = fieldFromInstruction32(Val, 5, 2); 1067 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1068 1069 // Register-register 1070 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1071 return MCDisassembler::Fail; 1072 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1073 return MCDisassembler::Fail; 1074 1075 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1076 switch (type) { 1077 case 0: 1078 Shift = ARM_AM::lsl; 1079 break; 1080 case 1: 1081 Shift = ARM_AM::lsr; 1082 break; 1083 case 2: 1084 Shift = ARM_AM::asr; 1085 break; 1086 case 3: 1087 Shift = ARM_AM::ror; 1088 break; 1089 } 1090 1091 Inst.addOperand(MCOperand::CreateImm(Shift)); 1092 1093 return S; 1094 } 1095 1096 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1097 uint64_t Address, const void *Decoder) { 1098 DecodeStatus S = MCDisassembler::Success; 1099 1100 bool writebackLoad = false; 1101 unsigned writebackReg = 0; 1102 switch (Inst.getOpcode()) { 1103 default: 1104 break; 1105 case ARM::LDMIA_UPD: 1106 case ARM::LDMDB_UPD: 1107 case ARM::LDMIB_UPD: 1108 case ARM::LDMDA_UPD: 1109 case ARM::t2LDMIA_UPD: 1110 case ARM::t2LDMDB_UPD: 1111 writebackLoad = true; 1112 writebackReg = Inst.getOperand(0).getReg(); 1113 break; 1114 } 1115 1116 // Empty register lists are not allowed. 1117 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1118 for (unsigned i = 0; i < 16; ++i) { 1119 if (Val & (1 << i)) { 1120 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1121 return MCDisassembler::Fail; 1122 // Writeback not allowed if Rn is in the target list. 1123 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1124 Check(S, MCDisassembler::SoftFail); 1125 } 1126 } 1127 1128 return S; 1129 } 1130 1131 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1132 uint64_t Address, const void *Decoder) { 1133 DecodeStatus S = MCDisassembler::Success; 1134 1135 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1136 unsigned regs = Val & 0xFF; 1137 1138 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1139 return MCDisassembler::Fail; 1140 for (unsigned i = 0; i < (regs - 1); ++i) { 1141 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1142 return MCDisassembler::Fail; 1143 } 1144 1145 return S; 1146 } 1147 1148 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1149 uint64_t Address, const void *Decoder) { 1150 DecodeStatus S = MCDisassembler::Success; 1151 1152 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1153 unsigned regs = (Val & 0xFF) / 2; 1154 1155 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1156 return MCDisassembler::Fail; 1157 for (unsigned i = 0; i < (regs - 1); ++i) { 1158 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1159 return MCDisassembler::Fail; 1160 } 1161 1162 return S; 1163 } 1164 1165 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1166 uint64_t Address, const void *Decoder) { 1167 // This operand encodes a mask of contiguous zeros between a specified MSB 1168 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1169 // the mask of all bits LSB-and-lower, and then xor them to create 1170 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1171 // create the final mask. 1172 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1173 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1174 1175 DecodeStatus S = MCDisassembler::Success; 1176 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1177 1178 uint32_t msb_mask = 0xFFFFFFFF; 1179 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1180 uint32_t lsb_mask = (1U << lsb) - 1; 1181 1182 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1183 return S; 1184 } 1185 1186 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1187 uint64_t Address, const void *Decoder) { 1188 DecodeStatus S = MCDisassembler::Success; 1189 1190 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1191 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1192 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1193 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1194 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1195 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1196 1197 switch (Inst.getOpcode()) { 1198 case ARM::LDC_OFFSET: 1199 case ARM::LDC_PRE: 1200 case ARM::LDC_POST: 1201 case ARM::LDC_OPTION: 1202 case ARM::LDCL_OFFSET: 1203 case ARM::LDCL_PRE: 1204 case ARM::LDCL_POST: 1205 case ARM::LDCL_OPTION: 1206 case ARM::STC_OFFSET: 1207 case ARM::STC_PRE: 1208 case ARM::STC_POST: 1209 case ARM::STC_OPTION: 1210 case ARM::STCL_OFFSET: 1211 case ARM::STCL_PRE: 1212 case ARM::STCL_POST: 1213 case ARM::STCL_OPTION: 1214 case ARM::t2LDC_OFFSET: 1215 case ARM::t2LDC_PRE: 1216 case ARM::t2LDC_POST: 1217 case ARM::t2LDC_OPTION: 1218 case ARM::t2LDCL_OFFSET: 1219 case ARM::t2LDCL_PRE: 1220 case ARM::t2LDCL_POST: 1221 case ARM::t2LDCL_OPTION: 1222 case ARM::t2STC_OFFSET: 1223 case ARM::t2STC_PRE: 1224 case ARM::t2STC_POST: 1225 case ARM::t2STC_OPTION: 1226 case ARM::t2STCL_OFFSET: 1227 case ARM::t2STCL_PRE: 1228 case ARM::t2STCL_POST: 1229 case ARM::t2STCL_OPTION: 1230 if (coproc == 0xA || coproc == 0xB) 1231 return MCDisassembler::Fail; 1232 break; 1233 default: 1234 break; 1235 } 1236 1237 Inst.addOperand(MCOperand::CreateImm(coproc)); 1238 Inst.addOperand(MCOperand::CreateImm(CRd)); 1239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1240 return MCDisassembler::Fail; 1241 1242 switch (Inst.getOpcode()) { 1243 case ARM::t2LDC2_OFFSET: 1244 case ARM::t2LDC2L_OFFSET: 1245 case ARM::t2LDC2_PRE: 1246 case ARM::t2LDC2L_PRE: 1247 case ARM::t2STC2_OFFSET: 1248 case ARM::t2STC2L_OFFSET: 1249 case ARM::t2STC2_PRE: 1250 case ARM::t2STC2L_PRE: 1251 case ARM::LDC2_OFFSET: 1252 case ARM::LDC2L_OFFSET: 1253 case ARM::LDC2_PRE: 1254 case ARM::LDC2L_PRE: 1255 case ARM::STC2_OFFSET: 1256 case ARM::STC2L_OFFSET: 1257 case ARM::STC2_PRE: 1258 case ARM::STC2L_PRE: 1259 case ARM::t2LDC_OFFSET: 1260 case ARM::t2LDCL_OFFSET: 1261 case ARM::t2LDC_PRE: 1262 case ARM::t2LDCL_PRE: 1263 case ARM::t2STC_OFFSET: 1264 case ARM::t2STCL_OFFSET: 1265 case ARM::t2STC_PRE: 1266 case ARM::t2STCL_PRE: 1267 case ARM::LDC_OFFSET: 1268 case ARM::LDCL_OFFSET: 1269 case ARM::LDC_PRE: 1270 case ARM::LDCL_PRE: 1271 case ARM::STC_OFFSET: 1272 case ARM::STCL_OFFSET: 1273 case ARM::STC_PRE: 1274 case ARM::STCL_PRE: 1275 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1276 Inst.addOperand(MCOperand::CreateImm(imm)); 1277 break; 1278 case ARM::t2LDC2_POST: 1279 case ARM::t2LDC2L_POST: 1280 case ARM::t2STC2_POST: 1281 case ARM::t2STC2L_POST: 1282 case ARM::LDC2_POST: 1283 case ARM::LDC2L_POST: 1284 case ARM::STC2_POST: 1285 case ARM::STC2L_POST: 1286 case ARM::t2LDC_POST: 1287 case ARM::t2LDCL_POST: 1288 case ARM::t2STC_POST: 1289 case ARM::t2STCL_POST: 1290 case ARM::LDC_POST: 1291 case ARM::LDCL_POST: 1292 case ARM::STC_POST: 1293 case ARM::STCL_POST: 1294 imm |= U << 8; 1295 // fall through. 1296 default: 1297 // The 'option' variant doesn't encode 'U' in the immediate since 1298 // the immediate is unsigned [0,255]. 1299 Inst.addOperand(MCOperand::CreateImm(imm)); 1300 break; 1301 } 1302 1303 switch (Inst.getOpcode()) { 1304 case ARM::LDC_OFFSET: 1305 case ARM::LDC_PRE: 1306 case ARM::LDC_POST: 1307 case ARM::LDC_OPTION: 1308 case ARM::LDCL_OFFSET: 1309 case ARM::LDCL_PRE: 1310 case ARM::LDCL_POST: 1311 case ARM::LDCL_OPTION: 1312 case ARM::STC_OFFSET: 1313 case ARM::STC_PRE: 1314 case ARM::STC_POST: 1315 case ARM::STC_OPTION: 1316 case ARM::STCL_OFFSET: 1317 case ARM::STCL_PRE: 1318 case ARM::STCL_POST: 1319 case ARM::STCL_OPTION: 1320 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1321 return MCDisassembler::Fail; 1322 break; 1323 default: 1324 break; 1325 } 1326 1327 return S; 1328 } 1329 1330 static DecodeStatus 1331 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1332 uint64_t Address, const void *Decoder) { 1333 DecodeStatus S = MCDisassembler::Success; 1334 1335 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1336 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1337 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1338 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1339 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1340 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1341 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1342 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1343 1344 // On stores, the writeback operand precedes Rt. 1345 switch (Inst.getOpcode()) { 1346 case ARM::STR_POST_IMM: 1347 case ARM::STR_POST_REG: 1348 case ARM::STRB_POST_IMM: 1349 case ARM::STRB_POST_REG: 1350 case ARM::STRT_POST_REG: 1351 case ARM::STRT_POST_IMM: 1352 case ARM::STRBT_POST_REG: 1353 case ARM::STRBT_POST_IMM: 1354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1355 return MCDisassembler::Fail; 1356 break; 1357 default: 1358 break; 1359 } 1360 1361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1362 return MCDisassembler::Fail; 1363 1364 // On loads, the writeback operand comes after Rt. 1365 switch (Inst.getOpcode()) { 1366 case ARM::LDR_POST_IMM: 1367 case ARM::LDR_POST_REG: 1368 case ARM::LDRB_POST_IMM: 1369 case ARM::LDRB_POST_REG: 1370 case ARM::LDRBT_POST_REG: 1371 case ARM::LDRBT_POST_IMM: 1372 case ARM::LDRT_POST_REG: 1373 case ARM::LDRT_POST_IMM: 1374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1375 return MCDisassembler::Fail; 1376 break; 1377 default: 1378 break; 1379 } 1380 1381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1382 return MCDisassembler::Fail; 1383 1384 ARM_AM::AddrOpc Op = ARM_AM::add; 1385 if (!fieldFromInstruction32(Insn, 23, 1)) 1386 Op = ARM_AM::sub; 1387 1388 bool writeback = (P == 0) || (W == 1); 1389 unsigned idx_mode = 0; 1390 if (P && writeback) 1391 idx_mode = ARMII::IndexModePre; 1392 else if (!P && writeback) 1393 idx_mode = ARMII::IndexModePost; 1394 1395 if (writeback && (Rn == 15 || Rn == Rt)) 1396 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1397 1398 if (reg) { 1399 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1400 return MCDisassembler::Fail; 1401 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1402 switch( fieldFromInstruction32(Insn, 5, 2)) { 1403 case 0: 1404 Opc = ARM_AM::lsl; 1405 break; 1406 case 1: 1407 Opc = ARM_AM::lsr; 1408 break; 1409 case 2: 1410 Opc = ARM_AM::asr; 1411 break; 1412 case 3: 1413 Opc = ARM_AM::ror; 1414 break; 1415 default: 1416 return MCDisassembler::Fail; 1417 } 1418 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1419 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1420 1421 Inst.addOperand(MCOperand::CreateImm(imm)); 1422 } else { 1423 Inst.addOperand(MCOperand::CreateReg(0)); 1424 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1425 Inst.addOperand(MCOperand::CreateImm(tmp)); 1426 } 1427 1428 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1429 return MCDisassembler::Fail; 1430 1431 return S; 1432 } 1433 1434 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1435 uint64_t Address, const void *Decoder) { 1436 DecodeStatus S = MCDisassembler::Success; 1437 1438 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1439 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1440 unsigned type = fieldFromInstruction32(Val, 5, 2); 1441 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1442 unsigned U = fieldFromInstruction32(Val, 12, 1); 1443 1444 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1445 switch (type) { 1446 case 0: 1447 ShOp = ARM_AM::lsl; 1448 break; 1449 case 1: 1450 ShOp = ARM_AM::lsr; 1451 break; 1452 case 2: 1453 ShOp = ARM_AM::asr; 1454 break; 1455 case 3: 1456 ShOp = ARM_AM::ror; 1457 break; 1458 } 1459 1460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1461 return MCDisassembler::Fail; 1462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1463 return MCDisassembler::Fail; 1464 unsigned shift; 1465 if (U) 1466 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1467 else 1468 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1469 Inst.addOperand(MCOperand::CreateImm(shift)); 1470 1471 return S; 1472 } 1473 1474 static DecodeStatus 1475 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1476 uint64_t Address, const void *Decoder) { 1477 DecodeStatus S = MCDisassembler::Success; 1478 1479 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1480 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1481 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1482 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1483 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1484 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1485 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1486 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1487 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1488 1489 bool writeback = (W == 1) | (P == 0); 1490 1491 // For {LD,ST}RD, Rt must be even, else undefined. 1492 switch (Inst.getOpcode()) { 1493 case ARM::STRD: 1494 case ARM::STRD_PRE: 1495 case ARM::STRD_POST: 1496 case ARM::LDRD: 1497 case ARM::LDRD_PRE: 1498 case ARM::LDRD_POST: 1499 if (Rt & 0x1) return MCDisassembler::Fail; 1500 break; 1501 default: 1502 break; 1503 } 1504 1505 if (writeback) { // Writeback 1506 if (P) 1507 U |= ARMII::IndexModePre << 9; 1508 else 1509 U |= ARMII::IndexModePost << 9; 1510 1511 // On stores, the writeback operand precedes Rt. 1512 switch (Inst.getOpcode()) { 1513 case ARM::STRD: 1514 case ARM::STRD_PRE: 1515 case ARM::STRD_POST: 1516 case ARM::STRH: 1517 case ARM::STRH_PRE: 1518 case ARM::STRH_POST: 1519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1520 return MCDisassembler::Fail; 1521 break; 1522 default: 1523 break; 1524 } 1525 } 1526 1527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1528 return MCDisassembler::Fail; 1529 switch (Inst.getOpcode()) { 1530 case ARM::STRD: 1531 case ARM::STRD_PRE: 1532 case ARM::STRD_POST: 1533 case ARM::LDRD: 1534 case ARM::LDRD_PRE: 1535 case ARM::LDRD_POST: 1536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1537 return MCDisassembler::Fail; 1538 break; 1539 default: 1540 break; 1541 } 1542 1543 if (writeback) { 1544 // On loads, the writeback operand comes after Rt. 1545 switch (Inst.getOpcode()) { 1546 case ARM::LDRD: 1547 case ARM::LDRD_PRE: 1548 case ARM::LDRD_POST: 1549 case ARM::LDRH: 1550 case ARM::LDRH_PRE: 1551 case ARM::LDRH_POST: 1552 case ARM::LDRSH: 1553 case ARM::LDRSH_PRE: 1554 case ARM::LDRSH_POST: 1555 case ARM::LDRSB: 1556 case ARM::LDRSB_PRE: 1557 case ARM::LDRSB_POST: 1558 case ARM::LDRHTr: 1559 case ARM::LDRSBTr: 1560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1561 return MCDisassembler::Fail; 1562 break; 1563 default: 1564 break; 1565 } 1566 } 1567 1568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1569 return MCDisassembler::Fail; 1570 1571 if (type) { 1572 Inst.addOperand(MCOperand::CreateReg(0)); 1573 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1574 } else { 1575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1576 return MCDisassembler::Fail; 1577 Inst.addOperand(MCOperand::CreateImm(U)); 1578 } 1579 1580 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1581 return MCDisassembler::Fail; 1582 1583 return S; 1584 } 1585 1586 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1587 uint64_t Address, const void *Decoder) { 1588 DecodeStatus S = MCDisassembler::Success; 1589 1590 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1591 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1592 1593 switch (mode) { 1594 case 0: 1595 mode = ARM_AM::da; 1596 break; 1597 case 1: 1598 mode = ARM_AM::ia; 1599 break; 1600 case 2: 1601 mode = ARM_AM::db; 1602 break; 1603 case 3: 1604 mode = ARM_AM::ib; 1605 break; 1606 } 1607 1608 Inst.addOperand(MCOperand::CreateImm(mode)); 1609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1610 return MCDisassembler::Fail; 1611 1612 return S; 1613 } 1614 1615 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1616 unsigned Insn, 1617 uint64_t Address, const void *Decoder) { 1618 DecodeStatus S = MCDisassembler::Success; 1619 1620 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1621 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1622 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1623 1624 if (pred == 0xF) { 1625 switch (Inst.getOpcode()) { 1626 case ARM::LDMDA: 1627 Inst.setOpcode(ARM::RFEDA); 1628 break; 1629 case ARM::LDMDA_UPD: 1630 Inst.setOpcode(ARM::RFEDA_UPD); 1631 break; 1632 case ARM::LDMDB: 1633 Inst.setOpcode(ARM::RFEDB); 1634 break; 1635 case ARM::LDMDB_UPD: 1636 Inst.setOpcode(ARM::RFEDB_UPD); 1637 break; 1638 case ARM::LDMIA: 1639 Inst.setOpcode(ARM::RFEIA); 1640 break; 1641 case ARM::LDMIA_UPD: 1642 Inst.setOpcode(ARM::RFEIA_UPD); 1643 break; 1644 case ARM::LDMIB: 1645 Inst.setOpcode(ARM::RFEIB); 1646 break; 1647 case ARM::LDMIB_UPD: 1648 Inst.setOpcode(ARM::RFEIB_UPD); 1649 break; 1650 case ARM::STMDA: 1651 Inst.setOpcode(ARM::SRSDA); 1652 break; 1653 case ARM::STMDA_UPD: 1654 Inst.setOpcode(ARM::SRSDA_UPD); 1655 break; 1656 case ARM::STMDB: 1657 Inst.setOpcode(ARM::SRSDB); 1658 break; 1659 case ARM::STMDB_UPD: 1660 Inst.setOpcode(ARM::SRSDB_UPD); 1661 break; 1662 case ARM::STMIA: 1663 Inst.setOpcode(ARM::SRSIA); 1664 break; 1665 case ARM::STMIA_UPD: 1666 Inst.setOpcode(ARM::SRSIA_UPD); 1667 break; 1668 case ARM::STMIB: 1669 Inst.setOpcode(ARM::SRSIB); 1670 break; 1671 case ARM::STMIB_UPD: 1672 Inst.setOpcode(ARM::SRSIB_UPD); 1673 break; 1674 default: 1675 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1676 } 1677 1678 // For stores (which become SRS's, the only operand is the mode. 1679 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1680 Inst.addOperand( 1681 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1682 return S; 1683 } 1684 1685 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1686 } 1687 1688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1689 return MCDisassembler::Fail; 1690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1691 return MCDisassembler::Fail; // Tied 1692 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1693 return MCDisassembler::Fail; 1694 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1695 return MCDisassembler::Fail; 1696 1697 return S; 1698 } 1699 1700 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1701 uint64_t Address, const void *Decoder) { 1702 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1703 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1704 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1705 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1706 1707 DecodeStatus S = MCDisassembler::Success; 1708 1709 // imod == '01' --> UNPREDICTABLE 1710 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1711 // return failure here. The '01' imod value is unprintable, so there's 1712 // nothing useful we could do even if we returned UNPREDICTABLE. 1713 1714 if (imod == 1) return MCDisassembler::Fail; 1715 1716 if (imod && M) { 1717 Inst.setOpcode(ARM::CPS3p); 1718 Inst.addOperand(MCOperand::CreateImm(imod)); 1719 Inst.addOperand(MCOperand::CreateImm(iflags)); 1720 Inst.addOperand(MCOperand::CreateImm(mode)); 1721 } else if (imod && !M) { 1722 Inst.setOpcode(ARM::CPS2p); 1723 Inst.addOperand(MCOperand::CreateImm(imod)); 1724 Inst.addOperand(MCOperand::CreateImm(iflags)); 1725 if (mode) S = MCDisassembler::SoftFail; 1726 } else if (!imod && M) { 1727 Inst.setOpcode(ARM::CPS1p); 1728 Inst.addOperand(MCOperand::CreateImm(mode)); 1729 if (iflags) S = MCDisassembler::SoftFail; 1730 } else { 1731 // imod == '00' && M == '0' --> UNPREDICTABLE 1732 Inst.setOpcode(ARM::CPS1p); 1733 Inst.addOperand(MCOperand::CreateImm(mode)); 1734 S = MCDisassembler::SoftFail; 1735 } 1736 1737 return S; 1738 } 1739 1740 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1741 uint64_t Address, const void *Decoder) { 1742 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1743 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1744 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1745 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1746 1747 DecodeStatus S = MCDisassembler::Success; 1748 1749 // imod == '01' --> UNPREDICTABLE 1750 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1751 // return failure here. The '01' imod value is unprintable, so there's 1752 // nothing useful we could do even if we returned UNPREDICTABLE. 1753 1754 if (imod == 1) return MCDisassembler::Fail; 1755 1756 if (imod && M) { 1757 Inst.setOpcode(ARM::t2CPS3p); 1758 Inst.addOperand(MCOperand::CreateImm(imod)); 1759 Inst.addOperand(MCOperand::CreateImm(iflags)); 1760 Inst.addOperand(MCOperand::CreateImm(mode)); 1761 } else if (imod && !M) { 1762 Inst.setOpcode(ARM::t2CPS2p); 1763 Inst.addOperand(MCOperand::CreateImm(imod)); 1764 Inst.addOperand(MCOperand::CreateImm(iflags)); 1765 if (mode) S = MCDisassembler::SoftFail; 1766 } else if (!imod && M) { 1767 Inst.setOpcode(ARM::t2CPS1p); 1768 Inst.addOperand(MCOperand::CreateImm(mode)); 1769 if (iflags) S = MCDisassembler::SoftFail; 1770 } else { 1771 // imod == '00' && M == '0' --> UNPREDICTABLE 1772 Inst.setOpcode(ARM::t2CPS1p); 1773 Inst.addOperand(MCOperand::CreateImm(mode)); 1774 S = MCDisassembler::SoftFail; 1775 } 1776 1777 return S; 1778 } 1779 1780 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1781 uint64_t Address, const void *Decoder) { 1782 DecodeStatus S = MCDisassembler::Success; 1783 1784 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1785 unsigned imm = 0; 1786 1787 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1788 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1789 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1790 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1791 1792 if (Inst.getOpcode() == ARM::t2MOVTi16) 1793 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1796 return MCDisassembler::Fail; 1797 1798 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1799 Inst.addOperand(MCOperand::CreateImm(imm)); 1800 1801 return S; 1802 } 1803 1804 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1805 uint64_t Address, const void *Decoder) { 1806 DecodeStatus S = MCDisassembler::Success; 1807 1808 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1809 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1810 unsigned imm = 0; 1811 1812 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1813 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1814 1815 if (Inst.getOpcode() == ARM::MOVTi16) 1816 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1817 return MCDisassembler::Fail; 1818 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1819 return MCDisassembler::Fail; 1820 1821 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1822 Inst.addOperand(MCOperand::CreateImm(imm)); 1823 1824 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1825 return MCDisassembler::Fail; 1826 1827 return S; 1828 } 1829 1830 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1831 uint64_t Address, const void *Decoder) { 1832 DecodeStatus S = MCDisassembler::Success; 1833 1834 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1835 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1836 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1837 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1838 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1839 1840 if (pred == 0xF) 1841 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1842 1843 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1844 return MCDisassembler::Fail; 1845 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1846 return MCDisassembler::Fail; 1847 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1848 return MCDisassembler::Fail; 1849 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1850 return MCDisassembler::Fail; 1851 1852 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1853 return MCDisassembler::Fail; 1854 1855 return S; 1856 } 1857 1858 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1859 uint64_t Address, const void *Decoder) { 1860 DecodeStatus S = MCDisassembler::Success; 1861 1862 unsigned add = fieldFromInstruction32(Val, 12, 1); 1863 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1864 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1865 1866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1867 return MCDisassembler::Fail; 1868 1869 if (!add) imm *= -1; 1870 if (imm == 0 && !add) imm = INT32_MIN; 1871 Inst.addOperand(MCOperand::CreateImm(imm)); 1872 if (Rn == 15) 1873 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1874 1875 return S; 1876 } 1877 1878 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1879 uint64_t Address, const void *Decoder) { 1880 DecodeStatus S = MCDisassembler::Success; 1881 1882 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1883 unsigned U = fieldFromInstruction32(Val, 8, 1); 1884 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1885 1886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1887 return MCDisassembler::Fail; 1888 1889 if (U) 1890 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1891 else 1892 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1893 1894 return S; 1895 } 1896 1897 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1898 uint64_t Address, const void *Decoder) { 1899 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1900 } 1901 1902 static DecodeStatus 1903 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1904 uint64_t Address, const void *Decoder) { 1905 DecodeStatus S = MCDisassembler::Success; 1906 1907 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1908 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1909 1910 if (pred == 0xF) { 1911 Inst.setOpcode(ARM::BLXi); 1912 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1913 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1914 return S; 1915 } 1916 1917 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true, 1918 4, Inst, Decoder)) 1919 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1920 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1921 return MCDisassembler::Fail; 1922 1923 return S; 1924 } 1925 1926 1927 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1928 uint64_t Address, const void *Decoder) { 1929 DecodeStatus S = MCDisassembler::Success; 1930 1931 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1932 unsigned align = fieldFromInstruction32(Val, 4, 2); 1933 1934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1935 return MCDisassembler::Fail; 1936 if (!align) 1937 Inst.addOperand(MCOperand::CreateImm(0)); 1938 else 1939 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1940 1941 return S; 1942 } 1943 1944 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1945 uint64_t Address, const void *Decoder) { 1946 DecodeStatus S = MCDisassembler::Success; 1947 1948 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1949 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1950 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1951 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1952 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1953 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1954 1955 // First output register 1956 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1957 return MCDisassembler::Fail; 1958 1959 // Second output register 1960 switch (Inst.getOpcode()) { 1961 case ARM::VLD3d8: 1962 case ARM::VLD3d16: 1963 case ARM::VLD3d32: 1964 case ARM::VLD3d8_UPD: 1965 case ARM::VLD3d16_UPD: 1966 case ARM::VLD3d32_UPD: 1967 case ARM::VLD4d8: 1968 case ARM::VLD4d16: 1969 case ARM::VLD4d32: 1970 case ARM::VLD4d8_UPD: 1971 case ARM::VLD4d16_UPD: 1972 case ARM::VLD4d32_UPD: 1973 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 break; 1976 case ARM::VLD3q8: 1977 case ARM::VLD3q16: 1978 case ARM::VLD3q32: 1979 case ARM::VLD3q8_UPD: 1980 case ARM::VLD3q16_UPD: 1981 case ARM::VLD3q32_UPD: 1982 case ARM::VLD4q8: 1983 case ARM::VLD4q16: 1984 case ARM::VLD4q32: 1985 case ARM::VLD4q8_UPD: 1986 case ARM::VLD4q16_UPD: 1987 case ARM::VLD4q32_UPD: 1988 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1989 return MCDisassembler::Fail; 1990 default: 1991 break; 1992 } 1993 1994 // Third output register 1995 switch(Inst.getOpcode()) { 1996 case ARM::VLD3d8: 1997 case ARM::VLD3d16: 1998 case ARM::VLD3d32: 1999 case ARM::VLD3d8_UPD: 2000 case ARM::VLD3d16_UPD: 2001 case ARM::VLD3d32_UPD: 2002 case ARM::VLD4d8: 2003 case ARM::VLD4d16: 2004 case ARM::VLD4d32: 2005 case ARM::VLD4d8_UPD: 2006 case ARM::VLD4d16_UPD: 2007 case ARM::VLD4d32_UPD: 2008 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2009 return MCDisassembler::Fail; 2010 break; 2011 case ARM::VLD3q8: 2012 case ARM::VLD3q16: 2013 case ARM::VLD3q32: 2014 case ARM::VLD3q8_UPD: 2015 case ARM::VLD3q16_UPD: 2016 case ARM::VLD3q32_UPD: 2017 case ARM::VLD4q8: 2018 case ARM::VLD4q16: 2019 case ARM::VLD4q32: 2020 case ARM::VLD4q8_UPD: 2021 case ARM::VLD4q16_UPD: 2022 case ARM::VLD4q32_UPD: 2023 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2024 return MCDisassembler::Fail; 2025 break; 2026 default: 2027 break; 2028 } 2029 2030 // Fourth output register 2031 switch (Inst.getOpcode()) { 2032 case ARM::VLD4d8: 2033 case ARM::VLD4d16: 2034 case ARM::VLD4d32: 2035 case ARM::VLD4d8_UPD: 2036 case ARM::VLD4d16_UPD: 2037 case ARM::VLD4d32_UPD: 2038 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2039 return MCDisassembler::Fail; 2040 break; 2041 case ARM::VLD4q8: 2042 case ARM::VLD4q16: 2043 case ARM::VLD4q32: 2044 case ARM::VLD4q8_UPD: 2045 case ARM::VLD4q16_UPD: 2046 case ARM::VLD4q32_UPD: 2047 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2048 return MCDisassembler::Fail; 2049 break; 2050 default: 2051 break; 2052 } 2053 2054 // Writeback operand 2055 switch (Inst.getOpcode()) { 2056 case ARM::VLD1d8wb_fixed: 2057 case ARM::VLD1d16wb_fixed: 2058 case ARM::VLD1d32wb_fixed: 2059 case ARM::VLD1d64wb_fixed: 2060 case ARM::VLD1d8wb_register: 2061 case ARM::VLD1d16wb_register: 2062 case ARM::VLD1d32wb_register: 2063 case ARM::VLD1d64wb_register: 2064 case ARM::VLD1q8wb_fixed: 2065 case ARM::VLD1q16wb_fixed: 2066 case ARM::VLD1q32wb_fixed: 2067 case ARM::VLD1q64wb_fixed: 2068 case ARM::VLD1q8wb_register: 2069 case ARM::VLD1q16wb_register: 2070 case ARM::VLD1q32wb_register: 2071 case ARM::VLD1q64wb_register: 2072 case ARM::VLD1d8Twb_fixed: 2073 case ARM::VLD1d8Twb_register: 2074 case ARM::VLD1d16Twb_fixed: 2075 case ARM::VLD1d16Twb_register: 2076 case ARM::VLD1d32Twb_fixed: 2077 case ARM::VLD1d32Twb_register: 2078 case ARM::VLD1d64Twb_fixed: 2079 case ARM::VLD1d64Twb_register: 2080 case ARM::VLD1d8Qwb_fixed: 2081 case ARM::VLD1d8Qwb_register: 2082 case ARM::VLD1d16Qwb_fixed: 2083 case ARM::VLD1d16Qwb_register: 2084 case ARM::VLD1d32Qwb_fixed: 2085 case ARM::VLD1d32Qwb_register: 2086 case ARM::VLD1d64Qwb_fixed: 2087 case ARM::VLD1d64Qwb_register: 2088 case ARM::VLD2d8_UPD: 2089 case ARM::VLD2d16_UPD: 2090 case ARM::VLD2d32_UPD: 2091 case ARM::VLD2q8_UPD: 2092 case ARM::VLD2q16_UPD: 2093 case ARM::VLD2q32_UPD: 2094 case ARM::VLD2b8_UPD: 2095 case ARM::VLD2b16_UPD: 2096 case ARM::VLD2b32_UPD: 2097 case ARM::VLD3d8_UPD: 2098 case ARM::VLD3d16_UPD: 2099 case ARM::VLD3d32_UPD: 2100 case ARM::VLD3q8_UPD: 2101 case ARM::VLD3q16_UPD: 2102 case ARM::VLD3q32_UPD: 2103 case ARM::VLD4d8_UPD: 2104 case ARM::VLD4d16_UPD: 2105 case ARM::VLD4d32_UPD: 2106 case ARM::VLD4q8_UPD: 2107 case ARM::VLD4q16_UPD: 2108 case ARM::VLD4q32_UPD: 2109 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 break; 2112 default: 2113 break; 2114 } 2115 2116 // AddrMode6 Base (register+alignment) 2117 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2118 return MCDisassembler::Fail; 2119 2120 // AddrMode6 Offset (register) 2121 switch (Inst.getOpcode()) { 2122 default: 2123 // The below have been updated to have explicit am6offset split 2124 // between fixed and register offset. For those instructions not 2125 // yet updated, we need to add an additional reg0 operand for the 2126 // fixed variant. 2127 // 2128 // The fixed offset encodes as Rm == 0xd, so we check for that. 2129 if (Rm == 0xd) { 2130 Inst.addOperand(MCOperand::CreateReg(0)); 2131 break; 2132 } 2133 // Fall through to handle the register offset variant. 2134 case ARM::VLD1d8wb_fixed: 2135 case ARM::VLD1d16wb_fixed: 2136 case ARM::VLD1d32wb_fixed: 2137 case ARM::VLD1d64wb_fixed: 2138 case ARM::VLD1d8Twb_fixed: 2139 case ARM::VLD1d16Twb_fixed: 2140 case ARM::VLD1d32Twb_fixed: 2141 case ARM::VLD1d64Twb_fixed: 2142 case ARM::VLD1d8Qwb_fixed: 2143 case ARM::VLD1d16Qwb_fixed: 2144 case ARM::VLD1d32Qwb_fixed: 2145 case ARM::VLD1d64Qwb_fixed: 2146 case ARM::VLD1d8wb_register: 2147 case ARM::VLD1d16wb_register: 2148 case ARM::VLD1d32wb_register: 2149 case ARM::VLD1d64wb_register: 2150 case ARM::VLD1q8wb_fixed: 2151 case ARM::VLD1q16wb_fixed: 2152 case ARM::VLD1q32wb_fixed: 2153 case ARM::VLD1q64wb_fixed: 2154 case ARM::VLD1q8wb_register: 2155 case ARM::VLD1q16wb_register: 2156 case ARM::VLD1q32wb_register: 2157 case ARM::VLD1q64wb_register: 2158 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2159 // variant encodes Rm == 0xf. Anything else is a register offset post- 2160 // increment and we need to add the register operand to the instruction. 2161 if (Rm != 0xD && Rm != 0xF && 2162 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2163 return MCDisassembler::Fail; 2164 break; 2165 } 2166 2167 return S; 2168 } 2169 2170 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2171 uint64_t Address, const void *Decoder) { 2172 DecodeStatus S = MCDisassembler::Success; 2173 2174 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2175 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2176 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2177 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2178 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2179 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2180 2181 // Writeback Operand 2182 switch (Inst.getOpcode()) { 2183 case ARM::VST1d8wb_fixed: 2184 case ARM::VST1d16wb_fixed: 2185 case ARM::VST1d32wb_fixed: 2186 case ARM::VST1d64wb_fixed: 2187 case ARM::VST1d8wb_register: 2188 case ARM::VST1d16wb_register: 2189 case ARM::VST1d32wb_register: 2190 case ARM::VST1d64wb_register: 2191 case ARM::VST1q8wb_fixed: 2192 case ARM::VST1q16wb_fixed: 2193 case ARM::VST1q32wb_fixed: 2194 case ARM::VST1q64wb_fixed: 2195 case ARM::VST1q8wb_register: 2196 case ARM::VST1q16wb_register: 2197 case ARM::VST1q32wb_register: 2198 case ARM::VST1q64wb_register: 2199 case ARM::VST1d8Twb_fixed: 2200 case ARM::VST1d16Twb_fixed: 2201 case ARM::VST1d32Twb_fixed: 2202 case ARM::VST1d64Twb_fixed: 2203 case ARM::VST1d8Twb_register: 2204 case ARM::VST1d16Twb_register: 2205 case ARM::VST1d32Twb_register: 2206 case ARM::VST1d64Twb_register: 2207 case ARM::VST1d8Qwb_fixed: 2208 case ARM::VST1d16Qwb_fixed: 2209 case ARM::VST1d32Qwb_fixed: 2210 case ARM::VST1d64Qwb_fixed: 2211 case ARM::VST1d8Qwb_register: 2212 case ARM::VST1d16Qwb_register: 2213 case ARM::VST1d32Qwb_register: 2214 case ARM::VST1d64Qwb_register: 2215 case ARM::VST2d8_UPD: 2216 case ARM::VST2d16_UPD: 2217 case ARM::VST2d32_UPD: 2218 case ARM::VST2q8_UPD: 2219 case ARM::VST2q16_UPD: 2220 case ARM::VST2q32_UPD: 2221 case ARM::VST2b8_UPD: 2222 case ARM::VST2b16_UPD: 2223 case ARM::VST2b32_UPD: 2224 case ARM::VST3d8_UPD: 2225 case ARM::VST3d16_UPD: 2226 case ARM::VST3d32_UPD: 2227 case ARM::VST3q8_UPD: 2228 case ARM::VST3q16_UPD: 2229 case ARM::VST3q32_UPD: 2230 case ARM::VST4d8_UPD: 2231 case ARM::VST4d16_UPD: 2232 case ARM::VST4d32_UPD: 2233 case ARM::VST4q8_UPD: 2234 case ARM::VST4q16_UPD: 2235 case ARM::VST4q32_UPD: 2236 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2237 return MCDisassembler::Fail; 2238 break; 2239 default: 2240 break; 2241 } 2242 2243 // AddrMode6 Base (register+alignment) 2244 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2245 return MCDisassembler::Fail; 2246 2247 // AddrMode6 Offset (register) 2248 switch (Inst.getOpcode()) { 2249 default: 2250 if (Rm == 0xD) 2251 Inst.addOperand(MCOperand::CreateReg(0)); 2252 else if (Rm != 0xF) { 2253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2254 return MCDisassembler::Fail; 2255 } 2256 break; 2257 case ARM::VST1d8wb_fixed: 2258 case ARM::VST1d16wb_fixed: 2259 case ARM::VST1d32wb_fixed: 2260 case ARM::VST1d64wb_fixed: 2261 case ARM::VST1q8wb_fixed: 2262 case ARM::VST1q16wb_fixed: 2263 case ARM::VST1q32wb_fixed: 2264 case ARM::VST1q64wb_fixed: 2265 break; 2266 } 2267 2268 2269 // First input register 2270 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2271 return MCDisassembler::Fail; 2272 2273 // Second input register 2274 switch (Inst.getOpcode()) { 2275 case ARM::VST2d8: 2276 case ARM::VST2d16: 2277 case ARM::VST2d32: 2278 case ARM::VST2d8_UPD: 2279 case ARM::VST2d16_UPD: 2280 case ARM::VST2d32_UPD: 2281 case ARM::VST2q8: 2282 case ARM::VST2q16: 2283 case ARM::VST2q32: 2284 case ARM::VST2q8_UPD: 2285 case ARM::VST2q16_UPD: 2286 case ARM::VST2q32_UPD: 2287 case ARM::VST3d8: 2288 case ARM::VST3d16: 2289 case ARM::VST3d32: 2290 case ARM::VST3d8_UPD: 2291 case ARM::VST3d16_UPD: 2292 case ARM::VST3d32_UPD: 2293 case ARM::VST4d8: 2294 case ARM::VST4d16: 2295 case ARM::VST4d32: 2296 case ARM::VST4d8_UPD: 2297 case ARM::VST4d16_UPD: 2298 case ARM::VST4d32_UPD: 2299 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2300 return MCDisassembler::Fail; 2301 break; 2302 case ARM::VST2b8: 2303 case ARM::VST2b16: 2304 case ARM::VST2b32: 2305 case ARM::VST2b8_UPD: 2306 case ARM::VST2b16_UPD: 2307 case ARM::VST2b32_UPD: 2308 case ARM::VST3q8: 2309 case ARM::VST3q16: 2310 case ARM::VST3q32: 2311 case ARM::VST3q8_UPD: 2312 case ARM::VST3q16_UPD: 2313 case ARM::VST3q32_UPD: 2314 case ARM::VST4q8: 2315 case ARM::VST4q16: 2316 case ARM::VST4q32: 2317 case ARM::VST4q8_UPD: 2318 case ARM::VST4q16_UPD: 2319 case ARM::VST4q32_UPD: 2320 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2321 return MCDisassembler::Fail; 2322 break; 2323 default: 2324 break; 2325 } 2326 2327 // Third input register 2328 switch (Inst.getOpcode()) { 2329 case ARM::VST2q8: 2330 case ARM::VST2q16: 2331 case ARM::VST2q32: 2332 case ARM::VST2q8_UPD: 2333 case ARM::VST2q16_UPD: 2334 case ARM::VST2q32_UPD: 2335 case ARM::VST3d8: 2336 case ARM::VST3d16: 2337 case ARM::VST3d32: 2338 case ARM::VST3d8_UPD: 2339 case ARM::VST3d16_UPD: 2340 case ARM::VST3d32_UPD: 2341 case ARM::VST4d8: 2342 case ARM::VST4d16: 2343 case ARM::VST4d32: 2344 case ARM::VST4d8_UPD: 2345 case ARM::VST4d16_UPD: 2346 case ARM::VST4d32_UPD: 2347 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2348 return MCDisassembler::Fail; 2349 break; 2350 case ARM::VST3q8: 2351 case ARM::VST3q16: 2352 case ARM::VST3q32: 2353 case ARM::VST3q8_UPD: 2354 case ARM::VST3q16_UPD: 2355 case ARM::VST3q32_UPD: 2356 case ARM::VST4q8: 2357 case ARM::VST4q16: 2358 case ARM::VST4q32: 2359 case ARM::VST4q8_UPD: 2360 case ARM::VST4q16_UPD: 2361 case ARM::VST4q32_UPD: 2362 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2363 return MCDisassembler::Fail; 2364 break; 2365 default: 2366 break; 2367 } 2368 2369 // Fourth input register 2370 switch (Inst.getOpcode()) { 2371 case ARM::VST2q8: 2372 case ARM::VST2q16: 2373 case ARM::VST2q32: 2374 case ARM::VST2q8_UPD: 2375 case ARM::VST2q16_UPD: 2376 case ARM::VST2q32_UPD: 2377 case ARM::VST4d8: 2378 case ARM::VST4d16: 2379 case ARM::VST4d32: 2380 case ARM::VST4d8_UPD: 2381 case ARM::VST4d16_UPD: 2382 case ARM::VST4d32_UPD: 2383 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2384 return MCDisassembler::Fail; 2385 break; 2386 case ARM::VST4q8: 2387 case ARM::VST4q16: 2388 case ARM::VST4q32: 2389 case ARM::VST4q8_UPD: 2390 case ARM::VST4q16_UPD: 2391 case ARM::VST4q32_UPD: 2392 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2393 return MCDisassembler::Fail; 2394 break; 2395 default: 2396 break; 2397 } 2398 2399 return S; 2400 } 2401 2402 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2403 uint64_t Address, const void *Decoder) { 2404 DecodeStatus S = MCDisassembler::Success; 2405 2406 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2407 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2408 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2409 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2410 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2411 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2412 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2413 2414 align *= (1 << size); 2415 2416 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2417 return MCDisassembler::Fail; 2418 if (Rm != 0xF) { 2419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2420 return MCDisassembler::Fail; 2421 } 2422 2423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2424 return MCDisassembler::Fail; 2425 Inst.addOperand(MCOperand::CreateImm(align)); 2426 2427 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2428 // variant encodes Rm == 0xf. Anything else is a register offset post- 2429 // increment and we need to add the register operand to the instruction. 2430 if (Rm != 0xD && Rm != 0xF && 2431 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2432 return MCDisassembler::Fail; 2433 2434 return S; 2435 } 2436 2437 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2438 uint64_t Address, const void *Decoder) { 2439 DecodeStatus S = MCDisassembler::Success; 2440 2441 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2442 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2443 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2444 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2445 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2446 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2447 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2448 align *= 2*size; 2449 2450 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2451 return MCDisassembler::Fail; 2452 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2453 return MCDisassembler::Fail; 2454 if (Rm != 0xF) { 2455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2456 return MCDisassembler::Fail; 2457 } 2458 2459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2460 return MCDisassembler::Fail; 2461 Inst.addOperand(MCOperand::CreateImm(align)); 2462 2463 if (Rm == 0xD) 2464 Inst.addOperand(MCOperand::CreateReg(0)); 2465 else if (Rm != 0xF) { 2466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2467 return MCDisassembler::Fail; 2468 } 2469 2470 return S; 2471 } 2472 2473 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2474 uint64_t Address, const void *Decoder) { 2475 DecodeStatus S = MCDisassembler::Success; 2476 2477 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2478 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2479 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2480 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2481 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2482 2483 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2484 return MCDisassembler::Fail; 2485 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2486 return MCDisassembler::Fail; 2487 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2488 return MCDisassembler::Fail; 2489 if (Rm != 0xF) { 2490 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2491 return MCDisassembler::Fail; 2492 } 2493 2494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2495 return MCDisassembler::Fail; 2496 Inst.addOperand(MCOperand::CreateImm(0)); 2497 2498 if (Rm == 0xD) 2499 Inst.addOperand(MCOperand::CreateReg(0)); 2500 else if (Rm != 0xF) { 2501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2502 return MCDisassembler::Fail; 2503 } 2504 2505 return S; 2506 } 2507 2508 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2509 uint64_t Address, const void *Decoder) { 2510 DecodeStatus S = MCDisassembler::Success; 2511 2512 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2513 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2514 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2515 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2516 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2517 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2518 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2519 2520 if (size == 0x3) { 2521 size = 4; 2522 align = 16; 2523 } else { 2524 if (size == 2) { 2525 size = 1 << size; 2526 align *= 8; 2527 } else { 2528 size = 1 << size; 2529 align *= 4*size; 2530 } 2531 } 2532 2533 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2536 return MCDisassembler::Fail; 2537 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2538 return MCDisassembler::Fail; 2539 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2540 return MCDisassembler::Fail; 2541 if (Rm != 0xF) { 2542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2543 return MCDisassembler::Fail; 2544 } 2545 2546 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2547 return MCDisassembler::Fail; 2548 Inst.addOperand(MCOperand::CreateImm(align)); 2549 2550 if (Rm == 0xD) 2551 Inst.addOperand(MCOperand::CreateReg(0)); 2552 else if (Rm != 0xF) { 2553 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2554 return MCDisassembler::Fail; 2555 } 2556 2557 return S; 2558 } 2559 2560 static DecodeStatus 2561 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2562 uint64_t Address, const void *Decoder) { 2563 DecodeStatus S = MCDisassembler::Success; 2564 2565 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2566 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2567 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2568 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2569 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2570 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2571 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2572 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2573 2574 if (Q) { 2575 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2576 return MCDisassembler::Fail; 2577 } else { 2578 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2579 return MCDisassembler::Fail; 2580 } 2581 2582 Inst.addOperand(MCOperand::CreateImm(imm)); 2583 2584 switch (Inst.getOpcode()) { 2585 case ARM::VORRiv4i16: 2586 case ARM::VORRiv2i32: 2587 case ARM::VBICiv4i16: 2588 case ARM::VBICiv2i32: 2589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2590 return MCDisassembler::Fail; 2591 break; 2592 case ARM::VORRiv8i16: 2593 case ARM::VORRiv4i32: 2594 case ARM::VBICiv8i16: 2595 case ARM::VBICiv4i32: 2596 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2597 return MCDisassembler::Fail; 2598 break; 2599 default: 2600 break; 2601 } 2602 2603 return S; 2604 } 2605 2606 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2607 uint64_t Address, const void *Decoder) { 2608 DecodeStatus S = MCDisassembler::Success; 2609 2610 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2611 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2612 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2613 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2614 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2615 2616 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2617 return MCDisassembler::Fail; 2618 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2619 return MCDisassembler::Fail; 2620 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2621 2622 return S; 2623 } 2624 2625 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2626 uint64_t Address, const void *Decoder) { 2627 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2628 return MCDisassembler::Success; 2629 } 2630 2631 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2632 uint64_t Address, const void *Decoder) { 2633 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2634 return MCDisassembler::Success; 2635 } 2636 2637 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2638 uint64_t Address, const void *Decoder) { 2639 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2640 return MCDisassembler::Success; 2641 } 2642 2643 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2644 uint64_t Address, const void *Decoder) { 2645 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2646 return MCDisassembler::Success; 2647 } 2648 2649 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2650 uint64_t Address, const void *Decoder) { 2651 DecodeStatus S = MCDisassembler::Success; 2652 2653 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2654 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2655 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2656 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2657 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2658 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2659 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2660 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2661 2662 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2663 return MCDisassembler::Fail; 2664 if (op) { 2665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2666 return MCDisassembler::Fail; // Writeback 2667 } 2668 2669 for (unsigned i = 0; i < length; ++i) { 2670 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2671 return MCDisassembler::Fail; 2672 } 2673 2674 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2675 return MCDisassembler::Fail; 2676 2677 return S; 2678 } 2679 2680 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2681 uint64_t Address, const void *Decoder) { 2682 DecodeStatus S = MCDisassembler::Success; 2683 2684 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2685 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2686 2687 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2688 return MCDisassembler::Fail; 2689 2690 switch(Inst.getOpcode()) { 2691 default: 2692 return MCDisassembler::Fail; 2693 case ARM::tADR: 2694 break; // tADR does not explicitly represent the PC as an operand. 2695 case ARM::tADDrSPi: 2696 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2697 break; 2698 } 2699 2700 Inst.addOperand(MCOperand::CreateImm(imm)); 2701 return S; 2702 } 2703 2704 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2705 uint64_t Address, const void *Decoder) { 2706 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2707 return MCDisassembler::Success; 2708 } 2709 2710 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2711 uint64_t Address, const void *Decoder) { 2712 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2713 return MCDisassembler::Success; 2714 } 2715 2716 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2717 uint64_t Address, const void *Decoder) { 2718 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2719 return MCDisassembler::Success; 2720 } 2721 2722 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2723 uint64_t Address, const void *Decoder) { 2724 DecodeStatus S = MCDisassembler::Success; 2725 2726 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2727 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2728 2729 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2730 return MCDisassembler::Fail; 2731 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2732 return MCDisassembler::Fail; 2733 2734 return S; 2735 } 2736 2737 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2738 uint64_t Address, const void *Decoder) { 2739 DecodeStatus S = MCDisassembler::Success; 2740 2741 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2742 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2743 2744 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2745 return MCDisassembler::Fail; 2746 Inst.addOperand(MCOperand::CreateImm(imm)); 2747 2748 return S; 2749 } 2750 2751 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2752 uint64_t Address, const void *Decoder) { 2753 unsigned imm = Val << 2; 2754 2755 Inst.addOperand(MCOperand::CreateImm(imm)); 2756 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2757 2758 return MCDisassembler::Success; 2759 } 2760 2761 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2762 uint64_t Address, const void *Decoder) { 2763 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2764 Inst.addOperand(MCOperand::CreateImm(Val)); 2765 2766 return MCDisassembler::Success; 2767 } 2768 2769 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2770 uint64_t Address, const void *Decoder) { 2771 DecodeStatus S = MCDisassembler::Success; 2772 2773 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2774 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2775 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2776 2777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2778 return MCDisassembler::Fail; 2779 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2780 return MCDisassembler::Fail; 2781 Inst.addOperand(MCOperand::CreateImm(imm)); 2782 2783 return S; 2784 } 2785 2786 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2787 uint64_t Address, const void *Decoder) { 2788 DecodeStatus S = MCDisassembler::Success; 2789 2790 switch (Inst.getOpcode()) { 2791 case ARM::t2PLDs: 2792 case ARM::t2PLDWs: 2793 case ARM::t2PLIs: 2794 break; 2795 default: { 2796 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2797 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2798 return MCDisassembler::Fail; 2799 } 2800 } 2801 2802 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2803 if (Rn == 0xF) { 2804 switch (Inst.getOpcode()) { 2805 case ARM::t2LDRBs: 2806 Inst.setOpcode(ARM::t2LDRBpci); 2807 break; 2808 case ARM::t2LDRHs: 2809 Inst.setOpcode(ARM::t2LDRHpci); 2810 break; 2811 case ARM::t2LDRSHs: 2812 Inst.setOpcode(ARM::t2LDRSHpci); 2813 break; 2814 case ARM::t2LDRSBs: 2815 Inst.setOpcode(ARM::t2LDRSBpci); 2816 break; 2817 case ARM::t2PLDs: 2818 Inst.setOpcode(ARM::t2PLDi12); 2819 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2820 break; 2821 default: 2822 return MCDisassembler::Fail; 2823 } 2824 2825 int imm = fieldFromInstruction32(Insn, 0, 12); 2826 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2827 Inst.addOperand(MCOperand::CreateImm(imm)); 2828 2829 return S; 2830 } 2831 2832 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2833 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2834 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2835 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 2838 return S; 2839 } 2840 2841 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2842 uint64_t Address, const void *Decoder) { 2843 int imm = Val & 0xFF; 2844 if (!(Val & 0x100)) imm *= -1; 2845 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2846 2847 return MCDisassembler::Success; 2848 } 2849 2850 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2851 uint64_t Address, const void *Decoder) { 2852 DecodeStatus S = MCDisassembler::Success; 2853 2854 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2855 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2856 2857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2858 return MCDisassembler::Fail; 2859 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2860 return MCDisassembler::Fail; 2861 2862 return S; 2863 } 2864 2865 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2866 uint64_t Address, const void *Decoder) { 2867 DecodeStatus S = MCDisassembler::Success; 2868 2869 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2870 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2871 2872 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2873 return MCDisassembler::Fail; 2874 2875 Inst.addOperand(MCOperand::CreateImm(imm)); 2876 2877 return S; 2878 } 2879 2880 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2881 uint64_t Address, const void *Decoder) { 2882 int imm = Val & 0xFF; 2883 if (Val == 0) 2884 imm = INT32_MIN; 2885 else if (!(Val & 0x100)) 2886 imm *= -1; 2887 Inst.addOperand(MCOperand::CreateImm(imm)); 2888 2889 return MCDisassembler::Success; 2890 } 2891 2892 2893 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2894 uint64_t Address, const void *Decoder) { 2895 DecodeStatus S = MCDisassembler::Success; 2896 2897 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2898 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2899 2900 // Some instructions always use an additive offset. 2901 switch (Inst.getOpcode()) { 2902 case ARM::t2LDRT: 2903 case ARM::t2LDRBT: 2904 case ARM::t2LDRHT: 2905 case ARM::t2LDRSBT: 2906 case ARM::t2LDRSHT: 2907 case ARM::t2STRT: 2908 case ARM::t2STRBT: 2909 case ARM::t2STRHT: 2910 imm |= 0x100; 2911 break; 2912 default: 2913 break; 2914 } 2915 2916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2917 return MCDisassembler::Fail; 2918 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2919 return MCDisassembler::Fail; 2920 2921 return S; 2922 } 2923 2924 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2925 uint64_t Address, const void *Decoder) { 2926 DecodeStatus S = MCDisassembler::Success; 2927 2928 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2929 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2930 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2931 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2932 addr |= Rn << 9; 2933 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2934 2935 if (!load) { 2936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2937 return MCDisassembler::Fail; 2938 } 2939 2940 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2941 return MCDisassembler::Fail; 2942 2943 if (load) { 2944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2945 return MCDisassembler::Fail; 2946 } 2947 2948 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2949 return MCDisassembler::Fail; 2950 2951 return S; 2952 } 2953 2954 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2955 uint64_t Address, const void *Decoder) { 2956 DecodeStatus S = MCDisassembler::Success; 2957 2958 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2959 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2960 2961 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2962 return MCDisassembler::Fail; 2963 Inst.addOperand(MCOperand::CreateImm(imm)); 2964 2965 return S; 2966 } 2967 2968 2969 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2970 uint64_t Address, const void *Decoder) { 2971 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2972 2973 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2974 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2975 Inst.addOperand(MCOperand::CreateImm(imm)); 2976 2977 return MCDisassembler::Success; 2978 } 2979 2980 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2981 uint64_t Address, const void *Decoder) { 2982 DecodeStatus S = MCDisassembler::Success; 2983 2984 if (Inst.getOpcode() == ARM::tADDrSP) { 2985 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2986 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2987 2988 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2989 return MCDisassembler::Fail; 2990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2991 return MCDisassembler::Fail; 2992 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2993 } else if (Inst.getOpcode() == ARM::tADDspr) { 2994 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2995 2996 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2997 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2999 return MCDisassembler::Fail; 3000 } 3001 3002 return S; 3003 } 3004 3005 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 3006 uint64_t Address, const void *Decoder) { 3007 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3008 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3009 3010 Inst.addOperand(MCOperand::CreateImm(imod)); 3011 Inst.addOperand(MCOperand::CreateImm(flags)); 3012 3013 return MCDisassembler::Success; 3014 } 3015 3016 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3017 uint64_t Address, const void *Decoder) { 3018 DecodeStatus S = MCDisassembler::Success; 3019 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3020 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3021 3022 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3023 return MCDisassembler::Fail; 3024 Inst.addOperand(MCOperand::CreateImm(add)); 3025 3026 return S; 3027 } 3028 3029 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3030 uint64_t Address, const void *Decoder) { 3031 if (!tryAddingSymbolicOperand(Address, 3032 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3033 true, 4, Inst, Decoder)) 3034 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3035 return MCDisassembler::Success; 3036 } 3037 3038 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3039 uint64_t Address, const void *Decoder) { 3040 if (Val == 0xA || Val == 0xB) 3041 return MCDisassembler::Fail; 3042 3043 Inst.addOperand(MCOperand::CreateImm(Val)); 3044 return MCDisassembler::Success; 3045 } 3046 3047 static DecodeStatus 3048 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3049 uint64_t Address, const void *Decoder) { 3050 DecodeStatus S = MCDisassembler::Success; 3051 3052 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3053 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3054 3055 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3057 return MCDisassembler::Fail; 3058 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3059 return MCDisassembler::Fail; 3060 return S; 3061 } 3062 3063 static DecodeStatus 3064 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3065 uint64_t Address, const void *Decoder) { 3066 DecodeStatus S = MCDisassembler::Success; 3067 3068 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3069 if (pred == 0xE || pred == 0xF) { 3070 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3071 switch (opc) { 3072 default: 3073 return MCDisassembler::Fail; 3074 case 0xf3bf8f4: 3075 Inst.setOpcode(ARM::t2DSB); 3076 break; 3077 case 0xf3bf8f5: 3078 Inst.setOpcode(ARM::t2DMB); 3079 break; 3080 case 0xf3bf8f6: 3081 Inst.setOpcode(ARM::t2ISB); 3082 break; 3083 } 3084 3085 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3086 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3087 } 3088 3089 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3090 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3091 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3092 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3093 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3094 3095 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3096 return MCDisassembler::Fail; 3097 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3098 return MCDisassembler::Fail; 3099 3100 return S; 3101 } 3102 3103 // Decode a shifted immediate operand. These basically consist 3104 // of an 8-bit value, and a 4-bit directive that specifies either 3105 // a splat operation or a rotation. 3106 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3107 uint64_t Address, const void *Decoder) { 3108 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3109 if (ctrl == 0) { 3110 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3111 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3112 switch (byte) { 3113 case 0: 3114 Inst.addOperand(MCOperand::CreateImm(imm)); 3115 break; 3116 case 1: 3117 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3118 break; 3119 case 2: 3120 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3121 break; 3122 case 3: 3123 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3124 (imm << 8) | imm)); 3125 break; 3126 } 3127 } else { 3128 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3129 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3130 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3131 Inst.addOperand(MCOperand::CreateImm(imm)); 3132 } 3133 3134 return MCDisassembler::Success; 3135 } 3136 3137 static DecodeStatus 3138 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3139 uint64_t Address, const void *Decoder){ 3140 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3141 return MCDisassembler::Success; 3142 } 3143 3144 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3145 uint64_t Address, const void *Decoder){ 3146 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3147 return MCDisassembler::Success; 3148 } 3149 3150 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3151 uint64_t Address, const void *Decoder) { 3152 switch (Val) { 3153 default: 3154 return MCDisassembler::Fail; 3155 case 0xF: // SY 3156 case 0xE: // ST 3157 case 0xB: // ISH 3158 case 0xA: // ISHST 3159 case 0x7: // NSH 3160 case 0x6: // NSHST 3161 case 0x3: // OSH 3162 case 0x2: // OSHST 3163 break; 3164 } 3165 3166 Inst.addOperand(MCOperand::CreateImm(Val)); 3167 return MCDisassembler::Success; 3168 } 3169 3170 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3171 uint64_t Address, const void *Decoder) { 3172 if (!Val) return MCDisassembler::Fail; 3173 Inst.addOperand(MCOperand::CreateImm(Val)); 3174 return MCDisassembler::Success; 3175 } 3176 3177 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3178 uint64_t Address, const void *Decoder) { 3179 DecodeStatus S = MCDisassembler::Success; 3180 3181 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3182 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3183 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3184 3185 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3186 3187 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3188 return MCDisassembler::Fail; 3189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3192 return MCDisassembler::Fail; 3193 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3194 return MCDisassembler::Fail; 3195 3196 return S; 3197 } 3198 3199 3200 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3201 uint64_t Address, const void *Decoder){ 3202 DecodeStatus S = MCDisassembler::Success; 3203 3204 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3205 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3206 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3207 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3208 3209 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3210 return MCDisassembler::Fail; 3211 3212 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3213 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3214 3215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3216 return MCDisassembler::Fail; 3217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3218 return MCDisassembler::Fail; 3219 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3220 return MCDisassembler::Fail; 3221 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3222 return MCDisassembler::Fail; 3223 3224 return S; 3225 } 3226 3227 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3228 uint64_t Address, const void *Decoder) { 3229 DecodeStatus S = MCDisassembler::Success; 3230 3231 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3232 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3233 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3234 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3235 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3236 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3237 3238 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3239 3240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3241 return MCDisassembler::Fail; 3242 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3243 return MCDisassembler::Fail; 3244 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3245 return MCDisassembler::Fail; 3246 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3247 return MCDisassembler::Fail; 3248 3249 return S; 3250 } 3251 3252 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3253 uint64_t Address, const void *Decoder) { 3254 DecodeStatus S = MCDisassembler::Success; 3255 3256 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3257 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3258 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3259 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3260 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3261 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3262 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3263 3264 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3265 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3266 3267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3268 return MCDisassembler::Fail; 3269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3270 return MCDisassembler::Fail; 3271 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3272 return MCDisassembler::Fail; 3273 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3274 return MCDisassembler::Fail; 3275 3276 return S; 3277 } 3278 3279 3280 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3281 uint64_t Address, const void *Decoder) { 3282 DecodeStatus S = MCDisassembler::Success; 3283 3284 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3285 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3286 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3287 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3288 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3289 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3290 3291 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3292 3293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3294 return MCDisassembler::Fail; 3295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3296 return MCDisassembler::Fail; 3297 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3298 return MCDisassembler::Fail; 3299 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3300 return MCDisassembler::Fail; 3301 3302 return S; 3303 } 3304 3305 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3306 uint64_t Address, const void *Decoder) { 3307 DecodeStatus S = MCDisassembler::Success; 3308 3309 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3310 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3311 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3312 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3313 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3314 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3315 3316 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3317 3318 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3319 return MCDisassembler::Fail; 3320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3321 return MCDisassembler::Fail; 3322 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3323 return MCDisassembler::Fail; 3324 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3325 return MCDisassembler::Fail; 3326 3327 return S; 3328 } 3329 3330 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3331 uint64_t Address, const void *Decoder) { 3332 DecodeStatus S = MCDisassembler::Success; 3333 3334 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3335 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3336 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3337 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3338 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3339 3340 unsigned align = 0; 3341 unsigned index = 0; 3342 switch (size) { 3343 default: 3344 return MCDisassembler::Fail; 3345 case 0: 3346 if (fieldFromInstruction32(Insn, 4, 1)) 3347 return MCDisassembler::Fail; // UNDEFINED 3348 index = fieldFromInstruction32(Insn, 5, 3); 3349 break; 3350 case 1: 3351 if (fieldFromInstruction32(Insn, 5, 1)) 3352 return MCDisassembler::Fail; // UNDEFINED 3353 index = fieldFromInstruction32(Insn, 6, 2); 3354 if (fieldFromInstruction32(Insn, 4, 1)) 3355 align = 2; 3356 break; 3357 case 2: 3358 if (fieldFromInstruction32(Insn, 6, 1)) 3359 return MCDisassembler::Fail; // UNDEFINED 3360 index = fieldFromInstruction32(Insn, 7, 1); 3361 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3362 align = 4; 3363 } 3364 3365 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 if (Rm != 0xF) { // Writeback 3368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3369 return MCDisassembler::Fail; 3370 } 3371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3372 return MCDisassembler::Fail; 3373 Inst.addOperand(MCOperand::CreateImm(align)); 3374 if (Rm != 0xF) { 3375 if (Rm != 0xD) { 3376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3377 return MCDisassembler::Fail; 3378 } else 3379 Inst.addOperand(MCOperand::CreateReg(0)); 3380 } 3381 3382 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3383 return MCDisassembler::Fail; 3384 Inst.addOperand(MCOperand::CreateImm(index)); 3385 3386 return S; 3387 } 3388 3389 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3390 uint64_t Address, const void *Decoder) { 3391 DecodeStatus S = MCDisassembler::Success; 3392 3393 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3394 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3395 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3396 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3397 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3398 3399 unsigned align = 0; 3400 unsigned index = 0; 3401 switch (size) { 3402 default: 3403 return MCDisassembler::Fail; 3404 case 0: 3405 if (fieldFromInstruction32(Insn, 4, 1)) 3406 return MCDisassembler::Fail; // UNDEFINED 3407 index = fieldFromInstruction32(Insn, 5, 3); 3408 break; 3409 case 1: 3410 if (fieldFromInstruction32(Insn, 5, 1)) 3411 return MCDisassembler::Fail; // UNDEFINED 3412 index = fieldFromInstruction32(Insn, 6, 2); 3413 if (fieldFromInstruction32(Insn, 4, 1)) 3414 align = 2; 3415 break; 3416 case 2: 3417 if (fieldFromInstruction32(Insn, 6, 1)) 3418 return MCDisassembler::Fail; // UNDEFINED 3419 index = fieldFromInstruction32(Insn, 7, 1); 3420 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3421 align = 4; 3422 } 3423 3424 if (Rm != 0xF) { // Writeback 3425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3426 return MCDisassembler::Fail; 3427 } 3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 Inst.addOperand(MCOperand::CreateImm(align)); 3431 if (Rm != 0xF) { 3432 if (Rm != 0xD) { 3433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 } else 3436 Inst.addOperand(MCOperand::CreateReg(0)); 3437 } 3438 3439 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3440 return MCDisassembler::Fail; 3441 Inst.addOperand(MCOperand::CreateImm(index)); 3442 3443 return S; 3444 } 3445 3446 3447 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3448 uint64_t Address, const void *Decoder) { 3449 DecodeStatus S = MCDisassembler::Success; 3450 3451 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3452 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3453 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3454 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3455 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3456 3457 unsigned align = 0; 3458 unsigned index = 0; 3459 unsigned inc = 1; 3460 switch (size) { 3461 default: 3462 return MCDisassembler::Fail; 3463 case 0: 3464 index = fieldFromInstruction32(Insn, 5, 3); 3465 if (fieldFromInstruction32(Insn, 4, 1)) 3466 align = 2; 3467 break; 3468 case 1: 3469 index = fieldFromInstruction32(Insn, 6, 2); 3470 if (fieldFromInstruction32(Insn, 4, 1)) 3471 align = 4; 3472 if (fieldFromInstruction32(Insn, 5, 1)) 3473 inc = 2; 3474 break; 3475 case 2: 3476 if (fieldFromInstruction32(Insn, 5, 1)) 3477 return MCDisassembler::Fail; // UNDEFINED 3478 index = fieldFromInstruction32(Insn, 7, 1); 3479 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3480 align = 8; 3481 if (fieldFromInstruction32(Insn, 6, 1)) 3482 inc = 2; 3483 break; 3484 } 3485 3486 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3487 return MCDisassembler::Fail; 3488 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3489 return MCDisassembler::Fail; 3490 if (Rm != 0xF) { // Writeback 3491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3492 return MCDisassembler::Fail; 3493 } 3494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3495 return MCDisassembler::Fail; 3496 Inst.addOperand(MCOperand::CreateImm(align)); 3497 if (Rm != 0xF) { 3498 if (Rm != 0xD) { 3499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 } else 3502 Inst.addOperand(MCOperand::CreateReg(0)); 3503 } 3504 3505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3506 return MCDisassembler::Fail; 3507 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3508 return MCDisassembler::Fail; 3509 Inst.addOperand(MCOperand::CreateImm(index)); 3510 3511 return S; 3512 } 3513 3514 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3515 uint64_t Address, const void *Decoder) { 3516 DecodeStatus S = MCDisassembler::Success; 3517 3518 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3519 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3520 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3521 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3522 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3523 3524 unsigned align = 0; 3525 unsigned index = 0; 3526 unsigned inc = 1; 3527 switch (size) { 3528 default: 3529 return MCDisassembler::Fail; 3530 case 0: 3531 index = fieldFromInstruction32(Insn, 5, 3); 3532 if (fieldFromInstruction32(Insn, 4, 1)) 3533 align = 2; 3534 break; 3535 case 1: 3536 index = fieldFromInstruction32(Insn, 6, 2); 3537 if (fieldFromInstruction32(Insn, 4, 1)) 3538 align = 4; 3539 if (fieldFromInstruction32(Insn, 5, 1)) 3540 inc = 2; 3541 break; 3542 case 2: 3543 if (fieldFromInstruction32(Insn, 5, 1)) 3544 return MCDisassembler::Fail; // UNDEFINED 3545 index = fieldFromInstruction32(Insn, 7, 1); 3546 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3547 align = 8; 3548 if (fieldFromInstruction32(Insn, 6, 1)) 3549 inc = 2; 3550 break; 3551 } 3552 3553 if (Rm != 0xF) { // Writeback 3554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3555 return MCDisassembler::Fail; 3556 } 3557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3558 return MCDisassembler::Fail; 3559 Inst.addOperand(MCOperand::CreateImm(align)); 3560 if (Rm != 0xF) { 3561 if (Rm != 0xD) { 3562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 } else 3565 Inst.addOperand(MCOperand::CreateReg(0)); 3566 } 3567 3568 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3569 return MCDisassembler::Fail; 3570 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3571 return MCDisassembler::Fail; 3572 Inst.addOperand(MCOperand::CreateImm(index)); 3573 3574 return S; 3575 } 3576 3577 3578 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3579 uint64_t Address, const void *Decoder) { 3580 DecodeStatus S = MCDisassembler::Success; 3581 3582 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3583 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3584 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3585 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3586 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3587 3588 unsigned align = 0; 3589 unsigned index = 0; 3590 unsigned inc = 1; 3591 switch (size) { 3592 default: 3593 return MCDisassembler::Fail; 3594 case 0: 3595 if (fieldFromInstruction32(Insn, 4, 1)) 3596 return MCDisassembler::Fail; // UNDEFINED 3597 index = fieldFromInstruction32(Insn, 5, 3); 3598 break; 3599 case 1: 3600 if (fieldFromInstruction32(Insn, 4, 1)) 3601 return MCDisassembler::Fail; // UNDEFINED 3602 index = fieldFromInstruction32(Insn, 6, 2); 3603 if (fieldFromInstruction32(Insn, 5, 1)) 3604 inc = 2; 3605 break; 3606 case 2: 3607 if (fieldFromInstruction32(Insn, 4, 2)) 3608 return MCDisassembler::Fail; // UNDEFINED 3609 index = fieldFromInstruction32(Insn, 7, 1); 3610 if (fieldFromInstruction32(Insn, 6, 1)) 3611 inc = 2; 3612 break; 3613 } 3614 3615 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3616 return MCDisassembler::Fail; 3617 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3618 return MCDisassembler::Fail; 3619 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3620 return MCDisassembler::Fail; 3621 3622 if (Rm != 0xF) { // Writeback 3623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3624 return MCDisassembler::Fail; 3625 } 3626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 Inst.addOperand(MCOperand::CreateImm(align)); 3629 if (Rm != 0xF) { 3630 if (Rm != 0xD) { 3631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3632 return MCDisassembler::Fail; 3633 } else 3634 Inst.addOperand(MCOperand::CreateReg(0)); 3635 } 3636 3637 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3638 return MCDisassembler::Fail; 3639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3640 return MCDisassembler::Fail; 3641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3642 return MCDisassembler::Fail; 3643 Inst.addOperand(MCOperand::CreateImm(index)); 3644 3645 return S; 3646 } 3647 3648 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3649 uint64_t Address, const void *Decoder) { 3650 DecodeStatus S = MCDisassembler::Success; 3651 3652 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3653 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3654 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3655 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3656 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3657 3658 unsigned align = 0; 3659 unsigned index = 0; 3660 unsigned inc = 1; 3661 switch (size) { 3662 default: 3663 return MCDisassembler::Fail; 3664 case 0: 3665 if (fieldFromInstruction32(Insn, 4, 1)) 3666 return MCDisassembler::Fail; // UNDEFINED 3667 index = fieldFromInstruction32(Insn, 5, 3); 3668 break; 3669 case 1: 3670 if (fieldFromInstruction32(Insn, 4, 1)) 3671 return MCDisassembler::Fail; // UNDEFINED 3672 index = fieldFromInstruction32(Insn, 6, 2); 3673 if (fieldFromInstruction32(Insn, 5, 1)) 3674 inc = 2; 3675 break; 3676 case 2: 3677 if (fieldFromInstruction32(Insn, 4, 2)) 3678 return MCDisassembler::Fail; // UNDEFINED 3679 index = fieldFromInstruction32(Insn, 7, 1); 3680 if (fieldFromInstruction32(Insn, 6, 1)) 3681 inc = 2; 3682 break; 3683 } 3684 3685 if (Rm != 0xF) { // Writeback 3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 } 3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 Inst.addOperand(MCOperand::CreateImm(align)); 3692 if (Rm != 0xF) { 3693 if (Rm != 0xD) { 3694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3695 return MCDisassembler::Fail; 3696 } else 3697 Inst.addOperand(MCOperand::CreateReg(0)); 3698 } 3699 3700 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3701 return MCDisassembler::Fail; 3702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3703 return MCDisassembler::Fail; 3704 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3705 return MCDisassembler::Fail; 3706 Inst.addOperand(MCOperand::CreateImm(index)); 3707 3708 return S; 3709 } 3710 3711 3712 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3713 uint64_t Address, const void *Decoder) { 3714 DecodeStatus S = MCDisassembler::Success; 3715 3716 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3717 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3718 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3719 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3720 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3721 3722 unsigned align = 0; 3723 unsigned index = 0; 3724 unsigned inc = 1; 3725 switch (size) { 3726 default: 3727 return MCDisassembler::Fail; 3728 case 0: 3729 if (fieldFromInstruction32(Insn, 4, 1)) 3730 align = 4; 3731 index = fieldFromInstruction32(Insn, 5, 3); 3732 break; 3733 case 1: 3734 if (fieldFromInstruction32(Insn, 4, 1)) 3735 align = 8; 3736 index = fieldFromInstruction32(Insn, 6, 2); 3737 if (fieldFromInstruction32(Insn, 5, 1)) 3738 inc = 2; 3739 break; 3740 case 2: 3741 if (fieldFromInstruction32(Insn, 4, 2)) 3742 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3743 index = fieldFromInstruction32(Insn, 7, 1); 3744 if (fieldFromInstruction32(Insn, 6, 1)) 3745 inc = 2; 3746 break; 3747 } 3748 3749 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3750 return MCDisassembler::Fail; 3751 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3752 return MCDisassembler::Fail; 3753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3754 return MCDisassembler::Fail; 3755 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3756 return MCDisassembler::Fail; 3757 3758 if (Rm != 0xF) { // Writeback 3759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 } 3762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3763 return MCDisassembler::Fail; 3764 Inst.addOperand(MCOperand::CreateImm(align)); 3765 if (Rm != 0xF) { 3766 if (Rm != 0xD) { 3767 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3768 return MCDisassembler::Fail; 3769 } else 3770 Inst.addOperand(MCOperand::CreateReg(0)); 3771 } 3772 3773 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3774 return MCDisassembler::Fail; 3775 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3776 return MCDisassembler::Fail; 3777 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3778 return MCDisassembler::Fail; 3779 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3780 return MCDisassembler::Fail; 3781 Inst.addOperand(MCOperand::CreateImm(index)); 3782 3783 return S; 3784 } 3785 3786 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3787 uint64_t Address, const void *Decoder) { 3788 DecodeStatus S = MCDisassembler::Success; 3789 3790 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3791 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3792 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3793 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3794 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3795 3796 unsigned align = 0; 3797 unsigned index = 0; 3798 unsigned inc = 1; 3799 switch (size) { 3800 default: 3801 return MCDisassembler::Fail; 3802 case 0: 3803 if (fieldFromInstruction32(Insn, 4, 1)) 3804 align = 4; 3805 index = fieldFromInstruction32(Insn, 5, 3); 3806 break; 3807 case 1: 3808 if (fieldFromInstruction32(Insn, 4, 1)) 3809 align = 8; 3810 index = fieldFromInstruction32(Insn, 6, 2); 3811 if (fieldFromInstruction32(Insn, 5, 1)) 3812 inc = 2; 3813 break; 3814 case 2: 3815 if (fieldFromInstruction32(Insn, 4, 2)) 3816 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3817 index = fieldFromInstruction32(Insn, 7, 1); 3818 if (fieldFromInstruction32(Insn, 6, 1)) 3819 inc = 2; 3820 break; 3821 } 3822 3823 if (Rm != 0xF) { // Writeback 3824 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3825 return MCDisassembler::Fail; 3826 } 3827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3828 return MCDisassembler::Fail; 3829 Inst.addOperand(MCOperand::CreateImm(align)); 3830 if (Rm != 0xF) { 3831 if (Rm != 0xD) { 3832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3833 return MCDisassembler::Fail; 3834 } else 3835 Inst.addOperand(MCOperand::CreateReg(0)); 3836 } 3837 3838 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3839 return MCDisassembler::Fail; 3840 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3841 return MCDisassembler::Fail; 3842 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3843 return MCDisassembler::Fail; 3844 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3845 return MCDisassembler::Fail; 3846 Inst.addOperand(MCOperand::CreateImm(index)); 3847 3848 return S; 3849 } 3850 3851 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3852 uint64_t Address, const void *Decoder) { 3853 DecodeStatus S = MCDisassembler::Success; 3854 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3855 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3856 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3857 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3858 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3859 3860 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3861 S = MCDisassembler::SoftFail; 3862 3863 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3864 return MCDisassembler::Fail; 3865 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3866 return MCDisassembler::Fail; 3867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3868 return MCDisassembler::Fail; 3869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3870 return MCDisassembler::Fail; 3871 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 3874 return S; 3875 } 3876 3877 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3878 uint64_t Address, const void *Decoder) { 3879 DecodeStatus S = MCDisassembler::Success; 3880 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3881 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3882 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3883 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3884 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3885 3886 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3887 S = MCDisassembler::SoftFail; 3888 3889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3890 return MCDisassembler::Fail; 3891 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3892 return MCDisassembler::Fail; 3893 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3894 return MCDisassembler::Fail; 3895 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3896 return MCDisassembler::Fail; 3897 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3898 return MCDisassembler::Fail; 3899 3900 return S; 3901 } 3902 3903 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3904 uint64_t Address, const void *Decoder) { 3905 DecodeStatus S = MCDisassembler::Success; 3906 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3907 // The InstPrinter needs to have the low bit of the predicate in 3908 // the mask operand to be able to print it properly. 3909 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3910 3911 if (pred == 0xF) { 3912 pred = 0xE; 3913 S = MCDisassembler::SoftFail; 3914 } 3915 3916 if ((mask & 0xF) == 0) { 3917 // Preserve the high bit of the mask, which is the low bit of 3918 // the predicate. 3919 mask &= 0x10; 3920 mask |= 0x8; 3921 S = MCDisassembler::SoftFail; 3922 } 3923 3924 Inst.addOperand(MCOperand::CreateImm(pred)); 3925 Inst.addOperand(MCOperand::CreateImm(mask)); 3926 return S; 3927 } 3928 3929 static DecodeStatus 3930 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3931 uint64_t Address, const void *Decoder) { 3932 DecodeStatus S = MCDisassembler::Success; 3933 3934 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3935 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3936 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3937 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3938 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3939 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3940 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3941 bool writeback = (W == 1) | (P == 0); 3942 3943 addr |= (U << 8) | (Rn << 9); 3944 3945 if (writeback && (Rn == Rt || Rn == Rt2)) 3946 Check(S, MCDisassembler::SoftFail); 3947 if (Rt == Rt2) 3948 Check(S, MCDisassembler::SoftFail); 3949 3950 // Rt 3951 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3952 return MCDisassembler::Fail; 3953 // Rt2 3954 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3955 return MCDisassembler::Fail; 3956 // Writeback operand 3957 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3958 return MCDisassembler::Fail; 3959 // addr 3960 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3961 return MCDisassembler::Fail; 3962 3963 return S; 3964 } 3965 3966 static DecodeStatus 3967 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3968 uint64_t Address, const void *Decoder) { 3969 DecodeStatus S = MCDisassembler::Success; 3970 3971 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3972 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3973 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3974 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3975 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3976 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3977 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3978 bool writeback = (W == 1) | (P == 0); 3979 3980 addr |= (U << 8) | (Rn << 9); 3981 3982 if (writeback && (Rn == Rt || Rn == Rt2)) 3983 Check(S, MCDisassembler::SoftFail); 3984 3985 // Writeback operand 3986 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3987 return MCDisassembler::Fail; 3988 // Rt 3989 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3990 return MCDisassembler::Fail; 3991 // Rt2 3992 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3993 return MCDisassembler::Fail; 3994 // addr 3995 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3996 return MCDisassembler::Fail; 3997 3998 return S; 3999 } 4000 4001 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 4002 uint64_t Address, const void *Decoder) { 4003 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4004 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4005 if (sign1 != sign2) return MCDisassembler::Fail; 4006 4007 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4008 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4009 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4010 Val |= sign1 << 12; 4011 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4012 4013 return MCDisassembler::Success; 4014 } 4015 4016 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4017 uint64_t Address, 4018 const void *Decoder) { 4019 DecodeStatus S = MCDisassembler::Success; 4020 4021 // Shift of "asr #32" is not allowed in Thumb2 mode. 4022 if (Val == 0x20) S = MCDisassembler::SoftFail; 4023 Inst.addOperand(MCOperand::CreateImm(Val)); 4024 return S; 4025 } 4026 4027 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 4028 uint64_t Address, const void *Decoder) { 4029 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4030 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4031 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4032 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4033 4034 if (pred == 0xF) 4035 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4036 4037 DecodeStatus S = MCDisassembler::Success; 4038 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4039 return MCDisassembler::Fail; 4040 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4041 return MCDisassembler::Fail; 4042 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4043 return MCDisassembler::Fail; 4044 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4045 return MCDisassembler::Fail; 4046 4047 return S; 4048 } 4049 4050 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 4051 uint64_t Address, const void *Decoder) { 4052 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4053 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4054 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4055 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4056 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4057 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4058 4059 DecodeStatus S = MCDisassembler::Success; 4060 4061 // VMOVv2f32 is ambiguous with these decodings. 4062 if (!(imm & 0x38) && cmode == 0xF) { 4063 Inst.setOpcode(ARM::VMOVv2f32); 4064 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4065 } 4066 4067 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4068 4069 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4070 return MCDisassembler::Fail; 4071 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4072 return MCDisassembler::Fail; 4073 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4074 4075 return S; 4076 } 4077 4078 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 4079 uint64_t Address, const void *Decoder) { 4080 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4081 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4082 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4083 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4084 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4085 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4086 4087 DecodeStatus S = MCDisassembler::Success; 4088 4089 // VMOVv4f32 is ambiguous with these decodings. 4090 if (!(imm & 0x38) && cmode == 0xF) { 4091 Inst.setOpcode(ARM::VMOVv4f32); 4092 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4093 } 4094 4095 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4096 4097 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4098 return MCDisassembler::Fail; 4099 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4100 return MCDisassembler::Fail; 4101 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4102 4103 return S; 4104 } 4105 4106