1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 137 uint64_t Address, const void *Decoder); 138 static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 139 uint64_t Address, const void *Decoder); 140 static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 145 uint64_t Address, const void *Decoder); 146 static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 147 uint64_t Address, const void *Decoder); 148 static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 161 162 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 163 uint64_t Address, const void *Decoder); 164 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 167 uint64_t Address, const void *Decoder); 168 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 169 uint64_t Address, const void *Decoder); 170 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 171 uint64_t Address, const void *Decoder); 172 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 173 uint64_t Address, const void *Decoder); 174 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 191 uint64_t Address, const void *Decoder); 192 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 193 uint64_t Address, const void *Decoder); 194 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 195 uint64_t Address, const void *Decoder); 196 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 211 #include "ARMGenDisassemblerTables.inc" 212 #include "ARMGenInstrInfo.inc" 213 #include "ARMGenEDInfo.inc" 214 215 using namespace llvm; 216 217 static MCDisassembler *createARMDisassembler(const Target &T) { 218 return new ARMDisassembler; 219 } 220 221 static MCDisassembler *createThumbDisassembler(const Target &T) { 222 return new ThumbDisassembler; 223 } 224 225 EDInstInfo *ARMDisassembler::getEDInfo() const { 226 return instInfoARM; 227 } 228 229 EDInstInfo *ThumbDisassembler::getEDInfo() const { 230 return instInfoARM; 231 } 232 233 234 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 235 const MemoryObject &Region, 236 uint64_t Address,raw_ostream &os) const { 237 uint8_t bytes[4]; 238 239 // We want to read exactly 4 bytes of data. 240 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 241 return false; 242 243 // Encoded as a small-endian 32-bit word in the stream. 244 uint32_t insn = (bytes[3] << 24) | 245 (bytes[2] << 16) | 246 (bytes[1] << 8) | 247 (bytes[0] << 0); 248 249 // Calling the auto-generated decoder function. 250 bool result = decodeARMInstruction32(MI, insn, Address, this); 251 if (result) { 252 Size = 4; 253 return true; 254 } 255 256 // Instructions that are shared between ARM and Thumb modes. 257 // FIXME: This shouldn't really exist. It's an artifact of the 258 // fact that we fail to encode a few instructions properly for Thumb. 259 MI.clear(); 260 result = decodeCommonInstruction32(MI, insn, Address, this); 261 if (result) { 262 Size = 4; 263 return true; 264 } 265 266 // VFP and NEON instructions, similarly, are shared between ARM 267 // and Thumb modes. 268 MI.clear(); 269 result = decodeVFPInstruction32(MI, insn, Address, this); 270 if (result) { 271 Size = 4; 272 return true; 273 } 274 275 MI.clear(); 276 result = decodeNEONDataInstruction32(MI, insn, Address, this); 277 if (result) { 278 Size = 4; 279 // Add a fake predicate operand, because we share these instruction 280 // definitions with Thumb2 where these instructions are predicable. 281 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 282 return true; 283 } 284 285 MI.clear(); 286 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 287 if (result) { 288 Size = 4; 289 // Add a fake predicate operand, because we share these instruction 290 // definitions with Thumb2 where these instructions are predicable. 291 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 292 return true; 293 } 294 295 MI.clear(); 296 result = decodeNEONDupInstruction32(MI, insn, Address, this); 297 if (result) { 298 Size = 4; 299 // Add a fake predicate operand, because we share these instruction 300 // definitions with Thumb2 where these instructions are predicable. 301 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 302 return true; 303 } 304 305 MI.clear(); 306 307 return false; 308 } 309 310 namespace llvm { 311 extern MCInstrDesc ARMInsts[]; 312 } 313 314 // Thumb1 instructions don't have explicit S bits. Rather, they 315 // implicitly set CPSR. Since it's not represented in the encoding, the 316 // auto-generated decoder won't inject the CPSR operand. We need to fix 317 // that as a post-pass. 318 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 319 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 320 MCInst::iterator I = MI.begin(); 321 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 322 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 323 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 324 return; 325 } 326 } 327 328 if (OpInfo[MI.size()].isOptionalDef() && 329 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 330 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 331 } 332 333 // Most Thumb instructions don't have explicit predicates in the 334 // encoding, but rather get their predicates from IT context. We need 335 // to fix up the predicate operands using this context information as a 336 // post-pass. 337 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 338 // A few instructions actually have predicates encoded in them. Don't 339 // try to overwrite it if we're seeing one of those. 340 switch (MI.getOpcode()) { 341 case ARM::tBcc: 342 case ARM::t2Bcc: 343 return; 344 default: 345 break; 346 } 347 348 // If we're in an IT block, base the predicate on that. Otherwise, 349 // assume a predicate of AL. 350 unsigned CC; 351 if (!ITBlock.empty()) { 352 CC = ITBlock.back(); 353 ITBlock.pop_back(); 354 } else 355 CC = ARMCC::AL; 356 357 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 358 MCInst::iterator I = MI.begin(); 359 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 360 if (OpInfo[i].isPredicate()) { 361 I = MI.insert(I, MCOperand::CreateImm(CC)); 362 ++I; 363 if (CC == ARMCC::AL) 364 MI.insert(I, MCOperand::CreateReg(0)); 365 else 366 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 367 return; 368 } 369 } 370 371 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 372 if (CC == ARMCC::AL) 373 MI.insert(MI.end(), MCOperand::CreateReg(0)); 374 else 375 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 376 } 377 378 // Thumb VFP instructions are a special case. Because we share their 379 // encodings between ARM and Thumb modes, and they are predicable in ARM 380 // mode, the auto-generated decoder will give them an (incorrect) 381 // predicate operand. We need to rewrite these operands based on the IT 382 // context as a post-pass. 383 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 384 unsigned CC; 385 if (!ITBlock.empty()) { 386 CC = ITBlock.back(); 387 ITBlock.pop_back(); 388 } else 389 CC = ARMCC::AL; 390 391 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 392 MCInst::iterator I = MI.begin(); 393 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 394 if (OpInfo[i].isPredicate() ) { 395 I->setImm(CC); 396 ++I; 397 if (CC == ARMCC::AL) 398 I->setReg(0); 399 else 400 I->setReg(ARM::CPSR); 401 return; 402 } 403 } 404 } 405 406 407 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 408 const MemoryObject &Region, 409 uint64_t Address,raw_ostream &os) const { 410 uint8_t bytes[4]; 411 412 // We want to read exactly 2 bytes of data. 413 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 414 return false; 415 416 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 417 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 418 if (result) { 419 Size = 2; 420 bool InITBlock = !ITBlock.empty(); 421 AddThumbPredicate(MI); 422 AddThumb1SBit(MI, InITBlock); 423 return true; 424 } 425 426 MI.clear(); 427 result = decodeThumb2Instruction16(MI, insn16, Address, this); 428 if (result) { 429 Size = 2; 430 AddThumbPredicate(MI); 431 432 // If we find an IT instruction, we need to parse its condition 433 // code and mask operands so that we can apply them correctly 434 // to the subsequent instructions. 435 if (MI.getOpcode() == ARM::t2IT) { 436 unsigned firstcond = MI.getOperand(0).getImm(); 437 uint32_t mask = MI.getOperand(1).getImm(); 438 unsigned zeros = CountTrailingZeros_32(mask); 439 mask >>= zeros+1; 440 441 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 442 if (firstcond ^ (mask & 1)) 443 ITBlock.push_back(firstcond ^ 1); 444 else 445 ITBlock.push_back(firstcond); 446 mask >>= 1; 447 } 448 ITBlock.push_back(firstcond); 449 } 450 451 return true; 452 } 453 454 // We want to read exactly 4 bytes of data. 455 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 456 return false; 457 458 uint32_t insn32 = (bytes[3] << 8) | 459 (bytes[2] << 0) | 460 (bytes[1] << 24) | 461 (bytes[0] << 16); 462 MI.clear(); 463 result = decodeThumbInstruction32(MI, insn32, Address, this); 464 if (result) { 465 Size = 4; 466 bool InITBlock = ITBlock.size(); 467 AddThumbPredicate(MI); 468 AddThumb1SBit(MI, InITBlock); 469 return true; 470 } 471 472 MI.clear(); 473 result = decodeThumb2Instruction32(MI, insn32, Address, this); 474 if (result) { 475 Size = 4; 476 AddThumbPredicate(MI); 477 return true; 478 } 479 480 MI.clear(); 481 result = decodeCommonInstruction32(MI, insn32, Address, this); 482 if (result) { 483 Size = 4; 484 AddThumbPredicate(MI); 485 return true; 486 } 487 488 MI.clear(); 489 result = decodeVFPInstruction32(MI, insn32, Address, this); 490 if (result) { 491 Size = 4; 492 UpdateThumbVFPPredicate(MI); 493 return true; 494 } 495 496 MI.clear(); 497 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 498 if (result) { 499 Size = 4; 500 AddThumbPredicate(MI); 501 return true; 502 } 503 504 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 505 MI.clear(); 506 uint32_t NEONLdStInsn = insn32; 507 NEONLdStInsn &= 0xF0FFFFFF; 508 NEONLdStInsn |= 0x04000000; 509 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 510 if (result) { 511 Size = 4; 512 AddThumbPredicate(MI); 513 return true; 514 } 515 } 516 517 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 518 MI.clear(); 519 uint32_t NEONDataInsn = insn32; 520 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 521 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 522 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 523 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 524 if (result) { 525 Size = 4; 526 AddThumbPredicate(MI); 527 return true; 528 } 529 } 530 531 return false; 532 } 533 534 535 extern "C" void LLVMInitializeARMDisassembler() { 536 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 537 createARMDisassembler); 538 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 539 createThumbDisassembler); 540 } 541 542 static const unsigned GPRDecoderTable[] = { 543 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 544 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 545 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 546 ARM::R12, ARM::SP, ARM::LR, ARM::PC 547 }; 548 549 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 550 uint64_t Address, const void *Decoder) { 551 if (RegNo > 15) 552 return false; 553 554 unsigned Register = GPRDecoderTable[RegNo]; 555 Inst.addOperand(MCOperand::CreateReg(Register)); 556 return true; 557 } 558 559 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 560 uint64_t Address, const void *Decoder) { 561 if (RegNo == 15) return false; 562 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 563 } 564 565 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 566 uint64_t Address, const void *Decoder) { 567 if (RegNo > 7) 568 return false; 569 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 570 } 571 572 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 573 uint64_t Address, const void *Decoder) { 574 unsigned Register = 0; 575 switch (RegNo) { 576 case 0: 577 Register = ARM::R0; 578 break; 579 case 1: 580 Register = ARM::R1; 581 break; 582 case 2: 583 Register = ARM::R2; 584 break; 585 case 3: 586 Register = ARM::R3; 587 break; 588 case 9: 589 Register = ARM::R9; 590 break; 591 case 12: 592 Register = ARM::R12; 593 break; 594 default: 595 return false; 596 } 597 598 Inst.addOperand(MCOperand::CreateReg(Register)); 599 return true; 600 } 601 602 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 603 uint64_t Address, const void *Decoder) { 604 if (RegNo == 13 || RegNo == 15) return false; 605 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 606 } 607 608 static const unsigned SPRDecoderTable[] = { 609 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 610 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 611 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 612 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 613 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 614 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 615 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 616 ARM::S28, ARM::S29, ARM::S30, ARM::S31 617 }; 618 619 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 620 uint64_t Address, const void *Decoder) { 621 if (RegNo > 31) 622 return false; 623 624 unsigned Register = SPRDecoderTable[RegNo]; 625 Inst.addOperand(MCOperand::CreateReg(Register)); 626 return true; 627 } 628 629 static const unsigned DPRDecoderTable[] = { 630 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 631 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 632 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 633 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 634 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 635 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 636 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 637 ARM::D28, ARM::D29, ARM::D30, ARM::D31 638 }; 639 640 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 641 uint64_t Address, const void *Decoder) { 642 if (RegNo > 31) 643 return false; 644 645 unsigned Register = DPRDecoderTable[RegNo]; 646 Inst.addOperand(MCOperand::CreateReg(Register)); 647 return true; 648 } 649 650 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 651 uint64_t Address, const void *Decoder) { 652 if (RegNo > 7) 653 return false; 654 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 655 } 656 657 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 658 uint64_t Address, const void *Decoder) { 659 if (RegNo > 15) 660 return false; 661 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 662 } 663 664 static const unsigned QPRDecoderTable[] = { 665 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 666 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 667 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 668 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 669 }; 670 671 672 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 673 uint64_t Address, const void *Decoder) { 674 if (RegNo > 31) 675 return false; 676 RegNo >>= 1; 677 678 unsigned Register = QPRDecoderTable[RegNo]; 679 Inst.addOperand(MCOperand::CreateReg(Register)); 680 return true; 681 } 682 683 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 684 uint64_t Address, const void *Decoder) { 685 if (Val == 0xF) return false; 686 // AL predicate is not allowed on Thumb1 branches. 687 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 688 return false; 689 Inst.addOperand(MCOperand::CreateImm(Val)); 690 if (Val == ARMCC::AL) { 691 Inst.addOperand(MCOperand::CreateReg(0)); 692 } else 693 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 694 return true; 695 } 696 697 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 698 uint64_t Address, const void *Decoder) { 699 if (Val) 700 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 701 else 702 Inst.addOperand(MCOperand::CreateReg(0)); 703 return true; 704 } 705 706 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 707 uint64_t Address, const void *Decoder) { 708 uint32_t imm = Val & 0xFF; 709 uint32_t rot = (Val & 0xF00) >> 7; 710 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 711 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 712 return true; 713 } 714 715 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 716 uint64_t Address, const void *Decoder) { 717 Val <<= 2; 718 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 719 return true; 720 } 721 722 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 723 uint64_t Address, const void *Decoder) { 724 725 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 726 unsigned type = fieldFromInstruction32(Val, 5, 2); 727 unsigned imm = fieldFromInstruction32(Val, 7, 5); 728 729 // Register-immediate 730 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 731 732 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 733 switch (type) { 734 case 0: 735 Shift = ARM_AM::lsl; 736 break; 737 case 1: 738 Shift = ARM_AM::lsr; 739 break; 740 case 2: 741 Shift = ARM_AM::asr; 742 break; 743 case 3: 744 Shift = ARM_AM::ror; 745 break; 746 } 747 748 if (Shift == ARM_AM::ror && imm == 0) 749 Shift = ARM_AM::rrx; 750 751 unsigned Op = Shift | (imm << 3); 752 Inst.addOperand(MCOperand::CreateImm(Op)); 753 754 return true; 755 } 756 757 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 758 uint64_t Address, const void *Decoder) { 759 760 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 761 unsigned type = fieldFromInstruction32(Val, 5, 2); 762 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 763 764 // Register-register 765 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 766 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 767 768 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 769 switch (type) { 770 case 0: 771 Shift = ARM_AM::lsl; 772 break; 773 case 1: 774 Shift = ARM_AM::lsr; 775 break; 776 case 2: 777 Shift = ARM_AM::asr; 778 break; 779 case 3: 780 Shift = ARM_AM::ror; 781 break; 782 } 783 784 Inst.addOperand(MCOperand::CreateImm(Shift)); 785 786 return true; 787 } 788 789 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 790 uint64_t Address, const void *Decoder) { 791 // Empty register lists are not allowed. 792 if (CountPopulation_32(Val) == 0) return false; 793 for (unsigned i = 0; i < 16; ++i) { 794 if (Val & (1 << i)) { 795 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 796 } 797 } 798 799 return true; 800 } 801 802 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 803 uint64_t Address, const void *Decoder) { 804 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 805 unsigned regs = Val & 0xFF; 806 807 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 808 for (unsigned i = 0; i < (regs - 1); ++i) { 809 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 810 } 811 812 return true; 813 } 814 815 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 816 uint64_t Address, const void *Decoder) { 817 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 818 unsigned regs = (Val & 0xFF) / 2; 819 820 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 821 for (unsigned i = 0; i < (regs - 1); ++i) { 822 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 823 } 824 825 return true; 826 } 827 828 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 829 uint64_t Address, const void *Decoder) { 830 // This operand encodes a mask of contiguous zeros between a specified MSB 831 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 832 // the mask of all bits LSB-and-lower, and then xor them to create 833 // the mask of that's all ones on [msb, lsb]. Finally we not it to 834 // create the final mask. 835 unsigned msb = fieldFromInstruction32(Val, 5, 5); 836 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 837 uint32_t msb_mask = (1 << (msb+1)) - 1; 838 uint32_t lsb_mask = (1 << lsb) - 1; 839 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 840 return true; 841 } 842 843 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 844 uint64_t Address, const void *Decoder) { 845 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 846 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 847 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 848 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 849 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 850 unsigned U = fieldFromInstruction32(Insn, 23, 1); 851 852 switch (Inst.getOpcode()) { 853 case ARM::LDC_OFFSET: 854 case ARM::LDC_PRE: 855 case ARM::LDC_POST: 856 case ARM::LDC_OPTION: 857 case ARM::LDCL_OFFSET: 858 case ARM::LDCL_PRE: 859 case ARM::LDCL_POST: 860 case ARM::LDCL_OPTION: 861 case ARM::STC_OFFSET: 862 case ARM::STC_PRE: 863 case ARM::STC_POST: 864 case ARM::STC_OPTION: 865 case ARM::STCL_OFFSET: 866 case ARM::STCL_PRE: 867 case ARM::STCL_POST: 868 case ARM::STCL_OPTION: 869 if (coproc == 0xA || coproc == 0xB) 870 return false; 871 break; 872 default: 873 break; 874 } 875 876 Inst.addOperand(MCOperand::CreateImm(coproc)); 877 Inst.addOperand(MCOperand::CreateImm(CRd)); 878 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 879 switch (Inst.getOpcode()) { 880 case ARM::LDC_OPTION: 881 case ARM::LDCL_OPTION: 882 case ARM::LDC2_OPTION: 883 case ARM::LDC2L_OPTION: 884 case ARM::STC_OPTION: 885 case ARM::STCL_OPTION: 886 case ARM::STC2_OPTION: 887 case ARM::STC2L_OPTION: 888 case ARM::LDCL_POST: 889 case ARM::STCL_POST: 890 break; 891 default: 892 Inst.addOperand(MCOperand::CreateReg(0)); 893 break; 894 } 895 896 unsigned P = fieldFromInstruction32(Insn, 24, 1); 897 unsigned W = fieldFromInstruction32(Insn, 21, 1); 898 899 bool writeback = (P == 0) || (W == 1); 900 unsigned idx_mode = 0; 901 if (P && writeback) 902 idx_mode = ARMII::IndexModePre; 903 else if (!P && writeback) 904 idx_mode = ARMII::IndexModePost; 905 906 switch (Inst.getOpcode()) { 907 case ARM::LDCL_POST: 908 case ARM::STCL_POST: 909 imm |= U << 8; 910 case ARM::LDC_OPTION: 911 case ARM::LDCL_OPTION: 912 case ARM::LDC2_OPTION: 913 case ARM::LDC2L_OPTION: 914 case ARM::STC_OPTION: 915 case ARM::STCL_OPTION: 916 case ARM::STC2_OPTION: 917 case ARM::STC2L_OPTION: 918 Inst.addOperand(MCOperand::CreateImm(imm)); 919 break; 920 default: 921 if (U) 922 Inst.addOperand(MCOperand::CreateImm( 923 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 924 else 925 Inst.addOperand(MCOperand::CreateImm( 926 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 927 break; 928 } 929 930 switch (Inst.getOpcode()) { 931 case ARM::LDC_OFFSET: 932 case ARM::LDC_PRE: 933 case ARM::LDC_POST: 934 case ARM::LDC_OPTION: 935 case ARM::LDCL_OFFSET: 936 case ARM::LDCL_PRE: 937 case ARM::LDCL_POST: 938 case ARM::LDCL_OPTION: 939 case ARM::STC_OFFSET: 940 case ARM::STC_PRE: 941 case ARM::STC_POST: 942 case ARM::STC_OPTION: 943 case ARM::STCL_OFFSET: 944 case ARM::STCL_PRE: 945 case ARM::STCL_POST: 946 case ARM::STCL_OPTION: 947 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 948 break; 949 default: 950 break; 951 } 952 953 return true; 954 } 955 956 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 957 uint64_t Address, const void *Decoder) { 958 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 959 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 960 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 961 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 962 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 963 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 964 unsigned P = fieldFromInstruction32(Insn, 24, 1); 965 unsigned W = fieldFromInstruction32(Insn, 21, 1); 966 967 // On stores, the writeback operand precedes Rt. 968 switch (Inst.getOpcode()) { 969 case ARM::STR_POST_IMM: 970 case ARM::STR_POST_REG: 971 case ARM::STRB_POST_IMM: 972 case ARM::STRB_POST_REG: 973 case ARM::STRT_POST_REG: 974 case ARM::STRT_POST_IMM: 975 case ARM::STRBT_POST_REG: 976 case ARM::STRBT_POST_IMM: 977 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 978 break; 979 default: 980 break; 981 } 982 983 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 984 985 // On loads, the writeback operand comes after Rt. 986 switch (Inst.getOpcode()) { 987 case ARM::LDR_POST_IMM: 988 case ARM::LDR_POST_REG: 989 case ARM::LDRB_POST_IMM: 990 case ARM::LDRB_POST_REG: 991 case ARM::LDR_PRE: 992 case ARM::LDRB_PRE: 993 case ARM::LDRBT_POST_REG: 994 case ARM::LDRBT_POST_IMM: 995 case ARM::LDRT_POST_REG: 996 case ARM::LDRT_POST_IMM: 997 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 998 return false; 999 break; 1000 default: 1001 break; 1002 } 1003 1004 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1005 1006 ARM_AM::AddrOpc Op = ARM_AM::add; 1007 if (!fieldFromInstruction32(Insn, 23, 1)) 1008 Op = ARM_AM::sub; 1009 1010 bool writeback = (P == 0) || (W == 1); 1011 unsigned idx_mode = 0; 1012 if (P && writeback) 1013 idx_mode = ARMII::IndexModePre; 1014 else if (!P && writeback) 1015 idx_mode = ARMII::IndexModePost; 1016 1017 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE 1018 1019 if (reg) { 1020 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 1021 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1022 switch( fieldFromInstruction32(Insn, 5, 2)) { 1023 case 0: 1024 Opc = ARM_AM::lsl; 1025 break; 1026 case 1: 1027 Opc = ARM_AM::lsr; 1028 break; 1029 case 2: 1030 Opc = ARM_AM::asr; 1031 break; 1032 case 3: 1033 Opc = ARM_AM::ror; 1034 break; 1035 default: 1036 return false; 1037 } 1038 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1039 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1040 1041 Inst.addOperand(MCOperand::CreateImm(imm)); 1042 } else { 1043 Inst.addOperand(MCOperand::CreateReg(0)); 1044 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1045 Inst.addOperand(MCOperand::CreateImm(tmp)); 1046 } 1047 1048 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1049 1050 return true; 1051 } 1052 1053 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1054 uint64_t Address, const void *Decoder) { 1055 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1056 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1057 unsigned type = fieldFromInstruction32(Val, 5, 2); 1058 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1059 unsigned U = fieldFromInstruction32(Val, 12, 1); 1060 1061 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1062 switch (type) { 1063 case 0: 1064 ShOp = ARM_AM::lsl; 1065 break; 1066 case 1: 1067 ShOp = ARM_AM::lsr; 1068 break; 1069 case 2: 1070 ShOp = ARM_AM::asr; 1071 break; 1072 case 3: 1073 ShOp = ARM_AM::ror; 1074 break; 1075 } 1076 1077 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1078 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1079 unsigned shift; 1080 if (U) 1081 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1082 else 1083 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1084 Inst.addOperand(MCOperand::CreateImm(shift)); 1085 1086 return true; 1087 } 1088 1089 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1090 uint64_t Address, const void *Decoder) { 1091 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1092 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1093 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1094 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1095 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1096 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1097 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1098 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1099 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1100 1101 bool writeback = (W == 1) | (P == 0); 1102 1103 // For {LD,ST}RD, Rt must be even, else undefined. 1104 switch (Inst.getOpcode()) { 1105 case ARM::STRD: 1106 case ARM::STRD_PRE: 1107 case ARM::STRD_POST: 1108 case ARM::LDRD: 1109 case ARM::LDRD_PRE: 1110 case ARM::LDRD_POST: 1111 if (Rt & 0x1) return false; 1112 break; 1113 default: 1114 break; 1115 } 1116 1117 if (writeback) { // Writeback 1118 if (P) 1119 U |= ARMII::IndexModePre << 9; 1120 else 1121 U |= ARMII::IndexModePost << 9; 1122 1123 // On stores, the writeback operand precedes Rt. 1124 switch (Inst.getOpcode()) { 1125 case ARM::STRD: 1126 case ARM::STRD_PRE: 1127 case ARM::STRD_POST: 1128 case ARM::STRH: 1129 case ARM::STRH_PRE: 1130 case ARM::STRH_POST: 1131 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1132 return false; 1133 break; 1134 default: 1135 break; 1136 } 1137 } 1138 1139 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1140 return false; 1141 switch (Inst.getOpcode()) { 1142 case ARM::STRD: 1143 case ARM::STRD_PRE: 1144 case ARM::STRD_POST: 1145 case ARM::LDRD: 1146 case ARM::LDRD_PRE: 1147 case ARM::LDRD_POST: 1148 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1149 return false; 1150 break; 1151 default: 1152 break; 1153 } 1154 1155 if (writeback) { 1156 // On loads, the writeback operand comes after Rt. 1157 switch (Inst.getOpcode()) { 1158 case ARM::LDRD: 1159 case ARM::LDRD_PRE: 1160 case ARM::LDRD_POST: 1161 case ARM::LDRH: 1162 case ARM::LDRH_PRE: 1163 case ARM::LDRH_POST: 1164 case ARM::LDRSH: 1165 case ARM::LDRSH_PRE: 1166 case ARM::LDRSH_POST: 1167 case ARM::LDRSB: 1168 case ARM::LDRSB_PRE: 1169 case ARM::LDRSB_POST: 1170 case ARM::LDRHTr: 1171 case ARM::LDRSBTr: 1172 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1173 return false; 1174 break; 1175 default: 1176 break; 1177 } 1178 } 1179 1180 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1181 return false; 1182 1183 if (type) { 1184 Inst.addOperand(MCOperand::CreateReg(0)); 1185 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1186 } else { 1187 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1188 return false; 1189 Inst.addOperand(MCOperand::CreateImm(U)); 1190 } 1191 1192 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1193 1194 return true; 1195 } 1196 1197 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1198 uint64_t Address, const void *Decoder) { 1199 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1200 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1201 1202 switch (mode) { 1203 case 0: 1204 mode = ARM_AM::da; 1205 break; 1206 case 1: 1207 mode = ARM_AM::ia; 1208 break; 1209 case 2: 1210 mode = ARM_AM::db; 1211 break; 1212 case 3: 1213 mode = ARM_AM::ib; 1214 break; 1215 } 1216 1217 Inst.addOperand(MCOperand::CreateImm(mode)); 1218 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1219 1220 return true; 1221 } 1222 1223 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1224 unsigned Insn, 1225 uint64_t Address, const void *Decoder) { 1226 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1227 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1228 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1229 1230 if (pred == 0xF) { 1231 switch (Inst.getOpcode()) { 1232 case ARM::STMDA: 1233 Inst.setOpcode(ARM::RFEDA); 1234 break; 1235 case ARM::STMDA_UPD: 1236 Inst.setOpcode(ARM::RFEDA_UPD); 1237 break; 1238 case ARM::STMDB: 1239 Inst.setOpcode(ARM::RFEDB); 1240 break; 1241 case ARM::STMDB_UPD: 1242 Inst.setOpcode(ARM::RFEDB_UPD); 1243 break; 1244 case ARM::STMIA: 1245 Inst.setOpcode(ARM::RFEIA); 1246 break; 1247 case ARM::STMIA_UPD: 1248 Inst.setOpcode(ARM::RFEIA_UPD); 1249 break; 1250 case ARM::STMIB: 1251 Inst.setOpcode(ARM::RFEIB); 1252 break; 1253 case ARM::STMIB_UPD: 1254 Inst.setOpcode(ARM::RFEIB_UPD); 1255 break; 1256 } 1257 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1258 } 1259 1260 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1261 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1262 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1263 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1264 return false; 1265 1266 return true; 1267 } 1268 1269 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1270 uint64_t Address, const void *Decoder) { 1271 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1272 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1273 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1274 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1275 1276 // imod == '01' --> UNPREDICTABLE 1277 if (imod == 1) return false; 1278 1279 if (M && mode && imod && iflags) { 1280 Inst.setOpcode(ARM::CPS3p); 1281 Inst.addOperand(MCOperand::CreateImm(imod)); 1282 Inst.addOperand(MCOperand::CreateImm(iflags)); 1283 Inst.addOperand(MCOperand::CreateImm(mode)); 1284 return true; 1285 } else if (!mode && !M) { 1286 Inst.setOpcode(ARM::CPS2p); 1287 Inst.addOperand(MCOperand::CreateImm(imod)); 1288 Inst.addOperand(MCOperand::CreateImm(iflags)); 1289 return true; 1290 } else if (!imod && !iflags && M) { 1291 Inst.setOpcode(ARM::CPS1p); 1292 Inst.addOperand(MCOperand::CreateImm(mode)); 1293 return true; 1294 } 1295 1296 return false; 1297 } 1298 1299 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1300 uint64_t Address, const void *Decoder) { 1301 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1302 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1303 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1304 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1305 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1306 1307 if (pred == 0xF) 1308 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1309 1310 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1311 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1312 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1313 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1314 return false; 1315 1316 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1317 1318 return true; 1319 } 1320 1321 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1322 uint64_t Address, const void *Decoder) { 1323 unsigned add = fieldFromInstruction32(Val, 12, 1); 1324 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1325 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1326 1327 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1328 return false; 1329 1330 if (!add) imm *= -1; 1331 if (imm == 0 && !add) imm = INT32_MIN; 1332 Inst.addOperand(MCOperand::CreateImm(imm)); 1333 1334 return true; 1335 } 1336 1337 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1338 uint64_t Address, const void *Decoder) { 1339 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1340 unsigned U = fieldFromInstruction32(Val, 8, 1); 1341 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1342 1343 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1344 return false; 1345 1346 if (U) 1347 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1348 else 1349 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1350 1351 return true; 1352 } 1353 1354 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1355 uint64_t Address, const void *Decoder) { 1356 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1357 } 1358 1359 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1360 uint64_t Address, const void *Decoder) { 1361 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1362 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1363 1364 if (pred == 0xF) { 1365 Inst.setOpcode(ARM::BLXi); 1366 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1367 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1368 return true; 1369 } 1370 1371 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1372 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1373 1374 return true; 1375 } 1376 1377 1378 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1379 uint64_t Address, const void *Decoder) { 1380 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1381 return true; 1382 } 1383 1384 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1385 uint64_t Address, const void *Decoder) { 1386 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1387 unsigned align = fieldFromInstruction32(Val, 4, 2); 1388 1389 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1390 return false; 1391 if (!align) 1392 Inst.addOperand(MCOperand::CreateImm(0)); 1393 else 1394 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1395 1396 return true; 1397 } 1398 1399 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1400 uint64_t Address, const void *Decoder) { 1401 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1402 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1403 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1404 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1405 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1406 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1407 1408 // First output register 1409 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1410 1411 // Second output register 1412 switch (Inst.getOpcode()) { 1413 case ARM::VLD1q8: 1414 case ARM::VLD1q16: 1415 case ARM::VLD1q32: 1416 case ARM::VLD1q64: 1417 case ARM::VLD1q8_UPD: 1418 case ARM::VLD1q16_UPD: 1419 case ARM::VLD1q32_UPD: 1420 case ARM::VLD1q64_UPD: 1421 case ARM::VLD1d8T: 1422 case ARM::VLD1d16T: 1423 case ARM::VLD1d32T: 1424 case ARM::VLD1d64T: 1425 case ARM::VLD1d8T_UPD: 1426 case ARM::VLD1d16T_UPD: 1427 case ARM::VLD1d32T_UPD: 1428 case ARM::VLD1d64T_UPD: 1429 case ARM::VLD1d8Q: 1430 case ARM::VLD1d16Q: 1431 case ARM::VLD1d32Q: 1432 case ARM::VLD1d64Q: 1433 case ARM::VLD1d8Q_UPD: 1434 case ARM::VLD1d16Q_UPD: 1435 case ARM::VLD1d32Q_UPD: 1436 case ARM::VLD1d64Q_UPD: 1437 case ARM::VLD2d8: 1438 case ARM::VLD2d16: 1439 case ARM::VLD2d32: 1440 case ARM::VLD2d8_UPD: 1441 case ARM::VLD2d16_UPD: 1442 case ARM::VLD2d32_UPD: 1443 case ARM::VLD2q8: 1444 case ARM::VLD2q16: 1445 case ARM::VLD2q32: 1446 case ARM::VLD2q8_UPD: 1447 case ARM::VLD2q16_UPD: 1448 case ARM::VLD2q32_UPD: 1449 case ARM::VLD3d8: 1450 case ARM::VLD3d16: 1451 case ARM::VLD3d32: 1452 case ARM::VLD3d8_UPD: 1453 case ARM::VLD3d16_UPD: 1454 case ARM::VLD3d32_UPD: 1455 case ARM::VLD4d8: 1456 case ARM::VLD4d16: 1457 case ARM::VLD4d32: 1458 case ARM::VLD4d8_UPD: 1459 case ARM::VLD4d16_UPD: 1460 case ARM::VLD4d32_UPD: 1461 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1462 break; 1463 case ARM::VLD2b8: 1464 case ARM::VLD2b16: 1465 case ARM::VLD2b32: 1466 case ARM::VLD2b8_UPD: 1467 case ARM::VLD2b16_UPD: 1468 case ARM::VLD2b32_UPD: 1469 case ARM::VLD3q8: 1470 case ARM::VLD3q16: 1471 case ARM::VLD3q32: 1472 case ARM::VLD3q8_UPD: 1473 case ARM::VLD3q16_UPD: 1474 case ARM::VLD3q32_UPD: 1475 case ARM::VLD4q8: 1476 case ARM::VLD4q16: 1477 case ARM::VLD4q32: 1478 case ARM::VLD4q8_UPD: 1479 case ARM::VLD4q16_UPD: 1480 case ARM::VLD4q32_UPD: 1481 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1482 default: 1483 break; 1484 } 1485 1486 // Third output register 1487 switch(Inst.getOpcode()) { 1488 case ARM::VLD1d8T: 1489 case ARM::VLD1d16T: 1490 case ARM::VLD1d32T: 1491 case ARM::VLD1d64T: 1492 case ARM::VLD1d8T_UPD: 1493 case ARM::VLD1d16T_UPD: 1494 case ARM::VLD1d32T_UPD: 1495 case ARM::VLD1d64T_UPD: 1496 case ARM::VLD1d8Q: 1497 case ARM::VLD1d16Q: 1498 case ARM::VLD1d32Q: 1499 case ARM::VLD1d64Q: 1500 case ARM::VLD1d8Q_UPD: 1501 case ARM::VLD1d16Q_UPD: 1502 case ARM::VLD1d32Q_UPD: 1503 case ARM::VLD1d64Q_UPD: 1504 case ARM::VLD2q8: 1505 case ARM::VLD2q16: 1506 case ARM::VLD2q32: 1507 case ARM::VLD2q8_UPD: 1508 case ARM::VLD2q16_UPD: 1509 case ARM::VLD2q32_UPD: 1510 case ARM::VLD3d8: 1511 case ARM::VLD3d16: 1512 case ARM::VLD3d32: 1513 case ARM::VLD3d8_UPD: 1514 case ARM::VLD3d16_UPD: 1515 case ARM::VLD3d32_UPD: 1516 case ARM::VLD4d8: 1517 case ARM::VLD4d16: 1518 case ARM::VLD4d32: 1519 case ARM::VLD4d8_UPD: 1520 case ARM::VLD4d16_UPD: 1521 case ARM::VLD4d32_UPD: 1522 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1523 break; 1524 case ARM::VLD3q8: 1525 case ARM::VLD3q16: 1526 case ARM::VLD3q32: 1527 case ARM::VLD3q8_UPD: 1528 case ARM::VLD3q16_UPD: 1529 case ARM::VLD3q32_UPD: 1530 case ARM::VLD4q8: 1531 case ARM::VLD4q16: 1532 case ARM::VLD4q32: 1533 case ARM::VLD4q8_UPD: 1534 case ARM::VLD4q16_UPD: 1535 case ARM::VLD4q32_UPD: 1536 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1537 break; 1538 default: 1539 break; 1540 } 1541 1542 // Fourth output register 1543 switch (Inst.getOpcode()) { 1544 case ARM::VLD1d8Q: 1545 case ARM::VLD1d16Q: 1546 case ARM::VLD1d32Q: 1547 case ARM::VLD1d64Q: 1548 case ARM::VLD1d8Q_UPD: 1549 case ARM::VLD1d16Q_UPD: 1550 case ARM::VLD1d32Q_UPD: 1551 case ARM::VLD1d64Q_UPD: 1552 case ARM::VLD2q8: 1553 case ARM::VLD2q16: 1554 case ARM::VLD2q32: 1555 case ARM::VLD2q8_UPD: 1556 case ARM::VLD2q16_UPD: 1557 case ARM::VLD2q32_UPD: 1558 case ARM::VLD4d8: 1559 case ARM::VLD4d16: 1560 case ARM::VLD4d32: 1561 case ARM::VLD4d8_UPD: 1562 case ARM::VLD4d16_UPD: 1563 case ARM::VLD4d32_UPD: 1564 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1565 break; 1566 case ARM::VLD4q8: 1567 case ARM::VLD4q16: 1568 case ARM::VLD4q32: 1569 case ARM::VLD4q8_UPD: 1570 case ARM::VLD4q16_UPD: 1571 case ARM::VLD4q32_UPD: 1572 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1573 break; 1574 default: 1575 break; 1576 } 1577 1578 // Writeback operand 1579 switch (Inst.getOpcode()) { 1580 case ARM::VLD1d8_UPD: 1581 case ARM::VLD1d16_UPD: 1582 case ARM::VLD1d32_UPD: 1583 case ARM::VLD1d64_UPD: 1584 case ARM::VLD1q8_UPD: 1585 case ARM::VLD1q16_UPD: 1586 case ARM::VLD1q32_UPD: 1587 case ARM::VLD1q64_UPD: 1588 case ARM::VLD1d8T_UPD: 1589 case ARM::VLD1d16T_UPD: 1590 case ARM::VLD1d32T_UPD: 1591 case ARM::VLD1d64T_UPD: 1592 case ARM::VLD1d8Q_UPD: 1593 case ARM::VLD1d16Q_UPD: 1594 case ARM::VLD1d32Q_UPD: 1595 case ARM::VLD1d64Q_UPD: 1596 case ARM::VLD2d8_UPD: 1597 case ARM::VLD2d16_UPD: 1598 case ARM::VLD2d32_UPD: 1599 case ARM::VLD2q8_UPD: 1600 case ARM::VLD2q16_UPD: 1601 case ARM::VLD2q32_UPD: 1602 case ARM::VLD2b8_UPD: 1603 case ARM::VLD2b16_UPD: 1604 case ARM::VLD2b32_UPD: 1605 case ARM::VLD3d8_UPD: 1606 case ARM::VLD3d16_UPD: 1607 case ARM::VLD3d32_UPD: 1608 case ARM::VLD3q8_UPD: 1609 case ARM::VLD3q16_UPD: 1610 case ARM::VLD3q32_UPD: 1611 case ARM::VLD4d8_UPD: 1612 case ARM::VLD4d16_UPD: 1613 case ARM::VLD4d32_UPD: 1614 case ARM::VLD4q8_UPD: 1615 case ARM::VLD4q16_UPD: 1616 case ARM::VLD4q32_UPD: 1617 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1618 break; 1619 default: 1620 break; 1621 } 1622 1623 // AddrMode6 Base (register+alignment) 1624 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1625 1626 // AddrMode6 Offset (register) 1627 if (Rm == 0xD) 1628 Inst.addOperand(MCOperand::CreateReg(0)); 1629 else if (Rm != 0xF) { 1630 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1631 return false; 1632 } 1633 1634 return true; 1635 } 1636 1637 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1638 uint64_t Address, const void *Decoder) { 1639 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1640 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1641 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1642 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1643 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1644 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1645 1646 // Writeback Operand 1647 switch (Inst.getOpcode()) { 1648 case ARM::VST1d8_UPD: 1649 case ARM::VST1d16_UPD: 1650 case ARM::VST1d32_UPD: 1651 case ARM::VST1d64_UPD: 1652 case ARM::VST1q8_UPD: 1653 case ARM::VST1q16_UPD: 1654 case ARM::VST1q32_UPD: 1655 case ARM::VST1q64_UPD: 1656 case ARM::VST1d8T_UPD: 1657 case ARM::VST1d16T_UPD: 1658 case ARM::VST1d32T_UPD: 1659 case ARM::VST1d64T_UPD: 1660 case ARM::VST1d8Q_UPD: 1661 case ARM::VST1d16Q_UPD: 1662 case ARM::VST1d32Q_UPD: 1663 case ARM::VST1d64Q_UPD: 1664 case ARM::VST2d8_UPD: 1665 case ARM::VST2d16_UPD: 1666 case ARM::VST2d32_UPD: 1667 case ARM::VST2q8_UPD: 1668 case ARM::VST2q16_UPD: 1669 case ARM::VST2q32_UPD: 1670 case ARM::VST2b8_UPD: 1671 case ARM::VST2b16_UPD: 1672 case ARM::VST2b32_UPD: 1673 case ARM::VST3d8_UPD: 1674 case ARM::VST3d16_UPD: 1675 case ARM::VST3d32_UPD: 1676 case ARM::VST3q8_UPD: 1677 case ARM::VST3q16_UPD: 1678 case ARM::VST3q32_UPD: 1679 case ARM::VST4d8_UPD: 1680 case ARM::VST4d16_UPD: 1681 case ARM::VST4d32_UPD: 1682 case ARM::VST4q8_UPD: 1683 case ARM::VST4q16_UPD: 1684 case ARM::VST4q32_UPD: 1685 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1686 return false; 1687 break; 1688 default: 1689 break; 1690 } 1691 1692 // AddrMode6 Base (register+alignment) 1693 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1694 1695 // AddrMode6 Offset (register) 1696 if (Rm == 0xD) 1697 Inst.addOperand(MCOperand::CreateReg(0)); 1698 else if (Rm != 0xF) { 1699 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1700 } 1701 1702 // First input register 1703 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1704 1705 // Second input register 1706 switch (Inst.getOpcode()) { 1707 case ARM::VST1q8: 1708 case ARM::VST1q16: 1709 case ARM::VST1q32: 1710 case ARM::VST1q64: 1711 case ARM::VST1q8_UPD: 1712 case ARM::VST1q16_UPD: 1713 case ARM::VST1q32_UPD: 1714 case ARM::VST1q64_UPD: 1715 case ARM::VST1d8T: 1716 case ARM::VST1d16T: 1717 case ARM::VST1d32T: 1718 case ARM::VST1d64T: 1719 case ARM::VST1d8T_UPD: 1720 case ARM::VST1d16T_UPD: 1721 case ARM::VST1d32T_UPD: 1722 case ARM::VST1d64T_UPD: 1723 case ARM::VST1d8Q: 1724 case ARM::VST1d16Q: 1725 case ARM::VST1d32Q: 1726 case ARM::VST1d64Q: 1727 case ARM::VST1d8Q_UPD: 1728 case ARM::VST1d16Q_UPD: 1729 case ARM::VST1d32Q_UPD: 1730 case ARM::VST1d64Q_UPD: 1731 case ARM::VST2d8: 1732 case ARM::VST2d16: 1733 case ARM::VST2d32: 1734 case ARM::VST2d8_UPD: 1735 case ARM::VST2d16_UPD: 1736 case ARM::VST2d32_UPD: 1737 case ARM::VST2q8: 1738 case ARM::VST2q16: 1739 case ARM::VST2q32: 1740 case ARM::VST2q8_UPD: 1741 case ARM::VST2q16_UPD: 1742 case ARM::VST2q32_UPD: 1743 case ARM::VST3d8: 1744 case ARM::VST3d16: 1745 case ARM::VST3d32: 1746 case ARM::VST3d8_UPD: 1747 case ARM::VST3d16_UPD: 1748 case ARM::VST3d32_UPD: 1749 case ARM::VST4d8: 1750 case ARM::VST4d16: 1751 case ARM::VST4d32: 1752 case ARM::VST4d8_UPD: 1753 case ARM::VST4d16_UPD: 1754 case ARM::VST4d32_UPD: 1755 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1756 break; 1757 case ARM::VST2b8: 1758 case ARM::VST2b16: 1759 case ARM::VST2b32: 1760 case ARM::VST2b8_UPD: 1761 case ARM::VST2b16_UPD: 1762 case ARM::VST2b32_UPD: 1763 case ARM::VST3q8: 1764 case ARM::VST3q16: 1765 case ARM::VST3q32: 1766 case ARM::VST3q8_UPD: 1767 case ARM::VST3q16_UPD: 1768 case ARM::VST3q32_UPD: 1769 case ARM::VST4q8: 1770 case ARM::VST4q16: 1771 case ARM::VST4q32: 1772 case ARM::VST4q8_UPD: 1773 case ARM::VST4q16_UPD: 1774 case ARM::VST4q32_UPD: 1775 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1776 break; 1777 default: 1778 break; 1779 } 1780 1781 // Third input register 1782 switch (Inst.getOpcode()) { 1783 case ARM::VST1d8T: 1784 case ARM::VST1d16T: 1785 case ARM::VST1d32T: 1786 case ARM::VST1d64T: 1787 case ARM::VST1d8T_UPD: 1788 case ARM::VST1d16T_UPD: 1789 case ARM::VST1d32T_UPD: 1790 case ARM::VST1d64T_UPD: 1791 case ARM::VST1d8Q: 1792 case ARM::VST1d16Q: 1793 case ARM::VST1d32Q: 1794 case ARM::VST1d64Q: 1795 case ARM::VST1d8Q_UPD: 1796 case ARM::VST1d16Q_UPD: 1797 case ARM::VST1d32Q_UPD: 1798 case ARM::VST1d64Q_UPD: 1799 case ARM::VST2q8: 1800 case ARM::VST2q16: 1801 case ARM::VST2q32: 1802 case ARM::VST2q8_UPD: 1803 case ARM::VST2q16_UPD: 1804 case ARM::VST2q32_UPD: 1805 case ARM::VST3d8: 1806 case ARM::VST3d16: 1807 case ARM::VST3d32: 1808 case ARM::VST3d8_UPD: 1809 case ARM::VST3d16_UPD: 1810 case ARM::VST3d32_UPD: 1811 case ARM::VST4d8: 1812 case ARM::VST4d16: 1813 case ARM::VST4d32: 1814 case ARM::VST4d8_UPD: 1815 case ARM::VST4d16_UPD: 1816 case ARM::VST4d32_UPD: 1817 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1818 break; 1819 case ARM::VST3q8: 1820 case ARM::VST3q16: 1821 case ARM::VST3q32: 1822 case ARM::VST3q8_UPD: 1823 case ARM::VST3q16_UPD: 1824 case ARM::VST3q32_UPD: 1825 case ARM::VST4q8: 1826 case ARM::VST4q16: 1827 case ARM::VST4q32: 1828 case ARM::VST4q8_UPD: 1829 case ARM::VST4q16_UPD: 1830 case ARM::VST4q32_UPD: 1831 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1832 break; 1833 default: 1834 break; 1835 } 1836 1837 // Fourth input register 1838 switch (Inst.getOpcode()) { 1839 case ARM::VST1d8Q: 1840 case ARM::VST1d16Q: 1841 case ARM::VST1d32Q: 1842 case ARM::VST1d64Q: 1843 case ARM::VST1d8Q_UPD: 1844 case ARM::VST1d16Q_UPD: 1845 case ARM::VST1d32Q_UPD: 1846 case ARM::VST1d64Q_UPD: 1847 case ARM::VST2q8: 1848 case ARM::VST2q16: 1849 case ARM::VST2q32: 1850 case ARM::VST2q8_UPD: 1851 case ARM::VST2q16_UPD: 1852 case ARM::VST2q32_UPD: 1853 case ARM::VST4d8: 1854 case ARM::VST4d16: 1855 case ARM::VST4d32: 1856 case ARM::VST4d8_UPD: 1857 case ARM::VST4d16_UPD: 1858 case ARM::VST4d32_UPD: 1859 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1860 break; 1861 case ARM::VST4q8: 1862 case ARM::VST4q16: 1863 case ARM::VST4q32: 1864 case ARM::VST4q8_UPD: 1865 case ARM::VST4q16_UPD: 1866 case ARM::VST4q32_UPD: 1867 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1868 break; 1869 default: 1870 break; 1871 } 1872 1873 return true; 1874 } 1875 1876 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1877 uint64_t Address, const void *Decoder) { 1878 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1879 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1880 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1881 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1882 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1883 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1884 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1885 1886 align *= (1 << size); 1887 1888 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1889 if (regs == 2) { 1890 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1891 } 1892 if (Rm == 0xD) { 1893 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1894 } 1895 1896 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1897 Inst.addOperand(MCOperand::CreateImm(align)); 1898 1899 if (Rm == 0xD) 1900 Inst.addOperand(MCOperand::CreateReg(0)); 1901 else if (Rm != 0xF) { 1902 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1903 } 1904 1905 return true; 1906 } 1907 1908 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1909 uint64_t Address, const void *Decoder) { 1910 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1911 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1912 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1913 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1914 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1915 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1916 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1917 align *= 2*size; 1918 1919 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1920 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1921 if (Rm == 0xD) { 1922 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1923 } 1924 1925 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1926 Inst.addOperand(MCOperand::CreateImm(align)); 1927 1928 if (Rm == 0xD) 1929 Inst.addOperand(MCOperand::CreateReg(0)); 1930 else if (Rm != 0xF) { 1931 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1932 } 1933 1934 return true; 1935 } 1936 1937 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1938 uint64_t Address, const void *Decoder) { 1939 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1940 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1941 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1942 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1943 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1944 1945 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1946 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1947 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1948 return false; 1949 if (Rm == 0xD) { 1950 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1951 } 1952 1953 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1954 Inst.addOperand(MCOperand::CreateImm(0)); 1955 1956 if (Rm == 0xD) 1957 Inst.addOperand(MCOperand::CreateReg(0)); 1958 else if (Rm != 0xF) { 1959 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1960 } 1961 1962 return true; 1963 } 1964 1965 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1966 uint64_t Address, const void *Decoder) { 1967 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1968 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1969 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1970 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1971 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1972 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1973 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1974 1975 if (size == 0x3) { 1976 size = 4; 1977 align = 16; 1978 } else { 1979 if (size == 2) { 1980 size = 1 << size; 1981 align *= 8; 1982 } else { 1983 size = 1 << size; 1984 align *= 4*size; 1985 } 1986 } 1987 1988 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1989 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1990 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1991 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 1992 return false; 1993 if (Rm == 0xD) { 1994 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1995 } 1996 1997 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1998 Inst.addOperand(MCOperand::CreateImm(align)); 1999 2000 if (Rm == 0xD) 2001 Inst.addOperand(MCOperand::CreateReg(0)); 2002 else if (Rm != 0xF) { 2003 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2004 } 2005 2006 return true; 2007 } 2008 2009 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2010 uint64_t Address, const void *Decoder) { 2011 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2012 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2013 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2014 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2015 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2016 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2017 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2018 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2019 2020 if (Q) { 2021 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2022 } else { 2023 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2024 } 2025 2026 Inst.addOperand(MCOperand::CreateImm(imm)); 2027 2028 switch (Inst.getOpcode()) { 2029 case ARM::VORRiv4i16: 2030 case ARM::VORRiv2i32: 2031 case ARM::VBICiv4i16: 2032 case ARM::VBICiv2i32: 2033 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2034 break; 2035 case ARM::VORRiv8i16: 2036 case ARM::VORRiv4i32: 2037 case ARM::VBICiv8i16: 2038 case ARM::VBICiv4i32: 2039 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2040 break; 2041 default: 2042 break; 2043 } 2044 2045 return true; 2046 } 2047 2048 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2049 uint64_t Address, const void *Decoder) { 2050 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2051 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2052 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2053 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2054 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2055 2056 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2057 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2058 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2059 2060 return true; 2061 } 2062 2063 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2064 uint64_t Address, const void *Decoder) { 2065 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2066 return true; 2067 } 2068 2069 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2070 uint64_t Address, const void *Decoder) { 2071 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2072 return true; 2073 } 2074 2075 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2076 uint64_t Address, const void *Decoder) { 2077 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2078 return true; 2079 } 2080 2081 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2082 uint64_t Address, const void *Decoder) { 2083 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2084 return true; 2085 } 2086 2087 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2088 uint64_t Address, const void *Decoder) { 2089 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2090 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2091 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2092 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2093 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2094 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2095 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2096 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2097 2098 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2099 if (op) { 2100 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2101 } 2102 2103 for (unsigned i = 0; i < length; ++i) { 2104 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2105 } 2106 2107 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2108 2109 return true; 2110 } 2111 2112 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2113 uint64_t Address, const void *Decoder) { 2114 // The immediate needs to be a fully instantiated float. However, the 2115 // auto-generated decoder is only able to fill in some of the bits 2116 // necessary. For instance, the 'b' bit is replicated multiple times, 2117 // and is even present in inverted form in one bit. We do a little 2118 // binary parsing here to fill in those missing bits, and then 2119 // reinterpret it all as a float. 2120 union { 2121 uint32_t integer; 2122 float fp; 2123 } fp_conv; 2124 2125 fp_conv.integer = Val; 2126 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2127 fp_conv.integer |= b << 26; 2128 fp_conv.integer |= b << 27; 2129 fp_conv.integer |= b << 28; 2130 fp_conv.integer |= b << 29; 2131 fp_conv.integer |= (~b & 0x1) << 30; 2132 2133 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2134 return true; 2135 } 2136 2137 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2138 uint64_t Address, const void *Decoder) { 2139 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2140 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2141 2142 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2143 2144 if (Inst.getOpcode() == ARM::tADR) 2145 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2146 else if (Inst.getOpcode() == ARM::tADDrSPi) 2147 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2148 else 2149 return false; 2150 2151 Inst.addOperand(MCOperand::CreateImm(imm)); 2152 return true; 2153 } 2154 2155 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2156 uint64_t Address, const void *Decoder) { 2157 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2158 return true; 2159 } 2160 2161 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2162 uint64_t Address, const void *Decoder) { 2163 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2164 return true; 2165 } 2166 2167 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2168 uint64_t Address, const void *Decoder) { 2169 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2170 return true; 2171 } 2172 2173 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2174 uint64_t Address, const void *Decoder) { 2175 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2176 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2177 2178 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2179 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2180 return false; 2181 2182 return true; 2183 } 2184 2185 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2186 uint64_t Address, const void *Decoder) { 2187 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2188 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2189 2190 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2191 Inst.addOperand(MCOperand::CreateImm(imm)); 2192 2193 return true; 2194 } 2195 2196 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2197 uint64_t Address, const void *Decoder) { 2198 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2199 2200 return true; 2201 } 2202 2203 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2204 uint64_t Address, const void *Decoder) { 2205 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2206 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2207 2208 return true; 2209 } 2210 2211 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2212 uint64_t Address, const void *Decoder) { 2213 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2214 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2215 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2216 2217 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2218 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2219 return false; 2220 Inst.addOperand(MCOperand::CreateImm(imm)); 2221 2222 return true; 2223 } 2224 2225 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2226 uint64_t Address, const void *Decoder) { 2227 if (Inst.getOpcode() != ARM::t2PLDs) { 2228 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2229 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2230 } 2231 2232 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2233 if (Rn == 0xF) { 2234 switch (Inst.getOpcode()) { 2235 case ARM::t2LDRBs: 2236 Inst.setOpcode(ARM::t2LDRBpci); 2237 break; 2238 case ARM::t2LDRHs: 2239 Inst.setOpcode(ARM::t2LDRHpci); 2240 break; 2241 case ARM::t2LDRSHs: 2242 Inst.setOpcode(ARM::t2LDRSHpci); 2243 break; 2244 case ARM::t2LDRSBs: 2245 Inst.setOpcode(ARM::t2LDRSBpci); 2246 break; 2247 case ARM::t2PLDs: 2248 Inst.setOpcode(ARM::t2PLDi12); 2249 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2250 break; 2251 default: 2252 return false; 2253 } 2254 2255 int imm = fieldFromInstruction32(Insn, 0, 12); 2256 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2257 Inst.addOperand(MCOperand::CreateImm(imm)); 2258 2259 return true; 2260 } 2261 2262 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2263 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2264 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2265 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2266 2267 return true; 2268 } 2269 2270 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2271 uint64_t Address, const void *Decoder) { 2272 int imm = Val & 0xFF; 2273 if (!(Val & 0x100)) imm *= -1; 2274 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2275 2276 return true; 2277 } 2278 2279 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2280 uint64_t Address, const void *Decoder) { 2281 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2282 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2283 2284 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2285 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2286 return false; 2287 2288 return true; 2289 } 2290 2291 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2292 uint64_t Address, const void *Decoder) { 2293 int imm = Val & 0xFF; 2294 if (!(Val & 0x100)) imm *= -1; 2295 Inst.addOperand(MCOperand::CreateImm(imm)); 2296 2297 return true; 2298 } 2299 2300 2301 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2302 uint64_t Address, const void *Decoder) { 2303 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2304 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2305 2306 // Some instructions always use an additive offset. 2307 switch (Inst.getOpcode()) { 2308 case ARM::t2LDRT: 2309 case ARM::t2LDRBT: 2310 case ARM::t2LDRHT: 2311 case ARM::t2LDRSBT: 2312 case ARM::t2LDRSHT: 2313 imm |= 0x100; 2314 break; 2315 default: 2316 break; 2317 } 2318 2319 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2320 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2321 return false; 2322 2323 return true; 2324 } 2325 2326 2327 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2328 uint64_t Address, const void *Decoder) { 2329 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2330 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2331 2332 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2333 Inst.addOperand(MCOperand::CreateImm(imm)); 2334 2335 return true; 2336 } 2337 2338 2339 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2340 uint64_t Address, const void *Decoder) { 2341 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2342 2343 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2344 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2345 Inst.addOperand(MCOperand::CreateImm(imm)); 2346 2347 return true; 2348 } 2349 2350 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2351 uint64_t Address, const void *Decoder) { 2352 if (Inst.getOpcode() == ARM::tADDrSP) { 2353 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2354 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2355 2356 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2357 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2358 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2359 } else if (Inst.getOpcode() == ARM::tADDspr) { 2360 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2361 2362 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2363 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2364 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2365 } 2366 2367 return true; 2368 } 2369 2370 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2371 uint64_t Address, const void *Decoder) { 2372 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2373 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2374 2375 Inst.addOperand(MCOperand::CreateImm(imod)); 2376 Inst.addOperand(MCOperand::CreateImm(flags)); 2377 2378 return true; 2379 } 2380 2381 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2382 uint64_t Address, const void *Decoder) { 2383 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2384 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2385 2386 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2387 Inst.addOperand(MCOperand::CreateImm(add)); 2388 2389 return true; 2390 } 2391 2392 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2393 uint64_t Address, const void *Decoder) { 2394 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2395 return true; 2396 } 2397 2398 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2399 uint64_t Address, const void *Decoder) { 2400 if (Val == 0xA || Val == 0xB) 2401 return false; 2402 2403 Inst.addOperand(MCOperand::CreateImm(Val)); 2404 return true; 2405 } 2406 2407 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2408 uint64_t Address, const void *Decoder) { 2409 if (Val == 0) 2410 Inst.addOperand(MCOperand::CreateImm(32)); 2411 else 2412 Inst.addOperand(MCOperand::CreateImm(Val)); 2413 return true; 2414 } 2415 2416 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2417 uint64_t Address, const void *Decoder) { 2418 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2419 if (pred == 0xE || pred == 0xF) { 2420 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2421 switch (opc) { 2422 default: 2423 return false; 2424 case 0: 2425 Inst.setOpcode(ARM::t2DSB); 2426 break; 2427 case 1: 2428 Inst.setOpcode(ARM::t2DMB); 2429 break; 2430 case 2: 2431 Inst.setOpcode(ARM::t2ISB); 2432 return true; 2433 } 2434 2435 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2436 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2437 } 2438 2439 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2440 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2441 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2442 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2443 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2444 2445 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2446 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2447 return false; 2448 2449 return true; 2450 } 2451 2452 // Decode a shifted immediate operand. These basically consist 2453 // of an 8-bit value, and a 4-bit directive that specifies either 2454 // a splat operation or a rotation. 2455 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2456 uint64_t Address, const void *Decoder) { 2457 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2458 if (ctrl == 0) { 2459 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2460 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2461 switch (byte) { 2462 case 0: 2463 Inst.addOperand(MCOperand::CreateImm(imm)); 2464 break; 2465 case 1: 2466 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2467 break; 2468 case 2: 2469 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2470 break; 2471 case 3: 2472 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2473 (imm << 8) | imm)); 2474 break; 2475 } 2476 } else { 2477 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2478 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2479 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2480 Inst.addOperand(MCOperand::CreateImm(imm)); 2481 } 2482 2483 return true; 2484 } 2485 2486 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2487 uint64_t Address, const void *Decoder){ 2488 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2489 return true; 2490 } 2491 2492 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2493 uint64_t Address, const void *Decoder){ 2494 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2495 return true; 2496 } 2497 2498 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2499 uint64_t Address, const void *Decoder) { 2500 switch (Val) { 2501 default: 2502 return false; 2503 case 0xF: // SY 2504 case 0xE: // ST 2505 case 0xB: // ISH 2506 case 0xA: // ISHST 2507 case 0x7: // NSH 2508 case 0x6: // NSHST 2509 case 0x3: // OSH 2510 case 0x2: // OSHST 2511 break; 2512 } 2513 2514 Inst.addOperand(MCOperand::CreateImm(Val)); 2515 return true; 2516 } 2517 2518 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2519 uint64_t Address, const void *Decoder) { 2520 if (!Val) return false; 2521 Inst.addOperand(MCOperand::CreateImm(Val)); 2522 return true; 2523 } 2524 2525 static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2526 uint64_t Address, const void *Decoder) { 2527 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2528 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2529 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2530 2531 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2532 2533 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2534 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2535 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2536 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2537 2538 return true; 2539 } 2540 2541 2542 static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2543 uint64_t Address, const void *Decoder) { 2544 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2545 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2546 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2547 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2548 2549 if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2550 2551 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2552 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; 2553 2554 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2555 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2556 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2557 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2558 2559 return true; 2560 } 2561 2562 static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2563 uint64_t Address, const void *Decoder) { 2564 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2565 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2566 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2567 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2568 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2569 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2570 2571 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2572 2573 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2574 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2575 if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false; 2576 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2577 2578 return true; 2579 } 2580 2581 static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2582 uint64_t Address, const void *Decoder) { 2583 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2584 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2585 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2586 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2587 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2588 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2589 2590 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2591 2592 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2593 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2594 if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false; 2595 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2596 2597 return true; 2598 } 2599 2600 static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2601 uint64_t Address, const void *Decoder) { 2602 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2603 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2604 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2605 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2606 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2607 2608 unsigned align = 0; 2609 unsigned index = 0; 2610 switch (size) { 2611 default: 2612 return false; 2613 case 0: 2614 if (fieldFromInstruction32(Insn, 4, 1)) 2615 return false; // UNDEFINED 2616 index = fieldFromInstruction32(Insn, 5, 3); 2617 break; 2618 case 1: 2619 if (fieldFromInstruction32(Insn, 5, 1)) 2620 return false; // UNDEFINED 2621 index = fieldFromInstruction32(Insn, 6, 2); 2622 if (fieldFromInstruction32(Insn, 4, 1)) 2623 align = 2; 2624 break; 2625 case 2: 2626 if (fieldFromInstruction32(Insn, 6, 1)) 2627 return false; // UNDEFINED 2628 index = fieldFromInstruction32(Insn, 7, 1); 2629 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2630 align = 4; 2631 } 2632 2633 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2634 if (Rm != 0xF) { // Writeback 2635 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2636 return false; 2637 } 2638 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2639 Inst.addOperand(MCOperand::CreateImm(align)); 2640 if (Rm != 0xF && Rm != 0xD) { 2641 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2642 return false; 2643 } 2644 2645 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2646 Inst.addOperand(MCOperand::CreateImm(index)); 2647 2648 return true; 2649 } 2650 2651 static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2652 uint64_t Address, const void *Decoder) { 2653 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2654 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2655 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2656 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2657 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2658 2659 unsigned align = 0; 2660 unsigned index = 0; 2661 switch (size) { 2662 default: 2663 return false; 2664 case 0: 2665 if (fieldFromInstruction32(Insn, 4, 1)) 2666 return false; // UNDEFINED 2667 index = fieldFromInstruction32(Insn, 5, 3); 2668 break; 2669 case 1: 2670 if (fieldFromInstruction32(Insn, 5, 1)) 2671 return false; // UNDEFINED 2672 index = fieldFromInstruction32(Insn, 6, 2); 2673 if (fieldFromInstruction32(Insn, 4, 1)) 2674 align = 2; 2675 break; 2676 case 2: 2677 if (fieldFromInstruction32(Insn, 6, 1)) 2678 return false; // UNDEFINED 2679 index = fieldFromInstruction32(Insn, 7, 1); 2680 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2681 align = 4; 2682 } 2683 2684 if (Rm != 0xF) { // Writeback 2685 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2686 return false; 2687 } 2688 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2689 Inst.addOperand(MCOperand::CreateImm(align)); 2690 if (Rm != 0xF && Rm != 0xD) { 2691 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2692 return false; 2693 } 2694 2695 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2696 Inst.addOperand(MCOperand::CreateImm(index)); 2697 2698 return true; 2699 } 2700 2701 2702 static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2703 uint64_t Address, const void *Decoder) { 2704 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2705 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2706 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2707 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2708 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2709 2710 unsigned align = 0; 2711 unsigned index = 0; 2712 unsigned inc = 1; 2713 switch (size) { 2714 default: 2715 return false; 2716 case 0: 2717 index = fieldFromInstruction32(Insn, 5, 3); 2718 if (fieldFromInstruction32(Insn, 4, 1)) 2719 align = 2; 2720 break; 2721 case 1: 2722 index = fieldFromInstruction32(Insn, 6, 2); 2723 if (fieldFromInstruction32(Insn, 4, 1)) 2724 align = 4; 2725 if (fieldFromInstruction32(Insn, 5, 1)) 2726 inc = 2; 2727 break; 2728 case 2: 2729 if (fieldFromInstruction32(Insn, 5, 1)) 2730 return false; // UNDEFINED 2731 index = fieldFromInstruction32(Insn, 7, 1); 2732 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2733 align = 8; 2734 if (fieldFromInstruction32(Insn, 6, 1)) 2735 inc = 2; 2736 break; 2737 } 2738 2739 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2740 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2741 if (Rm != 0xF) { // Writeback 2742 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2743 return false; 2744 } 2745 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2746 Inst.addOperand(MCOperand::CreateImm(align)); 2747 if (Rm != 0xF && Rm != 0xD) { 2748 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2749 return false; 2750 } 2751 2752 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2753 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2754 Inst.addOperand(MCOperand::CreateImm(index)); 2755 2756 return true; 2757 } 2758 2759 static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2760 uint64_t Address, const void *Decoder) { 2761 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2762 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2763 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2764 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2765 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2766 2767 unsigned align = 0; 2768 unsigned index = 0; 2769 unsigned inc = 1; 2770 switch (size) { 2771 default: 2772 return false; 2773 case 0: 2774 index = fieldFromInstruction32(Insn, 5, 3); 2775 if (fieldFromInstruction32(Insn, 4, 1)) 2776 align = 2; 2777 break; 2778 case 1: 2779 index = fieldFromInstruction32(Insn, 6, 2); 2780 if (fieldFromInstruction32(Insn, 4, 1)) 2781 align = 4; 2782 if (fieldFromInstruction32(Insn, 5, 1)) 2783 inc = 2; 2784 break; 2785 case 2: 2786 if (fieldFromInstruction32(Insn, 5, 1)) 2787 return false; // UNDEFINED 2788 index = fieldFromInstruction32(Insn, 7, 1); 2789 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2790 align = 8; 2791 if (fieldFromInstruction32(Insn, 6, 1)) 2792 inc = 2; 2793 break; 2794 } 2795 2796 if (Rm != 0xF) { // Writeback 2797 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2798 return false; 2799 } 2800 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2801 Inst.addOperand(MCOperand::CreateImm(align)); 2802 if (Rm != 0xF && Rm != 0xD) { 2803 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2804 return false; 2805 } 2806 2807 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2808 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2809 Inst.addOperand(MCOperand::CreateImm(index)); 2810 2811 return true; 2812 } 2813 2814 2815 static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 2816 uint64_t Address, const void *Decoder) { 2817 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2818 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2819 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2820 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2821 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2822 2823 unsigned align = 0; 2824 unsigned index = 0; 2825 unsigned inc = 1; 2826 switch (size) { 2827 default: 2828 return false; 2829 case 0: 2830 if (fieldFromInstruction32(Insn, 4, 1)) 2831 return false; // UNDEFINED 2832 index = fieldFromInstruction32(Insn, 5, 3); 2833 break; 2834 case 1: 2835 if (fieldFromInstruction32(Insn, 4, 1)) 2836 return false; // UNDEFINED 2837 index = fieldFromInstruction32(Insn, 6, 2); 2838 if (fieldFromInstruction32(Insn, 5, 1)) 2839 inc = 2; 2840 break; 2841 case 2: 2842 if (fieldFromInstruction32(Insn, 4, 2)) 2843 return false; // UNDEFINED 2844 index = fieldFromInstruction32(Insn, 7, 1); 2845 if (fieldFromInstruction32(Insn, 6, 1)) 2846 inc = 2; 2847 break; 2848 } 2849 2850 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2851 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2852 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2853 2854 if (Rm != 0xF) { // Writeback 2855 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2856 return false; 2857 } 2858 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2859 Inst.addOperand(MCOperand::CreateImm(align)); 2860 if (Rm != 0xF && Rm != 0xD) { 2861 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2862 return false; 2863 } 2864 2865 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2866 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2867 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2868 Inst.addOperand(MCOperand::CreateImm(index)); 2869 2870 return true; 2871 } 2872 2873 static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 2874 uint64_t Address, const void *Decoder) { 2875 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2876 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2877 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2878 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2879 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2880 2881 unsigned align = 0; 2882 unsigned index = 0; 2883 unsigned inc = 1; 2884 switch (size) { 2885 default: 2886 return false; 2887 case 0: 2888 if (fieldFromInstruction32(Insn, 4, 1)) 2889 return false; // UNDEFINED 2890 index = fieldFromInstruction32(Insn, 5, 3); 2891 break; 2892 case 1: 2893 if (fieldFromInstruction32(Insn, 4, 1)) 2894 return false; // UNDEFINED 2895 index = fieldFromInstruction32(Insn, 6, 2); 2896 if (fieldFromInstruction32(Insn, 5, 1)) 2897 inc = 2; 2898 break; 2899 case 2: 2900 if (fieldFromInstruction32(Insn, 4, 2)) 2901 return false; // UNDEFINED 2902 index = fieldFromInstruction32(Insn, 7, 1); 2903 if (fieldFromInstruction32(Insn, 6, 1)) 2904 inc = 2; 2905 break; 2906 } 2907 2908 if (Rm != 0xF) { // Writeback 2909 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2910 return false; 2911 } 2912 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2913 Inst.addOperand(MCOperand::CreateImm(align)); 2914 if (Rm != 0xF && Rm != 0xD) { 2915 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2916 return false; 2917 } 2918 2919 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2920 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2921 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2922 Inst.addOperand(MCOperand::CreateImm(index)); 2923 2924 return true; 2925 } 2926 2927 2928 static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 2929 uint64_t Address, const void *Decoder) { 2930 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2931 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2932 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2933 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2934 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2935 2936 unsigned align = 0; 2937 unsigned index = 0; 2938 unsigned inc = 1; 2939 switch (size) { 2940 default: 2941 return false; 2942 case 0: 2943 if (fieldFromInstruction32(Insn, 4, 1)) 2944 align = 4; 2945 index = fieldFromInstruction32(Insn, 5, 3); 2946 break; 2947 case 1: 2948 if (fieldFromInstruction32(Insn, 4, 1)) 2949 align = 8; 2950 index = fieldFromInstruction32(Insn, 6, 2); 2951 if (fieldFromInstruction32(Insn, 5, 1)) 2952 inc = 2; 2953 break; 2954 case 2: 2955 if (fieldFromInstruction32(Insn, 4, 2)) 2956 align = 4 << fieldFromInstruction32(Insn, 4, 2); 2957 index = fieldFromInstruction32(Insn, 7, 1); 2958 if (fieldFromInstruction32(Insn, 6, 1)) 2959 inc = 2; 2960 break; 2961 } 2962 2963 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2964 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2965 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2966 if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; 2967 2968 if (Rm != 0xF) { // Writeback 2969 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2970 return false; 2971 } 2972 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2973 Inst.addOperand(MCOperand::CreateImm(align)); 2974 if (Rm != 0xF && Rm != 0xD) { 2975 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2976 return false; 2977 } 2978 2979 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2980 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2981 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2982 if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; 2983 Inst.addOperand(MCOperand::CreateImm(index)); 2984 2985 return true; 2986 } 2987 2988 static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 2989 uint64_t Address, const void *Decoder) { 2990 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2991 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2992 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2993 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2994 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2995 2996 unsigned align = 0; 2997 unsigned index = 0; 2998 unsigned inc = 1; 2999 switch (size) { 3000 default: 3001 return false; 3002 case 0: 3003 if (fieldFromInstruction32(Insn, 4, 1)) 3004 align = 4; 3005 index = fieldFromInstruction32(Insn, 5, 3); 3006 break; 3007 case 1: 3008 if (fieldFromInstruction32(Insn, 4, 1)) 3009 align = 8; 3010 index = fieldFromInstruction32(Insn, 6, 2); 3011 if (fieldFromInstruction32(Insn, 5, 1)) 3012 inc = 2; 3013 break; 3014 case 2: 3015 if (fieldFromInstruction32(Insn, 4, 2)) 3016 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3017 index = fieldFromInstruction32(Insn, 7, 1); 3018 if (fieldFromInstruction32(Insn, 6, 1)) 3019 inc = 2; 3020 break; 3021 } 3022 3023 if (Rm != 0xF) { // Writeback 3024 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 3025 return false; 3026 } 3027 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 3028 Inst.addOperand(MCOperand::CreateImm(align)); 3029 if (Rm != 0xF && Rm != 0xD) { 3030 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 3031 return false; 3032 } 3033 3034 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 3035 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 3036 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 3037 if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; 3038 Inst.addOperand(MCOperand::CreateImm(index)); 3039 3040 return true; 3041 } 3042 3043