1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142 private: 143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 144 ArrayRef<uint8_t> Bytes, uint64_t Address, 145 raw_ostream &CStream) const; 146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 148 ArrayRef<uint8_t> Bytes, uint64_t Address, 149 raw_ostream &CStream) const; 150 151 mutable ITStatus ITBlock; 152 mutable VPTStatus VPTBlock; 153 154 DecodeStatus AddThumbPredicate(MCInst&) const; 155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 156 }; 157 158 } // end anonymous namespace 159 160 static bool Check(DecodeStatus &Out, DecodeStatus In) { 161 switch (In) { 162 case MCDisassembler::Success: 163 // Out stays the same. 164 return true; 165 case MCDisassembler::SoftFail: 166 Out = In; 167 return true; 168 case MCDisassembler::Fail: 169 Out = In; 170 return false; 171 } 172 llvm_unreachable("Invalid DecodeStatus!"); 173 } 174 175 // Forward declare these because the autogenerated code will reference them. 176 // Definitions are further down. 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus 186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodeGPRwithZRnospRegisterClass( 198 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, 211 const void *Decoder); 212 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 223 unsigned RegNo, 224 uint64_t Address, 225 const void *Decoder); 226 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 231 uint64_t Address, 232 const void *Decoder); 233 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 234 uint64_t Address, 235 const void *Decoder); 236 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 239 unsigned RegNo, uint64_t Address, 240 const void *Decoder); 241 242 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 253 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 258 unsigned Insn, 259 uint64_t Address, 260 const void *Decoder); 261 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 270 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 271 unsigned Insn, 272 uint64_t Adddress, 273 const void *Decoder); 274 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void *Decoder); 346 template<int shift> 347 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 400 unsigned Val, 401 uint64_t Address, 402 const void *Decoder); 403 404 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 417 uint64_t Address, const void *Decoder); 418 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 419 uint64_t Address, const void *Decoder); 420 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 421 uint64_t Address, const void *Decoder); 422 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 423 uint64_t Address, const void *Decoder); 424 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 425 uint64_t Address, const void* Decoder); 426 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void* Decoder); 428 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 429 uint64_t Address, const void* Decoder); 430 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 431 uint64_t Address, const void* Decoder); 432 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 433 uint64_t Address, const void *Decoder); 434 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 435 uint64_t Address, const void *Decoder); 436 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 437 uint64_t Address, const void *Decoder); 438 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 439 uint64_t Address, 440 const void *Decoder); 441 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 442 uint64_t Address, const void *Decoder); 443 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 444 uint64_t Address, const void *Decoder); 445 template<int shift> 446 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 447 uint64_t Address, const void *Decoder); 448 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 449 uint64_t Address, const void *Decoder); 450 template<int shift> 451 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 452 uint64_t Address, const void *Decoder); 453 template<int shift, int WriteBack> 454 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 455 uint64_t Address, const void *Decoder); 456 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 457 uint64_t Address, const void *Decoder); 458 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 459 uint64_t Address, const void *Decoder); 460 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 461 uint64_t Address, const void *Decoder); 462 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 463 uint64_t Address, const void *Decoder); 464 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 465 uint64_t Address, const void *Decoder); 466 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 467 uint64_t Address, const void *Decoder); 468 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 469 uint64_t Address, const void *Decoder); 470 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 471 uint64_t Address, const void *Decoder); 472 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 473 uint64_t Address, const void *Decoder); 474 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 475 uint64_t Address, const void *Decoder); 476 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 477 uint64_t Address, const void *Decoder); 478 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 479 uint64_t Address, const void *Decoder); 480 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 481 uint64_t Address, const void *Decoder); 482 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 483 uint64_t Address, const void *Decoder); 484 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 489 uint64_t Address, const void *Decoder); 490 491 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 492 uint64_t Address, const void *Decoder); 493 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 494 uint64_t Address, const void *Decoder); 495 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 496 uint64_t Address, const void *Decoder); 497 498 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 499 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 500 uint64_t Address, const void *Decoder); 501 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 502 uint64_t Address, 503 const void *Decoder); 504 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 505 uint64_t Address, 506 const void *Decoder); 507 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 508 const void *Decoder); 509 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 510 uint64_t Address, 511 const void *Decoder); 512 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 513 const void *Decoder); 514 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 515 uint64_t Address, const void *Decoder); 516 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 517 uint64_t Address, const void *Decoder); 518 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 519 uint64_t Address, 520 const void *Decoder); 521 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 522 uint64_t Address, 523 const void *Decoder); 524 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 525 uint64_t Address, 526 const void *Decoder); 527 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 528 unsigned Val, 529 uint64_t Address, 530 const void *Decoder); 531 template<bool Writeback> 532 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 533 uint64_t Address, 534 const void *Decoder); 535 template<int shift> 536 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 537 uint64_t Address, const void *Decoder); 538 template<int shift> 539 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 540 uint64_t Address, const void *Decoder); 541 template<int shift> 542 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 543 uint64_t Address, const void *Decoder); 544 template<unsigned MinLog, unsigned MaxLog> 545 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 546 uint64_t Address, 547 const void *Decoder); 548 template<unsigned start> 549 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 550 uint64_t Address, 551 const void *Decoder); 552 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 553 uint64_t Address, 554 const void *Decoder); 555 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 556 uint64_t Address, 557 const void *Decoder); 558 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 559 uint64_t Address, const void *Decoder); 560 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 561 uint64_t Address, const void *Decoder); 562 template<bool scalar, OperandDecoder predicate_decoder> 563 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 564 uint64_t Address, const void *Decoder); 565 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 566 uint64_t Address, const void *Decoder); 567 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 568 uint64_t Address, const void *Decoder); 569 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 570 uint64_t Address, 571 const void *Decoder); 572 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 573 uint64_t Address, const void *Decoder); 574 575 #include "ARMGenDisassemblerTables.inc" 576 577 static MCDisassembler *createARMDisassembler(const Target &T, 578 const MCSubtargetInfo &STI, 579 MCContext &Ctx) { 580 return new ARMDisassembler(STI, Ctx); 581 } 582 583 // Post-decoding checks 584 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 585 uint64_t Address, raw_ostream &CS, 586 uint32_t Insn, 587 DecodeStatus Result) { 588 switch (MI.getOpcode()) { 589 case ARM::HVC: { 590 // HVC is undefined if condition = 0xf otherwise upredictable 591 // if condition != 0xe 592 uint32_t Cond = (Insn >> 28) & 0xF; 593 if (Cond == 0xF) 594 return MCDisassembler::Fail; 595 if (Cond != 0xE) 596 return MCDisassembler::SoftFail; 597 return Result; 598 } 599 case ARM::t2ADDri: 600 case ARM::t2ADDri12: 601 case ARM::t2ADDrr: 602 case ARM::t2ADDrs: 603 case ARM::t2SUBri: 604 case ARM::t2SUBri12: 605 case ARM::t2SUBrr: 606 case ARM::t2SUBrs: 607 if (MI.getOperand(0).getReg() == ARM::SP && 608 MI.getOperand(1).getReg() != ARM::SP) 609 return MCDisassembler::SoftFail; 610 return Result; 611 default: return Result; 612 } 613 } 614 615 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 616 ArrayRef<uint8_t> Bytes, 617 uint64_t Address, 618 raw_ostream &CS) const { 619 if (STI.getFeatureBits()[ARM::ModeThumb]) 620 return getThumbInstruction(MI, Size, Bytes, Address, CS); 621 return getARMInstruction(MI, Size, Bytes, Address, CS); 622 } 623 624 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 625 ArrayRef<uint8_t> Bytes, 626 uint64_t Address, 627 raw_ostream &CS) const { 628 CommentStream = &CS; 629 630 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 631 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 632 "mode!"); 633 634 // We want to read exactly 4 bytes of data. 635 if (Bytes.size() < 4) { 636 Size = 0; 637 return MCDisassembler::Fail; 638 } 639 640 // Encoded as a small-endian 32-bit word in the stream. 641 uint32_t Insn = 642 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 643 644 // Calling the auto-generated decoder function. 645 DecodeStatus Result = 646 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 647 if (Result != MCDisassembler::Fail) { 648 Size = 4; 649 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 650 } 651 652 struct DecodeTable { 653 const uint8_t *P; 654 bool DecodePred; 655 }; 656 657 const DecodeTable Tables[] = { 658 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 659 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 660 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 661 {DecoderTablev8Crypto32, false}, 662 }; 663 664 for (auto Table : Tables) { 665 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 666 if (Result != MCDisassembler::Fail) { 667 Size = 4; 668 // Add a fake predicate operand, because we share these instruction 669 // definitions with Thumb2 where these instructions are predicable. 670 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 671 return MCDisassembler::Fail; 672 return Result; 673 } 674 } 675 676 Result = 677 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 678 if (Result != MCDisassembler::Fail) { 679 Size = 4; 680 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 681 } 682 683 Size = 4; 684 return MCDisassembler::Fail; 685 } 686 687 namespace llvm { 688 689 extern const MCInstrDesc ARMInsts[]; 690 691 } // end namespace llvm 692 693 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 694 /// immediate Value in the MCInst. The immediate Value has had any PC 695 /// adjustment made by the caller. If the instruction is a branch instruction 696 /// then isBranch is true, else false. If the getOpInfo() function was set as 697 /// part of the setupForSymbolicDisassembly() call then that function is called 698 /// to get any symbolic information at the Address for this instruction. If 699 /// that returns non-zero then the symbolic information it returns is used to 700 /// create an MCExpr and that is added as an operand to the MCInst. If 701 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 702 /// Value is done and if a symbol is found an MCExpr is created with that, else 703 /// an MCExpr with Value is created. This function returns true if it adds an 704 /// operand to the MCInst and false otherwise. 705 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 706 bool isBranch, uint64_t InstSize, 707 MCInst &MI, const void *Decoder) { 708 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 709 // FIXME: Does it make sense for value to be negative? 710 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 711 /* Offset */ 0, InstSize); 712 } 713 714 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 715 /// referenced by a load instruction with the base register that is the Pc. 716 /// These can often be values in a literal pool near the Address of the 717 /// instruction. The Address of the instruction and its immediate Value are 718 /// used as a possible literal pool entry. The SymbolLookUp call back will 719 /// return the name of a symbol referenced by the literal pool's entry if 720 /// the referenced address is that of a symbol. Or it will return a pointer to 721 /// a literal 'C' string if the referenced address of the literal pool's entry 722 /// is an address into a section with 'C' string literals. 723 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 724 const void *Decoder) { 725 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 726 Dis->tryAddingPcLoadReferenceComment(Value, Address); 727 } 728 729 // Thumb1 instructions don't have explicit S bits. Rather, they 730 // implicitly set CPSR. Since it's not represented in the encoding, the 731 // auto-generated decoder won't inject the CPSR operand. We need to fix 732 // that as a post-pass. 733 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 734 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 735 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 736 MCInst::iterator I = MI.begin(); 737 for (unsigned i = 0; i < NumOps; ++i, ++I) { 738 if (I == MI.end()) break; 739 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 740 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 741 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 742 return; 743 } 744 } 745 746 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 747 } 748 749 static bool isVectorPredicable(unsigned Opcode) { 750 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 751 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 752 for (unsigned i = 0; i < NumOps; ++i) { 753 if (ARM::isVpred(OpInfo[i].OperandType)) 754 return true; 755 } 756 return false; 757 } 758 759 // Most Thumb instructions don't have explicit predicates in the 760 // encoding, but rather get their predicates from IT context. We need 761 // to fix up the predicate operands using this context information as a 762 // post-pass. 763 MCDisassembler::DecodeStatus 764 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 765 MCDisassembler::DecodeStatus S = Success; 766 767 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 768 769 // A few instructions actually have predicates encoded in them. Don't 770 // try to overwrite it if we're seeing one of those. 771 switch (MI.getOpcode()) { 772 case ARM::tBcc: 773 case ARM::t2Bcc: 774 case ARM::tCBZ: 775 case ARM::tCBNZ: 776 case ARM::tCPS: 777 case ARM::t2CPS3p: 778 case ARM::t2CPS2p: 779 case ARM::t2CPS1p: 780 case ARM::t2CSEL: 781 case ARM::t2CSINC: 782 case ARM::t2CSINV: 783 case ARM::t2CSNEG: 784 case ARM::tMOVSr: 785 case ARM::tSETEND: 786 // Some instructions (mostly conditional branches) are not 787 // allowed in IT blocks. 788 if (ITBlock.instrInITBlock()) 789 S = SoftFail; 790 else 791 return Success; 792 break; 793 case ARM::t2HINT: 794 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 795 S = SoftFail; 796 break; 797 case ARM::tB: 798 case ARM::t2B: 799 case ARM::t2TBB: 800 case ARM::t2TBH: 801 // Some instructions (mostly unconditional branches) can 802 // only appears at the end of, or outside of, an IT. 803 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 804 S = SoftFail; 805 break; 806 default: 807 break; 808 } 809 810 // Warn on non-VPT predicable instruction in a VPT block and a VPT 811 // predicable instruction in an IT block 812 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 813 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 814 S = SoftFail; 815 816 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 817 // assume a predicate of AL. 818 unsigned CC = ARMCC::AL; 819 unsigned VCC = ARMVCC::None; 820 if (ITBlock.instrInITBlock()) { 821 CC = ITBlock.getITCC(); 822 ITBlock.advanceITState(); 823 } else if (VPTBlock.instrInVPTBlock()) { 824 VCC = VPTBlock.getVPTPred(); 825 VPTBlock.advanceVPTState(); 826 } 827 828 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 829 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 830 831 MCInst::iterator CCI = MI.begin(); 832 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 833 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 834 } 835 836 if (ARMInsts[MI.getOpcode()].isPredicable()) { 837 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 838 ++CCI; 839 if (CC == ARMCC::AL) 840 MI.insert(CCI, MCOperand::createReg(0)); 841 else 842 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 843 } else if (CC != ARMCC::AL) { 844 Check(S, SoftFail); 845 } 846 847 MCInst::iterator VCCI = MI.begin(); 848 unsigned VCCPos; 849 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 850 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 851 } 852 853 if (isVectorPredicable(MI.getOpcode())) { 854 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 855 ++VCCI; 856 if (VCC == ARMVCC::None) 857 MI.insert(VCCI, MCOperand::createReg(0)); 858 else 859 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 860 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 861 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 862 VCCPos + 2, MCOI::TIED_TO); 863 assert(TiedOp >= 0 && 864 "Inactive register in vpred_r is not tied to an output!"); 865 // Copy the operand to ensure it's not invalidated when MI grows. 866 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 867 } 868 } else if (VCC != ARMVCC::None) { 869 Check(S, SoftFail); 870 } 871 872 return S; 873 } 874 875 // Thumb VFP instructions are a special case. Because we share their 876 // encodings between ARM and Thumb modes, and they are predicable in ARM 877 // mode, the auto-generated decoder will give them an (incorrect) 878 // predicate operand. We need to rewrite these operands based on the IT 879 // context as a post-pass. 880 void ARMDisassembler::UpdateThumbVFPPredicate( 881 DecodeStatus &S, MCInst &MI) const { 882 unsigned CC; 883 CC = ITBlock.getITCC(); 884 if (CC == 0xF) 885 CC = ARMCC::AL; 886 if (ITBlock.instrInITBlock()) 887 ITBlock.advanceITState(); 888 else if (VPTBlock.instrInVPTBlock()) { 889 CC = VPTBlock.getVPTPred(); 890 VPTBlock.advanceVPTState(); 891 } 892 893 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 894 MCInst::iterator I = MI.begin(); 895 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 896 for (unsigned i = 0; i < NumOps; ++i, ++I) { 897 if (OpInfo[i].isPredicate() ) { 898 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 899 Check(S, SoftFail); 900 I->setImm(CC); 901 ++I; 902 if (CC == ARMCC::AL) 903 I->setReg(0); 904 else 905 I->setReg(ARM::CPSR); 906 return; 907 } 908 } 909 } 910 911 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 912 ArrayRef<uint8_t> Bytes, 913 uint64_t Address, 914 raw_ostream &CS) const { 915 CommentStream = &CS; 916 917 assert(STI.getFeatureBits()[ARM::ModeThumb] && 918 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 919 920 // We want to read exactly 2 bytes of data. 921 if (Bytes.size() < 2) { 922 Size = 0; 923 return MCDisassembler::Fail; 924 } 925 926 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 927 DecodeStatus Result = 928 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 929 if (Result != MCDisassembler::Fail) { 930 Size = 2; 931 Check(Result, AddThumbPredicate(MI)); 932 return Result; 933 } 934 935 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 936 STI); 937 if (Result) { 938 Size = 2; 939 bool InITBlock = ITBlock.instrInITBlock(); 940 Check(Result, AddThumbPredicate(MI)); 941 AddThumb1SBit(MI, InITBlock); 942 return Result; 943 } 944 945 Result = 946 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 947 if (Result != MCDisassembler::Fail) { 948 Size = 2; 949 950 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 951 // the Thumb predicate. 952 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 953 Result = MCDisassembler::SoftFail; 954 955 Check(Result, AddThumbPredicate(MI)); 956 957 // If we find an IT instruction, we need to parse its condition 958 // code and mask operands so that we can apply them correctly 959 // to the subsequent instructions. 960 if (MI.getOpcode() == ARM::t2IT) { 961 unsigned Firstcond = MI.getOperand(0).getImm(); 962 unsigned Mask = MI.getOperand(1).getImm(); 963 ITBlock.setITState(Firstcond, Mask); 964 965 // An IT instruction that would give a 'NV' predicate is unpredictable. 966 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 967 CS << "unpredictable IT predicate sequence"; 968 } 969 970 return Result; 971 } 972 973 // We want to read exactly 4 bytes of data. 974 if (Bytes.size() < 4) { 975 Size = 0; 976 return MCDisassembler::Fail; 977 } 978 979 uint32_t Insn32 = 980 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 981 982 Result = 983 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 984 if (Result != MCDisassembler::Fail) { 985 Size = 4; 986 987 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 988 // the VPT predicate. 989 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 990 Result = MCDisassembler::SoftFail; 991 992 Check(Result, AddThumbPredicate(MI)); 993 994 if (isVPTOpcode(MI.getOpcode())) { 995 unsigned Mask = MI.getOperand(0).getImm(); 996 VPTBlock.setVPTState(Mask); 997 } 998 999 return Result; 1000 } 1001 1002 Result = 1003 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1004 if (Result != MCDisassembler::Fail) { 1005 Size = 4; 1006 bool InITBlock = ITBlock.instrInITBlock(); 1007 Check(Result, AddThumbPredicate(MI)); 1008 AddThumb1SBit(MI, InITBlock); 1009 return Result; 1010 } 1011 1012 Result = 1013 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1014 if (Result != MCDisassembler::Fail) { 1015 Size = 4; 1016 Check(Result, AddThumbPredicate(MI)); 1017 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1018 } 1019 1020 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1021 Result = 1022 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1023 if (Result != MCDisassembler::Fail) { 1024 Size = 4; 1025 UpdateThumbVFPPredicate(Result, MI); 1026 return Result; 1027 } 1028 } 1029 1030 Result = 1031 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1032 if (Result != MCDisassembler::Fail) { 1033 Size = 4; 1034 return Result; 1035 } 1036 1037 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1038 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1039 STI); 1040 if (Result != MCDisassembler::Fail) { 1041 Size = 4; 1042 Check(Result, AddThumbPredicate(MI)); 1043 return Result; 1044 } 1045 } 1046 1047 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1048 uint32_t NEONLdStInsn = Insn32; 1049 NEONLdStInsn &= 0xF0FFFFFF; 1050 NEONLdStInsn |= 0x04000000; 1051 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1052 Address, this, STI); 1053 if (Result != MCDisassembler::Fail) { 1054 Size = 4; 1055 Check(Result, AddThumbPredicate(MI)); 1056 return Result; 1057 } 1058 } 1059 1060 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1061 uint32_t NEONDataInsn = Insn32; 1062 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1063 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1064 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1065 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1066 Address, this, STI); 1067 if (Result != MCDisassembler::Fail) { 1068 Size = 4; 1069 Check(Result, AddThumbPredicate(MI)); 1070 return Result; 1071 } 1072 1073 uint32_t NEONCryptoInsn = Insn32; 1074 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1075 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1076 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1077 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1078 Address, this, STI); 1079 if (Result != MCDisassembler::Fail) { 1080 Size = 4; 1081 return Result; 1082 } 1083 1084 uint32_t NEONv8Insn = Insn32; 1085 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1086 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1087 this, STI); 1088 if (Result != MCDisassembler::Fail) { 1089 Size = 4; 1090 return Result; 1091 } 1092 } 1093 1094 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1095 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1096 ? DecoderTableThumb2CDE32 1097 : DecoderTableThumb2CoProc32; 1098 Result = 1099 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1100 if (Result != MCDisassembler::Fail) { 1101 Size = 4; 1102 Check(Result, AddThumbPredicate(MI)); 1103 return Result; 1104 } 1105 1106 Size = 0; 1107 return MCDisassembler::Fail; 1108 } 1109 1110 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1111 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1112 createARMDisassembler); 1113 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1114 createARMDisassembler); 1115 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1116 createARMDisassembler); 1117 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1118 createARMDisassembler); 1119 } 1120 1121 static const uint16_t GPRDecoderTable[] = { 1122 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1123 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1124 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1125 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1126 }; 1127 1128 static const uint16_t CLRMGPRDecoderTable[] = { 1129 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1130 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1131 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1132 ARM::R12, 0, ARM::LR, ARM::APSR 1133 }; 1134 1135 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1136 uint64_t Address, const void *Decoder) { 1137 if (RegNo > 15) 1138 return MCDisassembler::Fail; 1139 1140 unsigned Register = GPRDecoderTable[RegNo]; 1141 Inst.addOperand(MCOperand::createReg(Register)); 1142 return MCDisassembler::Success; 1143 } 1144 1145 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1146 uint64_t Address, 1147 const void *Decoder) { 1148 if (RegNo > 15) 1149 return MCDisassembler::Fail; 1150 1151 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1152 if (Register == 0) 1153 return MCDisassembler::Fail; 1154 1155 Inst.addOperand(MCOperand::createReg(Register)); 1156 return MCDisassembler::Success; 1157 } 1158 1159 static DecodeStatus 1160 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1161 uint64_t Address, const void *Decoder) { 1162 DecodeStatus S = MCDisassembler::Success; 1163 1164 if (RegNo == 15) 1165 S = MCDisassembler::SoftFail; 1166 1167 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1168 1169 return S; 1170 } 1171 1172 static DecodeStatus 1173 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1174 uint64_t Address, const void *Decoder) { 1175 DecodeStatus S = MCDisassembler::Success; 1176 1177 if (RegNo == 15) 1178 { 1179 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1180 return MCDisassembler::Success; 1181 } 1182 1183 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1184 return S; 1185 } 1186 1187 static DecodeStatus 1188 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1189 uint64_t Address, const void *Decoder) { 1190 DecodeStatus S = MCDisassembler::Success; 1191 1192 if (RegNo == 15) 1193 { 1194 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1195 return MCDisassembler::Success; 1196 } 1197 1198 if (RegNo == 13) 1199 Check(S, MCDisassembler::SoftFail); 1200 1201 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1202 return S; 1203 } 1204 1205 static DecodeStatus 1206 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1207 uint64_t Address, const void *Decoder) { 1208 DecodeStatus S = MCDisassembler::Success; 1209 if (RegNo == 13) 1210 return MCDisassembler::Fail; 1211 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1212 return S; 1213 } 1214 1215 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1216 uint64_t Address, const void *Decoder) { 1217 if (RegNo > 7) 1218 return MCDisassembler::Fail; 1219 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1220 } 1221 1222 static const uint16_t GPRPairDecoderTable[] = { 1223 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1224 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1225 }; 1226 1227 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1228 uint64_t Address, const void *Decoder) { 1229 DecodeStatus S = MCDisassembler::Success; 1230 1231 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1232 // rather than SoftFail as there is no GPRPair table entry for index 7. 1233 if (RegNo > 13) 1234 return MCDisassembler::Fail; 1235 1236 if (RegNo & 1) 1237 S = MCDisassembler::SoftFail; 1238 1239 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1240 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1241 return S; 1242 } 1243 1244 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 1245 uint64_t Address, const void *Decoder) { 1246 if (RegNo > 13) 1247 return MCDisassembler::Fail; 1248 1249 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1250 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1251 1252 if ((RegNo & 1) || RegNo > 10) 1253 return MCDisassembler::SoftFail; 1254 return MCDisassembler::Success; 1255 } 1256 1257 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1258 uint64_t Address, 1259 const void *Decoder) { 1260 if (RegNo != 13) 1261 return MCDisassembler::Fail; 1262 1263 unsigned Register = GPRDecoderTable[RegNo]; 1264 Inst.addOperand(MCOperand::createReg(Register)); 1265 return MCDisassembler::Success; 1266 } 1267 1268 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1269 uint64_t Address, const void *Decoder) { 1270 unsigned Register = 0; 1271 switch (RegNo) { 1272 case 0: 1273 Register = ARM::R0; 1274 break; 1275 case 1: 1276 Register = ARM::R1; 1277 break; 1278 case 2: 1279 Register = ARM::R2; 1280 break; 1281 case 3: 1282 Register = ARM::R3; 1283 break; 1284 case 9: 1285 Register = ARM::R9; 1286 break; 1287 case 12: 1288 Register = ARM::R12; 1289 break; 1290 default: 1291 return MCDisassembler::Fail; 1292 } 1293 1294 Inst.addOperand(MCOperand::createReg(Register)); 1295 return MCDisassembler::Success; 1296 } 1297 1298 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1299 uint64_t Address, const void *Decoder) { 1300 DecodeStatus S = MCDisassembler::Success; 1301 1302 const FeatureBitset &featureBits = 1303 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1304 1305 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1306 S = MCDisassembler::SoftFail; 1307 1308 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1309 return S; 1310 } 1311 1312 static const uint16_t SPRDecoderTable[] = { 1313 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1314 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1315 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1316 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1317 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1318 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1319 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1320 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1321 }; 1322 1323 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1324 uint64_t Address, const void *Decoder) { 1325 if (RegNo > 31) 1326 return MCDisassembler::Fail; 1327 1328 unsigned Register = SPRDecoderTable[RegNo]; 1329 Inst.addOperand(MCOperand::createReg(Register)); 1330 return MCDisassembler::Success; 1331 } 1332 1333 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1334 uint64_t Address, const void *Decoder) { 1335 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1336 } 1337 1338 static const uint16_t DPRDecoderTable[] = { 1339 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1340 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1341 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1342 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1343 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1344 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1345 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1346 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1347 }; 1348 1349 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1350 uint64_t Address, const void *Decoder) { 1351 const FeatureBitset &featureBits = 1352 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1353 1354 bool hasD32 = featureBits[ARM::FeatureD32]; 1355 1356 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1357 return MCDisassembler::Fail; 1358 1359 unsigned Register = DPRDecoderTable[RegNo]; 1360 Inst.addOperand(MCOperand::createReg(Register)); 1361 return MCDisassembler::Success; 1362 } 1363 1364 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1365 uint64_t Address, const void *Decoder) { 1366 if (RegNo > 7) 1367 return MCDisassembler::Fail; 1368 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1369 } 1370 1371 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1372 uint64_t Address, const void *Decoder) { 1373 if (RegNo > 15) 1374 return MCDisassembler::Fail; 1375 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1376 } 1377 1378 static DecodeStatus 1379 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1380 uint64_t Address, const void *Decoder) { 1381 if (RegNo > 15) 1382 return MCDisassembler::Fail; 1383 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1384 } 1385 1386 static const uint16_t QPRDecoderTable[] = { 1387 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1388 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1389 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1390 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1391 }; 1392 1393 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1394 uint64_t Address, const void *Decoder) { 1395 if (RegNo > 31 || (RegNo & 1) != 0) 1396 return MCDisassembler::Fail; 1397 RegNo >>= 1; 1398 1399 unsigned Register = QPRDecoderTable[RegNo]; 1400 Inst.addOperand(MCOperand::createReg(Register)); 1401 return MCDisassembler::Success; 1402 } 1403 1404 static const uint16_t DPairDecoderTable[] = { 1405 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1406 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1407 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1408 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1409 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1410 ARM::Q15 1411 }; 1412 1413 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1414 uint64_t Address, const void *Decoder) { 1415 if (RegNo > 30) 1416 return MCDisassembler::Fail; 1417 1418 unsigned Register = DPairDecoderTable[RegNo]; 1419 Inst.addOperand(MCOperand::createReg(Register)); 1420 return MCDisassembler::Success; 1421 } 1422 1423 static const uint16_t DPairSpacedDecoderTable[] = { 1424 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1425 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1426 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1427 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1428 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1429 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1430 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1431 ARM::D28_D30, ARM::D29_D31 1432 }; 1433 1434 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1435 unsigned RegNo, 1436 uint64_t Address, 1437 const void *Decoder) { 1438 if (RegNo > 29) 1439 return MCDisassembler::Fail; 1440 1441 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1442 Inst.addOperand(MCOperand::createReg(Register)); 1443 return MCDisassembler::Success; 1444 } 1445 1446 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1447 uint64_t Address, const void *Decoder) { 1448 DecodeStatus S = MCDisassembler::Success; 1449 if (Val == 0xF) return MCDisassembler::Fail; 1450 // AL predicate is not allowed on Thumb1 branches. 1451 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1452 return MCDisassembler::Fail; 1453 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1454 Check(S, MCDisassembler::SoftFail); 1455 Inst.addOperand(MCOperand::createImm(Val)); 1456 if (Val == ARMCC::AL) { 1457 Inst.addOperand(MCOperand::createReg(0)); 1458 } else 1459 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1460 return S; 1461 } 1462 1463 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1464 uint64_t Address, const void *Decoder) { 1465 if (Val) 1466 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1467 else 1468 Inst.addOperand(MCOperand::createReg(0)); 1469 return MCDisassembler::Success; 1470 } 1471 1472 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1473 uint64_t Address, const void *Decoder) { 1474 DecodeStatus S = MCDisassembler::Success; 1475 1476 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1477 unsigned type = fieldFromInstruction(Val, 5, 2); 1478 unsigned imm = fieldFromInstruction(Val, 7, 5); 1479 1480 // Register-immediate 1481 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1482 return MCDisassembler::Fail; 1483 1484 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1485 switch (type) { 1486 case 0: 1487 Shift = ARM_AM::lsl; 1488 break; 1489 case 1: 1490 Shift = ARM_AM::lsr; 1491 break; 1492 case 2: 1493 Shift = ARM_AM::asr; 1494 break; 1495 case 3: 1496 Shift = ARM_AM::ror; 1497 break; 1498 } 1499 1500 if (Shift == ARM_AM::ror && imm == 0) 1501 Shift = ARM_AM::rrx; 1502 1503 unsigned Op = Shift | (imm << 3); 1504 Inst.addOperand(MCOperand::createImm(Op)); 1505 1506 return S; 1507 } 1508 1509 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1510 uint64_t Address, const void *Decoder) { 1511 DecodeStatus S = MCDisassembler::Success; 1512 1513 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1514 unsigned type = fieldFromInstruction(Val, 5, 2); 1515 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1516 1517 // Register-register 1518 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1519 return MCDisassembler::Fail; 1520 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1521 return MCDisassembler::Fail; 1522 1523 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1524 switch (type) { 1525 case 0: 1526 Shift = ARM_AM::lsl; 1527 break; 1528 case 1: 1529 Shift = ARM_AM::lsr; 1530 break; 1531 case 2: 1532 Shift = ARM_AM::asr; 1533 break; 1534 case 3: 1535 Shift = ARM_AM::ror; 1536 break; 1537 } 1538 1539 Inst.addOperand(MCOperand::createImm(Shift)); 1540 1541 return S; 1542 } 1543 1544 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1545 uint64_t Address, const void *Decoder) { 1546 DecodeStatus S = MCDisassembler::Success; 1547 1548 bool NeedDisjointWriteback = false; 1549 unsigned WritebackReg = 0; 1550 bool CLRM = false; 1551 switch (Inst.getOpcode()) { 1552 default: 1553 break; 1554 case ARM::LDMIA_UPD: 1555 case ARM::LDMDB_UPD: 1556 case ARM::LDMIB_UPD: 1557 case ARM::LDMDA_UPD: 1558 case ARM::t2LDMIA_UPD: 1559 case ARM::t2LDMDB_UPD: 1560 case ARM::t2STMIA_UPD: 1561 case ARM::t2STMDB_UPD: 1562 NeedDisjointWriteback = true; 1563 WritebackReg = Inst.getOperand(0).getReg(); 1564 break; 1565 case ARM::t2CLRM: 1566 CLRM = true; 1567 break; 1568 } 1569 1570 // Empty register lists are not allowed. 1571 if (Val == 0) return MCDisassembler::Fail; 1572 for (unsigned i = 0; i < 16; ++i) { 1573 if (Val & (1 << i)) { 1574 if (CLRM) { 1575 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1576 return MCDisassembler::Fail; 1577 } 1578 } else { 1579 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1580 return MCDisassembler::Fail; 1581 // Writeback not allowed if Rn is in the target list. 1582 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1583 Check(S, MCDisassembler::SoftFail); 1584 } 1585 } 1586 } 1587 1588 return S; 1589 } 1590 1591 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1592 uint64_t Address, const void *Decoder) { 1593 DecodeStatus S = MCDisassembler::Success; 1594 1595 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1596 unsigned regs = fieldFromInstruction(Val, 0, 8); 1597 1598 // In case of unpredictable encoding, tweak the operands. 1599 if (regs == 0 || (Vd + regs) > 32) { 1600 regs = Vd + regs > 32 ? 32 - Vd : regs; 1601 regs = std::max( 1u, regs); 1602 S = MCDisassembler::SoftFail; 1603 } 1604 1605 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1606 return MCDisassembler::Fail; 1607 for (unsigned i = 0; i < (regs - 1); ++i) { 1608 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1609 return MCDisassembler::Fail; 1610 } 1611 1612 return S; 1613 } 1614 1615 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1616 uint64_t Address, const void *Decoder) { 1617 DecodeStatus S = MCDisassembler::Success; 1618 1619 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1620 unsigned regs = fieldFromInstruction(Val, 1, 7); 1621 1622 // In case of unpredictable encoding, tweak the operands. 1623 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1624 regs = Vd + regs > 32 ? 32 - Vd : regs; 1625 regs = std::max( 1u, regs); 1626 regs = std::min(16u, regs); 1627 S = MCDisassembler::SoftFail; 1628 } 1629 1630 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1631 return MCDisassembler::Fail; 1632 for (unsigned i = 0; i < (regs - 1); ++i) { 1633 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1634 return MCDisassembler::Fail; 1635 } 1636 1637 return S; 1638 } 1639 1640 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1641 uint64_t Address, const void *Decoder) { 1642 // This operand encodes a mask of contiguous zeros between a specified MSB 1643 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1644 // the mask of all bits LSB-and-lower, and then xor them to create 1645 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1646 // create the final mask. 1647 unsigned msb = fieldFromInstruction(Val, 5, 5); 1648 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1649 1650 DecodeStatus S = MCDisassembler::Success; 1651 if (lsb > msb) { 1652 Check(S, MCDisassembler::SoftFail); 1653 // The check above will cause the warning for the "potentially undefined 1654 // instruction encoding" but we can't build a bad MCOperand value here 1655 // with a lsb > msb or else printing the MCInst will cause a crash. 1656 lsb = msb; 1657 } 1658 1659 uint32_t msb_mask = 0xFFFFFFFF; 1660 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1661 uint32_t lsb_mask = (1U << lsb) - 1; 1662 1663 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1664 return S; 1665 } 1666 1667 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1668 uint64_t Address, const void *Decoder) { 1669 DecodeStatus S = MCDisassembler::Success; 1670 1671 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1672 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1673 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1674 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1675 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1676 unsigned U = fieldFromInstruction(Insn, 23, 1); 1677 const FeatureBitset &featureBits = 1678 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1679 1680 switch (Inst.getOpcode()) { 1681 case ARM::LDC_OFFSET: 1682 case ARM::LDC_PRE: 1683 case ARM::LDC_POST: 1684 case ARM::LDC_OPTION: 1685 case ARM::LDCL_OFFSET: 1686 case ARM::LDCL_PRE: 1687 case ARM::LDCL_POST: 1688 case ARM::LDCL_OPTION: 1689 case ARM::STC_OFFSET: 1690 case ARM::STC_PRE: 1691 case ARM::STC_POST: 1692 case ARM::STC_OPTION: 1693 case ARM::STCL_OFFSET: 1694 case ARM::STCL_PRE: 1695 case ARM::STCL_POST: 1696 case ARM::STCL_OPTION: 1697 case ARM::t2LDC_OFFSET: 1698 case ARM::t2LDC_PRE: 1699 case ARM::t2LDC_POST: 1700 case ARM::t2LDC_OPTION: 1701 case ARM::t2LDCL_OFFSET: 1702 case ARM::t2LDCL_PRE: 1703 case ARM::t2LDCL_POST: 1704 case ARM::t2LDCL_OPTION: 1705 case ARM::t2STC_OFFSET: 1706 case ARM::t2STC_PRE: 1707 case ARM::t2STC_POST: 1708 case ARM::t2STC_OPTION: 1709 case ARM::t2STCL_OFFSET: 1710 case ARM::t2STCL_PRE: 1711 case ARM::t2STCL_POST: 1712 case ARM::t2STCL_OPTION: 1713 case ARM::t2LDC2_OFFSET: 1714 case ARM::t2LDC2L_OFFSET: 1715 case ARM::t2LDC2_PRE: 1716 case ARM::t2LDC2L_PRE: 1717 case ARM::t2STC2_OFFSET: 1718 case ARM::t2STC2L_OFFSET: 1719 case ARM::t2STC2_PRE: 1720 case ARM::t2STC2L_PRE: 1721 case ARM::LDC2_OFFSET: 1722 case ARM::LDC2L_OFFSET: 1723 case ARM::LDC2_PRE: 1724 case ARM::LDC2L_PRE: 1725 case ARM::STC2_OFFSET: 1726 case ARM::STC2L_OFFSET: 1727 case ARM::STC2_PRE: 1728 case ARM::STC2L_PRE: 1729 case ARM::t2LDC2_OPTION: 1730 case ARM::t2STC2_OPTION: 1731 case ARM::t2LDC2_POST: 1732 case ARM::t2LDC2L_POST: 1733 case ARM::t2STC2_POST: 1734 case ARM::t2STC2L_POST: 1735 case ARM::LDC2_POST: 1736 case ARM::LDC2L_POST: 1737 case ARM::STC2_POST: 1738 case ARM::STC2L_POST: 1739 if (coproc == 0xA || coproc == 0xB || 1740 (featureBits[ARM::HasV8_1MMainlineOps] && 1741 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1742 coproc == 0xE || coproc == 0xF))) 1743 return MCDisassembler::Fail; 1744 break; 1745 default: 1746 break; 1747 } 1748 1749 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1750 return MCDisassembler::Fail; 1751 1752 Inst.addOperand(MCOperand::createImm(coproc)); 1753 Inst.addOperand(MCOperand::createImm(CRd)); 1754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1755 return MCDisassembler::Fail; 1756 1757 switch (Inst.getOpcode()) { 1758 case ARM::t2LDC2_OFFSET: 1759 case ARM::t2LDC2L_OFFSET: 1760 case ARM::t2LDC2_PRE: 1761 case ARM::t2LDC2L_PRE: 1762 case ARM::t2STC2_OFFSET: 1763 case ARM::t2STC2L_OFFSET: 1764 case ARM::t2STC2_PRE: 1765 case ARM::t2STC2L_PRE: 1766 case ARM::LDC2_OFFSET: 1767 case ARM::LDC2L_OFFSET: 1768 case ARM::LDC2_PRE: 1769 case ARM::LDC2L_PRE: 1770 case ARM::STC2_OFFSET: 1771 case ARM::STC2L_OFFSET: 1772 case ARM::STC2_PRE: 1773 case ARM::STC2L_PRE: 1774 case ARM::t2LDC_OFFSET: 1775 case ARM::t2LDCL_OFFSET: 1776 case ARM::t2LDC_PRE: 1777 case ARM::t2LDCL_PRE: 1778 case ARM::t2STC_OFFSET: 1779 case ARM::t2STCL_OFFSET: 1780 case ARM::t2STC_PRE: 1781 case ARM::t2STCL_PRE: 1782 case ARM::LDC_OFFSET: 1783 case ARM::LDCL_OFFSET: 1784 case ARM::LDC_PRE: 1785 case ARM::LDCL_PRE: 1786 case ARM::STC_OFFSET: 1787 case ARM::STCL_OFFSET: 1788 case ARM::STC_PRE: 1789 case ARM::STCL_PRE: 1790 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1791 Inst.addOperand(MCOperand::createImm(imm)); 1792 break; 1793 case ARM::t2LDC2_POST: 1794 case ARM::t2LDC2L_POST: 1795 case ARM::t2STC2_POST: 1796 case ARM::t2STC2L_POST: 1797 case ARM::LDC2_POST: 1798 case ARM::LDC2L_POST: 1799 case ARM::STC2_POST: 1800 case ARM::STC2L_POST: 1801 case ARM::t2LDC_POST: 1802 case ARM::t2LDCL_POST: 1803 case ARM::t2STC_POST: 1804 case ARM::t2STCL_POST: 1805 case ARM::LDC_POST: 1806 case ARM::LDCL_POST: 1807 case ARM::STC_POST: 1808 case ARM::STCL_POST: 1809 imm |= U << 8; 1810 LLVM_FALLTHROUGH; 1811 default: 1812 // The 'option' variant doesn't encode 'U' in the immediate since 1813 // the immediate is unsigned [0,255]. 1814 Inst.addOperand(MCOperand::createImm(imm)); 1815 break; 1816 } 1817 1818 switch (Inst.getOpcode()) { 1819 case ARM::LDC_OFFSET: 1820 case ARM::LDC_PRE: 1821 case ARM::LDC_POST: 1822 case ARM::LDC_OPTION: 1823 case ARM::LDCL_OFFSET: 1824 case ARM::LDCL_PRE: 1825 case ARM::LDCL_POST: 1826 case ARM::LDCL_OPTION: 1827 case ARM::STC_OFFSET: 1828 case ARM::STC_PRE: 1829 case ARM::STC_POST: 1830 case ARM::STC_OPTION: 1831 case ARM::STCL_OFFSET: 1832 case ARM::STCL_PRE: 1833 case ARM::STCL_POST: 1834 case ARM::STCL_OPTION: 1835 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1836 return MCDisassembler::Fail; 1837 break; 1838 default: 1839 break; 1840 } 1841 1842 return S; 1843 } 1844 1845 static DecodeStatus 1846 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1847 uint64_t Address, const void *Decoder) { 1848 DecodeStatus S = MCDisassembler::Success; 1849 1850 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1851 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1852 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1853 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1854 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1855 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1856 unsigned P = fieldFromInstruction(Insn, 24, 1); 1857 unsigned W = fieldFromInstruction(Insn, 21, 1); 1858 1859 // On stores, the writeback operand precedes Rt. 1860 switch (Inst.getOpcode()) { 1861 case ARM::STR_POST_IMM: 1862 case ARM::STR_POST_REG: 1863 case ARM::STRB_POST_IMM: 1864 case ARM::STRB_POST_REG: 1865 case ARM::STRT_POST_REG: 1866 case ARM::STRT_POST_IMM: 1867 case ARM::STRBT_POST_REG: 1868 case ARM::STRBT_POST_IMM: 1869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1870 return MCDisassembler::Fail; 1871 break; 1872 default: 1873 break; 1874 } 1875 1876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1877 return MCDisassembler::Fail; 1878 1879 // On loads, the writeback operand comes after Rt. 1880 switch (Inst.getOpcode()) { 1881 case ARM::LDR_POST_IMM: 1882 case ARM::LDR_POST_REG: 1883 case ARM::LDRB_POST_IMM: 1884 case ARM::LDRB_POST_REG: 1885 case ARM::LDRBT_POST_REG: 1886 case ARM::LDRBT_POST_IMM: 1887 case ARM::LDRT_POST_REG: 1888 case ARM::LDRT_POST_IMM: 1889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1890 return MCDisassembler::Fail; 1891 break; 1892 default: 1893 break; 1894 } 1895 1896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1897 return MCDisassembler::Fail; 1898 1899 ARM_AM::AddrOpc Op = ARM_AM::add; 1900 if (!fieldFromInstruction(Insn, 23, 1)) 1901 Op = ARM_AM::sub; 1902 1903 bool writeback = (P == 0) || (W == 1); 1904 unsigned idx_mode = 0; 1905 if (P && writeback) 1906 idx_mode = ARMII::IndexModePre; 1907 else if (!P && writeback) 1908 idx_mode = ARMII::IndexModePost; 1909 1910 if (writeback && (Rn == 15 || Rn == Rt)) 1911 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1912 1913 if (reg) { 1914 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1915 return MCDisassembler::Fail; 1916 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1917 switch( fieldFromInstruction(Insn, 5, 2)) { 1918 case 0: 1919 Opc = ARM_AM::lsl; 1920 break; 1921 case 1: 1922 Opc = ARM_AM::lsr; 1923 break; 1924 case 2: 1925 Opc = ARM_AM::asr; 1926 break; 1927 case 3: 1928 Opc = ARM_AM::ror; 1929 break; 1930 default: 1931 return MCDisassembler::Fail; 1932 } 1933 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1934 if (Opc == ARM_AM::ror && amt == 0) 1935 Opc = ARM_AM::rrx; 1936 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1937 1938 Inst.addOperand(MCOperand::createImm(imm)); 1939 } else { 1940 Inst.addOperand(MCOperand::createReg(0)); 1941 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1942 Inst.addOperand(MCOperand::createImm(tmp)); 1943 } 1944 1945 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1946 return MCDisassembler::Fail; 1947 1948 return S; 1949 } 1950 1951 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1952 uint64_t Address, const void *Decoder) { 1953 DecodeStatus S = MCDisassembler::Success; 1954 1955 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1956 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1957 unsigned type = fieldFromInstruction(Val, 5, 2); 1958 unsigned imm = fieldFromInstruction(Val, 7, 5); 1959 unsigned U = fieldFromInstruction(Val, 12, 1); 1960 1961 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1962 switch (type) { 1963 case 0: 1964 ShOp = ARM_AM::lsl; 1965 break; 1966 case 1: 1967 ShOp = ARM_AM::lsr; 1968 break; 1969 case 2: 1970 ShOp = ARM_AM::asr; 1971 break; 1972 case 3: 1973 ShOp = ARM_AM::ror; 1974 break; 1975 } 1976 1977 if (ShOp == ARM_AM::ror && imm == 0) 1978 ShOp = ARM_AM::rrx; 1979 1980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1983 return MCDisassembler::Fail; 1984 unsigned shift; 1985 if (U) 1986 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1987 else 1988 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1989 Inst.addOperand(MCOperand::createImm(shift)); 1990 1991 return S; 1992 } 1993 1994 static DecodeStatus 1995 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1996 uint64_t Address, const void *Decoder) { 1997 DecodeStatus S = MCDisassembler::Success; 1998 1999 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2000 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2001 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2002 unsigned type = fieldFromInstruction(Insn, 22, 1); 2003 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2004 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2005 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2006 unsigned W = fieldFromInstruction(Insn, 21, 1); 2007 unsigned P = fieldFromInstruction(Insn, 24, 1); 2008 unsigned Rt2 = Rt + 1; 2009 2010 bool writeback = (W == 1) | (P == 0); 2011 2012 // For {LD,ST}RD, Rt must be even, else undefined. 2013 switch (Inst.getOpcode()) { 2014 case ARM::STRD: 2015 case ARM::STRD_PRE: 2016 case ARM::STRD_POST: 2017 case ARM::LDRD: 2018 case ARM::LDRD_PRE: 2019 case ARM::LDRD_POST: 2020 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2021 break; 2022 default: 2023 break; 2024 } 2025 switch (Inst.getOpcode()) { 2026 case ARM::STRD: 2027 case ARM::STRD_PRE: 2028 case ARM::STRD_POST: 2029 if (P == 0 && W == 1) 2030 S = MCDisassembler::SoftFail; 2031 2032 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2033 S = MCDisassembler::SoftFail; 2034 if (type && Rm == 15) 2035 S = MCDisassembler::SoftFail; 2036 if (Rt2 == 15) 2037 S = MCDisassembler::SoftFail; 2038 if (!type && fieldFromInstruction(Insn, 8, 4)) 2039 S = MCDisassembler::SoftFail; 2040 break; 2041 case ARM::STRH: 2042 case ARM::STRH_PRE: 2043 case ARM::STRH_POST: 2044 if (Rt == 15) 2045 S = MCDisassembler::SoftFail; 2046 if (writeback && (Rn == 15 || Rn == Rt)) 2047 S = MCDisassembler::SoftFail; 2048 if (!type && Rm == 15) 2049 S = MCDisassembler::SoftFail; 2050 break; 2051 case ARM::LDRD: 2052 case ARM::LDRD_PRE: 2053 case ARM::LDRD_POST: 2054 if (type && Rn == 15) { 2055 if (Rt2 == 15) 2056 S = MCDisassembler::SoftFail; 2057 break; 2058 } 2059 if (P == 0 && W == 1) 2060 S = MCDisassembler::SoftFail; 2061 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2062 S = MCDisassembler::SoftFail; 2063 if (!type && writeback && Rn == 15) 2064 S = MCDisassembler::SoftFail; 2065 if (writeback && (Rn == Rt || Rn == Rt2)) 2066 S = MCDisassembler::SoftFail; 2067 break; 2068 case ARM::LDRH: 2069 case ARM::LDRH_PRE: 2070 case ARM::LDRH_POST: 2071 if (type && Rn == 15) { 2072 if (Rt == 15) 2073 S = MCDisassembler::SoftFail; 2074 break; 2075 } 2076 if (Rt == 15) 2077 S = MCDisassembler::SoftFail; 2078 if (!type && Rm == 15) 2079 S = MCDisassembler::SoftFail; 2080 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2081 S = MCDisassembler::SoftFail; 2082 break; 2083 case ARM::LDRSH: 2084 case ARM::LDRSH_PRE: 2085 case ARM::LDRSH_POST: 2086 case ARM::LDRSB: 2087 case ARM::LDRSB_PRE: 2088 case ARM::LDRSB_POST: 2089 if (type && Rn == 15) { 2090 if (Rt == 15) 2091 S = MCDisassembler::SoftFail; 2092 break; 2093 } 2094 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2095 S = MCDisassembler::SoftFail; 2096 if (!type && (Rt == 15 || Rm == 15)) 2097 S = MCDisassembler::SoftFail; 2098 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2099 S = MCDisassembler::SoftFail; 2100 break; 2101 default: 2102 break; 2103 } 2104 2105 if (writeback) { // Writeback 2106 if (P) 2107 U |= ARMII::IndexModePre << 9; 2108 else 2109 U |= ARMII::IndexModePost << 9; 2110 2111 // On stores, the writeback operand precedes Rt. 2112 switch (Inst.getOpcode()) { 2113 case ARM::STRD: 2114 case ARM::STRD_PRE: 2115 case ARM::STRD_POST: 2116 case ARM::STRH: 2117 case ARM::STRH_PRE: 2118 case ARM::STRH_POST: 2119 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2120 return MCDisassembler::Fail; 2121 break; 2122 default: 2123 break; 2124 } 2125 } 2126 2127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2128 return MCDisassembler::Fail; 2129 switch (Inst.getOpcode()) { 2130 case ARM::STRD: 2131 case ARM::STRD_PRE: 2132 case ARM::STRD_POST: 2133 case ARM::LDRD: 2134 case ARM::LDRD_PRE: 2135 case ARM::LDRD_POST: 2136 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2137 return MCDisassembler::Fail; 2138 break; 2139 default: 2140 break; 2141 } 2142 2143 if (writeback) { 2144 // On loads, the writeback operand comes after Rt. 2145 switch (Inst.getOpcode()) { 2146 case ARM::LDRD: 2147 case ARM::LDRD_PRE: 2148 case ARM::LDRD_POST: 2149 case ARM::LDRH: 2150 case ARM::LDRH_PRE: 2151 case ARM::LDRH_POST: 2152 case ARM::LDRSH: 2153 case ARM::LDRSH_PRE: 2154 case ARM::LDRSH_POST: 2155 case ARM::LDRSB: 2156 case ARM::LDRSB_PRE: 2157 case ARM::LDRSB_POST: 2158 case ARM::LDRHTr: 2159 case ARM::LDRSBTr: 2160 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2161 return MCDisassembler::Fail; 2162 break; 2163 default: 2164 break; 2165 } 2166 } 2167 2168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2169 return MCDisassembler::Fail; 2170 2171 if (type) { 2172 Inst.addOperand(MCOperand::createReg(0)); 2173 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2174 } else { 2175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2176 return MCDisassembler::Fail; 2177 Inst.addOperand(MCOperand::createImm(U)); 2178 } 2179 2180 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2181 return MCDisassembler::Fail; 2182 2183 return S; 2184 } 2185 2186 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2187 uint64_t Address, const void *Decoder) { 2188 DecodeStatus S = MCDisassembler::Success; 2189 2190 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2191 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2192 2193 switch (mode) { 2194 case 0: 2195 mode = ARM_AM::da; 2196 break; 2197 case 1: 2198 mode = ARM_AM::ia; 2199 break; 2200 case 2: 2201 mode = ARM_AM::db; 2202 break; 2203 case 3: 2204 mode = ARM_AM::ib; 2205 break; 2206 } 2207 2208 Inst.addOperand(MCOperand::createImm(mode)); 2209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2210 return MCDisassembler::Fail; 2211 2212 return S; 2213 } 2214 2215 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2216 uint64_t Address, const void *Decoder) { 2217 DecodeStatus S = MCDisassembler::Success; 2218 2219 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2220 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2221 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2222 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2223 2224 if (pred == 0xF) 2225 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2226 2227 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2228 return MCDisassembler::Fail; 2229 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2230 return MCDisassembler::Fail; 2231 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2232 return MCDisassembler::Fail; 2233 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2234 return MCDisassembler::Fail; 2235 return S; 2236 } 2237 2238 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2239 unsigned Insn, 2240 uint64_t Address, const void *Decoder) { 2241 DecodeStatus S = MCDisassembler::Success; 2242 2243 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2244 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2245 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2246 2247 if (pred == 0xF) { 2248 // Ambiguous with RFE and SRS 2249 switch (Inst.getOpcode()) { 2250 case ARM::LDMDA: 2251 Inst.setOpcode(ARM::RFEDA); 2252 break; 2253 case ARM::LDMDA_UPD: 2254 Inst.setOpcode(ARM::RFEDA_UPD); 2255 break; 2256 case ARM::LDMDB: 2257 Inst.setOpcode(ARM::RFEDB); 2258 break; 2259 case ARM::LDMDB_UPD: 2260 Inst.setOpcode(ARM::RFEDB_UPD); 2261 break; 2262 case ARM::LDMIA: 2263 Inst.setOpcode(ARM::RFEIA); 2264 break; 2265 case ARM::LDMIA_UPD: 2266 Inst.setOpcode(ARM::RFEIA_UPD); 2267 break; 2268 case ARM::LDMIB: 2269 Inst.setOpcode(ARM::RFEIB); 2270 break; 2271 case ARM::LDMIB_UPD: 2272 Inst.setOpcode(ARM::RFEIB_UPD); 2273 break; 2274 case ARM::STMDA: 2275 Inst.setOpcode(ARM::SRSDA); 2276 break; 2277 case ARM::STMDA_UPD: 2278 Inst.setOpcode(ARM::SRSDA_UPD); 2279 break; 2280 case ARM::STMDB: 2281 Inst.setOpcode(ARM::SRSDB); 2282 break; 2283 case ARM::STMDB_UPD: 2284 Inst.setOpcode(ARM::SRSDB_UPD); 2285 break; 2286 case ARM::STMIA: 2287 Inst.setOpcode(ARM::SRSIA); 2288 break; 2289 case ARM::STMIA_UPD: 2290 Inst.setOpcode(ARM::SRSIA_UPD); 2291 break; 2292 case ARM::STMIB: 2293 Inst.setOpcode(ARM::SRSIB); 2294 break; 2295 case ARM::STMIB_UPD: 2296 Inst.setOpcode(ARM::SRSIB_UPD); 2297 break; 2298 default: 2299 return MCDisassembler::Fail; 2300 } 2301 2302 // For stores (which become SRS's, the only operand is the mode. 2303 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2304 // Check SRS encoding constraints 2305 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2306 fieldFromInstruction(Insn, 20, 1) == 0)) 2307 return MCDisassembler::Fail; 2308 2309 Inst.addOperand( 2310 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2311 return S; 2312 } 2313 2314 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2315 } 2316 2317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2318 return MCDisassembler::Fail; 2319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2320 return MCDisassembler::Fail; // Tied 2321 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2322 return MCDisassembler::Fail; 2323 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2324 return MCDisassembler::Fail; 2325 2326 return S; 2327 } 2328 2329 // Check for UNPREDICTABLE predicated ESB instruction 2330 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2331 uint64_t Address, const void *Decoder) { 2332 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2333 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2334 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2335 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2336 2337 DecodeStatus S = MCDisassembler::Success; 2338 2339 Inst.addOperand(MCOperand::createImm(imm8)); 2340 2341 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2342 return MCDisassembler::Fail; 2343 2344 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2345 // so all predicates should be allowed. 2346 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2347 S = MCDisassembler::SoftFail; 2348 2349 return S; 2350 } 2351 2352 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2353 uint64_t Address, const void *Decoder) { 2354 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2355 unsigned M = fieldFromInstruction(Insn, 17, 1); 2356 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2357 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2358 2359 DecodeStatus S = MCDisassembler::Success; 2360 2361 // This decoder is called from multiple location that do not check 2362 // the full encoding is valid before they do. 2363 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2364 fieldFromInstruction(Insn, 16, 1) != 0 || 2365 fieldFromInstruction(Insn, 20, 8) != 0x10) 2366 return MCDisassembler::Fail; 2367 2368 // imod == '01' --> UNPREDICTABLE 2369 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2370 // return failure here. The '01' imod value is unprintable, so there's 2371 // nothing useful we could do even if we returned UNPREDICTABLE. 2372 2373 if (imod == 1) return MCDisassembler::Fail; 2374 2375 if (imod && M) { 2376 Inst.setOpcode(ARM::CPS3p); 2377 Inst.addOperand(MCOperand::createImm(imod)); 2378 Inst.addOperand(MCOperand::createImm(iflags)); 2379 Inst.addOperand(MCOperand::createImm(mode)); 2380 } else if (imod && !M) { 2381 Inst.setOpcode(ARM::CPS2p); 2382 Inst.addOperand(MCOperand::createImm(imod)); 2383 Inst.addOperand(MCOperand::createImm(iflags)); 2384 if (mode) S = MCDisassembler::SoftFail; 2385 } else if (!imod && M) { 2386 Inst.setOpcode(ARM::CPS1p); 2387 Inst.addOperand(MCOperand::createImm(mode)); 2388 if (iflags) S = MCDisassembler::SoftFail; 2389 } else { 2390 // imod == '00' && M == '0' --> UNPREDICTABLE 2391 Inst.setOpcode(ARM::CPS1p); 2392 Inst.addOperand(MCOperand::createImm(mode)); 2393 S = MCDisassembler::SoftFail; 2394 } 2395 2396 return S; 2397 } 2398 2399 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2400 uint64_t Address, const void *Decoder) { 2401 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2402 unsigned M = fieldFromInstruction(Insn, 8, 1); 2403 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2404 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2405 2406 DecodeStatus S = MCDisassembler::Success; 2407 2408 // imod == '01' --> UNPREDICTABLE 2409 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2410 // return failure here. The '01' imod value is unprintable, so there's 2411 // nothing useful we could do even if we returned UNPREDICTABLE. 2412 2413 if (imod == 1) return MCDisassembler::Fail; 2414 2415 if (imod && M) { 2416 Inst.setOpcode(ARM::t2CPS3p); 2417 Inst.addOperand(MCOperand::createImm(imod)); 2418 Inst.addOperand(MCOperand::createImm(iflags)); 2419 Inst.addOperand(MCOperand::createImm(mode)); 2420 } else if (imod && !M) { 2421 Inst.setOpcode(ARM::t2CPS2p); 2422 Inst.addOperand(MCOperand::createImm(imod)); 2423 Inst.addOperand(MCOperand::createImm(iflags)); 2424 if (mode) S = MCDisassembler::SoftFail; 2425 } else if (!imod && M) { 2426 Inst.setOpcode(ARM::t2CPS1p); 2427 Inst.addOperand(MCOperand::createImm(mode)); 2428 if (iflags) S = MCDisassembler::SoftFail; 2429 } else { 2430 // imod == '00' && M == '0' --> this is a HINT instruction 2431 int imm = fieldFromInstruction(Insn, 0, 8); 2432 // HINT are defined only for immediate in [0..4] 2433 if(imm > 4) return MCDisassembler::Fail; 2434 Inst.setOpcode(ARM::t2HINT); 2435 Inst.addOperand(MCOperand::createImm(imm)); 2436 } 2437 2438 return S; 2439 } 2440 2441 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2442 uint64_t Address, const void *Decoder) { 2443 DecodeStatus S = MCDisassembler::Success; 2444 2445 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2446 unsigned imm = 0; 2447 2448 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2449 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2450 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2451 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2452 2453 if (Inst.getOpcode() == ARM::t2MOVTi16) 2454 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2455 return MCDisassembler::Fail; 2456 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2457 return MCDisassembler::Fail; 2458 2459 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2460 Inst.addOperand(MCOperand::createImm(imm)); 2461 2462 return S; 2463 } 2464 2465 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2466 uint64_t Address, const void *Decoder) { 2467 DecodeStatus S = MCDisassembler::Success; 2468 2469 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2470 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2471 unsigned imm = 0; 2472 2473 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2474 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2475 2476 if (Inst.getOpcode() == ARM::MOVTi16) 2477 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2478 return MCDisassembler::Fail; 2479 2480 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2481 return MCDisassembler::Fail; 2482 2483 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2484 Inst.addOperand(MCOperand::createImm(imm)); 2485 2486 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2487 return MCDisassembler::Fail; 2488 2489 return S; 2490 } 2491 2492 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2493 uint64_t Address, const void *Decoder) { 2494 DecodeStatus S = MCDisassembler::Success; 2495 2496 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2497 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2498 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2499 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2500 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2501 2502 if (pred == 0xF) 2503 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2504 2505 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2506 return MCDisassembler::Fail; 2507 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2508 return MCDisassembler::Fail; 2509 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2510 return MCDisassembler::Fail; 2511 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2512 return MCDisassembler::Fail; 2513 2514 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2515 return MCDisassembler::Fail; 2516 2517 return S; 2518 } 2519 2520 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2521 uint64_t Address, const void *Decoder) { 2522 DecodeStatus S = MCDisassembler::Success; 2523 2524 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2525 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2526 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2527 2528 if (Pred == 0xF) 2529 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2530 2531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2536 return MCDisassembler::Fail; 2537 2538 return S; 2539 } 2540 2541 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2542 uint64_t Address, const void *Decoder) { 2543 DecodeStatus S = MCDisassembler::Success; 2544 2545 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2546 2547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2548 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2549 2550 if (!FeatureBits[ARM::HasV8_1aOps] || 2551 !FeatureBits[ARM::HasV8Ops]) 2552 return MCDisassembler::Fail; 2553 2554 // Decoder can be called from DecodeTST, which does not check the full 2555 // encoding is valid. 2556 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2557 fieldFromInstruction(Insn, 4,4) != 0) 2558 return MCDisassembler::Fail; 2559 if (fieldFromInstruction(Insn, 10,10) != 0 || 2560 fieldFromInstruction(Insn, 0,4) != 0) 2561 S = MCDisassembler::SoftFail; 2562 2563 Inst.setOpcode(ARM::SETPAN); 2564 Inst.addOperand(MCOperand::createImm(Imm)); 2565 2566 return S; 2567 } 2568 2569 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2570 uint64_t Address, const void *Decoder) { 2571 DecodeStatus S = MCDisassembler::Success; 2572 2573 unsigned add = fieldFromInstruction(Val, 12, 1); 2574 unsigned imm = fieldFromInstruction(Val, 0, 12); 2575 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2576 2577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2578 return MCDisassembler::Fail; 2579 2580 if (!add) imm *= -1; 2581 if (imm == 0 && !add) imm = INT32_MIN; 2582 Inst.addOperand(MCOperand::createImm(imm)); 2583 if (Rn == 15) 2584 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2585 2586 return S; 2587 } 2588 2589 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2590 uint64_t Address, const void *Decoder) { 2591 DecodeStatus S = MCDisassembler::Success; 2592 2593 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2594 // U == 1 to add imm, 0 to subtract it. 2595 unsigned U = fieldFromInstruction(Val, 8, 1); 2596 unsigned imm = fieldFromInstruction(Val, 0, 8); 2597 2598 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2599 return MCDisassembler::Fail; 2600 2601 if (U) 2602 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2603 else 2604 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2605 2606 return S; 2607 } 2608 2609 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2610 uint64_t Address, const void *Decoder) { 2611 DecodeStatus S = MCDisassembler::Success; 2612 2613 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2614 // U == 1 to add imm, 0 to subtract it. 2615 unsigned U = fieldFromInstruction(Val, 8, 1); 2616 unsigned imm = fieldFromInstruction(Val, 0, 8); 2617 2618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2619 return MCDisassembler::Fail; 2620 2621 if (U) 2622 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2623 else 2624 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2625 2626 return S; 2627 } 2628 2629 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2630 uint64_t Address, const void *Decoder) { 2631 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2632 } 2633 2634 static DecodeStatus 2635 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2636 uint64_t Address, const void *Decoder) { 2637 DecodeStatus Status = MCDisassembler::Success; 2638 2639 // Note the J1 and J2 values are from the encoded instruction. So here 2640 // change them to I1 and I2 values via as documented: 2641 // I1 = NOT(J1 EOR S); 2642 // I2 = NOT(J2 EOR S); 2643 // and build the imm32 with one trailing zero as documented: 2644 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2645 unsigned S = fieldFromInstruction(Insn, 26, 1); 2646 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2647 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2648 unsigned I1 = !(J1 ^ S); 2649 unsigned I2 = !(J2 ^ S); 2650 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2651 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2652 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2653 int imm32 = SignExtend32<25>(tmp << 1); 2654 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2655 true, 4, Inst, Decoder)) 2656 Inst.addOperand(MCOperand::createImm(imm32)); 2657 2658 return Status; 2659 } 2660 2661 static DecodeStatus 2662 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2663 uint64_t Address, const void *Decoder) { 2664 DecodeStatus S = MCDisassembler::Success; 2665 2666 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2667 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2668 2669 if (pred == 0xF) { 2670 Inst.setOpcode(ARM::BLXi); 2671 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2672 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2673 true, 4, Inst, Decoder)) 2674 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2675 return S; 2676 } 2677 2678 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2679 true, 4, Inst, Decoder)) 2680 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2681 2682 // We already have BL_pred for BL w/ predicate, no need to add addition 2683 // predicate opreands for BL 2684 if (Inst.getOpcode() != ARM::BL) 2685 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2686 return MCDisassembler::Fail; 2687 2688 return S; 2689 } 2690 2691 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2692 uint64_t Address, const void *Decoder) { 2693 DecodeStatus S = MCDisassembler::Success; 2694 2695 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2696 unsigned align = fieldFromInstruction(Val, 4, 2); 2697 2698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2699 return MCDisassembler::Fail; 2700 if (!align) 2701 Inst.addOperand(MCOperand::createImm(0)); 2702 else 2703 Inst.addOperand(MCOperand::createImm(4 << align)); 2704 2705 return S; 2706 } 2707 2708 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2709 uint64_t Address, const void *Decoder) { 2710 DecodeStatus S = MCDisassembler::Success; 2711 2712 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2713 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2714 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2715 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2716 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2717 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2718 2719 // First output register 2720 switch (Inst.getOpcode()) { 2721 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2722 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2723 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2724 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2725 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2726 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2727 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2728 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2729 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2730 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2731 return MCDisassembler::Fail; 2732 break; 2733 case ARM::VLD2b16: 2734 case ARM::VLD2b32: 2735 case ARM::VLD2b8: 2736 case ARM::VLD2b16wb_fixed: 2737 case ARM::VLD2b16wb_register: 2738 case ARM::VLD2b32wb_fixed: 2739 case ARM::VLD2b32wb_register: 2740 case ARM::VLD2b8wb_fixed: 2741 case ARM::VLD2b8wb_register: 2742 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2743 return MCDisassembler::Fail; 2744 break; 2745 default: 2746 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2747 return MCDisassembler::Fail; 2748 } 2749 2750 // Second output register 2751 switch (Inst.getOpcode()) { 2752 case ARM::VLD3d8: 2753 case ARM::VLD3d16: 2754 case ARM::VLD3d32: 2755 case ARM::VLD3d8_UPD: 2756 case ARM::VLD3d16_UPD: 2757 case ARM::VLD3d32_UPD: 2758 case ARM::VLD4d8: 2759 case ARM::VLD4d16: 2760 case ARM::VLD4d32: 2761 case ARM::VLD4d8_UPD: 2762 case ARM::VLD4d16_UPD: 2763 case ARM::VLD4d32_UPD: 2764 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2765 return MCDisassembler::Fail; 2766 break; 2767 case ARM::VLD3q8: 2768 case ARM::VLD3q16: 2769 case ARM::VLD3q32: 2770 case ARM::VLD3q8_UPD: 2771 case ARM::VLD3q16_UPD: 2772 case ARM::VLD3q32_UPD: 2773 case ARM::VLD4q8: 2774 case ARM::VLD4q16: 2775 case ARM::VLD4q32: 2776 case ARM::VLD4q8_UPD: 2777 case ARM::VLD4q16_UPD: 2778 case ARM::VLD4q32_UPD: 2779 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2780 return MCDisassembler::Fail; 2781 break; 2782 default: 2783 break; 2784 } 2785 2786 // Third output register 2787 switch(Inst.getOpcode()) { 2788 case ARM::VLD3d8: 2789 case ARM::VLD3d16: 2790 case ARM::VLD3d32: 2791 case ARM::VLD3d8_UPD: 2792 case ARM::VLD3d16_UPD: 2793 case ARM::VLD3d32_UPD: 2794 case ARM::VLD4d8: 2795 case ARM::VLD4d16: 2796 case ARM::VLD4d32: 2797 case ARM::VLD4d8_UPD: 2798 case ARM::VLD4d16_UPD: 2799 case ARM::VLD4d32_UPD: 2800 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2801 return MCDisassembler::Fail; 2802 break; 2803 case ARM::VLD3q8: 2804 case ARM::VLD3q16: 2805 case ARM::VLD3q32: 2806 case ARM::VLD3q8_UPD: 2807 case ARM::VLD3q16_UPD: 2808 case ARM::VLD3q32_UPD: 2809 case ARM::VLD4q8: 2810 case ARM::VLD4q16: 2811 case ARM::VLD4q32: 2812 case ARM::VLD4q8_UPD: 2813 case ARM::VLD4q16_UPD: 2814 case ARM::VLD4q32_UPD: 2815 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2816 return MCDisassembler::Fail; 2817 break; 2818 default: 2819 break; 2820 } 2821 2822 // Fourth output register 2823 switch (Inst.getOpcode()) { 2824 case ARM::VLD4d8: 2825 case ARM::VLD4d16: 2826 case ARM::VLD4d32: 2827 case ARM::VLD4d8_UPD: 2828 case ARM::VLD4d16_UPD: 2829 case ARM::VLD4d32_UPD: 2830 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2831 return MCDisassembler::Fail; 2832 break; 2833 case ARM::VLD4q8: 2834 case ARM::VLD4q16: 2835 case ARM::VLD4q32: 2836 case ARM::VLD4q8_UPD: 2837 case ARM::VLD4q16_UPD: 2838 case ARM::VLD4q32_UPD: 2839 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2840 return MCDisassembler::Fail; 2841 break; 2842 default: 2843 break; 2844 } 2845 2846 // Writeback operand 2847 switch (Inst.getOpcode()) { 2848 case ARM::VLD1d8wb_fixed: 2849 case ARM::VLD1d16wb_fixed: 2850 case ARM::VLD1d32wb_fixed: 2851 case ARM::VLD1d64wb_fixed: 2852 case ARM::VLD1d8wb_register: 2853 case ARM::VLD1d16wb_register: 2854 case ARM::VLD1d32wb_register: 2855 case ARM::VLD1d64wb_register: 2856 case ARM::VLD1q8wb_fixed: 2857 case ARM::VLD1q16wb_fixed: 2858 case ARM::VLD1q32wb_fixed: 2859 case ARM::VLD1q64wb_fixed: 2860 case ARM::VLD1q8wb_register: 2861 case ARM::VLD1q16wb_register: 2862 case ARM::VLD1q32wb_register: 2863 case ARM::VLD1q64wb_register: 2864 case ARM::VLD1d8Twb_fixed: 2865 case ARM::VLD1d8Twb_register: 2866 case ARM::VLD1d16Twb_fixed: 2867 case ARM::VLD1d16Twb_register: 2868 case ARM::VLD1d32Twb_fixed: 2869 case ARM::VLD1d32Twb_register: 2870 case ARM::VLD1d64Twb_fixed: 2871 case ARM::VLD1d64Twb_register: 2872 case ARM::VLD1d8Qwb_fixed: 2873 case ARM::VLD1d8Qwb_register: 2874 case ARM::VLD1d16Qwb_fixed: 2875 case ARM::VLD1d16Qwb_register: 2876 case ARM::VLD1d32Qwb_fixed: 2877 case ARM::VLD1d32Qwb_register: 2878 case ARM::VLD1d64Qwb_fixed: 2879 case ARM::VLD1d64Qwb_register: 2880 case ARM::VLD2d8wb_fixed: 2881 case ARM::VLD2d16wb_fixed: 2882 case ARM::VLD2d32wb_fixed: 2883 case ARM::VLD2q8wb_fixed: 2884 case ARM::VLD2q16wb_fixed: 2885 case ARM::VLD2q32wb_fixed: 2886 case ARM::VLD2d8wb_register: 2887 case ARM::VLD2d16wb_register: 2888 case ARM::VLD2d32wb_register: 2889 case ARM::VLD2q8wb_register: 2890 case ARM::VLD2q16wb_register: 2891 case ARM::VLD2q32wb_register: 2892 case ARM::VLD2b8wb_fixed: 2893 case ARM::VLD2b16wb_fixed: 2894 case ARM::VLD2b32wb_fixed: 2895 case ARM::VLD2b8wb_register: 2896 case ARM::VLD2b16wb_register: 2897 case ARM::VLD2b32wb_register: 2898 Inst.addOperand(MCOperand::createImm(0)); 2899 break; 2900 case ARM::VLD3d8_UPD: 2901 case ARM::VLD3d16_UPD: 2902 case ARM::VLD3d32_UPD: 2903 case ARM::VLD3q8_UPD: 2904 case ARM::VLD3q16_UPD: 2905 case ARM::VLD3q32_UPD: 2906 case ARM::VLD4d8_UPD: 2907 case ARM::VLD4d16_UPD: 2908 case ARM::VLD4d32_UPD: 2909 case ARM::VLD4q8_UPD: 2910 case ARM::VLD4q16_UPD: 2911 case ARM::VLD4q32_UPD: 2912 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2913 return MCDisassembler::Fail; 2914 break; 2915 default: 2916 break; 2917 } 2918 2919 // AddrMode6 Base (register+alignment) 2920 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2921 return MCDisassembler::Fail; 2922 2923 // AddrMode6 Offset (register) 2924 switch (Inst.getOpcode()) { 2925 default: 2926 // The below have been updated to have explicit am6offset split 2927 // between fixed and register offset. For those instructions not 2928 // yet updated, we need to add an additional reg0 operand for the 2929 // fixed variant. 2930 // 2931 // The fixed offset encodes as Rm == 0xd, so we check for that. 2932 if (Rm == 0xd) { 2933 Inst.addOperand(MCOperand::createReg(0)); 2934 break; 2935 } 2936 // Fall through to handle the register offset variant. 2937 LLVM_FALLTHROUGH; 2938 case ARM::VLD1d8wb_fixed: 2939 case ARM::VLD1d16wb_fixed: 2940 case ARM::VLD1d32wb_fixed: 2941 case ARM::VLD1d64wb_fixed: 2942 case ARM::VLD1d8Twb_fixed: 2943 case ARM::VLD1d16Twb_fixed: 2944 case ARM::VLD1d32Twb_fixed: 2945 case ARM::VLD1d64Twb_fixed: 2946 case ARM::VLD1d8Qwb_fixed: 2947 case ARM::VLD1d16Qwb_fixed: 2948 case ARM::VLD1d32Qwb_fixed: 2949 case ARM::VLD1d64Qwb_fixed: 2950 case ARM::VLD1d8wb_register: 2951 case ARM::VLD1d16wb_register: 2952 case ARM::VLD1d32wb_register: 2953 case ARM::VLD1d64wb_register: 2954 case ARM::VLD1q8wb_fixed: 2955 case ARM::VLD1q16wb_fixed: 2956 case ARM::VLD1q32wb_fixed: 2957 case ARM::VLD1q64wb_fixed: 2958 case ARM::VLD1q8wb_register: 2959 case ARM::VLD1q16wb_register: 2960 case ARM::VLD1q32wb_register: 2961 case ARM::VLD1q64wb_register: 2962 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2963 // variant encodes Rm == 0xf. Anything else is a register offset post- 2964 // increment and we need to add the register operand to the instruction. 2965 if (Rm != 0xD && Rm != 0xF && 2966 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2967 return MCDisassembler::Fail; 2968 break; 2969 case ARM::VLD2d8wb_fixed: 2970 case ARM::VLD2d16wb_fixed: 2971 case ARM::VLD2d32wb_fixed: 2972 case ARM::VLD2b8wb_fixed: 2973 case ARM::VLD2b16wb_fixed: 2974 case ARM::VLD2b32wb_fixed: 2975 case ARM::VLD2q8wb_fixed: 2976 case ARM::VLD2q16wb_fixed: 2977 case ARM::VLD2q32wb_fixed: 2978 break; 2979 } 2980 2981 return S; 2982 } 2983 2984 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2985 uint64_t Address, const void *Decoder) { 2986 unsigned type = fieldFromInstruction(Insn, 8, 4); 2987 unsigned align = fieldFromInstruction(Insn, 4, 2); 2988 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2989 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2990 if (type == 10 && align == 3) return MCDisassembler::Fail; 2991 2992 unsigned load = fieldFromInstruction(Insn, 21, 1); 2993 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2994 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2995 } 2996 2997 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2998 uint64_t Address, const void *Decoder) { 2999 unsigned size = fieldFromInstruction(Insn, 6, 2); 3000 if (size == 3) return MCDisassembler::Fail; 3001 3002 unsigned type = fieldFromInstruction(Insn, 8, 4); 3003 unsigned align = fieldFromInstruction(Insn, 4, 2); 3004 if (type == 8 && align == 3) return MCDisassembler::Fail; 3005 if (type == 9 && align == 3) return MCDisassembler::Fail; 3006 3007 unsigned load = fieldFromInstruction(Insn, 21, 1); 3008 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3009 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3010 } 3011 3012 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3013 uint64_t Address, const void *Decoder) { 3014 unsigned size = fieldFromInstruction(Insn, 6, 2); 3015 if (size == 3) return MCDisassembler::Fail; 3016 3017 unsigned align = fieldFromInstruction(Insn, 4, 2); 3018 if (align & 2) return MCDisassembler::Fail; 3019 3020 unsigned load = fieldFromInstruction(Insn, 21, 1); 3021 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3022 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3023 } 3024 3025 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3026 uint64_t Address, const void *Decoder) { 3027 unsigned size = fieldFromInstruction(Insn, 6, 2); 3028 if (size == 3) return MCDisassembler::Fail; 3029 3030 unsigned load = fieldFromInstruction(Insn, 21, 1); 3031 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3032 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3033 } 3034 3035 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3036 uint64_t Address, const void *Decoder) { 3037 DecodeStatus S = MCDisassembler::Success; 3038 3039 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3040 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3041 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3042 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3043 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3044 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3045 3046 // Writeback Operand 3047 switch (Inst.getOpcode()) { 3048 case ARM::VST1d8wb_fixed: 3049 case ARM::VST1d16wb_fixed: 3050 case ARM::VST1d32wb_fixed: 3051 case ARM::VST1d64wb_fixed: 3052 case ARM::VST1d8wb_register: 3053 case ARM::VST1d16wb_register: 3054 case ARM::VST1d32wb_register: 3055 case ARM::VST1d64wb_register: 3056 case ARM::VST1q8wb_fixed: 3057 case ARM::VST1q16wb_fixed: 3058 case ARM::VST1q32wb_fixed: 3059 case ARM::VST1q64wb_fixed: 3060 case ARM::VST1q8wb_register: 3061 case ARM::VST1q16wb_register: 3062 case ARM::VST1q32wb_register: 3063 case ARM::VST1q64wb_register: 3064 case ARM::VST1d8Twb_fixed: 3065 case ARM::VST1d16Twb_fixed: 3066 case ARM::VST1d32Twb_fixed: 3067 case ARM::VST1d64Twb_fixed: 3068 case ARM::VST1d8Twb_register: 3069 case ARM::VST1d16Twb_register: 3070 case ARM::VST1d32Twb_register: 3071 case ARM::VST1d64Twb_register: 3072 case ARM::VST1d8Qwb_fixed: 3073 case ARM::VST1d16Qwb_fixed: 3074 case ARM::VST1d32Qwb_fixed: 3075 case ARM::VST1d64Qwb_fixed: 3076 case ARM::VST1d8Qwb_register: 3077 case ARM::VST1d16Qwb_register: 3078 case ARM::VST1d32Qwb_register: 3079 case ARM::VST1d64Qwb_register: 3080 case ARM::VST2d8wb_fixed: 3081 case ARM::VST2d16wb_fixed: 3082 case ARM::VST2d32wb_fixed: 3083 case ARM::VST2d8wb_register: 3084 case ARM::VST2d16wb_register: 3085 case ARM::VST2d32wb_register: 3086 case ARM::VST2q8wb_fixed: 3087 case ARM::VST2q16wb_fixed: 3088 case ARM::VST2q32wb_fixed: 3089 case ARM::VST2q8wb_register: 3090 case ARM::VST2q16wb_register: 3091 case ARM::VST2q32wb_register: 3092 case ARM::VST2b8wb_fixed: 3093 case ARM::VST2b16wb_fixed: 3094 case ARM::VST2b32wb_fixed: 3095 case ARM::VST2b8wb_register: 3096 case ARM::VST2b16wb_register: 3097 case ARM::VST2b32wb_register: 3098 if (Rm == 0xF) 3099 return MCDisassembler::Fail; 3100 Inst.addOperand(MCOperand::createImm(0)); 3101 break; 3102 case ARM::VST3d8_UPD: 3103 case ARM::VST3d16_UPD: 3104 case ARM::VST3d32_UPD: 3105 case ARM::VST3q8_UPD: 3106 case ARM::VST3q16_UPD: 3107 case ARM::VST3q32_UPD: 3108 case ARM::VST4d8_UPD: 3109 case ARM::VST4d16_UPD: 3110 case ARM::VST4d32_UPD: 3111 case ARM::VST4q8_UPD: 3112 case ARM::VST4q16_UPD: 3113 case ARM::VST4q32_UPD: 3114 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3115 return MCDisassembler::Fail; 3116 break; 3117 default: 3118 break; 3119 } 3120 3121 // AddrMode6 Base (register+alignment) 3122 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3123 return MCDisassembler::Fail; 3124 3125 // AddrMode6 Offset (register) 3126 switch (Inst.getOpcode()) { 3127 default: 3128 if (Rm == 0xD) 3129 Inst.addOperand(MCOperand::createReg(0)); 3130 else if (Rm != 0xF) { 3131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3132 return MCDisassembler::Fail; 3133 } 3134 break; 3135 case ARM::VST1d8wb_fixed: 3136 case ARM::VST1d16wb_fixed: 3137 case ARM::VST1d32wb_fixed: 3138 case ARM::VST1d64wb_fixed: 3139 case ARM::VST1q8wb_fixed: 3140 case ARM::VST1q16wb_fixed: 3141 case ARM::VST1q32wb_fixed: 3142 case ARM::VST1q64wb_fixed: 3143 case ARM::VST1d8Twb_fixed: 3144 case ARM::VST1d16Twb_fixed: 3145 case ARM::VST1d32Twb_fixed: 3146 case ARM::VST1d64Twb_fixed: 3147 case ARM::VST1d8Qwb_fixed: 3148 case ARM::VST1d16Qwb_fixed: 3149 case ARM::VST1d32Qwb_fixed: 3150 case ARM::VST1d64Qwb_fixed: 3151 case ARM::VST2d8wb_fixed: 3152 case ARM::VST2d16wb_fixed: 3153 case ARM::VST2d32wb_fixed: 3154 case ARM::VST2q8wb_fixed: 3155 case ARM::VST2q16wb_fixed: 3156 case ARM::VST2q32wb_fixed: 3157 case ARM::VST2b8wb_fixed: 3158 case ARM::VST2b16wb_fixed: 3159 case ARM::VST2b32wb_fixed: 3160 break; 3161 } 3162 3163 // First input register 3164 switch (Inst.getOpcode()) { 3165 case ARM::VST1q16: 3166 case ARM::VST1q32: 3167 case ARM::VST1q64: 3168 case ARM::VST1q8: 3169 case ARM::VST1q16wb_fixed: 3170 case ARM::VST1q16wb_register: 3171 case ARM::VST1q32wb_fixed: 3172 case ARM::VST1q32wb_register: 3173 case ARM::VST1q64wb_fixed: 3174 case ARM::VST1q64wb_register: 3175 case ARM::VST1q8wb_fixed: 3176 case ARM::VST1q8wb_register: 3177 case ARM::VST2d16: 3178 case ARM::VST2d32: 3179 case ARM::VST2d8: 3180 case ARM::VST2d16wb_fixed: 3181 case ARM::VST2d16wb_register: 3182 case ARM::VST2d32wb_fixed: 3183 case ARM::VST2d32wb_register: 3184 case ARM::VST2d8wb_fixed: 3185 case ARM::VST2d8wb_register: 3186 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 break; 3189 case ARM::VST2b16: 3190 case ARM::VST2b32: 3191 case ARM::VST2b8: 3192 case ARM::VST2b16wb_fixed: 3193 case ARM::VST2b16wb_register: 3194 case ARM::VST2b32wb_fixed: 3195 case ARM::VST2b32wb_register: 3196 case ARM::VST2b8wb_fixed: 3197 case ARM::VST2b8wb_register: 3198 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3199 return MCDisassembler::Fail; 3200 break; 3201 default: 3202 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3203 return MCDisassembler::Fail; 3204 } 3205 3206 // Second input register 3207 switch (Inst.getOpcode()) { 3208 case ARM::VST3d8: 3209 case ARM::VST3d16: 3210 case ARM::VST3d32: 3211 case ARM::VST3d8_UPD: 3212 case ARM::VST3d16_UPD: 3213 case ARM::VST3d32_UPD: 3214 case ARM::VST4d8: 3215 case ARM::VST4d16: 3216 case ARM::VST4d32: 3217 case ARM::VST4d8_UPD: 3218 case ARM::VST4d16_UPD: 3219 case ARM::VST4d32_UPD: 3220 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3221 return MCDisassembler::Fail; 3222 break; 3223 case ARM::VST3q8: 3224 case ARM::VST3q16: 3225 case ARM::VST3q32: 3226 case ARM::VST3q8_UPD: 3227 case ARM::VST3q16_UPD: 3228 case ARM::VST3q32_UPD: 3229 case ARM::VST4q8: 3230 case ARM::VST4q16: 3231 case ARM::VST4q32: 3232 case ARM::VST4q8_UPD: 3233 case ARM::VST4q16_UPD: 3234 case ARM::VST4q32_UPD: 3235 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3236 return MCDisassembler::Fail; 3237 break; 3238 default: 3239 break; 3240 } 3241 3242 // Third input register 3243 switch (Inst.getOpcode()) { 3244 case ARM::VST3d8: 3245 case ARM::VST3d16: 3246 case ARM::VST3d32: 3247 case ARM::VST3d8_UPD: 3248 case ARM::VST3d16_UPD: 3249 case ARM::VST3d32_UPD: 3250 case ARM::VST4d8: 3251 case ARM::VST4d16: 3252 case ARM::VST4d32: 3253 case ARM::VST4d8_UPD: 3254 case ARM::VST4d16_UPD: 3255 case ARM::VST4d32_UPD: 3256 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3257 return MCDisassembler::Fail; 3258 break; 3259 case ARM::VST3q8: 3260 case ARM::VST3q16: 3261 case ARM::VST3q32: 3262 case ARM::VST3q8_UPD: 3263 case ARM::VST3q16_UPD: 3264 case ARM::VST3q32_UPD: 3265 case ARM::VST4q8: 3266 case ARM::VST4q16: 3267 case ARM::VST4q32: 3268 case ARM::VST4q8_UPD: 3269 case ARM::VST4q16_UPD: 3270 case ARM::VST4q32_UPD: 3271 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3272 return MCDisassembler::Fail; 3273 break; 3274 default: 3275 break; 3276 } 3277 3278 // Fourth input register 3279 switch (Inst.getOpcode()) { 3280 case ARM::VST4d8: 3281 case ARM::VST4d16: 3282 case ARM::VST4d32: 3283 case ARM::VST4d8_UPD: 3284 case ARM::VST4d16_UPD: 3285 case ARM::VST4d32_UPD: 3286 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3287 return MCDisassembler::Fail; 3288 break; 3289 case ARM::VST4q8: 3290 case ARM::VST4q16: 3291 case ARM::VST4q32: 3292 case ARM::VST4q8_UPD: 3293 case ARM::VST4q16_UPD: 3294 case ARM::VST4q32_UPD: 3295 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3296 return MCDisassembler::Fail; 3297 break; 3298 default: 3299 break; 3300 } 3301 3302 return S; 3303 } 3304 3305 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3306 uint64_t Address, const void *Decoder) { 3307 DecodeStatus S = MCDisassembler::Success; 3308 3309 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3310 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3311 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3312 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3313 unsigned align = fieldFromInstruction(Insn, 4, 1); 3314 unsigned size = fieldFromInstruction(Insn, 6, 2); 3315 3316 if (size == 0 && align == 1) 3317 return MCDisassembler::Fail; 3318 align *= (1 << size); 3319 3320 switch (Inst.getOpcode()) { 3321 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3322 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3323 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3324 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3325 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3326 return MCDisassembler::Fail; 3327 break; 3328 default: 3329 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3330 return MCDisassembler::Fail; 3331 break; 3332 } 3333 if (Rm != 0xF) { 3334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3335 return MCDisassembler::Fail; 3336 } 3337 3338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3339 return MCDisassembler::Fail; 3340 Inst.addOperand(MCOperand::createImm(align)); 3341 3342 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3343 // variant encodes Rm == 0xf. Anything else is a register offset post- 3344 // increment and we need to add the register operand to the instruction. 3345 if (Rm != 0xD && Rm != 0xF && 3346 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3347 return MCDisassembler::Fail; 3348 3349 return S; 3350 } 3351 3352 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3353 uint64_t Address, const void *Decoder) { 3354 DecodeStatus S = MCDisassembler::Success; 3355 3356 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3357 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3358 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3359 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3360 unsigned align = fieldFromInstruction(Insn, 4, 1); 3361 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3362 align *= 2*size; 3363 3364 switch (Inst.getOpcode()) { 3365 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3366 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3367 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3368 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3369 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3370 return MCDisassembler::Fail; 3371 break; 3372 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3373 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3374 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3375 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3376 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3377 return MCDisassembler::Fail; 3378 break; 3379 default: 3380 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3381 return MCDisassembler::Fail; 3382 break; 3383 } 3384 3385 if (Rm != 0xF) 3386 Inst.addOperand(MCOperand::createImm(0)); 3387 3388 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3389 return MCDisassembler::Fail; 3390 Inst.addOperand(MCOperand::createImm(align)); 3391 3392 if (Rm != 0xD && Rm != 0xF) { 3393 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3394 return MCDisassembler::Fail; 3395 } 3396 3397 return S; 3398 } 3399 3400 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3401 uint64_t Address, const void *Decoder) { 3402 DecodeStatus S = MCDisassembler::Success; 3403 3404 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3405 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3406 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3407 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3408 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3409 3410 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3411 return MCDisassembler::Fail; 3412 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3413 return MCDisassembler::Fail; 3414 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3415 return MCDisassembler::Fail; 3416 if (Rm != 0xF) { 3417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3418 return MCDisassembler::Fail; 3419 } 3420 3421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3422 return MCDisassembler::Fail; 3423 Inst.addOperand(MCOperand::createImm(0)); 3424 3425 if (Rm == 0xD) 3426 Inst.addOperand(MCOperand::createReg(0)); 3427 else if (Rm != 0xF) { 3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 } 3431 3432 return S; 3433 } 3434 3435 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3436 uint64_t Address, const void *Decoder) { 3437 DecodeStatus S = MCDisassembler::Success; 3438 3439 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3440 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3441 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3442 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3443 unsigned size = fieldFromInstruction(Insn, 6, 2); 3444 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3445 unsigned align = fieldFromInstruction(Insn, 4, 1); 3446 3447 if (size == 0x3) { 3448 if (align == 0) 3449 return MCDisassembler::Fail; 3450 align = 16; 3451 } else { 3452 if (size == 2) { 3453 align *= 8; 3454 } else { 3455 size = 1 << size; 3456 align *= 4*size; 3457 } 3458 } 3459 3460 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3463 return MCDisassembler::Fail; 3464 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3467 return MCDisassembler::Fail; 3468 if (Rm != 0xF) { 3469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3470 return MCDisassembler::Fail; 3471 } 3472 3473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3474 return MCDisassembler::Fail; 3475 Inst.addOperand(MCOperand::createImm(align)); 3476 3477 if (Rm == 0xD) 3478 Inst.addOperand(MCOperand::createReg(0)); 3479 else if (Rm != 0xF) { 3480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3481 return MCDisassembler::Fail; 3482 } 3483 3484 return S; 3485 } 3486 3487 static DecodeStatus 3488 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3489 uint64_t Address, const void *Decoder) { 3490 DecodeStatus S = MCDisassembler::Success; 3491 3492 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3493 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3494 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3495 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3496 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3497 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3498 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3499 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3500 3501 if (Q) { 3502 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3503 return MCDisassembler::Fail; 3504 } else { 3505 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3506 return MCDisassembler::Fail; 3507 } 3508 3509 Inst.addOperand(MCOperand::createImm(imm)); 3510 3511 switch (Inst.getOpcode()) { 3512 case ARM::VORRiv4i16: 3513 case ARM::VORRiv2i32: 3514 case ARM::VBICiv4i16: 3515 case ARM::VBICiv2i32: 3516 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3517 return MCDisassembler::Fail; 3518 break; 3519 case ARM::VORRiv8i16: 3520 case ARM::VORRiv4i32: 3521 case ARM::VBICiv8i16: 3522 case ARM::VBICiv4i32: 3523 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3524 return MCDisassembler::Fail; 3525 break; 3526 default: 3527 break; 3528 } 3529 3530 return S; 3531 } 3532 3533 static DecodeStatus 3534 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3535 uint64_t Address, const void *Decoder) { 3536 DecodeStatus S = MCDisassembler::Success; 3537 3538 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3539 fieldFromInstruction(Insn, 13, 3)); 3540 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3541 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3542 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3543 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3544 imm |= cmode << 8; 3545 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3546 3547 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3548 return MCDisassembler::Fail; 3549 3550 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3551 return MCDisassembler::Fail; 3552 3553 Inst.addOperand(MCOperand::createImm(imm)); 3554 3555 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3556 Inst.addOperand(MCOperand::createReg(0)); 3557 Inst.addOperand(MCOperand::createImm(0)); 3558 3559 return S; 3560 } 3561 3562 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3563 uint64_t Address, const void *Decoder) { 3564 DecodeStatus S = MCDisassembler::Success; 3565 3566 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3567 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3568 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3569 return MCDisassembler::Fail; 3570 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3571 3572 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3573 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3574 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3575 return MCDisassembler::Fail; 3576 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3577 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3578 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3579 return MCDisassembler::Fail; 3580 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3581 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3582 Inst.addOperand(MCOperand::createImm(Qd)); 3583 3584 return S; 3585 } 3586 3587 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3588 uint64_t Address, const void *Decoder) { 3589 DecodeStatus S = MCDisassembler::Success; 3590 3591 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3592 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3593 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3594 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3595 unsigned size = fieldFromInstruction(Insn, 18, 2); 3596 3597 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3600 return MCDisassembler::Fail; 3601 Inst.addOperand(MCOperand::createImm(8 << size)); 3602 3603 return S; 3604 } 3605 3606 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3607 uint64_t Address, const void *Decoder) { 3608 Inst.addOperand(MCOperand::createImm(8 - Val)); 3609 return MCDisassembler::Success; 3610 } 3611 3612 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3613 uint64_t Address, const void *Decoder) { 3614 Inst.addOperand(MCOperand::createImm(16 - Val)); 3615 return MCDisassembler::Success; 3616 } 3617 3618 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3619 uint64_t Address, const void *Decoder) { 3620 Inst.addOperand(MCOperand::createImm(32 - Val)); 3621 return MCDisassembler::Success; 3622 } 3623 3624 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3625 uint64_t Address, const void *Decoder) { 3626 Inst.addOperand(MCOperand::createImm(64 - Val)); 3627 return MCDisassembler::Success; 3628 } 3629 3630 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3631 uint64_t Address, const void *Decoder) { 3632 DecodeStatus S = MCDisassembler::Success; 3633 3634 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3635 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3636 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3637 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3638 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3639 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3640 unsigned op = fieldFromInstruction(Insn, 6, 1); 3641 3642 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 if (op) { 3645 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3646 return MCDisassembler::Fail; // Writeback 3647 } 3648 3649 switch (Inst.getOpcode()) { 3650 case ARM::VTBL2: 3651 case ARM::VTBX2: 3652 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3653 return MCDisassembler::Fail; 3654 break; 3655 default: 3656 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3657 return MCDisassembler::Fail; 3658 } 3659 3660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3661 return MCDisassembler::Fail; 3662 3663 return S; 3664 } 3665 3666 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3667 uint64_t Address, const void *Decoder) { 3668 DecodeStatus S = MCDisassembler::Success; 3669 3670 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3671 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3672 3673 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3674 return MCDisassembler::Fail; 3675 3676 switch(Inst.getOpcode()) { 3677 default: 3678 return MCDisassembler::Fail; 3679 case ARM::tADR: 3680 break; // tADR does not explicitly represent the PC as an operand. 3681 case ARM::tADDrSPi: 3682 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3683 break; 3684 } 3685 3686 Inst.addOperand(MCOperand::createImm(imm)); 3687 return S; 3688 } 3689 3690 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3691 uint64_t Address, const void *Decoder) { 3692 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3693 true, 2, Inst, Decoder)) 3694 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3695 return MCDisassembler::Success; 3696 } 3697 3698 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3699 uint64_t Address, const void *Decoder) { 3700 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3701 true, 4, Inst, Decoder)) 3702 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3703 return MCDisassembler::Success; 3704 } 3705 3706 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3707 uint64_t Address, const void *Decoder) { 3708 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3709 true, 2, Inst, Decoder)) 3710 Inst.addOperand(MCOperand::createImm(Val << 1)); 3711 return MCDisassembler::Success; 3712 } 3713 3714 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3715 uint64_t Address, const void *Decoder) { 3716 DecodeStatus S = MCDisassembler::Success; 3717 3718 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3719 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3720 3721 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3722 return MCDisassembler::Fail; 3723 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3724 return MCDisassembler::Fail; 3725 3726 return S; 3727 } 3728 3729 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3730 uint64_t Address, const void *Decoder) { 3731 DecodeStatus S = MCDisassembler::Success; 3732 3733 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3734 unsigned imm = fieldFromInstruction(Val, 3, 5); 3735 3736 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3737 return MCDisassembler::Fail; 3738 Inst.addOperand(MCOperand::createImm(imm)); 3739 3740 return S; 3741 } 3742 3743 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3744 uint64_t Address, const void *Decoder) { 3745 unsigned imm = Val << 2; 3746 3747 Inst.addOperand(MCOperand::createImm(imm)); 3748 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3749 3750 return MCDisassembler::Success; 3751 } 3752 3753 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3754 uint64_t Address, const void *Decoder) { 3755 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3756 Inst.addOperand(MCOperand::createImm(Val)); 3757 3758 return MCDisassembler::Success; 3759 } 3760 3761 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3762 uint64_t Address, const void *Decoder) { 3763 DecodeStatus S = MCDisassembler::Success; 3764 3765 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3766 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3767 unsigned imm = fieldFromInstruction(Val, 0, 2); 3768 3769 // Thumb stores cannot use PC as dest register. 3770 switch (Inst.getOpcode()) { 3771 case ARM::t2STRHs: 3772 case ARM::t2STRBs: 3773 case ARM::t2STRs: 3774 if (Rn == 15) 3775 return MCDisassembler::Fail; 3776 break; 3777 default: 3778 break; 3779 } 3780 3781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3782 return MCDisassembler::Fail; 3783 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3784 return MCDisassembler::Fail; 3785 Inst.addOperand(MCOperand::createImm(imm)); 3786 3787 return S; 3788 } 3789 3790 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3791 uint64_t Address, const void *Decoder) { 3792 DecodeStatus S = MCDisassembler::Success; 3793 3794 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3795 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3796 3797 const FeatureBitset &featureBits = 3798 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3799 3800 bool hasMP = featureBits[ARM::FeatureMP]; 3801 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3802 3803 if (Rn == 15) { 3804 switch (Inst.getOpcode()) { 3805 case ARM::t2LDRBs: 3806 Inst.setOpcode(ARM::t2LDRBpci); 3807 break; 3808 case ARM::t2LDRHs: 3809 Inst.setOpcode(ARM::t2LDRHpci); 3810 break; 3811 case ARM::t2LDRSHs: 3812 Inst.setOpcode(ARM::t2LDRSHpci); 3813 break; 3814 case ARM::t2LDRSBs: 3815 Inst.setOpcode(ARM::t2LDRSBpci); 3816 break; 3817 case ARM::t2LDRs: 3818 Inst.setOpcode(ARM::t2LDRpci); 3819 break; 3820 case ARM::t2PLDs: 3821 Inst.setOpcode(ARM::t2PLDpci); 3822 break; 3823 case ARM::t2PLIs: 3824 Inst.setOpcode(ARM::t2PLIpci); 3825 break; 3826 default: 3827 return MCDisassembler::Fail; 3828 } 3829 3830 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3831 } 3832 3833 if (Rt == 15) { 3834 switch (Inst.getOpcode()) { 3835 case ARM::t2LDRSHs: 3836 return MCDisassembler::Fail; 3837 case ARM::t2LDRHs: 3838 Inst.setOpcode(ARM::t2PLDWs); 3839 break; 3840 case ARM::t2LDRSBs: 3841 Inst.setOpcode(ARM::t2PLIs); 3842 break; 3843 default: 3844 break; 3845 } 3846 } 3847 3848 switch (Inst.getOpcode()) { 3849 case ARM::t2PLDs: 3850 break; 3851 case ARM::t2PLIs: 3852 if (!hasV7Ops) 3853 return MCDisassembler::Fail; 3854 break; 3855 case ARM::t2PLDWs: 3856 if (!hasV7Ops || !hasMP) 3857 return MCDisassembler::Fail; 3858 break; 3859 default: 3860 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3861 return MCDisassembler::Fail; 3862 } 3863 3864 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3865 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3866 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3867 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3868 return MCDisassembler::Fail; 3869 3870 return S; 3871 } 3872 3873 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3874 uint64_t Address, const void* Decoder) { 3875 DecodeStatus S = MCDisassembler::Success; 3876 3877 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3878 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3879 unsigned U = fieldFromInstruction(Insn, 9, 1); 3880 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3881 imm |= (U << 8); 3882 imm |= (Rn << 9); 3883 unsigned add = fieldFromInstruction(Insn, 9, 1); 3884 3885 const FeatureBitset &featureBits = 3886 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3887 3888 bool hasMP = featureBits[ARM::FeatureMP]; 3889 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3890 3891 if (Rn == 15) { 3892 switch (Inst.getOpcode()) { 3893 case ARM::t2LDRi8: 3894 Inst.setOpcode(ARM::t2LDRpci); 3895 break; 3896 case ARM::t2LDRBi8: 3897 Inst.setOpcode(ARM::t2LDRBpci); 3898 break; 3899 case ARM::t2LDRSBi8: 3900 Inst.setOpcode(ARM::t2LDRSBpci); 3901 break; 3902 case ARM::t2LDRHi8: 3903 Inst.setOpcode(ARM::t2LDRHpci); 3904 break; 3905 case ARM::t2LDRSHi8: 3906 Inst.setOpcode(ARM::t2LDRSHpci); 3907 break; 3908 case ARM::t2PLDi8: 3909 Inst.setOpcode(ARM::t2PLDpci); 3910 break; 3911 case ARM::t2PLIi8: 3912 Inst.setOpcode(ARM::t2PLIpci); 3913 break; 3914 default: 3915 return MCDisassembler::Fail; 3916 } 3917 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3918 } 3919 3920 if (Rt == 15) { 3921 switch (Inst.getOpcode()) { 3922 case ARM::t2LDRSHi8: 3923 return MCDisassembler::Fail; 3924 case ARM::t2LDRHi8: 3925 if (!add) 3926 Inst.setOpcode(ARM::t2PLDWi8); 3927 break; 3928 case ARM::t2LDRSBi8: 3929 Inst.setOpcode(ARM::t2PLIi8); 3930 break; 3931 default: 3932 break; 3933 } 3934 } 3935 3936 switch (Inst.getOpcode()) { 3937 case ARM::t2PLDi8: 3938 break; 3939 case ARM::t2PLIi8: 3940 if (!hasV7Ops) 3941 return MCDisassembler::Fail; 3942 break; 3943 case ARM::t2PLDWi8: 3944 if (!hasV7Ops || !hasMP) 3945 return MCDisassembler::Fail; 3946 break; 3947 default: 3948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3949 return MCDisassembler::Fail; 3950 } 3951 3952 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3953 return MCDisassembler::Fail; 3954 return S; 3955 } 3956 3957 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3958 uint64_t Address, const void* Decoder) { 3959 DecodeStatus S = MCDisassembler::Success; 3960 3961 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3962 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3963 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3964 imm |= (Rn << 13); 3965 3966 const FeatureBitset &featureBits = 3967 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3968 3969 bool hasMP = featureBits[ARM::FeatureMP]; 3970 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3971 3972 if (Rn == 15) { 3973 switch (Inst.getOpcode()) { 3974 case ARM::t2LDRi12: 3975 Inst.setOpcode(ARM::t2LDRpci); 3976 break; 3977 case ARM::t2LDRHi12: 3978 Inst.setOpcode(ARM::t2LDRHpci); 3979 break; 3980 case ARM::t2LDRSHi12: 3981 Inst.setOpcode(ARM::t2LDRSHpci); 3982 break; 3983 case ARM::t2LDRBi12: 3984 Inst.setOpcode(ARM::t2LDRBpci); 3985 break; 3986 case ARM::t2LDRSBi12: 3987 Inst.setOpcode(ARM::t2LDRSBpci); 3988 break; 3989 case ARM::t2PLDi12: 3990 Inst.setOpcode(ARM::t2PLDpci); 3991 break; 3992 case ARM::t2PLIi12: 3993 Inst.setOpcode(ARM::t2PLIpci); 3994 break; 3995 default: 3996 return MCDisassembler::Fail; 3997 } 3998 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3999 } 4000 4001 if (Rt == 15) { 4002 switch (Inst.getOpcode()) { 4003 case ARM::t2LDRSHi12: 4004 return MCDisassembler::Fail; 4005 case ARM::t2LDRHi12: 4006 Inst.setOpcode(ARM::t2PLDWi12); 4007 break; 4008 case ARM::t2LDRSBi12: 4009 Inst.setOpcode(ARM::t2PLIi12); 4010 break; 4011 default: 4012 break; 4013 } 4014 } 4015 4016 switch (Inst.getOpcode()) { 4017 case ARM::t2PLDi12: 4018 break; 4019 case ARM::t2PLIi12: 4020 if (!hasV7Ops) 4021 return MCDisassembler::Fail; 4022 break; 4023 case ARM::t2PLDWi12: 4024 if (!hasV7Ops || !hasMP) 4025 return MCDisassembler::Fail; 4026 break; 4027 default: 4028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 } 4031 4032 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4033 return MCDisassembler::Fail; 4034 return S; 4035 } 4036 4037 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 4038 uint64_t Address, const void* Decoder) { 4039 DecodeStatus S = MCDisassembler::Success; 4040 4041 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4042 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4043 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4044 imm |= (Rn << 9); 4045 4046 if (Rn == 15) { 4047 switch (Inst.getOpcode()) { 4048 case ARM::t2LDRT: 4049 Inst.setOpcode(ARM::t2LDRpci); 4050 break; 4051 case ARM::t2LDRBT: 4052 Inst.setOpcode(ARM::t2LDRBpci); 4053 break; 4054 case ARM::t2LDRHT: 4055 Inst.setOpcode(ARM::t2LDRHpci); 4056 break; 4057 case ARM::t2LDRSBT: 4058 Inst.setOpcode(ARM::t2LDRSBpci); 4059 break; 4060 case ARM::t2LDRSHT: 4061 Inst.setOpcode(ARM::t2LDRSHpci); 4062 break; 4063 default: 4064 return MCDisassembler::Fail; 4065 } 4066 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4067 } 4068 4069 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4070 return MCDisassembler::Fail; 4071 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4072 return MCDisassembler::Fail; 4073 return S; 4074 } 4075 4076 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4077 uint64_t Address, const void* Decoder) { 4078 DecodeStatus S = MCDisassembler::Success; 4079 4080 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4081 unsigned U = fieldFromInstruction(Insn, 23, 1); 4082 int imm = fieldFromInstruction(Insn, 0, 12); 4083 4084 const FeatureBitset &featureBits = 4085 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4086 4087 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4088 4089 if (Rt == 15) { 4090 switch (Inst.getOpcode()) { 4091 case ARM::t2LDRBpci: 4092 case ARM::t2LDRHpci: 4093 Inst.setOpcode(ARM::t2PLDpci); 4094 break; 4095 case ARM::t2LDRSBpci: 4096 Inst.setOpcode(ARM::t2PLIpci); 4097 break; 4098 case ARM::t2LDRSHpci: 4099 return MCDisassembler::Fail; 4100 default: 4101 break; 4102 } 4103 } 4104 4105 switch(Inst.getOpcode()) { 4106 case ARM::t2PLDpci: 4107 break; 4108 case ARM::t2PLIpci: 4109 if (!hasV7Ops) 4110 return MCDisassembler::Fail; 4111 break; 4112 default: 4113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4114 return MCDisassembler::Fail; 4115 } 4116 4117 if (!U) { 4118 // Special case for #-0. 4119 if (imm == 0) 4120 imm = INT32_MIN; 4121 else 4122 imm = -imm; 4123 } 4124 Inst.addOperand(MCOperand::createImm(imm)); 4125 4126 return S; 4127 } 4128 4129 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4130 uint64_t Address, const void *Decoder) { 4131 if (Val == 0) 4132 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4133 else { 4134 int imm = Val & 0xFF; 4135 4136 if (!(Val & 0x100)) imm *= -1; 4137 Inst.addOperand(MCOperand::createImm(imm * 4)); 4138 } 4139 4140 return MCDisassembler::Success; 4141 } 4142 4143 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4144 const void *Decoder) { 4145 if (Val == 0) 4146 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4147 else { 4148 int imm = Val & 0x7F; 4149 4150 if (!(Val & 0x80)) 4151 imm *= -1; 4152 Inst.addOperand(MCOperand::createImm(imm * 4)); 4153 } 4154 4155 return MCDisassembler::Success; 4156 } 4157 4158 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4159 uint64_t Address, const void *Decoder) { 4160 DecodeStatus S = MCDisassembler::Success; 4161 4162 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4163 unsigned imm = fieldFromInstruction(Val, 0, 9); 4164 4165 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4166 return MCDisassembler::Fail; 4167 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4168 return MCDisassembler::Fail; 4169 4170 return S; 4171 } 4172 4173 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4174 uint64_t Address, 4175 const void *Decoder) { 4176 DecodeStatus S = MCDisassembler::Success; 4177 4178 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4179 unsigned imm = fieldFromInstruction(Val, 0, 8); 4180 4181 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4182 return MCDisassembler::Fail; 4183 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4184 return MCDisassembler::Fail; 4185 4186 return S; 4187 } 4188 4189 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4190 uint64_t Address, const void *Decoder) { 4191 DecodeStatus S = MCDisassembler::Success; 4192 4193 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4194 unsigned imm = fieldFromInstruction(Val, 0, 8); 4195 4196 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4197 return MCDisassembler::Fail; 4198 4199 Inst.addOperand(MCOperand::createImm(imm)); 4200 4201 return S; 4202 } 4203 4204 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4205 uint64_t Address, const void *Decoder) { 4206 int imm = Val & 0xFF; 4207 if (Val == 0) 4208 imm = INT32_MIN; 4209 else if (!(Val & 0x100)) 4210 imm *= -1; 4211 Inst.addOperand(MCOperand::createImm(imm)); 4212 4213 return MCDisassembler::Success; 4214 } 4215 4216 template<int shift> 4217 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4218 uint64_t Address, const void *Decoder) { 4219 int imm = Val & 0x7F; 4220 if (Val == 0) 4221 imm = INT32_MIN; 4222 else if (!(Val & 0x80)) 4223 imm *= -1; 4224 if (imm != INT32_MIN) 4225 imm *= (1U << shift); 4226 Inst.addOperand(MCOperand::createImm(imm)); 4227 4228 return MCDisassembler::Success; 4229 } 4230 4231 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4232 uint64_t Address, const void *Decoder) { 4233 DecodeStatus S = MCDisassembler::Success; 4234 4235 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4236 unsigned imm = fieldFromInstruction(Val, 0, 9); 4237 4238 // Thumb stores cannot use PC as dest register. 4239 switch (Inst.getOpcode()) { 4240 case ARM::t2STRT: 4241 case ARM::t2STRBT: 4242 case ARM::t2STRHT: 4243 case ARM::t2STRi8: 4244 case ARM::t2STRHi8: 4245 case ARM::t2STRBi8: 4246 if (Rn == 15) 4247 return MCDisassembler::Fail; 4248 break; 4249 default: 4250 break; 4251 } 4252 4253 // Some instructions always use an additive offset. 4254 switch (Inst.getOpcode()) { 4255 case ARM::t2LDRT: 4256 case ARM::t2LDRBT: 4257 case ARM::t2LDRHT: 4258 case ARM::t2LDRSBT: 4259 case ARM::t2LDRSHT: 4260 case ARM::t2STRT: 4261 case ARM::t2STRBT: 4262 case ARM::t2STRHT: 4263 imm |= 0x100; 4264 break; 4265 default: 4266 break; 4267 } 4268 4269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4270 return MCDisassembler::Fail; 4271 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4272 return MCDisassembler::Fail; 4273 4274 return S; 4275 } 4276 4277 template<int shift> 4278 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4279 uint64_t Address, 4280 const void *Decoder) { 4281 DecodeStatus S = MCDisassembler::Success; 4282 4283 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4284 unsigned imm = fieldFromInstruction(Val, 0, 8); 4285 4286 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4287 return MCDisassembler::Fail; 4288 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4289 return MCDisassembler::Fail; 4290 4291 return S; 4292 } 4293 4294 template<int shift, int WriteBack> 4295 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4296 uint64_t Address, 4297 const void *Decoder) { 4298 DecodeStatus S = MCDisassembler::Success; 4299 4300 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4301 unsigned imm = fieldFromInstruction(Val, 0, 8); 4302 if (WriteBack) { 4303 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4306 return MCDisassembler::Fail; 4307 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4308 return MCDisassembler::Fail; 4309 4310 return S; 4311 } 4312 4313 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4314 uint64_t Address, const void *Decoder) { 4315 DecodeStatus S = MCDisassembler::Success; 4316 4317 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4318 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4319 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4320 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4321 addr |= Rn << 9; 4322 unsigned load = fieldFromInstruction(Insn, 20, 1); 4323 4324 if (Rn == 15) { 4325 switch (Inst.getOpcode()) { 4326 case ARM::t2LDR_PRE: 4327 case ARM::t2LDR_POST: 4328 Inst.setOpcode(ARM::t2LDRpci); 4329 break; 4330 case ARM::t2LDRB_PRE: 4331 case ARM::t2LDRB_POST: 4332 Inst.setOpcode(ARM::t2LDRBpci); 4333 break; 4334 case ARM::t2LDRH_PRE: 4335 case ARM::t2LDRH_POST: 4336 Inst.setOpcode(ARM::t2LDRHpci); 4337 break; 4338 case ARM::t2LDRSB_PRE: 4339 case ARM::t2LDRSB_POST: 4340 if (Rt == 15) 4341 Inst.setOpcode(ARM::t2PLIpci); 4342 else 4343 Inst.setOpcode(ARM::t2LDRSBpci); 4344 break; 4345 case ARM::t2LDRSH_PRE: 4346 case ARM::t2LDRSH_POST: 4347 Inst.setOpcode(ARM::t2LDRSHpci); 4348 break; 4349 default: 4350 return MCDisassembler::Fail; 4351 } 4352 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4353 } 4354 4355 if (!load) { 4356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4357 return MCDisassembler::Fail; 4358 } 4359 4360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4361 return MCDisassembler::Fail; 4362 4363 if (load) { 4364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4365 return MCDisassembler::Fail; 4366 } 4367 4368 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4369 return MCDisassembler::Fail; 4370 4371 return S; 4372 } 4373 4374 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4375 uint64_t Address, const void *Decoder) { 4376 DecodeStatus S = MCDisassembler::Success; 4377 4378 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4379 unsigned imm = fieldFromInstruction(Val, 0, 12); 4380 4381 // Thumb stores cannot use PC as dest register. 4382 switch (Inst.getOpcode()) { 4383 case ARM::t2STRi12: 4384 case ARM::t2STRBi12: 4385 case ARM::t2STRHi12: 4386 if (Rn == 15) 4387 return MCDisassembler::Fail; 4388 break; 4389 default: 4390 break; 4391 } 4392 4393 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4394 return MCDisassembler::Fail; 4395 Inst.addOperand(MCOperand::createImm(imm)); 4396 4397 return S; 4398 } 4399 4400 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4401 uint64_t Address, const void *Decoder) { 4402 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4403 4404 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4405 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4406 Inst.addOperand(MCOperand::createImm(imm)); 4407 4408 return MCDisassembler::Success; 4409 } 4410 4411 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4412 uint64_t Address, const void *Decoder) { 4413 DecodeStatus S = MCDisassembler::Success; 4414 4415 if (Inst.getOpcode() == ARM::tADDrSP) { 4416 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4417 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4418 4419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4420 return MCDisassembler::Fail; 4421 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4423 return MCDisassembler::Fail; 4424 } else if (Inst.getOpcode() == ARM::tADDspr) { 4425 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4426 4427 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4428 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4430 return MCDisassembler::Fail; 4431 } 4432 4433 return S; 4434 } 4435 4436 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4437 uint64_t Address, const void *Decoder) { 4438 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4439 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4440 4441 Inst.addOperand(MCOperand::createImm(imod)); 4442 Inst.addOperand(MCOperand::createImm(flags)); 4443 4444 return MCDisassembler::Success; 4445 } 4446 4447 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4448 uint64_t Address, const void *Decoder) { 4449 DecodeStatus S = MCDisassembler::Success; 4450 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4451 unsigned add = fieldFromInstruction(Insn, 4, 1); 4452 4453 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4454 return MCDisassembler::Fail; 4455 Inst.addOperand(MCOperand::createImm(add)); 4456 4457 return S; 4458 } 4459 4460 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4461 uint64_t Address, const void *Decoder) { 4462 DecodeStatus S = MCDisassembler::Success; 4463 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4464 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4465 4466 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4467 return MCDisassembler::Fail; 4468 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4469 return MCDisassembler::Fail; 4470 4471 return S; 4472 } 4473 4474 template<int shift> 4475 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4476 uint64_t Address, const void *Decoder) { 4477 DecodeStatus S = MCDisassembler::Success; 4478 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4479 int imm = fieldFromInstruction(Insn, 0, 7); 4480 4481 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4482 return MCDisassembler::Fail; 4483 4484 if(!fieldFromInstruction(Insn, 7, 1)) { 4485 if (imm == 0) 4486 imm = INT32_MIN; // indicate -0 4487 else 4488 imm *= -1; 4489 } 4490 if (imm != INT32_MIN) 4491 imm *= (1U << shift); 4492 Inst.addOperand(MCOperand::createImm(imm)); 4493 4494 return S; 4495 } 4496 4497 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4498 uint64_t Address, const void *Decoder) { 4499 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4500 // Note only one trailing zero not two. Also the J1 and J2 values are from 4501 // the encoded instruction. So here change to I1 and I2 values via: 4502 // I1 = NOT(J1 EOR S); 4503 // I2 = NOT(J2 EOR S); 4504 // and build the imm32 with two trailing zeros as documented: 4505 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4506 unsigned S = (Val >> 23) & 1; 4507 unsigned J1 = (Val >> 22) & 1; 4508 unsigned J2 = (Val >> 21) & 1; 4509 unsigned I1 = !(J1 ^ S); 4510 unsigned I2 = !(J2 ^ S); 4511 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4512 int imm32 = SignExtend32<25>(tmp << 1); 4513 4514 if (!tryAddingSymbolicOperand(Address, 4515 (Address & ~2u) + imm32 + 4, 4516 true, 4, Inst, Decoder)) 4517 Inst.addOperand(MCOperand::createImm(imm32)); 4518 return MCDisassembler::Success; 4519 } 4520 4521 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4522 uint64_t Address, const void *Decoder) { 4523 if (Val == 0xA || Val == 0xB) 4524 return MCDisassembler::Fail; 4525 4526 const FeatureBitset &featureBits = 4527 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4528 4529 if (!isValidCoprocessorNumber(Val, featureBits)) 4530 return MCDisassembler::Fail; 4531 4532 Inst.addOperand(MCOperand::createImm(Val)); 4533 return MCDisassembler::Success; 4534 } 4535 4536 static DecodeStatus 4537 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4538 uint64_t Address, const void *Decoder) { 4539 const FeatureBitset &FeatureBits = 4540 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4541 DecodeStatus S = MCDisassembler::Success; 4542 4543 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4544 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4545 4546 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4548 return MCDisassembler::Fail; 4549 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4550 return MCDisassembler::Fail; 4551 return S; 4552 } 4553 4554 static DecodeStatus 4555 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4556 uint64_t Address, const void *Decoder) { 4557 DecodeStatus S = MCDisassembler::Success; 4558 4559 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4560 if (pred == 0xE || pred == 0xF) { 4561 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4562 switch (opc) { 4563 default: 4564 return MCDisassembler::Fail; 4565 case 0xf3bf8f4: 4566 Inst.setOpcode(ARM::t2DSB); 4567 break; 4568 case 0xf3bf8f5: 4569 Inst.setOpcode(ARM::t2DMB); 4570 break; 4571 case 0xf3bf8f6: 4572 Inst.setOpcode(ARM::t2ISB); 4573 break; 4574 } 4575 4576 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4577 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4578 } 4579 4580 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4581 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4582 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4583 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4584 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4585 4586 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4587 return MCDisassembler::Fail; 4588 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4589 return MCDisassembler::Fail; 4590 4591 return S; 4592 } 4593 4594 // Decode a shifted immediate operand. These basically consist 4595 // of an 8-bit value, and a 4-bit directive that specifies either 4596 // a splat operation or a rotation. 4597 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4598 uint64_t Address, const void *Decoder) { 4599 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4600 if (ctrl == 0) { 4601 unsigned byte = fieldFromInstruction(Val, 8, 2); 4602 unsigned imm = fieldFromInstruction(Val, 0, 8); 4603 switch (byte) { 4604 case 0: 4605 Inst.addOperand(MCOperand::createImm(imm)); 4606 break; 4607 case 1: 4608 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4609 break; 4610 case 2: 4611 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4612 break; 4613 case 3: 4614 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4615 (imm << 8) | imm)); 4616 break; 4617 } 4618 } else { 4619 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4620 unsigned rot = fieldFromInstruction(Val, 7, 5); 4621 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4622 Inst.addOperand(MCOperand::createImm(imm)); 4623 } 4624 4625 return MCDisassembler::Success; 4626 } 4627 4628 static DecodeStatus 4629 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4630 uint64_t Address, const void *Decoder) { 4631 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4632 true, 2, Inst, Decoder)) 4633 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4634 return MCDisassembler::Success; 4635 } 4636 4637 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4638 uint64_t Address, 4639 const void *Decoder) { 4640 // Val is passed in as S:J1:J2:imm10:imm11 4641 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4642 // the encoded instruction. So here change to I1 and I2 values via: 4643 // I1 = NOT(J1 EOR S); 4644 // I2 = NOT(J2 EOR S); 4645 // and build the imm32 with one trailing zero as documented: 4646 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4647 unsigned S = (Val >> 23) & 1; 4648 unsigned J1 = (Val >> 22) & 1; 4649 unsigned J2 = (Val >> 21) & 1; 4650 unsigned I1 = !(J1 ^ S); 4651 unsigned I2 = !(J2 ^ S); 4652 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4653 int imm32 = SignExtend32<25>(tmp << 1); 4654 4655 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4656 true, 4, Inst, Decoder)) 4657 Inst.addOperand(MCOperand::createImm(imm32)); 4658 return MCDisassembler::Success; 4659 } 4660 4661 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4662 uint64_t Address, const void *Decoder) { 4663 if (Val & ~0xf) 4664 return MCDisassembler::Fail; 4665 4666 Inst.addOperand(MCOperand::createImm(Val)); 4667 return MCDisassembler::Success; 4668 } 4669 4670 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4671 uint64_t Address, const void *Decoder) { 4672 if (Val & ~0xf) 4673 return MCDisassembler::Fail; 4674 4675 Inst.addOperand(MCOperand::createImm(Val)); 4676 return MCDisassembler::Success; 4677 } 4678 4679 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4680 uint64_t Address, const void *Decoder) { 4681 DecodeStatus S = MCDisassembler::Success; 4682 const FeatureBitset &FeatureBits = 4683 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4684 4685 if (FeatureBits[ARM::FeatureMClass]) { 4686 unsigned ValLow = Val & 0xff; 4687 4688 // Validate the SYSm value first. 4689 switch (ValLow) { 4690 case 0: // apsr 4691 case 1: // iapsr 4692 case 2: // eapsr 4693 case 3: // xpsr 4694 case 5: // ipsr 4695 case 6: // epsr 4696 case 7: // iepsr 4697 case 8: // msp 4698 case 9: // psp 4699 case 16: // primask 4700 case 20: // control 4701 break; 4702 case 17: // basepri 4703 case 18: // basepri_max 4704 case 19: // faultmask 4705 if (!(FeatureBits[ARM::HasV7Ops])) 4706 // Values basepri, basepri_max and faultmask are only valid for v7m. 4707 return MCDisassembler::Fail; 4708 break; 4709 case 0x8a: // msplim_ns 4710 case 0x8b: // psplim_ns 4711 case 0x91: // basepri_ns 4712 case 0x93: // faultmask_ns 4713 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4714 return MCDisassembler::Fail; 4715 LLVM_FALLTHROUGH; 4716 case 10: // msplim 4717 case 11: // psplim 4718 case 0x88: // msp_ns 4719 case 0x89: // psp_ns 4720 case 0x90: // primask_ns 4721 case 0x94: // control_ns 4722 case 0x98: // sp_ns 4723 if (!(FeatureBits[ARM::Feature8MSecExt])) 4724 return MCDisassembler::Fail; 4725 break; 4726 default: 4727 // Architecturally defined as unpredictable 4728 S = MCDisassembler::SoftFail; 4729 break; 4730 } 4731 4732 if (Inst.getOpcode() == ARM::t2MSR_M) { 4733 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4734 if (!(FeatureBits[ARM::HasV7Ops])) { 4735 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4736 // unpredictable. 4737 if (Mask != 2) 4738 S = MCDisassembler::SoftFail; 4739 } 4740 else { 4741 // The ARMv7-M architecture stores an additional 2-bit mask value in 4742 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4743 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4744 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4745 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4746 // only if the processor includes the DSP extension. 4747 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4748 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4749 S = MCDisassembler::SoftFail; 4750 } 4751 } 4752 } else { 4753 // A/R class 4754 if (Val == 0) 4755 return MCDisassembler::Fail; 4756 } 4757 Inst.addOperand(MCOperand::createImm(Val)); 4758 return S; 4759 } 4760 4761 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4762 uint64_t Address, const void *Decoder) { 4763 unsigned R = fieldFromInstruction(Val, 5, 1); 4764 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4765 4766 // The table of encodings for these banked registers comes from B9.2.3 of the 4767 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4768 // neater. So by fiat, these values are UNPREDICTABLE: 4769 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4770 return MCDisassembler::Fail; 4771 4772 Inst.addOperand(MCOperand::createImm(Val)); 4773 return MCDisassembler::Success; 4774 } 4775 4776 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4777 uint64_t Address, const void *Decoder) { 4778 DecodeStatus S = MCDisassembler::Success; 4779 4780 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4781 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4782 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4783 4784 if (Rn == 0xF) 4785 S = MCDisassembler::SoftFail; 4786 4787 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4788 return MCDisassembler::Fail; 4789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4790 return MCDisassembler::Fail; 4791 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4792 return MCDisassembler::Fail; 4793 4794 return S; 4795 } 4796 4797 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4798 uint64_t Address, 4799 const void *Decoder) { 4800 DecodeStatus S = MCDisassembler::Success; 4801 4802 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4803 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4804 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4805 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4806 4807 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4808 return MCDisassembler::Fail; 4809 4810 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4811 S = MCDisassembler::SoftFail; 4812 4813 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4814 return MCDisassembler::Fail; 4815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4816 return MCDisassembler::Fail; 4817 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4818 return MCDisassembler::Fail; 4819 4820 return S; 4821 } 4822 4823 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4824 uint64_t Address, const void *Decoder) { 4825 DecodeStatus S = MCDisassembler::Success; 4826 4827 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4828 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4829 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4830 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4831 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4832 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4833 4834 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4835 4836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4837 return MCDisassembler::Fail; 4838 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4839 return MCDisassembler::Fail; 4840 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4841 return MCDisassembler::Fail; 4842 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4843 return MCDisassembler::Fail; 4844 4845 return S; 4846 } 4847 4848 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4849 uint64_t Address, const void *Decoder) { 4850 DecodeStatus S = MCDisassembler::Success; 4851 4852 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4853 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4854 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4855 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4856 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4857 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4858 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4859 4860 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4861 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4862 4863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4864 return MCDisassembler::Fail; 4865 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4866 return MCDisassembler::Fail; 4867 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4868 return MCDisassembler::Fail; 4869 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4870 return MCDisassembler::Fail; 4871 4872 return S; 4873 } 4874 4875 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4876 uint64_t Address, const void *Decoder) { 4877 DecodeStatus S = MCDisassembler::Success; 4878 4879 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4880 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4881 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4882 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4883 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4884 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4885 4886 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4887 4888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4889 return MCDisassembler::Fail; 4890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4891 return MCDisassembler::Fail; 4892 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4893 return MCDisassembler::Fail; 4894 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4895 return MCDisassembler::Fail; 4896 4897 return S; 4898 } 4899 4900 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4901 uint64_t Address, const void *Decoder) { 4902 DecodeStatus S = MCDisassembler::Success; 4903 4904 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4905 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4906 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4907 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4908 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4909 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4910 4911 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4912 4913 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4914 return MCDisassembler::Fail; 4915 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4916 return MCDisassembler::Fail; 4917 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4918 return MCDisassembler::Fail; 4919 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4920 return MCDisassembler::Fail; 4921 4922 return S; 4923 } 4924 4925 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4926 uint64_t Address, const void *Decoder) { 4927 DecodeStatus S = MCDisassembler::Success; 4928 4929 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4930 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4931 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4932 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4933 unsigned size = fieldFromInstruction(Insn, 10, 2); 4934 4935 unsigned align = 0; 4936 unsigned index = 0; 4937 switch (size) { 4938 default: 4939 return MCDisassembler::Fail; 4940 case 0: 4941 if (fieldFromInstruction(Insn, 4, 1)) 4942 return MCDisassembler::Fail; // UNDEFINED 4943 index = fieldFromInstruction(Insn, 5, 3); 4944 break; 4945 case 1: 4946 if (fieldFromInstruction(Insn, 5, 1)) 4947 return MCDisassembler::Fail; // UNDEFINED 4948 index = fieldFromInstruction(Insn, 6, 2); 4949 if (fieldFromInstruction(Insn, 4, 1)) 4950 align = 2; 4951 break; 4952 case 2: 4953 if (fieldFromInstruction(Insn, 6, 1)) 4954 return MCDisassembler::Fail; // UNDEFINED 4955 index = fieldFromInstruction(Insn, 7, 1); 4956 4957 switch (fieldFromInstruction(Insn, 4, 2)) { 4958 case 0 : 4959 align = 0; break; 4960 case 3: 4961 align = 4; break; 4962 default: 4963 return MCDisassembler::Fail; 4964 } 4965 break; 4966 } 4967 4968 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4969 return MCDisassembler::Fail; 4970 if (Rm != 0xF) { // Writeback 4971 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4972 return MCDisassembler::Fail; 4973 } 4974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4975 return MCDisassembler::Fail; 4976 Inst.addOperand(MCOperand::createImm(align)); 4977 if (Rm != 0xF) { 4978 if (Rm != 0xD) { 4979 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4980 return MCDisassembler::Fail; 4981 } else 4982 Inst.addOperand(MCOperand::createReg(0)); 4983 } 4984 4985 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4986 return MCDisassembler::Fail; 4987 Inst.addOperand(MCOperand::createImm(index)); 4988 4989 return S; 4990 } 4991 4992 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4993 uint64_t Address, const void *Decoder) { 4994 DecodeStatus S = MCDisassembler::Success; 4995 4996 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4997 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4998 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4999 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5000 unsigned size = fieldFromInstruction(Insn, 10, 2); 5001 5002 unsigned align = 0; 5003 unsigned index = 0; 5004 switch (size) { 5005 default: 5006 return MCDisassembler::Fail; 5007 case 0: 5008 if (fieldFromInstruction(Insn, 4, 1)) 5009 return MCDisassembler::Fail; // UNDEFINED 5010 index = fieldFromInstruction(Insn, 5, 3); 5011 break; 5012 case 1: 5013 if (fieldFromInstruction(Insn, 5, 1)) 5014 return MCDisassembler::Fail; // UNDEFINED 5015 index = fieldFromInstruction(Insn, 6, 2); 5016 if (fieldFromInstruction(Insn, 4, 1)) 5017 align = 2; 5018 break; 5019 case 2: 5020 if (fieldFromInstruction(Insn, 6, 1)) 5021 return MCDisassembler::Fail; // UNDEFINED 5022 index = fieldFromInstruction(Insn, 7, 1); 5023 5024 switch (fieldFromInstruction(Insn, 4, 2)) { 5025 case 0: 5026 align = 0; break; 5027 case 3: 5028 align = 4; break; 5029 default: 5030 return MCDisassembler::Fail; 5031 } 5032 break; 5033 } 5034 5035 if (Rm != 0xF) { // Writeback 5036 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5037 return MCDisassembler::Fail; 5038 } 5039 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5040 return MCDisassembler::Fail; 5041 Inst.addOperand(MCOperand::createImm(align)); 5042 if (Rm != 0xF) { 5043 if (Rm != 0xD) { 5044 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5045 return MCDisassembler::Fail; 5046 } else 5047 Inst.addOperand(MCOperand::createReg(0)); 5048 } 5049 5050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5051 return MCDisassembler::Fail; 5052 Inst.addOperand(MCOperand::createImm(index)); 5053 5054 return S; 5055 } 5056 5057 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5058 uint64_t Address, const void *Decoder) { 5059 DecodeStatus S = MCDisassembler::Success; 5060 5061 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5062 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5063 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5064 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5065 unsigned size = fieldFromInstruction(Insn, 10, 2); 5066 5067 unsigned align = 0; 5068 unsigned index = 0; 5069 unsigned inc = 1; 5070 switch (size) { 5071 default: 5072 return MCDisassembler::Fail; 5073 case 0: 5074 index = fieldFromInstruction(Insn, 5, 3); 5075 if (fieldFromInstruction(Insn, 4, 1)) 5076 align = 2; 5077 break; 5078 case 1: 5079 index = fieldFromInstruction(Insn, 6, 2); 5080 if (fieldFromInstruction(Insn, 4, 1)) 5081 align = 4; 5082 if (fieldFromInstruction(Insn, 5, 1)) 5083 inc = 2; 5084 break; 5085 case 2: 5086 if (fieldFromInstruction(Insn, 5, 1)) 5087 return MCDisassembler::Fail; // UNDEFINED 5088 index = fieldFromInstruction(Insn, 7, 1); 5089 if (fieldFromInstruction(Insn, 4, 1) != 0) 5090 align = 8; 5091 if (fieldFromInstruction(Insn, 6, 1)) 5092 inc = 2; 5093 break; 5094 } 5095 5096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5097 return MCDisassembler::Fail; 5098 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5099 return MCDisassembler::Fail; 5100 if (Rm != 0xF) { // Writeback 5101 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5102 return MCDisassembler::Fail; 5103 } 5104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5105 return MCDisassembler::Fail; 5106 Inst.addOperand(MCOperand::createImm(align)); 5107 if (Rm != 0xF) { 5108 if (Rm != 0xD) { 5109 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5110 return MCDisassembler::Fail; 5111 } else 5112 Inst.addOperand(MCOperand::createReg(0)); 5113 } 5114 5115 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5116 return MCDisassembler::Fail; 5117 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5118 return MCDisassembler::Fail; 5119 Inst.addOperand(MCOperand::createImm(index)); 5120 5121 return S; 5122 } 5123 5124 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5125 uint64_t Address, const void *Decoder) { 5126 DecodeStatus S = MCDisassembler::Success; 5127 5128 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5129 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5130 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5131 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5132 unsigned size = fieldFromInstruction(Insn, 10, 2); 5133 5134 unsigned align = 0; 5135 unsigned index = 0; 5136 unsigned inc = 1; 5137 switch (size) { 5138 default: 5139 return MCDisassembler::Fail; 5140 case 0: 5141 index = fieldFromInstruction(Insn, 5, 3); 5142 if (fieldFromInstruction(Insn, 4, 1)) 5143 align = 2; 5144 break; 5145 case 1: 5146 index = fieldFromInstruction(Insn, 6, 2); 5147 if (fieldFromInstruction(Insn, 4, 1)) 5148 align = 4; 5149 if (fieldFromInstruction(Insn, 5, 1)) 5150 inc = 2; 5151 break; 5152 case 2: 5153 if (fieldFromInstruction(Insn, 5, 1)) 5154 return MCDisassembler::Fail; // UNDEFINED 5155 index = fieldFromInstruction(Insn, 7, 1); 5156 if (fieldFromInstruction(Insn, 4, 1) != 0) 5157 align = 8; 5158 if (fieldFromInstruction(Insn, 6, 1)) 5159 inc = 2; 5160 break; 5161 } 5162 5163 if (Rm != 0xF) { // Writeback 5164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5165 return MCDisassembler::Fail; 5166 } 5167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5168 return MCDisassembler::Fail; 5169 Inst.addOperand(MCOperand::createImm(align)); 5170 if (Rm != 0xF) { 5171 if (Rm != 0xD) { 5172 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5173 return MCDisassembler::Fail; 5174 } else 5175 Inst.addOperand(MCOperand::createReg(0)); 5176 } 5177 5178 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5179 return MCDisassembler::Fail; 5180 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5181 return MCDisassembler::Fail; 5182 Inst.addOperand(MCOperand::createImm(index)); 5183 5184 return S; 5185 } 5186 5187 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5188 uint64_t Address, const void *Decoder) { 5189 DecodeStatus S = MCDisassembler::Success; 5190 5191 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5192 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5193 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5194 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5195 unsigned size = fieldFromInstruction(Insn, 10, 2); 5196 5197 unsigned align = 0; 5198 unsigned index = 0; 5199 unsigned inc = 1; 5200 switch (size) { 5201 default: 5202 return MCDisassembler::Fail; 5203 case 0: 5204 if (fieldFromInstruction(Insn, 4, 1)) 5205 return MCDisassembler::Fail; // UNDEFINED 5206 index = fieldFromInstruction(Insn, 5, 3); 5207 break; 5208 case 1: 5209 if (fieldFromInstruction(Insn, 4, 1)) 5210 return MCDisassembler::Fail; // UNDEFINED 5211 index = fieldFromInstruction(Insn, 6, 2); 5212 if (fieldFromInstruction(Insn, 5, 1)) 5213 inc = 2; 5214 break; 5215 case 2: 5216 if (fieldFromInstruction(Insn, 4, 2)) 5217 return MCDisassembler::Fail; // UNDEFINED 5218 index = fieldFromInstruction(Insn, 7, 1); 5219 if (fieldFromInstruction(Insn, 6, 1)) 5220 inc = 2; 5221 break; 5222 } 5223 5224 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5225 return MCDisassembler::Fail; 5226 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5227 return MCDisassembler::Fail; 5228 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5229 return MCDisassembler::Fail; 5230 5231 if (Rm != 0xF) { // Writeback 5232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5233 return MCDisassembler::Fail; 5234 } 5235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5236 return MCDisassembler::Fail; 5237 Inst.addOperand(MCOperand::createImm(align)); 5238 if (Rm != 0xF) { 5239 if (Rm != 0xD) { 5240 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5241 return MCDisassembler::Fail; 5242 } else 5243 Inst.addOperand(MCOperand::createReg(0)); 5244 } 5245 5246 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5247 return MCDisassembler::Fail; 5248 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5249 return MCDisassembler::Fail; 5250 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5251 return MCDisassembler::Fail; 5252 Inst.addOperand(MCOperand::createImm(index)); 5253 5254 return S; 5255 } 5256 5257 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5258 uint64_t Address, const void *Decoder) { 5259 DecodeStatus S = MCDisassembler::Success; 5260 5261 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5262 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5263 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5264 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5265 unsigned size = fieldFromInstruction(Insn, 10, 2); 5266 5267 unsigned align = 0; 5268 unsigned index = 0; 5269 unsigned inc = 1; 5270 switch (size) { 5271 default: 5272 return MCDisassembler::Fail; 5273 case 0: 5274 if (fieldFromInstruction(Insn, 4, 1)) 5275 return MCDisassembler::Fail; // UNDEFINED 5276 index = fieldFromInstruction(Insn, 5, 3); 5277 break; 5278 case 1: 5279 if (fieldFromInstruction(Insn, 4, 1)) 5280 return MCDisassembler::Fail; // UNDEFINED 5281 index = fieldFromInstruction(Insn, 6, 2); 5282 if (fieldFromInstruction(Insn, 5, 1)) 5283 inc = 2; 5284 break; 5285 case 2: 5286 if (fieldFromInstruction(Insn, 4, 2)) 5287 return MCDisassembler::Fail; // UNDEFINED 5288 index = fieldFromInstruction(Insn, 7, 1); 5289 if (fieldFromInstruction(Insn, 6, 1)) 5290 inc = 2; 5291 break; 5292 } 5293 5294 if (Rm != 0xF) { // Writeback 5295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5296 return MCDisassembler::Fail; 5297 } 5298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5299 return MCDisassembler::Fail; 5300 Inst.addOperand(MCOperand::createImm(align)); 5301 if (Rm != 0xF) { 5302 if (Rm != 0xD) { 5303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5304 return MCDisassembler::Fail; 5305 } else 5306 Inst.addOperand(MCOperand::createReg(0)); 5307 } 5308 5309 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5310 return MCDisassembler::Fail; 5311 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5312 return MCDisassembler::Fail; 5313 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5314 return MCDisassembler::Fail; 5315 Inst.addOperand(MCOperand::createImm(index)); 5316 5317 return S; 5318 } 5319 5320 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5321 uint64_t Address, const void *Decoder) { 5322 DecodeStatus S = MCDisassembler::Success; 5323 5324 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5325 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5326 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5327 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5328 unsigned size = fieldFromInstruction(Insn, 10, 2); 5329 5330 unsigned align = 0; 5331 unsigned index = 0; 5332 unsigned inc = 1; 5333 switch (size) { 5334 default: 5335 return MCDisassembler::Fail; 5336 case 0: 5337 if (fieldFromInstruction(Insn, 4, 1)) 5338 align = 4; 5339 index = fieldFromInstruction(Insn, 5, 3); 5340 break; 5341 case 1: 5342 if (fieldFromInstruction(Insn, 4, 1)) 5343 align = 8; 5344 index = fieldFromInstruction(Insn, 6, 2); 5345 if (fieldFromInstruction(Insn, 5, 1)) 5346 inc = 2; 5347 break; 5348 case 2: 5349 switch (fieldFromInstruction(Insn, 4, 2)) { 5350 case 0: 5351 align = 0; break; 5352 case 3: 5353 return MCDisassembler::Fail; 5354 default: 5355 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5356 } 5357 5358 index = fieldFromInstruction(Insn, 7, 1); 5359 if (fieldFromInstruction(Insn, 6, 1)) 5360 inc = 2; 5361 break; 5362 } 5363 5364 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5365 return MCDisassembler::Fail; 5366 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5367 return MCDisassembler::Fail; 5368 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5369 return MCDisassembler::Fail; 5370 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5371 return MCDisassembler::Fail; 5372 5373 if (Rm != 0xF) { // Writeback 5374 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5375 return MCDisassembler::Fail; 5376 } 5377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5378 return MCDisassembler::Fail; 5379 Inst.addOperand(MCOperand::createImm(align)); 5380 if (Rm != 0xF) { 5381 if (Rm != 0xD) { 5382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5383 return MCDisassembler::Fail; 5384 } else 5385 Inst.addOperand(MCOperand::createReg(0)); 5386 } 5387 5388 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5389 return MCDisassembler::Fail; 5390 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5391 return MCDisassembler::Fail; 5392 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5393 return MCDisassembler::Fail; 5394 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5395 return MCDisassembler::Fail; 5396 Inst.addOperand(MCOperand::createImm(index)); 5397 5398 return S; 5399 } 5400 5401 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5402 uint64_t Address, const void *Decoder) { 5403 DecodeStatus S = MCDisassembler::Success; 5404 5405 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5406 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5407 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5408 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5409 unsigned size = fieldFromInstruction(Insn, 10, 2); 5410 5411 unsigned align = 0; 5412 unsigned index = 0; 5413 unsigned inc = 1; 5414 switch (size) { 5415 default: 5416 return MCDisassembler::Fail; 5417 case 0: 5418 if (fieldFromInstruction(Insn, 4, 1)) 5419 align = 4; 5420 index = fieldFromInstruction(Insn, 5, 3); 5421 break; 5422 case 1: 5423 if (fieldFromInstruction(Insn, 4, 1)) 5424 align = 8; 5425 index = fieldFromInstruction(Insn, 6, 2); 5426 if (fieldFromInstruction(Insn, 5, 1)) 5427 inc = 2; 5428 break; 5429 case 2: 5430 switch (fieldFromInstruction(Insn, 4, 2)) { 5431 case 0: 5432 align = 0; break; 5433 case 3: 5434 return MCDisassembler::Fail; 5435 default: 5436 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5437 } 5438 5439 index = fieldFromInstruction(Insn, 7, 1); 5440 if (fieldFromInstruction(Insn, 6, 1)) 5441 inc = 2; 5442 break; 5443 } 5444 5445 if (Rm != 0xF) { // Writeback 5446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5447 return MCDisassembler::Fail; 5448 } 5449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5450 return MCDisassembler::Fail; 5451 Inst.addOperand(MCOperand::createImm(align)); 5452 if (Rm != 0xF) { 5453 if (Rm != 0xD) { 5454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5455 return MCDisassembler::Fail; 5456 } else 5457 Inst.addOperand(MCOperand::createReg(0)); 5458 } 5459 5460 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5461 return MCDisassembler::Fail; 5462 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5463 return MCDisassembler::Fail; 5464 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5465 return MCDisassembler::Fail; 5466 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5467 return MCDisassembler::Fail; 5468 Inst.addOperand(MCOperand::createImm(index)); 5469 5470 return S; 5471 } 5472 5473 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5474 uint64_t Address, const void *Decoder) { 5475 DecodeStatus S = MCDisassembler::Success; 5476 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5477 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5478 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5479 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5480 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5481 5482 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5483 S = MCDisassembler::SoftFail; 5484 5485 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5486 return MCDisassembler::Fail; 5487 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5488 return MCDisassembler::Fail; 5489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5490 return MCDisassembler::Fail; 5491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5492 return MCDisassembler::Fail; 5493 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5494 return MCDisassembler::Fail; 5495 5496 return S; 5497 } 5498 5499 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5500 uint64_t Address, const void *Decoder) { 5501 DecodeStatus S = MCDisassembler::Success; 5502 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5503 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5504 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5505 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5506 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5507 5508 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5509 S = MCDisassembler::SoftFail; 5510 5511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5512 return MCDisassembler::Fail; 5513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5514 return MCDisassembler::Fail; 5515 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5516 return MCDisassembler::Fail; 5517 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5518 return MCDisassembler::Fail; 5519 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5520 return MCDisassembler::Fail; 5521 5522 return S; 5523 } 5524 5525 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5526 uint64_t Address, const void *Decoder) { 5527 DecodeStatus S = MCDisassembler::Success; 5528 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5529 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5530 5531 if (pred == 0xF) { 5532 pred = 0xE; 5533 S = MCDisassembler::SoftFail; 5534 } 5535 5536 if (mask == 0x0) 5537 return MCDisassembler::Fail; 5538 5539 // IT masks are encoded as a sequence of replacement low-order bits 5540 // for the condition code. So if the low bit of the starting 5541 // condition code is 1, then we have to flip all the bits above the 5542 // terminating bit (which is the lowest 1 bit). 5543 if (pred & 1) { 5544 unsigned LowBit = mask & -mask; 5545 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5546 mask ^= BitsAboveLowBit; 5547 } 5548 5549 Inst.addOperand(MCOperand::createImm(pred)); 5550 Inst.addOperand(MCOperand::createImm(mask)); 5551 return S; 5552 } 5553 5554 static DecodeStatus 5555 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5556 uint64_t Address, const void *Decoder) { 5557 DecodeStatus S = MCDisassembler::Success; 5558 5559 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5560 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5561 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5562 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5563 unsigned W = fieldFromInstruction(Insn, 21, 1); 5564 unsigned U = fieldFromInstruction(Insn, 23, 1); 5565 unsigned P = fieldFromInstruction(Insn, 24, 1); 5566 bool writeback = (W == 1) | (P == 0); 5567 5568 addr |= (U << 8) | (Rn << 9); 5569 5570 if (writeback && (Rn == Rt || Rn == Rt2)) 5571 Check(S, MCDisassembler::SoftFail); 5572 if (Rt == Rt2) 5573 Check(S, MCDisassembler::SoftFail); 5574 5575 // Rt 5576 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5577 return MCDisassembler::Fail; 5578 // Rt2 5579 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5580 return MCDisassembler::Fail; 5581 // Writeback operand 5582 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5583 return MCDisassembler::Fail; 5584 // addr 5585 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5586 return MCDisassembler::Fail; 5587 5588 return S; 5589 } 5590 5591 static DecodeStatus 5592 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5593 uint64_t Address, const void *Decoder) { 5594 DecodeStatus S = MCDisassembler::Success; 5595 5596 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5597 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5598 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5599 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5600 unsigned W = fieldFromInstruction(Insn, 21, 1); 5601 unsigned U = fieldFromInstruction(Insn, 23, 1); 5602 unsigned P = fieldFromInstruction(Insn, 24, 1); 5603 bool writeback = (W == 1) | (P == 0); 5604 5605 addr |= (U << 8) | (Rn << 9); 5606 5607 if (writeback && (Rn == Rt || Rn == Rt2)) 5608 Check(S, MCDisassembler::SoftFail); 5609 5610 // Writeback operand 5611 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5612 return MCDisassembler::Fail; 5613 // Rt 5614 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5615 return MCDisassembler::Fail; 5616 // Rt2 5617 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5618 return MCDisassembler::Fail; 5619 // addr 5620 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5621 return MCDisassembler::Fail; 5622 5623 return S; 5624 } 5625 5626 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5627 uint64_t Address, const void *Decoder) { 5628 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5629 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5630 if (sign1 != sign2) return MCDisassembler::Fail; 5631 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5632 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5633 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5634 5635 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5636 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5637 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5638 // If sign, then it is decreasing the address. 5639 if (sign1) { 5640 // Following ARMv7 Architecture Manual, when the offset 5641 // is zero, it is decoded as a subw, not as a adr.w 5642 if (!Val) { 5643 Inst.setOpcode(ARM::t2SUBri12); 5644 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5645 } else 5646 Val = -Val; 5647 } 5648 Inst.addOperand(MCOperand::createImm(Val)); 5649 return S; 5650 } 5651 5652 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5653 uint64_t Address, 5654 const void *Decoder) { 5655 DecodeStatus S = MCDisassembler::Success; 5656 5657 // Shift of "asr #32" is not allowed in Thumb2 mode. 5658 if (Val == 0x20) S = MCDisassembler::Fail; 5659 Inst.addOperand(MCOperand::createImm(Val)); 5660 return S; 5661 } 5662 5663 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5664 uint64_t Address, const void *Decoder) { 5665 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5666 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5667 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5668 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5669 5670 if (pred == 0xF) 5671 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5672 5673 DecodeStatus S = MCDisassembler::Success; 5674 5675 if (Rt == Rn || Rn == Rt2) 5676 S = MCDisassembler::SoftFail; 5677 5678 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5679 return MCDisassembler::Fail; 5680 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5681 return MCDisassembler::Fail; 5682 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5683 return MCDisassembler::Fail; 5684 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5685 return MCDisassembler::Fail; 5686 5687 return S; 5688 } 5689 5690 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5691 uint64_t Address, const void *Decoder) { 5692 const FeatureBitset &featureBits = 5693 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5694 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5695 5696 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5697 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5698 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5699 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5700 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5701 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5702 unsigned op = fieldFromInstruction(Insn, 5, 1); 5703 5704 DecodeStatus S = MCDisassembler::Success; 5705 5706 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5707 if (!(imm & 0x38)) { 5708 if (cmode == 0xF) { 5709 if (op == 1) return MCDisassembler::Fail; 5710 Inst.setOpcode(ARM::VMOVv2f32); 5711 } 5712 if (hasFullFP16) { 5713 if (cmode == 0xE) { 5714 if (op == 1) { 5715 Inst.setOpcode(ARM::VMOVv1i64); 5716 } else { 5717 Inst.setOpcode(ARM::VMOVv8i8); 5718 } 5719 } 5720 if (cmode == 0xD) { 5721 if (op == 1) { 5722 Inst.setOpcode(ARM::VMVNv2i32); 5723 } else { 5724 Inst.setOpcode(ARM::VMOVv2i32); 5725 } 5726 } 5727 if (cmode == 0xC) { 5728 if (op == 1) { 5729 Inst.setOpcode(ARM::VMVNv2i32); 5730 } else { 5731 Inst.setOpcode(ARM::VMOVv2i32); 5732 } 5733 } 5734 } 5735 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5736 } 5737 5738 if (!(imm & 0x20)) return MCDisassembler::Fail; 5739 5740 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5741 return MCDisassembler::Fail; 5742 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5743 return MCDisassembler::Fail; 5744 Inst.addOperand(MCOperand::createImm(64 - imm)); 5745 5746 return S; 5747 } 5748 5749 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5750 uint64_t Address, const void *Decoder) { 5751 const FeatureBitset &featureBits = 5752 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5753 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5754 5755 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5756 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5757 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5758 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5759 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5760 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5761 unsigned op = fieldFromInstruction(Insn, 5, 1); 5762 5763 DecodeStatus S = MCDisassembler::Success; 5764 5765 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5766 if (!(imm & 0x38)) { 5767 if (cmode == 0xF) { 5768 if (op == 1) return MCDisassembler::Fail; 5769 Inst.setOpcode(ARM::VMOVv4f32); 5770 } 5771 if (hasFullFP16) { 5772 if (cmode == 0xE) { 5773 if (op == 1) { 5774 Inst.setOpcode(ARM::VMOVv2i64); 5775 } else { 5776 Inst.setOpcode(ARM::VMOVv16i8); 5777 } 5778 } 5779 if (cmode == 0xD) { 5780 if (op == 1) { 5781 Inst.setOpcode(ARM::VMVNv4i32); 5782 } else { 5783 Inst.setOpcode(ARM::VMOVv4i32); 5784 } 5785 } 5786 if (cmode == 0xC) { 5787 if (op == 1) { 5788 Inst.setOpcode(ARM::VMVNv4i32); 5789 } else { 5790 Inst.setOpcode(ARM::VMOVv4i32); 5791 } 5792 } 5793 } 5794 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5795 } 5796 5797 if (!(imm & 0x20)) return MCDisassembler::Fail; 5798 5799 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5800 return MCDisassembler::Fail; 5801 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5802 return MCDisassembler::Fail; 5803 Inst.addOperand(MCOperand::createImm(64 - imm)); 5804 5805 return S; 5806 } 5807 5808 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5809 unsigned Insn, 5810 uint64_t Address, 5811 const void *Decoder) { 5812 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5813 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5814 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5815 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5816 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5817 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5818 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5819 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5820 5821 DecodeStatus S = MCDisassembler::Success; 5822 5823 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5824 5825 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5826 return MCDisassembler::Fail; 5827 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5828 return MCDisassembler::Fail; 5829 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5830 return MCDisassembler::Fail; 5831 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5832 return MCDisassembler::Fail; 5833 // The lane index does not have any bits in the encoding, because it can only 5834 // be 0. 5835 Inst.addOperand(MCOperand::createImm(0)); 5836 Inst.addOperand(MCOperand::createImm(rotate)); 5837 5838 return S; 5839 } 5840 5841 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5842 uint64_t Address, const void *Decoder) { 5843 DecodeStatus S = MCDisassembler::Success; 5844 5845 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5846 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5847 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5848 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5849 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5850 5851 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5852 S = MCDisassembler::SoftFail; 5853 5854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5855 return MCDisassembler::Fail; 5856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5857 return MCDisassembler::Fail; 5858 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5859 return MCDisassembler::Fail; 5860 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5861 return MCDisassembler::Fail; 5862 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5863 return MCDisassembler::Fail; 5864 5865 return S; 5866 } 5867 5868 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5869 uint64_t Address, const void *Decoder) { 5870 DecodeStatus S = MCDisassembler::Success; 5871 5872 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5873 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5874 unsigned cop = fieldFromInstruction(Val, 8, 4); 5875 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5876 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5877 5878 if ((cop & ~0x1) == 0xa) 5879 return MCDisassembler::Fail; 5880 5881 if (Rt == Rt2) 5882 S = MCDisassembler::SoftFail; 5883 5884 // We have to check if the instruction is MRRC2 5885 // or MCRR2 when constructing the operands for 5886 // Inst. Reason is because MRRC2 stores to two 5887 // registers so it's tablegen desc has has two 5888 // outputs whereas MCRR doesn't store to any 5889 // registers so all of it's operands are listed 5890 // as inputs, therefore the operand order for 5891 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5892 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5893 5894 if (Inst.getOpcode() == ARM::MRRC2) { 5895 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5896 return MCDisassembler::Fail; 5897 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5898 return MCDisassembler::Fail; 5899 } 5900 Inst.addOperand(MCOperand::createImm(cop)); 5901 Inst.addOperand(MCOperand::createImm(opc1)); 5902 if (Inst.getOpcode() == ARM::MCRR2) { 5903 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5904 return MCDisassembler::Fail; 5905 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5906 return MCDisassembler::Fail; 5907 } 5908 Inst.addOperand(MCOperand::createImm(CRm)); 5909 5910 return S; 5911 } 5912 5913 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5914 uint64_t Address, 5915 const void *Decoder) { 5916 const FeatureBitset &featureBits = 5917 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5918 DecodeStatus S = MCDisassembler::Success; 5919 5920 // Add explicit operand for the destination sysreg, for cases where 5921 // we have to model it for code generation purposes. 5922 switch (Inst.getOpcode()) { 5923 case ARM::VMSR_FPSCR_NZCVQC: 5924 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5925 break; 5926 case ARM::VMSR_P0: 5927 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5928 break; 5929 } 5930 5931 if (Inst.getOpcode() != ARM::FMSTAT) { 5932 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5933 5934 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5935 if (Rt == 13 || Rt == 15) 5936 S = MCDisassembler::SoftFail; 5937 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5938 } else 5939 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5940 } 5941 5942 // Add explicit operand for the source sysreg, similarly to above. 5943 switch (Inst.getOpcode()) { 5944 case ARM::VMRS_FPSCR_NZCVQC: 5945 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5946 break; 5947 case ARM::VMRS_P0: 5948 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5949 break; 5950 } 5951 5952 if (featureBits[ARM::ModeThumb]) { 5953 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5954 Inst.addOperand(MCOperand::createReg(0)); 5955 } else { 5956 unsigned pred = fieldFromInstruction(Val, 28, 4); 5957 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5958 return MCDisassembler::Fail; 5959 } 5960 5961 return S; 5962 } 5963 5964 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 5965 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5966 uint64_t Address, 5967 const void *Decoder) { 5968 DecodeStatus S = MCDisassembler::Success; 5969 if (Val == 0 && !zeroPermitted) 5970 S = MCDisassembler::Fail; 5971 5972 uint64_t DecVal; 5973 if (isSigned) 5974 DecVal = SignExtend32<size + 1>(Val << 1); 5975 else 5976 DecVal = (Val << 1); 5977 5978 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5979 Decoder)) 5980 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5981 return S; 5982 } 5983 5984 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5985 uint64_t Address, 5986 const void *Decoder) { 5987 5988 uint64_t LocImm = Inst.getOperand(0).getImm(); 5989 Val = LocImm + (2 << Val); 5990 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5991 Decoder)) 5992 Inst.addOperand(MCOperand::createImm(Val)); 5993 return MCDisassembler::Success; 5994 } 5995 5996 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5997 uint64_t Address, 5998 const void *Decoder) { 5999 if (Val >= ARMCC::AL) // also exclude the non-condition NV 6000 return MCDisassembler::Fail; 6001 Inst.addOperand(MCOperand::createImm(Val)); 6002 return MCDisassembler::Success; 6003 } 6004 6005 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6006 const void *Decoder) { 6007 DecodeStatus S = MCDisassembler::Success; 6008 6009 if (Inst.getOpcode() == ARM::MVE_LCTP) 6010 return S; 6011 6012 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6013 fieldFromInstruction(Insn, 1, 10) << 1; 6014 switch (Inst.getOpcode()) { 6015 case ARM::t2LEUpdate: 6016 case ARM::MVE_LETP: 6017 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6018 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6019 LLVM_FALLTHROUGH; 6020 case ARM::t2LE: 6021 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6022 Inst, Imm, Address, Decoder))) 6023 return MCDisassembler::Fail; 6024 break; 6025 case ARM::t2WLS: 6026 case ARM::MVE_WLSTP_8: 6027 case ARM::MVE_WLSTP_16: 6028 case ARM::MVE_WLSTP_32: 6029 case ARM::MVE_WLSTP_64: 6030 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6031 if (!Check(S, 6032 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6033 Address, Decoder)) || 6034 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6035 Inst, Imm, Address, Decoder))) 6036 return MCDisassembler::Fail; 6037 break; 6038 case ARM::t2DLS: 6039 case ARM::MVE_DLSTP_8: 6040 case ARM::MVE_DLSTP_16: 6041 case ARM::MVE_DLSTP_32: 6042 case ARM::MVE_DLSTP_64: 6043 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6044 if (Rn == 0xF) { 6045 // Enforce all the rest of the instruction bits in LCTP, which 6046 // won't have been reliably checked based on LCTP's own tablegen 6047 // record, because we came to this decode by a roundabout route. 6048 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6049 if ((Insn & ~SBZMask) != CanonicalLCTP) 6050 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6051 if (Insn != CanonicalLCTP) 6052 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6053 6054 Inst.setOpcode(ARM::MVE_LCTP); 6055 } else { 6056 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6057 if (!Check(S, DecoderGPRRegisterClass(Inst, 6058 fieldFromInstruction(Insn, 16, 4), 6059 Address, Decoder))) 6060 return MCDisassembler::Fail; 6061 } 6062 break; 6063 } 6064 return S; 6065 } 6066 6067 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6068 uint64_t Address, 6069 const void *Decoder) { 6070 DecodeStatus S = MCDisassembler::Success; 6071 6072 if (Val == 0) 6073 Val = 32; 6074 6075 Inst.addOperand(MCOperand::createImm(Val)); 6076 6077 return S; 6078 } 6079 6080 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6081 uint64_t Address, const void *Decoder) { 6082 if ((RegNo) + 1 > 11) 6083 return MCDisassembler::Fail; 6084 6085 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6086 Inst.addOperand(MCOperand::createReg(Register)); 6087 return MCDisassembler::Success; 6088 } 6089 6090 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6091 uint64_t Address, const void *Decoder) { 6092 if ((RegNo) > 14) 6093 return MCDisassembler::Fail; 6094 6095 unsigned Register = GPRDecoderTable[(RegNo)]; 6096 Inst.addOperand(MCOperand::createReg(Register)); 6097 return MCDisassembler::Success; 6098 } 6099 6100 static DecodeStatus 6101 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6102 uint64_t Address, const void *Decoder) { 6103 if (RegNo == 15) { 6104 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6105 return MCDisassembler::Success; 6106 } 6107 6108 unsigned Register = GPRDecoderTable[RegNo]; 6109 Inst.addOperand(MCOperand::createReg(Register)); 6110 6111 if (RegNo == 13) 6112 return MCDisassembler::SoftFail; 6113 6114 return MCDisassembler::Success; 6115 } 6116 6117 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6118 const void *Decoder) { 6119 DecodeStatus S = MCDisassembler::Success; 6120 6121 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6122 Inst.addOperand(MCOperand::createReg(0)); 6123 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6124 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6125 (fieldFromInstruction(Insn, 12, 4) << 8) | 6126 (fieldFromInstruction(Insn, 22, 1) << 12); 6127 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6128 return MCDisassembler::Fail; 6129 } 6130 } else { 6131 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6132 (fieldFromInstruction(Insn, 22, 1) << 8) | 6133 (fieldFromInstruction(Insn, 12, 4) << 9); 6134 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6135 return MCDisassembler::Fail; 6136 } 6137 } 6138 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6139 6140 return S; 6141 } 6142 6143 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6144 uint64_t Address, 6145 const void *Decoder) { 6146 if (RegNo > 7) 6147 return MCDisassembler::Fail; 6148 6149 unsigned Register = QPRDecoderTable[RegNo]; 6150 Inst.addOperand(MCOperand::createReg(Register)); 6151 return MCDisassembler::Success; 6152 } 6153 6154 static const uint16_t QQPRDecoderTable[] = { 6155 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6156 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6157 }; 6158 6159 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6160 uint64_t Address, 6161 const void *Decoder) { 6162 if (RegNo > 6) 6163 return MCDisassembler::Fail; 6164 6165 unsigned Register = QQPRDecoderTable[RegNo]; 6166 Inst.addOperand(MCOperand::createReg(Register)); 6167 return MCDisassembler::Success; 6168 } 6169 6170 static const uint16_t QQQQPRDecoderTable[] = { 6171 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6172 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6173 }; 6174 6175 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6176 uint64_t Address, 6177 const void *Decoder) { 6178 if (RegNo > 4) 6179 return MCDisassembler::Fail; 6180 6181 unsigned Register = QQQQPRDecoderTable[RegNo]; 6182 Inst.addOperand(MCOperand::createReg(Register)); 6183 return MCDisassembler::Success; 6184 } 6185 6186 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6187 uint64_t Address, 6188 const void *Decoder) { 6189 DecodeStatus S = MCDisassembler::Success; 6190 6191 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6192 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6193 // 't' as 0 and finish with a 1. 6194 unsigned Imm = 0; 6195 // We always start with a 't'. 6196 unsigned CurBit = 0; 6197 for (int i = 3; i >= 0; --i) { 6198 // If the bit we are looking at is not the same as last one, invert the 6199 // CurBit, if it is the same leave it as is. 6200 CurBit ^= (Val >> i) & 1U; 6201 6202 // Encode the CurBit at the right place in the immediate. 6203 Imm |= (CurBit << i); 6204 6205 // If we are done, finish the encoding with a 1. 6206 if ((Val & ~(~0U << i)) == 0) { 6207 Imm |= 1U << i; 6208 break; 6209 } 6210 } 6211 6212 Inst.addOperand(MCOperand::createImm(Imm)); 6213 6214 return S; 6215 } 6216 6217 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6218 uint64_t Address, const void *Decoder) { 6219 // The vpred_r operand type includes an MQPR register field derived 6220 // from the encoding. But we don't actually want to add an operand 6221 // to the MCInst at this stage, because AddThumbPredicate will do it 6222 // later, and will infer the register number from the TIED_TO 6223 // constraint. So this is a deliberately empty decoder method that 6224 // will inhibit the auto-generated disassembly code from adding an 6225 // operand at all. 6226 return MCDisassembler::Success; 6227 } 6228 6229 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6230 unsigned Val, 6231 uint64_t Address, 6232 const void *Decoder) { 6233 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6234 return MCDisassembler::Success; 6235 } 6236 6237 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6238 unsigned Val, 6239 uint64_t Address, 6240 const void *Decoder) { 6241 unsigned Code; 6242 switch (Val & 0x3) { 6243 case 0: 6244 Code = ARMCC::GE; 6245 break; 6246 case 1: 6247 Code = ARMCC::LT; 6248 break; 6249 case 2: 6250 Code = ARMCC::GT; 6251 break; 6252 case 3: 6253 Code = ARMCC::LE; 6254 break; 6255 } 6256 Inst.addOperand(MCOperand::createImm(Code)); 6257 return MCDisassembler::Success; 6258 } 6259 6260 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6261 unsigned Val, 6262 uint64_t Address, 6263 const void *Decoder) { 6264 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6265 return MCDisassembler::Success; 6266 } 6267 6268 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6269 uint64_t Address, 6270 const void *Decoder) { 6271 unsigned Code; 6272 switch (Val) { 6273 default: 6274 return MCDisassembler::Fail; 6275 case 0: 6276 Code = ARMCC::EQ; 6277 break; 6278 case 1: 6279 Code = ARMCC::NE; 6280 break; 6281 case 4: 6282 Code = ARMCC::GE; 6283 break; 6284 case 5: 6285 Code = ARMCC::LT; 6286 break; 6287 case 6: 6288 Code = ARMCC::GT; 6289 break; 6290 case 7: 6291 Code = ARMCC::LE; 6292 break; 6293 } 6294 6295 Inst.addOperand(MCOperand::createImm(Code)); 6296 return MCDisassembler::Success; 6297 } 6298 6299 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6300 uint64_t Address, const void *Decoder) { 6301 DecodeStatus S = MCDisassembler::Success; 6302 6303 unsigned DecodedVal = 64 - Val; 6304 6305 switch (Inst.getOpcode()) { 6306 case ARM::MVE_VCVTf16s16_fix: 6307 case ARM::MVE_VCVTs16f16_fix: 6308 case ARM::MVE_VCVTf16u16_fix: 6309 case ARM::MVE_VCVTu16f16_fix: 6310 if (DecodedVal > 16) 6311 return MCDisassembler::Fail; 6312 break; 6313 case ARM::MVE_VCVTf32s32_fix: 6314 case ARM::MVE_VCVTs32f32_fix: 6315 case ARM::MVE_VCVTf32u32_fix: 6316 case ARM::MVE_VCVTu32f32_fix: 6317 if (DecodedVal > 32) 6318 return MCDisassembler::Fail; 6319 break; 6320 } 6321 6322 Inst.addOperand(MCOperand::createImm(64 - Val)); 6323 6324 return S; 6325 } 6326 6327 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6328 switch (Opcode) { 6329 case ARM::VSTR_P0_off: 6330 case ARM::VSTR_P0_pre: 6331 case ARM::VSTR_P0_post: 6332 case ARM::VLDR_P0_off: 6333 case ARM::VLDR_P0_pre: 6334 case ARM::VLDR_P0_post: 6335 return ARM::P0; 6336 default: 6337 return 0; 6338 } 6339 } 6340 6341 template<bool Writeback> 6342 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6343 uint64_t Address, 6344 const void *Decoder) { 6345 switch (Inst.getOpcode()) { 6346 case ARM::VSTR_FPSCR_pre: 6347 case ARM::VSTR_FPSCR_NZCVQC_pre: 6348 case ARM::VLDR_FPSCR_pre: 6349 case ARM::VLDR_FPSCR_NZCVQC_pre: 6350 case ARM::VSTR_FPSCR_off: 6351 case ARM::VSTR_FPSCR_NZCVQC_off: 6352 case ARM::VLDR_FPSCR_off: 6353 case ARM::VLDR_FPSCR_NZCVQC_off: 6354 case ARM::VSTR_FPSCR_post: 6355 case ARM::VSTR_FPSCR_NZCVQC_post: 6356 case ARM::VLDR_FPSCR_post: 6357 case ARM::VLDR_FPSCR_NZCVQC_post: 6358 const FeatureBitset &featureBits = 6359 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6360 6361 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6362 return MCDisassembler::Fail; 6363 } 6364 6365 DecodeStatus S = MCDisassembler::Success; 6366 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6367 Inst.addOperand(MCOperand::createReg(Sysreg)); 6368 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6369 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6370 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6371 6372 if (Writeback) { 6373 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6374 return MCDisassembler::Fail; 6375 } 6376 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6377 return MCDisassembler::Fail; 6378 6379 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6380 Inst.addOperand(MCOperand::createReg(0)); 6381 6382 return S; 6383 } 6384 6385 static inline DecodeStatus DecodeMVE_MEM_pre( 6386 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6387 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6388 DecodeStatus S = MCDisassembler::Success; 6389 6390 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6391 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6392 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6393 6394 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6395 return MCDisassembler::Fail; 6396 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6397 return MCDisassembler::Fail; 6398 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6399 return MCDisassembler::Fail; 6400 6401 return S; 6402 } 6403 6404 template <int shift> 6405 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6406 uint64_t Address, const void *Decoder) { 6407 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6408 fieldFromInstruction(Val, 16, 3), 6409 DecodetGPRRegisterClass, 6410 DecodeTAddrModeImm7<shift>); 6411 } 6412 6413 template <int shift> 6414 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6415 uint64_t Address, const void *Decoder) { 6416 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6417 fieldFromInstruction(Val, 16, 4), 6418 DecoderGPRRegisterClass, 6419 DecodeT2AddrModeImm7<shift,1>); 6420 } 6421 6422 template <int shift> 6423 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6424 uint64_t Address, const void *Decoder) { 6425 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6426 fieldFromInstruction(Val, 17, 3), 6427 DecodeMQPRRegisterClass, 6428 DecodeMveAddrModeQ<shift>); 6429 } 6430 6431 template<unsigned MinLog, unsigned MaxLog> 6432 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6433 uint64_t Address, 6434 const void *Decoder) { 6435 DecodeStatus S = MCDisassembler::Success; 6436 6437 if (Val < MinLog || Val > MaxLog) 6438 return MCDisassembler::Fail; 6439 6440 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6441 return S; 6442 } 6443 6444 template<unsigned start> 6445 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6446 uint64_t Address, 6447 const void *Decoder) { 6448 DecodeStatus S = MCDisassembler::Success; 6449 6450 Inst.addOperand(MCOperand::createImm(start + Val)); 6451 6452 return S; 6453 } 6454 6455 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6456 uint64_t Address, const void *Decoder) { 6457 DecodeStatus S = MCDisassembler::Success; 6458 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6459 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6460 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6461 fieldFromInstruction(Insn, 13, 3)); 6462 unsigned index = fieldFromInstruction(Insn, 4, 1); 6463 6464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6465 return MCDisassembler::Fail; 6466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6467 return MCDisassembler::Fail; 6468 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6469 return MCDisassembler::Fail; 6470 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6471 return MCDisassembler::Fail; 6472 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6473 return MCDisassembler::Fail; 6474 6475 return S; 6476 } 6477 6478 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6479 uint64_t Address, const void *Decoder) { 6480 DecodeStatus S = MCDisassembler::Success; 6481 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6482 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6483 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6484 fieldFromInstruction(Insn, 13, 3)); 6485 unsigned index = fieldFromInstruction(Insn, 4, 1); 6486 6487 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6488 return MCDisassembler::Fail; 6489 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6490 return MCDisassembler::Fail; 6491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6492 return MCDisassembler::Fail; 6493 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6494 return MCDisassembler::Fail; 6495 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6496 return MCDisassembler::Fail; 6497 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6498 return MCDisassembler::Fail; 6499 6500 return S; 6501 } 6502 6503 static DecodeStatus DecodeMVEOverlappingLongShift( 6504 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6505 DecodeStatus S = MCDisassembler::Success; 6506 6507 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6508 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6509 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6510 6511 if (RdaHi == 14) { 6512 // This value of RdaHi (really indicating pc, because RdaHi has to 6513 // be an odd-numbered register, so the low bit will be set by the 6514 // decode function below) indicates that we must decode as SQRSHR 6515 // or UQRSHL, which both have a single Rda register field with all 6516 // four bits. 6517 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6518 6519 switch (Inst.getOpcode()) { 6520 case ARM::MVE_ASRLr: 6521 case ARM::MVE_SQRSHRL: 6522 Inst.setOpcode(ARM::MVE_SQRSHR); 6523 break; 6524 case ARM::MVE_LSLLr: 6525 case ARM::MVE_UQRSHLL: 6526 Inst.setOpcode(ARM::MVE_UQRSHL); 6527 break; 6528 default: 6529 llvm_unreachable("Unexpected starting opcode!"); 6530 } 6531 6532 // Rda as output parameter 6533 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6534 return MCDisassembler::Fail; 6535 6536 // Rda again as input parameter 6537 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6538 return MCDisassembler::Fail; 6539 6540 // Rm, the amount to shift by 6541 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6542 return MCDisassembler::Fail; 6543 6544 if (fieldFromInstruction (Insn, 6, 3) != 4) 6545 return MCDisassembler::SoftFail; 6546 6547 if (Rda == Rm) 6548 return MCDisassembler::SoftFail; 6549 6550 return S; 6551 } 6552 6553 // Otherwise, we decode as whichever opcode our caller has already 6554 // put into Inst. Those all look the same: 6555 6556 // RdaLo,RdaHi as output parameters 6557 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6558 return MCDisassembler::Fail; 6559 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6560 return MCDisassembler::Fail; 6561 6562 // RdaLo,RdaHi again as input parameters 6563 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6564 return MCDisassembler::Fail; 6565 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6566 return MCDisassembler::Fail; 6567 6568 // Rm, the amount to shift by 6569 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6570 return MCDisassembler::Fail; 6571 6572 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6573 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6574 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6575 // Saturate, the bit position for saturation 6576 Inst.addOperand(MCOperand::createImm(Saturate)); 6577 } 6578 6579 return S; 6580 } 6581 6582 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6583 const void *Decoder) { 6584 DecodeStatus S = MCDisassembler::Success; 6585 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6586 fieldFromInstruction(Insn, 13, 3)); 6587 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6588 fieldFromInstruction(Insn, 1, 3)); 6589 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6590 6591 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6592 return MCDisassembler::Fail; 6593 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6594 return MCDisassembler::Fail; 6595 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6596 return MCDisassembler::Fail; 6597 6598 return S; 6599 } 6600 6601 template<bool scalar, OperandDecoder predicate_decoder> 6602 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6603 const void *Decoder) { 6604 DecodeStatus S = MCDisassembler::Success; 6605 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6606 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6607 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6608 return MCDisassembler::Fail; 6609 6610 unsigned fc; 6611 6612 if (scalar) { 6613 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6614 fieldFromInstruction(Insn, 7, 1) | 6615 fieldFromInstruction(Insn, 5, 1) << 1; 6616 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6617 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6618 return MCDisassembler::Fail; 6619 } else { 6620 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6621 fieldFromInstruction(Insn, 7, 1) | 6622 fieldFromInstruction(Insn, 0, 1) << 1; 6623 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6624 fieldFromInstruction(Insn, 1, 3); 6625 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6626 return MCDisassembler::Fail; 6627 } 6628 6629 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6630 return MCDisassembler::Fail; 6631 6632 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6633 Inst.addOperand(MCOperand::createReg(0)); 6634 Inst.addOperand(MCOperand::createImm(0)); 6635 6636 return S; 6637 } 6638 6639 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6640 const void *Decoder) { 6641 DecodeStatus S = MCDisassembler::Success; 6642 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6643 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6644 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6645 return MCDisassembler::Fail; 6646 return S; 6647 } 6648 6649 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6650 const void *Decoder) { 6651 DecodeStatus S = MCDisassembler::Success; 6652 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6653 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6654 return S; 6655 } 6656 6657 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6658 uint64_t Address, const void *Decoder) { 6659 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6660 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6661 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6662 fieldFromInstruction(Insn, 12, 3) << 8 | 6663 fieldFromInstruction(Insn, 0, 8); 6664 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6665 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6666 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 6667 unsigned S = fieldFromInstruction(Insn, 20, 1); 6668 if (sign1 != sign2) 6669 return MCDisassembler::Fail; 6670 6671 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 6672 DecodeStatus DS = MCDisassembler::Success; 6673 if ((!Check(DS, 6674 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 6675 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 6676 return MCDisassembler::Fail; 6677 if (TypeT3) { 6678 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 6679 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 6680 } else { 6681 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 6682 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 6683 return MCDisassembler::Fail; 6684 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 6685 return MCDisassembler::Fail; 6686 } 6687 6688 return DS; 6689 } 6690