1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 137 uint64_t Address, const void *Decoder); 138 static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 139 uint64_t Address, const void *Decoder); 140 static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 145 uint64_t Address, const void *Decoder); 146 static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 147 uint64_t Address, const void *Decoder); 148 static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 161 162 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 163 uint64_t Address, const void *Decoder); 164 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 167 uint64_t Address, const void *Decoder); 168 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 169 uint64_t Address, const void *Decoder); 170 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 171 uint64_t Address, const void *Decoder); 172 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 173 uint64_t Address, const void *Decoder); 174 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 191 uint64_t Address, const void *Decoder); 192 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 193 uint64_t Address, const void *Decoder); 194 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 195 uint64_t Address, const void *Decoder); 196 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 211 #include "ARMGenDisassemblerTables.inc" 212 #include "ARMGenInstrInfo.inc" 213 #include "ARMGenEDInfo.inc" 214 215 using namespace llvm; 216 217 static MCDisassembler *createARMDisassembler(const Target &T) { 218 return new ARMDisassembler; 219 } 220 221 static MCDisassembler *createThumbDisassembler(const Target &T) { 222 return new ThumbDisassembler; 223 } 224 225 EDInstInfo *ARMDisassembler::getEDInfo() const { 226 return instInfoARM; 227 } 228 229 EDInstInfo *ThumbDisassembler::getEDInfo() const { 230 return instInfoARM; 231 } 232 233 234 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 235 const MemoryObject &Region, 236 uint64_t Address,raw_ostream &os) const { 237 uint8_t bytes[4]; 238 239 // We want to read exactly 4 bytes of data. 240 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 241 return false; 242 243 // Encoded as a small-endian 32-bit word in the stream. 244 uint32_t insn = (bytes[3] << 24) | 245 (bytes[2] << 16) | 246 (bytes[1] << 8) | 247 (bytes[0] << 0); 248 249 // Calling the auto-generated decoder function. 250 bool result = decodeARMInstruction32(MI, insn, Address, this); 251 if (result) { 252 Size = 4; 253 return true; 254 } 255 256 // Instructions that are shared between ARM and Thumb modes. 257 // FIXME: This shouldn't really exist. It's an artifact of the 258 // fact that we fail to encode a few instructions properly for Thumb. 259 MI.clear(); 260 result = decodeCommonInstruction32(MI, insn, Address, this); 261 if (result) { 262 Size = 4; 263 return true; 264 } 265 266 // VFP and NEON instructions, similarly, are shared between ARM 267 // and Thumb modes. 268 MI.clear(); 269 result = decodeVFPInstruction32(MI, insn, Address, this); 270 if (result) { 271 Size = 4; 272 return true; 273 } 274 275 MI.clear(); 276 result = decodeNEONDataInstruction32(MI, insn, Address, this); 277 if (result) { 278 Size = 4; 279 // Add a fake predicate operand, because we share these instruction 280 // definitions with Thumb2 where these instructions are predicable. 281 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 282 return true; 283 } 284 285 MI.clear(); 286 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 287 if (result) { 288 Size = 4; 289 // Add a fake predicate operand, because we share these instruction 290 // definitions with Thumb2 where these instructions are predicable. 291 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 292 return true; 293 } 294 295 MI.clear(); 296 result = decodeNEONDupInstruction32(MI, insn, Address, this); 297 if (result) { 298 Size = 4; 299 // Add a fake predicate operand, because we share these instruction 300 // definitions with Thumb2 where these instructions are predicable. 301 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 302 return true; 303 } 304 305 MI.clear(); 306 307 return false; 308 } 309 310 namespace llvm { 311 extern MCInstrDesc ARMInsts[]; 312 } 313 314 // Thumb1 instructions don't have explicit S bits. Rather, they 315 // implicitly set CPSR. Since it's not represented in the encoding, the 316 // auto-generated decoder won't inject the CPSR operand. We need to fix 317 // that as a post-pass. 318 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 319 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 320 MCInst::iterator I = MI.begin(); 321 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 322 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 323 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 324 return; 325 } 326 } 327 328 if (OpInfo[MI.size()].isOptionalDef() && 329 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 330 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 331 } 332 333 // Most Thumb instructions don't have explicit predicates in the 334 // encoding, but rather get their predicates from IT context. We need 335 // to fix up the predicate operands using this context information as a 336 // post-pass. 337 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 338 // A few instructions actually have predicates encoded in them. Don't 339 // try to overwrite it if we're seeing one of those. 340 switch (MI.getOpcode()) { 341 case ARM::tBcc: 342 case ARM::t2Bcc: 343 return; 344 default: 345 break; 346 } 347 348 // If we're in an IT block, base the predicate on that. Otherwise, 349 // assume a predicate of AL. 350 unsigned CC; 351 if (!ITBlock.empty()) { 352 CC = ITBlock.back(); 353 ITBlock.pop_back(); 354 } else 355 CC = ARMCC::AL; 356 357 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 358 MCInst::iterator I = MI.begin(); 359 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 360 if (OpInfo[i].isPredicate()) { 361 I = MI.insert(I, MCOperand::CreateImm(CC)); 362 ++I; 363 if (CC == ARMCC::AL) 364 MI.insert(I, MCOperand::CreateReg(0)); 365 else 366 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 367 return; 368 } 369 } 370 371 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 372 if (CC == ARMCC::AL) 373 MI.insert(MI.end(), MCOperand::CreateReg(0)); 374 else 375 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 376 } 377 378 // Thumb VFP instructions are a special case. Because we share their 379 // encodings between ARM and Thumb modes, and they are predicable in ARM 380 // mode, the auto-generated decoder will give them an (incorrect) 381 // predicate operand. We need to rewrite these operands based on the IT 382 // context as a post-pass. 383 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 384 unsigned CC; 385 if (!ITBlock.empty()) { 386 CC = ITBlock.back(); 387 ITBlock.pop_back(); 388 } else 389 CC = ARMCC::AL; 390 391 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 392 MCInst::iterator I = MI.begin(); 393 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 394 if (OpInfo[i].isPredicate() ) { 395 I->setImm(CC); 396 ++I; 397 if (CC == ARMCC::AL) 398 I->setReg(0); 399 else 400 I->setReg(ARM::CPSR); 401 return; 402 } 403 } 404 } 405 406 407 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 408 const MemoryObject &Region, 409 uint64_t Address,raw_ostream &os) const { 410 uint8_t bytes[4]; 411 412 // We want to read exactly 2 bytes of data. 413 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 414 return false; 415 416 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 417 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 418 if (result) { 419 Size = 2; 420 AddThumbPredicate(MI); 421 return true; 422 } 423 424 MI.clear(); 425 result = decodeThumbSBitInstruction16(MI, insn16, Address, this); 426 if (result) { 427 Size = 2; 428 bool InITBlock = !ITBlock.empty(); 429 AddThumbPredicate(MI); 430 AddThumb1SBit(MI, InITBlock); 431 return true; 432 } 433 434 MI.clear(); 435 result = decodeThumb2Instruction16(MI, insn16, Address, this); 436 if (result) { 437 Size = 2; 438 AddThumbPredicate(MI); 439 440 // If we find an IT instruction, we need to parse its condition 441 // code and mask operands so that we can apply them correctly 442 // to the subsequent instructions. 443 if (MI.getOpcode() == ARM::t2IT) { 444 unsigned firstcond = MI.getOperand(0).getImm(); 445 uint32_t mask = MI.getOperand(1).getImm(); 446 unsigned zeros = CountTrailingZeros_32(mask); 447 mask >>= zeros+1; 448 449 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 450 if (firstcond ^ (mask & 1)) 451 ITBlock.push_back(firstcond ^ 1); 452 else 453 ITBlock.push_back(firstcond); 454 mask >>= 1; 455 } 456 ITBlock.push_back(firstcond); 457 } 458 459 return true; 460 } 461 462 // We want to read exactly 4 bytes of data. 463 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 464 return false; 465 466 uint32_t insn32 = (bytes[3] << 8) | 467 (bytes[2] << 0) | 468 (bytes[1] << 24) | 469 (bytes[0] << 16); 470 MI.clear(); 471 result = decodeThumbInstruction32(MI, insn32, Address, this); 472 if (result) { 473 Size = 4; 474 bool InITBlock = ITBlock.size(); 475 AddThumbPredicate(MI); 476 AddThumb1SBit(MI, InITBlock); 477 return true; 478 } 479 480 MI.clear(); 481 result = decodeThumb2Instruction32(MI, insn32, Address, this); 482 if (result) { 483 Size = 4; 484 AddThumbPredicate(MI); 485 return true; 486 } 487 488 MI.clear(); 489 result = decodeCommonInstruction32(MI, insn32, Address, this); 490 if (result) { 491 Size = 4; 492 AddThumbPredicate(MI); 493 return true; 494 } 495 496 MI.clear(); 497 result = decodeVFPInstruction32(MI, insn32, Address, this); 498 if (result) { 499 Size = 4; 500 UpdateThumbVFPPredicate(MI); 501 return true; 502 } 503 504 MI.clear(); 505 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 506 if (result) { 507 Size = 4; 508 AddThumbPredicate(MI); 509 return true; 510 } 511 512 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 513 MI.clear(); 514 uint32_t NEONLdStInsn = insn32; 515 NEONLdStInsn &= 0xF0FFFFFF; 516 NEONLdStInsn |= 0x04000000; 517 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 518 if (result) { 519 Size = 4; 520 AddThumbPredicate(MI); 521 return true; 522 } 523 } 524 525 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 526 MI.clear(); 527 uint32_t NEONDataInsn = insn32; 528 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 529 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 530 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 531 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 532 if (result) { 533 Size = 4; 534 AddThumbPredicate(MI); 535 return true; 536 } 537 } 538 539 return false; 540 } 541 542 543 extern "C" void LLVMInitializeARMDisassembler() { 544 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 545 createARMDisassembler); 546 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 547 createThumbDisassembler); 548 } 549 550 static const unsigned GPRDecoderTable[] = { 551 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 552 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 553 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 554 ARM::R12, ARM::SP, ARM::LR, ARM::PC 555 }; 556 557 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 558 uint64_t Address, const void *Decoder) { 559 if (RegNo > 15) 560 return false; 561 562 unsigned Register = GPRDecoderTable[RegNo]; 563 Inst.addOperand(MCOperand::CreateReg(Register)); 564 return true; 565 } 566 567 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 568 uint64_t Address, const void *Decoder) { 569 if (RegNo == 15) return false; 570 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 571 } 572 573 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 574 uint64_t Address, const void *Decoder) { 575 if (RegNo > 7) 576 return false; 577 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 578 } 579 580 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 581 uint64_t Address, const void *Decoder) { 582 unsigned Register = 0; 583 switch (RegNo) { 584 case 0: 585 Register = ARM::R0; 586 break; 587 case 1: 588 Register = ARM::R1; 589 break; 590 case 2: 591 Register = ARM::R2; 592 break; 593 case 3: 594 Register = ARM::R3; 595 break; 596 case 9: 597 Register = ARM::R9; 598 break; 599 case 12: 600 Register = ARM::R12; 601 break; 602 default: 603 return false; 604 } 605 606 Inst.addOperand(MCOperand::CreateReg(Register)); 607 return true; 608 } 609 610 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 611 uint64_t Address, const void *Decoder) { 612 if (RegNo == 13 || RegNo == 15) return false; 613 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 614 } 615 616 static const unsigned SPRDecoderTable[] = { 617 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 618 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 619 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 620 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 621 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 622 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 623 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 624 ARM::S28, ARM::S29, ARM::S30, ARM::S31 625 }; 626 627 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 628 uint64_t Address, const void *Decoder) { 629 if (RegNo > 31) 630 return false; 631 632 unsigned Register = SPRDecoderTable[RegNo]; 633 Inst.addOperand(MCOperand::CreateReg(Register)); 634 return true; 635 } 636 637 static const unsigned DPRDecoderTable[] = { 638 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 639 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 640 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 641 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 642 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 643 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 644 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 645 ARM::D28, ARM::D29, ARM::D30, ARM::D31 646 }; 647 648 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 649 uint64_t Address, const void *Decoder) { 650 if (RegNo > 31) 651 return false; 652 653 unsigned Register = DPRDecoderTable[RegNo]; 654 Inst.addOperand(MCOperand::CreateReg(Register)); 655 return true; 656 } 657 658 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 659 uint64_t Address, const void *Decoder) { 660 if (RegNo > 7) 661 return false; 662 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 663 } 664 665 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 666 uint64_t Address, const void *Decoder) { 667 if (RegNo > 15) 668 return false; 669 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 670 } 671 672 static const unsigned QPRDecoderTable[] = { 673 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 674 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 675 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 676 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 677 }; 678 679 680 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 681 uint64_t Address, const void *Decoder) { 682 if (RegNo > 31) 683 return false; 684 RegNo >>= 1; 685 686 unsigned Register = QPRDecoderTable[RegNo]; 687 Inst.addOperand(MCOperand::CreateReg(Register)); 688 return true; 689 } 690 691 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 692 uint64_t Address, const void *Decoder) { 693 if (Val == 0xF) return false; 694 // AL predicate is not allowed on Thumb1 branches. 695 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 696 return false; 697 Inst.addOperand(MCOperand::CreateImm(Val)); 698 if (Val == ARMCC::AL) { 699 Inst.addOperand(MCOperand::CreateReg(0)); 700 } else 701 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 702 return true; 703 } 704 705 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 706 uint64_t Address, const void *Decoder) { 707 if (Val) 708 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 709 else 710 Inst.addOperand(MCOperand::CreateReg(0)); 711 return true; 712 } 713 714 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 715 uint64_t Address, const void *Decoder) { 716 uint32_t imm = Val & 0xFF; 717 uint32_t rot = (Val & 0xF00) >> 7; 718 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 719 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 720 return true; 721 } 722 723 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 724 uint64_t Address, const void *Decoder) { 725 Val <<= 2; 726 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 727 return true; 728 } 729 730 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 731 uint64_t Address, const void *Decoder) { 732 733 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 734 unsigned type = fieldFromInstruction32(Val, 5, 2); 735 unsigned imm = fieldFromInstruction32(Val, 7, 5); 736 737 // Register-immediate 738 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 739 740 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 741 switch (type) { 742 case 0: 743 Shift = ARM_AM::lsl; 744 break; 745 case 1: 746 Shift = ARM_AM::lsr; 747 break; 748 case 2: 749 Shift = ARM_AM::asr; 750 break; 751 case 3: 752 Shift = ARM_AM::ror; 753 break; 754 } 755 756 if (Shift == ARM_AM::ror && imm == 0) 757 Shift = ARM_AM::rrx; 758 759 unsigned Op = Shift | (imm << 3); 760 Inst.addOperand(MCOperand::CreateImm(Op)); 761 762 return true; 763 } 764 765 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 766 uint64_t Address, const void *Decoder) { 767 768 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 769 unsigned type = fieldFromInstruction32(Val, 5, 2); 770 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 771 772 // Register-register 773 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 774 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 775 776 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 777 switch (type) { 778 case 0: 779 Shift = ARM_AM::lsl; 780 break; 781 case 1: 782 Shift = ARM_AM::lsr; 783 break; 784 case 2: 785 Shift = ARM_AM::asr; 786 break; 787 case 3: 788 Shift = ARM_AM::ror; 789 break; 790 } 791 792 Inst.addOperand(MCOperand::CreateImm(Shift)); 793 794 return true; 795 } 796 797 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 798 uint64_t Address, const void *Decoder) { 799 // Empty register lists are not allowed. 800 if (CountPopulation_32(Val) == 0) return false; 801 for (unsigned i = 0; i < 16; ++i) { 802 if (Val & (1 << i)) { 803 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 804 } 805 } 806 807 return true; 808 } 809 810 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 811 uint64_t Address, const void *Decoder) { 812 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 813 unsigned regs = Val & 0xFF; 814 815 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 816 for (unsigned i = 0; i < (regs - 1); ++i) { 817 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 818 } 819 820 return true; 821 } 822 823 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 824 uint64_t Address, const void *Decoder) { 825 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 826 unsigned regs = (Val & 0xFF) / 2; 827 828 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 829 for (unsigned i = 0; i < (regs - 1); ++i) { 830 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 831 } 832 833 return true; 834 } 835 836 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 837 uint64_t Address, const void *Decoder) { 838 // This operand encodes a mask of contiguous zeros between a specified MSB 839 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 840 // the mask of all bits LSB-and-lower, and then xor them to create 841 // the mask of that's all ones on [msb, lsb]. Finally we not it to 842 // create the final mask. 843 unsigned msb = fieldFromInstruction32(Val, 5, 5); 844 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 845 uint32_t msb_mask = (1 << (msb+1)) - 1; 846 uint32_t lsb_mask = (1 << lsb) - 1; 847 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 848 return true; 849 } 850 851 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 852 uint64_t Address, const void *Decoder) { 853 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 854 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 855 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 856 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 857 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 858 unsigned U = fieldFromInstruction32(Insn, 23, 1); 859 860 switch (Inst.getOpcode()) { 861 case ARM::LDC_OFFSET: 862 case ARM::LDC_PRE: 863 case ARM::LDC_POST: 864 case ARM::LDC_OPTION: 865 case ARM::LDCL_OFFSET: 866 case ARM::LDCL_PRE: 867 case ARM::LDCL_POST: 868 case ARM::LDCL_OPTION: 869 case ARM::STC_OFFSET: 870 case ARM::STC_PRE: 871 case ARM::STC_POST: 872 case ARM::STC_OPTION: 873 case ARM::STCL_OFFSET: 874 case ARM::STCL_PRE: 875 case ARM::STCL_POST: 876 case ARM::STCL_OPTION: 877 if (coproc == 0xA || coproc == 0xB) 878 return false; 879 break; 880 default: 881 break; 882 } 883 884 Inst.addOperand(MCOperand::CreateImm(coproc)); 885 Inst.addOperand(MCOperand::CreateImm(CRd)); 886 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 887 switch (Inst.getOpcode()) { 888 case ARM::LDC_OPTION: 889 case ARM::LDCL_OPTION: 890 case ARM::LDC2_OPTION: 891 case ARM::LDC2L_OPTION: 892 case ARM::STC_OPTION: 893 case ARM::STCL_OPTION: 894 case ARM::STC2_OPTION: 895 case ARM::STC2L_OPTION: 896 case ARM::LDCL_POST: 897 case ARM::STCL_POST: 898 break; 899 default: 900 Inst.addOperand(MCOperand::CreateReg(0)); 901 break; 902 } 903 904 unsigned P = fieldFromInstruction32(Insn, 24, 1); 905 unsigned W = fieldFromInstruction32(Insn, 21, 1); 906 907 bool writeback = (P == 0) || (W == 1); 908 unsigned idx_mode = 0; 909 if (P && writeback) 910 idx_mode = ARMII::IndexModePre; 911 else if (!P && writeback) 912 idx_mode = ARMII::IndexModePost; 913 914 switch (Inst.getOpcode()) { 915 case ARM::LDCL_POST: 916 case ARM::STCL_POST: 917 imm |= U << 8; 918 case ARM::LDC_OPTION: 919 case ARM::LDCL_OPTION: 920 case ARM::LDC2_OPTION: 921 case ARM::LDC2L_OPTION: 922 case ARM::STC_OPTION: 923 case ARM::STCL_OPTION: 924 case ARM::STC2_OPTION: 925 case ARM::STC2L_OPTION: 926 Inst.addOperand(MCOperand::CreateImm(imm)); 927 break; 928 default: 929 if (U) 930 Inst.addOperand(MCOperand::CreateImm( 931 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 932 else 933 Inst.addOperand(MCOperand::CreateImm( 934 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 935 break; 936 } 937 938 switch (Inst.getOpcode()) { 939 case ARM::LDC_OFFSET: 940 case ARM::LDC_PRE: 941 case ARM::LDC_POST: 942 case ARM::LDC_OPTION: 943 case ARM::LDCL_OFFSET: 944 case ARM::LDCL_PRE: 945 case ARM::LDCL_POST: 946 case ARM::LDCL_OPTION: 947 case ARM::STC_OFFSET: 948 case ARM::STC_PRE: 949 case ARM::STC_POST: 950 case ARM::STC_OPTION: 951 case ARM::STCL_OFFSET: 952 case ARM::STCL_PRE: 953 case ARM::STCL_POST: 954 case ARM::STCL_OPTION: 955 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 956 break; 957 default: 958 break; 959 } 960 961 return true; 962 } 963 964 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 965 uint64_t Address, const void *Decoder) { 966 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 967 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 968 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 969 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 970 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 971 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 972 unsigned P = fieldFromInstruction32(Insn, 24, 1); 973 unsigned W = fieldFromInstruction32(Insn, 21, 1); 974 975 // On stores, the writeback operand precedes Rt. 976 switch (Inst.getOpcode()) { 977 case ARM::STR_POST_IMM: 978 case ARM::STR_POST_REG: 979 case ARM::STRB_POST_IMM: 980 case ARM::STRB_POST_REG: 981 case ARM::STRT_POST_REG: 982 case ARM::STRT_POST_IMM: 983 case ARM::STRBT_POST_REG: 984 case ARM::STRBT_POST_IMM: 985 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 986 break; 987 default: 988 break; 989 } 990 991 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 992 993 // On loads, the writeback operand comes after Rt. 994 switch (Inst.getOpcode()) { 995 case ARM::LDR_POST_IMM: 996 case ARM::LDR_POST_REG: 997 case ARM::LDRB_POST_IMM: 998 case ARM::LDRB_POST_REG: 999 case ARM::LDR_PRE: 1000 case ARM::LDRB_PRE: 1001 case ARM::LDRBT_POST_REG: 1002 case ARM::LDRBT_POST_IMM: 1003 case ARM::LDRT_POST_REG: 1004 case ARM::LDRT_POST_IMM: 1005 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1006 return false; 1007 break; 1008 default: 1009 break; 1010 } 1011 1012 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1013 1014 ARM_AM::AddrOpc Op = ARM_AM::add; 1015 if (!fieldFromInstruction32(Insn, 23, 1)) 1016 Op = ARM_AM::sub; 1017 1018 bool writeback = (P == 0) || (W == 1); 1019 unsigned idx_mode = 0; 1020 if (P && writeback) 1021 idx_mode = ARMII::IndexModePre; 1022 else if (!P && writeback) 1023 idx_mode = ARMII::IndexModePost; 1024 1025 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE 1026 1027 if (reg) { 1028 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 1029 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1030 switch( fieldFromInstruction32(Insn, 5, 2)) { 1031 case 0: 1032 Opc = ARM_AM::lsl; 1033 break; 1034 case 1: 1035 Opc = ARM_AM::lsr; 1036 break; 1037 case 2: 1038 Opc = ARM_AM::asr; 1039 break; 1040 case 3: 1041 Opc = ARM_AM::ror; 1042 break; 1043 default: 1044 return false; 1045 } 1046 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1047 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1048 1049 Inst.addOperand(MCOperand::CreateImm(imm)); 1050 } else { 1051 Inst.addOperand(MCOperand::CreateReg(0)); 1052 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1053 Inst.addOperand(MCOperand::CreateImm(tmp)); 1054 } 1055 1056 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1057 1058 return true; 1059 } 1060 1061 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1062 uint64_t Address, const void *Decoder) { 1063 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1064 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1065 unsigned type = fieldFromInstruction32(Val, 5, 2); 1066 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1067 unsigned U = fieldFromInstruction32(Val, 12, 1); 1068 1069 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1070 switch (type) { 1071 case 0: 1072 ShOp = ARM_AM::lsl; 1073 break; 1074 case 1: 1075 ShOp = ARM_AM::lsr; 1076 break; 1077 case 2: 1078 ShOp = ARM_AM::asr; 1079 break; 1080 case 3: 1081 ShOp = ARM_AM::ror; 1082 break; 1083 } 1084 1085 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1086 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1087 unsigned shift; 1088 if (U) 1089 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1090 else 1091 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1092 Inst.addOperand(MCOperand::CreateImm(shift)); 1093 1094 return true; 1095 } 1096 1097 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1098 uint64_t Address, const void *Decoder) { 1099 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1100 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1101 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1102 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1103 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1104 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1105 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1106 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1107 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1108 1109 bool writeback = (W == 1) | (P == 0); 1110 1111 // For {LD,ST}RD, Rt must be even, else undefined. 1112 switch (Inst.getOpcode()) { 1113 case ARM::STRD: 1114 case ARM::STRD_PRE: 1115 case ARM::STRD_POST: 1116 case ARM::LDRD: 1117 case ARM::LDRD_PRE: 1118 case ARM::LDRD_POST: 1119 if (Rt & 0x1) return false; 1120 break; 1121 default: 1122 break; 1123 } 1124 1125 if (writeback) { // Writeback 1126 if (P) 1127 U |= ARMII::IndexModePre << 9; 1128 else 1129 U |= ARMII::IndexModePost << 9; 1130 1131 // On stores, the writeback operand precedes Rt. 1132 switch (Inst.getOpcode()) { 1133 case ARM::STRD: 1134 case ARM::STRD_PRE: 1135 case ARM::STRD_POST: 1136 case ARM::STRH: 1137 case ARM::STRH_PRE: 1138 case ARM::STRH_POST: 1139 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1140 return false; 1141 break; 1142 default: 1143 break; 1144 } 1145 } 1146 1147 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1148 return false; 1149 switch (Inst.getOpcode()) { 1150 case ARM::STRD: 1151 case ARM::STRD_PRE: 1152 case ARM::STRD_POST: 1153 case ARM::LDRD: 1154 case ARM::LDRD_PRE: 1155 case ARM::LDRD_POST: 1156 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1157 return false; 1158 break; 1159 default: 1160 break; 1161 } 1162 1163 if (writeback) { 1164 // On loads, the writeback operand comes after Rt. 1165 switch (Inst.getOpcode()) { 1166 case ARM::LDRD: 1167 case ARM::LDRD_PRE: 1168 case ARM::LDRD_POST: 1169 case ARM::LDRH: 1170 case ARM::LDRH_PRE: 1171 case ARM::LDRH_POST: 1172 case ARM::LDRSH: 1173 case ARM::LDRSH_PRE: 1174 case ARM::LDRSH_POST: 1175 case ARM::LDRSB: 1176 case ARM::LDRSB_PRE: 1177 case ARM::LDRSB_POST: 1178 case ARM::LDRHTr: 1179 case ARM::LDRSBTr: 1180 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1181 return false; 1182 break; 1183 default: 1184 break; 1185 } 1186 } 1187 1188 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1189 return false; 1190 1191 if (type) { 1192 Inst.addOperand(MCOperand::CreateReg(0)); 1193 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1194 } else { 1195 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1196 return false; 1197 Inst.addOperand(MCOperand::CreateImm(U)); 1198 } 1199 1200 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1201 1202 return true; 1203 } 1204 1205 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1206 uint64_t Address, const void *Decoder) { 1207 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1208 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1209 1210 switch (mode) { 1211 case 0: 1212 mode = ARM_AM::da; 1213 break; 1214 case 1: 1215 mode = ARM_AM::ia; 1216 break; 1217 case 2: 1218 mode = ARM_AM::db; 1219 break; 1220 case 3: 1221 mode = ARM_AM::ib; 1222 break; 1223 } 1224 1225 Inst.addOperand(MCOperand::CreateImm(mode)); 1226 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1227 1228 return true; 1229 } 1230 1231 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1232 unsigned Insn, 1233 uint64_t Address, const void *Decoder) { 1234 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1235 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1236 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1237 1238 if (pred == 0xF) { 1239 switch (Inst.getOpcode()) { 1240 case ARM::STMDA: 1241 Inst.setOpcode(ARM::RFEDA); 1242 break; 1243 case ARM::STMDA_UPD: 1244 Inst.setOpcode(ARM::RFEDA_UPD); 1245 break; 1246 case ARM::STMDB: 1247 Inst.setOpcode(ARM::RFEDB); 1248 break; 1249 case ARM::STMDB_UPD: 1250 Inst.setOpcode(ARM::RFEDB_UPD); 1251 break; 1252 case ARM::STMIA: 1253 Inst.setOpcode(ARM::RFEIA); 1254 break; 1255 case ARM::STMIA_UPD: 1256 Inst.setOpcode(ARM::RFEIA_UPD); 1257 break; 1258 case ARM::STMIB: 1259 Inst.setOpcode(ARM::RFEIB); 1260 break; 1261 case ARM::STMIB_UPD: 1262 Inst.setOpcode(ARM::RFEIB_UPD); 1263 break; 1264 } 1265 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1266 } 1267 1268 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1269 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1270 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1271 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1272 return false; 1273 1274 return true; 1275 } 1276 1277 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1278 uint64_t Address, const void *Decoder) { 1279 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1280 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1281 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1282 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1283 1284 // imod == '01' --> UNPREDICTABLE 1285 if (imod == 1) return false; 1286 1287 if (M && mode && imod && iflags) { 1288 Inst.setOpcode(ARM::CPS3p); 1289 Inst.addOperand(MCOperand::CreateImm(imod)); 1290 Inst.addOperand(MCOperand::CreateImm(iflags)); 1291 Inst.addOperand(MCOperand::CreateImm(mode)); 1292 return true; 1293 } else if (!mode && !M) { 1294 Inst.setOpcode(ARM::CPS2p); 1295 Inst.addOperand(MCOperand::CreateImm(imod)); 1296 Inst.addOperand(MCOperand::CreateImm(iflags)); 1297 return true; 1298 } else if (!imod && !iflags && M) { 1299 Inst.setOpcode(ARM::CPS1p); 1300 Inst.addOperand(MCOperand::CreateImm(mode)); 1301 return true; 1302 } 1303 1304 return false; 1305 } 1306 1307 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1308 uint64_t Address, const void *Decoder) { 1309 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1310 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1311 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1312 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1313 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1314 1315 if (pred == 0xF) 1316 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1317 1318 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1319 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1320 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1321 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1322 return false; 1323 1324 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1325 1326 return true; 1327 } 1328 1329 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1330 uint64_t Address, const void *Decoder) { 1331 unsigned add = fieldFromInstruction32(Val, 12, 1); 1332 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1333 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1334 1335 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1336 return false; 1337 1338 if (!add) imm *= -1; 1339 if (imm == 0 && !add) imm = INT32_MIN; 1340 Inst.addOperand(MCOperand::CreateImm(imm)); 1341 1342 return true; 1343 } 1344 1345 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1346 uint64_t Address, const void *Decoder) { 1347 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1348 unsigned U = fieldFromInstruction32(Val, 8, 1); 1349 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1350 1351 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1352 return false; 1353 1354 if (U) 1355 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1356 else 1357 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1358 1359 return true; 1360 } 1361 1362 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1363 uint64_t Address, const void *Decoder) { 1364 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1365 } 1366 1367 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1368 uint64_t Address, const void *Decoder) { 1369 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1370 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1371 1372 if (pred == 0xF) { 1373 Inst.setOpcode(ARM::BLXi); 1374 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1375 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1376 return true; 1377 } 1378 1379 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1380 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1381 1382 return true; 1383 } 1384 1385 1386 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1387 uint64_t Address, const void *Decoder) { 1388 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1389 return true; 1390 } 1391 1392 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1393 uint64_t Address, const void *Decoder) { 1394 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1395 unsigned align = fieldFromInstruction32(Val, 4, 2); 1396 1397 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1398 return false; 1399 if (!align) 1400 Inst.addOperand(MCOperand::CreateImm(0)); 1401 else 1402 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1403 1404 return true; 1405 } 1406 1407 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1408 uint64_t Address, const void *Decoder) { 1409 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1410 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1411 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1412 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1413 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1414 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1415 1416 // First output register 1417 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1418 1419 // Second output register 1420 switch (Inst.getOpcode()) { 1421 case ARM::VLD1q8: 1422 case ARM::VLD1q16: 1423 case ARM::VLD1q32: 1424 case ARM::VLD1q64: 1425 case ARM::VLD1q8_UPD: 1426 case ARM::VLD1q16_UPD: 1427 case ARM::VLD1q32_UPD: 1428 case ARM::VLD1q64_UPD: 1429 case ARM::VLD1d8T: 1430 case ARM::VLD1d16T: 1431 case ARM::VLD1d32T: 1432 case ARM::VLD1d64T: 1433 case ARM::VLD1d8T_UPD: 1434 case ARM::VLD1d16T_UPD: 1435 case ARM::VLD1d32T_UPD: 1436 case ARM::VLD1d64T_UPD: 1437 case ARM::VLD1d8Q: 1438 case ARM::VLD1d16Q: 1439 case ARM::VLD1d32Q: 1440 case ARM::VLD1d64Q: 1441 case ARM::VLD1d8Q_UPD: 1442 case ARM::VLD1d16Q_UPD: 1443 case ARM::VLD1d32Q_UPD: 1444 case ARM::VLD1d64Q_UPD: 1445 case ARM::VLD2d8: 1446 case ARM::VLD2d16: 1447 case ARM::VLD2d32: 1448 case ARM::VLD2d8_UPD: 1449 case ARM::VLD2d16_UPD: 1450 case ARM::VLD2d32_UPD: 1451 case ARM::VLD2q8: 1452 case ARM::VLD2q16: 1453 case ARM::VLD2q32: 1454 case ARM::VLD2q8_UPD: 1455 case ARM::VLD2q16_UPD: 1456 case ARM::VLD2q32_UPD: 1457 case ARM::VLD3d8: 1458 case ARM::VLD3d16: 1459 case ARM::VLD3d32: 1460 case ARM::VLD3d8_UPD: 1461 case ARM::VLD3d16_UPD: 1462 case ARM::VLD3d32_UPD: 1463 case ARM::VLD4d8: 1464 case ARM::VLD4d16: 1465 case ARM::VLD4d32: 1466 case ARM::VLD4d8_UPD: 1467 case ARM::VLD4d16_UPD: 1468 case ARM::VLD4d32_UPD: 1469 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1470 break; 1471 case ARM::VLD2b8: 1472 case ARM::VLD2b16: 1473 case ARM::VLD2b32: 1474 case ARM::VLD2b8_UPD: 1475 case ARM::VLD2b16_UPD: 1476 case ARM::VLD2b32_UPD: 1477 case ARM::VLD3q8: 1478 case ARM::VLD3q16: 1479 case ARM::VLD3q32: 1480 case ARM::VLD3q8_UPD: 1481 case ARM::VLD3q16_UPD: 1482 case ARM::VLD3q32_UPD: 1483 case ARM::VLD4q8: 1484 case ARM::VLD4q16: 1485 case ARM::VLD4q32: 1486 case ARM::VLD4q8_UPD: 1487 case ARM::VLD4q16_UPD: 1488 case ARM::VLD4q32_UPD: 1489 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1490 default: 1491 break; 1492 } 1493 1494 // Third output register 1495 switch(Inst.getOpcode()) { 1496 case ARM::VLD1d8T: 1497 case ARM::VLD1d16T: 1498 case ARM::VLD1d32T: 1499 case ARM::VLD1d64T: 1500 case ARM::VLD1d8T_UPD: 1501 case ARM::VLD1d16T_UPD: 1502 case ARM::VLD1d32T_UPD: 1503 case ARM::VLD1d64T_UPD: 1504 case ARM::VLD1d8Q: 1505 case ARM::VLD1d16Q: 1506 case ARM::VLD1d32Q: 1507 case ARM::VLD1d64Q: 1508 case ARM::VLD1d8Q_UPD: 1509 case ARM::VLD1d16Q_UPD: 1510 case ARM::VLD1d32Q_UPD: 1511 case ARM::VLD1d64Q_UPD: 1512 case ARM::VLD2q8: 1513 case ARM::VLD2q16: 1514 case ARM::VLD2q32: 1515 case ARM::VLD2q8_UPD: 1516 case ARM::VLD2q16_UPD: 1517 case ARM::VLD2q32_UPD: 1518 case ARM::VLD3d8: 1519 case ARM::VLD3d16: 1520 case ARM::VLD3d32: 1521 case ARM::VLD3d8_UPD: 1522 case ARM::VLD3d16_UPD: 1523 case ARM::VLD3d32_UPD: 1524 case ARM::VLD4d8: 1525 case ARM::VLD4d16: 1526 case ARM::VLD4d32: 1527 case ARM::VLD4d8_UPD: 1528 case ARM::VLD4d16_UPD: 1529 case ARM::VLD4d32_UPD: 1530 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1531 break; 1532 case ARM::VLD3q8: 1533 case ARM::VLD3q16: 1534 case ARM::VLD3q32: 1535 case ARM::VLD3q8_UPD: 1536 case ARM::VLD3q16_UPD: 1537 case ARM::VLD3q32_UPD: 1538 case ARM::VLD4q8: 1539 case ARM::VLD4q16: 1540 case ARM::VLD4q32: 1541 case ARM::VLD4q8_UPD: 1542 case ARM::VLD4q16_UPD: 1543 case ARM::VLD4q32_UPD: 1544 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1545 break; 1546 default: 1547 break; 1548 } 1549 1550 // Fourth output register 1551 switch (Inst.getOpcode()) { 1552 case ARM::VLD1d8Q: 1553 case ARM::VLD1d16Q: 1554 case ARM::VLD1d32Q: 1555 case ARM::VLD1d64Q: 1556 case ARM::VLD1d8Q_UPD: 1557 case ARM::VLD1d16Q_UPD: 1558 case ARM::VLD1d32Q_UPD: 1559 case ARM::VLD1d64Q_UPD: 1560 case ARM::VLD2q8: 1561 case ARM::VLD2q16: 1562 case ARM::VLD2q32: 1563 case ARM::VLD2q8_UPD: 1564 case ARM::VLD2q16_UPD: 1565 case ARM::VLD2q32_UPD: 1566 case ARM::VLD4d8: 1567 case ARM::VLD4d16: 1568 case ARM::VLD4d32: 1569 case ARM::VLD4d8_UPD: 1570 case ARM::VLD4d16_UPD: 1571 case ARM::VLD4d32_UPD: 1572 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1573 break; 1574 case ARM::VLD4q8: 1575 case ARM::VLD4q16: 1576 case ARM::VLD4q32: 1577 case ARM::VLD4q8_UPD: 1578 case ARM::VLD4q16_UPD: 1579 case ARM::VLD4q32_UPD: 1580 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1581 break; 1582 default: 1583 break; 1584 } 1585 1586 // Writeback operand 1587 switch (Inst.getOpcode()) { 1588 case ARM::VLD1d8_UPD: 1589 case ARM::VLD1d16_UPD: 1590 case ARM::VLD1d32_UPD: 1591 case ARM::VLD1d64_UPD: 1592 case ARM::VLD1q8_UPD: 1593 case ARM::VLD1q16_UPD: 1594 case ARM::VLD1q32_UPD: 1595 case ARM::VLD1q64_UPD: 1596 case ARM::VLD1d8T_UPD: 1597 case ARM::VLD1d16T_UPD: 1598 case ARM::VLD1d32T_UPD: 1599 case ARM::VLD1d64T_UPD: 1600 case ARM::VLD1d8Q_UPD: 1601 case ARM::VLD1d16Q_UPD: 1602 case ARM::VLD1d32Q_UPD: 1603 case ARM::VLD1d64Q_UPD: 1604 case ARM::VLD2d8_UPD: 1605 case ARM::VLD2d16_UPD: 1606 case ARM::VLD2d32_UPD: 1607 case ARM::VLD2q8_UPD: 1608 case ARM::VLD2q16_UPD: 1609 case ARM::VLD2q32_UPD: 1610 case ARM::VLD2b8_UPD: 1611 case ARM::VLD2b16_UPD: 1612 case ARM::VLD2b32_UPD: 1613 case ARM::VLD3d8_UPD: 1614 case ARM::VLD3d16_UPD: 1615 case ARM::VLD3d32_UPD: 1616 case ARM::VLD3q8_UPD: 1617 case ARM::VLD3q16_UPD: 1618 case ARM::VLD3q32_UPD: 1619 case ARM::VLD4d8_UPD: 1620 case ARM::VLD4d16_UPD: 1621 case ARM::VLD4d32_UPD: 1622 case ARM::VLD4q8_UPD: 1623 case ARM::VLD4q16_UPD: 1624 case ARM::VLD4q32_UPD: 1625 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1626 break; 1627 default: 1628 break; 1629 } 1630 1631 // AddrMode6 Base (register+alignment) 1632 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1633 1634 // AddrMode6 Offset (register) 1635 if (Rm == 0xD) 1636 Inst.addOperand(MCOperand::CreateReg(0)); 1637 else if (Rm != 0xF) { 1638 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1639 return false; 1640 } 1641 1642 return true; 1643 } 1644 1645 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1646 uint64_t Address, const void *Decoder) { 1647 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1648 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1649 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1650 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1651 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1652 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1653 1654 // Writeback Operand 1655 switch (Inst.getOpcode()) { 1656 case ARM::VST1d8_UPD: 1657 case ARM::VST1d16_UPD: 1658 case ARM::VST1d32_UPD: 1659 case ARM::VST1d64_UPD: 1660 case ARM::VST1q8_UPD: 1661 case ARM::VST1q16_UPD: 1662 case ARM::VST1q32_UPD: 1663 case ARM::VST1q64_UPD: 1664 case ARM::VST1d8T_UPD: 1665 case ARM::VST1d16T_UPD: 1666 case ARM::VST1d32T_UPD: 1667 case ARM::VST1d64T_UPD: 1668 case ARM::VST1d8Q_UPD: 1669 case ARM::VST1d16Q_UPD: 1670 case ARM::VST1d32Q_UPD: 1671 case ARM::VST1d64Q_UPD: 1672 case ARM::VST2d8_UPD: 1673 case ARM::VST2d16_UPD: 1674 case ARM::VST2d32_UPD: 1675 case ARM::VST2q8_UPD: 1676 case ARM::VST2q16_UPD: 1677 case ARM::VST2q32_UPD: 1678 case ARM::VST2b8_UPD: 1679 case ARM::VST2b16_UPD: 1680 case ARM::VST2b32_UPD: 1681 case ARM::VST3d8_UPD: 1682 case ARM::VST3d16_UPD: 1683 case ARM::VST3d32_UPD: 1684 case ARM::VST3q8_UPD: 1685 case ARM::VST3q16_UPD: 1686 case ARM::VST3q32_UPD: 1687 case ARM::VST4d8_UPD: 1688 case ARM::VST4d16_UPD: 1689 case ARM::VST4d32_UPD: 1690 case ARM::VST4q8_UPD: 1691 case ARM::VST4q16_UPD: 1692 case ARM::VST4q32_UPD: 1693 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1694 return false; 1695 break; 1696 default: 1697 break; 1698 } 1699 1700 // AddrMode6 Base (register+alignment) 1701 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1702 1703 // AddrMode6 Offset (register) 1704 if (Rm == 0xD) 1705 Inst.addOperand(MCOperand::CreateReg(0)); 1706 else if (Rm != 0xF) { 1707 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1708 } 1709 1710 // First input register 1711 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1712 1713 // Second input register 1714 switch (Inst.getOpcode()) { 1715 case ARM::VST1q8: 1716 case ARM::VST1q16: 1717 case ARM::VST1q32: 1718 case ARM::VST1q64: 1719 case ARM::VST1q8_UPD: 1720 case ARM::VST1q16_UPD: 1721 case ARM::VST1q32_UPD: 1722 case ARM::VST1q64_UPD: 1723 case ARM::VST1d8T: 1724 case ARM::VST1d16T: 1725 case ARM::VST1d32T: 1726 case ARM::VST1d64T: 1727 case ARM::VST1d8T_UPD: 1728 case ARM::VST1d16T_UPD: 1729 case ARM::VST1d32T_UPD: 1730 case ARM::VST1d64T_UPD: 1731 case ARM::VST1d8Q: 1732 case ARM::VST1d16Q: 1733 case ARM::VST1d32Q: 1734 case ARM::VST1d64Q: 1735 case ARM::VST1d8Q_UPD: 1736 case ARM::VST1d16Q_UPD: 1737 case ARM::VST1d32Q_UPD: 1738 case ARM::VST1d64Q_UPD: 1739 case ARM::VST2d8: 1740 case ARM::VST2d16: 1741 case ARM::VST2d32: 1742 case ARM::VST2d8_UPD: 1743 case ARM::VST2d16_UPD: 1744 case ARM::VST2d32_UPD: 1745 case ARM::VST2q8: 1746 case ARM::VST2q16: 1747 case ARM::VST2q32: 1748 case ARM::VST2q8_UPD: 1749 case ARM::VST2q16_UPD: 1750 case ARM::VST2q32_UPD: 1751 case ARM::VST3d8: 1752 case ARM::VST3d16: 1753 case ARM::VST3d32: 1754 case ARM::VST3d8_UPD: 1755 case ARM::VST3d16_UPD: 1756 case ARM::VST3d32_UPD: 1757 case ARM::VST4d8: 1758 case ARM::VST4d16: 1759 case ARM::VST4d32: 1760 case ARM::VST4d8_UPD: 1761 case ARM::VST4d16_UPD: 1762 case ARM::VST4d32_UPD: 1763 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1764 break; 1765 case ARM::VST2b8: 1766 case ARM::VST2b16: 1767 case ARM::VST2b32: 1768 case ARM::VST2b8_UPD: 1769 case ARM::VST2b16_UPD: 1770 case ARM::VST2b32_UPD: 1771 case ARM::VST3q8: 1772 case ARM::VST3q16: 1773 case ARM::VST3q32: 1774 case ARM::VST3q8_UPD: 1775 case ARM::VST3q16_UPD: 1776 case ARM::VST3q32_UPD: 1777 case ARM::VST4q8: 1778 case ARM::VST4q16: 1779 case ARM::VST4q32: 1780 case ARM::VST4q8_UPD: 1781 case ARM::VST4q16_UPD: 1782 case ARM::VST4q32_UPD: 1783 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1784 break; 1785 default: 1786 break; 1787 } 1788 1789 // Third input register 1790 switch (Inst.getOpcode()) { 1791 case ARM::VST1d8T: 1792 case ARM::VST1d16T: 1793 case ARM::VST1d32T: 1794 case ARM::VST1d64T: 1795 case ARM::VST1d8T_UPD: 1796 case ARM::VST1d16T_UPD: 1797 case ARM::VST1d32T_UPD: 1798 case ARM::VST1d64T_UPD: 1799 case ARM::VST1d8Q: 1800 case ARM::VST1d16Q: 1801 case ARM::VST1d32Q: 1802 case ARM::VST1d64Q: 1803 case ARM::VST1d8Q_UPD: 1804 case ARM::VST1d16Q_UPD: 1805 case ARM::VST1d32Q_UPD: 1806 case ARM::VST1d64Q_UPD: 1807 case ARM::VST2q8: 1808 case ARM::VST2q16: 1809 case ARM::VST2q32: 1810 case ARM::VST2q8_UPD: 1811 case ARM::VST2q16_UPD: 1812 case ARM::VST2q32_UPD: 1813 case ARM::VST3d8: 1814 case ARM::VST3d16: 1815 case ARM::VST3d32: 1816 case ARM::VST3d8_UPD: 1817 case ARM::VST3d16_UPD: 1818 case ARM::VST3d32_UPD: 1819 case ARM::VST4d8: 1820 case ARM::VST4d16: 1821 case ARM::VST4d32: 1822 case ARM::VST4d8_UPD: 1823 case ARM::VST4d16_UPD: 1824 case ARM::VST4d32_UPD: 1825 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1826 break; 1827 case ARM::VST3q8: 1828 case ARM::VST3q16: 1829 case ARM::VST3q32: 1830 case ARM::VST3q8_UPD: 1831 case ARM::VST3q16_UPD: 1832 case ARM::VST3q32_UPD: 1833 case ARM::VST4q8: 1834 case ARM::VST4q16: 1835 case ARM::VST4q32: 1836 case ARM::VST4q8_UPD: 1837 case ARM::VST4q16_UPD: 1838 case ARM::VST4q32_UPD: 1839 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1840 break; 1841 default: 1842 break; 1843 } 1844 1845 // Fourth input register 1846 switch (Inst.getOpcode()) { 1847 case ARM::VST1d8Q: 1848 case ARM::VST1d16Q: 1849 case ARM::VST1d32Q: 1850 case ARM::VST1d64Q: 1851 case ARM::VST1d8Q_UPD: 1852 case ARM::VST1d16Q_UPD: 1853 case ARM::VST1d32Q_UPD: 1854 case ARM::VST1d64Q_UPD: 1855 case ARM::VST2q8: 1856 case ARM::VST2q16: 1857 case ARM::VST2q32: 1858 case ARM::VST2q8_UPD: 1859 case ARM::VST2q16_UPD: 1860 case ARM::VST2q32_UPD: 1861 case ARM::VST4d8: 1862 case ARM::VST4d16: 1863 case ARM::VST4d32: 1864 case ARM::VST4d8_UPD: 1865 case ARM::VST4d16_UPD: 1866 case ARM::VST4d32_UPD: 1867 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1868 break; 1869 case ARM::VST4q8: 1870 case ARM::VST4q16: 1871 case ARM::VST4q32: 1872 case ARM::VST4q8_UPD: 1873 case ARM::VST4q16_UPD: 1874 case ARM::VST4q32_UPD: 1875 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1876 break; 1877 default: 1878 break; 1879 } 1880 1881 return true; 1882 } 1883 1884 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1885 uint64_t Address, const void *Decoder) { 1886 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1887 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1888 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1889 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1890 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1891 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1892 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1893 1894 align *= (1 << size); 1895 1896 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1897 if (regs == 2) { 1898 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1899 } 1900 if (Rm == 0xD) { 1901 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1902 } 1903 1904 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1905 Inst.addOperand(MCOperand::CreateImm(align)); 1906 1907 if (Rm == 0xD) 1908 Inst.addOperand(MCOperand::CreateReg(0)); 1909 else if (Rm != 0xF) { 1910 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1911 } 1912 1913 return true; 1914 } 1915 1916 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1917 uint64_t Address, const void *Decoder) { 1918 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1919 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1920 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1921 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1922 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1923 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1924 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1925 align *= 2*size; 1926 1927 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1928 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1929 if (Rm == 0xD) { 1930 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1931 } 1932 1933 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1934 Inst.addOperand(MCOperand::CreateImm(align)); 1935 1936 if (Rm == 0xD) 1937 Inst.addOperand(MCOperand::CreateReg(0)); 1938 else if (Rm != 0xF) { 1939 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1940 } 1941 1942 return true; 1943 } 1944 1945 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1946 uint64_t Address, const void *Decoder) { 1947 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1948 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1949 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1950 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1951 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1952 1953 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1954 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1955 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1956 return false; 1957 if (Rm == 0xD) { 1958 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1959 } 1960 1961 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1962 Inst.addOperand(MCOperand::CreateImm(0)); 1963 1964 if (Rm == 0xD) 1965 Inst.addOperand(MCOperand::CreateReg(0)); 1966 else if (Rm != 0xF) { 1967 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1968 } 1969 1970 return true; 1971 } 1972 1973 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1974 uint64_t Address, const void *Decoder) { 1975 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1976 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1977 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1978 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1979 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1980 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1981 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1982 1983 if (size == 0x3) { 1984 size = 4; 1985 align = 16; 1986 } else { 1987 if (size == 2) { 1988 size = 1 << size; 1989 align *= 8; 1990 } else { 1991 size = 1 << size; 1992 align *= 4*size; 1993 } 1994 } 1995 1996 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1997 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1998 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1999 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 2000 return false; 2001 if (Rm == 0xD) { 2002 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2003 } 2004 2005 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2006 Inst.addOperand(MCOperand::CreateImm(align)); 2007 2008 if (Rm == 0xD) 2009 Inst.addOperand(MCOperand::CreateReg(0)); 2010 else if (Rm != 0xF) { 2011 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2012 } 2013 2014 return true; 2015 } 2016 2017 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2018 uint64_t Address, const void *Decoder) { 2019 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2020 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2021 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2022 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2023 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2024 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2025 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2026 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2027 2028 if (Q) { 2029 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2030 } else { 2031 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2032 } 2033 2034 Inst.addOperand(MCOperand::CreateImm(imm)); 2035 2036 switch (Inst.getOpcode()) { 2037 case ARM::VORRiv4i16: 2038 case ARM::VORRiv2i32: 2039 case ARM::VBICiv4i16: 2040 case ARM::VBICiv2i32: 2041 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2042 break; 2043 case ARM::VORRiv8i16: 2044 case ARM::VORRiv4i32: 2045 case ARM::VBICiv8i16: 2046 case ARM::VBICiv4i32: 2047 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2048 break; 2049 default: 2050 break; 2051 } 2052 2053 return true; 2054 } 2055 2056 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2057 uint64_t Address, const void *Decoder) { 2058 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2059 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2060 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2061 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2062 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2063 2064 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2065 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2066 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2067 2068 return true; 2069 } 2070 2071 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2072 uint64_t Address, const void *Decoder) { 2073 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2074 return true; 2075 } 2076 2077 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2078 uint64_t Address, const void *Decoder) { 2079 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2080 return true; 2081 } 2082 2083 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2084 uint64_t Address, const void *Decoder) { 2085 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2086 return true; 2087 } 2088 2089 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2090 uint64_t Address, const void *Decoder) { 2091 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2092 return true; 2093 } 2094 2095 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2096 uint64_t Address, const void *Decoder) { 2097 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2098 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2099 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2100 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2101 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2102 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2103 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2104 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2105 2106 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2107 if (op) { 2108 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2109 } 2110 2111 for (unsigned i = 0; i < length; ++i) { 2112 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2113 } 2114 2115 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2116 2117 return true; 2118 } 2119 2120 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2121 uint64_t Address, const void *Decoder) { 2122 // The immediate needs to be a fully instantiated float. However, the 2123 // auto-generated decoder is only able to fill in some of the bits 2124 // necessary. For instance, the 'b' bit is replicated multiple times, 2125 // and is even present in inverted form in one bit. We do a little 2126 // binary parsing here to fill in those missing bits, and then 2127 // reinterpret it all as a float. 2128 union { 2129 uint32_t integer; 2130 float fp; 2131 } fp_conv; 2132 2133 fp_conv.integer = Val; 2134 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2135 fp_conv.integer |= b << 26; 2136 fp_conv.integer |= b << 27; 2137 fp_conv.integer |= b << 28; 2138 fp_conv.integer |= b << 29; 2139 fp_conv.integer |= (~b & 0x1) << 30; 2140 2141 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2142 return true; 2143 } 2144 2145 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2146 uint64_t Address, const void *Decoder) { 2147 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2148 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2149 2150 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2151 2152 if (Inst.getOpcode() == ARM::tADR) 2153 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2154 else if (Inst.getOpcode() == ARM::tADDrSPi) 2155 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2156 else 2157 return false; 2158 2159 Inst.addOperand(MCOperand::CreateImm(imm)); 2160 return true; 2161 } 2162 2163 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2164 uint64_t Address, const void *Decoder) { 2165 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2166 return true; 2167 } 2168 2169 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2170 uint64_t Address, const void *Decoder) { 2171 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2172 return true; 2173 } 2174 2175 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2176 uint64_t Address, const void *Decoder) { 2177 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2178 return true; 2179 } 2180 2181 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2182 uint64_t Address, const void *Decoder) { 2183 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2184 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2185 2186 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2187 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2188 return false; 2189 2190 return true; 2191 } 2192 2193 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2194 uint64_t Address, const void *Decoder) { 2195 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2196 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2197 2198 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2199 Inst.addOperand(MCOperand::CreateImm(imm)); 2200 2201 return true; 2202 } 2203 2204 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2205 uint64_t Address, const void *Decoder) { 2206 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2207 2208 return true; 2209 } 2210 2211 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2212 uint64_t Address, const void *Decoder) { 2213 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2214 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2215 2216 return true; 2217 } 2218 2219 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2220 uint64_t Address, const void *Decoder) { 2221 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2222 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2223 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2224 2225 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2226 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2227 return false; 2228 Inst.addOperand(MCOperand::CreateImm(imm)); 2229 2230 return true; 2231 } 2232 2233 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2234 uint64_t Address, const void *Decoder) { 2235 if (Inst.getOpcode() != ARM::t2PLDs) { 2236 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2237 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2238 } 2239 2240 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2241 if (Rn == 0xF) { 2242 switch (Inst.getOpcode()) { 2243 case ARM::t2LDRBs: 2244 Inst.setOpcode(ARM::t2LDRBpci); 2245 break; 2246 case ARM::t2LDRHs: 2247 Inst.setOpcode(ARM::t2LDRHpci); 2248 break; 2249 case ARM::t2LDRSHs: 2250 Inst.setOpcode(ARM::t2LDRSHpci); 2251 break; 2252 case ARM::t2LDRSBs: 2253 Inst.setOpcode(ARM::t2LDRSBpci); 2254 break; 2255 case ARM::t2PLDs: 2256 Inst.setOpcode(ARM::t2PLDi12); 2257 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2258 break; 2259 default: 2260 return false; 2261 } 2262 2263 int imm = fieldFromInstruction32(Insn, 0, 12); 2264 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2265 Inst.addOperand(MCOperand::CreateImm(imm)); 2266 2267 return true; 2268 } 2269 2270 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2271 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2272 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2273 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2274 2275 return true; 2276 } 2277 2278 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2279 uint64_t Address, const void *Decoder) { 2280 int imm = Val & 0xFF; 2281 if (!(Val & 0x100)) imm *= -1; 2282 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2283 2284 return true; 2285 } 2286 2287 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2288 uint64_t Address, const void *Decoder) { 2289 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2290 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2291 2292 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2293 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2294 return false; 2295 2296 return true; 2297 } 2298 2299 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2300 uint64_t Address, const void *Decoder) { 2301 int imm = Val & 0xFF; 2302 if (!(Val & 0x100)) imm *= -1; 2303 Inst.addOperand(MCOperand::CreateImm(imm)); 2304 2305 return true; 2306 } 2307 2308 2309 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2310 uint64_t Address, const void *Decoder) { 2311 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2312 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2313 2314 // Some instructions always use an additive offset. 2315 switch (Inst.getOpcode()) { 2316 case ARM::t2LDRT: 2317 case ARM::t2LDRBT: 2318 case ARM::t2LDRHT: 2319 case ARM::t2LDRSBT: 2320 case ARM::t2LDRSHT: 2321 imm |= 0x100; 2322 break; 2323 default: 2324 break; 2325 } 2326 2327 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2328 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2329 return false; 2330 2331 return true; 2332 } 2333 2334 2335 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2336 uint64_t Address, const void *Decoder) { 2337 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2338 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2339 2340 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2341 Inst.addOperand(MCOperand::CreateImm(imm)); 2342 2343 return true; 2344 } 2345 2346 2347 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2348 uint64_t Address, const void *Decoder) { 2349 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2350 2351 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2352 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2353 Inst.addOperand(MCOperand::CreateImm(imm)); 2354 2355 return true; 2356 } 2357 2358 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2359 uint64_t Address, const void *Decoder) { 2360 if (Inst.getOpcode() == ARM::tADDrSP) { 2361 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2362 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2363 2364 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2365 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2366 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2367 } else if (Inst.getOpcode() == ARM::tADDspr) { 2368 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2369 2370 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2371 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2372 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2373 } 2374 2375 return true; 2376 } 2377 2378 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2379 uint64_t Address, const void *Decoder) { 2380 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2381 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2382 2383 Inst.addOperand(MCOperand::CreateImm(imod)); 2384 Inst.addOperand(MCOperand::CreateImm(flags)); 2385 2386 return true; 2387 } 2388 2389 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2390 uint64_t Address, const void *Decoder) { 2391 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2392 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2393 2394 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2395 Inst.addOperand(MCOperand::CreateImm(add)); 2396 2397 return true; 2398 } 2399 2400 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2401 uint64_t Address, const void *Decoder) { 2402 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2403 return true; 2404 } 2405 2406 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2407 uint64_t Address, const void *Decoder) { 2408 if (Val == 0xA || Val == 0xB) 2409 return false; 2410 2411 Inst.addOperand(MCOperand::CreateImm(Val)); 2412 return true; 2413 } 2414 2415 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2416 uint64_t Address, const void *Decoder) { 2417 if (Val == 0) 2418 Inst.addOperand(MCOperand::CreateImm(32)); 2419 else 2420 Inst.addOperand(MCOperand::CreateImm(Val)); 2421 return true; 2422 } 2423 2424 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2425 uint64_t Address, const void *Decoder) { 2426 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2427 if (pred == 0xE || pred == 0xF) { 2428 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2429 switch (opc) { 2430 default: 2431 return false; 2432 case 0: 2433 Inst.setOpcode(ARM::t2DSB); 2434 break; 2435 case 1: 2436 Inst.setOpcode(ARM::t2DMB); 2437 break; 2438 case 2: 2439 Inst.setOpcode(ARM::t2ISB); 2440 return true; 2441 } 2442 2443 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2444 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2445 } 2446 2447 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2448 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2449 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2450 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2451 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2452 2453 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2454 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2455 return false; 2456 2457 return true; 2458 } 2459 2460 // Decode a shifted immediate operand. These basically consist 2461 // of an 8-bit value, and a 4-bit directive that specifies either 2462 // a splat operation or a rotation. 2463 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2464 uint64_t Address, const void *Decoder) { 2465 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2466 if (ctrl == 0) { 2467 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2468 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2469 switch (byte) { 2470 case 0: 2471 Inst.addOperand(MCOperand::CreateImm(imm)); 2472 break; 2473 case 1: 2474 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2475 break; 2476 case 2: 2477 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2478 break; 2479 case 3: 2480 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2481 (imm << 8) | imm)); 2482 break; 2483 } 2484 } else { 2485 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2486 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2487 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2488 Inst.addOperand(MCOperand::CreateImm(imm)); 2489 } 2490 2491 return true; 2492 } 2493 2494 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2495 uint64_t Address, const void *Decoder){ 2496 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2497 return true; 2498 } 2499 2500 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2501 uint64_t Address, const void *Decoder){ 2502 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2503 return true; 2504 } 2505 2506 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2507 uint64_t Address, const void *Decoder) { 2508 switch (Val) { 2509 default: 2510 return false; 2511 case 0xF: // SY 2512 case 0xE: // ST 2513 case 0xB: // ISH 2514 case 0xA: // ISHST 2515 case 0x7: // NSH 2516 case 0x6: // NSHST 2517 case 0x3: // OSH 2518 case 0x2: // OSHST 2519 break; 2520 } 2521 2522 Inst.addOperand(MCOperand::CreateImm(Val)); 2523 return true; 2524 } 2525 2526 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2527 uint64_t Address, const void *Decoder) { 2528 if (!Val) return false; 2529 Inst.addOperand(MCOperand::CreateImm(Val)); 2530 return true; 2531 } 2532 2533 static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2534 uint64_t Address, const void *Decoder) { 2535 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2536 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2537 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2538 2539 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2540 2541 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2542 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2543 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2544 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2545 2546 return true; 2547 } 2548 2549 2550 static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2551 uint64_t Address, const void *Decoder) { 2552 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2553 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2554 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2555 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2556 2557 if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2558 2559 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2560 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; 2561 2562 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2563 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2564 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2565 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2566 2567 return true; 2568 } 2569 2570 static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2571 uint64_t Address, const void *Decoder) { 2572 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2573 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2574 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2575 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2576 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2577 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2578 2579 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2580 2581 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2582 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2583 if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false; 2584 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2585 2586 return true; 2587 } 2588 2589 static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2590 uint64_t Address, const void *Decoder) { 2591 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2592 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2593 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2594 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2595 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2596 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2597 2598 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2599 2600 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2601 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2602 if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false; 2603 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2604 2605 return true; 2606 } 2607 2608 static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2609 uint64_t Address, const void *Decoder) { 2610 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2611 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2612 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2613 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2614 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2615 2616 unsigned align = 0; 2617 unsigned index = 0; 2618 switch (size) { 2619 default: 2620 return false; 2621 case 0: 2622 if (fieldFromInstruction32(Insn, 4, 1)) 2623 return false; // UNDEFINED 2624 index = fieldFromInstruction32(Insn, 5, 3); 2625 break; 2626 case 1: 2627 if (fieldFromInstruction32(Insn, 5, 1)) 2628 return false; // UNDEFINED 2629 index = fieldFromInstruction32(Insn, 6, 2); 2630 if (fieldFromInstruction32(Insn, 4, 1)) 2631 align = 2; 2632 break; 2633 case 2: 2634 if (fieldFromInstruction32(Insn, 6, 1)) 2635 return false; // UNDEFINED 2636 index = fieldFromInstruction32(Insn, 7, 1); 2637 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2638 align = 4; 2639 } 2640 2641 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2642 if (Rm != 0xF) { // Writeback 2643 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2644 return false; 2645 } 2646 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2647 Inst.addOperand(MCOperand::CreateImm(align)); 2648 if (Rm != 0xF && Rm != 0xD) { 2649 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2650 return false; 2651 } 2652 2653 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2654 Inst.addOperand(MCOperand::CreateImm(index)); 2655 2656 return true; 2657 } 2658 2659 static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2660 uint64_t Address, const void *Decoder) { 2661 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2662 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2663 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2664 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2665 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2666 2667 unsigned align = 0; 2668 unsigned index = 0; 2669 switch (size) { 2670 default: 2671 return false; 2672 case 0: 2673 if (fieldFromInstruction32(Insn, 4, 1)) 2674 return false; // UNDEFINED 2675 index = fieldFromInstruction32(Insn, 5, 3); 2676 break; 2677 case 1: 2678 if (fieldFromInstruction32(Insn, 5, 1)) 2679 return false; // UNDEFINED 2680 index = fieldFromInstruction32(Insn, 6, 2); 2681 if (fieldFromInstruction32(Insn, 4, 1)) 2682 align = 2; 2683 break; 2684 case 2: 2685 if (fieldFromInstruction32(Insn, 6, 1)) 2686 return false; // UNDEFINED 2687 index = fieldFromInstruction32(Insn, 7, 1); 2688 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2689 align = 4; 2690 } 2691 2692 if (Rm != 0xF) { // Writeback 2693 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2694 return false; 2695 } 2696 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2697 Inst.addOperand(MCOperand::CreateImm(align)); 2698 if (Rm != 0xF && Rm != 0xD) { 2699 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2700 return false; 2701 } 2702 2703 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2704 Inst.addOperand(MCOperand::CreateImm(index)); 2705 2706 return true; 2707 } 2708 2709 2710 static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2711 uint64_t Address, const void *Decoder) { 2712 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2713 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2714 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2715 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2716 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2717 2718 unsigned align = 0; 2719 unsigned index = 0; 2720 unsigned inc = 1; 2721 switch (size) { 2722 default: 2723 return false; 2724 case 0: 2725 index = fieldFromInstruction32(Insn, 5, 3); 2726 if (fieldFromInstruction32(Insn, 4, 1)) 2727 align = 2; 2728 break; 2729 case 1: 2730 index = fieldFromInstruction32(Insn, 6, 2); 2731 if (fieldFromInstruction32(Insn, 4, 1)) 2732 align = 4; 2733 if (fieldFromInstruction32(Insn, 5, 1)) 2734 inc = 2; 2735 break; 2736 case 2: 2737 if (fieldFromInstruction32(Insn, 5, 1)) 2738 return false; // UNDEFINED 2739 index = fieldFromInstruction32(Insn, 7, 1); 2740 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2741 align = 8; 2742 if (fieldFromInstruction32(Insn, 6, 1)) 2743 inc = 2; 2744 break; 2745 } 2746 2747 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2748 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2749 if (Rm != 0xF) { // Writeback 2750 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2751 return false; 2752 } 2753 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2754 Inst.addOperand(MCOperand::CreateImm(align)); 2755 if (Rm != 0xF && Rm != 0xD) { 2756 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2757 return false; 2758 } 2759 2760 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2761 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2762 Inst.addOperand(MCOperand::CreateImm(index)); 2763 2764 return true; 2765 } 2766 2767 static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2768 uint64_t Address, const void *Decoder) { 2769 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2770 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2771 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2772 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2773 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2774 2775 unsigned align = 0; 2776 unsigned index = 0; 2777 unsigned inc = 1; 2778 switch (size) { 2779 default: 2780 return false; 2781 case 0: 2782 index = fieldFromInstruction32(Insn, 5, 3); 2783 if (fieldFromInstruction32(Insn, 4, 1)) 2784 align = 2; 2785 break; 2786 case 1: 2787 index = fieldFromInstruction32(Insn, 6, 2); 2788 if (fieldFromInstruction32(Insn, 4, 1)) 2789 align = 4; 2790 if (fieldFromInstruction32(Insn, 5, 1)) 2791 inc = 2; 2792 break; 2793 case 2: 2794 if (fieldFromInstruction32(Insn, 5, 1)) 2795 return false; // UNDEFINED 2796 index = fieldFromInstruction32(Insn, 7, 1); 2797 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2798 align = 8; 2799 if (fieldFromInstruction32(Insn, 6, 1)) 2800 inc = 2; 2801 break; 2802 } 2803 2804 if (Rm != 0xF) { // Writeback 2805 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2806 return false; 2807 } 2808 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2809 Inst.addOperand(MCOperand::CreateImm(align)); 2810 if (Rm != 0xF && Rm != 0xD) { 2811 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2812 return false; 2813 } 2814 2815 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2816 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2817 Inst.addOperand(MCOperand::CreateImm(index)); 2818 2819 return true; 2820 } 2821 2822 2823 static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 2824 uint64_t Address, const void *Decoder) { 2825 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2826 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2827 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2828 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2829 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2830 2831 unsigned align = 0; 2832 unsigned index = 0; 2833 unsigned inc = 1; 2834 switch (size) { 2835 default: 2836 return false; 2837 case 0: 2838 if (fieldFromInstruction32(Insn, 4, 1)) 2839 return false; // UNDEFINED 2840 index = fieldFromInstruction32(Insn, 5, 3); 2841 break; 2842 case 1: 2843 if (fieldFromInstruction32(Insn, 4, 1)) 2844 return false; // UNDEFINED 2845 index = fieldFromInstruction32(Insn, 6, 2); 2846 if (fieldFromInstruction32(Insn, 5, 1)) 2847 inc = 2; 2848 break; 2849 case 2: 2850 if (fieldFromInstruction32(Insn, 4, 2)) 2851 return false; // UNDEFINED 2852 index = fieldFromInstruction32(Insn, 7, 1); 2853 if (fieldFromInstruction32(Insn, 6, 1)) 2854 inc = 2; 2855 break; 2856 } 2857 2858 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2859 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2860 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2861 2862 if (Rm != 0xF) { // Writeback 2863 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2864 return false; 2865 } 2866 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2867 Inst.addOperand(MCOperand::CreateImm(align)); 2868 if (Rm != 0xF && Rm != 0xD) { 2869 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2870 return false; 2871 } 2872 2873 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2874 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2875 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2876 Inst.addOperand(MCOperand::CreateImm(index)); 2877 2878 return true; 2879 } 2880 2881 static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 2882 uint64_t Address, const void *Decoder) { 2883 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2884 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2885 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2886 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2887 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2888 2889 unsigned align = 0; 2890 unsigned index = 0; 2891 unsigned inc = 1; 2892 switch (size) { 2893 default: 2894 return false; 2895 case 0: 2896 if (fieldFromInstruction32(Insn, 4, 1)) 2897 return false; // UNDEFINED 2898 index = fieldFromInstruction32(Insn, 5, 3); 2899 break; 2900 case 1: 2901 if (fieldFromInstruction32(Insn, 4, 1)) 2902 return false; // UNDEFINED 2903 index = fieldFromInstruction32(Insn, 6, 2); 2904 if (fieldFromInstruction32(Insn, 5, 1)) 2905 inc = 2; 2906 break; 2907 case 2: 2908 if (fieldFromInstruction32(Insn, 4, 2)) 2909 return false; // UNDEFINED 2910 index = fieldFromInstruction32(Insn, 7, 1); 2911 if (fieldFromInstruction32(Insn, 6, 1)) 2912 inc = 2; 2913 break; 2914 } 2915 2916 if (Rm != 0xF) { // Writeback 2917 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2918 return false; 2919 } 2920 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2921 Inst.addOperand(MCOperand::CreateImm(align)); 2922 if (Rm != 0xF && Rm != 0xD) { 2923 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2924 return false; 2925 } 2926 2927 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2928 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2929 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2930 Inst.addOperand(MCOperand::CreateImm(index)); 2931 2932 return true; 2933 } 2934 2935 2936 static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 2937 uint64_t Address, const void *Decoder) { 2938 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2939 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2940 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2941 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2942 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2943 2944 unsigned align = 0; 2945 unsigned index = 0; 2946 unsigned inc = 1; 2947 switch (size) { 2948 default: 2949 return false; 2950 case 0: 2951 if (fieldFromInstruction32(Insn, 4, 1)) 2952 align = 4; 2953 index = fieldFromInstruction32(Insn, 5, 3); 2954 break; 2955 case 1: 2956 if (fieldFromInstruction32(Insn, 4, 1)) 2957 align = 8; 2958 index = fieldFromInstruction32(Insn, 6, 2); 2959 if (fieldFromInstruction32(Insn, 5, 1)) 2960 inc = 2; 2961 break; 2962 case 2: 2963 if (fieldFromInstruction32(Insn, 4, 2)) 2964 align = 4 << fieldFromInstruction32(Insn, 4, 2); 2965 index = fieldFromInstruction32(Insn, 7, 1); 2966 if (fieldFromInstruction32(Insn, 6, 1)) 2967 inc = 2; 2968 break; 2969 } 2970 2971 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2972 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2973 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2974 if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; 2975 2976 if (Rm != 0xF) { // Writeback 2977 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2978 return false; 2979 } 2980 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2981 Inst.addOperand(MCOperand::CreateImm(align)); 2982 if (Rm != 0xF && Rm != 0xD) { 2983 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2984 return false; 2985 } 2986 2987 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2988 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2989 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2990 if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; 2991 Inst.addOperand(MCOperand::CreateImm(index)); 2992 2993 return true; 2994 } 2995 2996 static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 2997 uint64_t Address, const void *Decoder) { 2998 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2999 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3000 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3001 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3002 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3003 3004 unsigned align = 0; 3005 unsigned index = 0; 3006 unsigned inc = 1; 3007 switch (size) { 3008 default: 3009 return false; 3010 case 0: 3011 if (fieldFromInstruction32(Insn, 4, 1)) 3012 align = 4; 3013 index = fieldFromInstruction32(Insn, 5, 3); 3014 break; 3015 case 1: 3016 if (fieldFromInstruction32(Insn, 4, 1)) 3017 align = 8; 3018 index = fieldFromInstruction32(Insn, 6, 2); 3019 if (fieldFromInstruction32(Insn, 5, 1)) 3020 inc = 2; 3021 break; 3022 case 2: 3023 if (fieldFromInstruction32(Insn, 4, 2)) 3024 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3025 index = fieldFromInstruction32(Insn, 7, 1); 3026 if (fieldFromInstruction32(Insn, 6, 1)) 3027 inc = 2; 3028 break; 3029 } 3030 3031 if (Rm != 0xF) { // Writeback 3032 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 3033 return false; 3034 } 3035 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 3036 Inst.addOperand(MCOperand::CreateImm(align)); 3037 if (Rm != 0xF && Rm != 0xD) { 3038 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 3039 return false; 3040 } 3041 3042 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 3043 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 3044 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 3045 if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; 3046 Inst.addOperand(MCOperand::CreateImm(index)); 3047 3048 return true; 3049 } 3050 3051