1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMSubtarget.h" 14 #include "MCTargetDesc/ARMAddressingModes.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDisassembler.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 /// ARMDisassembler - ARM disassembler for all ARM platforms. 35 class ARMDisassembler : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 EDInstInfo *getEDInfo() const; 56 private: 57 }; 58 59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60 class ThumbDisassembler : public MCDisassembler { 61 public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 EDInstInfo *getEDInfo() const; 81 private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85 }; 86 } 87 88 static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 return false; 101 } 102 103 104 // Forward declare these because the autogenerated code will reference them. 105 // Definitions are further down. 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129 130 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 146 uint64_t Address, const void *Decoder); 147 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 160 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 161 unsigned Insn, 162 uint64_t Adddress, 163 const void *Decoder); 164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 255 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 316 uint64_t Address, const void *Decoder); 317 318 319 320 #include "ARMGenDisassemblerTables.inc" 321 #include "ARMGenInstrInfo.inc" 322 #include "ARMGenEDInfo.inc" 323 324 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 325 return new ARMDisassembler(STI); 326 } 327 328 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 329 return new ThumbDisassembler(STI); 330 } 331 332 EDInstInfo *ARMDisassembler::getEDInfo() const { 333 return instInfoARM; 334 } 335 336 EDInstInfo *ThumbDisassembler::getEDInfo() const { 337 return instInfoARM; 338 } 339 340 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 341 const MemoryObject &Region, 342 uint64_t Address, 343 raw_ostream &os, 344 raw_ostream &cs) const { 345 CommentStream = &cs; 346 347 uint8_t bytes[4]; 348 349 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 350 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 351 352 // We want to read exactly 4 bytes of data. 353 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 354 Size = 0; 355 return MCDisassembler::Fail; 356 } 357 358 // Encoded as a small-endian 32-bit word in the stream. 359 uint32_t insn = (bytes[3] << 24) | 360 (bytes[2] << 16) | 361 (bytes[1] << 8) | 362 (bytes[0] << 0); 363 364 // Calling the auto-generated decoder function. 365 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 366 if (result != MCDisassembler::Fail) { 367 Size = 4; 368 return result; 369 } 370 371 // VFP and NEON instructions, similarly, are shared between ARM 372 // and Thumb modes. 373 MI.clear(); 374 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 375 if (result != MCDisassembler::Fail) { 376 Size = 4; 377 return result; 378 } 379 380 MI.clear(); 381 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 382 if (result != MCDisassembler::Fail) { 383 Size = 4; 384 // Add a fake predicate operand, because we share these instruction 385 // definitions with Thumb2 where these instructions are predicable. 386 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 387 return MCDisassembler::Fail; 388 return result; 389 } 390 391 MI.clear(); 392 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 393 if (result != MCDisassembler::Fail) { 394 Size = 4; 395 // Add a fake predicate operand, because we share these instruction 396 // definitions with Thumb2 where these instructions are predicable. 397 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 398 return MCDisassembler::Fail; 399 return result; 400 } 401 402 MI.clear(); 403 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 404 if (result != MCDisassembler::Fail) { 405 Size = 4; 406 // Add a fake predicate operand, because we share these instruction 407 // definitions with Thumb2 where these instructions are predicable. 408 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 409 return MCDisassembler::Fail; 410 return result; 411 } 412 413 MI.clear(); 414 415 Size = 0; 416 return MCDisassembler::Fail; 417 } 418 419 namespace llvm { 420 extern const MCInstrDesc ARMInsts[]; 421 } 422 423 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 424 /// immediate Value in the MCInst. The immediate Value has had any PC 425 /// adjustment made by the caller. If the instruction is a branch instruction 426 /// then isBranch is true, else false. If the getOpInfo() function was set as 427 /// part of the setupForSymbolicDisassembly() call then that function is called 428 /// to get any symbolic information at the Address for this instruction. If 429 /// that returns non-zero then the symbolic information it returns is used to 430 /// create an MCExpr and that is added as an operand to the MCInst. If 431 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 432 /// Value is done and if a symbol is found an MCExpr is created with that, else 433 /// an MCExpr with Value is created. This function returns true if it adds an 434 /// operand to the MCInst and false otherwise. 435 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 436 bool isBranch, uint64_t InstSize, 437 MCInst &MI, const void *Decoder) { 438 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 439 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 440 if (!getOpInfo) 441 return false; 442 443 struct LLVMOpInfo1 SymbolicOp; 444 SymbolicOp.Value = Value; 445 void *DisInfo = Dis->getDisInfoBlock(); 446 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 447 if (isBranch) { 448 LLVMSymbolLookupCallback SymbolLookUp = 449 Dis->getLLVMSymbolLookupCallback(); 450 if (SymbolLookUp) { 451 uint64_t ReferenceType; 452 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 453 const char *ReferenceName; 454 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 455 &ReferenceName); 456 if (Name) { 457 SymbolicOp.AddSymbol.Name = Name; 458 SymbolicOp.AddSymbol.Present = true; 459 SymbolicOp.Value = 0; 460 } 461 else { 462 SymbolicOp.Value = Value; 463 } 464 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 465 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 466 } 467 else { 468 return false; 469 } 470 } 471 else { 472 return false; 473 } 474 } 475 476 MCContext *Ctx = Dis->getMCContext(); 477 const MCExpr *Add = NULL; 478 if (SymbolicOp.AddSymbol.Present) { 479 if (SymbolicOp.AddSymbol.Name) { 480 StringRef Name(SymbolicOp.AddSymbol.Name); 481 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 482 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 483 } else { 484 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 485 } 486 } 487 488 const MCExpr *Sub = NULL; 489 if (SymbolicOp.SubtractSymbol.Present) { 490 if (SymbolicOp.SubtractSymbol.Name) { 491 StringRef Name(SymbolicOp.SubtractSymbol.Name); 492 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 493 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 494 } else { 495 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 496 } 497 } 498 499 const MCExpr *Off = NULL; 500 if (SymbolicOp.Value != 0) 501 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 502 503 const MCExpr *Expr; 504 if (Sub) { 505 const MCExpr *LHS; 506 if (Add) 507 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 508 else 509 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 510 if (Off != 0) 511 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 512 else 513 Expr = LHS; 514 } else if (Add) { 515 if (Off != 0) 516 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 517 else 518 Expr = Add; 519 } else { 520 if (Off != 0) 521 Expr = Off; 522 else 523 Expr = MCConstantExpr::Create(0, *Ctx); 524 } 525 526 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 529 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 530 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 531 MI.addOperand(MCOperand::CreateExpr(Expr)); 532 else 533 assert(0 && "bad SymbolicOp.VariantKind"); 534 535 return true; 536 } 537 538 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 539 /// referenced by a load instruction with the base register that is the Pc. 540 /// These can often be values in a literal pool near the Address of the 541 /// instruction. The Address of the instruction and its immediate Value are 542 /// used as a possible literal pool entry. The SymbolLookUp call back will 543 /// return the name of a symbol referenced by the the literal pool's entry if 544 /// the referenced address is that of a symbol. Or it will return a pointer to 545 /// a literal 'C' string if the referenced address of the literal pool's entry 546 /// is an address into a section with 'C' string literals. 547 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 548 const void *Decoder) { 549 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 550 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 551 if (SymbolLookUp) { 552 void *DisInfo = Dis->getDisInfoBlock(); 553 uint64_t ReferenceType; 554 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 555 const char *ReferenceName; 556 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 557 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 558 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 559 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 560 } 561 } 562 563 // Thumb1 instructions don't have explicit S bits. Rather, they 564 // implicitly set CPSR. Since it's not represented in the encoding, the 565 // auto-generated decoder won't inject the CPSR operand. We need to fix 566 // that as a post-pass. 567 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 568 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 569 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 570 MCInst::iterator I = MI.begin(); 571 for (unsigned i = 0; i < NumOps; ++i, ++I) { 572 if (I == MI.end()) break; 573 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 574 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 575 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 576 return; 577 } 578 } 579 580 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 581 } 582 583 // Most Thumb instructions don't have explicit predicates in the 584 // encoding, but rather get their predicates from IT context. We need 585 // to fix up the predicate operands using this context information as a 586 // post-pass. 587 MCDisassembler::DecodeStatus 588 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 589 MCDisassembler::DecodeStatus S = Success; 590 591 // A few instructions actually have predicates encoded in them. Don't 592 // try to overwrite it if we're seeing one of those. 593 switch (MI.getOpcode()) { 594 case ARM::tBcc: 595 case ARM::t2Bcc: 596 case ARM::tCBZ: 597 case ARM::tCBNZ: 598 case ARM::tCPS: 599 case ARM::t2CPS3p: 600 case ARM::t2CPS2p: 601 case ARM::t2CPS1p: 602 case ARM::tMOVSr: 603 case ARM::tSETEND: 604 // Some instructions (mostly conditional branches) are not 605 // allowed in IT blocks. 606 if (!ITBlock.empty()) 607 S = SoftFail; 608 else 609 return Success; 610 break; 611 case ARM::tB: 612 case ARM::t2B: 613 case ARM::t2TBB: 614 case ARM::t2TBH: 615 // Some instructions (mostly unconditional branches) can 616 // only appears at the end of, or outside of, an IT. 617 if (ITBlock.size() > 1) 618 S = SoftFail; 619 break; 620 default: 621 break; 622 } 623 624 // If we're in an IT block, base the predicate on that. Otherwise, 625 // assume a predicate of AL. 626 unsigned CC; 627 if (!ITBlock.empty()) { 628 CC = ITBlock.back(); 629 if (CC == 0xF) 630 CC = ARMCC::AL; 631 ITBlock.pop_back(); 632 } else 633 CC = ARMCC::AL; 634 635 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 636 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 637 MCInst::iterator I = MI.begin(); 638 for (unsigned i = 0; i < NumOps; ++i, ++I) { 639 if (I == MI.end()) break; 640 if (OpInfo[i].isPredicate()) { 641 I = MI.insert(I, MCOperand::CreateImm(CC)); 642 ++I; 643 if (CC == ARMCC::AL) 644 MI.insert(I, MCOperand::CreateReg(0)); 645 else 646 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 647 return S; 648 } 649 } 650 651 I = MI.insert(I, MCOperand::CreateImm(CC)); 652 ++I; 653 if (CC == ARMCC::AL) 654 MI.insert(I, MCOperand::CreateReg(0)); 655 else 656 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 657 658 return S; 659 } 660 661 // Thumb VFP instructions are a special case. Because we share their 662 // encodings between ARM and Thumb modes, and they are predicable in ARM 663 // mode, the auto-generated decoder will give them an (incorrect) 664 // predicate operand. We need to rewrite these operands based on the IT 665 // context as a post-pass. 666 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 667 unsigned CC; 668 if (!ITBlock.empty()) { 669 CC = ITBlock.back(); 670 ITBlock.pop_back(); 671 } else 672 CC = ARMCC::AL; 673 674 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 675 MCInst::iterator I = MI.begin(); 676 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 677 for (unsigned i = 0; i < NumOps; ++i, ++I) { 678 if (OpInfo[i].isPredicate() ) { 679 I->setImm(CC); 680 ++I; 681 if (CC == ARMCC::AL) 682 I->setReg(0); 683 else 684 I->setReg(ARM::CPSR); 685 return; 686 } 687 } 688 } 689 690 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 691 const MemoryObject &Region, 692 uint64_t Address, 693 raw_ostream &os, 694 raw_ostream &cs) const { 695 CommentStream = &cs; 696 697 uint8_t bytes[4]; 698 699 assert((STI.getFeatureBits() & ARM::ModeThumb) && 700 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 701 702 // We want to read exactly 2 bytes of data. 703 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 704 Size = 0; 705 return MCDisassembler::Fail; 706 } 707 708 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 709 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 710 if (result != MCDisassembler::Fail) { 711 Size = 2; 712 Check(result, AddThumbPredicate(MI)); 713 return result; 714 } 715 716 MI.clear(); 717 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 718 if (result) { 719 Size = 2; 720 bool InITBlock = !ITBlock.empty(); 721 Check(result, AddThumbPredicate(MI)); 722 AddThumb1SBit(MI, InITBlock); 723 return result; 724 } 725 726 MI.clear(); 727 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 728 if (result != MCDisassembler::Fail) { 729 Size = 2; 730 731 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 732 // the Thumb predicate. 733 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 734 result = MCDisassembler::SoftFail; 735 736 Check(result, AddThumbPredicate(MI)); 737 738 // If we find an IT instruction, we need to parse its condition 739 // code and mask operands so that we can apply them correctly 740 // to the subsequent instructions. 741 if (MI.getOpcode() == ARM::t2IT) { 742 743 // (3 - the number of trailing zeros) is the number of then / else. 744 unsigned firstcond = MI.getOperand(0).getImm(); 745 unsigned Mask = MI.getOperand(1).getImm(); 746 unsigned CondBit0 = Mask >> 4 & 1; 747 unsigned NumTZ = CountTrailingZeros_32(Mask); 748 assert(NumTZ <= 3 && "Invalid IT mask!"); 749 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 750 bool T = ((Mask >> Pos) & 1) == CondBit0; 751 if (T) 752 ITBlock.insert(ITBlock.begin(), firstcond); 753 else 754 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 755 } 756 757 ITBlock.push_back(firstcond); 758 } 759 760 return result; 761 } 762 763 // We want to read exactly 4 bytes of data. 764 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 765 Size = 0; 766 return MCDisassembler::Fail; 767 } 768 769 uint32_t insn32 = (bytes[3] << 8) | 770 (bytes[2] << 0) | 771 (bytes[1] << 24) | 772 (bytes[0] << 16); 773 MI.clear(); 774 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 775 if (result != MCDisassembler::Fail) { 776 Size = 4; 777 bool InITBlock = ITBlock.size(); 778 Check(result, AddThumbPredicate(MI)); 779 AddThumb1SBit(MI, InITBlock); 780 return result; 781 } 782 783 MI.clear(); 784 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 785 if (result != MCDisassembler::Fail) { 786 Size = 4; 787 Check(result, AddThumbPredicate(MI)); 788 return result; 789 } 790 791 MI.clear(); 792 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 793 if (result != MCDisassembler::Fail) { 794 Size = 4; 795 UpdateThumbVFPPredicate(MI); 796 return result; 797 } 798 799 MI.clear(); 800 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 801 if (result != MCDisassembler::Fail) { 802 Size = 4; 803 Check(result, AddThumbPredicate(MI)); 804 return result; 805 } 806 807 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 808 MI.clear(); 809 uint32_t NEONLdStInsn = insn32; 810 NEONLdStInsn &= 0xF0FFFFFF; 811 NEONLdStInsn |= 0x04000000; 812 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 813 if (result != MCDisassembler::Fail) { 814 Size = 4; 815 Check(result, AddThumbPredicate(MI)); 816 return result; 817 } 818 } 819 820 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 821 MI.clear(); 822 uint32_t NEONDataInsn = insn32; 823 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 824 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 825 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 826 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 827 if (result != MCDisassembler::Fail) { 828 Size = 4; 829 Check(result, AddThumbPredicate(MI)); 830 return result; 831 } 832 } 833 834 Size = 0; 835 return MCDisassembler::Fail; 836 } 837 838 839 extern "C" void LLVMInitializeARMDisassembler() { 840 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 841 createARMDisassembler); 842 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 843 createThumbDisassembler); 844 } 845 846 static const unsigned GPRDecoderTable[] = { 847 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 848 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 849 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 850 ARM::R12, ARM::SP, ARM::LR, ARM::PC 851 }; 852 853 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 854 uint64_t Address, const void *Decoder) { 855 if (RegNo > 15) 856 return MCDisassembler::Fail; 857 858 unsigned Register = GPRDecoderTable[RegNo]; 859 Inst.addOperand(MCOperand::CreateReg(Register)); 860 return MCDisassembler::Success; 861 } 862 863 static DecodeStatus 864 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 865 uint64_t Address, const void *Decoder) { 866 if (RegNo == 15) return MCDisassembler::Fail; 867 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 868 } 869 870 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 871 uint64_t Address, const void *Decoder) { 872 if (RegNo > 7) 873 return MCDisassembler::Fail; 874 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 875 } 876 877 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 878 uint64_t Address, const void *Decoder) { 879 unsigned Register = 0; 880 switch (RegNo) { 881 case 0: 882 Register = ARM::R0; 883 break; 884 case 1: 885 Register = ARM::R1; 886 break; 887 case 2: 888 Register = ARM::R2; 889 break; 890 case 3: 891 Register = ARM::R3; 892 break; 893 case 9: 894 Register = ARM::R9; 895 break; 896 case 12: 897 Register = ARM::R12; 898 break; 899 default: 900 return MCDisassembler::Fail; 901 } 902 903 Inst.addOperand(MCOperand::CreateReg(Register)); 904 return MCDisassembler::Success; 905 } 906 907 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 908 uint64_t Address, const void *Decoder) { 909 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 910 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 911 } 912 913 static const unsigned SPRDecoderTable[] = { 914 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 915 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 916 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 917 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 918 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 919 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 920 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 921 ARM::S28, ARM::S29, ARM::S30, ARM::S31 922 }; 923 924 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 925 uint64_t Address, const void *Decoder) { 926 if (RegNo > 31) 927 return MCDisassembler::Fail; 928 929 unsigned Register = SPRDecoderTable[RegNo]; 930 Inst.addOperand(MCOperand::CreateReg(Register)); 931 return MCDisassembler::Success; 932 } 933 934 static const unsigned DPRDecoderTable[] = { 935 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 936 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 937 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 938 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 939 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 940 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 941 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 942 ARM::D28, ARM::D29, ARM::D30, ARM::D31 943 }; 944 945 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 946 uint64_t Address, const void *Decoder) { 947 if (RegNo > 31) 948 return MCDisassembler::Fail; 949 950 unsigned Register = DPRDecoderTable[RegNo]; 951 Inst.addOperand(MCOperand::CreateReg(Register)); 952 return MCDisassembler::Success; 953 } 954 955 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 956 uint64_t Address, const void *Decoder) { 957 if (RegNo > 7) 958 return MCDisassembler::Fail; 959 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 960 } 961 962 static DecodeStatus 963 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 964 uint64_t Address, const void *Decoder) { 965 if (RegNo > 15) 966 return MCDisassembler::Fail; 967 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 968 } 969 970 static const unsigned QPRDecoderTable[] = { 971 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 972 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 973 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 974 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 975 }; 976 977 978 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 979 uint64_t Address, const void *Decoder) { 980 if (RegNo > 31) 981 return MCDisassembler::Fail; 982 RegNo >>= 1; 983 984 unsigned Register = QPRDecoderTable[RegNo]; 985 Inst.addOperand(MCOperand::CreateReg(Register)); 986 return MCDisassembler::Success; 987 } 988 989 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 990 uint64_t Address, const void *Decoder) { 991 if (Val == 0xF) return MCDisassembler::Fail; 992 // AL predicate is not allowed on Thumb1 branches. 993 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 994 return MCDisassembler::Fail; 995 Inst.addOperand(MCOperand::CreateImm(Val)); 996 if (Val == ARMCC::AL) { 997 Inst.addOperand(MCOperand::CreateReg(0)); 998 } else 999 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1000 return MCDisassembler::Success; 1001 } 1002 1003 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1004 uint64_t Address, const void *Decoder) { 1005 if (Val) 1006 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1007 else 1008 Inst.addOperand(MCOperand::CreateReg(0)); 1009 return MCDisassembler::Success; 1010 } 1011 1012 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1013 uint64_t Address, const void *Decoder) { 1014 uint32_t imm = Val & 0xFF; 1015 uint32_t rot = (Val & 0xF00) >> 7; 1016 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1017 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1018 return MCDisassembler::Success; 1019 } 1020 1021 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1022 uint64_t Address, const void *Decoder) { 1023 DecodeStatus S = MCDisassembler::Success; 1024 1025 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1026 unsigned type = fieldFromInstruction32(Val, 5, 2); 1027 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1028 1029 // Register-immediate 1030 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1031 return MCDisassembler::Fail; 1032 1033 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1034 switch (type) { 1035 case 0: 1036 Shift = ARM_AM::lsl; 1037 break; 1038 case 1: 1039 Shift = ARM_AM::lsr; 1040 break; 1041 case 2: 1042 Shift = ARM_AM::asr; 1043 break; 1044 case 3: 1045 Shift = ARM_AM::ror; 1046 break; 1047 } 1048 1049 if (Shift == ARM_AM::ror && imm == 0) 1050 Shift = ARM_AM::rrx; 1051 1052 unsigned Op = Shift | (imm << 3); 1053 Inst.addOperand(MCOperand::CreateImm(Op)); 1054 1055 return S; 1056 } 1057 1058 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1059 uint64_t Address, const void *Decoder) { 1060 DecodeStatus S = MCDisassembler::Success; 1061 1062 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1063 unsigned type = fieldFromInstruction32(Val, 5, 2); 1064 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1065 1066 // Register-register 1067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1068 return MCDisassembler::Fail; 1069 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1070 return MCDisassembler::Fail; 1071 1072 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1073 switch (type) { 1074 case 0: 1075 Shift = ARM_AM::lsl; 1076 break; 1077 case 1: 1078 Shift = ARM_AM::lsr; 1079 break; 1080 case 2: 1081 Shift = ARM_AM::asr; 1082 break; 1083 case 3: 1084 Shift = ARM_AM::ror; 1085 break; 1086 } 1087 1088 Inst.addOperand(MCOperand::CreateImm(Shift)); 1089 1090 return S; 1091 } 1092 1093 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1094 uint64_t Address, const void *Decoder) { 1095 DecodeStatus S = MCDisassembler::Success; 1096 1097 bool writebackLoad = false; 1098 unsigned writebackReg = 0; 1099 switch (Inst.getOpcode()) { 1100 default: 1101 break; 1102 case ARM::LDMIA_UPD: 1103 case ARM::LDMDB_UPD: 1104 case ARM::LDMIB_UPD: 1105 case ARM::LDMDA_UPD: 1106 case ARM::t2LDMIA_UPD: 1107 case ARM::t2LDMDB_UPD: 1108 writebackLoad = true; 1109 writebackReg = Inst.getOperand(0).getReg(); 1110 break; 1111 } 1112 1113 // Empty register lists are not allowed. 1114 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1115 for (unsigned i = 0; i < 16; ++i) { 1116 if (Val & (1 << i)) { 1117 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1118 return MCDisassembler::Fail; 1119 // Writeback not allowed if Rn is in the target list. 1120 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1121 Check(S, MCDisassembler::SoftFail); 1122 } 1123 } 1124 1125 return S; 1126 } 1127 1128 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1129 uint64_t Address, const void *Decoder) { 1130 DecodeStatus S = MCDisassembler::Success; 1131 1132 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1133 unsigned regs = Val & 0xFF; 1134 1135 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1136 return MCDisassembler::Fail; 1137 for (unsigned i = 0; i < (regs - 1); ++i) { 1138 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1139 return MCDisassembler::Fail; 1140 } 1141 1142 return S; 1143 } 1144 1145 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1146 uint64_t Address, const void *Decoder) { 1147 DecodeStatus S = MCDisassembler::Success; 1148 1149 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1150 unsigned regs = (Val & 0xFF) / 2; 1151 1152 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1153 return MCDisassembler::Fail; 1154 for (unsigned i = 0; i < (regs - 1); ++i) { 1155 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1156 return MCDisassembler::Fail; 1157 } 1158 1159 return S; 1160 } 1161 1162 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1163 uint64_t Address, const void *Decoder) { 1164 // This operand encodes a mask of contiguous zeros between a specified MSB 1165 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1166 // the mask of all bits LSB-and-lower, and then xor them to create 1167 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1168 // create the final mask. 1169 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1170 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1171 1172 DecodeStatus S = MCDisassembler::Success; 1173 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1174 1175 uint32_t msb_mask = 0xFFFFFFFF; 1176 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1177 uint32_t lsb_mask = (1U << lsb) - 1; 1178 1179 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1180 return S; 1181 } 1182 1183 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1184 uint64_t Address, const void *Decoder) { 1185 DecodeStatus S = MCDisassembler::Success; 1186 1187 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1188 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1189 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1190 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1191 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1192 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1193 1194 switch (Inst.getOpcode()) { 1195 case ARM::LDC_OFFSET: 1196 case ARM::LDC_PRE: 1197 case ARM::LDC_POST: 1198 case ARM::LDC_OPTION: 1199 case ARM::LDCL_OFFSET: 1200 case ARM::LDCL_PRE: 1201 case ARM::LDCL_POST: 1202 case ARM::LDCL_OPTION: 1203 case ARM::STC_OFFSET: 1204 case ARM::STC_PRE: 1205 case ARM::STC_POST: 1206 case ARM::STC_OPTION: 1207 case ARM::STCL_OFFSET: 1208 case ARM::STCL_PRE: 1209 case ARM::STCL_POST: 1210 case ARM::STCL_OPTION: 1211 case ARM::t2LDC_OFFSET: 1212 case ARM::t2LDC_PRE: 1213 case ARM::t2LDC_POST: 1214 case ARM::t2LDC_OPTION: 1215 case ARM::t2LDCL_OFFSET: 1216 case ARM::t2LDCL_PRE: 1217 case ARM::t2LDCL_POST: 1218 case ARM::t2LDCL_OPTION: 1219 case ARM::t2STC_OFFSET: 1220 case ARM::t2STC_PRE: 1221 case ARM::t2STC_POST: 1222 case ARM::t2STC_OPTION: 1223 case ARM::t2STCL_OFFSET: 1224 case ARM::t2STCL_PRE: 1225 case ARM::t2STCL_POST: 1226 case ARM::t2STCL_OPTION: 1227 if (coproc == 0xA || coproc == 0xB) 1228 return MCDisassembler::Fail; 1229 break; 1230 default: 1231 break; 1232 } 1233 1234 Inst.addOperand(MCOperand::CreateImm(coproc)); 1235 Inst.addOperand(MCOperand::CreateImm(CRd)); 1236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1237 return MCDisassembler::Fail; 1238 1239 switch (Inst.getOpcode()) { 1240 case ARM::t2LDC2_OFFSET: 1241 case ARM::t2LDC2L_OFFSET: 1242 case ARM::t2LDC2_PRE: 1243 case ARM::t2LDC2L_PRE: 1244 case ARM::t2STC2_OFFSET: 1245 case ARM::t2STC2L_OFFSET: 1246 case ARM::t2STC2_PRE: 1247 case ARM::t2STC2L_PRE: 1248 case ARM::LDC2_OFFSET: 1249 case ARM::LDC2L_OFFSET: 1250 case ARM::LDC2_PRE: 1251 case ARM::LDC2L_PRE: 1252 case ARM::STC2_OFFSET: 1253 case ARM::STC2L_OFFSET: 1254 case ARM::STC2_PRE: 1255 case ARM::STC2L_PRE: 1256 case ARM::t2LDC_OFFSET: 1257 case ARM::t2LDCL_OFFSET: 1258 case ARM::t2LDC_PRE: 1259 case ARM::t2LDCL_PRE: 1260 case ARM::t2STC_OFFSET: 1261 case ARM::t2STCL_OFFSET: 1262 case ARM::t2STC_PRE: 1263 case ARM::t2STCL_PRE: 1264 case ARM::LDC_OFFSET: 1265 case ARM::LDCL_OFFSET: 1266 case ARM::LDC_PRE: 1267 case ARM::LDCL_PRE: 1268 case ARM::STC_OFFSET: 1269 case ARM::STCL_OFFSET: 1270 case ARM::STC_PRE: 1271 case ARM::STCL_PRE: 1272 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1273 Inst.addOperand(MCOperand::CreateImm(imm)); 1274 break; 1275 case ARM::t2LDC2_POST: 1276 case ARM::t2LDC2L_POST: 1277 case ARM::t2STC2_POST: 1278 case ARM::t2STC2L_POST: 1279 case ARM::LDC2_POST: 1280 case ARM::LDC2L_POST: 1281 case ARM::STC2_POST: 1282 case ARM::STC2L_POST: 1283 case ARM::t2LDC_POST: 1284 case ARM::t2LDCL_POST: 1285 case ARM::t2STC_POST: 1286 case ARM::t2STCL_POST: 1287 case ARM::LDC_POST: 1288 case ARM::LDCL_POST: 1289 case ARM::STC_POST: 1290 case ARM::STCL_POST: 1291 imm |= U << 8; 1292 // fall through. 1293 default: 1294 // The 'option' variant doesn't encode 'U' in the immediate since 1295 // the immediate is unsigned [0,255]. 1296 Inst.addOperand(MCOperand::CreateImm(imm)); 1297 break; 1298 } 1299 1300 switch (Inst.getOpcode()) { 1301 case ARM::LDC_OFFSET: 1302 case ARM::LDC_PRE: 1303 case ARM::LDC_POST: 1304 case ARM::LDC_OPTION: 1305 case ARM::LDCL_OFFSET: 1306 case ARM::LDCL_PRE: 1307 case ARM::LDCL_POST: 1308 case ARM::LDCL_OPTION: 1309 case ARM::STC_OFFSET: 1310 case ARM::STC_PRE: 1311 case ARM::STC_POST: 1312 case ARM::STC_OPTION: 1313 case ARM::STCL_OFFSET: 1314 case ARM::STCL_PRE: 1315 case ARM::STCL_POST: 1316 case ARM::STCL_OPTION: 1317 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1318 return MCDisassembler::Fail; 1319 break; 1320 default: 1321 break; 1322 } 1323 1324 return S; 1325 } 1326 1327 static DecodeStatus 1328 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1329 uint64_t Address, const void *Decoder) { 1330 DecodeStatus S = MCDisassembler::Success; 1331 1332 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1333 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1334 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1335 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1336 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1337 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1338 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1339 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1340 1341 // On stores, the writeback operand precedes Rt. 1342 switch (Inst.getOpcode()) { 1343 case ARM::STR_POST_IMM: 1344 case ARM::STR_POST_REG: 1345 case ARM::STRB_POST_IMM: 1346 case ARM::STRB_POST_REG: 1347 case ARM::STRT_POST_REG: 1348 case ARM::STRT_POST_IMM: 1349 case ARM::STRBT_POST_REG: 1350 case ARM::STRBT_POST_IMM: 1351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1352 return MCDisassembler::Fail; 1353 break; 1354 default: 1355 break; 1356 } 1357 1358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1359 return MCDisassembler::Fail; 1360 1361 // On loads, the writeback operand comes after Rt. 1362 switch (Inst.getOpcode()) { 1363 case ARM::LDR_POST_IMM: 1364 case ARM::LDR_POST_REG: 1365 case ARM::LDRB_POST_IMM: 1366 case ARM::LDRB_POST_REG: 1367 case ARM::LDRBT_POST_REG: 1368 case ARM::LDRBT_POST_IMM: 1369 case ARM::LDRT_POST_REG: 1370 case ARM::LDRT_POST_IMM: 1371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1372 return MCDisassembler::Fail; 1373 break; 1374 default: 1375 break; 1376 } 1377 1378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1379 return MCDisassembler::Fail; 1380 1381 ARM_AM::AddrOpc Op = ARM_AM::add; 1382 if (!fieldFromInstruction32(Insn, 23, 1)) 1383 Op = ARM_AM::sub; 1384 1385 bool writeback = (P == 0) || (W == 1); 1386 unsigned idx_mode = 0; 1387 if (P && writeback) 1388 idx_mode = ARMII::IndexModePre; 1389 else if (!P && writeback) 1390 idx_mode = ARMII::IndexModePost; 1391 1392 if (writeback && (Rn == 15 || Rn == Rt)) 1393 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1394 1395 if (reg) { 1396 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1397 return MCDisassembler::Fail; 1398 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1399 switch( fieldFromInstruction32(Insn, 5, 2)) { 1400 case 0: 1401 Opc = ARM_AM::lsl; 1402 break; 1403 case 1: 1404 Opc = ARM_AM::lsr; 1405 break; 1406 case 2: 1407 Opc = ARM_AM::asr; 1408 break; 1409 case 3: 1410 Opc = ARM_AM::ror; 1411 break; 1412 default: 1413 return MCDisassembler::Fail; 1414 } 1415 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1416 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1417 1418 Inst.addOperand(MCOperand::CreateImm(imm)); 1419 } else { 1420 Inst.addOperand(MCOperand::CreateReg(0)); 1421 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1422 Inst.addOperand(MCOperand::CreateImm(tmp)); 1423 } 1424 1425 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1426 return MCDisassembler::Fail; 1427 1428 return S; 1429 } 1430 1431 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1432 uint64_t Address, const void *Decoder) { 1433 DecodeStatus S = MCDisassembler::Success; 1434 1435 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1436 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1437 unsigned type = fieldFromInstruction32(Val, 5, 2); 1438 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1439 unsigned U = fieldFromInstruction32(Val, 12, 1); 1440 1441 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1442 switch (type) { 1443 case 0: 1444 ShOp = ARM_AM::lsl; 1445 break; 1446 case 1: 1447 ShOp = ARM_AM::lsr; 1448 break; 1449 case 2: 1450 ShOp = ARM_AM::asr; 1451 break; 1452 case 3: 1453 ShOp = ARM_AM::ror; 1454 break; 1455 } 1456 1457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1458 return MCDisassembler::Fail; 1459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1460 return MCDisassembler::Fail; 1461 unsigned shift; 1462 if (U) 1463 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1464 else 1465 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1466 Inst.addOperand(MCOperand::CreateImm(shift)); 1467 1468 return S; 1469 } 1470 1471 static DecodeStatus 1472 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1473 uint64_t Address, const void *Decoder) { 1474 DecodeStatus S = MCDisassembler::Success; 1475 1476 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1477 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1478 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1479 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1480 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1481 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1482 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1483 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1484 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1485 1486 bool writeback = (W == 1) | (P == 0); 1487 1488 // For {LD,ST}RD, Rt must be even, else undefined. 1489 switch (Inst.getOpcode()) { 1490 case ARM::STRD: 1491 case ARM::STRD_PRE: 1492 case ARM::STRD_POST: 1493 case ARM::LDRD: 1494 case ARM::LDRD_PRE: 1495 case ARM::LDRD_POST: 1496 if (Rt & 0x1) return MCDisassembler::Fail; 1497 break; 1498 default: 1499 break; 1500 } 1501 1502 if (writeback) { // Writeback 1503 if (P) 1504 U |= ARMII::IndexModePre << 9; 1505 else 1506 U |= ARMII::IndexModePost << 9; 1507 1508 // On stores, the writeback operand precedes Rt. 1509 switch (Inst.getOpcode()) { 1510 case ARM::STRD: 1511 case ARM::STRD_PRE: 1512 case ARM::STRD_POST: 1513 case ARM::STRH: 1514 case ARM::STRH_PRE: 1515 case ARM::STRH_POST: 1516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1517 return MCDisassembler::Fail; 1518 break; 1519 default: 1520 break; 1521 } 1522 } 1523 1524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1525 return MCDisassembler::Fail; 1526 switch (Inst.getOpcode()) { 1527 case ARM::STRD: 1528 case ARM::STRD_PRE: 1529 case ARM::STRD_POST: 1530 case ARM::LDRD: 1531 case ARM::LDRD_PRE: 1532 case ARM::LDRD_POST: 1533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1534 return MCDisassembler::Fail; 1535 break; 1536 default: 1537 break; 1538 } 1539 1540 if (writeback) { 1541 // On loads, the writeback operand comes after Rt. 1542 switch (Inst.getOpcode()) { 1543 case ARM::LDRD: 1544 case ARM::LDRD_PRE: 1545 case ARM::LDRD_POST: 1546 case ARM::LDRH: 1547 case ARM::LDRH_PRE: 1548 case ARM::LDRH_POST: 1549 case ARM::LDRSH: 1550 case ARM::LDRSH_PRE: 1551 case ARM::LDRSH_POST: 1552 case ARM::LDRSB: 1553 case ARM::LDRSB_PRE: 1554 case ARM::LDRSB_POST: 1555 case ARM::LDRHTr: 1556 case ARM::LDRSBTr: 1557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1558 return MCDisassembler::Fail; 1559 break; 1560 default: 1561 break; 1562 } 1563 } 1564 1565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1566 return MCDisassembler::Fail; 1567 1568 if (type) { 1569 Inst.addOperand(MCOperand::CreateReg(0)); 1570 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1571 } else { 1572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1573 return MCDisassembler::Fail; 1574 Inst.addOperand(MCOperand::CreateImm(U)); 1575 } 1576 1577 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1578 return MCDisassembler::Fail; 1579 1580 return S; 1581 } 1582 1583 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1584 uint64_t Address, const void *Decoder) { 1585 DecodeStatus S = MCDisassembler::Success; 1586 1587 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1588 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1589 1590 switch (mode) { 1591 case 0: 1592 mode = ARM_AM::da; 1593 break; 1594 case 1: 1595 mode = ARM_AM::ia; 1596 break; 1597 case 2: 1598 mode = ARM_AM::db; 1599 break; 1600 case 3: 1601 mode = ARM_AM::ib; 1602 break; 1603 } 1604 1605 Inst.addOperand(MCOperand::CreateImm(mode)); 1606 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1607 return MCDisassembler::Fail; 1608 1609 return S; 1610 } 1611 1612 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1613 unsigned Insn, 1614 uint64_t Address, const void *Decoder) { 1615 DecodeStatus S = MCDisassembler::Success; 1616 1617 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1618 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1619 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1620 1621 if (pred == 0xF) { 1622 switch (Inst.getOpcode()) { 1623 case ARM::LDMDA: 1624 Inst.setOpcode(ARM::RFEDA); 1625 break; 1626 case ARM::LDMDA_UPD: 1627 Inst.setOpcode(ARM::RFEDA_UPD); 1628 break; 1629 case ARM::LDMDB: 1630 Inst.setOpcode(ARM::RFEDB); 1631 break; 1632 case ARM::LDMDB_UPD: 1633 Inst.setOpcode(ARM::RFEDB_UPD); 1634 break; 1635 case ARM::LDMIA: 1636 Inst.setOpcode(ARM::RFEIA); 1637 break; 1638 case ARM::LDMIA_UPD: 1639 Inst.setOpcode(ARM::RFEIA_UPD); 1640 break; 1641 case ARM::LDMIB: 1642 Inst.setOpcode(ARM::RFEIB); 1643 break; 1644 case ARM::LDMIB_UPD: 1645 Inst.setOpcode(ARM::RFEIB_UPD); 1646 break; 1647 case ARM::STMDA: 1648 Inst.setOpcode(ARM::SRSDA); 1649 break; 1650 case ARM::STMDA_UPD: 1651 Inst.setOpcode(ARM::SRSDA_UPD); 1652 break; 1653 case ARM::STMDB: 1654 Inst.setOpcode(ARM::SRSDB); 1655 break; 1656 case ARM::STMDB_UPD: 1657 Inst.setOpcode(ARM::SRSDB_UPD); 1658 break; 1659 case ARM::STMIA: 1660 Inst.setOpcode(ARM::SRSIA); 1661 break; 1662 case ARM::STMIA_UPD: 1663 Inst.setOpcode(ARM::SRSIA_UPD); 1664 break; 1665 case ARM::STMIB: 1666 Inst.setOpcode(ARM::SRSIB); 1667 break; 1668 case ARM::STMIB_UPD: 1669 Inst.setOpcode(ARM::SRSIB_UPD); 1670 break; 1671 default: 1672 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1673 } 1674 1675 // For stores (which become SRS's, the only operand is the mode. 1676 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1677 Inst.addOperand( 1678 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1679 return S; 1680 } 1681 1682 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1683 } 1684 1685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1686 return MCDisassembler::Fail; 1687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1688 return MCDisassembler::Fail; // Tied 1689 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1690 return MCDisassembler::Fail; 1691 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1692 return MCDisassembler::Fail; 1693 1694 return S; 1695 } 1696 1697 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1698 uint64_t Address, const void *Decoder) { 1699 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1700 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1701 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1702 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1703 1704 DecodeStatus S = MCDisassembler::Success; 1705 1706 // imod == '01' --> UNPREDICTABLE 1707 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1708 // return failure here. The '01' imod value is unprintable, so there's 1709 // nothing useful we could do even if we returned UNPREDICTABLE. 1710 1711 if (imod == 1) return MCDisassembler::Fail; 1712 1713 if (imod && M) { 1714 Inst.setOpcode(ARM::CPS3p); 1715 Inst.addOperand(MCOperand::CreateImm(imod)); 1716 Inst.addOperand(MCOperand::CreateImm(iflags)); 1717 Inst.addOperand(MCOperand::CreateImm(mode)); 1718 } else if (imod && !M) { 1719 Inst.setOpcode(ARM::CPS2p); 1720 Inst.addOperand(MCOperand::CreateImm(imod)); 1721 Inst.addOperand(MCOperand::CreateImm(iflags)); 1722 if (mode) S = MCDisassembler::SoftFail; 1723 } else if (!imod && M) { 1724 Inst.setOpcode(ARM::CPS1p); 1725 Inst.addOperand(MCOperand::CreateImm(mode)); 1726 if (iflags) S = MCDisassembler::SoftFail; 1727 } else { 1728 // imod == '00' && M == '0' --> UNPREDICTABLE 1729 Inst.setOpcode(ARM::CPS1p); 1730 Inst.addOperand(MCOperand::CreateImm(mode)); 1731 S = MCDisassembler::SoftFail; 1732 } 1733 1734 return S; 1735 } 1736 1737 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1738 uint64_t Address, const void *Decoder) { 1739 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1740 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1741 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1742 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1743 1744 DecodeStatus S = MCDisassembler::Success; 1745 1746 // imod == '01' --> UNPREDICTABLE 1747 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1748 // return failure here. The '01' imod value is unprintable, so there's 1749 // nothing useful we could do even if we returned UNPREDICTABLE. 1750 1751 if (imod == 1) return MCDisassembler::Fail; 1752 1753 if (imod && M) { 1754 Inst.setOpcode(ARM::t2CPS3p); 1755 Inst.addOperand(MCOperand::CreateImm(imod)); 1756 Inst.addOperand(MCOperand::CreateImm(iflags)); 1757 Inst.addOperand(MCOperand::CreateImm(mode)); 1758 } else if (imod && !M) { 1759 Inst.setOpcode(ARM::t2CPS2p); 1760 Inst.addOperand(MCOperand::CreateImm(imod)); 1761 Inst.addOperand(MCOperand::CreateImm(iflags)); 1762 if (mode) S = MCDisassembler::SoftFail; 1763 } else if (!imod && M) { 1764 Inst.setOpcode(ARM::t2CPS1p); 1765 Inst.addOperand(MCOperand::CreateImm(mode)); 1766 if (iflags) S = MCDisassembler::SoftFail; 1767 } else { 1768 // imod == '00' && M == '0' --> UNPREDICTABLE 1769 Inst.setOpcode(ARM::t2CPS1p); 1770 Inst.addOperand(MCOperand::CreateImm(mode)); 1771 S = MCDisassembler::SoftFail; 1772 } 1773 1774 return S; 1775 } 1776 1777 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1778 uint64_t Address, const void *Decoder) { 1779 DecodeStatus S = MCDisassembler::Success; 1780 1781 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1782 unsigned imm = 0; 1783 1784 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1785 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1786 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1787 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1788 1789 if (Inst.getOpcode() == ARM::t2MOVTi16) 1790 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1791 return MCDisassembler::Fail; 1792 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1793 return MCDisassembler::Fail; 1794 1795 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1796 Inst.addOperand(MCOperand::CreateImm(imm)); 1797 1798 return S; 1799 } 1800 1801 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1802 uint64_t Address, const void *Decoder) { 1803 DecodeStatus S = MCDisassembler::Success; 1804 1805 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1806 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1807 unsigned imm = 0; 1808 1809 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1810 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1811 1812 if (Inst.getOpcode() == ARM::MOVTi16) 1813 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1814 return MCDisassembler::Fail; 1815 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1816 return MCDisassembler::Fail; 1817 1818 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1819 Inst.addOperand(MCOperand::CreateImm(imm)); 1820 1821 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1822 return MCDisassembler::Fail; 1823 1824 return S; 1825 } 1826 1827 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1828 uint64_t Address, const void *Decoder) { 1829 DecodeStatus S = MCDisassembler::Success; 1830 1831 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1832 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1833 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1834 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1835 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1836 1837 if (pred == 0xF) 1838 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1839 1840 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1841 return MCDisassembler::Fail; 1842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1843 return MCDisassembler::Fail; 1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1845 return MCDisassembler::Fail; 1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1847 return MCDisassembler::Fail; 1848 1849 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1850 return MCDisassembler::Fail; 1851 1852 return S; 1853 } 1854 1855 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1856 uint64_t Address, const void *Decoder) { 1857 DecodeStatus S = MCDisassembler::Success; 1858 1859 unsigned add = fieldFromInstruction32(Val, 12, 1); 1860 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1861 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1862 1863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1864 return MCDisassembler::Fail; 1865 1866 if (!add) imm *= -1; 1867 if (imm == 0 && !add) imm = INT32_MIN; 1868 Inst.addOperand(MCOperand::CreateImm(imm)); 1869 if (Rn == 15) 1870 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1871 1872 return S; 1873 } 1874 1875 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1876 uint64_t Address, const void *Decoder) { 1877 DecodeStatus S = MCDisassembler::Success; 1878 1879 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1880 unsigned U = fieldFromInstruction32(Val, 8, 1); 1881 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1882 1883 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1884 return MCDisassembler::Fail; 1885 1886 if (U) 1887 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1888 else 1889 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1890 1891 return S; 1892 } 1893 1894 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1895 uint64_t Address, const void *Decoder) { 1896 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1897 } 1898 1899 static DecodeStatus 1900 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1901 uint64_t Address, const void *Decoder) { 1902 DecodeStatus S = MCDisassembler::Success; 1903 1904 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1905 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1906 1907 if (pred == 0xF) { 1908 Inst.setOpcode(ARM::BLXi); 1909 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1910 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1911 return S; 1912 } 1913 1914 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true, 1915 4, Inst, Decoder)) 1916 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1917 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1918 return MCDisassembler::Fail; 1919 1920 return S; 1921 } 1922 1923 1924 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1925 uint64_t Address, const void *Decoder) { 1926 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1927 return MCDisassembler::Success; 1928 } 1929 1930 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1931 uint64_t Address, const void *Decoder) { 1932 DecodeStatus S = MCDisassembler::Success; 1933 1934 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1935 unsigned align = fieldFromInstruction32(Val, 4, 2); 1936 1937 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1938 return MCDisassembler::Fail; 1939 if (!align) 1940 Inst.addOperand(MCOperand::CreateImm(0)); 1941 else 1942 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1943 1944 return S; 1945 } 1946 1947 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1948 uint64_t Address, const void *Decoder) { 1949 DecodeStatus S = MCDisassembler::Success; 1950 1951 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1952 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1953 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1954 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1955 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1956 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1957 1958 // First output register 1959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1960 return MCDisassembler::Fail; 1961 1962 // Second output register 1963 switch (Inst.getOpcode()) { 1964 case ARM::VLD3d8: 1965 case ARM::VLD3d16: 1966 case ARM::VLD3d32: 1967 case ARM::VLD3d8_UPD: 1968 case ARM::VLD3d16_UPD: 1969 case ARM::VLD3d32_UPD: 1970 case ARM::VLD4d8: 1971 case ARM::VLD4d16: 1972 case ARM::VLD4d32: 1973 case ARM::VLD4d8_UPD: 1974 case ARM::VLD4d16_UPD: 1975 case ARM::VLD4d32_UPD: 1976 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1977 return MCDisassembler::Fail; 1978 break; 1979 case ARM::VLD3q8: 1980 case ARM::VLD3q16: 1981 case ARM::VLD3q32: 1982 case ARM::VLD3q8_UPD: 1983 case ARM::VLD3q16_UPD: 1984 case ARM::VLD3q32_UPD: 1985 case ARM::VLD4q8: 1986 case ARM::VLD4q16: 1987 case ARM::VLD4q32: 1988 case ARM::VLD4q8_UPD: 1989 case ARM::VLD4q16_UPD: 1990 case ARM::VLD4q32_UPD: 1991 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1992 return MCDisassembler::Fail; 1993 default: 1994 break; 1995 } 1996 1997 // Third output register 1998 switch(Inst.getOpcode()) { 1999 case ARM::VLD3d8: 2000 case ARM::VLD3d16: 2001 case ARM::VLD3d32: 2002 case ARM::VLD3d8_UPD: 2003 case ARM::VLD3d16_UPD: 2004 case ARM::VLD3d32_UPD: 2005 case ARM::VLD4d8: 2006 case ARM::VLD4d16: 2007 case ARM::VLD4d32: 2008 case ARM::VLD4d8_UPD: 2009 case ARM::VLD4d16_UPD: 2010 case ARM::VLD4d32_UPD: 2011 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2012 return MCDisassembler::Fail; 2013 break; 2014 case ARM::VLD3q8: 2015 case ARM::VLD3q16: 2016 case ARM::VLD3q32: 2017 case ARM::VLD3q8_UPD: 2018 case ARM::VLD3q16_UPD: 2019 case ARM::VLD3q32_UPD: 2020 case ARM::VLD4q8: 2021 case ARM::VLD4q16: 2022 case ARM::VLD4q32: 2023 case ARM::VLD4q8_UPD: 2024 case ARM::VLD4q16_UPD: 2025 case ARM::VLD4q32_UPD: 2026 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2027 return MCDisassembler::Fail; 2028 break; 2029 default: 2030 break; 2031 } 2032 2033 // Fourth output register 2034 switch (Inst.getOpcode()) { 2035 case ARM::VLD4d8: 2036 case ARM::VLD4d16: 2037 case ARM::VLD4d32: 2038 case ARM::VLD4d8_UPD: 2039 case ARM::VLD4d16_UPD: 2040 case ARM::VLD4d32_UPD: 2041 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2042 return MCDisassembler::Fail; 2043 break; 2044 case ARM::VLD4q8: 2045 case ARM::VLD4q16: 2046 case ARM::VLD4q32: 2047 case ARM::VLD4q8_UPD: 2048 case ARM::VLD4q16_UPD: 2049 case ARM::VLD4q32_UPD: 2050 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2051 return MCDisassembler::Fail; 2052 break; 2053 default: 2054 break; 2055 } 2056 2057 // Writeback operand 2058 switch (Inst.getOpcode()) { 2059 case ARM::VLD1d8wb_fixed: 2060 case ARM::VLD1d16wb_fixed: 2061 case ARM::VLD1d32wb_fixed: 2062 case ARM::VLD1d64wb_fixed: 2063 case ARM::VLD1d8wb_register: 2064 case ARM::VLD1d16wb_register: 2065 case ARM::VLD1d32wb_register: 2066 case ARM::VLD1d64wb_register: 2067 case ARM::VLD1q8wb_fixed: 2068 case ARM::VLD1q16wb_fixed: 2069 case ARM::VLD1q32wb_fixed: 2070 case ARM::VLD1q64wb_fixed: 2071 case ARM::VLD1q8wb_register: 2072 case ARM::VLD1q16wb_register: 2073 case ARM::VLD1q32wb_register: 2074 case ARM::VLD1q64wb_register: 2075 case ARM::VLD1d8Twb_fixed: 2076 case ARM::VLD1d8Twb_register: 2077 case ARM::VLD1d16Twb_fixed: 2078 case ARM::VLD1d16Twb_register: 2079 case ARM::VLD1d32Twb_fixed: 2080 case ARM::VLD1d32Twb_register: 2081 case ARM::VLD1d64Twb_fixed: 2082 case ARM::VLD1d64Twb_register: 2083 case ARM::VLD1d8Qwb_fixed: 2084 case ARM::VLD1d8Qwb_register: 2085 case ARM::VLD1d16Qwb_fixed: 2086 case ARM::VLD1d16Qwb_register: 2087 case ARM::VLD1d32Qwb_fixed: 2088 case ARM::VLD1d32Qwb_register: 2089 case ARM::VLD1d64Qwb_fixed: 2090 case ARM::VLD1d64Qwb_register: 2091 case ARM::VLD2d8_UPD: 2092 case ARM::VLD2d16_UPD: 2093 case ARM::VLD2d32_UPD: 2094 case ARM::VLD2q8_UPD: 2095 case ARM::VLD2q16_UPD: 2096 case ARM::VLD2q32_UPD: 2097 case ARM::VLD2b8_UPD: 2098 case ARM::VLD2b16_UPD: 2099 case ARM::VLD2b32_UPD: 2100 case ARM::VLD3d8_UPD: 2101 case ARM::VLD3d16_UPD: 2102 case ARM::VLD3d32_UPD: 2103 case ARM::VLD3q8_UPD: 2104 case ARM::VLD3q16_UPD: 2105 case ARM::VLD3q32_UPD: 2106 case ARM::VLD4d8_UPD: 2107 case ARM::VLD4d16_UPD: 2108 case ARM::VLD4d32_UPD: 2109 case ARM::VLD4q8_UPD: 2110 case ARM::VLD4q16_UPD: 2111 case ARM::VLD4q32_UPD: 2112 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2113 return MCDisassembler::Fail; 2114 break; 2115 default: 2116 break; 2117 } 2118 2119 // AddrMode6 Base (register+alignment) 2120 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2121 return MCDisassembler::Fail; 2122 2123 // AddrMode6 Offset (register) 2124 switch (Inst.getOpcode()) { 2125 default: 2126 // The below have been updated to have explicit am6offset split 2127 // between fixed and register offset. For those instructions not 2128 // yet updated, we need to add an additional reg0 operand for the 2129 // fixed variant. 2130 // 2131 // The fixed offset encodes as Rm == 0xd, so we check for that. 2132 if (Rm == 0xd) { 2133 Inst.addOperand(MCOperand::CreateReg(0)); 2134 break; 2135 } 2136 // Fall through to handle the register offset variant. 2137 case ARM::VLD1d8wb_fixed: 2138 case ARM::VLD1d16wb_fixed: 2139 case ARM::VLD1d32wb_fixed: 2140 case ARM::VLD1d64wb_fixed: 2141 case ARM::VLD1d8Twb_fixed: 2142 case ARM::VLD1d16Twb_fixed: 2143 case ARM::VLD1d32Twb_fixed: 2144 case ARM::VLD1d64Twb_fixed: 2145 case ARM::VLD1d8Qwb_fixed: 2146 case ARM::VLD1d16Qwb_fixed: 2147 case ARM::VLD1d32Qwb_fixed: 2148 case ARM::VLD1d64Qwb_fixed: 2149 case ARM::VLD1d8wb_register: 2150 case ARM::VLD1d16wb_register: 2151 case ARM::VLD1d32wb_register: 2152 case ARM::VLD1d64wb_register: 2153 case ARM::VLD1q8wb_fixed: 2154 case ARM::VLD1q16wb_fixed: 2155 case ARM::VLD1q32wb_fixed: 2156 case ARM::VLD1q64wb_fixed: 2157 case ARM::VLD1q8wb_register: 2158 case ARM::VLD1q16wb_register: 2159 case ARM::VLD1q32wb_register: 2160 case ARM::VLD1q64wb_register: 2161 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2162 // variant encodes Rm == 0xf. Anything else is a register offset post- 2163 // increment and we need to add the register operand to the instruction. 2164 if (Rm != 0xD && Rm != 0xF && 2165 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2166 return MCDisassembler::Fail; 2167 break; 2168 } 2169 2170 return S; 2171 } 2172 2173 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2174 uint64_t Address, const void *Decoder) { 2175 DecodeStatus S = MCDisassembler::Success; 2176 2177 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2178 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2179 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2180 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2181 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2182 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2183 2184 // Writeback Operand 2185 switch (Inst.getOpcode()) { 2186 case ARM::VST1d8wb_fixed: 2187 case ARM::VST1d16wb_fixed: 2188 case ARM::VST1d32wb_fixed: 2189 case ARM::VST1d64wb_fixed: 2190 case ARM::VST1d8wb_register: 2191 case ARM::VST1d16wb_register: 2192 case ARM::VST1d32wb_register: 2193 case ARM::VST1d64wb_register: 2194 case ARM::VST1q8wb_fixed: 2195 case ARM::VST1q16wb_fixed: 2196 case ARM::VST1q32wb_fixed: 2197 case ARM::VST1q64wb_fixed: 2198 case ARM::VST1q8wb_register: 2199 case ARM::VST1q16wb_register: 2200 case ARM::VST1q32wb_register: 2201 case ARM::VST1q64wb_register: 2202 case ARM::VST1d8T_UPD: 2203 case ARM::VST1d16T_UPD: 2204 case ARM::VST1d32T_UPD: 2205 case ARM::VST1d64T_UPD: 2206 case ARM::VST1d8Q_UPD: 2207 case ARM::VST1d16Q_UPD: 2208 case ARM::VST1d32Q_UPD: 2209 case ARM::VST1d64Q_UPD: 2210 case ARM::VST2d8_UPD: 2211 case ARM::VST2d16_UPD: 2212 case ARM::VST2d32_UPD: 2213 case ARM::VST2q8_UPD: 2214 case ARM::VST2q16_UPD: 2215 case ARM::VST2q32_UPD: 2216 case ARM::VST2b8_UPD: 2217 case ARM::VST2b16_UPD: 2218 case ARM::VST2b32_UPD: 2219 case ARM::VST3d8_UPD: 2220 case ARM::VST3d16_UPD: 2221 case ARM::VST3d32_UPD: 2222 case ARM::VST3q8_UPD: 2223 case ARM::VST3q16_UPD: 2224 case ARM::VST3q32_UPD: 2225 case ARM::VST4d8_UPD: 2226 case ARM::VST4d16_UPD: 2227 case ARM::VST4d32_UPD: 2228 case ARM::VST4q8_UPD: 2229 case ARM::VST4q16_UPD: 2230 case ARM::VST4q32_UPD: 2231 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2232 return MCDisassembler::Fail; 2233 break; 2234 default: 2235 break; 2236 } 2237 2238 // AddrMode6 Base (register+alignment) 2239 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2240 return MCDisassembler::Fail; 2241 2242 // AddrMode6 Offset (register) 2243 switch (Inst.getOpcode()) { 2244 default: 2245 if (Rm == 0xD) 2246 Inst.addOperand(MCOperand::CreateReg(0)); 2247 else if (Rm != 0xF) { 2248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2249 return MCDisassembler::Fail; 2250 } 2251 break; 2252 case ARM::VST1d8wb_fixed: 2253 case ARM::VST1d16wb_fixed: 2254 case ARM::VST1d32wb_fixed: 2255 case ARM::VST1d64wb_fixed: 2256 case ARM::VST1q8wb_fixed: 2257 case ARM::VST1q16wb_fixed: 2258 case ARM::VST1q32wb_fixed: 2259 case ARM::VST1q64wb_fixed: 2260 break; 2261 } 2262 2263 2264 // First input register 2265 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2266 return MCDisassembler::Fail; 2267 2268 // Second input register 2269 switch (Inst.getOpcode()) { 2270 case ARM::VST1d8T: 2271 case ARM::VST1d16T: 2272 case ARM::VST1d32T: 2273 case ARM::VST1d64T: 2274 case ARM::VST1d8T_UPD: 2275 case ARM::VST1d16T_UPD: 2276 case ARM::VST1d32T_UPD: 2277 case ARM::VST1d64T_UPD: 2278 case ARM::VST1d8Q: 2279 case ARM::VST1d16Q: 2280 case ARM::VST1d32Q: 2281 case ARM::VST1d64Q: 2282 case ARM::VST1d8Q_UPD: 2283 case ARM::VST1d16Q_UPD: 2284 case ARM::VST1d32Q_UPD: 2285 case ARM::VST1d64Q_UPD: 2286 case ARM::VST2d8: 2287 case ARM::VST2d16: 2288 case ARM::VST2d32: 2289 case ARM::VST2d8_UPD: 2290 case ARM::VST2d16_UPD: 2291 case ARM::VST2d32_UPD: 2292 case ARM::VST2q8: 2293 case ARM::VST2q16: 2294 case ARM::VST2q32: 2295 case ARM::VST2q8_UPD: 2296 case ARM::VST2q16_UPD: 2297 case ARM::VST2q32_UPD: 2298 case ARM::VST3d8: 2299 case ARM::VST3d16: 2300 case ARM::VST3d32: 2301 case ARM::VST3d8_UPD: 2302 case ARM::VST3d16_UPD: 2303 case ARM::VST3d32_UPD: 2304 case ARM::VST4d8: 2305 case ARM::VST4d16: 2306 case ARM::VST4d32: 2307 case ARM::VST4d8_UPD: 2308 case ARM::VST4d16_UPD: 2309 case ARM::VST4d32_UPD: 2310 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2311 return MCDisassembler::Fail; 2312 break; 2313 case ARM::VST2b8: 2314 case ARM::VST2b16: 2315 case ARM::VST2b32: 2316 case ARM::VST2b8_UPD: 2317 case ARM::VST2b16_UPD: 2318 case ARM::VST2b32_UPD: 2319 case ARM::VST3q8: 2320 case ARM::VST3q16: 2321 case ARM::VST3q32: 2322 case ARM::VST3q8_UPD: 2323 case ARM::VST3q16_UPD: 2324 case ARM::VST3q32_UPD: 2325 case ARM::VST4q8: 2326 case ARM::VST4q16: 2327 case ARM::VST4q32: 2328 case ARM::VST4q8_UPD: 2329 case ARM::VST4q16_UPD: 2330 case ARM::VST4q32_UPD: 2331 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2332 return MCDisassembler::Fail; 2333 break; 2334 default: 2335 break; 2336 } 2337 2338 // Third input register 2339 switch (Inst.getOpcode()) { 2340 case ARM::VST1d8T: 2341 case ARM::VST1d16T: 2342 case ARM::VST1d32T: 2343 case ARM::VST1d64T: 2344 case ARM::VST1d8T_UPD: 2345 case ARM::VST1d16T_UPD: 2346 case ARM::VST1d32T_UPD: 2347 case ARM::VST1d64T_UPD: 2348 case ARM::VST1d8Q: 2349 case ARM::VST1d16Q: 2350 case ARM::VST1d32Q: 2351 case ARM::VST1d64Q: 2352 case ARM::VST1d8Q_UPD: 2353 case ARM::VST1d16Q_UPD: 2354 case ARM::VST1d32Q_UPD: 2355 case ARM::VST1d64Q_UPD: 2356 case ARM::VST2q8: 2357 case ARM::VST2q16: 2358 case ARM::VST2q32: 2359 case ARM::VST2q8_UPD: 2360 case ARM::VST2q16_UPD: 2361 case ARM::VST2q32_UPD: 2362 case ARM::VST3d8: 2363 case ARM::VST3d16: 2364 case ARM::VST3d32: 2365 case ARM::VST3d8_UPD: 2366 case ARM::VST3d16_UPD: 2367 case ARM::VST3d32_UPD: 2368 case ARM::VST4d8: 2369 case ARM::VST4d16: 2370 case ARM::VST4d32: 2371 case ARM::VST4d8_UPD: 2372 case ARM::VST4d16_UPD: 2373 case ARM::VST4d32_UPD: 2374 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2375 return MCDisassembler::Fail; 2376 break; 2377 case ARM::VST3q8: 2378 case ARM::VST3q16: 2379 case ARM::VST3q32: 2380 case ARM::VST3q8_UPD: 2381 case ARM::VST3q16_UPD: 2382 case ARM::VST3q32_UPD: 2383 case ARM::VST4q8: 2384 case ARM::VST4q16: 2385 case ARM::VST4q32: 2386 case ARM::VST4q8_UPD: 2387 case ARM::VST4q16_UPD: 2388 case ARM::VST4q32_UPD: 2389 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2390 return MCDisassembler::Fail; 2391 break; 2392 default: 2393 break; 2394 } 2395 2396 // Fourth input register 2397 switch (Inst.getOpcode()) { 2398 case ARM::VST1d8Q: 2399 case ARM::VST1d16Q: 2400 case ARM::VST1d32Q: 2401 case ARM::VST1d64Q: 2402 case ARM::VST1d8Q_UPD: 2403 case ARM::VST1d16Q_UPD: 2404 case ARM::VST1d32Q_UPD: 2405 case ARM::VST1d64Q_UPD: 2406 case ARM::VST2q8: 2407 case ARM::VST2q16: 2408 case ARM::VST2q32: 2409 case ARM::VST2q8_UPD: 2410 case ARM::VST2q16_UPD: 2411 case ARM::VST2q32_UPD: 2412 case ARM::VST4d8: 2413 case ARM::VST4d16: 2414 case ARM::VST4d32: 2415 case ARM::VST4d8_UPD: 2416 case ARM::VST4d16_UPD: 2417 case ARM::VST4d32_UPD: 2418 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2419 return MCDisassembler::Fail; 2420 break; 2421 case ARM::VST4q8: 2422 case ARM::VST4q16: 2423 case ARM::VST4q32: 2424 case ARM::VST4q8_UPD: 2425 case ARM::VST4q16_UPD: 2426 case ARM::VST4q32_UPD: 2427 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2428 return MCDisassembler::Fail; 2429 break; 2430 default: 2431 break; 2432 } 2433 2434 return S; 2435 } 2436 2437 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2438 uint64_t Address, const void *Decoder) { 2439 DecodeStatus S = MCDisassembler::Success; 2440 2441 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2442 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2443 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2444 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2445 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2446 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2447 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 2448 2449 align *= (1 << size); 2450 2451 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2452 return MCDisassembler::Fail; 2453 if (regs == 2) { 2454 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2455 return MCDisassembler::Fail; 2456 } 2457 if (Rm != 0xF) { 2458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2459 return MCDisassembler::Fail; 2460 } 2461 2462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2463 return MCDisassembler::Fail; 2464 Inst.addOperand(MCOperand::CreateImm(align)); 2465 2466 if (Rm == 0xD) 2467 Inst.addOperand(MCOperand::CreateReg(0)); 2468 else if (Rm != 0xF) { 2469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2470 return MCDisassembler::Fail; 2471 } 2472 2473 return S; 2474 } 2475 2476 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2477 uint64_t Address, const void *Decoder) { 2478 DecodeStatus S = MCDisassembler::Success; 2479 2480 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2481 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2482 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2483 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2484 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2485 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2486 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2487 align *= 2*size; 2488 2489 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2490 return MCDisassembler::Fail; 2491 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2492 return MCDisassembler::Fail; 2493 if (Rm != 0xF) { 2494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2495 return MCDisassembler::Fail; 2496 } 2497 2498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2499 return MCDisassembler::Fail; 2500 Inst.addOperand(MCOperand::CreateImm(align)); 2501 2502 if (Rm == 0xD) 2503 Inst.addOperand(MCOperand::CreateReg(0)); 2504 else if (Rm != 0xF) { 2505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2506 return MCDisassembler::Fail; 2507 } 2508 2509 return S; 2510 } 2511 2512 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2513 uint64_t Address, const void *Decoder) { 2514 DecodeStatus S = MCDisassembler::Success; 2515 2516 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2517 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2518 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2519 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2520 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2521 2522 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2523 return MCDisassembler::Fail; 2524 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2525 return MCDisassembler::Fail; 2526 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2527 return MCDisassembler::Fail; 2528 if (Rm != 0xF) { 2529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2530 return MCDisassembler::Fail; 2531 } 2532 2533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 Inst.addOperand(MCOperand::CreateImm(0)); 2536 2537 if (Rm == 0xD) 2538 Inst.addOperand(MCOperand::CreateReg(0)); 2539 else if (Rm != 0xF) { 2540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2541 return MCDisassembler::Fail; 2542 } 2543 2544 return S; 2545 } 2546 2547 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2548 uint64_t Address, const void *Decoder) { 2549 DecodeStatus S = MCDisassembler::Success; 2550 2551 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2552 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2553 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2554 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2555 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2556 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2557 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2558 2559 if (size == 0x3) { 2560 size = 4; 2561 align = 16; 2562 } else { 2563 if (size == 2) { 2564 size = 1 << size; 2565 align *= 8; 2566 } else { 2567 size = 1 << size; 2568 align *= 4*size; 2569 } 2570 } 2571 2572 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2573 return MCDisassembler::Fail; 2574 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2575 return MCDisassembler::Fail; 2576 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2577 return MCDisassembler::Fail; 2578 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2579 return MCDisassembler::Fail; 2580 if (Rm != 0xF) { 2581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2582 return MCDisassembler::Fail; 2583 } 2584 2585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2586 return MCDisassembler::Fail; 2587 Inst.addOperand(MCOperand::CreateImm(align)); 2588 2589 if (Rm == 0xD) 2590 Inst.addOperand(MCOperand::CreateReg(0)); 2591 else if (Rm != 0xF) { 2592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2593 return MCDisassembler::Fail; 2594 } 2595 2596 return S; 2597 } 2598 2599 static DecodeStatus 2600 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2601 uint64_t Address, const void *Decoder) { 2602 DecodeStatus S = MCDisassembler::Success; 2603 2604 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2605 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2606 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2607 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2608 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2609 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2610 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2611 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2612 2613 if (Q) { 2614 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2615 return MCDisassembler::Fail; 2616 } else { 2617 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2618 return MCDisassembler::Fail; 2619 } 2620 2621 Inst.addOperand(MCOperand::CreateImm(imm)); 2622 2623 switch (Inst.getOpcode()) { 2624 case ARM::VORRiv4i16: 2625 case ARM::VORRiv2i32: 2626 case ARM::VBICiv4i16: 2627 case ARM::VBICiv2i32: 2628 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2629 return MCDisassembler::Fail; 2630 break; 2631 case ARM::VORRiv8i16: 2632 case ARM::VORRiv4i32: 2633 case ARM::VBICiv8i16: 2634 case ARM::VBICiv4i32: 2635 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2636 return MCDisassembler::Fail; 2637 break; 2638 default: 2639 break; 2640 } 2641 2642 return S; 2643 } 2644 2645 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2646 uint64_t Address, const void *Decoder) { 2647 DecodeStatus S = MCDisassembler::Success; 2648 2649 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2650 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2651 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2652 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2653 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2654 2655 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2656 return MCDisassembler::Fail; 2657 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2658 return MCDisassembler::Fail; 2659 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2660 2661 return S; 2662 } 2663 2664 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2665 uint64_t Address, const void *Decoder) { 2666 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2667 return MCDisassembler::Success; 2668 } 2669 2670 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2671 uint64_t Address, const void *Decoder) { 2672 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2673 return MCDisassembler::Success; 2674 } 2675 2676 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2677 uint64_t Address, const void *Decoder) { 2678 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2679 return MCDisassembler::Success; 2680 } 2681 2682 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2683 uint64_t Address, const void *Decoder) { 2684 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2685 return MCDisassembler::Success; 2686 } 2687 2688 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2689 uint64_t Address, const void *Decoder) { 2690 DecodeStatus S = MCDisassembler::Success; 2691 2692 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2693 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2694 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2695 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2696 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2697 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2698 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2699 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2700 2701 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2702 return MCDisassembler::Fail; 2703 if (op) { 2704 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2705 return MCDisassembler::Fail; // Writeback 2706 } 2707 2708 for (unsigned i = 0; i < length; ++i) { 2709 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder))) 2710 return MCDisassembler::Fail; 2711 } 2712 2713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2714 return MCDisassembler::Fail; 2715 2716 return S; 2717 } 2718 2719 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2720 uint64_t Address, const void *Decoder) { 2721 DecodeStatus S = MCDisassembler::Success; 2722 2723 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2724 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2725 2726 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2727 return MCDisassembler::Fail; 2728 2729 switch(Inst.getOpcode()) { 2730 default: 2731 return MCDisassembler::Fail; 2732 case ARM::tADR: 2733 break; // tADR does not explicitly represent the PC as an operand. 2734 case ARM::tADDrSPi: 2735 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2736 break; 2737 } 2738 2739 Inst.addOperand(MCOperand::CreateImm(imm)); 2740 return S; 2741 } 2742 2743 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2744 uint64_t Address, const void *Decoder) { 2745 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2746 return MCDisassembler::Success; 2747 } 2748 2749 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2750 uint64_t Address, const void *Decoder) { 2751 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2752 return MCDisassembler::Success; 2753 } 2754 2755 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2756 uint64_t Address, const void *Decoder) { 2757 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2758 return MCDisassembler::Success; 2759 } 2760 2761 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2762 uint64_t Address, const void *Decoder) { 2763 DecodeStatus S = MCDisassembler::Success; 2764 2765 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2766 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2767 2768 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2769 return MCDisassembler::Fail; 2770 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2771 return MCDisassembler::Fail; 2772 2773 return S; 2774 } 2775 2776 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2777 uint64_t Address, const void *Decoder) { 2778 DecodeStatus S = MCDisassembler::Success; 2779 2780 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2781 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2782 2783 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2784 return MCDisassembler::Fail; 2785 Inst.addOperand(MCOperand::CreateImm(imm)); 2786 2787 return S; 2788 } 2789 2790 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2791 uint64_t Address, const void *Decoder) { 2792 unsigned imm = Val << 2; 2793 2794 Inst.addOperand(MCOperand::CreateImm(imm)); 2795 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2796 2797 return MCDisassembler::Success; 2798 } 2799 2800 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2801 uint64_t Address, const void *Decoder) { 2802 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2803 Inst.addOperand(MCOperand::CreateImm(Val)); 2804 2805 return MCDisassembler::Success; 2806 } 2807 2808 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2809 uint64_t Address, const void *Decoder) { 2810 DecodeStatus S = MCDisassembler::Success; 2811 2812 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2813 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2814 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2815 2816 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2817 return MCDisassembler::Fail; 2818 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2819 return MCDisassembler::Fail; 2820 Inst.addOperand(MCOperand::CreateImm(imm)); 2821 2822 return S; 2823 } 2824 2825 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2826 uint64_t Address, const void *Decoder) { 2827 DecodeStatus S = MCDisassembler::Success; 2828 2829 switch (Inst.getOpcode()) { 2830 case ARM::t2PLDs: 2831 case ARM::t2PLDWs: 2832 case ARM::t2PLIs: 2833 break; 2834 default: { 2835 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2836 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2837 return MCDisassembler::Fail; 2838 } 2839 } 2840 2841 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2842 if (Rn == 0xF) { 2843 switch (Inst.getOpcode()) { 2844 case ARM::t2LDRBs: 2845 Inst.setOpcode(ARM::t2LDRBpci); 2846 break; 2847 case ARM::t2LDRHs: 2848 Inst.setOpcode(ARM::t2LDRHpci); 2849 break; 2850 case ARM::t2LDRSHs: 2851 Inst.setOpcode(ARM::t2LDRSHpci); 2852 break; 2853 case ARM::t2LDRSBs: 2854 Inst.setOpcode(ARM::t2LDRSBpci); 2855 break; 2856 case ARM::t2PLDs: 2857 Inst.setOpcode(ARM::t2PLDi12); 2858 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2859 break; 2860 default: 2861 return MCDisassembler::Fail; 2862 } 2863 2864 int imm = fieldFromInstruction32(Insn, 0, 12); 2865 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2866 Inst.addOperand(MCOperand::CreateImm(imm)); 2867 2868 return S; 2869 } 2870 2871 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2872 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2873 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2874 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 2877 return S; 2878 } 2879 2880 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2881 uint64_t Address, const void *Decoder) { 2882 int imm = Val & 0xFF; 2883 if (!(Val & 0x100)) imm *= -1; 2884 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2885 2886 return MCDisassembler::Success; 2887 } 2888 2889 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2890 uint64_t Address, const void *Decoder) { 2891 DecodeStatus S = MCDisassembler::Success; 2892 2893 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2894 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2895 2896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2897 return MCDisassembler::Fail; 2898 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2899 return MCDisassembler::Fail; 2900 2901 return S; 2902 } 2903 2904 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2905 uint64_t Address, const void *Decoder) { 2906 DecodeStatus S = MCDisassembler::Success; 2907 2908 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2909 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2910 2911 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2912 return MCDisassembler::Fail; 2913 2914 Inst.addOperand(MCOperand::CreateImm(imm)); 2915 2916 return S; 2917 } 2918 2919 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2920 uint64_t Address, const void *Decoder) { 2921 int imm = Val & 0xFF; 2922 if (Val == 0) 2923 imm = INT32_MIN; 2924 else if (!(Val & 0x100)) 2925 imm *= -1; 2926 Inst.addOperand(MCOperand::CreateImm(imm)); 2927 2928 return MCDisassembler::Success; 2929 } 2930 2931 2932 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2933 uint64_t Address, const void *Decoder) { 2934 DecodeStatus S = MCDisassembler::Success; 2935 2936 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2937 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2938 2939 // Some instructions always use an additive offset. 2940 switch (Inst.getOpcode()) { 2941 case ARM::t2LDRT: 2942 case ARM::t2LDRBT: 2943 case ARM::t2LDRHT: 2944 case ARM::t2LDRSBT: 2945 case ARM::t2LDRSHT: 2946 case ARM::t2STRT: 2947 case ARM::t2STRBT: 2948 case ARM::t2STRHT: 2949 imm |= 0x100; 2950 break; 2951 default: 2952 break; 2953 } 2954 2955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2956 return MCDisassembler::Fail; 2957 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2958 return MCDisassembler::Fail; 2959 2960 return S; 2961 } 2962 2963 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2964 uint64_t Address, const void *Decoder) { 2965 DecodeStatus S = MCDisassembler::Success; 2966 2967 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2968 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2969 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2970 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2971 addr |= Rn << 9; 2972 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2973 2974 if (!load) { 2975 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2976 return MCDisassembler::Fail; 2977 } 2978 2979 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2980 return MCDisassembler::Fail; 2981 2982 if (load) { 2983 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 } 2986 2987 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2988 return MCDisassembler::Fail; 2989 2990 return S; 2991 } 2992 2993 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2994 uint64_t Address, const void *Decoder) { 2995 DecodeStatus S = MCDisassembler::Success; 2996 2997 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2998 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2999 3000 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3001 return MCDisassembler::Fail; 3002 Inst.addOperand(MCOperand::CreateImm(imm)); 3003 3004 return S; 3005 } 3006 3007 3008 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 3009 uint64_t Address, const void *Decoder) { 3010 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 3011 3012 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3013 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3014 Inst.addOperand(MCOperand::CreateImm(imm)); 3015 3016 return MCDisassembler::Success; 3017 } 3018 3019 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 3020 uint64_t Address, const void *Decoder) { 3021 DecodeStatus S = MCDisassembler::Success; 3022 3023 if (Inst.getOpcode() == ARM::tADDrSP) { 3024 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 3025 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 3026 3027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3028 return MCDisassembler::Fail; 3029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3030 return MCDisassembler::Fail; 3031 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3032 } else if (Inst.getOpcode() == ARM::tADDspr) { 3033 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 3034 3035 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3036 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3037 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3038 return MCDisassembler::Fail; 3039 } 3040 3041 return S; 3042 } 3043 3044 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 3045 uint64_t Address, const void *Decoder) { 3046 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 3047 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 3048 3049 Inst.addOperand(MCOperand::CreateImm(imod)); 3050 Inst.addOperand(MCOperand::CreateImm(flags)); 3051 3052 return MCDisassembler::Success; 3053 } 3054 3055 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3056 uint64_t Address, const void *Decoder) { 3057 DecodeStatus S = MCDisassembler::Success; 3058 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3059 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3060 3061 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3062 return MCDisassembler::Fail; 3063 Inst.addOperand(MCOperand::CreateImm(add)); 3064 3065 return S; 3066 } 3067 3068 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3069 uint64_t Address, const void *Decoder) { 3070 if (!tryAddingSymbolicOperand(Address, 3071 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3072 true, 4, Inst, Decoder)) 3073 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3074 return MCDisassembler::Success; 3075 } 3076 3077 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3078 uint64_t Address, const void *Decoder) { 3079 if (Val == 0xA || Val == 0xB) 3080 return MCDisassembler::Fail; 3081 3082 Inst.addOperand(MCOperand::CreateImm(Val)); 3083 return MCDisassembler::Success; 3084 } 3085 3086 static DecodeStatus 3087 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3088 uint64_t Address, const void *Decoder) { 3089 DecodeStatus S = MCDisassembler::Success; 3090 3091 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3092 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3093 3094 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3095 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3096 return MCDisassembler::Fail; 3097 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3098 return MCDisassembler::Fail; 3099 return S; 3100 } 3101 3102 static DecodeStatus 3103 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3104 uint64_t Address, const void *Decoder) { 3105 DecodeStatus S = MCDisassembler::Success; 3106 3107 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3108 if (pred == 0xE || pred == 0xF) { 3109 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3110 switch (opc) { 3111 default: 3112 return MCDisassembler::Fail; 3113 case 0xf3bf8f4: 3114 Inst.setOpcode(ARM::t2DSB); 3115 break; 3116 case 0xf3bf8f5: 3117 Inst.setOpcode(ARM::t2DMB); 3118 break; 3119 case 0xf3bf8f6: 3120 Inst.setOpcode(ARM::t2ISB); 3121 break; 3122 } 3123 3124 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3125 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3126 } 3127 3128 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3129 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3130 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3131 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3132 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3133 3134 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3135 return MCDisassembler::Fail; 3136 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3137 return MCDisassembler::Fail; 3138 3139 return S; 3140 } 3141 3142 // Decode a shifted immediate operand. These basically consist 3143 // of an 8-bit value, and a 4-bit directive that specifies either 3144 // a splat operation or a rotation. 3145 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3146 uint64_t Address, const void *Decoder) { 3147 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3148 if (ctrl == 0) { 3149 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3150 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3151 switch (byte) { 3152 case 0: 3153 Inst.addOperand(MCOperand::CreateImm(imm)); 3154 break; 3155 case 1: 3156 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3157 break; 3158 case 2: 3159 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3160 break; 3161 case 3: 3162 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3163 (imm << 8) | imm)); 3164 break; 3165 } 3166 } else { 3167 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3168 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3169 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3170 Inst.addOperand(MCOperand::CreateImm(imm)); 3171 } 3172 3173 return MCDisassembler::Success; 3174 } 3175 3176 static DecodeStatus 3177 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3178 uint64_t Address, const void *Decoder){ 3179 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3180 return MCDisassembler::Success; 3181 } 3182 3183 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3184 uint64_t Address, const void *Decoder){ 3185 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3186 return MCDisassembler::Success; 3187 } 3188 3189 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3190 uint64_t Address, const void *Decoder) { 3191 switch (Val) { 3192 default: 3193 return MCDisassembler::Fail; 3194 case 0xF: // SY 3195 case 0xE: // ST 3196 case 0xB: // ISH 3197 case 0xA: // ISHST 3198 case 0x7: // NSH 3199 case 0x6: // NSHST 3200 case 0x3: // OSH 3201 case 0x2: // OSHST 3202 break; 3203 } 3204 3205 Inst.addOperand(MCOperand::CreateImm(Val)); 3206 return MCDisassembler::Success; 3207 } 3208 3209 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3210 uint64_t Address, const void *Decoder) { 3211 if (!Val) return MCDisassembler::Fail; 3212 Inst.addOperand(MCOperand::CreateImm(Val)); 3213 return MCDisassembler::Success; 3214 } 3215 3216 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3217 uint64_t Address, const void *Decoder) { 3218 DecodeStatus S = MCDisassembler::Success; 3219 3220 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3221 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3222 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3223 3224 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3225 3226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3227 return MCDisassembler::Fail; 3228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3231 return MCDisassembler::Fail; 3232 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3233 return MCDisassembler::Fail; 3234 3235 return S; 3236 } 3237 3238 3239 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3240 uint64_t Address, const void *Decoder){ 3241 DecodeStatus S = MCDisassembler::Success; 3242 3243 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3244 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3245 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3246 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3247 3248 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3249 return MCDisassembler::Fail; 3250 3251 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3252 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3253 3254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3255 return MCDisassembler::Fail; 3256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3257 return MCDisassembler::Fail; 3258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3259 return MCDisassembler::Fail; 3260 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3261 return MCDisassembler::Fail; 3262 3263 return S; 3264 } 3265 3266 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3267 uint64_t Address, const void *Decoder) { 3268 DecodeStatus S = MCDisassembler::Success; 3269 3270 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3271 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3272 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3273 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3274 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3275 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3276 3277 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3278 3279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3280 return MCDisassembler::Fail; 3281 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3282 return MCDisassembler::Fail; 3283 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3284 return MCDisassembler::Fail; 3285 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3286 return MCDisassembler::Fail; 3287 3288 return S; 3289 } 3290 3291 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3292 uint64_t Address, const void *Decoder) { 3293 DecodeStatus S = MCDisassembler::Success; 3294 3295 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3296 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3297 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3298 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3299 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3300 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3301 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3302 3303 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3304 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3305 3306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3307 return MCDisassembler::Fail; 3308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3309 return MCDisassembler::Fail; 3310 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3311 return MCDisassembler::Fail; 3312 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3313 return MCDisassembler::Fail; 3314 3315 return S; 3316 } 3317 3318 3319 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3320 uint64_t Address, const void *Decoder) { 3321 DecodeStatus S = MCDisassembler::Success; 3322 3323 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3324 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3325 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3326 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3327 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3328 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3329 3330 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3331 3332 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3333 return MCDisassembler::Fail; 3334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3335 return MCDisassembler::Fail; 3336 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3337 return MCDisassembler::Fail; 3338 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3339 return MCDisassembler::Fail; 3340 3341 return S; 3342 } 3343 3344 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3345 uint64_t Address, const void *Decoder) { 3346 DecodeStatus S = MCDisassembler::Success; 3347 3348 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3349 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3350 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3351 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3352 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3353 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3354 3355 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3356 3357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3358 return MCDisassembler::Fail; 3359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3360 return MCDisassembler::Fail; 3361 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3362 return MCDisassembler::Fail; 3363 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3364 return MCDisassembler::Fail; 3365 3366 return S; 3367 } 3368 3369 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3370 uint64_t Address, const void *Decoder) { 3371 DecodeStatus S = MCDisassembler::Success; 3372 3373 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3374 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3375 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3376 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3377 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3378 3379 unsigned align = 0; 3380 unsigned index = 0; 3381 switch (size) { 3382 default: 3383 return MCDisassembler::Fail; 3384 case 0: 3385 if (fieldFromInstruction32(Insn, 4, 1)) 3386 return MCDisassembler::Fail; // UNDEFINED 3387 index = fieldFromInstruction32(Insn, 5, 3); 3388 break; 3389 case 1: 3390 if (fieldFromInstruction32(Insn, 5, 1)) 3391 return MCDisassembler::Fail; // UNDEFINED 3392 index = fieldFromInstruction32(Insn, 6, 2); 3393 if (fieldFromInstruction32(Insn, 4, 1)) 3394 align = 2; 3395 break; 3396 case 2: 3397 if (fieldFromInstruction32(Insn, 6, 1)) 3398 return MCDisassembler::Fail; // UNDEFINED 3399 index = fieldFromInstruction32(Insn, 7, 1); 3400 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3401 align = 4; 3402 } 3403 3404 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3405 return MCDisassembler::Fail; 3406 if (Rm != 0xF) { // Writeback 3407 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3408 return MCDisassembler::Fail; 3409 } 3410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3411 return MCDisassembler::Fail; 3412 Inst.addOperand(MCOperand::CreateImm(align)); 3413 if (Rm != 0xF) { 3414 if (Rm != 0xD) { 3415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3416 return MCDisassembler::Fail; 3417 } else 3418 Inst.addOperand(MCOperand::CreateReg(0)); 3419 } 3420 3421 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3422 return MCDisassembler::Fail; 3423 Inst.addOperand(MCOperand::CreateImm(index)); 3424 3425 return S; 3426 } 3427 3428 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3429 uint64_t Address, const void *Decoder) { 3430 DecodeStatus S = MCDisassembler::Success; 3431 3432 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3433 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3434 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3435 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3436 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3437 3438 unsigned align = 0; 3439 unsigned index = 0; 3440 switch (size) { 3441 default: 3442 return MCDisassembler::Fail; 3443 case 0: 3444 if (fieldFromInstruction32(Insn, 4, 1)) 3445 return MCDisassembler::Fail; // UNDEFINED 3446 index = fieldFromInstruction32(Insn, 5, 3); 3447 break; 3448 case 1: 3449 if (fieldFromInstruction32(Insn, 5, 1)) 3450 return MCDisassembler::Fail; // UNDEFINED 3451 index = fieldFromInstruction32(Insn, 6, 2); 3452 if (fieldFromInstruction32(Insn, 4, 1)) 3453 align = 2; 3454 break; 3455 case 2: 3456 if (fieldFromInstruction32(Insn, 6, 1)) 3457 return MCDisassembler::Fail; // UNDEFINED 3458 index = fieldFromInstruction32(Insn, 7, 1); 3459 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3460 align = 4; 3461 } 3462 3463 if (Rm != 0xF) { // Writeback 3464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 } 3467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3468 return MCDisassembler::Fail; 3469 Inst.addOperand(MCOperand::CreateImm(align)); 3470 if (Rm != 0xF) { 3471 if (Rm != 0xD) { 3472 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3473 return MCDisassembler::Fail; 3474 } else 3475 Inst.addOperand(MCOperand::CreateReg(0)); 3476 } 3477 3478 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3479 return MCDisassembler::Fail; 3480 Inst.addOperand(MCOperand::CreateImm(index)); 3481 3482 return S; 3483 } 3484 3485 3486 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3487 uint64_t Address, const void *Decoder) { 3488 DecodeStatus S = MCDisassembler::Success; 3489 3490 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3491 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3492 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3493 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3494 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3495 3496 unsigned align = 0; 3497 unsigned index = 0; 3498 unsigned inc = 1; 3499 switch (size) { 3500 default: 3501 return MCDisassembler::Fail; 3502 case 0: 3503 index = fieldFromInstruction32(Insn, 5, 3); 3504 if (fieldFromInstruction32(Insn, 4, 1)) 3505 align = 2; 3506 break; 3507 case 1: 3508 index = fieldFromInstruction32(Insn, 6, 2); 3509 if (fieldFromInstruction32(Insn, 4, 1)) 3510 align = 4; 3511 if (fieldFromInstruction32(Insn, 5, 1)) 3512 inc = 2; 3513 break; 3514 case 2: 3515 if (fieldFromInstruction32(Insn, 5, 1)) 3516 return MCDisassembler::Fail; // UNDEFINED 3517 index = fieldFromInstruction32(Insn, 7, 1); 3518 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3519 align = 8; 3520 if (fieldFromInstruction32(Insn, 6, 1)) 3521 inc = 2; 3522 break; 3523 } 3524 3525 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3526 return MCDisassembler::Fail; 3527 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3528 return MCDisassembler::Fail; 3529 if (Rm != 0xF) { // Writeback 3530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 } 3533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3534 return MCDisassembler::Fail; 3535 Inst.addOperand(MCOperand::CreateImm(align)); 3536 if (Rm != 0xF) { 3537 if (Rm != 0xD) { 3538 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3539 return MCDisassembler::Fail; 3540 } else 3541 Inst.addOperand(MCOperand::CreateReg(0)); 3542 } 3543 3544 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3545 return MCDisassembler::Fail; 3546 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3547 return MCDisassembler::Fail; 3548 Inst.addOperand(MCOperand::CreateImm(index)); 3549 3550 return S; 3551 } 3552 3553 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3554 uint64_t Address, const void *Decoder) { 3555 DecodeStatus S = MCDisassembler::Success; 3556 3557 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3558 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3559 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3560 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3561 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3562 3563 unsigned align = 0; 3564 unsigned index = 0; 3565 unsigned inc = 1; 3566 switch (size) { 3567 default: 3568 return MCDisassembler::Fail; 3569 case 0: 3570 index = fieldFromInstruction32(Insn, 5, 3); 3571 if (fieldFromInstruction32(Insn, 4, 1)) 3572 align = 2; 3573 break; 3574 case 1: 3575 index = fieldFromInstruction32(Insn, 6, 2); 3576 if (fieldFromInstruction32(Insn, 4, 1)) 3577 align = 4; 3578 if (fieldFromInstruction32(Insn, 5, 1)) 3579 inc = 2; 3580 break; 3581 case 2: 3582 if (fieldFromInstruction32(Insn, 5, 1)) 3583 return MCDisassembler::Fail; // UNDEFINED 3584 index = fieldFromInstruction32(Insn, 7, 1); 3585 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3586 align = 8; 3587 if (fieldFromInstruction32(Insn, 6, 1)) 3588 inc = 2; 3589 break; 3590 } 3591 3592 if (Rm != 0xF) { // Writeback 3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 } 3596 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3597 return MCDisassembler::Fail; 3598 Inst.addOperand(MCOperand::CreateImm(align)); 3599 if (Rm != 0xF) { 3600 if (Rm != 0xD) { 3601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3602 return MCDisassembler::Fail; 3603 } else 3604 Inst.addOperand(MCOperand::CreateReg(0)); 3605 } 3606 3607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3608 return MCDisassembler::Fail; 3609 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3610 return MCDisassembler::Fail; 3611 Inst.addOperand(MCOperand::CreateImm(index)); 3612 3613 return S; 3614 } 3615 3616 3617 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3618 uint64_t Address, const void *Decoder) { 3619 DecodeStatus S = MCDisassembler::Success; 3620 3621 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3622 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3623 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3624 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3625 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3626 3627 unsigned align = 0; 3628 unsigned index = 0; 3629 unsigned inc = 1; 3630 switch (size) { 3631 default: 3632 return MCDisassembler::Fail; 3633 case 0: 3634 if (fieldFromInstruction32(Insn, 4, 1)) 3635 return MCDisassembler::Fail; // UNDEFINED 3636 index = fieldFromInstruction32(Insn, 5, 3); 3637 break; 3638 case 1: 3639 if (fieldFromInstruction32(Insn, 4, 1)) 3640 return MCDisassembler::Fail; // UNDEFINED 3641 index = fieldFromInstruction32(Insn, 6, 2); 3642 if (fieldFromInstruction32(Insn, 5, 1)) 3643 inc = 2; 3644 break; 3645 case 2: 3646 if (fieldFromInstruction32(Insn, 4, 2)) 3647 return MCDisassembler::Fail; // UNDEFINED 3648 index = fieldFromInstruction32(Insn, 7, 1); 3649 if (fieldFromInstruction32(Insn, 6, 1)) 3650 inc = 2; 3651 break; 3652 } 3653 3654 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3655 return MCDisassembler::Fail; 3656 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3657 return MCDisassembler::Fail; 3658 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3659 return MCDisassembler::Fail; 3660 3661 if (Rm != 0xF) { // Writeback 3662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3663 return MCDisassembler::Fail; 3664 } 3665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3666 return MCDisassembler::Fail; 3667 Inst.addOperand(MCOperand::CreateImm(align)); 3668 if (Rm != 0xF) { 3669 if (Rm != 0xD) { 3670 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3671 return MCDisassembler::Fail; 3672 } else 3673 Inst.addOperand(MCOperand::CreateReg(0)); 3674 } 3675 3676 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3677 return MCDisassembler::Fail; 3678 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3679 return MCDisassembler::Fail; 3680 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3681 return MCDisassembler::Fail; 3682 Inst.addOperand(MCOperand::CreateImm(index)); 3683 3684 return S; 3685 } 3686 3687 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3688 uint64_t Address, const void *Decoder) { 3689 DecodeStatus S = MCDisassembler::Success; 3690 3691 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3692 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3693 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3694 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3695 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3696 3697 unsigned align = 0; 3698 unsigned index = 0; 3699 unsigned inc = 1; 3700 switch (size) { 3701 default: 3702 return MCDisassembler::Fail; 3703 case 0: 3704 if (fieldFromInstruction32(Insn, 4, 1)) 3705 return MCDisassembler::Fail; // UNDEFINED 3706 index = fieldFromInstruction32(Insn, 5, 3); 3707 break; 3708 case 1: 3709 if (fieldFromInstruction32(Insn, 4, 1)) 3710 return MCDisassembler::Fail; // UNDEFINED 3711 index = fieldFromInstruction32(Insn, 6, 2); 3712 if (fieldFromInstruction32(Insn, 5, 1)) 3713 inc = 2; 3714 break; 3715 case 2: 3716 if (fieldFromInstruction32(Insn, 4, 2)) 3717 return MCDisassembler::Fail; // UNDEFINED 3718 index = fieldFromInstruction32(Insn, 7, 1); 3719 if (fieldFromInstruction32(Insn, 6, 1)) 3720 inc = 2; 3721 break; 3722 } 3723 3724 if (Rm != 0xF) { // Writeback 3725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3726 return MCDisassembler::Fail; 3727 } 3728 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3729 return MCDisassembler::Fail; 3730 Inst.addOperand(MCOperand::CreateImm(align)); 3731 if (Rm != 0xF) { 3732 if (Rm != 0xD) { 3733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3734 return MCDisassembler::Fail; 3735 } else 3736 Inst.addOperand(MCOperand::CreateReg(0)); 3737 } 3738 3739 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3740 return MCDisassembler::Fail; 3741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3742 return MCDisassembler::Fail; 3743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3744 return MCDisassembler::Fail; 3745 Inst.addOperand(MCOperand::CreateImm(index)); 3746 3747 return S; 3748 } 3749 3750 3751 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3752 uint64_t Address, const void *Decoder) { 3753 DecodeStatus S = MCDisassembler::Success; 3754 3755 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3756 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3757 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3758 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3759 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3760 3761 unsigned align = 0; 3762 unsigned index = 0; 3763 unsigned inc = 1; 3764 switch (size) { 3765 default: 3766 return MCDisassembler::Fail; 3767 case 0: 3768 if (fieldFromInstruction32(Insn, 4, 1)) 3769 align = 4; 3770 index = fieldFromInstruction32(Insn, 5, 3); 3771 break; 3772 case 1: 3773 if (fieldFromInstruction32(Insn, 4, 1)) 3774 align = 8; 3775 index = fieldFromInstruction32(Insn, 6, 2); 3776 if (fieldFromInstruction32(Insn, 5, 1)) 3777 inc = 2; 3778 break; 3779 case 2: 3780 if (fieldFromInstruction32(Insn, 4, 2)) 3781 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3782 index = fieldFromInstruction32(Insn, 7, 1); 3783 if (fieldFromInstruction32(Insn, 6, 1)) 3784 inc = 2; 3785 break; 3786 } 3787 3788 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3789 return MCDisassembler::Fail; 3790 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3791 return MCDisassembler::Fail; 3792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3793 return MCDisassembler::Fail; 3794 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3795 return MCDisassembler::Fail; 3796 3797 if (Rm != 0xF) { // Writeback 3798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3799 return MCDisassembler::Fail; 3800 } 3801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3802 return MCDisassembler::Fail; 3803 Inst.addOperand(MCOperand::CreateImm(align)); 3804 if (Rm != 0xF) { 3805 if (Rm != 0xD) { 3806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3807 return MCDisassembler::Fail; 3808 } else 3809 Inst.addOperand(MCOperand::CreateReg(0)); 3810 } 3811 3812 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3813 return MCDisassembler::Fail; 3814 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3815 return MCDisassembler::Fail; 3816 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3817 return MCDisassembler::Fail; 3818 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3819 return MCDisassembler::Fail; 3820 Inst.addOperand(MCOperand::CreateImm(index)); 3821 3822 return S; 3823 } 3824 3825 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3826 uint64_t Address, const void *Decoder) { 3827 DecodeStatus S = MCDisassembler::Success; 3828 3829 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3830 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3831 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3832 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3833 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3834 3835 unsigned align = 0; 3836 unsigned index = 0; 3837 unsigned inc = 1; 3838 switch (size) { 3839 default: 3840 return MCDisassembler::Fail; 3841 case 0: 3842 if (fieldFromInstruction32(Insn, 4, 1)) 3843 align = 4; 3844 index = fieldFromInstruction32(Insn, 5, 3); 3845 break; 3846 case 1: 3847 if (fieldFromInstruction32(Insn, 4, 1)) 3848 align = 8; 3849 index = fieldFromInstruction32(Insn, 6, 2); 3850 if (fieldFromInstruction32(Insn, 5, 1)) 3851 inc = 2; 3852 break; 3853 case 2: 3854 if (fieldFromInstruction32(Insn, 4, 2)) 3855 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3856 index = fieldFromInstruction32(Insn, 7, 1); 3857 if (fieldFromInstruction32(Insn, 6, 1)) 3858 inc = 2; 3859 break; 3860 } 3861 3862 if (Rm != 0xF) { // Writeback 3863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3864 return MCDisassembler::Fail; 3865 } 3866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3867 return MCDisassembler::Fail; 3868 Inst.addOperand(MCOperand::CreateImm(align)); 3869 if (Rm != 0xF) { 3870 if (Rm != 0xD) { 3871 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 } else 3874 Inst.addOperand(MCOperand::CreateReg(0)); 3875 } 3876 3877 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3878 return MCDisassembler::Fail; 3879 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3880 return MCDisassembler::Fail; 3881 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3882 return MCDisassembler::Fail; 3883 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3884 return MCDisassembler::Fail; 3885 Inst.addOperand(MCOperand::CreateImm(index)); 3886 3887 return S; 3888 } 3889 3890 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3891 uint64_t Address, const void *Decoder) { 3892 DecodeStatus S = MCDisassembler::Success; 3893 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3894 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3895 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3896 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3897 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3898 3899 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3900 S = MCDisassembler::SoftFail; 3901 3902 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3903 return MCDisassembler::Fail; 3904 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3905 return MCDisassembler::Fail; 3906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3907 return MCDisassembler::Fail; 3908 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3909 return MCDisassembler::Fail; 3910 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3911 return MCDisassembler::Fail; 3912 3913 return S; 3914 } 3915 3916 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3917 uint64_t Address, const void *Decoder) { 3918 DecodeStatus S = MCDisassembler::Success; 3919 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3920 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3921 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3922 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3923 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3924 3925 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3926 S = MCDisassembler::SoftFail; 3927 3928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3929 return MCDisassembler::Fail; 3930 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3931 return MCDisassembler::Fail; 3932 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3933 return MCDisassembler::Fail; 3934 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3935 return MCDisassembler::Fail; 3936 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3937 return MCDisassembler::Fail; 3938 3939 return S; 3940 } 3941 3942 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3943 uint64_t Address, const void *Decoder) { 3944 DecodeStatus S = MCDisassembler::Success; 3945 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3946 // The InstPrinter needs to have the low bit of the predicate in 3947 // the mask operand to be able to print it properly. 3948 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3949 3950 if (pred == 0xF) { 3951 pred = 0xE; 3952 S = MCDisassembler::SoftFail; 3953 } 3954 3955 if ((mask & 0xF) == 0) { 3956 // Preserve the high bit of the mask, which is the low bit of 3957 // the predicate. 3958 mask &= 0x10; 3959 mask |= 0x8; 3960 S = MCDisassembler::SoftFail; 3961 } 3962 3963 Inst.addOperand(MCOperand::CreateImm(pred)); 3964 Inst.addOperand(MCOperand::CreateImm(mask)); 3965 return S; 3966 } 3967 3968 static DecodeStatus 3969 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3970 uint64_t Address, const void *Decoder) { 3971 DecodeStatus S = MCDisassembler::Success; 3972 3973 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3974 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3975 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3976 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3977 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3978 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3979 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3980 bool writeback = (W == 1) | (P == 0); 3981 3982 addr |= (U << 8) | (Rn << 9); 3983 3984 if (writeback && (Rn == Rt || Rn == Rt2)) 3985 Check(S, MCDisassembler::SoftFail); 3986 if (Rt == Rt2) 3987 Check(S, MCDisassembler::SoftFail); 3988 3989 // Rt 3990 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3991 return MCDisassembler::Fail; 3992 // Rt2 3993 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3994 return MCDisassembler::Fail; 3995 // Writeback operand 3996 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3997 return MCDisassembler::Fail; 3998 // addr 3999 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4000 return MCDisassembler::Fail; 4001 4002 return S; 4003 } 4004 4005 static DecodeStatus 4006 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 4007 uint64_t Address, const void *Decoder) { 4008 DecodeStatus S = MCDisassembler::Success; 4009 4010 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4011 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 4012 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4013 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 4014 unsigned W = fieldFromInstruction32(Insn, 21, 1); 4015 unsigned U = fieldFromInstruction32(Insn, 23, 1); 4016 unsigned P = fieldFromInstruction32(Insn, 24, 1); 4017 bool writeback = (W == 1) | (P == 0); 4018 4019 addr |= (U << 8) | (Rn << 9); 4020 4021 if (writeback && (Rn == Rt || Rn == Rt2)) 4022 Check(S, MCDisassembler::SoftFail); 4023 4024 // Writeback operand 4025 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4026 return MCDisassembler::Fail; 4027 // Rt 4028 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 // Rt2 4031 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 // addr 4034 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4035 return MCDisassembler::Fail; 4036 4037 return S; 4038 } 4039 4040 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 4041 uint64_t Address, const void *Decoder) { 4042 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 4043 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 4044 if (sign1 != sign2) return MCDisassembler::Fail; 4045 4046 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 4047 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 4048 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 4049 Val |= sign1 << 12; 4050 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4051 4052 return MCDisassembler::Success; 4053 } 4054 4055 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4056 uint64_t Address, 4057 const void *Decoder) { 4058 DecodeStatus S = MCDisassembler::Success; 4059 4060 // Shift of "asr #32" is not allowed in Thumb2 mode. 4061 if (Val == 0x20) S = MCDisassembler::SoftFail; 4062 Inst.addOperand(MCOperand::CreateImm(Val)); 4063 return S; 4064 } 4065 4066 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 4067 uint64_t Address, const void *Decoder) { 4068 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4069 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4070 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4071 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4072 4073 if (pred == 0xF) 4074 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4075 4076 DecodeStatus S = MCDisassembler::Success; 4077 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4078 return MCDisassembler::Fail; 4079 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4080 return MCDisassembler::Fail; 4081 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4082 return MCDisassembler::Fail; 4083 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4084 return MCDisassembler::Fail; 4085 4086 return S; 4087 } 4088