1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/ARMAddressingModes.h" 10 #include "MCTargetDesc/ARMBaseInfo.h" 11 #include "MCTargetDesc/ARMMCTargetDesc.h" 12 #include "TargetInfo/ARMTargetInfo.h" 13 #include "Utils/ARMBaseInfo.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 16 #include "llvm/MC/MCFixedLenDisassembler.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/MC/SubtargetFeature.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/MathExtras.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <algorithm> 27 #include <cassert> 28 #include <cstdint> 29 #include <vector> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "arm-disassembler" 34 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 namespace { 38 39 // Handles the condition code status of instructions in IT blocks 40 class ITStatus 41 { 42 public: 43 // Returns the condition code for instruction in IT block 44 unsigned getITCC() { 45 unsigned CC = ARMCC::AL; 46 if (instrInITBlock()) 47 CC = ITStates.back(); 48 return CC; 49 } 50 51 // Advances the IT block state to the next T or E 52 void advanceITState() { 53 ITStates.pop_back(); 54 } 55 56 // Returns true if the current instruction is in an IT block 57 bool instrInITBlock() { 58 return !ITStates.empty(); 59 } 60 61 // Returns true if current instruction is the last instruction in an IT block 62 bool instrLastInITBlock() { 63 return ITStates.size() == 1; 64 } 65 66 // Called when decoding an IT instruction. Sets the IT state for the following 67 // instructions that for the IT block. Firstcond and Mask correspond to the 68 // fields in the IT instruction encoding. 69 void setITState(char Firstcond, char Mask) { 70 // (3 - the number of trailing zeros) is the number of then / else. 71 unsigned CondBit0 = Firstcond & 1; 72 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 73 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 74 assert(NumTZ <= 3 && "Invalid IT mask!"); 75 // push condition codes onto the stack the correct order for the pops 76 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 77 bool T = ((Mask >> Pos) & 1) == CondBit0; 78 if (T) 79 ITStates.push_back(CCBits); 80 else 81 ITStates.push_back(CCBits ^ 1); 82 } 83 ITStates.push_back(CCBits); 84 } 85 86 private: 87 std::vector<unsigned char> ITStates; 88 }; 89 90 /// ARM disassembler for all ARM platforms. 91 class ARMDisassembler : public MCDisassembler { 92 public: 93 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 94 MCDisassembler(STI, Ctx) { 95 } 96 97 ~ARMDisassembler() override = default; 98 99 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 100 ArrayRef<uint8_t> Bytes, uint64_t Address, 101 raw_ostream &VStream, 102 raw_ostream &CStream) const override; 103 }; 104 105 /// Thumb disassembler for all Thumb platforms. 106 class ThumbDisassembler : public MCDisassembler { 107 public: 108 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 109 MCDisassembler(STI, Ctx) { 110 } 111 112 ~ThumbDisassembler() override = default; 113 114 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 115 ArrayRef<uint8_t> Bytes, uint64_t Address, 116 raw_ostream &VStream, 117 raw_ostream &CStream) const override; 118 119 private: 120 mutable ITStatus ITBlock; 121 122 DecodeStatus AddThumbPredicate(MCInst&) const; 123 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 124 }; 125 126 } // end anonymous namespace 127 128 static bool Check(DecodeStatus &Out, DecodeStatus In) { 129 switch (In) { 130 case MCDisassembler::Success: 131 // Out stays the same. 132 return true; 133 case MCDisassembler::SoftFail: 134 Out = In; 135 return true; 136 case MCDisassembler::Fail: 137 Out = In; 138 return false; 139 } 140 llvm_unreachable("Invalid DecodeStatus!"); 141 } 142 143 // Forward declare these because the autogenerated code will reference them. 144 // Definitions are further down. 145 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 146 uint64_t Address, const void *Decoder); 147 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 148 uint64_t Address, const void *Decoder); 149 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 150 unsigned RegNo, uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 153 unsigned RegNo, uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 156 unsigned RegNo, uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 177 unsigned RegNo, 178 uint64_t Address, 179 const void *Decoder); 180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 185 unsigned RegNo, uint64_t Address, 186 const void *Decoder); 187 188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 199 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 204 unsigned Insn, 205 uint64_t Address, 206 const void *Decoder); 207 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 216 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 217 unsigned Insn, 218 uint64_t Adddress, 219 const void *Decoder); 220 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 335 unsigned Val, 336 uint64_t Address, 337 const void *Decoder); 338 339 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void* Decoder); 361 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void* Decoder); 363 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void* Decoder); 365 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void* Decoder); 367 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 374 uint64_t Address, 375 const void *Decoder); 376 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 401 uint64_t Address, const void *Decoder); 402 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 403 uint64_t Address, const void *Decoder); 404 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 417 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 418 uint64_t Address, const void *Decoder); 419 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 420 uint64_t Address, const void *Decoder); 421 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 422 uint64_t Address, const void *Decoder); 423 424 template <bool isSigned, bool isNeg, int size> 425 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 426 uint64_t Address, const void *Decoder); 427 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 428 uint64_t Address, 429 const void *Decoder); 430 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 431 uint64_t Address, 432 const void *Decoder); 433 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 434 const void *Decoder); 435 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 436 const void *Decoder); 437 template<bool Writeback> 438 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 439 uint64_t Address, 440 const void *Decoder); 441 #include "ARMGenDisassemblerTables.inc" 442 443 static MCDisassembler *createARMDisassembler(const Target &T, 444 const MCSubtargetInfo &STI, 445 MCContext &Ctx) { 446 return new ARMDisassembler(STI, Ctx); 447 } 448 449 static MCDisassembler *createThumbDisassembler(const Target &T, 450 const MCSubtargetInfo &STI, 451 MCContext &Ctx) { 452 return new ThumbDisassembler(STI, Ctx); 453 } 454 455 // Post-decoding checks 456 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 457 uint64_t Address, raw_ostream &OS, 458 raw_ostream &CS, 459 uint32_t Insn, 460 DecodeStatus Result) { 461 switch (MI.getOpcode()) { 462 case ARM::HVC: { 463 // HVC is undefined if condition = 0xf otherwise upredictable 464 // if condition != 0xe 465 uint32_t Cond = (Insn >> 28) & 0xF; 466 if (Cond == 0xF) 467 return MCDisassembler::Fail; 468 if (Cond != 0xE) 469 return MCDisassembler::SoftFail; 470 return Result; 471 } 472 case ARM::t2ADDri: 473 case ARM::t2ADDri12: 474 case ARM::t2ADDrr: 475 case ARM::t2ADDrs: 476 case ARM::t2SUBri: 477 case ARM::t2SUBri12: 478 case ARM::t2SUBrr: 479 case ARM::t2SUBrs: 480 if (MI.getOperand(0).getReg() == ARM::SP && 481 MI.getOperand(1).getReg() != ARM::SP) 482 return MCDisassembler::SoftFail; 483 return Result; 484 default: return Result; 485 } 486 } 487 488 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 489 ArrayRef<uint8_t> Bytes, 490 uint64_t Address, raw_ostream &OS, 491 raw_ostream &CS) const { 492 CommentStream = &CS; 493 494 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 495 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 496 "mode!"); 497 498 // We want to read exactly 4 bytes of data. 499 if (Bytes.size() < 4) { 500 Size = 0; 501 return MCDisassembler::Fail; 502 } 503 504 // Encoded as a small-endian 32-bit word in the stream. 505 uint32_t Insn = 506 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 507 508 // Calling the auto-generated decoder function. 509 DecodeStatus Result = 510 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 511 if (Result != MCDisassembler::Fail) { 512 Size = 4; 513 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 514 } 515 516 struct DecodeTable { 517 const uint8_t *P; 518 bool DecodePred; 519 }; 520 521 const DecodeTable Tables[] = { 522 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 523 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 524 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 525 {DecoderTablev8Crypto32, false}, 526 }; 527 528 for (auto Table : Tables) { 529 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 530 if (Result != MCDisassembler::Fail) { 531 Size = 4; 532 // Add a fake predicate operand, because we share these instruction 533 // definitions with Thumb2 where these instructions are predicable. 534 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 535 return MCDisassembler::Fail; 536 return Result; 537 } 538 } 539 540 Result = 541 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 542 if (Result != MCDisassembler::Fail) { 543 Size = 4; 544 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 545 } 546 547 Size = 4; 548 return MCDisassembler::Fail; 549 } 550 551 namespace llvm { 552 553 extern const MCInstrDesc ARMInsts[]; 554 555 } // end namespace llvm 556 557 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 558 /// immediate Value in the MCInst. The immediate Value has had any PC 559 /// adjustment made by the caller. If the instruction is a branch instruction 560 /// then isBranch is true, else false. If the getOpInfo() function was set as 561 /// part of the setupForSymbolicDisassembly() call then that function is called 562 /// to get any symbolic information at the Address for this instruction. If 563 /// that returns non-zero then the symbolic information it returns is used to 564 /// create an MCExpr and that is added as an operand to the MCInst. If 565 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 566 /// Value is done and if a symbol is found an MCExpr is created with that, else 567 /// an MCExpr with Value is created. This function returns true if it adds an 568 /// operand to the MCInst and false otherwise. 569 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 570 bool isBranch, uint64_t InstSize, 571 MCInst &MI, const void *Decoder) { 572 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 573 // FIXME: Does it make sense for value to be negative? 574 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 575 /* Offset */ 0, InstSize); 576 } 577 578 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 579 /// referenced by a load instruction with the base register that is the Pc. 580 /// These can often be values in a literal pool near the Address of the 581 /// instruction. The Address of the instruction and its immediate Value are 582 /// used as a possible literal pool entry. The SymbolLookUp call back will 583 /// return the name of a symbol referenced by the literal pool's entry if 584 /// the referenced address is that of a symbol. Or it will return a pointer to 585 /// a literal 'C' string if the referenced address of the literal pool's entry 586 /// is an address into a section with 'C' string literals. 587 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 588 const void *Decoder) { 589 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 590 Dis->tryAddingPcLoadReferenceComment(Value, Address); 591 } 592 593 // Thumb1 instructions don't have explicit S bits. Rather, they 594 // implicitly set CPSR. Since it's not represented in the encoding, the 595 // auto-generated decoder won't inject the CPSR operand. We need to fix 596 // that as a post-pass. 597 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 598 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 599 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 600 MCInst::iterator I = MI.begin(); 601 for (unsigned i = 0; i < NumOps; ++i, ++I) { 602 if (I == MI.end()) break; 603 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 604 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 605 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 606 return; 607 } 608 } 609 610 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 611 } 612 613 // Most Thumb instructions don't have explicit predicates in the 614 // encoding, but rather get their predicates from IT context. We need 615 // to fix up the predicate operands using this context information as a 616 // post-pass. 617 MCDisassembler::DecodeStatus 618 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 619 MCDisassembler::DecodeStatus S = Success; 620 621 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 622 623 // A few instructions actually have predicates encoded in them. Don't 624 // try to overwrite it if we're seeing one of those. 625 switch (MI.getOpcode()) { 626 case ARM::tBcc: 627 case ARM::t2Bcc: 628 case ARM::tCBZ: 629 case ARM::tCBNZ: 630 case ARM::tCPS: 631 case ARM::t2CPS3p: 632 case ARM::t2CPS2p: 633 case ARM::t2CPS1p: 634 case ARM::t2CSEL: 635 case ARM::t2CSINC: 636 case ARM::t2CSINV: 637 case ARM::t2CSNEG: 638 case ARM::tMOVSr: 639 case ARM::tSETEND: 640 // Some instructions (mostly conditional branches) are not 641 // allowed in IT blocks. 642 if (ITBlock.instrInITBlock()) 643 S = SoftFail; 644 else 645 return Success; 646 break; 647 case ARM::t2HINT: 648 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 649 S = SoftFail; 650 break; 651 case ARM::tB: 652 case ARM::t2B: 653 case ARM::t2TBB: 654 case ARM::t2TBH: 655 // Some instructions (mostly unconditional branches) can 656 // only appears at the end of, or outside of, an IT. 657 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 658 S = SoftFail; 659 break; 660 default: 661 break; 662 } 663 664 // If we're in an IT block, base the predicate on that. Otherwise, 665 // assume a predicate of AL. 666 unsigned CC; 667 CC = ITBlock.getITCC(); 668 if (CC == 0xF) 669 CC = ARMCC::AL; 670 if (ITBlock.instrInITBlock()) 671 ITBlock.advanceITState(); 672 673 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 675 MCInst::iterator I = MI.begin(); 676 for (unsigned i = 0; i < NumOps; ++i, ++I) { 677 if (I == MI.end()) break; 678 if (OpInfo[i].isPredicate()) { 679 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 680 Check(S, SoftFail); 681 I = MI.insert(I, MCOperand::createImm(CC)); 682 ++I; 683 if (CC == ARMCC::AL) 684 MI.insert(I, MCOperand::createReg(0)); 685 else 686 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 687 return S; 688 } 689 } 690 691 I = MI.insert(I, MCOperand::createImm(CC)); 692 ++I; 693 if (CC == ARMCC::AL) 694 MI.insert(I, MCOperand::createReg(0)); 695 else 696 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 697 698 return S; 699 } 700 701 // Thumb VFP instructions are a special case. Because we share their 702 // encodings between ARM and Thumb modes, and they are predicable in ARM 703 // mode, the auto-generated decoder will give them an (incorrect) 704 // predicate operand. We need to rewrite these operands based on the IT 705 // context as a post-pass. 706 void ThumbDisassembler::UpdateThumbVFPPredicate( 707 DecodeStatus &S, MCInst &MI) const { 708 unsigned CC; 709 CC = ITBlock.getITCC(); 710 if (CC == 0xF) 711 CC = ARMCC::AL; 712 if (ITBlock.instrInITBlock()) 713 ITBlock.advanceITState(); 714 715 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 716 MCInst::iterator I = MI.begin(); 717 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 718 for (unsigned i = 0; i < NumOps; ++i, ++I) { 719 if (OpInfo[i].isPredicate() ) { 720 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 721 Check(S, SoftFail); 722 I->setImm(CC); 723 ++I; 724 if (CC == ARMCC::AL) 725 I->setReg(0); 726 else 727 I->setReg(ARM::CPSR); 728 return; 729 } 730 } 731 } 732 733 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 734 ArrayRef<uint8_t> Bytes, 735 uint64_t Address, 736 raw_ostream &OS, 737 raw_ostream &CS) const { 738 CommentStream = &CS; 739 740 assert(STI.getFeatureBits()[ARM::ModeThumb] && 741 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 742 743 // We want to read exactly 2 bytes of data. 744 if (Bytes.size() < 2) { 745 Size = 0; 746 return MCDisassembler::Fail; 747 } 748 749 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 750 DecodeStatus Result = 751 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 752 if (Result != MCDisassembler::Fail) { 753 Size = 2; 754 Check(Result, AddThumbPredicate(MI)); 755 return Result; 756 } 757 758 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 759 STI); 760 if (Result) { 761 Size = 2; 762 bool InITBlock = ITBlock.instrInITBlock(); 763 Check(Result, AddThumbPredicate(MI)); 764 AddThumb1SBit(MI, InITBlock); 765 return Result; 766 } 767 768 Result = 769 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 770 if (Result != MCDisassembler::Fail) { 771 Size = 2; 772 773 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 774 // the Thumb predicate. 775 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 776 Result = MCDisassembler::SoftFail; 777 778 Check(Result, AddThumbPredicate(MI)); 779 780 // If we find an IT instruction, we need to parse its condition 781 // code and mask operands so that we can apply them correctly 782 // to the subsequent instructions. 783 if (MI.getOpcode() == ARM::t2IT) { 784 unsigned Firstcond = MI.getOperand(0).getImm(); 785 unsigned Mask = MI.getOperand(1).getImm(); 786 ITBlock.setITState(Firstcond, Mask); 787 788 // An IT instruction that would give a 'NV' predicate is unpredictable. 789 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 790 CS << "unpredictable IT predicate sequence"; 791 } 792 793 return Result; 794 } 795 796 // We want to read exactly 4 bytes of data. 797 if (Bytes.size() < 4) { 798 Size = 0; 799 return MCDisassembler::Fail; 800 } 801 802 uint32_t Insn32 = 803 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 804 Result = 805 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 806 if (Result != MCDisassembler::Fail) { 807 Size = 4; 808 bool InITBlock = ITBlock.instrInITBlock(); 809 Check(Result, AddThumbPredicate(MI)); 810 AddThumb1SBit(MI, InITBlock); 811 return Result; 812 } 813 814 Result = 815 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 816 if (Result != MCDisassembler::Fail) { 817 Size = 4; 818 Check(Result, AddThumbPredicate(MI)); 819 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 820 } 821 822 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 823 Result = 824 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 825 if (Result != MCDisassembler::Fail) { 826 Size = 4; 827 UpdateThumbVFPPredicate(Result, MI); 828 return Result; 829 } 830 } 831 832 Result = 833 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 834 if (Result != MCDisassembler::Fail) { 835 Size = 4; 836 return Result; 837 } 838 839 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 840 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 841 STI); 842 if (Result != MCDisassembler::Fail) { 843 Size = 4; 844 Check(Result, AddThumbPredicate(MI)); 845 return Result; 846 } 847 } 848 849 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 850 uint32_t NEONLdStInsn = Insn32; 851 NEONLdStInsn &= 0xF0FFFFFF; 852 NEONLdStInsn |= 0x04000000; 853 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 854 Address, this, STI); 855 if (Result != MCDisassembler::Fail) { 856 Size = 4; 857 Check(Result, AddThumbPredicate(MI)); 858 return Result; 859 } 860 } 861 862 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 863 uint32_t NEONDataInsn = Insn32; 864 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 865 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 866 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 867 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 868 Address, this, STI); 869 if (Result != MCDisassembler::Fail) { 870 Size = 4; 871 Check(Result, AddThumbPredicate(MI)); 872 return Result; 873 } 874 875 uint32_t NEONCryptoInsn = Insn32; 876 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 877 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 878 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 879 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 880 Address, this, STI); 881 if (Result != MCDisassembler::Fail) { 882 Size = 4; 883 return Result; 884 } 885 886 uint32_t NEONv8Insn = Insn32; 887 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 888 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 889 this, STI); 890 if (Result != MCDisassembler::Fail) { 891 Size = 4; 892 return Result; 893 } 894 } 895 896 Result = 897 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 898 if (Result != MCDisassembler::Fail) { 899 Size = 4; 900 Check(Result, AddThumbPredicate(MI)); 901 return Result; 902 } 903 904 Size = 0; 905 return MCDisassembler::Fail; 906 } 907 908 extern "C" void LLVMInitializeARMDisassembler() { 909 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 910 createARMDisassembler); 911 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 912 createARMDisassembler); 913 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 914 createThumbDisassembler); 915 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 916 createThumbDisassembler); 917 } 918 919 static const uint16_t GPRDecoderTable[] = { 920 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 921 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 922 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 923 ARM::R12, ARM::SP, ARM::LR, ARM::PC 924 }; 925 926 static const uint16_t CLRMGPRDecoderTable[] = { 927 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 928 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 929 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 930 ARM::R12, 0, ARM::LR, ARM::APSR 931 }; 932 933 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 934 uint64_t Address, const void *Decoder) { 935 if (RegNo > 15) 936 return MCDisassembler::Fail; 937 938 unsigned Register = GPRDecoderTable[RegNo]; 939 Inst.addOperand(MCOperand::createReg(Register)); 940 return MCDisassembler::Success; 941 } 942 943 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 944 uint64_t Address, 945 const void *Decoder) { 946 if (RegNo > 15) 947 return MCDisassembler::Fail; 948 949 unsigned Register = CLRMGPRDecoderTable[RegNo]; 950 if (Register == 0) 951 return MCDisassembler::Fail; 952 953 Inst.addOperand(MCOperand::createReg(Register)); 954 return MCDisassembler::Success; 955 } 956 957 static DecodeStatus 958 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 959 uint64_t Address, const void *Decoder) { 960 DecodeStatus S = MCDisassembler::Success; 961 962 if (RegNo == 15) 963 S = MCDisassembler::SoftFail; 964 965 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 966 967 return S; 968 } 969 970 static DecodeStatus 971 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 972 uint64_t Address, const void *Decoder) { 973 DecodeStatus S = MCDisassembler::Success; 974 975 if (RegNo == 15) 976 { 977 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 978 return MCDisassembler::Success; 979 } 980 981 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 982 return S; 983 } 984 985 static DecodeStatus 986 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 987 uint64_t Address, const void *Decoder) { 988 DecodeStatus S = MCDisassembler::Success; 989 990 if (RegNo == 15) 991 { 992 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 993 return MCDisassembler::Success; 994 } 995 996 if (RegNo == 13) 997 S = MCDisassembler::SoftFail; 998 999 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1000 return S; 1001 } 1002 1003 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1004 uint64_t Address, const void *Decoder) { 1005 if (RegNo > 7) 1006 return MCDisassembler::Fail; 1007 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1008 } 1009 1010 static const uint16_t GPRPairDecoderTable[] = { 1011 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1012 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1013 }; 1014 1015 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1016 uint64_t Address, const void *Decoder) { 1017 DecodeStatus S = MCDisassembler::Success; 1018 1019 if (RegNo > 13) 1020 return MCDisassembler::Fail; 1021 1022 if ((RegNo & 1) || RegNo == 0xe) 1023 S = MCDisassembler::SoftFail; 1024 1025 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1026 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1027 return S; 1028 } 1029 1030 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1031 uint64_t Address, const void *Decoder) { 1032 unsigned Register = 0; 1033 switch (RegNo) { 1034 case 0: 1035 Register = ARM::R0; 1036 break; 1037 case 1: 1038 Register = ARM::R1; 1039 break; 1040 case 2: 1041 Register = ARM::R2; 1042 break; 1043 case 3: 1044 Register = ARM::R3; 1045 break; 1046 case 9: 1047 Register = ARM::R9; 1048 break; 1049 case 12: 1050 Register = ARM::R12; 1051 break; 1052 default: 1053 return MCDisassembler::Fail; 1054 } 1055 1056 Inst.addOperand(MCOperand::createReg(Register)); 1057 return MCDisassembler::Success; 1058 } 1059 1060 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1061 uint64_t Address, const void *Decoder) { 1062 DecodeStatus S = MCDisassembler::Success; 1063 1064 const FeatureBitset &featureBits = 1065 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1066 1067 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1068 S = MCDisassembler::SoftFail; 1069 1070 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1071 return S; 1072 } 1073 1074 static const uint16_t SPRDecoderTable[] = { 1075 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1076 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1077 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1078 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1079 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1080 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1081 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1082 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1083 }; 1084 1085 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1086 uint64_t Address, const void *Decoder) { 1087 if (RegNo > 31) 1088 return MCDisassembler::Fail; 1089 1090 unsigned Register = SPRDecoderTable[RegNo]; 1091 Inst.addOperand(MCOperand::createReg(Register)); 1092 return MCDisassembler::Success; 1093 } 1094 1095 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1096 uint64_t Address, const void *Decoder) { 1097 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1098 } 1099 1100 static const uint16_t DPRDecoderTable[] = { 1101 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1102 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1103 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1104 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1105 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1106 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1107 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1108 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1109 }; 1110 1111 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1112 uint64_t Address, const void *Decoder) { 1113 const FeatureBitset &featureBits = 1114 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1115 1116 bool hasD32 = featureBits[ARM::FeatureD32]; 1117 1118 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1119 return MCDisassembler::Fail; 1120 1121 unsigned Register = DPRDecoderTable[RegNo]; 1122 Inst.addOperand(MCOperand::createReg(Register)); 1123 return MCDisassembler::Success; 1124 } 1125 1126 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1127 uint64_t Address, const void *Decoder) { 1128 if (RegNo > 7) 1129 return MCDisassembler::Fail; 1130 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1131 } 1132 1133 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1134 uint64_t Address, const void *Decoder) { 1135 if (RegNo > 15) 1136 return MCDisassembler::Fail; 1137 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1138 } 1139 1140 static DecodeStatus 1141 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1142 uint64_t Address, const void *Decoder) { 1143 if (RegNo > 15) 1144 return MCDisassembler::Fail; 1145 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1146 } 1147 1148 static const uint16_t QPRDecoderTable[] = { 1149 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1150 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1151 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1152 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1153 }; 1154 1155 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1156 uint64_t Address, const void *Decoder) { 1157 if (RegNo > 31 || (RegNo & 1) != 0) 1158 return MCDisassembler::Fail; 1159 RegNo >>= 1; 1160 1161 unsigned Register = QPRDecoderTable[RegNo]; 1162 Inst.addOperand(MCOperand::createReg(Register)); 1163 return MCDisassembler::Success; 1164 } 1165 1166 static const uint16_t DPairDecoderTable[] = { 1167 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1168 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1169 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1170 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1171 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1172 ARM::Q15 1173 }; 1174 1175 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1176 uint64_t Address, const void *Decoder) { 1177 if (RegNo > 30) 1178 return MCDisassembler::Fail; 1179 1180 unsigned Register = DPairDecoderTable[RegNo]; 1181 Inst.addOperand(MCOperand::createReg(Register)); 1182 return MCDisassembler::Success; 1183 } 1184 1185 static const uint16_t DPairSpacedDecoderTable[] = { 1186 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1187 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1188 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1189 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1190 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1191 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1192 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1193 ARM::D28_D30, ARM::D29_D31 1194 }; 1195 1196 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1197 unsigned RegNo, 1198 uint64_t Address, 1199 const void *Decoder) { 1200 if (RegNo > 29) 1201 return MCDisassembler::Fail; 1202 1203 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1204 Inst.addOperand(MCOperand::createReg(Register)); 1205 return MCDisassembler::Success; 1206 } 1207 1208 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1209 uint64_t Address, const void *Decoder) { 1210 DecodeStatus S = MCDisassembler::Success; 1211 if (Val == 0xF) return MCDisassembler::Fail; 1212 // AL predicate is not allowed on Thumb1 branches. 1213 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1214 return MCDisassembler::Fail; 1215 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1216 Check(S, MCDisassembler::SoftFail); 1217 Inst.addOperand(MCOperand::createImm(Val)); 1218 if (Val == ARMCC::AL) { 1219 Inst.addOperand(MCOperand::createReg(0)); 1220 } else 1221 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1222 return S; 1223 } 1224 1225 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1226 uint64_t Address, const void *Decoder) { 1227 if (Val) 1228 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1229 else 1230 Inst.addOperand(MCOperand::createReg(0)); 1231 return MCDisassembler::Success; 1232 } 1233 1234 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1235 uint64_t Address, const void *Decoder) { 1236 DecodeStatus S = MCDisassembler::Success; 1237 1238 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1239 unsigned type = fieldFromInstruction(Val, 5, 2); 1240 unsigned imm = fieldFromInstruction(Val, 7, 5); 1241 1242 // Register-immediate 1243 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1244 return MCDisassembler::Fail; 1245 1246 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1247 switch (type) { 1248 case 0: 1249 Shift = ARM_AM::lsl; 1250 break; 1251 case 1: 1252 Shift = ARM_AM::lsr; 1253 break; 1254 case 2: 1255 Shift = ARM_AM::asr; 1256 break; 1257 case 3: 1258 Shift = ARM_AM::ror; 1259 break; 1260 } 1261 1262 if (Shift == ARM_AM::ror && imm == 0) 1263 Shift = ARM_AM::rrx; 1264 1265 unsigned Op = Shift | (imm << 3); 1266 Inst.addOperand(MCOperand::createImm(Op)); 1267 1268 return S; 1269 } 1270 1271 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1272 uint64_t Address, const void *Decoder) { 1273 DecodeStatus S = MCDisassembler::Success; 1274 1275 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1276 unsigned type = fieldFromInstruction(Val, 5, 2); 1277 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1278 1279 // Register-register 1280 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1281 return MCDisassembler::Fail; 1282 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1283 return MCDisassembler::Fail; 1284 1285 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1286 switch (type) { 1287 case 0: 1288 Shift = ARM_AM::lsl; 1289 break; 1290 case 1: 1291 Shift = ARM_AM::lsr; 1292 break; 1293 case 2: 1294 Shift = ARM_AM::asr; 1295 break; 1296 case 3: 1297 Shift = ARM_AM::ror; 1298 break; 1299 } 1300 1301 Inst.addOperand(MCOperand::createImm(Shift)); 1302 1303 return S; 1304 } 1305 1306 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1307 uint64_t Address, const void *Decoder) { 1308 DecodeStatus S = MCDisassembler::Success; 1309 1310 bool NeedDisjointWriteback = false; 1311 unsigned WritebackReg = 0; 1312 bool CLRM = false; 1313 switch (Inst.getOpcode()) { 1314 default: 1315 break; 1316 case ARM::LDMIA_UPD: 1317 case ARM::LDMDB_UPD: 1318 case ARM::LDMIB_UPD: 1319 case ARM::LDMDA_UPD: 1320 case ARM::t2LDMIA_UPD: 1321 case ARM::t2LDMDB_UPD: 1322 case ARM::t2STMIA_UPD: 1323 case ARM::t2STMDB_UPD: 1324 NeedDisjointWriteback = true; 1325 WritebackReg = Inst.getOperand(0).getReg(); 1326 break; 1327 case ARM::t2CLRM: 1328 CLRM = true; 1329 break; 1330 } 1331 1332 // Empty register lists are not allowed. 1333 if (Val == 0) return MCDisassembler::Fail; 1334 for (unsigned i = 0; i < 16; ++i) { 1335 if (Val & (1 << i)) { 1336 if (CLRM) { 1337 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1338 return MCDisassembler::Fail; 1339 } 1340 } else { 1341 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1342 return MCDisassembler::Fail; 1343 // Writeback not allowed if Rn is in the target list. 1344 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1345 Check(S, MCDisassembler::SoftFail); 1346 } 1347 } 1348 } 1349 1350 return S; 1351 } 1352 1353 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1354 uint64_t Address, const void *Decoder) { 1355 DecodeStatus S = MCDisassembler::Success; 1356 1357 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1358 unsigned regs = fieldFromInstruction(Val, 0, 8); 1359 1360 // In case of unpredictable encoding, tweak the operands. 1361 if (regs == 0 || (Vd + regs) > 32) { 1362 regs = Vd + regs > 32 ? 32 - Vd : regs; 1363 regs = std::max( 1u, regs); 1364 S = MCDisassembler::SoftFail; 1365 } 1366 1367 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1368 return MCDisassembler::Fail; 1369 for (unsigned i = 0; i < (regs - 1); ++i) { 1370 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1371 return MCDisassembler::Fail; 1372 } 1373 1374 return S; 1375 } 1376 1377 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1378 uint64_t Address, const void *Decoder) { 1379 DecodeStatus S = MCDisassembler::Success; 1380 1381 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1382 unsigned regs = fieldFromInstruction(Val, 1, 7); 1383 1384 // In case of unpredictable encoding, tweak the operands. 1385 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1386 regs = Vd + regs > 32 ? 32 - Vd : regs; 1387 regs = std::max( 1u, regs); 1388 regs = std::min(16u, regs); 1389 S = MCDisassembler::SoftFail; 1390 } 1391 1392 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1393 return MCDisassembler::Fail; 1394 for (unsigned i = 0; i < (regs - 1); ++i) { 1395 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1396 return MCDisassembler::Fail; 1397 } 1398 1399 return S; 1400 } 1401 1402 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1403 uint64_t Address, const void *Decoder) { 1404 // This operand encodes a mask of contiguous zeros between a specified MSB 1405 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1406 // the mask of all bits LSB-and-lower, and then xor them to create 1407 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1408 // create the final mask. 1409 unsigned msb = fieldFromInstruction(Val, 5, 5); 1410 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1411 1412 DecodeStatus S = MCDisassembler::Success; 1413 if (lsb > msb) { 1414 Check(S, MCDisassembler::SoftFail); 1415 // The check above will cause the warning for the "potentially undefined 1416 // instruction encoding" but we can't build a bad MCOperand value here 1417 // with a lsb > msb or else printing the MCInst will cause a crash. 1418 lsb = msb; 1419 } 1420 1421 uint32_t msb_mask = 0xFFFFFFFF; 1422 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1423 uint32_t lsb_mask = (1U << lsb) - 1; 1424 1425 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1426 return S; 1427 } 1428 1429 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1430 uint64_t Address, const void *Decoder) { 1431 DecodeStatus S = MCDisassembler::Success; 1432 1433 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1434 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1435 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1436 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1437 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1438 unsigned U = fieldFromInstruction(Insn, 23, 1); 1439 const FeatureBitset &featureBits = 1440 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1441 1442 switch (Inst.getOpcode()) { 1443 case ARM::LDC_OFFSET: 1444 case ARM::LDC_PRE: 1445 case ARM::LDC_POST: 1446 case ARM::LDC_OPTION: 1447 case ARM::LDCL_OFFSET: 1448 case ARM::LDCL_PRE: 1449 case ARM::LDCL_POST: 1450 case ARM::LDCL_OPTION: 1451 case ARM::STC_OFFSET: 1452 case ARM::STC_PRE: 1453 case ARM::STC_POST: 1454 case ARM::STC_OPTION: 1455 case ARM::STCL_OFFSET: 1456 case ARM::STCL_PRE: 1457 case ARM::STCL_POST: 1458 case ARM::STCL_OPTION: 1459 case ARM::t2LDC_OFFSET: 1460 case ARM::t2LDC_PRE: 1461 case ARM::t2LDC_POST: 1462 case ARM::t2LDC_OPTION: 1463 case ARM::t2LDCL_OFFSET: 1464 case ARM::t2LDCL_PRE: 1465 case ARM::t2LDCL_POST: 1466 case ARM::t2LDCL_OPTION: 1467 case ARM::t2STC_OFFSET: 1468 case ARM::t2STC_PRE: 1469 case ARM::t2STC_POST: 1470 case ARM::t2STC_OPTION: 1471 case ARM::t2STCL_OFFSET: 1472 case ARM::t2STCL_PRE: 1473 case ARM::t2STCL_POST: 1474 case ARM::t2STCL_OPTION: 1475 case ARM::t2LDC2_OFFSET: 1476 case ARM::t2LDC2L_OFFSET: 1477 case ARM::t2LDC2_PRE: 1478 case ARM::t2LDC2L_PRE: 1479 case ARM::t2STC2_OFFSET: 1480 case ARM::t2STC2L_OFFSET: 1481 case ARM::t2STC2_PRE: 1482 case ARM::t2STC2L_PRE: 1483 case ARM::LDC2_OFFSET: 1484 case ARM::LDC2L_OFFSET: 1485 case ARM::LDC2_PRE: 1486 case ARM::LDC2L_PRE: 1487 case ARM::STC2_OFFSET: 1488 case ARM::STC2L_OFFSET: 1489 case ARM::STC2_PRE: 1490 case ARM::STC2L_PRE: 1491 case ARM::t2LDC2_OPTION: 1492 case ARM::t2STC2_OPTION: 1493 case ARM::t2LDC2_POST: 1494 case ARM::t2LDC2L_POST: 1495 case ARM::t2STC2_POST: 1496 case ARM::t2STC2L_POST: 1497 case ARM::LDC2_POST: 1498 case ARM::LDC2L_POST: 1499 case ARM::STC2_POST: 1500 case ARM::STC2L_POST: 1501 if (coproc == 0xA || coproc == 0xB || 1502 (featureBits[ARM::HasV8_1MMainlineOps] && 1503 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1504 coproc == 0xE || coproc == 0xF))) 1505 return MCDisassembler::Fail; 1506 break; 1507 default: 1508 break; 1509 } 1510 1511 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1512 return MCDisassembler::Fail; 1513 1514 Inst.addOperand(MCOperand::createImm(coproc)); 1515 Inst.addOperand(MCOperand::createImm(CRd)); 1516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1517 return MCDisassembler::Fail; 1518 1519 switch (Inst.getOpcode()) { 1520 case ARM::t2LDC2_OFFSET: 1521 case ARM::t2LDC2L_OFFSET: 1522 case ARM::t2LDC2_PRE: 1523 case ARM::t2LDC2L_PRE: 1524 case ARM::t2STC2_OFFSET: 1525 case ARM::t2STC2L_OFFSET: 1526 case ARM::t2STC2_PRE: 1527 case ARM::t2STC2L_PRE: 1528 case ARM::LDC2_OFFSET: 1529 case ARM::LDC2L_OFFSET: 1530 case ARM::LDC2_PRE: 1531 case ARM::LDC2L_PRE: 1532 case ARM::STC2_OFFSET: 1533 case ARM::STC2L_OFFSET: 1534 case ARM::STC2_PRE: 1535 case ARM::STC2L_PRE: 1536 case ARM::t2LDC_OFFSET: 1537 case ARM::t2LDCL_OFFSET: 1538 case ARM::t2LDC_PRE: 1539 case ARM::t2LDCL_PRE: 1540 case ARM::t2STC_OFFSET: 1541 case ARM::t2STCL_OFFSET: 1542 case ARM::t2STC_PRE: 1543 case ARM::t2STCL_PRE: 1544 case ARM::LDC_OFFSET: 1545 case ARM::LDCL_OFFSET: 1546 case ARM::LDC_PRE: 1547 case ARM::LDCL_PRE: 1548 case ARM::STC_OFFSET: 1549 case ARM::STCL_OFFSET: 1550 case ARM::STC_PRE: 1551 case ARM::STCL_PRE: 1552 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1553 Inst.addOperand(MCOperand::createImm(imm)); 1554 break; 1555 case ARM::t2LDC2_POST: 1556 case ARM::t2LDC2L_POST: 1557 case ARM::t2STC2_POST: 1558 case ARM::t2STC2L_POST: 1559 case ARM::LDC2_POST: 1560 case ARM::LDC2L_POST: 1561 case ARM::STC2_POST: 1562 case ARM::STC2L_POST: 1563 case ARM::t2LDC_POST: 1564 case ARM::t2LDCL_POST: 1565 case ARM::t2STC_POST: 1566 case ARM::t2STCL_POST: 1567 case ARM::LDC_POST: 1568 case ARM::LDCL_POST: 1569 case ARM::STC_POST: 1570 case ARM::STCL_POST: 1571 imm |= U << 8; 1572 LLVM_FALLTHROUGH; 1573 default: 1574 // The 'option' variant doesn't encode 'U' in the immediate since 1575 // the immediate is unsigned [0,255]. 1576 Inst.addOperand(MCOperand::createImm(imm)); 1577 break; 1578 } 1579 1580 switch (Inst.getOpcode()) { 1581 case ARM::LDC_OFFSET: 1582 case ARM::LDC_PRE: 1583 case ARM::LDC_POST: 1584 case ARM::LDC_OPTION: 1585 case ARM::LDCL_OFFSET: 1586 case ARM::LDCL_PRE: 1587 case ARM::LDCL_POST: 1588 case ARM::LDCL_OPTION: 1589 case ARM::STC_OFFSET: 1590 case ARM::STC_PRE: 1591 case ARM::STC_POST: 1592 case ARM::STC_OPTION: 1593 case ARM::STCL_OFFSET: 1594 case ARM::STCL_PRE: 1595 case ARM::STCL_POST: 1596 case ARM::STCL_OPTION: 1597 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1598 return MCDisassembler::Fail; 1599 break; 1600 default: 1601 break; 1602 } 1603 1604 return S; 1605 } 1606 1607 static DecodeStatus 1608 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1609 uint64_t Address, const void *Decoder) { 1610 DecodeStatus S = MCDisassembler::Success; 1611 1612 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1613 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1614 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1615 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1616 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1617 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1618 unsigned P = fieldFromInstruction(Insn, 24, 1); 1619 unsigned W = fieldFromInstruction(Insn, 21, 1); 1620 1621 // On stores, the writeback operand precedes Rt. 1622 switch (Inst.getOpcode()) { 1623 case ARM::STR_POST_IMM: 1624 case ARM::STR_POST_REG: 1625 case ARM::STRB_POST_IMM: 1626 case ARM::STRB_POST_REG: 1627 case ARM::STRT_POST_REG: 1628 case ARM::STRT_POST_IMM: 1629 case ARM::STRBT_POST_REG: 1630 case ARM::STRBT_POST_IMM: 1631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1632 return MCDisassembler::Fail; 1633 break; 1634 default: 1635 break; 1636 } 1637 1638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1639 return MCDisassembler::Fail; 1640 1641 // On loads, the writeback operand comes after Rt. 1642 switch (Inst.getOpcode()) { 1643 case ARM::LDR_POST_IMM: 1644 case ARM::LDR_POST_REG: 1645 case ARM::LDRB_POST_IMM: 1646 case ARM::LDRB_POST_REG: 1647 case ARM::LDRBT_POST_REG: 1648 case ARM::LDRBT_POST_IMM: 1649 case ARM::LDRT_POST_REG: 1650 case ARM::LDRT_POST_IMM: 1651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1652 return MCDisassembler::Fail; 1653 break; 1654 default: 1655 break; 1656 } 1657 1658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1659 return MCDisassembler::Fail; 1660 1661 ARM_AM::AddrOpc Op = ARM_AM::add; 1662 if (!fieldFromInstruction(Insn, 23, 1)) 1663 Op = ARM_AM::sub; 1664 1665 bool writeback = (P == 0) || (W == 1); 1666 unsigned idx_mode = 0; 1667 if (P && writeback) 1668 idx_mode = ARMII::IndexModePre; 1669 else if (!P && writeback) 1670 idx_mode = ARMII::IndexModePost; 1671 1672 if (writeback && (Rn == 15 || Rn == Rt)) 1673 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1674 1675 if (reg) { 1676 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1677 return MCDisassembler::Fail; 1678 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1679 switch( fieldFromInstruction(Insn, 5, 2)) { 1680 case 0: 1681 Opc = ARM_AM::lsl; 1682 break; 1683 case 1: 1684 Opc = ARM_AM::lsr; 1685 break; 1686 case 2: 1687 Opc = ARM_AM::asr; 1688 break; 1689 case 3: 1690 Opc = ARM_AM::ror; 1691 break; 1692 default: 1693 return MCDisassembler::Fail; 1694 } 1695 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1696 if (Opc == ARM_AM::ror && amt == 0) 1697 Opc = ARM_AM::rrx; 1698 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1699 1700 Inst.addOperand(MCOperand::createImm(imm)); 1701 } else { 1702 Inst.addOperand(MCOperand::createReg(0)); 1703 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1704 Inst.addOperand(MCOperand::createImm(tmp)); 1705 } 1706 1707 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1708 return MCDisassembler::Fail; 1709 1710 return S; 1711 } 1712 1713 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1714 uint64_t Address, const void *Decoder) { 1715 DecodeStatus S = MCDisassembler::Success; 1716 1717 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1718 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1719 unsigned type = fieldFromInstruction(Val, 5, 2); 1720 unsigned imm = fieldFromInstruction(Val, 7, 5); 1721 unsigned U = fieldFromInstruction(Val, 12, 1); 1722 1723 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1724 switch (type) { 1725 case 0: 1726 ShOp = ARM_AM::lsl; 1727 break; 1728 case 1: 1729 ShOp = ARM_AM::lsr; 1730 break; 1731 case 2: 1732 ShOp = ARM_AM::asr; 1733 break; 1734 case 3: 1735 ShOp = ARM_AM::ror; 1736 break; 1737 } 1738 1739 if (ShOp == ARM_AM::ror && imm == 0) 1740 ShOp = ARM_AM::rrx; 1741 1742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1743 return MCDisassembler::Fail; 1744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1745 return MCDisassembler::Fail; 1746 unsigned shift; 1747 if (U) 1748 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1749 else 1750 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1751 Inst.addOperand(MCOperand::createImm(shift)); 1752 1753 return S; 1754 } 1755 1756 static DecodeStatus 1757 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1758 uint64_t Address, const void *Decoder) { 1759 DecodeStatus S = MCDisassembler::Success; 1760 1761 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1762 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1763 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1764 unsigned type = fieldFromInstruction(Insn, 22, 1); 1765 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1766 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1767 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1768 unsigned W = fieldFromInstruction(Insn, 21, 1); 1769 unsigned P = fieldFromInstruction(Insn, 24, 1); 1770 unsigned Rt2 = Rt + 1; 1771 1772 bool writeback = (W == 1) | (P == 0); 1773 1774 // For {LD,ST}RD, Rt must be even, else undefined. 1775 switch (Inst.getOpcode()) { 1776 case ARM::STRD: 1777 case ARM::STRD_PRE: 1778 case ARM::STRD_POST: 1779 case ARM::LDRD: 1780 case ARM::LDRD_PRE: 1781 case ARM::LDRD_POST: 1782 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1783 break; 1784 default: 1785 break; 1786 } 1787 switch (Inst.getOpcode()) { 1788 case ARM::STRD: 1789 case ARM::STRD_PRE: 1790 case ARM::STRD_POST: 1791 if (P == 0 && W == 1) 1792 S = MCDisassembler::SoftFail; 1793 1794 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1795 S = MCDisassembler::SoftFail; 1796 if (type && Rm == 15) 1797 S = MCDisassembler::SoftFail; 1798 if (Rt2 == 15) 1799 S = MCDisassembler::SoftFail; 1800 if (!type && fieldFromInstruction(Insn, 8, 4)) 1801 S = MCDisassembler::SoftFail; 1802 break; 1803 case ARM::STRH: 1804 case ARM::STRH_PRE: 1805 case ARM::STRH_POST: 1806 if (Rt == 15) 1807 S = MCDisassembler::SoftFail; 1808 if (writeback && (Rn == 15 || Rn == Rt)) 1809 S = MCDisassembler::SoftFail; 1810 if (!type && Rm == 15) 1811 S = MCDisassembler::SoftFail; 1812 break; 1813 case ARM::LDRD: 1814 case ARM::LDRD_PRE: 1815 case ARM::LDRD_POST: 1816 if (type && Rn == 15) { 1817 if (Rt2 == 15) 1818 S = MCDisassembler::SoftFail; 1819 break; 1820 } 1821 if (P == 0 && W == 1) 1822 S = MCDisassembler::SoftFail; 1823 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1824 S = MCDisassembler::SoftFail; 1825 if (!type && writeback && Rn == 15) 1826 S = MCDisassembler::SoftFail; 1827 if (writeback && (Rn == Rt || Rn == Rt2)) 1828 S = MCDisassembler::SoftFail; 1829 break; 1830 case ARM::LDRH: 1831 case ARM::LDRH_PRE: 1832 case ARM::LDRH_POST: 1833 if (type && Rn == 15) { 1834 if (Rt == 15) 1835 S = MCDisassembler::SoftFail; 1836 break; 1837 } 1838 if (Rt == 15) 1839 S = MCDisassembler::SoftFail; 1840 if (!type && Rm == 15) 1841 S = MCDisassembler::SoftFail; 1842 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1843 S = MCDisassembler::SoftFail; 1844 break; 1845 case ARM::LDRSH: 1846 case ARM::LDRSH_PRE: 1847 case ARM::LDRSH_POST: 1848 case ARM::LDRSB: 1849 case ARM::LDRSB_PRE: 1850 case ARM::LDRSB_POST: 1851 if (type && Rn == 15) { 1852 if (Rt == 15) 1853 S = MCDisassembler::SoftFail; 1854 break; 1855 } 1856 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1857 S = MCDisassembler::SoftFail; 1858 if (!type && (Rt == 15 || Rm == 15)) 1859 S = MCDisassembler::SoftFail; 1860 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1861 S = MCDisassembler::SoftFail; 1862 break; 1863 default: 1864 break; 1865 } 1866 1867 if (writeback) { // Writeback 1868 if (P) 1869 U |= ARMII::IndexModePre << 9; 1870 else 1871 U |= ARMII::IndexModePost << 9; 1872 1873 // On stores, the writeback operand precedes Rt. 1874 switch (Inst.getOpcode()) { 1875 case ARM::STRD: 1876 case ARM::STRD_PRE: 1877 case ARM::STRD_POST: 1878 case ARM::STRH: 1879 case ARM::STRH_PRE: 1880 case ARM::STRH_POST: 1881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1882 return MCDisassembler::Fail; 1883 break; 1884 default: 1885 break; 1886 } 1887 } 1888 1889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1890 return MCDisassembler::Fail; 1891 switch (Inst.getOpcode()) { 1892 case ARM::STRD: 1893 case ARM::STRD_PRE: 1894 case ARM::STRD_POST: 1895 case ARM::LDRD: 1896 case ARM::LDRD_PRE: 1897 case ARM::LDRD_POST: 1898 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1899 return MCDisassembler::Fail; 1900 break; 1901 default: 1902 break; 1903 } 1904 1905 if (writeback) { 1906 // On loads, the writeback operand comes after Rt. 1907 switch (Inst.getOpcode()) { 1908 case ARM::LDRD: 1909 case ARM::LDRD_PRE: 1910 case ARM::LDRD_POST: 1911 case ARM::LDRH: 1912 case ARM::LDRH_PRE: 1913 case ARM::LDRH_POST: 1914 case ARM::LDRSH: 1915 case ARM::LDRSH_PRE: 1916 case ARM::LDRSH_POST: 1917 case ARM::LDRSB: 1918 case ARM::LDRSB_PRE: 1919 case ARM::LDRSB_POST: 1920 case ARM::LDRHTr: 1921 case ARM::LDRSBTr: 1922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1923 return MCDisassembler::Fail; 1924 break; 1925 default: 1926 break; 1927 } 1928 } 1929 1930 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1931 return MCDisassembler::Fail; 1932 1933 if (type) { 1934 Inst.addOperand(MCOperand::createReg(0)); 1935 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1936 } else { 1937 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1938 return MCDisassembler::Fail; 1939 Inst.addOperand(MCOperand::createImm(U)); 1940 } 1941 1942 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1943 return MCDisassembler::Fail; 1944 1945 return S; 1946 } 1947 1948 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1949 uint64_t Address, const void *Decoder) { 1950 DecodeStatus S = MCDisassembler::Success; 1951 1952 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1953 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1954 1955 switch (mode) { 1956 case 0: 1957 mode = ARM_AM::da; 1958 break; 1959 case 1: 1960 mode = ARM_AM::ia; 1961 break; 1962 case 2: 1963 mode = ARM_AM::db; 1964 break; 1965 case 3: 1966 mode = ARM_AM::ib; 1967 break; 1968 } 1969 1970 Inst.addOperand(MCOperand::createImm(mode)); 1971 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1972 return MCDisassembler::Fail; 1973 1974 return S; 1975 } 1976 1977 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1978 uint64_t Address, const void *Decoder) { 1979 DecodeStatus S = MCDisassembler::Success; 1980 1981 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1982 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1983 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1984 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1985 1986 if (pred == 0xF) 1987 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1988 1989 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1990 return MCDisassembler::Fail; 1991 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1992 return MCDisassembler::Fail; 1993 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1994 return MCDisassembler::Fail; 1995 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1996 return MCDisassembler::Fail; 1997 return S; 1998 } 1999 2000 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2001 unsigned Insn, 2002 uint64_t Address, const void *Decoder) { 2003 DecodeStatus S = MCDisassembler::Success; 2004 2005 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2006 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2007 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2008 2009 if (pred == 0xF) { 2010 // Ambiguous with RFE and SRS 2011 switch (Inst.getOpcode()) { 2012 case ARM::LDMDA: 2013 Inst.setOpcode(ARM::RFEDA); 2014 break; 2015 case ARM::LDMDA_UPD: 2016 Inst.setOpcode(ARM::RFEDA_UPD); 2017 break; 2018 case ARM::LDMDB: 2019 Inst.setOpcode(ARM::RFEDB); 2020 break; 2021 case ARM::LDMDB_UPD: 2022 Inst.setOpcode(ARM::RFEDB_UPD); 2023 break; 2024 case ARM::LDMIA: 2025 Inst.setOpcode(ARM::RFEIA); 2026 break; 2027 case ARM::LDMIA_UPD: 2028 Inst.setOpcode(ARM::RFEIA_UPD); 2029 break; 2030 case ARM::LDMIB: 2031 Inst.setOpcode(ARM::RFEIB); 2032 break; 2033 case ARM::LDMIB_UPD: 2034 Inst.setOpcode(ARM::RFEIB_UPD); 2035 break; 2036 case ARM::STMDA: 2037 Inst.setOpcode(ARM::SRSDA); 2038 break; 2039 case ARM::STMDA_UPD: 2040 Inst.setOpcode(ARM::SRSDA_UPD); 2041 break; 2042 case ARM::STMDB: 2043 Inst.setOpcode(ARM::SRSDB); 2044 break; 2045 case ARM::STMDB_UPD: 2046 Inst.setOpcode(ARM::SRSDB_UPD); 2047 break; 2048 case ARM::STMIA: 2049 Inst.setOpcode(ARM::SRSIA); 2050 break; 2051 case ARM::STMIA_UPD: 2052 Inst.setOpcode(ARM::SRSIA_UPD); 2053 break; 2054 case ARM::STMIB: 2055 Inst.setOpcode(ARM::SRSIB); 2056 break; 2057 case ARM::STMIB_UPD: 2058 Inst.setOpcode(ARM::SRSIB_UPD); 2059 break; 2060 default: 2061 return MCDisassembler::Fail; 2062 } 2063 2064 // For stores (which become SRS's, the only operand is the mode. 2065 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2066 // Check SRS encoding constraints 2067 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2068 fieldFromInstruction(Insn, 20, 1) == 0)) 2069 return MCDisassembler::Fail; 2070 2071 Inst.addOperand( 2072 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2073 return S; 2074 } 2075 2076 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2077 } 2078 2079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2080 return MCDisassembler::Fail; 2081 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2082 return MCDisassembler::Fail; // Tied 2083 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2084 return MCDisassembler::Fail; 2085 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2086 return MCDisassembler::Fail; 2087 2088 return S; 2089 } 2090 2091 // Check for UNPREDICTABLE predicated ESB instruction 2092 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2093 uint64_t Address, const void *Decoder) { 2094 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2095 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2096 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2097 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2098 2099 DecodeStatus S = MCDisassembler::Success; 2100 2101 Inst.addOperand(MCOperand::createImm(imm8)); 2102 2103 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2104 return MCDisassembler::Fail; 2105 2106 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2107 // so all predicates should be allowed. 2108 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2109 S = MCDisassembler::SoftFail; 2110 2111 return S; 2112 } 2113 2114 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2115 uint64_t Address, const void *Decoder) { 2116 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2117 unsigned M = fieldFromInstruction(Insn, 17, 1); 2118 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2119 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2120 2121 DecodeStatus S = MCDisassembler::Success; 2122 2123 // This decoder is called from multiple location that do not check 2124 // the full encoding is valid before they do. 2125 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2126 fieldFromInstruction(Insn, 16, 1) != 0 || 2127 fieldFromInstruction(Insn, 20, 8) != 0x10) 2128 return MCDisassembler::Fail; 2129 2130 // imod == '01' --> UNPREDICTABLE 2131 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2132 // return failure here. The '01' imod value is unprintable, so there's 2133 // nothing useful we could do even if we returned UNPREDICTABLE. 2134 2135 if (imod == 1) return MCDisassembler::Fail; 2136 2137 if (imod && M) { 2138 Inst.setOpcode(ARM::CPS3p); 2139 Inst.addOperand(MCOperand::createImm(imod)); 2140 Inst.addOperand(MCOperand::createImm(iflags)); 2141 Inst.addOperand(MCOperand::createImm(mode)); 2142 } else if (imod && !M) { 2143 Inst.setOpcode(ARM::CPS2p); 2144 Inst.addOperand(MCOperand::createImm(imod)); 2145 Inst.addOperand(MCOperand::createImm(iflags)); 2146 if (mode) S = MCDisassembler::SoftFail; 2147 } else if (!imod && M) { 2148 Inst.setOpcode(ARM::CPS1p); 2149 Inst.addOperand(MCOperand::createImm(mode)); 2150 if (iflags) S = MCDisassembler::SoftFail; 2151 } else { 2152 // imod == '00' && M == '0' --> UNPREDICTABLE 2153 Inst.setOpcode(ARM::CPS1p); 2154 Inst.addOperand(MCOperand::createImm(mode)); 2155 S = MCDisassembler::SoftFail; 2156 } 2157 2158 return S; 2159 } 2160 2161 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2162 uint64_t Address, const void *Decoder) { 2163 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2164 unsigned M = fieldFromInstruction(Insn, 8, 1); 2165 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2166 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2167 2168 DecodeStatus S = MCDisassembler::Success; 2169 2170 // imod == '01' --> UNPREDICTABLE 2171 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2172 // return failure here. The '01' imod value is unprintable, so there's 2173 // nothing useful we could do even if we returned UNPREDICTABLE. 2174 2175 if (imod == 1) return MCDisassembler::Fail; 2176 2177 if (imod && M) { 2178 Inst.setOpcode(ARM::t2CPS3p); 2179 Inst.addOperand(MCOperand::createImm(imod)); 2180 Inst.addOperand(MCOperand::createImm(iflags)); 2181 Inst.addOperand(MCOperand::createImm(mode)); 2182 } else if (imod && !M) { 2183 Inst.setOpcode(ARM::t2CPS2p); 2184 Inst.addOperand(MCOperand::createImm(imod)); 2185 Inst.addOperand(MCOperand::createImm(iflags)); 2186 if (mode) S = MCDisassembler::SoftFail; 2187 } else if (!imod && M) { 2188 Inst.setOpcode(ARM::t2CPS1p); 2189 Inst.addOperand(MCOperand::createImm(mode)); 2190 if (iflags) S = MCDisassembler::SoftFail; 2191 } else { 2192 // imod == '00' && M == '0' --> this is a HINT instruction 2193 int imm = fieldFromInstruction(Insn, 0, 8); 2194 // HINT are defined only for immediate in [0..4] 2195 if(imm > 4) return MCDisassembler::Fail; 2196 Inst.setOpcode(ARM::t2HINT); 2197 Inst.addOperand(MCOperand::createImm(imm)); 2198 } 2199 2200 return S; 2201 } 2202 2203 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2204 uint64_t Address, const void *Decoder) { 2205 DecodeStatus S = MCDisassembler::Success; 2206 2207 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2208 unsigned imm = 0; 2209 2210 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2211 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2212 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2213 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2214 2215 if (Inst.getOpcode() == ARM::t2MOVTi16) 2216 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2217 return MCDisassembler::Fail; 2218 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2219 return MCDisassembler::Fail; 2220 2221 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2222 Inst.addOperand(MCOperand::createImm(imm)); 2223 2224 return S; 2225 } 2226 2227 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2228 uint64_t Address, const void *Decoder) { 2229 DecodeStatus S = MCDisassembler::Success; 2230 2231 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2232 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2233 unsigned imm = 0; 2234 2235 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2236 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2237 2238 if (Inst.getOpcode() == ARM::MOVTi16) 2239 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2240 return MCDisassembler::Fail; 2241 2242 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2243 return MCDisassembler::Fail; 2244 2245 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2246 Inst.addOperand(MCOperand::createImm(imm)); 2247 2248 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2249 return MCDisassembler::Fail; 2250 2251 return S; 2252 } 2253 2254 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2255 uint64_t Address, const void *Decoder) { 2256 DecodeStatus S = MCDisassembler::Success; 2257 2258 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2259 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2260 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2261 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2262 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2263 2264 if (pred == 0xF) 2265 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2266 2267 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2268 return MCDisassembler::Fail; 2269 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2270 return MCDisassembler::Fail; 2271 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2272 return MCDisassembler::Fail; 2273 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2274 return MCDisassembler::Fail; 2275 2276 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2277 return MCDisassembler::Fail; 2278 2279 return S; 2280 } 2281 2282 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2283 uint64_t Address, const void *Decoder) { 2284 DecodeStatus S = MCDisassembler::Success; 2285 2286 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2287 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2288 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2289 2290 if (Pred == 0xF) 2291 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2292 2293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2294 return MCDisassembler::Fail; 2295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2296 return MCDisassembler::Fail; 2297 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2298 return MCDisassembler::Fail; 2299 2300 return S; 2301 } 2302 2303 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2304 uint64_t Address, const void *Decoder) { 2305 DecodeStatus S = MCDisassembler::Success; 2306 2307 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2308 2309 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2310 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2311 2312 if (!FeatureBits[ARM::HasV8_1aOps] || 2313 !FeatureBits[ARM::HasV8Ops]) 2314 return MCDisassembler::Fail; 2315 2316 // Decoder can be called from DecodeTST, which does not check the full 2317 // encoding is valid. 2318 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2319 fieldFromInstruction(Insn, 4,4) != 0) 2320 return MCDisassembler::Fail; 2321 if (fieldFromInstruction(Insn, 10,10) != 0 || 2322 fieldFromInstruction(Insn, 0,4) != 0) 2323 S = MCDisassembler::SoftFail; 2324 2325 Inst.setOpcode(ARM::SETPAN); 2326 Inst.addOperand(MCOperand::createImm(Imm)); 2327 2328 return S; 2329 } 2330 2331 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2332 uint64_t Address, const void *Decoder) { 2333 DecodeStatus S = MCDisassembler::Success; 2334 2335 unsigned add = fieldFromInstruction(Val, 12, 1); 2336 unsigned imm = fieldFromInstruction(Val, 0, 12); 2337 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2338 2339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2340 return MCDisassembler::Fail; 2341 2342 if (!add) imm *= -1; 2343 if (imm == 0 && !add) imm = INT32_MIN; 2344 Inst.addOperand(MCOperand::createImm(imm)); 2345 if (Rn == 15) 2346 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2347 2348 return S; 2349 } 2350 2351 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2352 uint64_t Address, const void *Decoder) { 2353 DecodeStatus S = MCDisassembler::Success; 2354 2355 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2356 // U == 1 to add imm, 0 to subtract it. 2357 unsigned U = fieldFromInstruction(Val, 8, 1); 2358 unsigned imm = fieldFromInstruction(Val, 0, 8); 2359 2360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2361 return MCDisassembler::Fail; 2362 2363 if (U) 2364 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2365 else 2366 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2367 2368 return S; 2369 } 2370 2371 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2372 uint64_t Address, const void *Decoder) { 2373 DecodeStatus S = MCDisassembler::Success; 2374 2375 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2376 // U == 1 to add imm, 0 to subtract it. 2377 unsigned U = fieldFromInstruction(Val, 8, 1); 2378 unsigned imm = fieldFromInstruction(Val, 0, 8); 2379 2380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2381 return MCDisassembler::Fail; 2382 2383 if (U) 2384 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2385 else 2386 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2387 2388 return S; 2389 } 2390 2391 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2392 uint64_t Address, const void *Decoder) { 2393 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2394 } 2395 2396 static DecodeStatus 2397 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2398 uint64_t Address, const void *Decoder) { 2399 DecodeStatus Status = MCDisassembler::Success; 2400 2401 // Note the J1 and J2 values are from the encoded instruction. So here 2402 // change them to I1 and I2 values via as documented: 2403 // I1 = NOT(J1 EOR S); 2404 // I2 = NOT(J2 EOR S); 2405 // and build the imm32 with one trailing zero as documented: 2406 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2407 unsigned S = fieldFromInstruction(Insn, 26, 1); 2408 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2409 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2410 unsigned I1 = !(J1 ^ S); 2411 unsigned I2 = !(J2 ^ S); 2412 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2413 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2414 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2415 int imm32 = SignExtend32<25>(tmp << 1); 2416 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2417 true, 4, Inst, Decoder)) 2418 Inst.addOperand(MCOperand::createImm(imm32)); 2419 2420 return Status; 2421 } 2422 2423 static DecodeStatus 2424 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2425 uint64_t Address, const void *Decoder) { 2426 DecodeStatus S = MCDisassembler::Success; 2427 2428 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2429 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2430 2431 if (pred == 0xF) { 2432 Inst.setOpcode(ARM::BLXi); 2433 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2434 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2435 true, 4, Inst, Decoder)) 2436 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2437 return S; 2438 } 2439 2440 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2441 true, 4, Inst, Decoder)) 2442 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2443 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2444 return MCDisassembler::Fail; 2445 2446 return S; 2447 } 2448 2449 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2450 uint64_t Address, const void *Decoder) { 2451 DecodeStatus S = MCDisassembler::Success; 2452 2453 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2454 unsigned align = fieldFromInstruction(Val, 4, 2); 2455 2456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2457 return MCDisassembler::Fail; 2458 if (!align) 2459 Inst.addOperand(MCOperand::createImm(0)); 2460 else 2461 Inst.addOperand(MCOperand::createImm(4 << align)); 2462 2463 return S; 2464 } 2465 2466 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2467 uint64_t Address, const void *Decoder) { 2468 DecodeStatus S = MCDisassembler::Success; 2469 2470 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2471 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2472 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2473 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2474 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2475 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2476 2477 // First output register 2478 switch (Inst.getOpcode()) { 2479 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2480 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2481 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2482 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2483 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2484 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2485 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2486 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2487 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2488 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2489 return MCDisassembler::Fail; 2490 break; 2491 case ARM::VLD2b16: 2492 case ARM::VLD2b32: 2493 case ARM::VLD2b8: 2494 case ARM::VLD2b16wb_fixed: 2495 case ARM::VLD2b16wb_register: 2496 case ARM::VLD2b32wb_fixed: 2497 case ARM::VLD2b32wb_register: 2498 case ARM::VLD2b8wb_fixed: 2499 case ARM::VLD2b8wb_register: 2500 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2501 return MCDisassembler::Fail; 2502 break; 2503 default: 2504 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2505 return MCDisassembler::Fail; 2506 } 2507 2508 // Second output register 2509 switch (Inst.getOpcode()) { 2510 case ARM::VLD3d8: 2511 case ARM::VLD3d16: 2512 case ARM::VLD3d32: 2513 case ARM::VLD3d8_UPD: 2514 case ARM::VLD3d16_UPD: 2515 case ARM::VLD3d32_UPD: 2516 case ARM::VLD4d8: 2517 case ARM::VLD4d16: 2518 case ARM::VLD4d32: 2519 case ARM::VLD4d8_UPD: 2520 case ARM::VLD4d16_UPD: 2521 case ARM::VLD4d32_UPD: 2522 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2523 return MCDisassembler::Fail; 2524 break; 2525 case ARM::VLD3q8: 2526 case ARM::VLD3q16: 2527 case ARM::VLD3q32: 2528 case ARM::VLD3q8_UPD: 2529 case ARM::VLD3q16_UPD: 2530 case ARM::VLD3q32_UPD: 2531 case ARM::VLD4q8: 2532 case ARM::VLD4q16: 2533 case ARM::VLD4q32: 2534 case ARM::VLD4q8_UPD: 2535 case ARM::VLD4q16_UPD: 2536 case ARM::VLD4q32_UPD: 2537 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2538 return MCDisassembler::Fail; 2539 break; 2540 default: 2541 break; 2542 } 2543 2544 // Third output register 2545 switch(Inst.getOpcode()) { 2546 case ARM::VLD3d8: 2547 case ARM::VLD3d16: 2548 case ARM::VLD3d32: 2549 case ARM::VLD3d8_UPD: 2550 case ARM::VLD3d16_UPD: 2551 case ARM::VLD3d32_UPD: 2552 case ARM::VLD4d8: 2553 case ARM::VLD4d16: 2554 case ARM::VLD4d32: 2555 case ARM::VLD4d8_UPD: 2556 case ARM::VLD4d16_UPD: 2557 case ARM::VLD4d32_UPD: 2558 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2559 return MCDisassembler::Fail; 2560 break; 2561 case ARM::VLD3q8: 2562 case ARM::VLD3q16: 2563 case ARM::VLD3q32: 2564 case ARM::VLD3q8_UPD: 2565 case ARM::VLD3q16_UPD: 2566 case ARM::VLD3q32_UPD: 2567 case ARM::VLD4q8: 2568 case ARM::VLD4q16: 2569 case ARM::VLD4q32: 2570 case ARM::VLD4q8_UPD: 2571 case ARM::VLD4q16_UPD: 2572 case ARM::VLD4q32_UPD: 2573 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2574 return MCDisassembler::Fail; 2575 break; 2576 default: 2577 break; 2578 } 2579 2580 // Fourth output register 2581 switch (Inst.getOpcode()) { 2582 case ARM::VLD4d8: 2583 case ARM::VLD4d16: 2584 case ARM::VLD4d32: 2585 case ARM::VLD4d8_UPD: 2586 case ARM::VLD4d16_UPD: 2587 case ARM::VLD4d32_UPD: 2588 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2589 return MCDisassembler::Fail; 2590 break; 2591 case ARM::VLD4q8: 2592 case ARM::VLD4q16: 2593 case ARM::VLD4q32: 2594 case ARM::VLD4q8_UPD: 2595 case ARM::VLD4q16_UPD: 2596 case ARM::VLD4q32_UPD: 2597 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2598 return MCDisassembler::Fail; 2599 break; 2600 default: 2601 break; 2602 } 2603 2604 // Writeback operand 2605 switch (Inst.getOpcode()) { 2606 case ARM::VLD1d8wb_fixed: 2607 case ARM::VLD1d16wb_fixed: 2608 case ARM::VLD1d32wb_fixed: 2609 case ARM::VLD1d64wb_fixed: 2610 case ARM::VLD1d8wb_register: 2611 case ARM::VLD1d16wb_register: 2612 case ARM::VLD1d32wb_register: 2613 case ARM::VLD1d64wb_register: 2614 case ARM::VLD1q8wb_fixed: 2615 case ARM::VLD1q16wb_fixed: 2616 case ARM::VLD1q32wb_fixed: 2617 case ARM::VLD1q64wb_fixed: 2618 case ARM::VLD1q8wb_register: 2619 case ARM::VLD1q16wb_register: 2620 case ARM::VLD1q32wb_register: 2621 case ARM::VLD1q64wb_register: 2622 case ARM::VLD1d8Twb_fixed: 2623 case ARM::VLD1d8Twb_register: 2624 case ARM::VLD1d16Twb_fixed: 2625 case ARM::VLD1d16Twb_register: 2626 case ARM::VLD1d32Twb_fixed: 2627 case ARM::VLD1d32Twb_register: 2628 case ARM::VLD1d64Twb_fixed: 2629 case ARM::VLD1d64Twb_register: 2630 case ARM::VLD1d8Qwb_fixed: 2631 case ARM::VLD1d8Qwb_register: 2632 case ARM::VLD1d16Qwb_fixed: 2633 case ARM::VLD1d16Qwb_register: 2634 case ARM::VLD1d32Qwb_fixed: 2635 case ARM::VLD1d32Qwb_register: 2636 case ARM::VLD1d64Qwb_fixed: 2637 case ARM::VLD1d64Qwb_register: 2638 case ARM::VLD2d8wb_fixed: 2639 case ARM::VLD2d16wb_fixed: 2640 case ARM::VLD2d32wb_fixed: 2641 case ARM::VLD2q8wb_fixed: 2642 case ARM::VLD2q16wb_fixed: 2643 case ARM::VLD2q32wb_fixed: 2644 case ARM::VLD2d8wb_register: 2645 case ARM::VLD2d16wb_register: 2646 case ARM::VLD2d32wb_register: 2647 case ARM::VLD2q8wb_register: 2648 case ARM::VLD2q16wb_register: 2649 case ARM::VLD2q32wb_register: 2650 case ARM::VLD2b8wb_fixed: 2651 case ARM::VLD2b16wb_fixed: 2652 case ARM::VLD2b32wb_fixed: 2653 case ARM::VLD2b8wb_register: 2654 case ARM::VLD2b16wb_register: 2655 case ARM::VLD2b32wb_register: 2656 Inst.addOperand(MCOperand::createImm(0)); 2657 break; 2658 case ARM::VLD3d8_UPD: 2659 case ARM::VLD3d16_UPD: 2660 case ARM::VLD3d32_UPD: 2661 case ARM::VLD3q8_UPD: 2662 case ARM::VLD3q16_UPD: 2663 case ARM::VLD3q32_UPD: 2664 case ARM::VLD4d8_UPD: 2665 case ARM::VLD4d16_UPD: 2666 case ARM::VLD4d32_UPD: 2667 case ARM::VLD4q8_UPD: 2668 case ARM::VLD4q16_UPD: 2669 case ARM::VLD4q32_UPD: 2670 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2671 return MCDisassembler::Fail; 2672 break; 2673 default: 2674 break; 2675 } 2676 2677 // AddrMode6 Base (register+alignment) 2678 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2679 return MCDisassembler::Fail; 2680 2681 // AddrMode6 Offset (register) 2682 switch (Inst.getOpcode()) { 2683 default: 2684 // The below have been updated to have explicit am6offset split 2685 // between fixed and register offset. For those instructions not 2686 // yet updated, we need to add an additional reg0 operand for the 2687 // fixed variant. 2688 // 2689 // The fixed offset encodes as Rm == 0xd, so we check for that. 2690 if (Rm == 0xd) { 2691 Inst.addOperand(MCOperand::createReg(0)); 2692 break; 2693 } 2694 // Fall through to handle the register offset variant. 2695 LLVM_FALLTHROUGH; 2696 case ARM::VLD1d8wb_fixed: 2697 case ARM::VLD1d16wb_fixed: 2698 case ARM::VLD1d32wb_fixed: 2699 case ARM::VLD1d64wb_fixed: 2700 case ARM::VLD1d8Twb_fixed: 2701 case ARM::VLD1d16Twb_fixed: 2702 case ARM::VLD1d32Twb_fixed: 2703 case ARM::VLD1d64Twb_fixed: 2704 case ARM::VLD1d8Qwb_fixed: 2705 case ARM::VLD1d16Qwb_fixed: 2706 case ARM::VLD1d32Qwb_fixed: 2707 case ARM::VLD1d64Qwb_fixed: 2708 case ARM::VLD1d8wb_register: 2709 case ARM::VLD1d16wb_register: 2710 case ARM::VLD1d32wb_register: 2711 case ARM::VLD1d64wb_register: 2712 case ARM::VLD1q8wb_fixed: 2713 case ARM::VLD1q16wb_fixed: 2714 case ARM::VLD1q32wb_fixed: 2715 case ARM::VLD1q64wb_fixed: 2716 case ARM::VLD1q8wb_register: 2717 case ARM::VLD1q16wb_register: 2718 case ARM::VLD1q32wb_register: 2719 case ARM::VLD1q64wb_register: 2720 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2721 // variant encodes Rm == 0xf. Anything else is a register offset post- 2722 // increment and we need to add the register operand to the instruction. 2723 if (Rm != 0xD && Rm != 0xF && 2724 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2725 return MCDisassembler::Fail; 2726 break; 2727 case ARM::VLD2d8wb_fixed: 2728 case ARM::VLD2d16wb_fixed: 2729 case ARM::VLD2d32wb_fixed: 2730 case ARM::VLD2b8wb_fixed: 2731 case ARM::VLD2b16wb_fixed: 2732 case ARM::VLD2b32wb_fixed: 2733 case ARM::VLD2q8wb_fixed: 2734 case ARM::VLD2q16wb_fixed: 2735 case ARM::VLD2q32wb_fixed: 2736 break; 2737 } 2738 2739 return S; 2740 } 2741 2742 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2743 uint64_t Address, const void *Decoder) { 2744 unsigned type = fieldFromInstruction(Insn, 8, 4); 2745 unsigned align = fieldFromInstruction(Insn, 4, 2); 2746 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2747 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2748 if (type == 10 && align == 3) return MCDisassembler::Fail; 2749 2750 unsigned load = fieldFromInstruction(Insn, 21, 1); 2751 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2752 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2753 } 2754 2755 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2756 uint64_t Address, const void *Decoder) { 2757 unsigned size = fieldFromInstruction(Insn, 6, 2); 2758 if (size == 3) return MCDisassembler::Fail; 2759 2760 unsigned type = fieldFromInstruction(Insn, 8, 4); 2761 unsigned align = fieldFromInstruction(Insn, 4, 2); 2762 if (type == 8 && align == 3) return MCDisassembler::Fail; 2763 if (type == 9 && align == 3) return MCDisassembler::Fail; 2764 2765 unsigned load = fieldFromInstruction(Insn, 21, 1); 2766 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2767 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2768 } 2769 2770 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2771 uint64_t Address, const void *Decoder) { 2772 unsigned size = fieldFromInstruction(Insn, 6, 2); 2773 if (size == 3) return MCDisassembler::Fail; 2774 2775 unsigned align = fieldFromInstruction(Insn, 4, 2); 2776 if (align & 2) return MCDisassembler::Fail; 2777 2778 unsigned load = fieldFromInstruction(Insn, 21, 1); 2779 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2780 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2781 } 2782 2783 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2784 uint64_t Address, const void *Decoder) { 2785 unsigned size = fieldFromInstruction(Insn, 6, 2); 2786 if (size == 3) return MCDisassembler::Fail; 2787 2788 unsigned load = fieldFromInstruction(Insn, 21, 1); 2789 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2790 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2791 } 2792 2793 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2794 uint64_t Address, const void *Decoder) { 2795 DecodeStatus S = MCDisassembler::Success; 2796 2797 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2798 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2799 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2800 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2801 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2802 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2803 2804 // Writeback Operand 2805 switch (Inst.getOpcode()) { 2806 case ARM::VST1d8wb_fixed: 2807 case ARM::VST1d16wb_fixed: 2808 case ARM::VST1d32wb_fixed: 2809 case ARM::VST1d64wb_fixed: 2810 case ARM::VST1d8wb_register: 2811 case ARM::VST1d16wb_register: 2812 case ARM::VST1d32wb_register: 2813 case ARM::VST1d64wb_register: 2814 case ARM::VST1q8wb_fixed: 2815 case ARM::VST1q16wb_fixed: 2816 case ARM::VST1q32wb_fixed: 2817 case ARM::VST1q64wb_fixed: 2818 case ARM::VST1q8wb_register: 2819 case ARM::VST1q16wb_register: 2820 case ARM::VST1q32wb_register: 2821 case ARM::VST1q64wb_register: 2822 case ARM::VST1d8Twb_fixed: 2823 case ARM::VST1d16Twb_fixed: 2824 case ARM::VST1d32Twb_fixed: 2825 case ARM::VST1d64Twb_fixed: 2826 case ARM::VST1d8Twb_register: 2827 case ARM::VST1d16Twb_register: 2828 case ARM::VST1d32Twb_register: 2829 case ARM::VST1d64Twb_register: 2830 case ARM::VST1d8Qwb_fixed: 2831 case ARM::VST1d16Qwb_fixed: 2832 case ARM::VST1d32Qwb_fixed: 2833 case ARM::VST1d64Qwb_fixed: 2834 case ARM::VST1d8Qwb_register: 2835 case ARM::VST1d16Qwb_register: 2836 case ARM::VST1d32Qwb_register: 2837 case ARM::VST1d64Qwb_register: 2838 case ARM::VST2d8wb_fixed: 2839 case ARM::VST2d16wb_fixed: 2840 case ARM::VST2d32wb_fixed: 2841 case ARM::VST2d8wb_register: 2842 case ARM::VST2d16wb_register: 2843 case ARM::VST2d32wb_register: 2844 case ARM::VST2q8wb_fixed: 2845 case ARM::VST2q16wb_fixed: 2846 case ARM::VST2q32wb_fixed: 2847 case ARM::VST2q8wb_register: 2848 case ARM::VST2q16wb_register: 2849 case ARM::VST2q32wb_register: 2850 case ARM::VST2b8wb_fixed: 2851 case ARM::VST2b16wb_fixed: 2852 case ARM::VST2b32wb_fixed: 2853 case ARM::VST2b8wb_register: 2854 case ARM::VST2b16wb_register: 2855 case ARM::VST2b32wb_register: 2856 if (Rm == 0xF) 2857 return MCDisassembler::Fail; 2858 Inst.addOperand(MCOperand::createImm(0)); 2859 break; 2860 case ARM::VST3d8_UPD: 2861 case ARM::VST3d16_UPD: 2862 case ARM::VST3d32_UPD: 2863 case ARM::VST3q8_UPD: 2864 case ARM::VST3q16_UPD: 2865 case ARM::VST3q32_UPD: 2866 case ARM::VST4d8_UPD: 2867 case ARM::VST4d16_UPD: 2868 case ARM::VST4d32_UPD: 2869 case ARM::VST4q8_UPD: 2870 case ARM::VST4q16_UPD: 2871 case ARM::VST4q32_UPD: 2872 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2873 return MCDisassembler::Fail; 2874 break; 2875 default: 2876 break; 2877 } 2878 2879 // AddrMode6 Base (register+alignment) 2880 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2881 return MCDisassembler::Fail; 2882 2883 // AddrMode6 Offset (register) 2884 switch (Inst.getOpcode()) { 2885 default: 2886 if (Rm == 0xD) 2887 Inst.addOperand(MCOperand::createReg(0)); 2888 else if (Rm != 0xF) { 2889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2890 return MCDisassembler::Fail; 2891 } 2892 break; 2893 case ARM::VST1d8wb_fixed: 2894 case ARM::VST1d16wb_fixed: 2895 case ARM::VST1d32wb_fixed: 2896 case ARM::VST1d64wb_fixed: 2897 case ARM::VST1q8wb_fixed: 2898 case ARM::VST1q16wb_fixed: 2899 case ARM::VST1q32wb_fixed: 2900 case ARM::VST1q64wb_fixed: 2901 case ARM::VST1d8Twb_fixed: 2902 case ARM::VST1d16Twb_fixed: 2903 case ARM::VST1d32Twb_fixed: 2904 case ARM::VST1d64Twb_fixed: 2905 case ARM::VST1d8Qwb_fixed: 2906 case ARM::VST1d16Qwb_fixed: 2907 case ARM::VST1d32Qwb_fixed: 2908 case ARM::VST1d64Qwb_fixed: 2909 case ARM::VST2d8wb_fixed: 2910 case ARM::VST2d16wb_fixed: 2911 case ARM::VST2d32wb_fixed: 2912 case ARM::VST2q8wb_fixed: 2913 case ARM::VST2q16wb_fixed: 2914 case ARM::VST2q32wb_fixed: 2915 case ARM::VST2b8wb_fixed: 2916 case ARM::VST2b16wb_fixed: 2917 case ARM::VST2b32wb_fixed: 2918 break; 2919 } 2920 2921 // First input register 2922 switch (Inst.getOpcode()) { 2923 case ARM::VST1q16: 2924 case ARM::VST1q32: 2925 case ARM::VST1q64: 2926 case ARM::VST1q8: 2927 case ARM::VST1q16wb_fixed: 2928 case ARM::VST1q16wb_register: 2929 case ARM::VST1q32wb_fixed: 2930 case ARM::VST1q32wb_register: 2931 case ARM::VST1q64wb_fixed: 2932 case ARM::VST1q64wb_register: 2933 case ARM::VST1q8wb_fixed: 2934 case ARM::VST1q8wb_register: 2935 case ARM::VST2d16: 2936 case ARM::VST2d32: 2937 case ARM::VST2d8: 2938 case ARM::VST2d16wb_fixed: 2939 case ARM::VST2d16wb_register: 2940 case ARM::VST2d32wb_fixed: 2941 case ARM::VST2d32wb_register: 2942 case ARM::VST2d8wb_fixed: 2943 case ARM::VST2d8wb_register: 2944 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2945 return MCDisassembler::Fail; 2946 break; 2947 case ARM::VST2b16: 2948 case ARM::VST2b32: 2949 case ARM::VST2b8: 2950 case ARM::VST2b16wb_fixed: 2951 case ARM::VST2b16wb_register: 2952 case ARM::VST2b32wb_fixed: 2953 case ARM::VST2b32wb_register: 2954 case ARM::VST2b8wb_fixed: 2955 case ARM::VST2b8wb_register: 2956 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 break; 2959 default: 2960 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2961 return MCDisassembler::Fail; 2962 } 2963 2964 // Second input register 2965 switch (Inst.getOpcode()) { 2966 case ARM::VST3d8: 2967 case ARM::VST3d16: 2968 case ARM::VST3d32: 2969 case ARM::VST3d8_UPD: 2970 case ARM::VST3d16_UPD: 2971 case ARM::VST3d32_UPD: 2972 case ARM::VST4d8: 2973 case ARM::VST4d16: 2974 case ARM::VST4d32: 2975 case ARM::VST4d8_UPD: 2976 case ARM::VST4d16_UPD: 2977 case ARM::VST4d32_UPD: 2978 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2979 return MCDisassembler::Fail; 2980 break; 2981 case ARM::VST3q8: 2982 case ARM::VST3q16: 2983 case ARM::VST3q32: 2984 case ARM::VST3q8_UPD: 2985 case ARM::VST3q16_UPD: 2986 case ARM::VST3q32_UPD: 2987 case ARM::VST4q8: 2988 case ARM::VST4q16: 2989 case ARM::VST4q32: 2990 case ARM::VST4q8_UPD: 2991 case ARM::VST4q16_UPD: 2992 case ARM::VST4q32_UPD: 2993 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2994 return MCDisassembler::Fail; 2995 break; 2996 default: 2997 break; 2998 } 2999 3000 // Third input register 3001 switch (Inst.getOpcode()) { 3002 case ARM::VST3d8: 3003 case ARM::VST3d16: 3004 case ARM::VST3d32: 3005 case ARM::VST3d8_UPD: 3006 case ARM::VST3d16_UPD: 3007 case ARM::VST3d32_UPD: 3008 case ARM::VST4d8: 3009 case ARM::VST4d16: 3010 case ARM::VST4d32: 3011 case ARM::VST4d8_UPD: 3012 case ARM::VST4d16_UPD: 3013 case ARM::VST4d32_UPD: 3014 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3015 return MCDisassembler::Fail; 3016 break; 3017 case ARM::VST3q8: 3018 case ARM::VST3q16: 3019 case ARM::VST3q32: 3020 case ARM::VST3q8_UPD: 3021 case ARM::VST3q16_UPD: 3022 case ARM::VST3q32_UPD: 3023 case ARM::VST4q8: 3024 case ARM::VST4q16: 3025 case ARM::VST4q32: 3026 case ARM::VST4q8_UPD: 3027 case ARM::VST4q16_UPD: 3028 case ARM::VST4q32_UPD: 3029 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3030 return MCDisassembler::Fail; 3031 break; 3032 default: 3033 break; 3034 } 3035 3036 // Fourth input register 3037 switch (Inst.getOpcode()) { 3038 case ARM::VST4d8: 3039 case ARM::VST4d16: 3040 case ARM::VST4d32: 3041 case ARM::VST4d8_UPD: 3042 case ARM::VST4d16_UPD: 3043 case ARM::VST4d32_UPD: 3044 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3045 return MCDisassembler::Fail; 3046 break; 3047 case ARM::VST4q8: 3048 case ARM::VST4q16: 3049 case ARM::VST4q32: 3050 case ARM::VST4q8_UPD: 3051 case ARM::VST4q16_UPD: 3052 case ARM::VST4q32_UPD: 3053 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3054 return MCDisassembler::Fail; 3055 break; 3056 default: 3057 break; 3058 } 3059 3060 return S; 3061 } 3062 3063 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3064 uint64_t Address, const void *Decoder) { 3065 DecodeStatus S = MCDisassembler::Success; 3066 3067 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3068 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3069 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3070 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3071 unsigned align = fieldFromInstruction(Insn, 4, 1); 3072 unsigned size = fieldFromInstruction(Insn, 6, 2); 3073 3074 if (size == 0 && align == 1) 3075 return MCDisassembler::Fail; 3076 align *= (1 << size); 3077 3078 switch (Inst.getOpcode()) { 3079 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3080 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3081 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3082 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3083 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3084 return MCDisassembler::Fail; 3085 break; 3086 default: 3087 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 break; 3090 } 3091 if (Rm != 0xF) { 3092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3093 return MCDisassembler::Fail; 3094 } 3095 3096 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3097 return MCDisassembler::Fail; 3098 Inst.addOperand(MCOperand::createImm(align)); 3099 3100 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3101 // variant encodes Rm == 0xf. Anything else is a register offset post- 3102 // increment and we need to add the register operand to the instruction. 3103 if (Rm != 0xD && Rm != 0xF && 3104 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3105 return MCDisassembler::Fail; 3106 3107 return S; 3108 } 3109 3110 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3111 uint64_t Address, const void *Decoder) { 3112 DecodeStatus S = MCDisassembler::Success; 3113 3114 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3115 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3116 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3117 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3118 unsigned align = fieldFromInstruction(Insn, 4, 1); 3119 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3120 align *= 2*size; 3121 3122 switch (Inst.getOpcode()) { 3123 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3124 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3125 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3126 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3127 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3128 return MCDisassembler::Fail; 3129 break; 3130 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3131 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3132 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3133 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3134 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3135 return MCDisassembler::Fail; 3136 break; 3137 default: 3138 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3139 return MCDisassembler::Fail; 3140 break; 3141 } 3142 3143 if (Rm != 0xF) 3144 Inst.addOperand(MCOperand::createImm(0)); 3145 3146 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3147 return MCDisassembler::Fail; 3148 Inst.addOperand(MCOperand::createImm(align)); 3149 3150 if (Rm != 0xD && Rm != 0xF) { 3151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3152 return MCDisassembler::Fail; 3153 } 3154 3155 return S; 3156 } 3157 3158 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3159 uint64_t Address, const void *Decoder) { 3160 DecodeStatus S = MCDisassembler::Success; 3161 3162 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3163 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3164 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3165 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3166 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3167 3168 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3169 return MCDisassembler::Fail; 3170 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3171 return MCDisassembler::Fail; 3172 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3173 return MCDisassembler::Fail; 3174 if (Rm != 0xF) { 3175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3176 return MCDisassembler::Fail; 3177 } 3178 3179 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3180 return MCDisassembler::Fail; 3181 Inst.addOperand(MCOperand::createImm(0)); 3182 3183 if (Rm == 0xD) 3184 Inst.addOperand(MCOperand::createReg(0)); 3185 else if (Rm != 0xF) { 3186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 } 3189 3190 return S; 3191 } 3192 3193 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3194 uint64_t Address, const void *Decoder) { 3195 DecodeStatus S = MCDisassembler::Success; 3196 3197 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3198 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3199 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3200 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3201 unsigned size = fieldFromInstruction(Insn, 6, 2); 3202 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3203 unsigned align = fieldFromInstruction(Insn, 4, 1); 3204 3205 if (size == 0x3) { 3206 if (align == 0) 3207 return MCDisassembler::Fail; 3208 align = 16; 3209 } else { 3210 if (size == 2) { 3211 align *= 8; 3212 } else { 3213 size = 1 << size; 3214 align *= 4*size; 3215 } 3216 } 3217 3218 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3219 return MCDisassembler::Fail; 3220 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3221 return MCDisassembler::Fail; 3222 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3223 return MCDisassembler::Fail; 3224 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3225 return MCDisassembler::Fail; 3226 if (Rm != 0xF) { 3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 } 3230 3231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3232 return MCDisassembler::Fail; 3233 Inst.addOperand(MCOperand::createImm(align)); 3234 3235 if (Rm == 0xD) 3236 Inst.addOperand(MCOperand::createReg(0)); 3237 else if (Rm != 0xF) { 3238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3239 return MCDisassembler::Fail; 3240 } 3241 3242 return S; 3243 } 3244 3245 static DecodeStatus 3246 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3247 uint64_t Address, const void *Decoder) { 3248 DecodeStatus S = MCDisassembler::Success; 3249 3250 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3251 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3252 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3253 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3254 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3255 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3256 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3257 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3258 3259 if (Q) { 3260 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3261 return MCDisassembler::Fail; 3262 } else { 3263 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3264 return MCDisassembler::Fail; 3265 } 3266 3267 Inst.addOperand(MCOperand::createImm(imm)); 3268 3269 switch (Inst.getOpcode()) { 3270 case ARM::VORRiv4i16: 3271 case ARM::VORRiv2i32: 3272 case ARM::VBICiv4i16: 3273 case ARM::VBICiv2i32: 3274 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3275 return MCDisassembler::Fail; 3276 break; 3277 case ARM::VORRiv8i16: 3278 case ARM::VORRiv4i32: 3279 case ARM::VBICiv8i16: 3280 case ARM::VBICiv4i32: 3281 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3282 return MCDisassembler::Fail; 3283 break; 3284 default: 3285 break; 3286 } 3287 3288 return S; 3289 } 3290 3291 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3292 uint64_t Address, const void *Decoder) { 3293 DecodeStatus S = MCDisassembler::Success; 3294 3295 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3296 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3297 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3298 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3299 unsigned size = fieldFromInstruction(Insn, 18, 2); 3300 3301 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3302 return MCDisassembler::Fail; 3303 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3304 return MCDisassembler::Fail; 3305 Inst.addOperand(MCOperand::createImm(8 << size)); 3306 3307 return S; 3308 } 3309 3310 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3311 uint64_t Address, const void *Decoder) { 3312 Inst.addOperand(MCOperand::createImm(8 - Val)); 3313 return MCDisassembler::Success; 3314 } 3315 3316 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3317 uint64_t Address, const void *Decoder) { 3318 Inst.addOperand(MCOperand::createImm(16 - Val)); 3319 return MCDisassembler::Success; 3320 } 3321 3322 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3323 uint64_t Address, const void *Decoder) { 3324 Inst.addOperand(MCOperand::createImm(32 - Val)); 3325 return MCDisassembler::Success; 3326 } 3327 3328 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3329 uint64_t Address, const void *Decoder) { 3330 Inst.addOperand(MCOperand::createImm(64 - Val)); 3331 return MCDisassembler::Success; 3332 } 3333 3334 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3335 uint64_t Address, const void *Decoder) { 3336 DecodeStatus S = MCDisassembler::Success; 3337 3338 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3339 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3340 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3341 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3342 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3343 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3344 unsigned op = fieldFromInstruction(Insn, 6, 1); 3345 3346 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3347 return MCDisassembler::Fail; 3348 if (op) { 3349 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3350 return MCDisassembler::Fail; // Writeback 3351 } 3352 3353 switch (Inst.getOpcode()) { 3354 case ARM::VTBL2: 3355 case ARM::VTBX2: 3356 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3357 return MCDisassembler::Fail; 3358 break; 3359 default: 3360 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3361 return MCDisassembler::Fail; 3362 } 3363 3364 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3365 return MCDisassembler::Fail; 3366 3367 return S; 3368 } 3369 3370 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3371 uint64_t Address, const void *Decoder) { 3372 DecodeStatus S = MCDisassembler::Success; 3373 3374 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3375 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3376 3377 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3378 return MCDisassembler::Fail; 3379 3380 switch(Inst.getOpcode()) { 3381 default: 3382 return MCDisassembler::Fail; 3383 case ARM::tADR: 3384 break; // tADR does not explicitly represent the PC as an operand. 3385 case ARM::tADDrSPi: 3386 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3387 break; 3388 } 3389 3390 Inst.addOperand(MCOperand::createImm(imm)); 3391 return S; 3392 } 3393 3394 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3395 uint64_t Address, const void *Decoder) { 3396 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3397 true, 2, Inst, Decoder)) 3398 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3399 return MCDisassembler::Success; 3400 } 3401 3402 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3403 uint64_t Address, const void *Decoder) { 3404 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3405 true, 4, Inst, Decoder)) 3406 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3407 return MCDisassembler::Success; 3408 } 3409 3410 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3411 uint64_t Address, const void *Decoder) { 3412 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3413 true, 2, Inst, Decoder)) 3414 Inst.addOperand(MCOperand::createImm(Val << 1)); 3415 return MCDisassembler::Success; 3416 } 3417 3418 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3419 uint64_t Address, const void *Decoder) { 3420 DecodeStatus S = MCDisassembler::Success; 3421 3422 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3423 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3424 3425 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3426 return MCDisassembler::Fail; 3427 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3428 return MCDisassembler::Fail; 3429 3430 return S; 3431 } 3432 3433 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3434 uint64_t Address, const void *Decoder) { 3435 DecodeStatus S = MCDisassembler::Success; 3436 3437 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3438 unsigned imm = fieldFromInstruction(Val, 3, 5); 3439 3440 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3441 return MCDisassembler::Fail; 3442 Inst.addOperand(MCOperand::createImm(imm)); 3443 3444 return S; 3445 } 3446 3447 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3448 uint64_t Address, const void *Decoder) { 3449 unsigned imm = Val << 2; 3450 3451 Inst.addOperand(MCOperand::createImm(imm)); 3452 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3453 3454 return MCDisassembler::Success; 3455 } 3456 3457 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3458 uint64_t Address, const void *Decoder) { 3459 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3460 Inst.addOperand(MCOperand::createImm(Val)); 3461 3462 return MCDisassembler::Success; 3463 } 3464 3465 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3466 uint64_t Address, const void *Decoder) { 3467 DecodeStatus S = MCDisassembler::Success; 3468 3469 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3470 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3471 unsigned imm = fieldFromInstruction(Val, 0, 2); 3472 3473 // Thumb stores cannot use PC as dest register. 3474 switch (Inst.getOpcode()) { 3475 case ARM::t2STRHs: 3476 case ARM::t2STRBs: 3477 case ARM::t2STRs: 3478 if (Rn == 15) 3479 return MCDisassembler::Fail; 3480 break; 3481 default: 3482 break; 3483 } 3484 3485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3486 return MCDisassembler::Fail; 3487 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3488 return MCDisassembler::Fail; 3489 Inst.addOperand(MCOperand::createImm(imm)); 3490 3491 return S; 3492 } 3493 3494 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3495 uint64_t Address, const void *Decoder) { 3496 DecodeStatus S = MCDisassembler::Success; 3497 3498 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3499 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3500 3501 const FeatureBitset &featureBits = 3502 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3503 3504 bool hasMP = featureBits[ARM::FeatureMP]; 3505 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3506 3507 if (Rn == 15) { 3508 switch (Inst.getOpcode()) { 3509 case ARM::t2LDRBs: 3510 Inst.setOpcode(ARM::t2LDRBpci); 3511 break; 3512 case ARM::t2LDRHs: 3513 Inst.setOpcode(ARM::t2LDRHpci); 3514 break; 3515 case ARM::t2LDRSHs: 3516 Inst.setOpcode(ARM::t2LDRSHpci); 3517 break; 3518 case ARM::t2LDRSBs: 3519 Inst.setOpcode(ARM::t2LDRSBpci); 3520 break; 3521 case ARM::t2LDRs: 3522 Inst.setOpcode(ARM::t2LDRpci); 3523 break; 3524 case ARM::t2PLDs: 3525 Inst.setOpcode(ARM::t2PLDpci); 3526 break; 3527 case ARM::t2PLIs: 3528 Inst.setOpcode(ARM::t2PLIpci); 3529 break; 3530 default: 3531 return MCDisassembler::Fail; 3532 } 3533 3534 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3535 } 3536 3537 if (Rt == 15) { 3538 switch (Inst.getOpcode()) { 3539 case ARM::t2LDRSHs: 3540 return MCDisassembler::Fail; 3541 case ARM::t2LDRHs: 3542 Inst.setOpcode(ARM::t2PLDWs); 3543 break; 3544 case ARM::t2LDRSBs: 3545 Inst.setOpcode(ARM::t2PLIs); 3546 break; 3547 default: 3548 break; 3549 } 3550 } 3551 3552 switch (Inst.getOpcode()) { 3553 case ARM::t2PLDs: 3554 break; 3555 case ARM::t2PLIs: 3556 if (!hasV7Ops) 3557 return MCDisassembler::Fail; 3558 break; 3559 case ARM::t2PLDWs: 3560 if (!hasV7Ops || !hasMP) 3561 return MCDisassembler::Fail; 3562 break; 3563 default: 3564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3565 return MCDisassembler::Fail; 3566 } 3567 3568 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3569 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3570 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3571 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3572 return MCDisassembler::Fail; 3573 3574 return S; 3575 } 3576 3577 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3578 uint64_t Address, const void* Decoder) { 3579 DecodeStatus S = MCDisassembler::Success; 3580 3581 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3582 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3583 unsigned U = fieldFromInstruction(Insn, 9, 1); 3584 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3585 imm |= (U << 8); 3586 imm |= (Rn << 9); 3587 unsigned add = fieldFromInstruction(Insn, 9, 1); 3588 3589 const FeatureBitset &featureBits = 3590 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3591 3592 bool hasMP = featureBits[ARM::FeatureMP]; 3593 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3594 3595 if (Rn == 15) { 3596 switch (Inst.getOpcode()) { 3597 case ARM::t2LDRi8: 3598 Inst.setOpcode(ARM::t2LDRpci); 3599 break; 3600 case ARM::t2LDRBi8: 3601 Inst.setOpcode(ARM::t2LDRBpci); 3602 break; 3603 case ARM::t2LDRSBi8: 3604 Inst.setOpcode(ARM::t2LDRSBpci); 3605 break; 3606 case ARM::t2LDRHi8: 3607 Inst.setOpcode(ARM::t2LDRHpci); 3608 break; 3609 case ARM::t2LDRSHi8: 3610 Inst.setOpcode(ARM::t2LDRSHpci); 3611 break; 3612 case ARM::t2PLDi8: 3613 Inst.setOpcode(ARM::t2PLDpci); 3614 break; 3615 case ARM::t2PLIi8: 3616 Inst.setOpcode(ARM::t2PLIpci); 3617 break; 3618 default: 3619 return MCDisassembler::Fail; 3620 } 3621 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3622 } 3623 3624 if (Rt == 15) { 3625 switch (Inst.getOpcode()) { 3626 case ARM::t2LDRSHi8: 3627 return MCDisassembler::Fail; 3628 case ARM::t2LDRHi8: 3629 if (!add) 3630 Inst.setOpcode(ARM::t2PLDWi8); 3631 break; 3632 case ARM::t2LDRSBi8: 3633 Inst.setOpcode(ARM::t2PLIi8); 3634 break; 3635 default: 3636 break; 3637 } 3638 } 3639 3640 switch (Inst.getOpcode()) { 3641 case ARM::t2PLDi8: 3642 break; 3643 case ARM::t2PLIi8: 3644 if (!hasV7Ops) 3645 return MCDisassembler::Fail; 3646 break; 3647 case ARM::t2PLDWi8: 3648 if (!hasV7Ops || !hasMP) 3649 return MCDisassembler::Fail; 3650 break; 3651 default: 3652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3653 return MCDisassembler::Fail; 3654 } 3655 3656 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3657 return MCDisassembler::Fail; 3658 return S; 3659 } 3660 3661 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3662 uint64_t Address, const void* Decoder) { 3663 DecodeStatus S = MCDisassembler::Success; 3664 3665 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3666 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3667 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3668 imm |= (Rn << 13); 3669 3670 const FeatureBitset &featureBits = 3671 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3672 3673 bool hasMP = featureBits[ARM::FeatureMP]; 3674 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3675 3676 if (Rn == 15) { 3677 switch (Inst.getOpcode()) { 3678 case ARM::t2LDRi12: 3679 Inst.setOpcode(ARM::t2LDRpci); 3680 break; 3681 case ARM::t2LDRHi12: 3682 Inst.setOpcode(ARM::t2LDRHpci); 3683 break; 3684 case ARM::t2LDRSHi12: 3685 Inst.setOpcode(ARM::t2LDRSHpci); 3686 break; 3687 case ARM::t2LDRBi12: 3688 Inst.setOpcode(ARM::t2LDRBpci); 3689 break; 3690 case ARM::t2LDRSBi12: 3691 Inst.setOpcode(ARM::t2LDRSBpci); 3692 break; 3693 case ARM::t2PLDi12: 3694 Inst.setOpcode(ARM::t2PLDpci); 3695 break; 3696 case ARM::t2PLIi12: 3697 Inst.setOpcode(ARM::t2PLIpci); 3698 break; 3699 default: 3700 return MCDisassembler::Fail; 3701 } 3702 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3703 } 3704 3705 if (Rt == 15) { 3706 switch (Inst.getOpcode()) { 3707 case ARM::t2LDRSHi12: 3708 return MCDisassembler::Fail; 3709 case ARM::t2LDRHi12: 3710 Inst.setOpcode(ARM::t2PLDWi12); 3711 break; 3712 case ARM::t2LDRSBi12: 3713 Inst.setOpcode(ARM::t2PLIi12); 3714 break; 3715 default: 3716 break; 3717 } 3718 } 3719 3720 switch (Inst.getOpcode()) { 3721 case ARM::t2PLDi12: 3722 break; 3723 case ARM::t2PLIi12: 3724 if (!hasV7Ops) 3725 return MCDisassembler::Fail; 3726 break; 3727 case ARM::t2PLDWi12: 3728 if (!hasV7Ops || !hasMP) 3729 return MCDisassembler::Fail; 3730 break; 3731 default: 3732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3733 return MCDisassembler::Fail; 3734 } 3735 3736 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3737 return MCDisassembler::Fail; 3738 return S; 3739 } 3740 3741 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3742 uint64_t Address, const void* Decoder) { 3743 DecodeStatus S = MCDisassembler::Success; 3744 3745 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3746 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3747 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3748 imm |= (Rn << 9); 3749 3750 if (Rn == 15) { 3751 switch (Inst.getOpcode()) { 3752 case ARM::t2LDRT: 3753 Inst.setOpcode(ARM::t2LDRpci); 3754 break; 3755 case ARM::t2LDRBT: 3756 Inst.setOpcode(ARM::t2LDRBpci); 3757 break; 3758 case ARM::t2LDRHT: 3759 Inst.setOpcode(ARM::t2LDRHpci); 3760 break; 3761 case ARM::t2LDRSBT: 3762 Inst.setOpcode(ARM::t2LDRSBpci); 3763 break; 3764 case ARM::t2LDRSHT: 3765 Inst.setOpcode(ARM::t2LDRSHpci); 3766 break; 3767 default: 3768 return MCDisassembler::Fail; 3769 } 3770 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3771 } 3772 3773 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3774 return MCDisassembler::Fail; 3775 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3776 return MCDisassembler::Fail; 3777 return S; 3778 } 3779 3780 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3781 uint64_t Address, const void* Decoder) { 3782 DecodeStatus S = MCDisassembler::Success; 3783 3784 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3785 unsigned U = fieldFromInstruction(Insn, 23, 1); 3786 int imm = fieldFromInstruction(Insn, 0, 12); 3787 3788 const FeatureBitset &featureBits = 3789 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3790 3791 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3792 3793 if (Rt == 15) { 3794 switch (Inst.getOpcode()) { 3795 case ARM::t2LDRBpci: 3796 case ARM::t2LDRHpci: 3797 Inst.setOpcode(ARM::t2PLDpci); 3798 break; 3799 case ARM::t2LDRSBpci: 3800 Inst.setOpcode(ARM::t2PLIpci); 3801 break; 3802 case ARM::t2LDRSHpci: 3803 return MCDisassembler::Fail; 3804 default: 3805 break; 3806 } 3807 } 3808 3809 switch(Inst.getOpcode()) { 3810 case ARM::t2PLDpci: 3811 break; 3812 case ARM::t2PLIpci: 3813 if (!hasV7Ops) 3814 return MCDisassembler::Fail; 3815 break; 3816 default: 3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3818 return MCDisassembler::Fail; 3819 } 3820 3821 if (!U) { 3822 // Special case for #-0. 3823 if (imm == 0) 3824 imm = INT32_MIN; 3825 else 3826 imm = -imm; 3827 } 3828 Inst.addOperand(MCOperand::createImm(imm)); 3829 3830 return S; 3831 } 3832 3833 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3834 uint64_t Address, const void *Decoder) { 3835 if (Val == 0) 3836 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3837 else { 3838 int imm = Val & 0xFF; 3839 3840 if (!(Val & 0x100)) imm *= -1; 3841 Inst.addOperand(MCOperand::createImm(imm * 4)); 3842 } 3843 3844 return MCDisassembler::Success; 3845 } 3846 3847 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 3848 const void *Decoder) { 3849 if (Val == 0) 3850 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3851 else { 3852 int imm = Val & 0x7F; 3853 3854 if (!(Val & 0x80)) 3855 imm *= -1; 3856 Inst.addOperand(MCOperand::createImm(imm * 4)); 3857 } 3858 3859 return MCDisassembler::Success; 3860 } 3861 3862 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3863 uint64_t Address, const void *Decoder) { 3864 DecodeStatus S = MCDisassembler::Success; 3865 3866 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3867 unsigned imm = fieldFromInstruction(Val, 0, 9); 3868 3869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3870 return MCDisassembler::Fail; 3871 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 3874 return S; 3875 } 3876 3877 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 3878 uint64_t Address, 3879 const void *Decoder) { 3880 DecodeStatus S = MCDisassembler::Success; 3881 3882 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3883 unsigned imm = fieldFromInstruction(Val, 0, 8); 3884 3885 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3886 return MCDisassembler::Fail; 3887 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 3888 return MCDisassembler::Fail; 3889 3890 return S; 3891 } 3892 3893 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3894 uint64_t Address, const void *Decoder) { 3895 DecodeStatus S = MCDisassembler::Success; 3896 3897 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3898 unsigned imm = fieldFromInstruction(Val, 0, 8); 3899 3900 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3901 return MCDisassembler::Fail; 3902 3903 Inst.addOperand(MCOperand::createImm(imm)); 3904 3905 return S; 3906 } 3907 3908 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3909 uint64_t Address, const void *Decoder) { 3910 int imm = Val & 0xFF; 3911 if (Val == 0) 3912 imm = INT32_MIN; 3913 else if (!(Val & 0x100)) 3914 imm *= -1; 3915 Inst.addOperand(MCOperand::createImm(imm)); 3916 3917 return MCDisassembler::Success; 3918 } 3919 3920 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3921 uint64_t Address, const void *Decoder) { 3922 DecodeStatus S = MCDisassembler::Success; 3923 3924 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3925 unsigned imm = fieldFromInstruction(Val, 0, 9); 3926 3927 // Thumb stores cannot use PC as dest register. 3928 switch (Inst.getOpcode()) { 3929 case ARM::t2STRT: 3930 case ARM::t2STRBT: 3931 case ARM::t2STRHT: 3932 case ARM::t2STRi8: 3933 case ARM::t2STRHi8: 3934 case ARM::t2STRBi8: 3935 if (Rn == 15) 3936 return MCDisassembler::Fail; 3937 break; 3938 default: 3939 break; 3940 } 3941 3942 // Some instructions always use an additive offset. 3943 switch (Inst.getOpcode()) { 3944 case ARM::t2LDRT: 3945 case ARM::t2LDRBT: 3946 case ARM::t2LDRHT: 3947 case ARM::t2LDRSBT: 3948 case ARM::t2LDRSHT: 3949 case ARM::t2STRT: 3950 case ARM::t2STRBT: 3951 case ARM::t2STRHT: 3952 imm |= 0x100; 3953 break; 3954 default: 3955 break; 3956 } 3957 3958 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3959 return MCDisassembler::Fail; 3960 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3961 return MCDisassembler::Fail; 3962 3963 return S; 3964 } 3965 3966 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3967 uint64_t Address, const void *Decoder) { 3968 DecodeStatus S = MCDisassembler::Success; 3969 3970 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3971 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3972 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3973 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3974 addr |= Rn << 9; 3975 unsigned load = fieldFromInstruction(Insn, 20, 1); 3976 3977 if (Rn == 15) { 3978 switch (Inst.getOpcode()) { 3979 case ARM::t2LDR_PRE: 3980 case ARM::t2LDR_POST: 3981 Inst.setOpcode(ARM::t2LDRpci); 3982 break; 3983 case ARM::t2LDRB_PRE: 3984 case ARM::t2LDRB_POST: 3985 Inst.setOpcode(ARM::t2LDRBpci); 3986 break; 3987 case ARM::t2LDRH_PRE: 3988 case ARM::t2LDRH_POST: 3989 Inst.setOpcode(ARM::t2LDRHpci); 3990 break; 3991 case ARM::t2LDRSB_PRE: 3992 case ARM::t2LDRSB_POST: 3993 if (Rt == 15) 3994 Inst.setOpcode(ARM::t2PLIpci); 3995 else 3996 Inst.setOpcode(ARM::t2LDRSBpci); 3997 break; 3998 case ARM::t2LDRSH_PRE: 3999 case ARM::t2LDRSH_POST: 4000 Inst.setOpcode(ARM::t2LDRSHpci); 4001 break; 4002 default: 4003 return MCDisassembler::Fail; 4004 } 4005 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4006 } 4007 4008 if (!load) { 4009 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4010 return MCDisassembler::Fail; 4011 } 4012 4013 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4014 return MCDisassembler::Fail; 4015 4016 if (load) { 4017 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4018 return MCDisassembler::Fail; 4019 } 4020 4021 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4022 return MCDisassembler::Fail; 4023 4024 return S; 4025 } 4026 4027 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4028 uint64_t Address, const void *Decoder) { 4029 DecodeStatus S = MCDisassembler::Success; 4030 4031 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4032 unsigned imm = fieldFromInstruction(Val, 0, 12); 4033 4034 // Thumb stores cannot use PC as dest register. 4035 switch (Inst.getOpcode()) { 4036 case ARM::t2STRi12: 4037 case ARM::t2STRBi12: 4038 case ARM::t2STRHi12: 4039 if (Rn == 15) 4040 return MCDisassembler::Fail; 4041 break; 4042 default: 4043 break; 4044 } 4045 4046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4047 return MCDisassembler::Fail; 4048 Inst.addOperand(MCOperand::createImm(imm)); 4049 4050 return S; 4051 } 4052 4053 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4054 uint64_t Address, const void *Decoder) { 4055 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4056 4057 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4058 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4059 Inst.addOperand(MCOperand::createImm(imm)); 4060 4061 return MCDisassembler::Success; 4062 } 4063 4064 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4065 uint64_t Address, const void *Decoder) { 4066 DecodeStatus S = MCDisassembler::Success; 4067 4068 if (Inst.getOpcode() == ARM::tADDrSP) { 4069 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4070 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4071 4072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4073 return MCDisassembler::Fail; 4074 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4076 return MCDisassembler::Fail; 4077 } else if (Inst.getOpcode() == ARM::tADDspr) { 4078 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4079 4080 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4081 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4083 return MCDisassembler::Fail; 4084 } 4085 4086 return S; 4087 } 4088 4089 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4090 uint64_t Address, const void *Decoder) { 4091 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4092 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4093 4094 Inst.addOperand(MCOperand::createImm(imod)); 4095 Inst.addOperand(MCOperand::createImm(flags)); 4096 4097 return MCDisassembler::Success; 4098 } 4099 4100 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4101 uint64_t Address, const void *Decoder) { 4102 DecodeStatus S = MCDisassembler::Success; 4103 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4104 unsigned add = fieldFromInstruction(Insn, 4, 1); 4105 4106 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4107 return MCDisassembler::Fail; 4108 Inst.addOperand(MCOperand::createImm(add)); 4109 4110 return S; 4111 } 4112 4113 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4114 uint64_t Address, const void *Decoder) { 4115 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4116 // Note only one trailing zero not two. Also the J1 and J2 values are from 4117 // the encoded instruction. So here change to I1 and I2 values via: 4118 // I1 = NOT(J1 EOR S); 4119 // I2 = NOT(J2 EOR S); 4120 // and build the imm32 with two trailing zeros as documented: 4121 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4122 unsigned S = (Val >> 23) & 1; 4123 unsigned J1 = (Val >> 22) & 1; 4124 unsigned J2 = (Val >> 21) & 1; 4125 unsigned I1 = !(J1 ^ S); 4126 unsigned I2 = !(J2 ^ S); 4127 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4128 int imm32 = SignExtend32<25>(tmp << 1); 4129 4130 if (!tryAddingSymbolicOperand(Address, 4131 (Address & ~2u) + imm32 + 4, 4132 true, 4, Inst, Decoder)) 4133 Inst.addOperand(MCOperand::createImm(imm32)); 4134 return MCDisassembler::Success; 4135 } 4136 4137 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4138 uint64_t Address, const void *Decoder) { 4139 if (Val == 0xA || Val == 0xB) 4140 return MCDisassembler::Fail; 4141 4142 const FeatureBitset &featureBits = 4143 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4144 4145 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4146 return MCDisassembler::Fail; 4147 4148 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should 4149 // decode as VFP/MVE instructions. 4150 if (featureBits[ARM::HasV8_1MMainlineOps] && 4151 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || 4152 (Val & 0xE) == 0xE)) 4153 return MCDisassembler::Fail; 4154 4155 Inst.addOperand(MCOperand::createImm(Val)); 4156 return MCDisassembler::Success; 4157 } 4158 4159 static DecodeStatus 4160 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4161 uint64_t Address, const void *Decoder) { 4162 DecodeStatus S = MCDisassembler::Success; 4163 4164 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4165 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4166 4167 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4169 return MCDisassembler::Fail; 4170 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4171 return MCDisassembler::Fail; 4172 return S; 4173 } 4174 4175 static DecodeStatus 4176 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4177 uint64_t Address, const void *Decoder) { 4178 DecodeStatus S = MCDisassembler::Success; 4179 4180 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4181 if (pred == 0xE || pred == 0xF) { 4182 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4183 switch (opc) { 4184 default: 4185 return MCDisassembler::Fail; 4186 case 0xf3bf8f4: 4187 Inst.setOpcode(ARM::t2DSB); 4188 break; 4189 case 0xf3bf8f5: 4190 Inst.setOpcode(ARM::t2DMB); 4191 break; 4192 case 0xf3bf8f6: 4193 Inst.setOpcode(ARM::t2ISB); 4194 break; 4195 } 4196 4197 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4198 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4199 } 4200 4201 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4202 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4203 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4204 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4205 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4206 4207 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4208 return MCDisassembler::Fail; 4209 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4210 return MCDisassembler::Fail; 4211 4212 return S; 4213 } 4214 4215 // Decode a shifted immediate operand. These basically consist 4216 // of an 8-bit value, and a 4-bit directive that specifies either 4217 // a splat operation or a rotation. 4218 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4219 uint64_t Address, const void *Decoder) { 4220 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4221 if (ctrl == 0) { 4222 unsigned byte = fieldFromInstruction(Val, 8, 2); 4223 unsigned imm = fieldFromInstruction(Val, 0, 8); 4224 switch (byte) { 4225 case 0: 4226 Inst.addOperand(MCOperand::createImm(imm)); 4227 break; 4228 case 1: 4229 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4230 break; 4231 case 2: 4232 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4233 break; 4234 case 3: 4235 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4236 (imm << 8) | imm)); 4237 break; 4238 } 4239 } else { 4240 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4241 unsigned rot = fieldFromInstruction(Val, 7, 5); 4242 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4243 Inst.addOperand(MCOperand::createImm(imm)); 4244 } 4245 4246 return MCDisassembler::Success; 4247 } 4248 4249 static DecodeStatus 4250 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4251 uint64_t Address, const void *Decoder) { 4252 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4253 true, 2, Inst, Decoder)) 4254 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4255 return MCDisassembler::Success; 4256 } 4257 4258 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4259 uint64_t Address, 4260 const void *Decoder) { 4261 // Val is passed in as S:J1:J2:imm10:imm11 4262 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4263 // the encoded instruction. So here change to I1 and I2 values via: 4264 // I1 = NOT(J1 EOR S); 4265 // I2 = NOT(J2 EOR S); 4266 // and build the imm32 with one trailing zero as documented: 4267 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4268 unsigned S = (Val >> 23) & 1; 4269 unsigned J1 = (Val >> 22) & 1; 4270 unsigned J2 = (Val >> 21) & 1; 4271 unsigned I1 = !(J1 ^ S); 4272 unsigned I2 = !(J2 ^ S); 4273 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4274 int imm32 = SignExtend32<25>(tmp << 1); 4275 4276 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4277 true, 4, Inst, Decoder)) 4278 Inst.addOperand(MCOperand::createImm(imm32)); 4279 return MCDisassembler::Success; 4280 } 4281 4282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4283 uint64_t Address, const void *Decoder) { 4284 if (Val & ~0xf) 4285 return MCDisassembler::Fail; 4286 4287 Inst.addOperand(MCOperand::createImm(Val)); 4288 return MCDisassembler::Success; 4289 } 4290 4291 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4292 uint64_t Address, const void *Decoder) { 4293 if (Val & ~0xf) 4294 return MCDisassembler::Fail; 4295 4296 Inst.addOperand(MCOperand::createImm(Val)); 4297 return MCDisassembler::Success; 4298 } 4299 4300 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4301 uint64_t Address, const void *Decoder) { 4302 DecodeStatus S = MCDisassembler::Success; 4303 const FeatureBitset &FeatureBits = 4304 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4305 4306 if (FeatureBits[ARM::FeatureMClass]) { 4307 unsigned ValLow = Val & 0xff; 4308 4309 // Validate the SYSm value first. 4310 switch (ValLow) { 4311 case 0: // apsr 4312 case 1: // iapsr 4313 case 2: // eapsr 4314 case 3: // xpsr 4315 case 5: // ipsr 4316 case 6: // epsr 4317 case 7: // iepsr 4318 case 8: // msp 4319 case 9: // psp 4320 case 16: // primask 4321 case 20: // control 4322 break; 4323 case 17: // basepri 4324 case 18: // basepri_max 4325 case 19: // faultmask 4326 if (!(FeatureBits[ARM::HasV7Ops])) 4327 // Values basepri, basepri_max and faultmask are only valid for v7m. 4328 return MCDisassembler::Fail; 4329 break; 4330 case 0x8a: // msplim_ns 4331 case 0x8b: // psplim_ns 4332 case 0x91: // basepri_ns 4333 case 0x93: // faultmask_ns 4334 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4335 return MCDisassembler::Fail; 4336 LLVM_FALLTHROUGH; 4337 case 10: // msplim 4338 case 11: // psplim 4339 case 0x88: // msp_ns 4340 case 0x89: // psp_ns 4341 case 0x90: // primask_ns 4342 case 0x94: // control_ns 4343 case 0x98: // sp_ns 4344 if (!(FeatureBits[ARM::Feature8MSecExt])) 4345 return MCDisassembler::Fail; 4346 break; 4347 default: 4348 // Architecturally defined as unpredictable 4349 S = MCDisassembler::SoftFail; 4350 break; 4351 } 4352 4353 if (Inst.getOpcode() == ARM::t2MSR_M) { 4354 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4355 if (!(FeatureBits[ARM::HasV7Ops])) { 4356 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4357 // unpredictable. 4358 if (Mask != 2) 4359 S = MCDisassembler::SoftFail; 4360 } 4361 else { 4362 // The ARMv7-M architecture stores an additional 2-bit mask value in 4363 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4364 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4365 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4366 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4367 // only if the processor includes the DSP extension. 4368 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4369 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4370 S = MCDisassembler::SoftFail; 4371 } 4372 } 4373 } else { 4374 // A/R class 4375 if (Val == 0) 4376 return MCDisassembler::Fail; 4377 } 4378 Inst.addOperand(MCOperand::createImm(Val)); 4379 return S; 4380 } 4381 4382 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4383 uint64_t Address, const void *Decoder) { 4384 unsigned R = fieldFromInstruction(Val, 5, 1); 4385 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4386 4387 // The table of encodings for these banked registers comes from B9.2.3 of the 4388 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4389 // neater. So by fiat, these values are UNPREDICTABLE: 4390 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4391 return MCDisassembler::Fail; 4392 4393 Inst.addOperand(MCOperand::createImm(Val)); 4394 return MCDisassembler::Success; 4395 } 4396 4397 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4398 uint64_t Address, const void *Decoder) { 4399 DecodeStatus S = MCDisassembler::Success; 4400 4401 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4402 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4403 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4404 4405 if (Rn == 0xF) 4406 S = MCDisassembler::SoftFail; 4407 4408 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4409 return MCDisassembler::Fail; 4410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4411 return MCDisassembler::Fail; 4412 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4413 return MCDisassembler::Fail; 4414 4415 return S; 4416 } 4417 4418 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4419 uint64_t Address, 4420 const void *Decoder) { 4421 DecodeStatus S = MCDisassembler::Success; 4422 4423 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4424 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4425 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4426 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4427 4428 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4429 return MCDisassembler::Fail; 4430 4431 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4432 S = MCDisassembler::SoftFail; 4433 4434 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4435 return MCDisassembler::Fail; 4436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4437 return MCDisassembler::Fail; 4438 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4439 return MCDisassembler::Fail; 4440 4441 return S; 4442 } 4443 4444 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4445 uint64_t Address, const void *Decoder) { 4446 DecodeStatus S = MCDisassembler::Success; 4447 4448 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4449 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4450 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4451 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4452 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4453 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4454 4455 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4456 4457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4458 return MCDisassembler::Fail; 4459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4460 return MCDisassembler::Fail; 4461 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4462 return MCDisassembler::Fail; 4463 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4464 return MCDisassembler::Fail; 4465 4466 return S; 4467 } 4468 4469 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4470 uint64_t Address, const void *Decoder) { 4471 DecodeStatus S = MCDisassembler::Success; 4472 4473 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4474 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4475 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4476 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4477 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4478 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4479 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4480 4481 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4482 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4483 4484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4485 return MCDisassembler::Fail; 4486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4487 return MCDisassembler::Fail; 4488 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4489 return MCDisassembler::Fail; 4490 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4491 return MCDisassembler::Fail; 4492 4493 return S; 4494 } 4495 4496 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4497 uint64_t Address, const void *Decoder) { 4498 DecodeStatus S = MCDisassembler::Success; 4499 4500 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4501 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4502 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4503 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4504 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4505 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4506 4507 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4508 4509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4510 return MCDisassembler::Fail; 4511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4512 return MCDisassembler::Fail; 4513 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4514 return MCDisassembler::Fail; 4515 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4516 return MCDisassembler::Fail; 4517 4518 return S; 4519 } 4520 4521 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4522 uint64_t Address, const void *Decoder) { 4523 DecodeStatus S = MCDisassembler::Success; 4524 4525 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4526 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4527 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4528 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4529 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4530 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4531 4532 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4533 4534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4535 return MCDisassembler::Fail; 4536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4537 return MCDisassembler::Fail; 4538 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4539 return MCDisassembler::Fail; 4540 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4541 return MCDisassembler::Fail; 4542 4543 return S; 4544 } 4545 4546 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4547 uint64_t Address, const void *Decoder) { 4548 DecodeStatus S = MCDisassembler::Success; 4549 4550 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4551 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4552 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4553 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4554 unsigned size = fieldFromInstruction(Insn, 10, 2); 4555 4556 unsigned align = 0; 4557 unsigned index = 0; 4558 switch (size) { 4559 default: 4560 return MCDisassembler::Fail; 4561 case 0: 4562 if (fieldFromInstruction(Insn, 4, 1)) 4563 return MCDisassembler::Fail; // UNDEFINED 4564 index = fieldFromInstruction(Insn, 5, 3); 4565 break; 4566 case 1: 4567 if (fieldFromInstruction(Insn, 5, 1)) 4568 return MCDisassembler::Fail; // UNDEFINED 4569 index = fieldFromInstruction(Insn, 6, 2); 4570 if (fieldFromInstruction(Insn, 4, 1)) 4571 align = 2; 4572 break; 4573 case 2: 4574 if (fieldFromInstruction(Insn, 6, 1)) 4575 return MCDisassembler::Fail; // UNDEFINED 4576 index = fieldFromInstruction(Insn, 7, 1); 4577 4578 switch (fieldFromInstruction(Insn, 4, 2)) { 4579 case 0 : 4580 align = 0; break; 4581 case 3: 4582 align = 4; break; 4583 default: 4584 return MCDisassembler::Fail; 4585 } 4586 break; 4587 } 4588 4589 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4590 return MCDisassembler::Fail; 4591 if (Rm != 0xF) { // Writeback 4592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4593 return MCDisassembler::Fail; 4594 } 4595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4596 return MCDisassembler::Fail; 4597 Inst.addOperand(MCOperand::createImm(align)); 4598 if (Rm != 0xF) { 4599 if (Rm != 0xD) { 4600 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4601 return MCDisassembler::Fail; 4602 } else 4603 Inst.addOperand(MCOperand::createReg(0)); 4604 } 4605 4606 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4607 return MCDisassembler::Fail; 4608 Inst.addOperand(MCOperand::createImm(index)); 4609 4610 return S; 4611 } 4612 4613 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4614 uint64_t Address, const void *Decoder) { 4615 DecodeStatus S = MCDisassembler::Success; 4616 4617 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4618 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4619 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4620 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4621 unsigned size = fieldFromInstruction(Insn, 10, 2); 4622 4623 unsigned align = 0; 4624 unsigned index = 0; 4625 switch (size) { 4626 default: 4627 return MCDisassembler::Fail; 4628 case 0: 4629 if (fieldFromInstruction(Insn, 4, 1)) 4630 return MCDisassembler::Fail; // UNDEFINED 4631 index = fieldFromInstruction(Insn, 5, 3); 4632 break; 4633 case 1: 4634 if (fieldFromInstruction(Insn, 5, 1)) 4635 return MCDisassembler::Fail; // UNDEFINED 4636 index = fieldFromInstruction(Insn, 6, 2); 4637 if (fieldFromInstruction(Insn, 4, 1)) 4638 align = 2; 4639 break; 4640 case 2: 4641 if (fieldFromInstruction(Insn, 6, 1)) 4642 return MCDisassembler::Fail; // UNDEFINED 4643 index = fieldFromInstruction(Insn, 7, 1); 4644 4645 switch (fieldFromInstruction(Insn, 4, 2)) { 4646 case 0: 4647 align = 0; break; 4648 case 3: 4649 align = 4; break; 4650 default: 4651 return MCDisassembler::Fail; 4652 } 4653 break; 4654 } 4655 4656 if (Rm != 0xF) { // Writeback 4657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4658 return MCDisassembler::Fail; 4659 } 4660 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4661 return MCDisassembler::Fail; 4662 Inst.addOperand(MCOperand::createImm(align)); 4663 if (Rm != 0xF) { 4664 if (Rm != 0xD) { 4665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4666 return MCDisassembler::Fail; 4667 } else 4668 Inst.addOperand(MCOperand::createReg(0)); 4669 } 4670 4671 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4672 return MCDisassembler::Fail; 4673 Inst.addOperand(MCOperand::createImm(index)); 4674 4675 return S; 4676 } 4677 4678 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4679 uint64_t Address, const void *Decoder) { 4680 DecodeStatus S = MCDisassembler::Success; 4681 4682 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4683 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4684 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4685 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4686 unsigned size = fieldFromInstruction(Insn, 10, 2); 4687 4688 unsigned align = 0; 4689 unsigned index = 0; 4690 unsigned inc = 1; 4691 switch (size) { 4692 default: 4693 return MCDisassembler::Fail; 4694 case 0: 4695 index = fieldFromInstruction(Insn, 5, 3); 4696 if (fieldFromInstruction(Insn, 4, 1)) 4697 align = 2; 4698 break; 4699 case 1: 4700 index = fieldFromInstruction(Insn, 6, 2); 4701 if (fieldFromInstruction(Insn, 4, 1)) 4702 align = 4; 4703 if (fieldFromInstruction(Insn, 5, 1)) 4704 inc = 2; 4705 break; 4706 case 2: 4707 if (fieldFromInstruction(Insn, 5, 1)) 4708 return MCDisassembler::Fail; // UNDEFINED 4709 index = fieldFromInstruction(Insn, 7, 1); 4710 if (fieldFromInstruction(Insn, 4, 1) != 0) 4711 align = 8; 4712 if (fieldFromInstruction(Insn, 6, 1)) 4713 inc = 2; 4714 break; 4715 } 4716 4717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4718 return MCDisassembler::Fail; 4719 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4720 return MCDisassembler::Fail; 4721 if (Rm != 0xF) { // Writeback 4722 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4723 return MCDisassembler::Fail; 4724 } 4725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4726 return MCDisassembler::Fail; 4727 Inst.addOperand(MCOperand::createImm(align)); 4728 if (Rm != 0xF) { 4729 if (Rm != 0xD) { 4730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4731 return MCDisassembler::Fail; 4732 } else 4733 Inst.addOperand(MCOperand::createReg(0)); 4734 } 4735 4736 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4737 return MCDisassembler::Fail; 4738 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4739 return MCDisassembler::Fail; 4740 Inst.addOperand(MCOperand::createImm(index)); 4741 4742 return S; 4743 } 4744 4745 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4746 uint64_t Address, const void *Decoder) { 4747 DecodeStatus S = MCDisassembler::Success; 4748 4749 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4750 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4751 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4752 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4753 unsigned size = fieldFromInstruction(Insn, 10, 2); 4754 4755 unsigned align = 0; 4756 unsigned index = 0; 4757 unsigned inc = 1; 4758 switch (size) { 4759 default: 4760 return MCDisassembler::Fail; 4761 case 0: 4762 index = fieldFromInstruction(Insn, 5, 3); 4763 if (fieldFromInstruction(Insn, 4, 1)) 4764 align = 2; 4765 break; 4766 case 1: 4767 index = fieldFromInstruction(Insn, 6, 2); 4768 if (fieldFromInstruction(Insn, 4, 1)) 4769 align = 4; 4770 if (fieldFromInstruction(Insn, 5, 1)) 4771 inc = 2; 4772 break; 4773 case 2: 4774 if (fieldFromInstruction(Insn, 5, 1)) 4775 return MCDisassembler::Fail; // UNDEFINED 4776 index = fieldFromInstruction(Insn, 7, 1); 4777 if (fieldFromInstruction(Insn, 4, 1) != 0) 4778 align = 8; 4779 if (fieldFromInstruction(Insn, 6, 1)) 4780 inc = 2; 4781 break; 4782 } 4783 4784 if (Rm != 0xF) { // Writeback 4785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4786 return MCDisassembler::Fail; 4787 } 4788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4789 return MCDisassembler::Fail; 4790 Inst.addOperand(MCOperand::createImm(align)); 4791 if (Rm != 0xF) { 4792 if (Rm != 0xD) { 4793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4794 return MCDisassembler::Fail; 4795 } else 4796 Inst.addOperand(MCOperand::createReg(0)); 4797 } 4798 4799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4800 return MCDisassembler::Fail; 4801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4802 return MCDisassembler::Fail; 4803 Inst.addOperand(MCOperand::createImm(index)); 4804 4805 return S; 4806 } 4807 4808 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4809 uint64_t Address, const void *Decoder) { 4810 DecodeStatus S = MCDisassembler::Success; 4811 4812 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4813 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4814 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4815 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4816 unsigned size = fieldFromInstruction(Insn, 10, 2); 4817 4818 unsigned align = 0; 4819 unsigned index = 0; 4820 unsigned inc = 1; 4821 switch (size) { 4822 default: 4823 return MCDisassembler::Fail; 4824 case 0: 4825 if (fieldFromInstruction(Insn, 4, 1)) 4826 return MCDisassembler::Fail; // UNDEFINED 4827 index = fieldFromInstruction(Insn, 5, 3); 4828 break; 4829 case 1: 4830 if (fieldFromInstruction(Insn, 4, 1)) 4831 return MCDisassembler::Fail; // UNDEFINED 4832 index = fieldFromInstruction(Insn, 6, 2); 4833 if (fieldFromInstruction(Insn, 5, 1)) 4834 inc = 2; 4835 break; 4836 case 2: 4837 if (fieldFromInstruction(Insn, 4, 2)) 4838 return MCDisassembler::Fail; // UNDEFINED 4839 index = fieldFromInstruction(Insn, 7, 1); 4840 if (fieldFromInstruction(Insn, 6, 1)) 4841 inc = 2; 4842 break; 4843 } 4844 4845 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4846 return MCDisassembler::Fail; 4847 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4848 return MCDisassembler::Fail; 4849 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4850 return MCDisassembler::Fail; 4851 4852 if (Rm != 0xF) { // Writeback 4853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4854 return MCDisassembler::Fail; 4855 } 4856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4857 return MCDisassembler::Fail; 4858 Inst.addOperand(MCOperand::createImm(align)); 4859 if (Rm != 0xF) { 4860 if (Rm != 0xD) { 4861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4862 return MCDisassembler::Fail; 4863 } else 4864 Inst.addOperand(MCOperand::createReg(0)); 4865 } 4866 4867 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4868 return MCDisassembler::Fail; 4869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4870 return MCDisassembler::Fail; 4871 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4872 return MCDisassembler::Fail; 4873 Inst.addOperand(MCOperand::createImm(index)); 4874 4875 return S; 4876 } 4877 4878 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4879 uint64_t Address, const void *Decoder) { 4880 DecodeStatus S = MCDisassembler::Success; 4881 4882 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4883 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4884 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4885 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4886 unsigned size = fieldFromInstruction(Insn, 10, 2); 4887 4888 unsigned align = 0; 4889 unsigned index = 0; 4890 unsigned inc = 1; 4891 switch (size) { 4892 default: 4893 return MCDisassembler::Fail; 4894 case 0: 4895 if (fieldFromInstruction(Insn, 4, 1)) 4896 return MCDisassembler::Fail; // UNDEFINED 4897 index = fieldFromInstruction(Insn, 5, 3); 4898 break; 4899 case 1: 4900 if (fieldFromInstruction(Insn, 4, 1)) 4901 return MCDisassembler::Fail; // UNDEFINED 4902 index = fieldFromInstruction(Insn, 6, 2); 4903 if (fieldFromInstruction(Insn, 5, 1)) 4904 inc = 2; 4905 break; 4906 case 2: 4907 if (fieldFromInstruction(Insn, 4, 2)) 4908 return MCDisassembler::Fail; // UNDEFINED 4909 index = fieldFromInstruction(Insn, 7, 1); 4910 if (fieldFromInstruction(Insn, 6, 1)) 4911 inc = 2; 4912 break; 4913 } 4914 4915 if (Rm != 0xF) { // Writeback 4916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4917 return MCDisassembler::Fail; 4918 } 4919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4920 return MCDisassembler::Fail; 4921 Inst.addOperand(MCOperand::createImm(align)); 4922 if (Rm != 0xF) { 4923 if (Rm != 0xD) { 4924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4925 return MCDisassembler::Fail; 4926 } else 4927 Inst.addOperand(MCOperand::createReg(0)); 4928 } 4929 4930 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4931 return MCDisassembler::Fail; 4932 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4933 return MCDisassembler::Fail; 4934 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4935 return MCDisassembler::Fail; 4936 Inst.addOperand(MCOperand::createImm(index)); 4937 4938 return S; 4939 } 4940 4941 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4942 uint64_t Address, const void *Decoder) { 4943 DecodeStatus S = MCDisassembler::Success; 4944 4945 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4946 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4947 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4948 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4949 unsigned size = fieldFromInstruction(Insn, 10, 2); 4950 4951 unsigned align = 0; 4952 unsigned index = 0; 4953 unsigned inc = 1; 4954 switch (size) { 4955 default: 4956 return MCDisassembler::Fail; 4957 case 0: 4958 if (fieldFromInstruction(Insn, 4, 1)) 4959 align = 4; 4960 index = fieldFromInstruction(Insn, 5, 3); 4961 break; 4962 case 1: 4963 if (fieldFromInstruction(Insn, 4, 1)) 4964 align = 8; 4965 index = fieldFromInstruction(Insn, 6, 2); 4966 if (fieldFromInstruction(Insn, 5, 1)) 4967 inc = 2; 4968 break; 4969 case 2: 4970 switch (fieldFromInstruction(Insn, 4, 2)) { 4971 case 0: 4972 align = 0; break; 4973 case 3: 4974 return MCDisassembler::Fail; 4975 default: 4976 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4977 } 4978 4979 index = fieldFromInstruction(Insn, 7, 1); 4980 if (fieldFromInstruction(Insn, 6, 1)) 4981 inc = 2; 4982 break; 4983 } 4984 4985 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4986 return MCDisassembler::Fail; 4987 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4988 return MCDisassembler::Fail; 4989 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4990 return MCDisassembler::Fail; 4991 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4992 return MCDisassembler::Fail; 4993 4994 if (Rm != 0xF) { // Writeback 4995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4996 return MCDisassembler::Fail; 4997 } 4998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4999 return MCDisassembler::Fail; 5000 Inst.addOperand(MCOperand::createImm(align)); 5001 if (Rm != 0xF) { 5002 if (Rm != 0xD) { 5003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5004 return MCDisassembler::Fail; 5005 } else 5006 Inst.addOperand(MCOperand::createReg(0)); 5007 } 5008 5009 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5010 return MCDisassembler::Fail; 5011 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5012 return MCDisassembler::Fail; 5013 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5014 return MCDisassembler::Fail; 5015 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5016 return MCDisassembler::Fail; 5017 Inst.addOperand(MCOperand::createImm(index)); 5018 5019 return S; 5020 } 5021 5022 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5023 uint64_t Address, const void *Decoder) { 5024 DecodeStatus S = MCDisassembler::Success; 5025 5026 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5027 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5028 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5029 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5030 unsigned size = fieldFromInstruction(Insn, 10, 2); 5031 5032 unsigned align = 0; 5033 unsigned index = 0; 5034 unsigned inc = 1; 5035 switch (size) { 5036 default: 5037 return MCDisassembler::Fail; 5038 case 0: 5039 if (fieldFromInstruction(Insn, 4, 1)) 5040 align = 4; 5041 index = fieldFromInstruction(Insn, 5, 3); 5042 break; 5043 case 1: 5044 if (fieldFromInstruction(Insn, 4, 1)) 5045 align = 8; 5046 index = fieldFromInstruction(Insn, 6, 2); 5047 if (fieldFromInstruction(Insn, 5, 1)) 5048 inc = 2; 5049 break; 5050 case 2: 5051 switch (fieldFromInstruction(Insn, 4, 2)) { 5052 case 0: 5053 align = 0; break; 5054 case 3: 5055 return MCDisassembler::Fail; 5056 default: 5057 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5058 } 5059 5060 index = fieldFromInstruction(Insn, 7, 1); 5061 if (fieldFromInstruction(Insn, 6, 1)) 5062 inc = 2; 5063 break; 5064 } 5065 5066 if (Rm != 0xF) { // Writeback 5067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5068 return MCDisassembler::Fail; 5069 } 5070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5071 return MCDisassembler::Fail; 5072 Inst.addOperand(MCOperand::createImm(align)); 5073 if (Rm != 0xF) { 5074 if (Rm != 0xD) { 5075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5076 return MCDisassembler::Fail; 5077 } else 5078 Inst.addOperand(MCOperand::createReg(0)); 5079 } 5080 5081 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5082 return MCDisassembler::Fail; 5083 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5084 return MCDisassembler::Fail; 5085 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5086 return MCDisassembler::Fail; 5087 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5088 return MCDisassembler::Fail; 5089 Inst.addOperand(MCOperand::createImm(index)); 5090 5091 return S; 5092 } 5093 5094 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5095 uint64_t Address, const void *Decoder) { 5096 DecodeStatus S = MCDisassembler::Success; 5097 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5098 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5099 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5100 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5101 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5102 5103 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5104 S = MCDisassembler::SoftFail; 5105 5106 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5107 return MCDisassembler::Fail; 5108 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5109 return MCDisassembler::Fail; 5110 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5111 return MCDisassembler::Fail; 5112 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5113 return MCDisassembler::Fail; 5114 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5115 return MCDisassembler::Fail; 5116 5117 return S; 5118 } 5119 5120 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5121 uint64_t Address, const void *Decoder) { 5122 DecodeStatus S = MCDisassembler::Success; 5123 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5124 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5125 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5126 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5127 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5128 5129 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5130 S = MCDisassembler::SoftFail; 5131 5132 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5133 return MCDisassembler::Fail; 5134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5135 return MCDisassembler::Fail; 5136 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5137 return MCDisassembler::Fail; 5138 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5139 return MCDisassembler::Fail; 5140 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5141 return MCDisassembler::Fail; 5142 5143 return S; 5144 } 5145 5146 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5147 uint64_t Address, const void *Decoder) { 5148 DecodeStatus S = MCDisassembler::Success; 5149 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5150 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5151 5152 if (pred == 0xF) { 5153 pred = 0xE; 5154 S = MCDisassembler::SoftFail; 5155 } 5156 5157 if (mask == 0x0) 5158 return MCDisassembler::Fail; 5159 5160 Inst.addOperand(MCOperand::createImm(pred)); 5161 Inst.addOperand(MCOperand::createImm(mask)); 5162 return S; 5163 } 5164 5165 static DecodeStatus 5166 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5167 uint64_t Address, const void *Decoder) { 5168 DecodeStatus S = MCDisassembler::Success; 5169 5170 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5171 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5172 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5173 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5174 unsigned W = fieldFromInstruction(Insn, 21, 1); 5175 unsigned U = fieldFromInstruction(Insn, 23, 1); 5176 unsigned P = fieldFromInstruction(Insn, 24, 1); 5177 bool writeback = (W == 1) | (P == 0); 5178 5179 addr |= (U << 8) | (Rn << 9); 5180 5181 if (writeback && (Rn == Rt || Rn == Rt2)) 5182 Check(S, MCDisassembler::SoftFail); 5183 if (Rt == Rt2) 5184 Check(S, MCDisassembler::SoftFail); 5185 5186 // Rt 5187 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5188 return MCDisassembler::Fail; 5189 // Rt2 5190 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5191 return MCDisassembler::Fail; 5192 // Writeback operand 5193 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5194 return MCDisassembler::Fail; 5195 // addr 5196 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5197 return MCDisassembler::Fail; 5198 5199 return S; 5200 } 5201 5202 static DecodeStatus 5203 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5204 uint64_t Address, const void *Decoder) { 5205 DecodeStatus S = MCDisassembler::Success; 5206 5207 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5208 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5209 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5210 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5211 unsigned W = fieldFromInstruction(Insn, 21, 1); 5212 unsigned U = fieldFromInstruction(Insn, 23, 1); 5213 unsigned P = fieldFromInstruction(Insn, 24, 1); 5214 bool writeback = (W == 1) | (P == 0); 5215 5216 addr |= (U << 8) | (Rn << 9); 5217 5218 if (writeback && (Rn == Rt || Rn == Rt2)) 5219 Check(S, MCDisassembler::SoftFail); 5220 5221 // Writeback operand 5222 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5223 return MCDisassembler::Fail; 5224 // Rt 5225 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5226 return MCDisassembler::Fail; 5227 // Rt2 5228 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5229 return MCDisassembler::Fail; 5230 // addr 5231 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5232 return MCDisassembler::Fail; 5233 5234 return S; 5235 } 5236 5237 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5238 uint64_t Address, const void *Decoder) { 5239 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5240 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5241 if (sign1 != sign2) return MCDisassembler::Fail; 5242 5243 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5244 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5245 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5246 Val |= sign1 << 12; 5247 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5248 5249 return MCDisassembler::Success; 5250 } 5251 5252 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5253 uint64_t Address, 5254 const void *Decoder) { 5255 DecodeStatus S = MCDisassembler::Success; 5256 5257 // Shift of "asr #32" is not allowed in Thumb2 mode. 5258 if (Val == 0x20) S = MCDisassembler::Fail; 5259 Inst.addOperand(MCOperand::createImm(Val)); 5260 return S; 5261 } 5262 5263 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5264 uint64_t Address, const void *Decoder) { 5265 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5266 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5267 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5268 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5269 5270 if (pred == 0xF) 5271 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5272 5273 DecodeStatus S = MCDisassembler::Success; 5274 5275 if (Rt == Rn || Rn == Rt2) 5276 S = MCDisassembler::SoftFail; 5277 5278 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5279 return MCDisassembler::Fail; 5280 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5281 return MCDisassembler::Fail; 5282 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5283 return MCDisassembler::Fail; 5284 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5285 return MCDisassembler::Fail; 5286 5287 return S; 5288 } 5289 5290 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5291 uint64_t Address, const void *Decoder) { 5292 const FeatureBitset &featureBits = 5293 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5294 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5295 5296 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5297 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5298 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5299 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5300 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5301 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5302 unsigned op = fieldFromInstruction(Insn, 5, 1); 5303 5304 DecodeStatus S = MCDisassembler::Success; 5305 5306 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5307 if (!(imm & 0x38)) { 5308 if (cmode == 0xF) { 5309 if (op == 1) return MCDisassembler::Fail; 5310 Inst.setOpcode(ARM::VMOVv2f32); 5311 } 5312 if (hasFullFP16) { 5313 if (cmode == 0xE) { 5314 if (op == 1) { 5315 Inst.setOpcode(ARM::VMOVv1i64); 5316 } else { 5317 Inst.setOpcode(ARM::VMOVv8i8); 5318 } 5319 } 5320 if (cmode == 0xD) { 5321 if (op == 1) { 5322 Inst.setOpcode(ARM::VMVNv2i32); 5323 } else { 5324 Inst.setOpcode(ARM::VMOVv2i32); 5325 } 5326 } 5327 if (cmode == 0xC) { 5328 if (op == 1) { 5329 Inst.setOpcode(ARM::VMVNv2i32); 5330 } else { 5331 Inst.setOpcode(ARM::VMOVv2i32); 5332 } 5333 } 5334 } 5335 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5336 } 5337 5338 if (!(imm & 0x20)) return MCDisassembler::Fail; 5339 5340 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5341 return MCDisassembler::Fail; 5342 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5343 return MCDisassembler::Fail; 5344 Inst.addOperand(MCOperand::createImm(64 - imm)); 5345 5346 return S; 5347 } 5348 5349 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5350 uint64_t Address, const void *Decoder) { 5351 const FeatureBitset &featureBits = 5352 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5353 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5354 5355 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5356 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5357 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5358 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5359 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5360 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5361 unsigned op = fieldFromInstruction(Insn, 5, 1); 5362 5363 DecodeStatus S = MCDisassembler::Success; 5364 5365 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5366 if (!(imm & 0x38)) { 5367 if (cmode == 0xF) { 5368 if (op == 1) return MCDisassembler::Fail; 5369 Inst.setOpcode(ARM::VMOVv4f32); 5370 } 5371 if (hasFullFP16) { 5372 if (cmode == 0xE) { 5373 if (op == 1) { 5374 Inst.setOpcode(ARM::VMOVv2i64); 5375 } else { 5376 Inst.setOpcode(ARM::VMOVv16i8); 5377 } 5378 } 5379 if (cmode == 0xD) { 5380 if (op == 1) { 5381 Inst.setOpcode(ARM::VMVNv4i32); 5382 } else { 5383 Inst.setOpcode(ARM::VMOVv4i32); 5384 } 5385 } 5386 if (cmode == 0xC) { 5387 if (op == 1) { 5388 Inst.setOpcode(ARM::VMVNv4i32); 5389 } else { 5390 Inst.setOpcode(ARM::VMOVv4i32); 5391 } 5392 } 5393 } 5394 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5395 } 5396 5397 if (!(imm & 0x20)) return MCDisassembler::Fail; 5398 5399 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5400 return MCDisassembler::Fail; 5401 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5402 return MCDisassembler::Fail; 5403 Inst.addOperand(MCOperand::createImm(64 - imm)); 5404 5405 return S; 5406 } 5407 5408 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5409 unsigned Insn, 5410 uint64_t Address, 5411 const void *Decoder) { 5412 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5413 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5414 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5415 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5416 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5417 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5418 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5419 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5420 5421 DecodeStatus S = MCDisassembler::Success; 5422 5423 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5424 5425 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5426 return MCDisassembler::Fail; 5427 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5428 return MCDisassembler::Fail; 5429 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5430 return MCDisassembler::Fail; 5431 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5432 return MCDisassembler::Fail; 5433 // The lane index does not have any bits in the encoding, because it can only 5434 // be 0. 5435 Inst.addOperand(MCOperand::createImm(0)); 5436 Inst.addOperand(MCOperand::createImm(rotate)); 5437 5438 return S; 5439 } 5440 5441 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5442 uint64_t Address, const void *Decoder) { 5443 DecodeStatus S = MCDisassembler::Success; 5444 5445 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5446 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5447 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5448 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5449 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5450 5451 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5452 S = MCDisassembler::SoftFail; 5453 5454 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5455 return MCDisassembler::Fail; 5456 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5457 return MCDisassembler::Fail; 5458 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5459 return MCDisassembler::Fail; 5460 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5461 return MCDisassembler::Fail; 5462 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5463 return MCDisassembler::Fail; 5464 5465 return S; 5466 } 5467 5468 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5469 uint64_t Address, const void *Decoder) { 5470 DecodeStatus S = MCDisassembler::Success; 5471 5472 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5473 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5474 unsigned cop = fieldFromInstruction(Val, 8, 4); 5475 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5476 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5477 5478 if ((cop & ~0x1) == 0xa) 5479 return MCDisassembler::Fail; 5480 5481 if (Rt == Rt2) 5482 S = MCDisassembler::SoftFail; 5483 5484 // We have to check if the instruction is MRRC2 5485 // or MCRR2 when constructing the operands for 5486 // Inst. Reason is because MRRC2 stores to two 5487 // registers so it's tablegen desc has has two 5488 // outputs whereas MCRR doesn't store to any 5489 // registers so all of it's operands are listed 5490 // as inputs, therefore the operand order for 5491 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5492 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5493 5494 if (Inst.getOpcode() == ARM::MRRC2) { 5495 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5496 return MCDisassembler::Fail; 5497 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5498 return MCDisassembler::Fail; 5499 } 5500 Inst.addOperand(MCOperand::createImm(cop)); 5501 Inst.addOperand(MCOperand::createImm(opc1)); 5502 if (Inst.getOpcode() == ARM::MCRR2) { 5503 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5504 return MCDisassembler::Fail; 5505 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5506 return MCDisassembler::Fail; 5507 } 5508 Inst.addOperand(MCOperand::createImm(CRm)); 5509 5510 return S; 5511 } 5512 5513 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5514 uint64_t Address, 5515 const void *Decoder) { 5516 const FeatureBitset &featureBits = 5517 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5518 DecodeStatus S = MCDisassembler::Success; 5519 5520 // Add explicit operand for the destination sysreg, for cases where 5521 // we have to model it for code generation purposes. 5522 switch (Inst.getOpcode()) { 5523 case ARM::VMSR_FPSCR_NZCVQC: 5524 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5525 break; 5526 case ARM::VMSR_P0: 5527 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5528 break; 5529 } 5530 5531 if (Inst.getOpcode() != ARM::FMSTAT) { 5532 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5533 5534 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5535 if (Rt == 13 || Rt == 15) 5536 S = MCDisassembler::SoftFail; 5537 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5538 } else 5539 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5540 } 5541 5542 // Add explicit operand for the source sysreg, similarly to above. 5543 switch (Inst.getOpcode()) { 5544 case ARM::VMRS_FPSCR_NZCVQC: 5545 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5546 break; 5547 case ARM::VMRS_P0: 5548 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5549 break; 5550 } 5551 5552 if (featureBits[ARM::ModeThumb]) { 5553 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5554 Inst.addOperand(MCOperand::createReg(0)); 5555 } else { 5556 unsigned pred = fieldFromInstruction(Val, 28, 4); 5557 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5558 return MCDisassembler::Fail; 5559 } 5560 5561 return S; 5562 } 5563 5564 template <bool isSigned, bool isNeg, int size> 5565 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5566 uint64_t Address, 5567 const void *Decoder) { 5568 DecodeStatus S = MCDisassembler::Success; 5569 if (Val == 0) 5570 S = MCDisassembler::SoftFail; 5571 5572 uint64_t DecVal; 5573 if (isSigned) 5574 DecVal = SignExtend32<size + 1>(Val << 1); 5575 else 5576 DecVal = (Val << 1); 5577 5578 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5579 Decoder)) 5580 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5581 return S; 5582 } 5583 5584 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5585 uint64_t Address, 5586 const void *Decoder) { 5587 5588 uint64_t LocImm = Inst.getOperand(0).getImm(); 5589 Val = LocImm + (2 << Val); 5590 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5591 Decoder)) 5592 Inst.addOperand(MCOperand::createImm(Val)); 5593 return MCDisassembler::Success; 5594 } 5595 5596 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5597 uint64_t Address, 5598 const void *Decoder) { 5599 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5600 return MCDisassembler::Fail; 5601 Inst.addOperand(MCOperand::createImm(Val)); 5602 return MCDisassembler::Success; 5603 } 5604 5605 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5606 const void *Decoder) { 5607 DecodeStatus S = MCDisassembler::Success; 5608 5609 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5610 fieldFromInstruction(Insn, 1, 10) << 1; 5611 switch (Inst.getOpcode()) { 5612 case ARM::t2LEUpdate: 5613 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5614 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5615 LLVM_FALLTHROUGH; 5616 case ARM::t2LE: 5617 if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address, 5618 Decoder))) 5619 return MCDisassembler::Fail; 5620 break; 5621 case ARM::t2WLS: 5622 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5623 if (!Check(S, 5624 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5625 Address, Decoder)) || 5626 !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address, 5627 Decoder))) 5628 return MCDisassembler::Fail; 5629 break; 5630 case ARM::t2DLS: 5631 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5632 if (Rn == 0xF) { 5633 return MCDisassembler::Fail; 5634 } else { 5635 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5636 if (!Check(S, DecoderGPRRegisterClass(Inst, 5637 fieldFromInstruction(Insn, 16, 4), 5638 Address, Decoder))) 5639 return MCDisassembler::Fail; 5640 } 5641 break; 5642 } 5643 return S; 5644 } 5645 5646 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 5647 const void *Decoder) { 5648 DecodeStatus S = MCDisassembler::Success; 5649 5650 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5651 Inst.addOperand(MCOperand::createReg(0)); 5652 if (Inst.getOpcode() == ARM::VSCCLRMD) { 5653 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 5654 (fieldFromInstruction(Insn, 12, 4) << 8) | 5655 (fieldFromInstruction(Insn, 22, 1) << 12); 5656 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 5657 return MCDisassembler::Fail; 5658 } 5659 } else { 5660 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 5661 (fieldFromInstruction(Insn, 22, 1) << 8) | 5662 (fieldFromInstruction(Insn, 12, 4) << 9); 5663 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 5664 return MCDisassembler::Fail; 5665 } 5666 } 5667 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5668 5669 return S; 5670 } 5671 5672 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 5673 switch (Opcode) { 5674 case ARM::VSTR_P0_off: 5675 case ARM::VSTR_P0_pre: 5676 case ARM::VSTR_P0_post: 5677 case ARM::VLDR_P0_off: 5678 case ARM::VLDR_P0_pre: 5679 case ARM::VLDR_P0_post: 5680 return ARM::P0; 5681 default: 5682 return 0; 5683 } 5684 } 5685 5686 template<bool Writeback> 5687 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 5688 uint64_t Address, 5689 const void *Decoder) { 5690 switch (Inst.getOpcode()) { 5691 case ARM::VSTR_FPSCR_pre: 5692 case ARM::VSTR_FPSCR_NZCVQC_pre: 5693 case ARM::VLDR_FPSCR_pre: 5694 case ARM::VLDR_FPSCR_NZCVQC_pre: 5695 case ARM::VSTR_FPSCR_off: 5696 case ARM::VSTR_FPSCR_NZCVQC_off: 5697 case ARM::VLDR_FPSCR_off: 5698 case ARM::VLDR_FPSCR_NZCVQC_off: 5699 case ARM::VSTR_FPSCR_post: 5700 case ARM::VSTR_FPSCR_NZCVQC_post: 5701 case ARM::VLDR_FPSCR_post: 5702 case ARM::VLDR_FPSCR_NZCVQC_post: 5703 const FeatureBitset &featureBits = 5704 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5705 5706 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 5707 return MCDisassembler::Fail; 5708 } 5709 5710 DecodeStatus S = MCDisassembler::Success; 5711 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 5712 Inst.addOperand(MCOperand::createReg(Sysreg)); 5713 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5714 unsigned addr = fieldFromInstruction(Val, 0, 7) | 5715 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 5716 5717 if (Writeback) { 5718 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5719 return MCDisassembler::Fail; 5720 } 5721 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 5722 return MCDisassembler::Fail; 5723 5724 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5725 Inst.addOperand(MCOperand::createReg(0)); 5726 5727 return S; 5728 } 5729