1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &VStream, 141 raw_ostream &CStream) const override; 142 143 private: 144 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 145 ArrayRef<uint8_t> Bytes, uint64_t Address, 146 raw_ostream &VStream, 147 raw_ostream &CStream) const; 148 149 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 150 ArrayRef<uint8_t> Bytes, uint64_t Address, 151 raw_ostream &VStream, 152 raw_ostream &CStream) const; 153 154 mutable ITStatus ITBlock; 155 mutable VPTStatus VPTBlock; 156 157 DecodeStatus AddThumbPredicate(MCInst&) const; 158 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 159 }; 160 161 } // end anonymous namespace 162 163 static bool Check(DecodeStatus &Out, DecodeStatus In) { 164 switch (In) { 165 case MCDisassembler::Success: 166 // Out stays the same. 167 return true; 168 case MCDisassembler::SoftFail: 169 Out = In; 170 return true; 171 case MCDisassembler::Fail: 172 Out = In; 173 return false; 174 } 175 llvm_unreachable("Invalid DecodeStatus!"); 176 } 177 178 // Forward declare these because the autogenerated code will reference them. 179 // Definitions are further down. 180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 216 unsigned RegNo, 217 uint64_t Address, 218 const void *Decoder); 219 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 230 unsigned RegNo, uint64_t Address, 231 const void *Decoder); 232 233 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 244 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 249 unsigned Insn, 250 uint64_t Address, 251 const void *Decoder); 252 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 261 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 262 unsigned Insn, 263 uint64_t Adddress, 264 const void *Decoder); 265 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 336 uint64_t Address, const void *Decoder); 337 template<int shift> 338 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 391 unsigned Val, 392 uint64_t Address, 393 const void *Decoder); 394 395 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 408 uint64_t Address, const void *Decoder); 409 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 410 uint64_t Address, const void *Decoder); 411 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 412 uint64_t Address, const void *Decoder); 413 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 414 uint64_t Address, const void *Decoder); 415 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 416 uint64_t Address, const void* Decoder); 417 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 418 uint64_t Address, const void* Decoder); 419 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 420 uint64_t Address, const void* Decoder); 421 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 422 uint64_t Address, const void* Decoder); 423 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 424 uint64_t Address, const void *Decoder); 425 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 426 uint64_t Address, const void *Decoder); 427 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 428 uint64_t Address, const void *Decoder); 429 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 430 uint64_t Address, 431 const void *Decoder); 432 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 433 uint64_t Address, const void *Decoder); 434 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 435 uint64_t Address, const void *Decoder); 436 template<int shift> 437 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 438 uint64_t Address, const void *Decoder); 439 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 440 uint64_t Address, const void *Decoder); 441 template<int shift> 442 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 443 uint64_t Address, const void *Decoder); 444 template<int shift, int WriteBack> 445 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 446 uint64_t Address, const void *Decoder); 447 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 448 uint64_t Address, const void *Decoder); 449 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 450 uint64_t Address, const void *Decoder); 451 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 452 uint64_t Address, const void *Decoder); 453 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 454 uint64_t Address, const void *Decoder); 455 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 456 uint64_t Address, const void *Decoder); 457 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 458 uint64_t Address, const void *Decoder); 459 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 460 uint64_t Address, const void *Decoder); 461 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 462 uint64_t Address, const void *Decoder); 463 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 464 uint64_t Address, const void *Decoder); 465 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 466 uint64_t Address, const void *Decoder); 467 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 468 uint64_t Address, const void *Decoder); 469 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 470 uint64_t Address, const void *Decoder); 471 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 472 uint64_t Address, const void *Decoder); 473 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 474 uint64_t Address, const void *Decoder); 475 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 476 uint64_t Address, const void *Decoder); 477 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 478 uint64_t Address, const void *Decoder); 479 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 480 uint64_t Address, const void *Decoder); 481 482 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 483 uint64_t Address, const void *Decoder); 484 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 489 template <bool isSigned, bool isNeg, int size> 490 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 491 uint64_t Address, const void *Decoder); 492 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 493 uint64_t Address, 494 const void *Decoder); 495 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 496 uint64_t Address, 497 const void *Decoder); 498 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 499 const void *Decoder); 500 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 501 uint64_t Address, 502 const void *Decoder); 503 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 504 const void *Decoder); 505 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 506 uint64_t Address, const void *Decoder); 507 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 508 uint64_t Address, const void *Decoder); 509 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 510 uint64_t Address, 511 const void *Decoder); 512 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 513 uint64_t Address, 514 const void *Decoder); 515 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 516 uint64_t Address, 517 const void *Decoder); 518 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 519 unsigned Val, 520 uint64_t Address, 521 const void *Decoder); 522 template<bool Writeback> 523 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 524 uint64_t Address, 525 const void *Decoder); 526 template<int shift> 527 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 528 uint64_t Address, const void *Decoder); 529 template<int shift> 530 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 531 uint64_t Address, const void *Decoder); 532 template<int shift> 533 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 534 uint64_t Address, const void *Decoder); 535 template<unsigned MinLog, unsigned MaxLog> 536 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 537 uint64_t Address, 538 const void *Decoder); 539 template <int shift> 540 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 541 uint64_t Address, 542 const void *Decoder); 543 template<unsigned start> 544 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 545 uint64_t Address, 546 const void *Decoder); 547 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 548 uint64_t Address, 549 const void *Decoder); 550 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 551 uint64_t Address, 552 const void *Decoder); 553 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 554 uint64_t Address, const void *Decoder); 555 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 556 uint64_t Address, const void *Decoder); 557 template<bool scalar, OperandDecoder predicate_decoder> 558 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 559 uint64_t Address, const void *Decoder); 560 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 561 uint64_t Address, const void *Decoder); 562 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 563 uint64_t Address, 564 const void *Decoder); 565 #include "ARMGenDisassemblerTables.inc" 566 567 static MCDisassembler *createARMDisassembler(const Target &T, 568 const MCSubtargetInfo &STI, 569 MCContext &Ctx) { 570 return new ARMDisassembler(STI, Ctx); 571 } 572 573 // Post-decoding checks 574 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 575 uint64_t Address, raw_ostream &OS, 576 raw_ostream &CS, 577 uint32_t Insn, 578 DecodeStatus Result) { 579 switch (MI.getOpcode()) { 580 case ARM::HVC: { 581 // HVC is undefined if condition = 0xf otherwise upredictable 582 // if condition != 0xe 583 uint32_t Cond = (Insn >> 28) & 0xF; 584 if (Cond == 0xF) 585 return MCDisassembler::Fail; 586 if (Cond != 0xE) 587 return MCDisassembler::SoftFail; 588 return Result; 589 } 590 case ARM::t2ADDri: 591 case ARM::t2ADDri12: 592 case ARM::t2ADDrr: 593 case ARM::t2ADDrs: 594 case ARM::t2SUBri: 595 case ARM::t2SUBri12: 596 case ARM::t2SUBrr: 597 case ARM::t2SUBrs: 598 if (MI.getOperand(0).getReg() == ARM::SP && 599 MI.getOperand(1).getReg() != ARM::SP) 600 return MCDisassembler::SoftFail; 601 return Result; 602 default: return Result; 603 } 604 } 605 606 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 607 ArrayRef<uint8_t> Bytes, 608 uint64_t Address, raw_ostream &OS, 609 raw_ostream &CS) const { 610 if (STI.getFeatureBits()[ARM::ModeThumb]) 611 return getThumbInstruction(MI, Size, Bytes, Address, OS, CS); 612 return getARMInstruction(MI, Size, Bytes, Address, OS, CS); 613 } 614 615 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 616 ArrayRef<uint8_t> Bytes, 617 uint64_t Address, 618 raw_ostream &OS, 619 raw_ostream &CS) const { 620 CommentStream = &CS; 621 622 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 623 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 624 "mode!"); 625 626 // We want to read exactly 4 bytes of data. 627 if (Bytes.size() < 4) { 628 Size = 0; 629 return MCDisassembler::Fail; 630 } 631 632 // Encoded as a small-endian 32-bit word in the stream. 633 uint32_t Insn = 634 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 635 636 // Calling the auto-generated decoder function. 637 DecodeStatus Result = 638 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 639 if (Result != MCDisassembler::Fail) { 640 Size = 4; 641 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 642 } 643 644 struct DecodeTable { 645 const uint8_t *P; 646 bool DecodePred; 647 }; 648 649 const DecodeTable Tables[] = { 650 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 651 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 652 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 653 {DecoderTablev8Crypto32, false}, 654 }; 655 656 for (auto Table : Tables) { 657 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 658 if (Result != MCDisassembler::Fail) { 659 Size = 4; 660 // Add a fake predicate operand, because we share these instruction 661 // definitions with Thumb2 where these instructions are predicable. 662 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 663 return MCDisassembler::Fail; 664 return Result; 665 } 666 } 667 668 Result = 669 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 670 if (Result != MCDisassembler::Fail) { 671 Size = 4; 672 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 673 } 674 675 Size = 4; 676 return MCDisassembler::Fail; 677 } 678 679 namespace llvm { 680 681 extern const MCInstrDesc ARMInsts[]; 682 683 } // end namespace llvm 684 685 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 686 /// immediate Value in the MCInst. The immediate Value has had any PC 687 /// adjustment made by the caller. If the instruction is a branch instruction 688 /// then isBranch is true, else false. If the getOpInfo() function was set as 689 /// part of the setupForSymbolicDisassembly() call then that function is called 690 /// to get any symbolic information at the Address for this instruction. If 691 /// that returns non-zero then the symbolic information it returns is used to 692 /// create an MCExpr and that is added as an operand to the MCInst. If 693 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 694 /// Value is done and if a symbol is found an MCExpr is created with that, else 695 /// an MCExpr with Value is created. This function returns true if it adds an 696 /// operand to the MCInst and false otherwise. 697 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 698 bool isBranch, uint64_t InstSize, 699 MCInst &MI, const void *Decoder) { 700 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 701 // FIXME: Does it make sense for value to be negative? 702 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 703 /* Offset */ 0, InstSize); 704 } 705 706 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 707 /// referenced by a load instruction with the base register that is the Pc. 708 /// These can often be values in a literal pool near the Address of the 709 /// instruction. The Address of the instruction and its immediate Value are 710 /// used as a possible literal pool entry. The SymbolLookUp call back will 711 /// return the name of a symbol referenced by the literal pool's entry if 712 /// the referenced address is that of a symbol. Or it will return a pointer to 713 /// a literal 'C' string if the referenced address of the literal pool's entry 714 /// is an address into a section with 'C' string literals. 715 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 716 const void *Decoder) { 717 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 718 Dis->tryAddingPcLoadReferenceComment(Value, Address); 719 } 720 721 // Thumb1 instructions don't have explicit S bits. Rather, they 722 // implicitly set CPSR. Since it's not represented in the encoding, the 723 // auto-generated decoder won't inject the CPSR operand. We need to fix 724 // that as a post-pass. 725 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 726 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 727 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 728 MCInst::iterator I = MI.begin(); 729 for (unsigned i = 0; i < NumOps; ++i, ++I) { 730 if (I == MI.end()) break; 731 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 732 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 733 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 734 return; 735 } 736 } 737 738 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 739 } 740 741 static bool isVectorPredicable(unsigned Opcode) { 742 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 743 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 744 for (unsigned i = 0; i < NumOps; ++i) { 745 if (ARM::isVpred(OpInfo[i].OperandType)) 746 return true; 747 } 748 return false; 749 } 750 751 // Most Thumb instructions don't have explicit predicates in the 752 // encoding, but rather get their predicates from IT context. We need 753 // to fix up the predicate operands using this context information as a 754 // post-pass. 755 MCDisassembler::DecodeStatus 756 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 757 MCDisassembler::DecodeStatus S = Success; 758 759 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 760 761 // A few instructions actually have predicates encoded in them. Don't 762 // try to overwrite it if we're seeing one of those. 763 switch (MI.getOpcode()) { 764 case ARM::tBcc: 765 case ARM::t2Bcc: 766 case ARM::tCBZ: 767 case ARM::tCBNZ: 768 case ARM::tCPS: 769 case ARM::t2CPS3p: 770 case ARM::t2CPS2p: 771 case ARM::t2CPS1p: 772 case ARM::t2CSEL: 773 case ARM::t2CSINC: 774 case ARM::t2CSINV: 775 case ARM::t2CSNEG: 776 case ARM::tMOVSr: 777 case ARM::tSETEND: 778 // Some instructions (mostly conditional branches) are not 779 // allowed in IT blocks. 780 if (ITBlock.instrInITBlock()) 781 S = SoftFail; 782 else 783 return Success; 784 break; 785 case ARM::t2HINT: 786 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 787 S = SoftFail; 788 break; 789 case ARM::tB: 790 case ARM::t2B: 791 case ARM::t2TBB: 792 case ARM::t2TBH: 793 // Some instructions (mostly unconditional branches) can 794 // only appears at the end of, or outside of, an IT. 795 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 796 S = SoftFail; 797 break; 798 default: 799 break; 800 } 801 802 // Warn on non-VPT predicable instruction in a VPT block and a VPT 803 // predicable instruction in an IT block 804 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 805 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 806 S = SoftFail; 807 808 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 809 // assume a predicate of AL. 810 unsigned CC = ARMCC::AL; 811 unsigned VCC = ARMVCC::None; 812 if (ITBlock.instrInITBlock()) { 813 CC = ITBlock.getITCC(); 814 ITBlock.advanceITState(); 815 } else if (VPTBlock.instrInVPTBlock()) { 816 VCC = VPTBlock.getVPTPred(); 817 VPTBlock.advanceVPTState(); 818 } 819 820 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 821 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 822 823 MCInst::iterator CCI = MI.begin(); 824 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 825 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 826 } 827 828 if (ARMInsts[MI.getOpcode()].isPredicable()) { 829 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 830 ++CCI; 831 if (CC == ARMCC::AL) 832 MI.insert(CCI, MCOperand::createReg(0)); 833 else 834 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 835 } else if (CC != ARMCC::AL) { 836 Check(S, SoftFail); 837 } 838 839 MCInst::iterator VCCI = MI.begin(); 840 unsigned VCCPos; 841 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 842 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 843 } 844 845 if (isVectorPredicable(MI.getOpcode())) { 846 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 847 ++VCCI; 848 if (VCC == ARMVCC::None) 849 MI.insert(VCCI, MCOperand::createReg(0)); 850 else 851 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 852 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 853 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 854 VCCPos + 2, MCOI::TIED_TO); 855 assert(TiedOp >= 0 && 856 "Inactive register in vpred_r is not tied to an output!"); 857 MI.insert(VCCI, MI.getOperand(TiedOp)); 858 } 859 } else if (VCC != ARMVCC::None) { 860 Check(S, SoftFail); 861 } 862 863 return S; 864 } 865 866 // Thumb VFP instructions are a special case. Because we share their 867 // encodings between ARM and Thumb modes, and they are predicable in ARM 868 // mode, the auto-generated decoder will give them an (incorrect) 869 // predicate operand. We need to rewrite these operands based on the IT 870 // context as a post-pass. 871 void ARMDisassembler::UpdateThumbVFPPredicate( 872 DecodeStatus &S, MCInst &MI) const { 873 unsigned CC; 874 CC = ITBlock.getITCC(); 875 if (CC == 0xF) 876 CC = ARMCC::AL; 877 if (ITBlock.instrInITBlock()) 878 ITBlock.advanceITState(); 879 else if (VPTBlock.instrInVPTBlock()) { 880 CC = VPTBlock.getVPTPred(); 881 VPTBlock.advanceVPTState(); 882 } 883 884 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 885 MCInst::iterator I = MI.begin(); 886 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 887 for (unsigned i = 0; i < NumOps; ++i, ++I) { 888 if (OpInfo[i].isPredicate() ) { 889 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 890 Check(S, SoftFail); 891 I->setImm(CC); 892 ++I; 893 if (CC == ARMCC::AL) 894 I->setReg(0); 895 else 896 I->setReg(ARM::CPSR); 897 return; 898 } 899 } 900 } 901 902 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 903 ArrayRef<uint8_t> Bytes, 904 uint64_t Address, 905 raw_ostream &OS, 906 raw_ostream &CS) const { 907 CommentStream = &CS; 908 909 assert(STI.getFeatureBits()[ARM::ModeThumb] && 910 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 911 912 // We want to read exactly 2 bytes of data. 913 if (Bytes.size() < 2) { 914 Size = 0; 915 return MCDisassembler::Fail; 916 } 917 918 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 919 DecodeStatus Result = 920 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 921 if (Result != MCDisassembler::Fail) { 922 Size = 2; 923 Check(Result, AddThumbPredicate(MI)); 924 return Result; 925 } 926 927 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 928 STI); 929 if (Result) { 930 Size = 2; 931 bool InITBlock = ITBlock.instrInITBlock(); 932 Check(Result, AddThumbPredicate(MI)); 933 AddThumb1SBit(MI, InITBlock); 934 return Result; 935 } 936 937 Result = 938 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 939 if (Result != MCDisassembler::Fail) { 940 Size = 2; 941 942 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 943 // the Thumb predicate. 944 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 945 Result = MCDisassembler::SoftFail; 946 947 Check(Result, AddThumbPredicate(MI)); 948 949 // If we find an IT instruction, we need to parse its condition 950 // code and mask operands so that we can apply them correctly 951 // to the subsequent instructions. 952 if (MI.getOpcode() == ARM::t2IT) { 953 unsigned Firstcond = MI.getOperand(0).getImm(); 954 unsigned Mask = MI.getOperand(1).getImm(); 955 ITBlock.setITState(Firstcond, Mask); 956 957 // An IT instruction that would give a 'NV' predicate is unpredictable. 958 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 959 CS << "unpredictable IT predicate sequence"; 960 } 961 962 return Result; 963 } 964 965 // We want to read exactly 4 bytes of data. 966 if (Bytes.size() < 4) { 967 Size = 0; 968 return MCDisassembler::Fail; 969 } 970 971 uint32_t Insn32 = 972 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 973 974 Result = 975 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 976 if (Result != MCDisassembler::Fail) { 977 Size = 4; 978 979 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 980 // the VPT predicate. 981 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 982 Result = MCDisassembler::SoftFail; 983 984 Check(Result, AddThumbPredicate(MI)); 985 986 if (isVPTOpcode(MI.getOpcode())) { 987 unsigned Mask = MI.getOperand(0).getImm(); 988 VPTBlock.setVPTState(Mask); 989 } 990 991 return Result; 992 } 993 994 Result = 995 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 996 if (Result != MCDisassembler::Fail) { 997 Size = 4; 998 bool InITBlock = ITBlock.instrInITBlock(); 999 Check(Result, AddThumbPredicate(MI)); 1000 AddThumb1SBit(MI, InITBlock); 1001 return Result; 1002 } 1003 1004 Result = 1005 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1006 if (Result != MCDisassembler::Fail) { 1007 Size = 4; 1008 Check(Result, AddThumbPredicate(MI)); 1009 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 1010 } 1011 1012 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1013 Result = 1014 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1015 if (Result != MCDisassembler::Fail) { 1016 Size = 4; 1017 UpdateThumbVFPPredicate(Result, MI); 1018 return Result; 1019 } 1020 } 1021 1022 Result = 1023 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1024 if (Result != MCDisassembler::Fail) { 1025 Size = 4; 1026 return Result; 1027 } 1028 1029 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1030 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1031 STI); 1032 if (Result != MCDisassembler::Fail) { 1033 Size = 4; 1034 Check(Result, AddThumbPredicate(MI)); 1035 return Result; 1036 } 1037 } 1038 1039 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1040 uint32_t NEONLdStInsn = Insn32; 1041 NEONLdStInsn &= 0xF0FFFFFF; 1042 NEONLdStInsn |= 0x04000000; 1043 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1044 Address, this, STI); 1045 if (Result != MCDisassembler::Fail) { 1046 Size = 4; 1047 Check(Result, AddThumbPredicate(MI)); 1048 return Result; 1049 } 1050 } 1051 1052 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1053 uint32_t NEONDataInsn = Insn32; 1054 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1055 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1056 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1057 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1058 Address, this, STI); 1059 if (Result != MCDisassembler::Fail) { 1060 Size = 4; 1061 Check(Result, AddThumbPredicate(MI)); 1062 return Result; 1063 } 1064 1065 uint32_t NEONCryptoInsn = Insn32; 1066 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1067 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1068 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1069 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1070 Address, this, STI); 1071 if (Result != MCDisassembler::Fail) { 1072 Size = 4; 1073 return Result; 1074 } 1075 1076 uint32_t NEONv8Insn = Insn32; 1077 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1078 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1079 this, STI); 1080 if (Result != MCDisassembler::Fail) { 1081 Size = 4; 1082 return Result; 1083 } 1084 } 1085 1086 Result = 1087 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1088 if (Result != MCDisassembler::Fail) { 1089 Size = 4; 1090 Check(Result, AddThumbPredicate(MI)); 1091 return Result; 1092 } 1093 1094 Size = 0; 1095 return MCDisassembler::Fail; 1096 } 1097 1098 extern "C" void LLVMInitializeARMDisassembler() { 1099 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1100 createARMDisassembler); 1101 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1102 createARMDisassembler); 1103 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1104 createARMDisassembler); 1105 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1106 createARMDisassembler); 1107 } 1108 1109 static const uint16_t GPRDecoderTable[] = { 1110 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1111 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1112 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1113 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1114 }; 1115 1116 static const uint16_t CLRMGPRDecoderTable[] = { 1117 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1118 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1119 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1120 ARM::R12, 0, ARM::LR, ARM::APSR 1121 }; 1122 1123 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1124 uint64_t Address, const void *Decoder) { 1125 if (RegNo > 15) 1126 return MCDisassembler::Fail; 1127 1128 unsigned Register = GPRDecoderTable[RegNo]; 1129 Inst.addOperand(MCOperand::createReg(Register)); 1130 return MCDisassembler::Success; 1131 } 1132 1133 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1134 uint64_t Address, 1135 const void *Decoder) { 1136 if (RegNo > 15) 1137 return MCDisassembler::Fail; 1138 1139 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1140 if (Register == 0) 1141 return MCDisassembler::Fail; 1142 1143 Inst.addOperand(MCOperand::createReg(Register)); 1144 return MCDisassembler::Success; 1145 } 1146 1147 static DecodeStatus 1148 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1149 uint64_t Address, const void *Decoder) { 1150 DecodeStatus S = MCDisassembler::Success; 1151 1152 if (RegNo == 15) 1153 S = MCDisassembler::SoftFail; 1154 1155 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1156 1157 return S; 1158 } 1159 1160 static DecodeStatus 1161 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1162 uint64_t Address, const void *Decoder) { 1163 DecodeStatus S = MCDisassembler::Success; 1164 1165 if (RegNo == 15) 1166 { 1167 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1168 return MCDisassembler::Success; 1169 } 1170 1171 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1172 return S; 1173 } 1174 1175 static DecodeStatus 1176 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1177 uint64_t Address, const void *Decoder) { 1178 DecodeStatus S = MCDisassembler::Success; 1179 1180 if (RegNo == 15) 1181 { 1182 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1183 return MCDisassembler::Success; 1184 } 1185 1186 if (RegNo == 13) 1187 S = MCDisassembler::SoftFail; 1188 1189 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1190 return S; 1191 } 1192 1193 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1194 uint64_t Address, const void *Decoder) { 1195 if (RegNo > 7) 1196 return MCDisassembler::Fail; 1197 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1198 } 1199 1200 static const uint16_t GPRPairDecoderTable[] = { 1201 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1202 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1203 }; 1204 1205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1206 uint64_t Address, const void *Decoder) { 1207 DecodeStatus S = MCDisassembler::Success; 1208 1209 if (RegNo > 13) 1210 return MCDisassembler::Fail; 1211 1212 if ((RegNo & 1) || RegNo == 0xe) 1213 S = MCDisassembler::SoftFail; 1214 1215 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1216 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1217 return S; 1218 } 1219 1220 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1221 uint64_t Address, const void *Decoder) { 1222 unsigned Register = 0; 1223 switch (RegNo) { 1224 case 0: 1225 Register = ARM::R0; 1226 break; 1227 case 1: 1228 Register = ARM::R1; 1229 break; 1230 case 2: 1231 Register = ARM::R2; 1232 break; 1233 case 3: 1234 Register = ARM::R3; 1235 break; 1236 case 9: 1237 Register = ARM::R9; 1238 break; 1239 case 12: 1240 Register = ARM::R12; 1241 break; 1242 default: 1243 return MCDisassembler::Fail; 1244 } 1245 1246 Inst.addOperand(MCOperand::createReg(Register)); 1247 return MCDisassembler::Success; 1248 } 1249 1250 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1251 uint64_t Address, const void *Decoder) { 1252 DecodeStatus S = MCDisassembler::Success; 1253 1254 const FeatureBitset &featureBits = 1255 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1256 1257 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1258 S = MCDisassembler::SoftFail; 1259 1260 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1261 return S; 1262 } 1263 1264 static const uint16_t SPRDecoderTable[] = { 1265 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1266 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1267 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1268 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1269 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1270 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1271 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1272 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1273 }; 1274 1275 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1276 uint64_t Address, const void *Decoder) { 1277 if (RegNo > 31) 1278 return MCDisassembler::Fail; 1279 1280 unsigned Register = SPRDecoderTable[RegNo]; 1281 Inst.addOperand(MCOperand::createReg(Register)); 1282 return MCDisassembler::Success; 1283 } 1284 1285 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1286 uint64_t Address, const void *Decoder) { 1287 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1288 } 1289 1290 static const uint16_t DPRDecoderTable[] = { 1291 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1292 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1293 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1294 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1295 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1296 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1297 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1298 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1299 }; 1300 1301 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1302 uint64_t Address, const void *Decoder) { 1303 const FeatureBitset &featureBits = 1304 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1305 1306 bool hasD32 = featureBits[ARM::FeatureD32]; 1307 1308 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1309 return MCDisassembler::Fail; 1310 1311 unsigned Register = DPRDecoderTable[RegNo]; 1312 Inst.addOperand(MCOperand::createReg(Register)); 1313 return MCDisassembler::Success; 1314 } 1315 1316 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1317 uint64_t Address, const void *Decoder) { 1318 if (RegNo > 7) 1319 return MCDisassembler::Fail; 1320 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1321 } 1322 1323 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1324 uint64_t Address, const void *Decoder) { 1325 if (RegNo > 15) 1326 return MCDisassembler::Fail; 1327 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1328 } 1329 1330 static DecodeStatus 1331 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1332 uint64_t Address, const void *Decoder) { 1333 if (RegNo > 15) 1334 return MCDisassembler::Fail; 1335 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1336 } 1337 1338 static const uint16_t QPRDecoderTable[] = { 1339 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1340 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1341 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1342 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1343 }; 1344 1345 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1346 uint64_t Address, const void *Decoder) { 1347 if (RegNo > 31 || (RegNo & 1) != 0) 1348 return MCDisassembler::Fail; 1349 RegNo >>= 1; 1350 1351 unsigned Register = QPRDecoderTable[RegNo]; 1352 Inst.addOperand(MCOperand::createReg(Register)); 1353 return MCDisassembler::Success; 1354 } 1355 1356 static const uint16_t DPairDecoderTable[] = { 1357 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1358 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1359 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1360 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1361 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1362 ARM::Q15 1363 }; 1364 1365 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1366 uint64_t Address, const void *Decoder) { 1367 if (RegNo > 30) 1368 return MCDisassembler::Fail; 1369 1370 unsigned Register = DPairDecoderTable[RegNo]; 1371 Inst.addOperand(MCOperand::createReg(Register)); 1372 return MCDisassembler::Success; 1373 } 1374 1375 static const uint16_t DPairSpacedDecoderTable[] = { 1376 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1377 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1378 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1379 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1380 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1381 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1382 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1383 ARM::D28_D30, ARM::D29_D31 1384 }; 1385 1386 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1387 unsigned RegNo, 1388 uint64_t Address, 1389 const void *Decoder) { 1390 if (RegNo > 29) 1391 return MCDisassembler::Fail; 1392 1393 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1394 Inst.addOperand(MCOperand::createReg(Register)); 1395 return MCDisassembler::Success; 1396 } 1397 1398 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1399 uint64_t Address, const void *Decoder) { 1400 DecodeStatus S = MCDisassembler::Success; 1401 if (Val == 0xF) return MCDisassembler::Fail; 1402 // AL predicate is not allowed on Thumb1 branches. 1403 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1404 return MCDisassembler::Fail; 1405 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1406 Check(S, MCDisassembler::SoftFail); 1407 Inst.addOperand(MCOperand::createImm(Val)); 1408 if (Val == ARMCC::AL) { 1409 Inst.addOperand(MCOperand::createReg(0)); 1410 } else 1411 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1412 return S; 1413 } 1414 1415 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1416 uint64_t Address, const void *Decoder) { 1417 if (Val) 1418 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1419 else 1420 Inst.addOperand(MCOperand::createReg(0)); 1421 return MCDisassembler::Success; 1422 } 1423 1424 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1425 uint64_t Address, const void *Decoder) { 1426 DecodeStatus S = MCDisassembler::Success; 1427 1428 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1429 unsigned type = fieldFromInstruction(Val, 5, 2); 1430 unsigned imm = fieldFromInstruction(Val, 7, 5); 1431 1432 // Register-immediate 1433 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1434 return MCDisassembler::Fail; 1435 1436 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1437 switch (type) { 1438 case 0: 1439 Shift = ARM_AM::lsl; 1440 break; 1441 case 1: 1442 Shift = ARM_AM::lsr; 1443 break; 1444 case 2: 1445 Shift = ARM_AM::asr; 1446 break; 1447 case 3: 1448 Shift = ARM_AM::ror; 1449 break; 1450 } 1451 1452 if (Shift == ARM_AM::ror && imm == 0) 1453 Shift = ARM_AM::rrx; 1454 1455 unsigned Op = Shift | (imm << 3); 1456 Inst.addOperand(MCOperand::createImm(Op)); 1457 1458 return S; 1459 } 1460 1461 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1462 uint64_t Address, const void *Decoder) { 1463 DecodeStatus S = MCDisassembler::Success; 1464 1465 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1466 unsigned type = fieldFromInstruction(Val, 5, 2); 1467 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1468 1469 // Register-register 1470 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1471 return MCDisassembler::Fail; 1472 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1473 return MCDisassembler::Fail; 1474 1475 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1476 switch (type) { 1477 case 0: 1478 Shift = ARM_AM::lsl; 1479 break; 1480 case 1: 1481 Shift = ARM_AM::lsr; 1482 break; 1483 case 2: 1484 Shift = ARM_AM::asr; 1485 break; 1486 case 3: 1487 Shift = ARM_AM::ror; 1488 break; 1489 } 1490 1491 Inst.addOperand(MCOperand::createImm(Shift)); 1492 1493 return S; 1494 } 1495 1496 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1497 uint64_t Address, const void *Decoder) { 1498 DecodeStatus S = MCDisassembler::Success; 1499 1500 bool NeedDisjointWriteback = false; 1501 unsigned WritebackReg = 0; 1502 bool CLRM = false; 1503 switch (Inst.getOpcode()) { 1504 default: 1505 break; 1506 case ARM::LDMIA_UPD: 1507 case ARM::LDMDB_UPD: 1508 case ARM::LDMIB_UPD: 1509 case ARM::LDMDA_UPD: 1510 case ARM::t2LDMIA_UPD: 1511 case ARM::t2LDMDB_UPD: 1512 case ARM::t2STMIA_UPD: 1513 case ARM::t2STMDB_UPD: 1514 NeedDisjointWriteback = true; 1515 WritebackReg = Inst.getOperand(0).getReg(); 1516 break; 1517 case ARM::t2CLRM: 1518 CLRM = true; 1519 break; 1520 } 1521 1522 // Empty register lists are not allowed. 1523 if (Val == 0) return MCDisassembler::Fail; 1524 for (unsigned i = 0; i < 16; ++i) { 1525 if (Val & (1 << i)) { 1526 if (CLRM) { 1527 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1528 return MCDisassembler::Fail; 1529 } 1530 } else { 1531 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1532 return MCDisassembler::Fail; 1533 // Writeback not allowed if Rn is in the target list. 1534 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1535 Check(S, MCDisassembler::SoftFail); 1536 } 1537 } 1538 } 1539 1540 return S; 1541 } 1542 1543 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1544 uint64_t Address, const void *Decoder) { 1545 DecodeStatus S = MCDisassembler::Success; 1546 1547 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1548 unsigned regs = fieldFromInstruction(Val, 0, 8); 1549 1550 // In case of unpredictable encoding, tweak the operands. 1551 if (regs == 0 || (Vd + regs) > 32) { 1552 regs = Vd + regs > 32 ? 32 - Vd : regs; 1553 regs = std::max( 1u, regs); 1554 S = MCDisassembler::SoftFail; 1555 } 1556 1557 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1558 return MCDisassembler::Fail; 1559 for (unsigned i = 0; i < (regs - 1); ++i) { 1560 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1561 return MCDisassembler::Fail; 1562 } 1563 1564 return S; 1565 } 1566 1567 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1568 uint64_t Address, const void *Decoder) { 1569 DecodeStatus S = MCDisassembler::Success; 1570 1571 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1572 unsigned regs = fieldFromInstruction(Val, 1, 7); 1573 1574 // In case of unpredictable encoding, tweak the operands. 1575 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1576 regs = Vd + regs > 32 ? 32 - Vd : regs; 1577 regs = std::max( 1u, regs); 1578 regs = std::min(16u, regs); 1579 S = MCDisassembler::SoftFail; 1580 } 1581 1582 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1583 return MCDisassembler::Fail; 1584 for (unsigned i = 0; i < (regs - 1); ++i) { 1585 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1586 return MCDisassembler::Fail; 1587 } 1588 1589 return S; 1590 } 1591 1592 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1593 uint64_t Address, const void *Decoder) { 1594 // This operand encodes a mask of contiguous zeros between a specified MSB 1595 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1596 // the mask of all bits LSB-and-lower, and then xor them to create 1597 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1598 // create the final mask. 1599 unsigned msb = fieldFromInstruction(Val, 5, 5); 1600 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1601 1602 DecodeStatus S = MCDisassembler::Success; 1603 if (lsb > msb) { 1604 Check(S, MCDisassembler::SoftFail); 1605 // The check above will cause the warning for the "potentially undefined 1606 // instruction encoding" but we can't build a bad MCOperand value here 1607 // with a lsb > msb or else printing the MCInst will cause a crash. 1608 lsb = msb; 1609 } 1610 1611 uint32_t msb_mask = 0xFFFFFFFF; 1612 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1613 uint32_t lsb_mask = (1U << lsb) - 1; 1614 1615 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1616 return S; 1617 } 1618 1619 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1620 uint64_t Address, const void *Decoder) { 1621 DecodeStatus S = MCDisassembler::Success; 1622 1623 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1624 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1625 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1626 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1627 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1628 unsigned U = fieldFromInstruction(Insn, 23, 1); 1629 const FeatureBitset &featureBits = 1630 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1631 1632 switch (Inst.getOpcode()) { 1633 case ARM::LDC_OFFSET: 1634 case ARM::LDC_PRE: 1635 case ARM::LDC_POST: 1636 case ARM::LDC_OPTION: 1637 case ARM::LDCL_OFFSET: 1638 case ARM::LDCL_PRE: 1639 case ARM::LDCL_POST: 1640 case ARM::LDCL_OPTION: 1641 case ARM::STC_OFFSET: 1642 case ARM::STC_PRE: 1643 case ARM::STC_POST: 1644 case ARM::STC_OPTION: 1645 case ARM::STCL_OFFSET: 1646 case ARM::STCL_PRE: 1647 case ARM::STCL_POST: 1648 case ARM::STCL_OPTION: 1649 case ARM::t2LDC_OFFSET: 1650 case ARM::t2LDC_PRE: 1651 case ARM::t2LDC_POST: 1652 case ARM::t2LDC_OPTION: 1653 case ARM::t2LDCL_OFFSET: 1654 case ARM::t2LDCL_PRE: 1655 case ARM::t2LDCL_POST: 1656 case ARM::t2LDCL_OPTION: 1657 case ARM::t2STC_OFFSET: 1658 case ARM::t2STC_PRE: 1659 case ARM::t2STC_POST: 1660 case ARM::t2STC_OPTION: 1661 case ARM::t2STCL_OFFSET: 1662 case ARM::t2STCL_PRE: 1663 case ARM::t2STCL_POST: 1664 case ARM::t2STCL_OPTION: 1665 case ARM::t2LDC2_OFFSET: 1666 case ARM::t2LDC2L_OFFSET: 1667 case ARM::t2LDC2_PRE: 1668 case ARM::t2LDC2L_PRE: 1669 case ARM::t2STC2_OFFSET: 1670 case ARM::t2STC2L_OFFSET: 1671 case ARM::t2STC2_PRE: 1672 case ARM::t2STC2L_PRE: 1673 case ARM::LDC2_OFFSET: 1674 case ARM::LDC2L_OFFSET: 1675 case ARM::LDC2_PRE: 1676 case ARM::LDC2L_PRE: 1677 case ARM::STC2_OFFSET: 1678 case ARM::STC2L_OFFSET: 1679 case ARM::STC2_PRE: 1680 case ARM::STC2L_PRE: 1681 case ARM::t2LDC2_OPTION: 1682 case ARM::t2STC2_OPTION: 1683 case ARM::t2LDC2_POST: 1684 case ARM::t2LDC2L_POST: 1685 case ARM::t2STC2_POST: 1686 case ARM::t2STC2L_POST: 1687 case ARM::LDC2_POST: 1688 case ARM::LDC2L_POST: 1689 case ARM::STC2_POST: 1690 case ARM::STC2L_POST: 1691 if (coproc == 0xA || coproc == 0xB || 1692 (featureBits[ARM::HasV8_1MMainlineOps] && 1693 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1694 coproc == 0xE || coproc == 0xF))) 1695 return MCDisassembler::Fail; 1696 break; 1697 default: 1698 break; 1699 } 1700 1701 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1702 return MCDisassembler::Fail; 1703 1704 Inst.addOperand(MCOperand::createImm(coproc)); 1705 Inst.addOperand(MCOperand::createImm(CRd)); 1706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1707 return MCDisassembler::Fail; 1708 1709 switch (Inst.getOpcode()) { 1710 case ARM::t2LDC2_OFFSET: 1711 case ARM::t2LDC2L_OFFSET: 1712 case ARM::t2LDC2_PRE: 1713 case ARM::t2LDC2L_PRE: 1714 case ARM::t2STC2_OFFSET: 1715 case ARM::t2STC2L_OFFSET: 1716 case ARM::t2STC2_PRE: 1717 case ARM::t2STC2L_PRE: 1718 case ARM::LDC2_OFFSET: 1719 case ARM::LDC2L_OFFSET: 1720 case ARM::LDC2_PRE: 1721 case ARM::LDC2L_PRE: 1722 case ARM::STC2_OFFSET: 1723 case ARM::STC2L_OFFSET: 1724 case ARM::STC2_PRE: 1725 case ARM::STC2L_PRE: 1726 case ARM::t2LDC_OFFSET: 1727 case ARM::t2LDCL_OFFSET: 1728 case ARM::t2LDC_PRE: 1729 case ARM::t2LDCL_PRE: 1730 case ARM::t2STC_OFFSET: 1731 case ARM::t2STCL_OFFSET: 1732 case ARM::t2STC_PRE: 1733 case ARM::t2STCL_PRE: 1734 case ARM::LDC_OFFSET: 1735 case ARM::LDCL_OFFSET: 1736 case ARM::LDC_PRE: 1737 case ARM::LDCL_PRE: 1738 case ARM::STC_OFFSET: 1739 case ARM::STCL_OFFSET: 1740 case ARM::STC_PRE: 1741 case ARM::STCL_PRE: 1742 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1743 Inst.addOperand(MCOperand::createImm(imm)); 1744 break; 1745 case ARM::t2LDC2_POST: 1746 case ARM::t2LDC2L_POST: 1747 case ARM::t2STC2_POST: 1748 case ARM::t2STC2L_POST: 1749 case ARM::LDC2_POST: 1750 case ARM::LDC2L_POST: 1751 case ARM::STC2_POST: 1752 case ARM::STC2L_POST: 1753 case ARM::t2LDC_POST: 1754 case ARM::t2LDCL_POST: 1755 case ARM::t2STC_POST: 1756 case ARM::t2STCL_POST: 1757 case ARM::LDC_POST: 1758 case ARM::LDCL_POST: 1759 case ARM::STC_POST: 1760 case ARM::STCL_POST: 1761 imm |= U << 8; 1762 LLVM_FALLTHROUGH; 1763 default: 1764 // The 'option' variant doesn't encode 'U' in the immediate since 1765 // the immediate is unsigned [0,255]. 1766 Inst.addOperand(MCOperand::createImm(imm)); 1767 break; 1768 } 1769 1770 switch (Inst.getOpcode()) { 1771 case ARM::LDC_OFFSET: 1772 case ARM::LDC_PRE: 1773 case ARM::LDC_POST: 1774 case ARM::LDC_OPTION: 1775 case ARM::LDCL_OFFSET: 1776 case ARM::LDCL_PRE: 1777 case ARM::LDCL_POST: 1778 case ARM::LDCL_OPTION: 1779 case ARM::STC_OFFSET: 1780 case ARM::STC_PRE: 1781 case ARM::STC_POST: 1782 case ARM::STC_OPTION: 1783 case ARM::STCL_OFFSET: 1784 case ARM::STCL_PRE: 1785 case ARM::STCL_POST: 1786 case ARM::STCL_OPTION: 1787 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1788 return MCDisassembler::Fail; 1789 break; 1790 default: 1791 break; 1792 } 1793 1794 return S; 1795 } 1796 1797 static DecodeStatus 1798 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1799 uint64_t Address, const void *Decoder) { 1800 DecodeStatus S = MCDisassembler::Success; 1801 1802 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1803 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1804 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1805 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1806 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1807 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1808 unsigned P = fieldFromInstruction(Insn, 24, 1); 1809 unsigned W = fieldFromInstruction(Insn, 21, 1); 1810 1811 // On stores, the writeback operand precedes Rt. 1812 switch (Inst.getOpcode()) { 1813 case ARM::STR_POST_IMM: 1814 case ARM::STR_POST_REG: 1815 case ARM::STRB_POST_IMM: 1816 case ARM::STRB_POST_REG: 1817 case ARM::STRT_POST_REG: 1818 case ARM::STRT_POST_IMM: 1819 case ARM::STRBT_POST_REG: 1820 case ARM::STRBT_POST_IMM: 1821 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1822 return MCDisassembler::Fail; 1823 break; 1824 default: 1825 break; 1826 } 1827 1828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1829 return MCDisassembler::Fail; 1830 1831 // On loads, the writeback operand comes after Rt. 1832 switch (Inst.getOpcode()) { 1833 case ARM::LDR_POST_IMM: 1834 case ARM::LDR_POST_REG: 1835 case ARM::LDRB_POST_IMM: 1836 case ARM::LDRB_POST_REG: 1837 case ARM::LDRBT_POST_REG: 1838 case ARM::LDRBT_POST_IMM: 1839 case ARM::LDRT_POST_REG: 1840 case ARM::LDRT_POST_IMM: 1841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1842 return MCDisassembler::Fail; 1843 break; 1844 default: 1845 break; 1846 } 1847 1848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1849 return MCDisassembler::Fail; 1850 1851 ARM_AM::AddrOpc Op = ARM_AM::add; 1852 if (!fieldFromInstruction(Insn, 23, 1)) 1853 Op = ARM_AM::sub; 1854 1855 bool writeback = (P == 0) || (W == 1); 1856 unsigned idx_mode = 0; 1857 if (P && writeback) 1858 idx_mode = ARMII::IndexModePre; 1859 else if (!P && writeback) 1860 idx_mode = ARMII::IndexModePost; 1861 1862 if (writeback && (Rn == 15 || Rn == Rt)) 1863 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1864 1865 if (reg) { 1866 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1867 return MCDisassembler::Fail; 1868 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1869 switch( fieldFromInstruction(Insn, 5, 2)) { 1870 case 0: 1871 Opc = ARM_AM::lsl; 1872 break; 1873 case 1: 1874 Opc = ARM_AM::lsr; 1875 break; 1876 case 2: 1877 Opc = ARM_AM::asr; 1878 break; 1879 case 3: 1880 Opc = ARM_AM::ror; 1881 break; 1882 default: 1883 return MCDisassembler::Fail; 1884 } 1885 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1886 if (Opc == ARM_AM::ror && amt == 0) 1887 Opc = ARM_AM::rrx; 1888 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1889 1890 Inst.addOperand(MCOperand::createImm(imm)); 1891 } else { 1892 Inst.addOperand(MCOperand::createReg(0)); 1893 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1894 Inst.addOperand(MCOperand::createImm(tmp)); 1895 } 1896 1897 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1898 return MCDisassembler::Fail; 1899 1900 return S; 1901 } 1902 1903 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1904 uint64_t Address, const void *Decoder) { 1905 DecodeStatus S = MCDisassembler::Success; 1906 1907 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1908 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1909 unsigned type = fieldFromInstruction(Val, 5, 2); 1910 unsigned imm = fieldFromInstruction(Val, 7, 5); 1911 unsigned U = fieldFromInstruction(Val, 12, 1); 1912 1913 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1914 switch (type) { 1915 case 0: 1916 ShOp = ARM_AM::lsl; 1917 break; 1918 case 1: 1919 ShOp = ARM_AM::lsr; 1920 break; 1921 case 2: 1922 ShOp = ARM_AM::asr; 1923 break; 1924 case 3: 1925 ShOp = ARM_AM::ror; 1926 break; 1927 } 1928 1929 if (ShOp == ARM_AM::ror && imm == 0) 1930 ShOp = ARM_AM::rrx; 1931 1932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1933 return MCDisassembler::Fail; 1934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1935 return MCDisassembler::Fail; 1936 unsigned shift; 1937 if (U) 1938 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1939 else 1940 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1941 Inst.addOperand(MCOperand::createImm(shift)); 1942 1943 return S; 1944 } 1945 1946 static DecodeStatus 1947 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1948 uint64_t Address, const void *Decoder) { 1949 DecodeStatus S = MCDisassembler::Success; 1950 1951 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1952 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1953 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1954 unsigned type = fieldFromInstruction(Insn, 22, 1); 1955 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1956 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1957 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1958 unsigned W = fieldFromInstruction(Insn, 21, 1); 1959 unsigned P = fieldFromInstruction(Insn, 24, 1); 1960 unsigned Rt2 = Rt + 1; 1961 1962 bool writeback = (W == 1) | (P == 0); 1963 1964 // For {LD,ST}RD, Rt must be even, else undefined. 1965 switch (Inst.getOpcode()) { 1966 case ARM::STRD: 1967 case ARM::STRD_PRE: 1968 case ARM::STRD_POST: 1969 case ARM::LDRD: 1970 case ARM::LDRD_PRE: 1971 case ARM::LDRD_POST: 1972 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1973 break; 1974 default: 1975 break; 1976 } 1977 switch (Inst.getOpcode()) { 1978 case ARM::STRD: 1979 case ARM::STRD_PRE: 1980 case ARM::STRD_POST: 1981 if (P == 0 && W == 1) 1982 S = MCDisassembler::SoftFail; 1983 1984 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1985 S = MCDisassembler::SoftFail; 1986 if (type && Rm == 15) 1987 S = MCDisassembler::SoftFail; 1988 if (Rt2 == 15) 1989 S = MCDisassembler::SoftFail; 1990 if (!type && fieldFromInstruction(Insn, 8, 4)) 1991 S = MCDisassembler::SoftFail; 1992 break; 1993 case ARM::STRH: 1994 case ARM::STRH_PRE: 1995 case ARM::STRH_POST: 1996 if (Rt == 15) 1997 S = MCDisassembler::SoftFail; 1998 if (writeback && (Rn == 15 || Rn == Rt)) 1999 S = MCDisassembler::SoftFail; 2000 if (!type && Rm == 15) 2001 S = MCDisassembler::SoftFail; 2002 break; 2003 case ARM::LDRD: 2004 case ARM::LDRD_PRE: 2005 case ARM::LDRD_POST: 2006 if (type && Rn == 15) { 2007 if (Rt2 == 15) 2008 S = MCDisassembler::SoftFail; 2009 break; 2010 } 2011 if (P == 0 && W == 1) 2012 S = MCDisassembler::SoftFail; 2013 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2014 S = MCDisassembler::SoftFail; 2015 if (!type && writeback && Rn == 15) 2016 S = MCDisassembler::SoftFail; 2017 if (writeback && (Rn == Rt || Rn == Rt2)) 2018 S = MCDisassembler::SoftFail; 2019 break; 2020 case ARM::LDRH: 2021 case ARM::LDRH_PRE: 2022 case ARM::LDRH_POST: 2023 if (type && Rn == 15) { 2024 if (Rt == 15) 2025 S = MCDisassembler::SoftFail; 2026 break; 2027 } 2028 if (Rt == 15) 2029 S = MCDisassembler::SoftFail; 2030 if (!type && Rm == 15) 2031 S = MCDisassembler::SoftFail; 2032 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2033 S = MCDisassembler::SoftFail; 2034 break; 2035 case ARM::LDRSH: 2036 case ARM::LDRSH_PRE: 2037 case ARM::LDRSH_POST: 2038 case ARM::LDRSB: 2039 case ARM::LDRSB_PRE: 2040 case ARM::LDRSB_POST: 2041 if (type && Rn == 15) { 2042 if (Rt == 15) 2043 S = MCDisassembler::SoftFail; 2044 break; 2045 } 2046 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2047 S = MCDisassembler::SoftFail; 2048 if (!type && (Rt == 15 || Rm == 15)) 2049 S = MCDisassembler::SoftFail; 2050 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2051 S = MCDisassembler::SoftFail; 2052 break; 2053 default: 2054 break; 2055 } 2056 2057 if (writeback) { // Writeback 2058 if (P) 2059 U |= ARMII::IndexModePre << 9; 2060 else 2061 U |= ARMII::IndexModePost << 9; 2062 2063 // On stores, the writeback operand precedes Rt. 2064 switch (Inst.getOpcode()) { 2065 case ARM::STRD: 2066 case ARM::STRD_PRE: 2067 case ARM::STRD_POST: 2068 case ARM::STRH: 2069 case ARM::STRH_PRE: 2070 case ARM::STRH_POST: 2071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2072 return MCDisassembler::Fail; 2073 break; 2074 default: 2075 break; 2076 } 2077 } 2078 2079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2080 return MCDisassembler::Fail; 2081 switch (Inst.getOpcode()) { 2082 case ARM::STRD: 2083 case ARM::STRD_PRE: 2084 case ARM::STRD_POST: 2085 case ARM::LDRD: 2086 case ARM::LDRD_PRE: 2087 case ARM::LDRD_POST: 2088 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2089 return MCDisassembler::Fail; 2090 break; 2091 default: 2092 break; 2093 } 2094 2095 if (writeback) { 2096 // On loads, the writeback operand comes after Rt. 2097 switch (Inst.getOpcode()) { 2098 case ARM::LDRD: 2099 case ARM::LDRD_PRE: 2100 case ARM::LDRD_POST: 2101 case ARM::LDRH: 2102 case ARM::LDRH_PRE: 2103 case ARM::LDRH_POST: 2104 case ARM::LDRSH: 2105 case ARM::LDRSH_PRE: 2106 case ARM::LDRSH_POST: 2107 case ARM::LDRSB: 2108 case ARM::LDRSB_PRE: 2109 case ARM::LDRSB_POST: 2110 case ARM::LDRHTr: 2111 case ARM::LDRSBTr: 2112 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2113 return MCDisassembler::Fail; 2114 break; 2115 default: 2116 break; 2117 } 2118 } 2119 2120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2121 return MCDisassembler::Fail; 2122 2123 if (type) { 2124 Inst.addOperand(MCOperand::createReg(0)); 2125 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2126 } else { 2127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2128 return MCDisassembler::Fail; 2129 Inst.addOperand(MCOperand::createImm(U)); 2130 } 2131 2132 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2133 return MCDisassembler::Fail; 2134 2135 return S; 2136 } 2137 2138 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2139 uint64_t Address, const void *Decoder) { 2140 DecodeStatus S = MCDisassembler::Success; 2141 2142 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2143 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2144 2145 switch (mode) { 2146 case 0: 2147 mode = ARM_AM::da; 2148 break; 2149 case 1: 2150 mode = ARM_AM::ia; 2151 break; 2152 case 2: 2153 mode = ARM_AM::db; 2154 break; 2155 case 3: 2156 mode = ARM_AM::ib; 2157 break; 2158 } 2159 2160 Inst.addOperand(MCOperand::createImm(mode)); 2161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2162 return MCDisassembler::Fail; 2163 2164 return S; 2165 } 2166 2167 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2168 uint64_t Address, const void *Decoder) { 2169 DecodeStatus S = MCDisassembler::Success; 2170 2171 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2172 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2173 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2174 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2175 2176 if (pred == 0xF) 2177 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2178 2179 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2180 return MCDisassembler::Fail; 2181 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2182 return MCDisassembler::Fail; 2183 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2184 return MCDisassembler::Fail; 2185 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2186 return MCDisassembler::Fail; 2187 return S; 2188 } 2189 2190 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2191 unsigned Insn, 2192 uint64_t Address, const void *Decoder) { 2193 DecodeStatus S = MCDisassembler::Success; 2194 2195 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2196 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2197 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2198 2199 if (pred == 0xF) { 2200 // Ambiguous with RFE and SRS 2201 switch (Inst.getOpcode()) { 2202 case ARM::LDMDA: 2203 Inst.setOpcode(ARM::RFEDA); 2204 break; 2205 case ARM::LDMDA_UPD: 2206 Inst.setOpcode(ARM::RFEDA_UPD); 2207 break; 2208 case ARM::LDMDB: 2209 Inst.setOpcode(ARM::RFEDB); 2210 break; 2211 case ARM::LDMDB_UPD: 2212 Inst.setOpcode(ARM::RFEDB_UPD); 2213 break; 2214 case ARM::LDMIA: 2215 Inst.setOpcode(ARM::RFEIA); 2216 break; 2217 case ARM::LDMIA_UPD: 2218 Inst.setOpcode(ARM::RFEIA_UPD); 2219 break; 2220 case ARM::LDMIB: 2221 Inst.setOpcode(ARM::RFEIB); 2222 break; 2223 case ARM::LDMIB_UPD: 2224 Inst.setOpcode(ARM::RFEIB_UPD); 2225 break; 2226 case ARM::STMDA: 2227 Inst.setOpcode(ARM::SRSDA); 2228 break; 2229 case ARM::STMDA_UPD: 2230 Inst.setOpcode(ARM::SRSDA_UPD); 2231 break; 2232 case ARM::STMDB: 2233 Inst.setOpcode(ARM::SRSDB); 2234 break; 2235 case ARM::STMDB_UPD: 2236 Inst.setOpcode(ARM::SRSDB_UPD); 2237 break; 2238 case ARM::STMIA: 2239 Inst.setOpcode(ARM::SRSIA); 2240 break; 2241 case ARM::STMIA_UPD: 2242 Inst.setOpcode(ARM::SRSIA_UPD); 2243 break; 2244 case ARM::STMIB: 2245 Inst.setOpcode(ARM::SRSIB); 2246 break; 2247 case ARM::STMIB_UPD: 2248 Inst.setOpcode(ARM::SRSIB_UPD); 2249 break; 2250 default: 2251 return MCDisassembler::Fail; 2252 } 2253 2254 // For stores (which become SRS's, the only operand is the mode. 2255 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2256 // Check SRS encoding constraints 2257 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2258 fieldFromInstruction(Insn, 20, 1) == 0)) 2259 return MCDisassembler::Fail; 2260 2261 Inst.addOperand( 2262 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2263 return S; 2264 } 2265 2266 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2267 } 2268 2269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2270 return MCDisassembler::Fail; 2271 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2272 return MCDisassembler::Fail; // Tied 2273 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2274 return MCDisassembler::Fail; 2275 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2276 return MCDisassembler::Fail; 2277 2278 return S; 2279 } 2280 2281 // Check for UNPREDICTABLE predicated ESB instruction 2282 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2283 uint64_t Address, const void *Decoder) { 2284 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2285 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2286 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2287 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2288 2289 DecodeStatus S = MCDisassembler::Success; 2290 2291 Inst.addOperand(MCOperand::createImm(imm8)); 2292 2293 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2294 return MCDisassembler::Fail; 2295 2296 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2297 // so all predicates should be allowed. 2298 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2299 S = MCDisassembler::SoftFail; 2300 2301 return S; 2302 } 2303 2304 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2305 uint64_t Address, const void *Decoder) { 2306 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2307 unsigned M = fieldFromInstruction(Insn, 17, 1); 2308 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2309 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2310 2311 DecodeStatus S = MCDisassembler::Success; 2312 2313 // This decoder is called from multiple location that do not check 2314 // the full encoding is valid before they do. 2315 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2316 fieldFromInstruction(Insn, 16, 1) != 0 || 2317 fieldFromInstruction(Insn, 20, 8) != 0x10) 2318 return MCDisassembler::Fail; 2319 2320 // imod == '01' --> UNPREDICTABLE 2321 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2322 // return failure here. The '01' imod value is unprintable, so there's 2323 // nothing useful we could do even if we returned UNPREDICTABLE. 2324 2325 if (imod == 1) return MCDisassembler::Fail; 2326 2327 if (imod && M) { 2328 Inst.setOpcode(ARM::CPS3p); 2329 Inst.addOperand(MCOperand::createImm(imod)); 2330 Inst.addOperand(MCOperand::createImm(iflags)); 2331 Inst.addOperand(MCOperand::createImm(mode)); 2332 } else if (imod && !M) { 2333 Inst.setOpcode(ARM::CPS2p); 2334 Inst.addOperand(MCOperand::createImm(imod)); 2335 Inst.addOperand(MCOperand::createImm(iflags)); 2336 if (mode) S = MCDisassembler::SoftFail; 2337 } else if (!imod && M) { 2338 Inst.setOpcode(ARM::CPS1p); 2339 Inst.addOperand(MCOperand::createImm(mode)); 2340 if (iflags) S = MCDisassembler::SoftFail; 2341 } else { 2342 // imod == '00' && M == '0' --> UNPREDICTABLE 2343 Inst.setOpcode(ARM::CPS1p); 2344 Inst.addOperand(MCOperand::createImm(mode)); 2345 S = MCDisassembler::SoftFail; 2346 } 2347 2348 return S; 2349 } 2350 2351 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2352 uint64_t Address, const void *Decoder) { 2353 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2354 unsigned M = fieldFromInstruction(Insn, 8, 1); 2355 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2356 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2357 2358 DecodeStatus S = MCDisassembler::Success; 2359 2360 // imod == '01' --> UNPREDICTABLE 2361 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2362 // return failure here. The '01' imod value is unprintable, so there's 2363 // nothing useful we could do even if we returned UNPREDICTABLE. 2364 2365 if (imod == 1) return MCDisassembler::Fail; 2366 2367 if (imod && M) { 2368 Inst.setOpcode(ARM::t2CPS3p); 2369 Inst.addOperand(MCOperand::createImm(imod)); 2370 Inst.addOperand(MCOperand::createImm(iflags)); 2371 Inst.addOperand(MCOperand::createImm(mode)); 2372 } else if (imod && !M) { 2373 Inst.setOpcode(ARM::t2CPS2p); 2374 Inst.addOperand(MCOperand::createImm(imod)); 2375 Inst.addOperand(MCOperand::createImm(iflags)); 2376 if (mode) S = MCDisassembler::SoftFail; 2377 } else if (!imod && M) { 2378 Inst.setOpcode(ARM::t2CPS1p); 2379 Inst.addOperand(MCOperand::createImm(mode)); 2380 if (iflags) S = MCDisassembler::SoftFail; 2381 } else { 2382 // imod == '00' && M == '0' --> this is a HINT instruction 2383 int imm = fieldFromInstruction(Insn, 0, 8); 2384 // HINT are defined only for immediate in [0..4] 2385 if(imm > 4) return MCDisassembler::Fail; 2386 Inst.setOpcode(ARM::t2HINT); 2387 Inst.addOperand(MCOperand::createImm(imm)); 2388 } 2389 2390 return S; 2391 } 2392 2393 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2394 uint64_t Address, const void *Decoder) { 2395 DecodeStatus S = MCDisassembler::Success; 2396 2397 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2398 unsigned imm = 0; 2399 2400 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2401 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2402 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2403 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2404 2405 if (Inst.getOpcode() == ARM::t2MOVTi16) 2406 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2407 return MCDisassembler::Fail; 2408 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2409 return MCDisassembler::Fail; 2410 2411 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2412 Inst.addOperand(MCOperand::createImm(imm)); 2413 2414 return S; 2415 } 2416 2417 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2418 uint64_t Address, const void *Decoder) { 2419 DecodeStatus S = MCDisassembler::Success; 2420 2421 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2422 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2423 unsigned imm = 0; 2424 2425 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2426 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2427 2428 if (Inst.getOpcode() == ARM::MOVTi16) 2429 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2430 return MCDisassembler::Fail; 2431 2432 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2433 return MCDisassembler::Fail; 2434 2435 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2436 Inst.addOperand(MCOperand::createImm(imm)); 2437 2438 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2439 return MCDisassembler::Fail; 2440 2441 return S; 2442 } 2443 2444 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2445 uint64_t Address, const void *Decoder) { 2446 DecodeStatus S = MCDisassembler::Success; 2447 2448 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2449 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2450 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2451 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2452 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2453 2454 if (pred == 0xF) 2455 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2456 2457 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2458 return MCDisassembler::Fail; 2459 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2460 return MCDisassembler::Fail; 2461 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2462 return MCDisassembler::Fail; 2463 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2464 return MCDisassembler::Fail; 2465 2466 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2467 return MCDisassembler::Fail; 2468 2469 return S; 2470 } 2471 2472 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2473 uint64_t Address, const void *Decoder) { 2474 DecodeStatus S = MCDisassembler::Success; 2475 2476 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2477 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2478 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2479 2480 if (Pred == 0xF) 2481 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2482 2483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2484 return MCDisassembler::Fail; 2485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2486 return MCDisassembler::Fail; 2487 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2488 return MCDisassembler::Fail; 2489 2490 return S; 2491 } 2492 2493 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2494 uint64_t Address, const void *Decoder) { 2495 DecodeStatus S = MCDisassembler::Success; 2496 2497 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2498 2499 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2500 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2501 2502 if (!FeatureBits[ARM::HasV8_1aOps] || 2503 !FeatureBits[ARM::HasV8Ops]) 2504 return MCDisassembler::Fail; 2505 2506 // Decoder can be called from DecodeTST, which does not check the full 2507 // encoding is valid. 2508 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2509 fieldFromInstruction(Insn, 4,4) != 0) 2510 return MCDisassembler::Fail; 2511 if (fieldFromInstruction(Insn, 10,10) != 0 || 2512 fieldFromInstruction(Insn, 0,4) != 0) 2513 S = MCDisassembler::SoftFail; 2514 2515 Inst.setOpcode(ARM::SETPAN); 2516 Inst.addOperand(MCOperand::createImm(Imm)); 2517 2518 return S; 2519 } 2520 2521 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2522 uint64_t Address, const void *Decoder) { 2523 DecodeStatus S = MCDisassembler::Success; 2524 2525 unsigned add = fieldFromInstruction(Val, 12, 1); 2526 unsigned imm = fieldFromInstruction(Val, 0, 12); 2527 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2528 2529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2530 return MCDisassembler::Fail; 2531 2532 if (!add) imm *= -1; 2533 if (imm == 0 && !add) imm = INT32_MIN; 2534 Inst.addOperand(MCOperand::createImm(imm)); 2535 if (Rn == 15) 2536 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2537 2538 return S; 2539 } 2540 2541 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2542 uint64_t Address, const void *Decoder) { 2543 DecodeStatus S = MCDisassembler::Success; 2544 2545 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2546 // U == 1 to add imm, 0 to subtract it. 2547 unsigned U = fieldFromInstruction(Val, 8, 1); 2548 unsigned imm = fieldFromInstruction(Val, 0, 8); 2549 2550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2551 return MCDisassembler::Fail; 2552 2553 if (U) 2554 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2555 else 2556 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2557 2558 return S; 2559 } 2560 2561 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2562 uint64_t Address, const void *Decoder) { 2563 DecodeStatus S = MCDisassembler::Success; 2564 2565 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2566 // U == 1 to add imm, 0 to subtract it. 2567 unsigned U = fieldFromInstruction(Val, 8, 1); 2568 unsigned imm = fieldFromInstruction(Val, 0, 8); 2569 2570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2571 return MCDisassembler::Fail; 2572 2573 if (U) 2574 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2575 else 2576 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2577 2578 return S; 2579 } 2580 2581 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2582 uint64_t Address, const void *Decoder) { 2583 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2584 } 2585 2586 static DecodeStatus 2587 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2588 uint64_t Address, const void *Decoder) { 2589 DecodeStatus Status = MCDisassembler::Success; 2590 2591 // Note the J1 and J2 values are from the encoded instruction. So here 2592 // change them to I1 and I2 values via as documented: 2593 // I1 = NOT(J1 EOR S); 2594 // I2 = NOT(J2 EOR S); 2595 // and build the imm32 with one trailing zero as documented: 2596 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2597 unsigned S = fieldFromInstruction(Insn, 26, 1); 2598 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2599 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2600 unsigned I1 = !(J1 ^ S); 2601 unsigned I2 = !(J2 ^ S); 2602 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2603 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2604 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2605 int imm32 = SignExtend32<25>(tmp << 1); 2606 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2607 true, 4, Inst, Decoder)) 2608 Inst.addOperand(MCOperand::createImm(imm32)); 2609 2610 return Status; 2611 } 2612 2613 static DecodeStatus 2614 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2615 uint64_t Address, const void *Decoder) { 2616 DecodeStatus S = MCDisassembler::Success; 2617 2618 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2619 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2620 2621 if (pred == 0xF) { 2622 Inst.setOpcode(ARM::BLXi); 2623 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2624 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2625 true, 4, Inst, Decoder)) 2626 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2627 return S; 2628 } 2629 2630 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2631 true, 4, Inst, Decoder)) 2632 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2633 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2634 return MCDisassembler::Fail; 2635 2636 return S; 2637 } 2638 2639 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2640 uint64_t Address, const void *Decoder) { 2641 DecodeStatus S = MCDisassembler::Success; 2642 2643 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2644 unsigned align = fieldFromInstruction(Val, 4, 2); 2645 2646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2647 return MCDisassembler::Fail; 2648 if (!align) 2649 Inst.addOperand(MCOperand::createImm(0)); 2650 else 2651 Inst.addOperand(MCOperand::createImm(4 << align)); 2652 2653 return S; 2654 } 2655 2656 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2657 uint64_t Address, const void *Decoder) { 2658 DecodeStatus S = MCDisassembler::Success; 2659 2660 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2661 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2662 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2663 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2664 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2665 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2666 2667 // First output register 2668 switch (Inst.getOpcode()) { 2669 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2670 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2671 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2672 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2673 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2674 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2675 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2676 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2677 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2678 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2679 return MCDisassembler::Fail; 2680 break; 2681 case ARM::VLD2b16: 2682 case ARM::VLD2b32: 2683 case ARM::VLD2b8: 2684 case ARM::VLD2b16wb_fixed: 2685 case ARM::VLD2b16wb_register: 2686 case ARM::VLD2b32wb_fixed: 2687 case ARM::VLD2b32wb_register: 2688 case ARM::VLD2b8wb_fixed: 2689 case ARM::VLD2b8wb_register: 2690 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2691 return MCDisassembler::Fail; 2692 break; 2693 default: 2694 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2695 return MCDisassembler::Fail; 2696 } 2697 2698 // Second output register 2699 switch (Inst.getOpcode()) { 2700 case ARM::VLD3d8: 2701 case ARM::VLD3d16: 2702 case ARM::VLD3d32: 2703 case ARM::VLD3d8_UPD: 2704 case ARM::VLD3d16_UPD: 2705 case ARM::VLD3d32_UPD: 2706 case ARM::VLD4d8: 2707 case ARM::VLD4d16: 2708 case ARM::VLD4d32: 2709 case ARM::VLD4d8_UPD: 2710 case ARM::VLD4d16_UPD: 2711 case ARM::VLD4d32_UPD: 2712 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2713 return MCDisassembler::Fail; 2714 break; 2715 case ARM::VLD3q8: 2716 case ARM::VLD3q16: 2717 case ARM::VLD3q32: 2718 case ARM::VLD3q8_UPD: 2719 case ARM::VLD3q16_UPD: 2720 case ARM::VLD3q32_UPD: 2721 case ARM::VLD4q8: 2722 case ARM::VLD4q16: 2723 case ARM::VLD4q32: 2724 case ARM::VLD4q8_UPD: 2725 case ARM::VLD4q16_UPD: 2726 case ARM::VLD4q32_UPD: 2727 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2728 return MCDisassembler::Fail; 2729 break; 2730 default: 2731 break; 2732 } 2733 2734 // Third output register 2735 switch(Inst.getOpcode()) { 2736 case ARM::VLD3d8: 2737 case ARM::VLD3d16: 2738 case ARM::VLD3d32: 2739 case ARM::VLD3d8_UPD: 2740 case ARM::VLD3d16_UPD: 2741 case ARM::VLD3d32_UPD: 2742 case ARM::VLD4d8: 2743 case ARM::VLD4d16: 2744 case ARM::VLD4d32: 2745 case ARM::VLD4d8_UPD: 2746 case ARM::VLD4d16_UPD: 2747 case ARM::VLD4d32_UPD: 2748 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 break; 2751 case ARM::VLD3q8: 2752 case ARM::VLD3q16: 2753 case ARM::VLD3q32: 2754 case ARM::VLD3q8_UPD: 2755 case ARM::VLD3q16_UPD: 2756 case ARM::VLD3q32_UPD: 2757 case ARM::VLD4q8: 2758 case ARM::VLD4q16: 2759 case ARM::VLD4q32: 2760 case ARM::VLD4q8_UPD: 2761 case ARM::VLD4q16_UPD: 2762 case ARM::VLD4q32_UPD: 2763 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2764 return MCDisassembler::Fail; 2765 break; 2766 default: 2767 break; 2768 } 2769 2770 // Fourth output register 2771 switch (Inst.getOpcode()) { 2772 case ARM::VLD4d8: 2773 case ARM::VLD4d16: 2774 case ARM::VLD4d32: 2775 case ARM::VLD4d8_UPD: 2776 case ARM::VLD4d16_UPD: 2777 case ARM::VLD4d32_UPD: 2778 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2779 return MCDisassembler::Fail; 2780 break; 2781 case ARM::VLD4q8: 2782 case ARM::VLD4q16: 2783 case ARM::VLD4q32: 2784 case ARM::VLD4q8_UPD: 2785 case ARM::VLD4q16_UPD: 2786 case ARM::VLD4q32_UPD: 2787 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2788 return MCDisassembler::Fail; 2789 break; 2790 default: 2791 break; 2792 } 2793 2794 // Writeback operand 2795 switch (Inst.getOpcode()) { 2796 case ARM::VLD1d8wb_fixed: 2797 case ARM::VLD1d16wb_fixed: 2798 case ARM::VLD1d32wb_fixed: 2799 case ARM::VLD1d64wb_fixed: 2800 case ARM::VLD1d8wb_register: 2801 case ARM::VLD1d16wb_register: 2802 case ARM::VLD1d32wb_register: 2803 case ARM::VLD1d64wb_register: 2804 case ARM::VLD1q8wb_fixed: 2805 case ARM::VLD1q16wb_fixed: 2806 case ARM::VLD1q32wb_fixed: 2807 case ARM::VLD1q64wb_fixed: 2808 case ARM::VLD1q8wb_register: 2809 case ARM::VLD1q16wb_register: 2810 case ARM::VLD1q32wb_register: 2811 case ARM::VLD1q64wb_register: 2812 case ARM::VLD1d8Twb_fixed: 2813 case ARM::VLD1d8Twb_register: 2814 case ARM::VLD1d16Twb_fixed: 2815 case ARM::VLD1d16Twb_register: 2816 case ARM::VLD1d32Twb_fixed: 2817 case ARM::VLD1d32Twb_register: 2818 case ARM::VLD1d64Twb_fixed: 2819 case ARM::VLD1d64Twb_register: 2820 case ARM::VLD1d8Qwb_fixed: 2821 case ARM::VLD1d8Qwb_register: 2822 case ARM::VLD1d16Qwb_fixed: 2823 case ARM::VLD1d16Qwb_register: 2824 case ARM::VLD1d32Qwb_fixed: 2825 case ARM::VLD1d32Qwb_register: 2826 case ARM::VLD1d64Qwb_fixed: 2827 case ARM::VLD1d64Qwb_register: 2828 case ARM::VLD2d8wb_fixed: 2829 case ARM::VLD2d16wb_fixed: 2830 case ARM::VLD2d32wb_fixed: 2831 case ARM::VLD2q8wb_fixed: 2832 case ARM::VLD2q16wb_fixed: 2833 case ARM::VLD2q32wb_fixed: 2834 case ARM::VLD2d8wb_register: 2835 case ARM::VLD2d16wb_register: 2836 case ARM::VLD2d32wb_register: 2837 case ARM::VLD2q8wb_register: 2838 case ARM::VLD2q16wb_register: 2839 case ARM::VLD2q32wb_register: 2840 case ARM::VLD2b8wb_fixed: 2841 case ARM::VLD2b16wb_fixed: 2842 case ARM::VLD2b32wb_fixed: 2843 case ARM::VLD2b8wb_register: 2844 case ARM::VLD2b16wb_register: 2845 case ARM::VLD2b32wb_register: 2846 Inst.addOperand(MCOperand::createImm(0)); 2847 break; 2848 case ARM::VLD3d8_UPD: 2849 case ARM::VLD3d16_UPD: 2850 case ARM::VLD3d32_UPD: 2851 case ARM::VLD3q8_UPD: 2852 case ARM::VLD3q16_UPD: 2853 case ARM::VLD3q32_UPD: 2854 case ARM::VLD4d8_UPD: 2855 case ARM::VLD4d16_UPD: 2856 case ARM::VLD4d32_UPD: 2857 case ARM::VLD4q8_UPD: 2858 case ARM::VLD4q16_UPD: 2859 case ARM::VLD4q32_UPD: 2860 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2861 return MCDisassembler::Fail; 2862 break; 2863 default: 2864 break; 2865 } 2866 2867 // AddrMode6 Base (register+alignment) 2868 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2869 return MCDisassembler::Fail; 2870 2871 // AddrMode6 Offset (register) 2872 switch (Inst.getOpcode()) { 2873 default: 2874 // The below have been updated to have explicit am6offset split 2875 // between fixed and register offset. For those instructions not 2876 // yet updated, we need to add an additional reg0 operand for the 2877 // fixed variant. 2878 // 2879 // The fixed offset encodes as Rm == 0xd, so we check for that. 2880 if (Rm == 0xd) { 2881 Inst.addOperand(MCOperand::createReg(0)); 2882 break; 2883 } 2884 // Fall through to handle the register offset variant. 2885 LLVM_FALLTHROUGH; 2886 case ARM::VLD1d8wb_fixed: 2887 case ARM::VLD1d16wb_fixed: 2888 case ARM::VLD1d32wb_fixed: 2889 case ARM::VLD1d64wb_fixed: 2890 case ARM::VLD1d8Twb_fixed: 2891 case ARM::VLD1d16Twb_fixed: 2892 case ARM::VLD1d32Twb_fixed: 2893 case ARM::VLD1d64Twb_fixed: 2894 case ARM::VLD1d8Qwb_fixed: 2895 case ARM::VLD1d16Qwb_fixed: 2896 case ARM::VLD1d32Qwb_fixed: 2897 case ARM::VLD1d64Qwb_fixed: 2898 case ARM::VLD1d8wb_register: 2899 case ARM::VLD1d16wb_register: 2900 case ARM::VLD1d32wb_register: 2901 case ARM::VLD1d64wb_register: 2902 case ARM::VLD1q8wb_fixed: 2903 case ARM::VLD1q16wb_fixed: 2904 case ARM::VLD1q32wb_fixed: 2905 case ARM::VLD1q64wb_fixed: 2906 case ARM::VLD1q8wb_register: 2907 case ARM::VLD1q16wb_register: 2908 case ARM::VLD1q32wb_register: 2909 case ARM::VLD1q64wb_register: 2910 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2911 // variant encodes Rm == 0xf. Anything else is a register offset post- 2912 // increment and we need to add the register operand to the instruction. 2913 if (Rm != 0xD && Rm != 0xF && 2914 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2915 return MCDisassembler::Fail; 2916 break; 2917 case ARM::VLD2d8wb_fixed: 2918 case ARM::VLD2d16wb_fixed: 2919 case ARM::VLD2d32wb_fixed: 2920 case ARM::VLD2b8wb_fixed: 2921 case ARM::VLD2b16wb_fixed: 2922 case ARM::VLD2b32wb_fixed: 2923 case ARM::VLD2q8wb_fixed: 2924 case ARM::VLD2q16wb_fixed: 2925 case ARM::VLD2q32wb_fixed: 2926 break; 2927 } 2928 2929 return S; 2930 } 2931 2932 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2933 uint64_t Address, const void *Decoder) { 2934 unsigned type = fieldFromInstruction(Insn, 8, 4); 2935 unsigned align = fieldFromInstruction(Insn, 4, 2); 2936 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2937 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2938 if (type == 10 && align == 3) return MCDisassembler::Fail; 2939 2940 unsigned load = fieldFromInstruction(Insn, 21, 1); 2941 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2942 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2943 } 2944 2945 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2946 uint64_t Address, const void *Decoder) { 2947 unsigned size = fieldFromInstruction(Insn, 6, 2); 2948 if (size == 3) return MCDisassembler::Fail; 2949 2950 unsigned type = fieldFromInstruction(Insn, 8, 4); 2951 unsigned align = fieldFromInstruction(Insn, 4, 2); 2952 if (type == 8 && align == 3) return MCDisassembler::Fail; 2953 if (type == 9 && align == 3) return MCDisassembler::Fail; 2954 2955 unsigned load = fieldFromInstruction(Insn, 21, 1); 2956 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2957 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2958 } 2959 2960 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2961 uint64_t Address, const void *Decoder) { 2962 unsigned size = fieldFromInstruction(Insn, 6, 2); 2963 if (size == 3) return MCDisassembler::Fail; 2964 2965 unsigned align = fieldFromInstruction(Insn, 4, 2); 2966 if (align & 2) return MCDisassembler::Fail; 2967 2968 unsigned load = fieldFromInstruction(Insn, 21, 1); 2969 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2970 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2971 } 2972 2973 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2974 uint64_t Address, const void *Decoder) { 2975 unsigned size = fieldFromInstruction(Insn, 6, 2); 2976 if (size == 3) return MCDisassembler::Fail; 2977 2978 unsigned load = fieldFromInstruction(Insn, 21, 1); 2979 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2980 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2981 } 2982 2983 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2984 uint64_t Address, const void *Decoder) { 2985 DecodeStatus S = MCDisassembler::Success; 2986 2987 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2988 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2989 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2990 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2991 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2992 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2993 2994 // Writeback Operand 2995 switch (Inst.getOpcode()) { 2996 case ARM::VST1d8wb_fixed: 2997 case ARM::VST1d16wb_fixed: 2998 case ARM::VST1d32wb_fixed: 2999 case ARM::VST1d64wb_fixed: 3000 case ARM::VST1d8wb_register: 3001 case ARM::VST1d16wb_register: 3002 case ARM::VST1d32wb_register: 3003 case ARM::VST1d64wb_register: 3004 case ARM::VST1q8wb_fixed: 3005 case ARM::VST1q16wb_fixed: 3006 case ARM::VST1q32wb_fixed: 3007 case ARM::VST1q64wb_fixed: 3008 case ARM::VST1q8wb_register: 3009 case ARM::VST1q16wb_register: 3010 case ARM::VST1q32wb_register: 3011 case ARM::VST1q64wb_register: 3012 case ARM::VST1d8Twb_fixed: 3013 case ARM::VST1d16Twb_fixed: 3014 case ARM::VST1d32Twb_fixed: 3015 case ARM::VST1d64Twb_fixed: 3016 case ARM::VST1d8Twb_register: 3017 case ARM::VST1d16Twb_register: 3018 case ARM::VST1d32Twb_register: 3019 case ARM::VST1d64Twb_register: 3020 case ARM::VST1d8Qwb_fixed: 3021 case ARM::VST1d16Qwb_fixed: 3022 case ARM::VST1d32Qwb_fixed: 3023 case ARM::VST1d64Qwb_fixed: 3024 case ARM::VST1d8Qwb_register: 3025 case ARM::VST1d16Qwb_register: 3026 case ARM::VST1d32Qwb_register: 3027 case ARM::VST1d64Qwb_register: 3028 case ARM::VST2d8wb_fixed: 3029 case ARM::VST2d16wb_fixed: 3030 case ARM::VST2d32wb_fixed: 3031 case ARM::VST2d8wb_register: 3032 case ARM::VST2d16wb_register: 3033 case ARM::VST2d32wb_register: 3034 case ARM::VST2q8wb_fixed: 3035 case ARM::VST2q16wb_fixed: 3036 case ARM::VST2q32wb_fixed: 3037 case ARM::VST2q8wb_register: 3038 case ARM::VST2q16wb_register: 3039 case ARM::VST2q32wb_register: 3040 case ARM::VST2b8wb_fixed: 3041 case ARM::VST2b16wb_fixed: 3042 case ARM::VST2b32wb_fixed: 3043 case ARM::VST2b8wb_register: 3044 case ARM::VST2b16wb_register: 3045 case ARM::VST2b32wb_register: 3046 if (Rm == 0xF) 3047 return MCDisassembler::Fail; 3048 Inst.addOperand(MCOperand::createImm(0)); 3049 break; 3050 case ARM::VST3d8_UPD: 3051 case ARM::VST3d16_UPD: 3052 case ARM::VST3d32_UPD: 3053 case ARM::VST3q8_UPD: 3054 case ARM::VST3q16_UPD: 3055 case ARM::VST3q32_UPD: 3056 case ARM::VST4d8_UPD: 3057 case ARM::VST4d16_UPD: 3058 case ARM::VST4d32_UPD: 3059 case ARM::VST4q8_UPD: 3060 case ARM::VST4q16_UPD: 3061 case ARM::VST4q32_UPD: 3062 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3063 return MCDisassembler::Fail; 3064 break; 3065 default: 3066 break; 3067 } 3068 3069 // AddrMode6 Base (register+alignment) 3070 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3071 return MCDisassembler::Fail; 3072 3073 // AddrMode6 Offset (register) 3074 switch (Inst.getOpcode()) { 3075 default: 3076 if (Rm == 0xD) 3077 Inst.addOperand(MCOperand::createReg(0)); 3078 else if (Rm != 0xF) { 3079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3080 return MCDisassembler::Fail; 3081 } 3082 break; 3083 case ARM::VST1d8wb_fixed: 3084 case ARM::VST1d16wb_fixed: 3085 case ARM::VST1d32wb_fixed: 3086 case ARM::VST1d64wb_fixed: 3087 case ARM::VST1q8wb_fixed: 3088 case ARM::VST1q16wb_fixed: 3089 case ARM::VST1q32wb_fixed: 3090 case ARM::VST1q64wb_fixed: 3091 case ARM::VST1d8Twb_fixed: 3092 case ARM::VST1d16Twb_fixed: 3093 case ARM::VST1d32Twb_fixed: 3094 case ARM::VST1d64Twb_fixed: 3095 case ARM::VST1d8Qwb_fixed: 3096 case ARM::VST1d16Qwb_fixed: 3097 case ARM::VST1d32Qwb_fixed: 3098 case ARM::VST1d64Qwb_fixed: 3099 case ARM::VST2d8wb_fixed: 3100 case ARM::VST2d16wb_fixed: 3101 case ARM::VST2d32wb_fixed: 3102 case ARM::VST2q8wb_fixed: 3103 case ARM::VST2q16wb_fixed: 3104 case ARM::VST2q32wb_fixed: 3105 case ARM::VST2b8wb_fixed: 3106 case ARM::VST2b16wb_fixed: 3107 case ARM::VST2b32wb_fixed: 3108 break; 3109 } 3110 3111 // First input register 3112 switch (Inst.getOpcode()) { 3113 case ARM::VST1q16: 3114 case ARM::VST1q32: 3115 case ARM::VST1q64: 3116 case ARM::VST1q8: 3117 case ARM::VST1q16wb_fixed: 3118 case ARM::VST1q16wb_register: 3119 case ARM::VST1q32wb_fixed: 3120 case ARM::VST1q32wb_register: 3121 case ARM::VST1q64wb_fixed: 3122 case ARM::VST1q64wb_register: 3123 case ARM::VST1q8wb_fixed: 3124 case ARM::VST1q8wb_register: 3125 case ARM::VST2d16: 3126 case ARM::VST2d32: 3127 case ARM::VST2d8: 3128 case ARM::VST2d16wb_fixed: 3129 case ARM::VST2d16wb_register: 3130 case ARM::VST2d32wb_fixed: 3131 case ARM::VST2d32wb_register: 3132 case ARM::VST2d8wb_fixed: 3133 case ARM::VST2d8wb_register: 3134 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3135 return MCDisassembler::Fail; 3136 break; 3137 case ARM::VST2b16: 3138 case ARM::VST2b32: 3139 case ARM::VST2b8: 3140 case ARM::VST2b16wb_fixed: 3141 case ARM::VST2b16wb_register: 3142 case ARM::VST2b32wb_fixed: 3143 case ARM::VST2b32wb_register: 3144 case ARM::VST2b8wb_fixed: 3145 case ARM::VST2b8wb_register: 3146 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3147 return MCDisassembler::Fail; 3148 break; 3149 default: 3150 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3151 return MCDisassembler::Fail; 3152 } 3153 3154 // Second input register 3155 switch (Inst.getOpcode()) { 3156 case ARM::VST3d8: 3157 case ARM::VST3d16: 3158 case ARM::VST3d32: 3159 case ARM::VST3d8_UPD: 3160 case ARM::VST3d16_UPD: 3161 case ARM::VST3d32_UPD: 3162 case ARM::VST4d8: 3163 case ARM::VST4d16: 3164 case ARM::VST4d32: 3165 case ARM::VST4d8_UPD: 3166 case ARM::VST4d16_UPD: 3167 case ARM::VST4d32_UPD: 3168 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3169 return MCDisassembler::Fail; 3170 break; 3171 case ARM::VST3q8: 3172 case ARM::VST3q16: 3173 case ARM::VST3q32: 3174 case ARM::VST3q8_UPD: 3175 case ARM::VST3q16_UPD: 3176 case ARM::VST3q32_UPD: 3177 case ARM::VST4q8: 3178 case ARM::VST4q16: 3179 case ARM::VST4q32: 3180 case ARM::VST4q8_UPD: 3181 case ARM::VST4q16_UPD: 3182 case ARM::VST4q32_UPD: 3183 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3184 return MCDisassembler::Fail; 3185 break; 3186 default: 3187 break; 3188 } 3189 3190 // Third input register 3191 switch (Inst.getOpcode()) { 3192 case ARM::VST3d8: 3193 case ARM::VST3d16: 3194 case ARM::VST3d32: 3195 case ARM::VST3d8_UPD: 3196 case ARM::VST3d16_UPD: 3197 case ARM::VST3d32_UPD: 3198 case ARM::VST4d8: 3199 case ARM::VST4d16: 3200 case ARM::VST4d32: 3201 case ARM::VST4d8_UPD: 3202 case ARM::VST4d16_UPD: 3203 case ARM::VST4d32_UPD: 3204 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3205 return MCDisassembler::Fail; 3206 break; 3207 case ARM::VST3q8: 3208 case ARM::VST3q16: 3209 case ARM::VST3q32: 3210 case ARM::VST3q8_UPD: 3211 case ARM::VST3q16_UPD: 3212 case ARM::VST3q32_UPD: 3213 case ARM::VST4q8: 3214 case ARM::VST4q16: 3215 case ARM::VST4q32: 3216 case ARM::VST4q8_UPD: 3217 case ARM::VST4q16_UPD: 3218 case ARM::VST4q32_UPD: 3219 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3220 return MCDisassembler::Fail; 3221 break; 3222 default: 3223 break; 3224 } 3225 3226 // Fourth input register 3227 switch (Inst.getOpcode()) { 3228 case ARM::VST4d8: 3229 case ARM::VST4d16: 3230 case ARM::VST4d32: 3231 case ARM::VST4d8_UPD: 3232 case ARM::VST4d16_UPD: 3233 case ARM::VST4d32_UPD: 3234 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3235 return MCDisassembler::Fail; 3236 break; 3237 case ARM::VST4q8: 3238 case ARM::VST4q16: 3239 case ARM::VST4q32: 3240 case ARM::VST4q8_UPD: 3241 case ARM::VST4q16_UPD: 3242 case ARM::VST4q32_UPD: 3243 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3244 return MCDisassembler::Fail; 3245 break; 3246 default: 3247 break; 3248 } 3249 3250 return S; 3251 } 3252 3253 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3254 uint64_t Address, const void *Decoder) { 3255 DecodeStatus S = MCDisassembler::Success; 3256 3257 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3258 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3259 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3260 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3261 unsigned align = fieldFromInstruction(Insn, 4, 1); 3262 unsigned size = fieldFromInstruction(Insn, 6, 2); 3263 3264 if (size == 0 && align == 1) 3265 return MCDisassembler::Fail; 3266 align *= (1 << size); 3267 3268 switch (Inst.getOpcode()) { 3269 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3270 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3271 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3272 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3273 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3274 return MCDisassembler::Fail; 3275 break; 3276 default: 3277 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3278 return MCDisassembler::Fail; 3279 break; 3280 } 3281 if (Rm != 0xF) { 3282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3283 return MCDisassembler::Fail; 3284 } 3285 3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3287 return MCDisassembler::Fail; 3288 Inst.addOperand(MCOperand::createImm(align)); 3289 3290 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3291 // variant encodes Rm == 0xf. Anything else is a register offset post- 3292 // increment and we need to add the register operand to the instruction. 3293 if (Rm != 0xD && Rm != 0xF && 3294 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3295 return MCDisassembler::Fail; 3296 3297 return S; 3298 } 3299 3300 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3301 uint64_t Address, const void *Decoder) { 3302 DecodeStatus S = MCDisassembler::Success; 3303 3304 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3305 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3306 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3307 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3308 unsigned align = fieldFromInstruction(Insn, 4, 1); 3309 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3310 align *= 2*size; 3311 3312 switch (Inst.getOpcode()) { 3313 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3314 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3315 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3316 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3317 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3318 return MCDisassembler::Fail; 3319 break; 3320 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3321 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3322 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3323 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3324 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3325 return MCDisassembler::Fail; 3326 break; 3327 default: 3328 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3329 return MCDisassembler::Fail; 3330 break; 3331 } 3332 3333 if (Rm != 0xF) 3334 Inst.addOperand(MCOperand::createImm(0)); 3335 3336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3337 return MCDisassembler::Fail; 3338 Inst.addOperand(MCOperand::createImm(align)); 3339 3340 if (Rm != 0xD && Rm != 0xF) { 3341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3342 return MCDisassembler::Fail; 3343 } 3344 3345 return S; 3346 } 3347 3348 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3349 uint64_t Address, const void *Decoder) { 3350 DecodeStatus S = MCDisassembler::Success; 3351 3352 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3353 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3354 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3355 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3356 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3357 3358 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3359 return MCDisassembler::Fail; 3360 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3361 return MCDisassembler::Fail; 3362 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3363 return MCDisassembler::Fail; 3364 if (Rm != 0xF) { 3365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 } 3368 3369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3370 return MCDisassembler::Fail; 3371 Inst.addOperand(MCOperand::createImm(0)); 3372 3373 if (Rm == 0xD) 3374 Inst.addOperand(MCOperand::createReg(0)); 3375 else if (Rm != 0xF) { 3376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3377 return MCDisassembler::Fail; 3378 } 3379 3380 return S; 3381 } 3382 3383 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3384 uint64_t Address, const void *Decoder) { 3385 DecodeStatus S = MCDisassembler::Success; 3386 3387 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3388 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3389 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3390 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3391 unsigned size = fieldFromInstruction(Insn, 6, 2); 3392 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3393 unsigned align = fieldFromInstruction(Insn, 4, 1); 3394 3395 if (size == 0x3) { 3396 if (align == 0) 3397 return MCDisassembler::Fail; 3398 align = 16; 3399 } else { 3400 if (size == 2) { 3401 align *= 8; 3402 } else { 3403 size = 1 << size; 3404 align *= 4*size; 3405 } 3406 } 3407 3408 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3411 return MCDisassembler::Fail; 3412 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3413 return MCDisassembler::Fail; 3414 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3415 return MCDisassembler::Fail; 3416 if (Rm != 0xF) { 3417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3418 return MCDisassembler::Fail; 3419 } 3420 3421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3422 return MCDisassembler::Fail; 3423 Inst.addOperand(MCOperand::createImm(align)); 3424 3425 if (Rm == 0xD) 3426 Inst.addOperand(MCOperand::createReg(0)); 3427 else if (Rm != 0xF) { 3428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 } 3431 3432 return S; 3433 } 3434 3435 static DecodeStatus 3436 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3437 uint64_t Address, const void *Decoder) { 3438 DecodeStatus S = MCDisassembler::Success; 3439 3440 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3441 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3442 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3443 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3444 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3445 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3446 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3447 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3448 3449 if (Q) { 3450 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3451 return MCDisassembler::Fail; 3452 } else { 3453 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3454 return MCDisassembler::Fail; 3455 } 3456 3457 Inst.addOperand(MCOperand::createImm(imm)); 3458 3459 switch (Inst.getOpcode()) { 3460 case ARM::VORRiv4i16: 3461 case ARM::VORRiv2i32: 3462 case ARM::VBICiv4i16: 3463 case ARM::VBICiv2i32: 3464 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 break; 3467 case ARM::VORRiv8i16: 3468 case ARM::VORRiv4i32: 3469 case ARM::VBICiv8i16: 3470 case ARM::VBICiv4i32: 3471 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3472 return MCDisassembler::Fail; 3473 break; 3474 default: 3475 break; 3476 } 3477 3478 return S; 3479 } 3480 3481 static DecodeStatus 3482 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3483 uint64_t Address, const void *Decoder) { 3484 DecodeStatus S = MCDisassembler::Success; 3485 3486 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3487 fieldFromInstruction(Insn, 13, 3)); 3488 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3489 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3490 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3491 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3492 imm |= cmode << 8; 3493 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3494 3495 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3496 return MCDisassembler::Fail; 3497 3498 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3499 return MCDisassembler::Fail; 3500 3501 Inst.addOperand(MCOperand::createImm(imm)); 3502 3503 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3504 Inst.addOperand(MCOperand::createReg(0)); 3505 Inst.addOperand(MCOperand::createImm(0)); 3506 3507 return S; 3508 } 3509 3510 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3511 uint64_t Address, const void *Decoder) { 3512 DecodeStatus S = MCDisassembler::Success; 3513 3514 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3515 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3516 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3517 return MCDisassembler::Fail; 3518 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3519 3520 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3521 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3522 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3523 return MCDisassembler::Fail; 3524 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3525 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3526 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3527 return MCDisassembler::Fail; 3528 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3529 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3530 Inst.addOperand(MCOperand::createImm(Qd)); 3531 3532 return S; 3533 } 3534 3535 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3536 uint64_t Address, const void *Decoder) { 3537 DecodeStatus S = MCDisassembler::Success; 3538 3539 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3540 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3541 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3542 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3543 unsigned size = fieldFromInstruction(Insn, 18, 2); 3544 3545 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3546 return MCDisassembler::Fail; 3547 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3548 return MCDisassembler::Fail; 3549 Inst.addOperand(MCOperand::createImm(8 << size)); 3550 3551 return S; 3552 } 3553 3554 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3555 uint64_t Address, const void *Decoder) { 3556 Inst.addOperand(MCOperand::createImm(8 - Val)); 3557 return MCDisassembler::Success; 3558 } 3559 3560 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3561 uint64_t Address, const void *Decoder) { 3562 Inst.addOperand(MCOperand::createImm(16 - Val)); 3563 return MCDisassembler::Success; 3564 } 3565 3566 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3567 uint64_t Address, const void *Decoder) { 3568 Inst.addOperand(MCOperand::createImm(32 - Val)); 3569 return MCDisassembler::Success; 3570 } 3571 3572 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3573 uint64_t Address, const void *Decoder) { 3574 Inst.addOperand(MCOperand::createImm(64 - Val)); 3575 return MCDisassembler::Success; 3576 } 3577 3578 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3579 uint64_t Address, const void *Decoder) { 3580 DecodeStatus S = MCDisassembler::Success; 3581 3582 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3583 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3584 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3585 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3586 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3587 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3588 unsigned op = fieldFromInstruction(Insn, 6, 1); 3589 3590 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3591 return MCDisassembler::Fail; 3592 if (op) { 3593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3594 return MCDisassembler::Fail; // Writeback 3595 } 3596 3597 switch (Inst.getOpcode()) { 3598 case ARM::VTBL2: 3599 case ARM::VTBX2: 3600 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3601 return MCDisassembler::Fail; 3602 break; 3603 default: 3604 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3605 return MCDisassembler::Fail; 3606 } 3607 3608 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3609 return MCDisassembler::Fail; 3610 3611 return S; 3612 } 3613 3614 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3615 uint64_t Address, const void *Decoder) { 3616 DecodeStatus S = MCDisassembler::Success; 3617 3618 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3619 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3620 3621 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3622 return MCDisassembler::Fail; 3623 3624 switch(Inst.getOpcode()) { 3625 default: 3626 return MCDisassembler::Fail; 3627 case ARM::tADR: 3628 break; // tADR does not explicitly represent the PC as an operand. 3629 case ARM::tADDrSPi: 3630 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3631 break; 3632 } 3633 3634 Inst.addOperand(MCOperand::createImm(imm)); 3635 return S; 3636 } 3637 3638 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3639 uint64_t Address, const void *Decoder) { 3640 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3641 true, 2, Inst, Decoder)) 3642 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3643 return MCDisassembler::Success; 3644 } 3645 3646 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3647 uint64_t Address, const void *Decoder) { 3648 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3649 true, 4, Inst, Decoder)) 3650 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3651 return MCDisassembler::Success; 3652 } 3653 3654 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3655 uint64_t Address, const void *Decoder) { 3656 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3657 true, 2, Inst, Decoder)) 3658 Inst.addOperand(MCOperand::createImm(Val << 1)); 3659 return MCDisassembler::Success; 3660 } 3661 3662 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3663 uint64_t Address, const void *Decoder) { 3664 DecodeStatus S = MCDisassembler::Success; 3665 3666 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3667 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3668 3669 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3670 return MCDisassembler::Fail; 3671 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3672 return MCDisassembler::Fail; 3673 3674 return S; 3675 } 3676 3677 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3678 uint64_t Address, const void *Decoder) { 3679 DecodeStatus S = MCDisassembler::Success; 3680 3681 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3682 unsigned imm = fieldFromInstruction(Val, 3, 5); 3683 3684 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3685 return MCDisassembler::Fail; 3686 Inst.addOperand(MCOperand::createImm(imm)); 3687 3688 return S; 3689 } 3690 3691 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3692 uint64_t Address, const void *Decoder) { 3693 unsigned imm = Val << 2; 3694 3695 Inst.addOperand(MCOperand::createImm(imm)); 3696 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3697 3698 return MCDisassembler::Success; 3699 } 3700 3701 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3702 uint64_t Address, const void *Decoder) { 3703 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3704 Inst.addOperand(MCOperand::createImm(Val)); 3705 3706 return MCDisassembler::Success; 3707 } 3708 3709 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3710 uint64_t Address, const void *Decoder) { 3711 DecodeStatus S = MCDisassembler::Success; 3712 3713 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3714 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3715 unsigned imm = fieldFromInstruction(Val, 0, 2); 3716 3717 // Thumb stores cannot use PC as dest register. 3718 switch (Inst.getOpcode()) { 3719 case ARM::t2STRHs: 3720 case ARM::t2STRBs: 3721 case ARM::t2STRs: 3722 if (Rn == 15) 3723 return MCDisassembler::Fail; 3724 break; 3725 default: 3726 break; 3727 } 3728 3729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3730 return MCDisassembler::Fail; 3731 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3732 return MCDisassembler::Fail; 3733 Inst.addOperand(MCOperand::createImm(imm)); 3734 3735 return S; 3736 } 3737 3738 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3739 uint64_t Address, const void *Decoder) { 3740 DecodeStatus S = MCDisassembler::Success; 3741 3742 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3743 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3744 3745 const FeatureBitset &featureBits = 3746 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3747 3748 bool hasMP = featureBits[ARM::FeatureMP]; 3749 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3750 3751 if (Rn == 15) { 3752 switch (Inst.getOpcode()) { 3753 case ARM::t2LDRBs: 3754 Inst.setOpcode(ARM::t2LDRBpci); 3755 break; 3756 case ARM::t2LDRHs: 3757 Inst.setOpcode(ARM::t2LDRHpci); 3758 break; 3759 case ARM::t2LDRSHs: 3760 Inst.setOpcode(ARM::t2LDRSHpci); 3761 break; 3762 case ARM::t2LDRSBs: 3763 Inst.setOpcode(ARM::t2LDRSBpci); 3764 break; 3765 case ARM::t2LDRs: 3766 Inst.setOpcode(ARM::t2LDRpci); 3767 break; 3768 case ARM::t2PLDs: 3769 Inst.setOpcode(ARM::t2PLDpci); 3770 break; 3771 case ARM::t2PLIs: 3772 Inst.setOpcode(ARM::t2PLIpci); 3773 break; 3774 default: 3775 return MCDisassembler::Fail; 3776 } 3777 3778 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3779 } 3780 3781 if (Rt == 15) { 3782 switch (Inst.getOpcode()) { 3783 case ARM::t2LDRSHs: 3784 return MCDisassembler::Fail; 3785 case ARM::t2LDRHs: 3786 Inst.setOpcode(ARM::t2PLDWs); 3787 break; 3788 case ARM::t2LDRSBs: 3789 Inst.setOpcode(ARM::t2PLIs); 3790 break; 3791 default: 3792 break; 3793 } 3794 } 3795 3796 switch (Inst.getOpcode()) { 3797 case ARM::t2PLDs: 3798 break; 3799 case ARM::t2PLIs: 3800 if (!hasV7Ops) 3801 return MCDisassembler::Fail; 3802 break; 3803 case ARM::t2PLDWs: 3804 if (!hasV7Ops || !hasMP) 3805 return MCDisassembler::Fail; 3806 break; 3807 default: 3808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3809 return MCDisassembler::Fail; 3810 } 3811 3812 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3813 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3814 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3815 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3816 return MCDisassembler::Fail; 3817 3818 return S; 3819 } 3820 3821 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3822 uint64_t Address, const void* Decoder) { 3823 DecodeStatus S = MCDisassembler::Success; 3824 3825 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3826 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3827 unsigned U = fieldFromInstruction(Insn, 9, 1); 3828 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3829 imm |= (U << 8); 3830 imm |= (Rn << 9); 3831 unsigned add = fieldFromInstruction(Insn, 9, 1); 3832 3833 const FeatureBitset &featureBits = 3834 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3835 3836 bool hasMP = featureBits[ARM::FeatureMP]; 3837 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3838 3839 if (Rn == 15) { 3840 switch (Inst.getOpcode()) { 3841 case ARM::t2LDRi8: 3842 Inst.setOpcode(ARM::t2LDRpci); 3843 break; 3844 case ARM::t2LDRBi8: 3845 Inst.setOpcode(ARM::t2LDRBpci); 3846 break; 3847 case ARM::t2LDRSBi8: 3848 Inst.setOpcode(ARM::t2LDRSBpci); 3849 break; 3850 case ARM::t2LDRHi8: 3851 Inst.setOpcode(ARM::t2LDRHpci); 3852 break; 3853 case ARM::t2LDRSHi8: 3854 Inst.setOpcode(ARM::t2LDRSHpci); 3855 break; 3856 case ARM::t2PLDi8: 3857 Inst.setOpcode(ARM::t2PLDpci); 3858 break; 3859 case ARM::t2PLIi8: 3860 Inst.setOpcode(ARM::t2PLIpci); 3861 break; 3862 default: 3863 return MCDisassembler::Fail; 3864 } 3865 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3866 } 3867 3868 if (Rt == 15) { 3869 switch (Inst.getOpcode()) { 3870 case ARM::t2LDRSHi8: 3871 return MCDisassembler::Fail; 3872 case ARM::t2LDRHi8: 3873 if (!add) 3874 Inst.setOpcode(ARM::t2PLDWi8); 3875 break; 3876 case ARM::t2LDRSBi8: 3877 Inst.setOpcode(ARM::t2PLIi8); 3878 break; 3879 default: 3880 break; 3881 } 3882 } 3883 3884 switch (Inst.getOpcode()) { 3885 case ARM::t2PLDi8: 3886 break; 3887 case ARM::t2PLIi8: 3888 if (!hasV7Ops) 3889 return MCDisassembler::Fail; 3890 break; 3891 case ARM::t2PLDWi8: 3892 if (!hasV7Ops || !hasMP) 3893 return MCDisassembler::Fail; 3894 break; 3895 default: 3896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3897 return MCDisassembler::Fail; 3898 } 3899 3900 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3901 return MCDisassembler::Fail; 3902 return S; 3903 } 3904 3905 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3906 uint64_t Address, const void* Decoder) { 3907 DecodeStatus S = MCDisassembler::Success; 3908 3909 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3910 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3911 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3912 imm |= (Rn << 13); 3913 3914 const FeatureBitset &featureBits = 3915 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3916 3917 bool hasMP = featureBits[ARM::FeatureMP]; 3918 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3919 3920 if (Rn == 15) { 3921 switch (Inst.getOpcode()) { 3922 case ARM::t2LDRi12: 3923 Inst.setOpcode(ARM::t2LDRpci); 3924 break; 3925 case ARM::t2LDRHi12: 3926 Inst.setOpcode(ARM::t2LDRHpci); 3927 break; 3928 case ARM::t2LDRSHi12: 3929 Inst.setOpcode(ARM::t2LDRSHpci); 3930 break; 3931 case ARM::t2LDRBi12: 3932 Inst.setOpcode(ARM::t2LDRBpci); 3933 break; 3934 case ARM::t2LDRSBi12: 3935 Inst.setOpcode(ARM::t2LDRSBpci); 3936 break; 3937 case ARM::t2PLDi12: 3938 Inst.setOpcode(ARM::t2PLDpci); 3939 break; 3940 case ARM::t2PLIi12: 3941 Inst.setOpcode(ARM::t2PLIpci); 3942 break; 3943 default: 3944 return MCDisassembler::Fail; 3945 } 3946 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3947 } 3948 3949 if (Rt == 15) { 3950 switch (Inst.getOpcode()) { 3951 case ARM::t2LDRSHi12: 3952 return MCDisassembler::Fail; 3953 case ARM::t2LDRHi12: 3954 Inst.setOpcode(ARM::t2PLDWi12); 3955 break; 3956 case ARM::t2LDRSBi12: 3957 Inst.setOpcode(ARM::t2PLIi12); 3958 break; 3959 default: 3960 break; 3961 } 3962 } 3963 3964 switch (Inst.getOpcode()) { 3965 case ARM::t2PLDi12: 3966 break; 3967 case ARM::t2PLIi12: 3968 if (!hasV7Ops) 3969 return MCDisassembler::Fail; 3970 break; 3971 case ARM::t2PLDWi12: 3972 if (!hasV7Ops || !hasMP) 3973 return MCDisassembler::Fail; 3974 break; 3975 default: 3976 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3977 return MCDisassembler::Fail; 3978 } 3979 3980 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3981 return MCDisassembler::Fail; 3982 return S; 3983 } 3984 3985 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3986 uint64_t Address, const void* Decoder) { 3987 DecodeStatus S = MCDisassembler::Success; 3988 3989 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3990 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3991 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3992 imm |= (Rn << 9); 3993 3994 if (Rn == 15) { 3995 switch (Inst.getOpcode()) { 3996 case ARM::t2LDRT: 3997 Inst.setOpcode(ARM::t2LDRpci); 3998 break; 3999 case ARM::t2LDRBT: 4000 Inst.setOpcode(ARM::t2LDRBpci); 4001 break; 4002 case ARM::t2LDRHT: 4003 Inst.setOpcode(ARM::t2LDRHpci); 4004 break; 4005 case ARM::t2LDRSBT: 4006 Inst.setOpcode(ARM::t2LDRSBpci); 4007 break; 4008 case ARM::t2LDRSHT: 4009 Inst.setOpcode(ARM::t2LDRSHpci); 4010 break; 4011 default: 4012 return MCDisassembler::Fail; 4013 } 4014 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4015 } 4016 4017 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4018 return MCDisassembler::Fail; 4019 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4020 return MCDisassembler::Fail; 4021 return S; 4022 } 4023 4024 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4025 uint64_t Address, const void* Decoder) { 4026 DecodeStatus S = MCDisassembler::Success; 4027 4028 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4029 unsigned U = fieldFromInstruction(Insn, 23, 1); 4030 int imm = fieldFromInstruction(Insn, 0, 12); 4031 4032 const FeatureBitset &featureBits = 4033 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4034 4035 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4036 4037 if (Rt == 15) { 4038 switch (Inst.getOpcode()) { 4039 case ARM::t2LDRBpci: 4040 case ARM::t2LDRHpci: 4041 Inst.setOpcode(ARM::t2PLDpci); 4042 break; 4043 case ARM::t2LDRSBpci: 4044 Inst.setOpcode(ARM::t2PLIpci); 4045 break; 4046 case ARM::t2LDRSHpci: 4047 return MCDisassembler::Fail; 4048 default: 4049 break; 4050 } 4051 } 4052 4053 switch(Inst.getOpcode()) { 4054 case ARM::t2PLDpci: 4055 break; 4056 case ARM::t2PLIpci: 4057 if (!hasV7Ops) 4058 return MCDisassembler::Fail; 4059 break; 4060 default: 4061 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4062 return MCDisassembler::Fail; 4063 } 4064 4065 if (!U) { 4066 // Special case for #-0. 4067 if (imm == 0) 4068 imm = INT32_MIN; 4069 else 4070 imm = -imm; 4071 } 4072 Inst.addOperand(MCOperand::createImm(imm)); 4073 4074 return S; 4075 } 4076 4077 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4078 uint64_t Address, const void *Decoder) { 4079 if (Val == 0) 4080 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4081 else { 4082 int imm = Val & 0xFF; 4083 4084 if (!(Val & 0x100)) imm *= -1; 4085 Inst.addOperand(MCOperand::createImm(imm * 4)); 4086 } 4087 4088 return MCDisassembler::Success; 4089 } 4090 4091 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4092 const void *Decoder) { 4093 if (Val == 0) 4094 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4095 else { 4096 int imm = Val & 0x7F; 4097 4098 if (!(Val & 0x80)) 4099 imm *= -1; 4100 Inst.addOperand(MCOperand::createImm(imm * 4)); 4101 } 4102 4103 return MCDisassembler::Success; 4104 } 4105 4106 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4107 uint64_t Address, const void *Decoder) { 4108 DecodeStatus S = MCDisassembler::Success; 4109 4110 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4111 unsigned imm = fieldFromInstruction(Val, 0, 9); 4112 4113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4114 return MCDisassembler::Fail; 4115 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4116 return MCDisassembler::Fail; 4117 4118 return S; 4119 } 4120 4121 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4122 uint64_t Address, 4123 const void *Decoder) { 4124 DecodeStatus S = MCDisassembler::Success; 4125 4126 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4127 unsigned imm = fieldFromInstruction(Val, 0, 8); 4128 4129 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4130 return MCDisassembler::Fail; 4131 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4132 return MCDisassembler::Fail; 4133 4134 return S; 4135 } 4136 4137 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4138 uint64_t Address, const void *Decoder) { 4139 DecodeStatus S = MCDisassembler::Success; 4140 4141 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4142 unsigned imm = fieldFromInstruction(Val, 0, 8); 4143 4144 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4145 return MCDisassembler::Fail; 4146 4147 Inst.addOperand(MCOperand::createImm(imm)); 4148 4149 return S; 4150 } 4151 4152 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4153 uint64_t Address, const void *Decoder) { 4154 int imm = Val & 0xFF; 4155 if (Val == 0) 4156 imm = INT32_MIN; 4157 else if (!(Val & 0x100)) 4158 imm *= -1; 4159 Inst.addOperand(MCOperand::createImm(imm)); 4160 4161 return MCDisassembler::Success; 4162 } 4163 4164 template<int shift> 4165 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4166 uint64_t Address, const void *Decoder) { 4167 int imm = Val & 0x7F; 4168 if (Val == 0) 4169 imm = INT32_MIN; 4170 else if (!(Val & 0x80)) 4171 imm *= -1; 4172 if (imm != INT32_MIN) 4173 imm <<= shift; 4174 Inst.addOperand(MCOperand::createImm(imm)); 4175 4176 return MCDisassembler::Success; 4177 } 4178 4179 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4180 uint64_t Address, const void *Decoder) { 4181 DecodeStatus S = MCDisassembler::Success; 4182 4183 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4184 unsigned imm = fieldFromInstruction(Val, 0, 9); 4185 4186 // Thumb stores cannot use PC as dest register. 4187 switch (Inst.getOpcode()) { 4188 case ARM::t2STRT: 4189 case ARM::t2STRBT: 4190 case ARM::t2STRHT: 4191 case ARM::t2STRi8: 4192 case ARM::t2STRHi8: 4193 case ARM::t2STRBi8: 4194 if (Rn == 15) 4195 return MCDisassembler::Fail; 4196 break; 4197 default: 4198 break; 4199 } 4200 4201 // Some instructions always use an additive offset. 4202 switch (Inst.getOpcode()) { 4203 case ARM::t2LDRT: 4204 case ARM::t2LDRBT: 4205 case ARM::t2LDRHT: 4206 case ARM::t2LDRSBT: 4207 case ARM::t2LDRSHT: 4208 case ARM::t2STRT: 4209 case ARM::t2STRBT: 4210 case ARM::t2STRHT: 4211 imm |= 0x100; 4212 break; 4213 default: 4214 break; 4215 } 4216 4217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4218 return MCDisassembler::Fail; 4219 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4220 return MCDisassembler::Fail; 4221 4222 return S; 4223 } 4224 4225 template<int shift> 4226 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4227 uint64_t Address, 4228 const void *Decoder) { 4229 DecodeStatus S = MCDisassembler::Success; 4230 4231 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4232 unsigned imm = fieldFromInstruction(Val, 0, 8); 4233 4234 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4235 return MCDisassembler::Fail; 4236 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4237 return MCDisassembler::Fail; 4238 4239 return S; 4240 } 4241 4242 template<int shift, int WriteBack> 4243 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4244 uint64_t Address, 4245 const void *Decoder) { 4246 DecodeStatus S = MCDisassembler::Success; 4247 4248 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4249 unsigned imm = fieldFromInstruction(Val, 0, 8); 4250 if (WriteBack) { 4251 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4252 return MCDisassembler::Fail; 4253 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4254 return MCDisassembler::Fail; 4255 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4256 return MCDisassembler::Fail; 4257 4258 return S; 4259 } 4260 4261 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4262 uint64_t Address, const void *Decoder) { 4263 DecodeStatus S = MCDisassembler::Success; 4264 4265 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4266 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4267 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4268 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4269 addr |= Rn << 9; 4270 unsigned load = fieldFromInstruction(Insn, 20, 1); 4271 4272 if (Rn == 15) { 4273 switch (Inst.getOpcode()) { 4274 case ARM::t2LDR_PRE: 4275 case ARM::t2LDR_POST: 4276 Inst.setOpcode(ARM::t2LDRpci); 4277 break; 4278 case ARM::t2LDRB_PRE: 4279 case ARM::t2LDRB_POST: 4280 Inst.setOpcode(ARM::t2LDRBpci); 4281 break; 4282 case ARM::t2LDRH_PRE: 4283 case ARM::t2LDRH_POST: 4284 Inst.setOpcode(ARM::t2LDRHpci); 4285 break; 4286 case ARM::t2LDRSB_PRE: 4287 case ARM::t2LDRSB_POST: 4288 if (Rt == 15) 4289 Inst.setOpcode(ARM::t2PLIpci); 4290 else 4291 Inst.setOpcode(ARM::t2LDRSBpci); 4292 break; 4293 case ARM::t2LDRSH_PRE: 4294 case ARM::t2LDRSH_POST: 4295 Inst.setOpcode(ARM::t2LDRSHpci); 4296 break; 4297 default: 4298 return MCDisassembler::Fail; 4299 } 4300 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4301 } 4302 4303 if (!load) { 4304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4305 return MCDisassembler::Fail; 4306 } 4307 4308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4309 return MCDisassembler::Fail; 4310 4311 if (load) { 4312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4313 return MCDisassembler::Fail; 4314 } 4315 4316 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4317 return MCDisassembler::Fail; 4318 4319 return S; 4320 } 4321 4322 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4323 uint64_t Address, const void *Decoder) { 4324 DecodeStatus S = MCDisassembler::Success; 4325 4326 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4327 unsigned imm = fieldFromInstruction(Val, 0, 12); 4328 4329 // Thumb stores cannot use PC as dest register. 4330 switch (Inst.getOpcode()) { 4331 case ARM::t2STRi12: 4332 case ARM::t2STRBi12: 4333 case ARM::t2STRHi12: 4334 if (Rn == 15) 4335 return MCDisassembler::Fail; 4336 break; 4337 default: 4338 break; 4339 } 4340 4341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4342 return MCDisassembler::Fail; 4343 Inst.addOperand(MCOperand::createImm(imm)); 4344 4345 return S; 4346 } 4347 4348 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4349 uint64_t Address, const void *Decoder) { 4350 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4351 4352 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4353 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4354 Inst.addOperand(MCOperand::createImm(imm)); 4355 4356 return MCDisassembler::Success; 4357 } 4358 4359 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4360 uint64_t Address, const void *Decoder) { 4361 DecodeStatus S = MCDisassembler::Success; 4362 4363 if (Inst.getOpcode() == ARM::tADDrSP) { 4364 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4365 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4366 4367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4368 return MCDisassembler::Fail; 4369 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4370 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4371 return MCDisassembler::Fail; 4372 } else if (Inst.getOpcode() == ARM::tADDspr) { 4373 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4374 4375 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4376 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4378 return MCDisassembler::Fail; 4379 } 4380 4381 return S; 4382 } 4383 4384 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4385 uint64_t Address, const void *Decoder) { 4386 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4387 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4388 4389 Inst.addOperand(MCOperand::createImm(imod)); 4390 Inst.addOperand(MCOperand::createImm(flags)); 4391 4392 return MCDisassembler::Success; 4393 } 4394 4395 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4396 uint64_t Address, const void *Decoder) { 4397 DecodeStatus S = MCDisassembler::Success; 4398 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4399 unsigned add = fieldFromInstruction(Insn, 4, 1); 4400 4401 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4402 return MCDisassembler::Fail; 4403 Inst.addOperand(MCOperand::createImm(add)); 4404 4405 return S; 4406 } 4407 4408 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4409 uint64_t Address, const void *Decoder) { 4410 DecodeStatus S = MCDisassembler::Success; 4411 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4412 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4413 4414 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4415 return MCDisassembler::Fail; 4416 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4417 return MCDisassembler::Fail; 4418 4419 return S; 4420 } 4421 4422 template<int shift> 4423 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4424 uint64_t Address, const void *Decoder) { 4425 DecodeStatus S = MCDisassembler::Success; 4426 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4427 int imm = fieldFromInstruction(Insn, 0, 7); 4428 4429 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4430 return MCDisassembler::Fail; 4431 4432 if(!fieldFromInstruction(Insn, 7, 1)) { 4433 if (imm == 0) 4434 imm = INT32_MIN; // indicate -0 4435 else 4436 imm *= -1; 4437 } 4438 if (imm != INT32_MIN) 4439 imm <<= shift; 4440 Inst.addOperand(MCOperand::createImm(imm)); 4441 4442 return S; 4443 } 4444 4445 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4446 uint64_t Address, const void *Decoder) { 4447 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4448 // Note only one trailing zero not two. Also the J1 and J2 values are from 4449 // the encoded instruction. So here change to I1 and I2 values via: 4450 // I1 = NOT(J1 EOR S); 4451 // I2 = NOT(J2 EOR S); 4452 // and build the imm32 with two trailing zeros as documented: 4453 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4454 unsigned S = (Val >> 23) & 1; 4455 unsigned J1 = (Val >> 22) & 1; 4456 unsigned J2 = (Val >> 21) & 1; 4457 unsigned I1 = !(J1 ^ S); 4458 unsigned I2 = !(J2 ^ S); 4459 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4460 int imm32 = SignExtend32<25>(tmp << 1); 4461 4462 if (!tryAddingSymbolicOperand(Address, 4463 (Address & ~2u) + imm32 + 4, 4464 true, 4, Inst, Decoder)) 4465 Inst.addOperand(MCOperand::createImm(imm32)); 4466 return MCDisassembler::Success; 4467 } 4468 4469 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4470 uint64_t Address, const void *Decoder) { 4471 if (Val == 0xA || Val == 0xB) 4472 return MCDisassembler::Fail; 4473 4474 const FeatureBitset &featureBits = 4475 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4476 4477 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4478 return MCDisassembler::Fail; 4479 4480 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should 4481 // decode as VFP/MVE instructions. 4482 if (featureBits[ARM::HasV8_1MMainlineOps] && 4483 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || 4484 (Val & 0xE) == 0xE)) 4485 return MCDisassembler::Fail; 4486 4487 Inst.addOperand(MCOperand::createImm(Val)); 4488 return MCDisassembler::Success; 4489 } 4490 4491 static DecodeStatus 4492 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4493 uint64_t Address, const void *Decoder) { 4494 DecodeStatus S = MCDisassembler::Success; 4495 4496 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4497 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4498 4499 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4501 return MCDisassembler::Fail; 4502 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4503 return MCDisassembler::Fail; 4504 return S; 4505 } 4506 4507 static DecodeStatus 4508 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4509 uint64_t Address, const void *Decoder) { 4510 DecodeStatus S = MCDisassembler::Success; 4511 4512 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4513 if (pred == 0xE || pred == 0xF) { 4514 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4515 switch (opc) { 4516 default: 4517 return MCDisassembler::Fail; 4518 case 0xf3bf8f4: 4519 Inst.setOpcode(ARM::t2DSB); 4520 break; 4521 case 0xf3bf8f5: 4522 Inst.setOpcode(ARM::t2DMB); 4523 break; 4524 case 0xf3bf8f6: 4525 Inst.setOpcode(ARM::t2ISB); 4526 break; 4527 } 4528 4529 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4530 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4531 } 4532 4533 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4534 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4535 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4536 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4537 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4538 4539 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4540 return MCDisassembler::Fail; 4541 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4542 return MCDisassembler::Fail; 4543 4544 return S; 4545 } 4546 4547 // Decode a shifted immediate operand. These basically consist 4548 // of an 8-bit value, and a 4-bit directive that specifies either 4549 // a splat operation or a rotation. 4550 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4551 uint64_t Address, const void *Decoder) { 4552 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4553 if (ctrl == 0) { 4554 unsigned byte = fieldFromInstruction(Val, 8, 2); 4555 unsigned imm = fieldFromInstruction(Val, 0, 8); 4556 switch (byte) { 4557 case 0: 4558 Inst.addOperand(MCOperand::createImm(imm)); 4559 break; 4560 case 1: 4561 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4562 break; 4563 case 2: 4564 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4565 break; 4566 case 3: 4567 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4568 (imm << 8) | imm)); 4569 break; 4570 } 4571 } else { 4572 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4573 unsigned rot = fieldFromInstruction(Val, 7, 5); 4574 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4575 Inst.addOperand(MCOperand::createImm(imm)); 4576 } 4577 4578 return MCDisassembler::Success; 4579 } 4580 4581 static DecodeStatus 4582 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4583 uint64_t Address, const void *Decoder) { 4584 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4585 true, 2, Inst, Decoder)) 4586 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4587 return MCDisassembler::Success; 4588 } 4589 4590 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4591 uint64_t Address, 4592 const void *Decoder) { 4593 // Val is passed in as S:J1:J2:imm10:imm11 4594 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4595 // the encoded instruction. So here change to I1 and I2 values via: 4596 // I1 = NOT(J1 EOR S); 4597 // I2 = NOT(J2 EOR S); 4598 // and build the imm32 with one trailing zero as documented: 4599 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4600 unsigned S = (Val >> 23) & 1; 4601 unsigned J1 = (Val >> 22) & 1; 4602 unsigned J2 = (Val >> 21) & 1; 4603 unsigned I1 = !(J1 ^ S); 4604 unsigned I2 = !(J2 ^ S); 4605 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4606 int imm32 = SignExtend32<25>(tmp << 1); 4607 4608 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4609 true, 4, Inst, Decoder)) 4610 Inst.addOperand(MCOperand::createImm(imm32)); 4611 return MCDisassembler::Success; 4612 } 4613 4614 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4615 uint64_t Address, const void *Decoder) { 4616 if (Val & ~0xf) 4617 return MCDisassembler::Fail; 4618 4619 Inst.addOperand(MCOperand::createImm(Val)); 4620 return MCDisassembler::Success; 4621 } 4622 4623 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4624 uint64_t Address, const void *Decoder) { 4625 if (Val & ~0xf) 4626 return MCDisassembler::Fail; 4627 4628 Inst.addOperand(MCOperand::createImm(Val)); 4629 return MCDisassembler::Success; 4630 } 4631 4632 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4633 uint64_t Address, const void *Decoder) { 4634 DecodeStatus S = MCDisassembler::Success; 4635 const FeatureBitset &FeatureBits = 4636 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4637 4638 if (FeatureBits[ARM::FeatureMClass]) { 4639 unsigned ValLow = Val & 0xff; 4640 4641 // Validate the SYSm value first. 4642 switch (ValLow) { 4643 case 0: // apsr 4644 case 1: // iapsr 4645 case 2: // eapsr 4646 case 3: // xpsr 4647 case 5: // ipsr 4648 case 6: // epsr 4649 case 7: // iepsr 4650 case 8: // msp 4651 case 9: // psp 4652 case 16: // primask 4653 case 20: // control 4654 break; 4655 case 17: // basepri 4656 case 18: // basepri_max 4657 case 19: // faultmask 4658 if (!(FeatureBits[ARM::HasV7Ops])) 4659 // Values basepri, basepri_max and faultmask are only valid for v7m. 4660 return MCDisassembler::Fail; 4661 break; 4662 case 0x8a: // msplim_ns 4663 case 0x8b: // psplim_ns 4664 case 0x91: // basepri_ns 4665 case 0x93: // faultmask_ns 4666 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4667 return MCDisassembler::Fail; 4668 LLVM_FALLTHROUGH; 4669 case 10: // msplim 4670 case 11: // psplim 4671 case 0x88: // msp_ns 4672 case 0x89: // psp_ns 4673 case 0x90: // primask_ns 4674 case 0x94: // control_ns 4675 case 0x98: // sp_ns 4676 if (!(FeatureBits[ARM::Feature8MSecExt])) 4677 return MCDisassembler::Fail; 4678 break; 4679 default: 4680 // Architecturally defined as unpredictable 4681 S = MCDisassembler::SoftFail; 4682 break; 4683 } 4684 4685 if (Inst.getOpcode() == ARM::t2MSR_M) { 4686 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4687 if (!(FeatureBits[ARM::HasV7Ops])) { 4688 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4689 // unpredictable. 4690 if (Mask != 2) 4691 S = MCDisassembler::SoftFail; 4692 } 4693 else { 4694 // The ARMv7-M architecture stores an additional 2-bit mask value in 4695 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4696 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4697 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4698 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4699 // only if the processor includes the DSP extension. 4700 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4701 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4702 S = MCDisassembler::SoftFail; 4703 } 4704 } 4705 } else { 4706 // A/R class 4707 if (Val == 0) 4708 return MCDisassembler::Fail; 4709 } 4710 Inst.addOperand(MCOperand::createImm(Val)); 4711 return S; 4712 } 4713 4714 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4715 uint64_t Address, const void *Decoder) { 4716 unsigned R = fieldFromInstruction(Val, 5, 1); 4717 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4718 4719 // The table of encodings for these banked registers comes from B9.2.3 of the 4720 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4721 // neater. So by fiat, these values are UNPREDICTABLE: 4722 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4723 return MCDisassembler::Fail; 4724 4725 Inst.addOperand(MCOperand::createImm(Val)); 4726 return MCDisassembler::Success; 4727 } 4728 4729 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4730 uint64_t Address, const void *Decoder) { 4731 DecodeStatus S = MCDisassembler::Success; 4732 4733 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4734 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4735 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4736 4737 if (Rn == 0xF) 4738 S = MCDisassembler::SoftFail; 4739 4740 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4741 return MCDisassembler::Fail; 4742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4743 return MCDisassembler::Fail; 4744 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4745 return MCDisassembler::Fail; 4746 4747 return S; 4748 } 4749 4750 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4751 uint64_t Address, 4752 const void *Decoder) { 4753 DecodeStatus S = MCDisassembler::Success; 4754 4755 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4756 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4757 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4758 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4759 4760 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4761 return MCDisassembler::Fail; 4762 4763 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4764 S = MCDisassembler::SoftFail; 4765 4766 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4767 return MCDisassembler::Fail; 4768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4769 return MCDisassembler::Fail; 4770 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4771 return MCDisassembler::Fail; 4772 4773 return S; 4774 } 4775 4776 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4777 uint64_t Address, const void *Decoder) { 4778 DecodeStatus S = MCDisassembler::Success; 4779 4780 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4781 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4782 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4783 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4784 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4785 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4786 4787 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4788 4789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4790 return MCDisassembler::Fail; 4791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4792 return MCDisassembler::Fail; 4793 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4794 return MCDisassembler::Fail; 4795 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4796 return MCDisassembler::Fail; 4797 4798 return S; 4799 } 4800 4801 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4802 uint64_t Address, const void *Decoder) { 4803 DecodeStatus S = MCDisassembler::Success; 4804 4805 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4806 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4807 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4808 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4809 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4810 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4811 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4812 4813 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4814 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4815 4816 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4817 return MCDisassembler::Fail; 4818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4819 return MCDisassembler::Fail; 4820 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4821 return MCDisassembler::Fail; 4822 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4823 return MCDisassembler::Fail; 4824 4825 return S; 4826 } 4827 4828 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4829 uint64_t Address, const void *Decoder) { 4830 DecodeStatus S = MCDisassembler::Success; 4831 4832 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4833 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4834 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4835 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4836 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4837 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4838 4839 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4840 4841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4842 return MCDisassembler::Fail; 4843 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4844 return MCDisassembler::Fail; 4845 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4846 return MCDisassembler::Fail; 4847 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4848 return MCDisassembler::Fail; 4849 4850 return S; 4851 } 4852 4853 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4854 uint64_t Address, const void *Decoder) { 4855 DecodeStatus S = MCDisassembler::Success; 4856 4857 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4858 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4859 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4860 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4861 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4862 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4863 4864 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4865 4866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4867 return MCDisassembler::Fail; 4868 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4869 return MCDisassembler::Fail; 4870 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4871 return MCDisassembler::Fail; 4872 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4873 return MCDisassembler::Fail; 4874 4875 return S; 4876 } 4877 4878 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4879 uint64_t Address, const void *Decoder) { 4880 DecodeStatus S = MCDisassembler::Success; 4881 4882 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4883 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4884 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4885 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4886 unsigned size = fieldFromInstruction(Insn, 10, 2); 4887 4888 unsigned align = 0; 4889 unsigned index = 0; 4890 switch (size) { 4891 default: 4892 return MCDisassembler::Fail; 4893 case 0: 4894 if (fieldFromInstruction(Insn, 4, 1)) 4895 return MCDisassembler::Fail; // UNDEFINED 4896 index = fieldFromInstruction(Insn, 5, 3); 4897 break; 4898 case 1: 4899 if (fieldFromInstruction(Insn, 5, 1)) 4900 return MCDisassembler::Fail; // UNDEFINED 4901 index = fieldFromInstruction(Insn, 6, 2); 4902 if (fieldFromInstruction(Insn, 4, 1)) 4903 align = 2; 4904 break; 4905 case 2: 4906 if (fieldFromInstruction(Insn, 6, 1)) 4907 return MCDisassembler::Fail; // UNDEFINED 4908 index = fieldFromInstruction(Insn, 7, 1); 4909 4910 switch (fieldFromInstruction(Insn, 4, 2)) { 4911 case 0 : 4912 align = 0; break; 4913 case 3: 4914 align = 4; break; 4915 default: 4916 return MCDisassembler::Fail; 4917 } 4918 break; 4919 } 4920 4921 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4922 return MCDisassembler::Fail; 4923 if (Rm != 0xF) { // Writeback 4924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4925 return MCDisassembler::Fail; 4926 } 4927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4928 return MCDisassembler::Fail; 4929 Inst.addOperand(MCOperand::createImm(align)); 4930 if (Rm != 0xF) { 4931 if (Rm != 0xD) { 4932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4933 return MCDisassembler::Fail; 4934 } else 4935 Inst.addOperand(MCOperand::createReg(0)); 4936 } 4937 4938 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4939 return MCDisassembler::Fail; 4940 Inst.addOperand(MCOperand::createImm(index)); 4941 4942 return S; 4943 } 4944 4945 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4946 uint64_t Address, const void *Decoder) { 4947 DecodeStatus S = MCDisassembler::Success; 4948 4949 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4950 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4951 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4952 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4953 unsigned size = fieldFromInstruction(Insn, 10, 2); 4954 4955 unsigned align = 0; 4956 unsigned index = 0; 4957 switch (size) { 4958 default: 4959 return MCDisassembler::Fail; 4960 case 0: 4961 if (fieldFromInstruction(Insn, 4, 1)) 4962 return MCDisassembler::Fail; // UNDEFINED 4963 index = fieldFromInstruction(Insn, 5, 3); 4964 break; 4965 case 1: 4966 if (fieldFromInstruction(Insn, 5, 1)) 4967 return MCDisassembler::Fail; // UNDEFINED 4968 index = fieldFromInstruction(Insn, 6, 2); 4969 if (fieldFromInstruction(Insn, 4, 1)) 4970 align = 2; 4971 break; 4972 case 2: 4973 if (fieldFromInstruction(Insn, 6, 1)) 4974 return MCDisassembler::Fail; // UNDEFINED 4975 index = fieldFromInstruction(Insn, 7, 1); 4976 4977 switch (fieldFromInstruction(Insn, 4, 2)) { 4978 case 0: 4979 align = 0; break; 4980 case 3: 4981 align = 4; break; 4982 default: 4983 return MCDisassembler::Fail; 4984 } 4985 break; 4986 } 4987 4988 if (Rm != 0xF) { // Writeback 4989 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4990 return MCDisassembler::Fail; 4991 } 4992 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4993 return MCDisassembler::Fail; 4994 Inst.addOperand(MCOperand::createImm(align)); 4995 if (Rm != 0xF) { 4996 if (Rm != 0xD) { 4997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4998 return MCDisassembler::Fail; 4999 } else 5000 Inst.addOperand(MCOperand::createReg(0)); 5001 } 5002 5003 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5004 return MCDisassembler::Fail; 5005 Inst.addOperand(MCOperand::createImm(index)); 5006 5007 return S; 5008 } 5009 5010 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5011 uint64_t Address, const void *Decoder) { 5012 DecodeStatus S = MCDisassembler::Success; 5013 5014 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5015 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5016 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5017 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5018 unsigned size = fieldFromInstruction(Insn, 10, 2); 5019 5020 unsigned align = 0; 5021 unsigned index = 0; 5022 unsigned inc = 1; 5023 switch (size) { 5024 default: 5025 return MCDisassembler::Fail; 5026 case 0: 5027 index = fieldFromInstruction(Insn, 5, 3); 5028 if (fieldFromInstruction(Insn, 4, 1)) 5029 align = 2; 5030 break; 5031 case 1: 5032 index = fieldFromInstruction(Insn, 6, 2); 5033 if (fieldFromInstruction(Insn, 4, 1)) 5034 align = 4; 5035 if (fieldFromInstruction(Insn, 5, 1)) 5036 inc = 2; 5037 break; 5038 case 2: 5039 if (fieldFromInstruction(Insn, 5, 1)) 5040 return MCDisassembler::Fail; // UNDEFINED 5041 index = fieldFromInstruction(Insn, 7, 1); 5042 if (fieldFromInstruction(Insn, 4, 1) != 0) 5043 align = 8; 5044 if (fieldFromInstruction(Insn, 6, 1)) 5045 inc = 2; 5046 break; 5047 } 5048 5049 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5050 return MCDisassembler::Fail; 5051 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5052 return MCDisassembler::Fail; 5053 if (Rm != 0xF) { // Writeback 5054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5055 return MCDisassembler::Fail; 5056 } 5057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5058 return MCDisassembler::Fail; 5059 Inst.addOperand(MCOperand::createImm(align)); 5060 if (Rm != 0xF) { 5061 if (Rm != 0xD) { 5062 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5063 return MCDisassembler::Fail; 5064 } else 5065 Inst.addOperand(MCOperand::createReg(0)); 5066 } 5067 5068 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5069 return MCDisassembler::Fail; 5070 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5071 return MCDisassembler::Fail; 5072 Inst.addOperand(MCOperand::createImm(index)); 5073 5074 return S; 5075 } 5076 5077 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5078 uint64_t Address, const void *Decoder) { 5079 DecodeStatus S = MCDisassembler::Success; 5080 5081 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5082 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5083 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5084 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5085 unsigned size = fieldFromInstruction(Insn, 10, 2); 5086 5087 unsigned align = 0; 5088 unsigned index = 0; 5089 unsigned inc = 1; 5090 switch (size) { 5091 default: 5092 return MCDisassembler::Fail; 5093 case 0: 5094 index = fieldFromInstruction(Insn, 5, 3); 5095 if (fieldFromInstruction(Insn, 4, 1)) 5096 align = 2; 5097 break; 5098 case 1: 5099 index = fieldFromInstruction(Insn, 6, 2); 5100 if (fieldFromInstruction(Insn, 4, 1)) 5101 align = 4; 5102 if (fieldFromInstruction(Insn, 5, 1)) 5103 inc = 2; 5104 break; 5105 case 2: 5106 if (fieldFromInstruction(Insn, 5, 1)) 5107 return MCDisassembler::Fail; // UNDEFINED 5108 index = fieldFromInstruction(Insn, 7, 1); 5109 if (fieldFromInstruction(Insn, 4, 1) != 0) 5110 align = 8; 5111 if (fieldFromInstruction(Insn, 6, 1)) 5112 inc = 2; 5113 break; 5114 } 5115 5116 if (Rm != 0xF) { // Writeback 5117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5118 return MCDisassembler::Fail; 5119 } 5120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5121 return MCDisassembler::Fail; 5122 Inst.addOperand(MCOperand::createImm(align)); 5123 if (Rm != 0xF) { 5124 if (Rm != 0xD) { 5125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5126 return MCDisassembler::Fail; 5127 } else 5128 Inst.addOperand(MCOperand::createReg(0)); 5129 } 5130 5131 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5132 return MCDisassembler::Fail; 5133 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5134 return MCDisassembler::Fail; 5135 Inst.addOperand(MCOperand::createImm(index)); 5136 5137 return S; 5138 } 5139 5140 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5141 uint64_t Address, const void *Decoder) { 5142 DecodeStatus S = MCDisassembler::Success; 5143 5144 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5145 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5146 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5147 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5148 unsigned size = fieldFromInstruction(Insn, 10, 2); 5149 5150 unsigned align = 0; 5151 unsigned index = 0; 5152 unsigned inc = 1; 5153 switch (size) { 5154 default: 5155 return MCDisassembler::Fail; 5156 case 0: 5157 if (fieldFromInstruction(Insn, 4, 1)) 5158 return MCDisassembler::Fail; // UNDEFINED 5159 index = fieldFromInstruction(Insn, 5, 3); 5160 break; 5161 case 1: 5162 if (fieldFromInstruction(Insn, 4, 1)) 5163 return MCDisassembler::Fail; // UNDEFINED 5164 index = fieldFromInstruction(Insn, 6, 2); 5165 if (fieldFromInstruction(Insn, 5, 1)) 5166 inc = 2; 5167 break; 5168 case 2: 5169 if (fieldFromInstruction(Insn, 4, 2)) 5170 return MCDisassembler::Fail; // UNDEFINED 5171 index = fieldFromInstruction(Insn, 7, 1); 5172 if (fieldFromInstruction(Insn, 6, 1)) 5173 inc = 2; 5174 break; 5175 } 5176 5177 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5178 return MCDisassembler::Fail; 5179 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5180 return MCDisassembler::Fail; 5181 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5182 return MCDisassembler::Fail; 5183 5184 if (Rm != 0xF) { // Writeback 5185 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5186 return MCDisassembler::Fail; 5187 } 5188 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5189 return MCDisassembler::Fail; 5190 Inst.addOperand(MCOperand::createImm(align)); 5191 if (Rm != 0xF) { 5192 if (Rm != 0xD) { 5193 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5194 return MCDisassembler::Fail; 5195 } else 5196 Inst.addOperand(MCOperand::createReg(0)); 5197 } 5198 5199 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5200 return MCDisassembler::Fail; 5201 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5202 return MCDisassembler::Fail; 5203 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5204 return MCDisassembler::Fail; 5205 Inst.addOperand(MCOperand::createImm(index)); 5206 5207 return S; 5208 } 5209 5210 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5211 uint64_t Address, const void *Decoder) { 5212 DecodeStatus S = MCDisassembler::Success; 5213 5214 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5215 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5216 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5217 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5218 unsigned size = fieldFromInstruction(Insn, 10, 2); 5219 5220 unsigned align = 0; 5221 unsigned index = 0; 5222 unsigned inc = 1; 5223 switch (size) { 5224 default: 5225 return MCDisassembler::Fail; 5226 case 0: 5227 if (fieldFromInstruction(Insn, 4, 1)) 5228 return MCDisassembler::Fail; // UNDEFINED 5229 index = fieldFromInstruction(Insn, 5, 3); 5230 break; 5231 case 1: 5232 if (fieldFromInstruction(Insn, 4, 1)) 5233 return MCDisassembler::Fail; // UNDEFINED 5234 index = fieldFromInstruction(Insn, 6, 2); 5235 if (fieldFromInstruction(Insn, 5, 1)) 5236 inc = 2; 5237 break; 5238 case 2: 5239 if (fieldFromInstruction(Insn, 4, 2)) 5240 return MCDisassembler::Fail; // UNDEFINED 5241 index = fieldFromInstruction(Insn, 7, 1); 5242 if (fieldFromInstruction(Insn, 6, 1)) 5243 inc = 2; 5244 break; 5245 } 5246 5247 if (Rm != 0xF) { // Writeback 5248 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5249 return MCDisassembler::Fail; 5250 } 5251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5252 return MCDisassembler::Fail; 5253 Inst.addOperand(MCOperand::createImm(align)); 5254 if (Rm != 0xF) { 5255 if (Rm != 0xD) { 5256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5257 return MCDisassembler::Fail; 5258 } else 5259 Inst.addOperand(MCOperand::createReg(0)); 5260 } 5261 5262 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5263 return MCDisassembler::Fail; 5264 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5265 return MCDisassembler::Fail; 5266 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5267 return MCDisassembler::Fail; 5268 Inst.addOperand(MCOperand::createImm(index)); 5269 5270 return S; 5271 } 5272 5273 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5274 uint64_t Address, const void *Decoder) { 5275 DecodeStatus S = MCDisassembler::Success; 5276 5277 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5278 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5279 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5280 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5281 unsigned size = fieldFromInstruction(Insn, 10, 2); 5282 5283 unsigned align = 0; 5284 unsigned index = 0; 5285 unsigned inc = 1; 5286 switch (size) { 5287 default: 5288 return MCDisassembler::Fail; 5289 case 0: 5290 if (fieldFromInstruction(Insn, 4, 1)) 5291 align = 4; 5292 index = fieldFromInstruction(Insn, 5, 3); 5293 break; 5294 case 1: 5295 if (fieldFromInstruction(Insn, 4, 1)) 5296 align = 8; 5297 index = fieldFromInstruction(Insn, 6, 2); 5298 if (fieldFromInstruction(Insn, 5, 1)) 5299 inc = 2; 5300 break; 5301 case 2: 5302 switch (fieldFromInstruction(Insn, 4, 2)) { 5303 case 0: 5304 align = 0; break; 5305 case 3: 5306 return MCDisassembler::Fail; 5307 default: 5308 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5309 } 5310 5311 index = fieldFromInstruction(Insn, 7, 1); 5312 if (fieldFromInstruction(Insn, 6, 1)) 5313 inc = 2; 5314 break; 5315 } 5316 5317 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5318 return MCDisassembler::Fail; 5319 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5320 return MCDisassembler::Fail; 5321 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5322 return MCDisassembler::Fail; 5323 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5324 return MCDisassembler::Fail; 5325 5326 if (Rm != 0xF) { // Writeback 5327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5328 return MCDisassembler::Fail; 5329 } 5330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5331 return MCDisassembler::Fail; 5332 Inst.addOperand(MCOperand::createImm(align)); 5333 if (Rm != 0xF) { 5334 if (Rm != 0xD) { 5335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5336 return MCDisassembler::Fail; 5337 } else 5338 Inst.addOperand(MCOperand::createReg(0)); 5339 } 5340 5341 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5342 return MCDisassembler::Fail; 5343 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5344 return MCDisassembler::Fail; 5345 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5346 return MCDisassembler::Fail; 5347 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5348 return MCDisassembler::Fail; 5349 Inst.addOperand(MCOperand::createImm(index)); 5350 5351 return S; 5352 } 5353 5354 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5355 uint64_t Address, const void *Decoder) { 5356 DecodeStatus S = MCDisassembler::Success; 5357 5358 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5359 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5360 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5361 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5362 unsigned size = fieldFromInstruction(Insn, 10, 2); 5363 5364 unsigned align = 0; 5365 unsigned index = 0; 5366 unsigned inc = 1; 5367 switch (size) { 5368 default: 5369 return MCDisassembler::Fail; 5370 case 0: 5371 if (fieldFromInstruction(Insn, 4, 1)) 5372 align = 4; 5373 index = fieldFromInstruction(Insn, 5, 3); 5374 break; 5375 case 1: 5376 if (fieldFromInstruction(Insn, 4, 1)) 5377 align = 8; 5378 index = fieldFromInstruction(Insn, 6, 2); 5379 if (fieldFromInstruction(Insn, 5, 1)) 5380 inc = 2; 5381 break; 5382 case 2: 5383 switch (fieldFromInstruction(Insn, 4, 2)) { 5384 case 0: 5385 align = 0; break; 5386 case 3: 5387 return MCDisassembler::Fail; 5388 default: 5389 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5390 } 5391 5392 index = fieldFromInstruction(Insn, 7, 1); 5393 if (fieldFromInstruction(Insn, 6, 1)) 5394 inc = 2; 5395 break; 5396 } 5397 5398 if (Rm != 0xF) { // Writeback 5399 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5400 return MCDisassembler::Fail; 5401 } 5402 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5403 return MCDisassembler::Fail; 5404 Inst.addOperand(MCOperand::createImm(align)); 5405 if (Rm != 0xF) { 5406 if (Rm != 0xD) { 5407 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5408 return MCDisassembler::Fail; 5409 } else 5410 Inst.addOperand(MCOperand::createReg(0)); 5411 } 5412 5413 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5414 return MCDisassembler::Fail; 5415 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5416 return MCDisassembler::Fail; 5417 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5418 return MCDisassembler::Fail; 5419 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5420 return MCDisassembler::Fail; 5421 Inst.addOperand(MCOperand::createImm(index)); 5422 5423 return S; 5424 } 5425 5426 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5427 uint64_t Address, const void *Decoder) { 5428 DecodeStatus S = MCDisassembler::Success; 5429 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5430 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5431 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5432 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5433 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5434 5435 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5436 S = MCDisassembler::SoftFail; 5437 5438 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5439 return MCDisassembler::Fail; 5440 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5441 return MCDisassembler::Fail; 5442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5443 return MCDisassembler::Fail; 5444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5445 return MCDisassembler::Fail; 5446 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5447 return MCDisassembler::Fail; 5448 5449 return S; 5450 } 5451 5452 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5453 uint64_t Address, const void *Decoder) { 5454 DecodeStatus S = MCDisassembler::Success; 5455 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5456 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5457 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5458 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5459 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5460 5461 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5462 S = MCDisassembler::SoftFail; 5463 5464 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5465 return MCDisassembler::Fail; 5466 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5467 return MCDisassembler::Fail; 5468 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5469 return MCDisassembler::Fail; 5470 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5471 return MCDisassembler::Fail; 5472 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5473 return MCDisassembler::Fail; 5474 5475 return S; 5476 } 5477 5478 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5479 uint64_t Address, const void *Decoder) { 5480 DecodeStatus S = MCDisassembler::Success; 5481 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5482 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5483 5484 if (pred == 0xF) { 5485 pred = 0xE; 5486 S = MCDisassembler::SoftFail; 5487 } 5488 5489 if (mask == 0x0) 5490 return MCDisassembler::Fail; 5491 5492 // IT masks are encoded as a sequence of replacement low-order bits 5493 // for the condition code. So if the low bit of the starting 5494 // condition code is 1, then we have to flip all the bits above the 5495 // terminating bit (which is the lowest 1 bit). 5496 if (pred & 1) { 5497 unsigned LowBit = mask & -mask; 5498 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5499 mask ^= BitsAboveLowBit; 5500 } 5501 5502 Inst.addOperand(MCOperand::createImm(pred)); 5503 Inst.addOperand(MCOperand::createImm(mask)); 5504 return S; 5505 } 5506 5507 static DecodeStatus 5508 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5509 uint64_t Address, const void *Decoder) { 5510 DecodeStatus S = MCDisassembler::Success; 5511 5512 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5513 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5514 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5515 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5516 unsigned W = fieldFromInstruction(Insn, 21, 1); 5517 unsigned U = fieldFromInstruction(Insn, 23, 1); 5518 unsigned P = fieldFromInstruction(Insn, 24, 1); 5519 bool writeback = (W == 1) | (P == 0); 5520 5521 addr |= (U << 8) | (Rn << 9); 5522 5523 if (writeback && (Rn == Rt || Rn == Rt2)) 5524 Check(S, MCDisassembler::SoftFail); 5525 if (Rt == Rt2) 5526 Check(S, MCDisassembler::SoftFail); 5527 5528 // Rt 5529 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5530 return MCDisassembler::Fail; 5531 // Rt2 5532 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5533 return MCDisassembler::Fail; 5534 // Writeback operand 5535 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5536 return MCDisassembler::Fail; 5537 // addr 5538 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5539 return MCDisassembler::Fail; 5540 5541 return S; 5542 } 5543 5544 static DecodeStatus 5545 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5546 uint64_t Address, const void *Decoder) { 5547 DecodeStatus S = MCDisassembler::Success; 5548 5549 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5550 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5551 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5552 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5553 unsigned W = fieldFromInstruction(Insn, 21, 1); 5554 unsigned U = fieldFromInstruction(Insn, 23, 1); 5555 unsigned P = fieldFromInstruction(Insn, 24, 1); 5556 bool writeback = (W == 1) | (P == 0); 5557 5558 addr |= (U << 8) | (Rn << 9); 5559 5560 if (writeback && (Rn == Rt || Rn == Rt2)) 5561 Check(S, MCDisassembler::SoftFail); 5562 5563 // Writeback operand 5564 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5565 return MCDisassembler::Fail; 5566 // Rt 5567 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5568 return MCDisassembler::Fail; 5569 // Rt2 5570 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5571 return MCDisassembler::Fail; 5572 // addr 5573 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5574 return MCDisassembler::Fail; 5575 5576 return S; 5577 } 5578 5579 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5580 uint64_t Address, const void *Decoder) { 5581 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5582 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5583 if (sign1 != sign2) return MCDisassembler::Fail; 5584 5585 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5586 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5587 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5588 Val |= sign1 << 12; 5589 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5590 5591 return MCDisassembler::Success; 5592 } 5593 5594 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5595 uint64_t Address, 5596 const void *Decoder) { 5597 DecodeStatus S = MCDisassembler::Success; 5598 5599 // Shift of "asr #32" is not allowed in Thumb2 mode. 5600 if (Val == 0x20) S = MCDisassembler::Fail; 5601 Inst.addOperand(MCOperand::createImm(Val)); 5602 return S; 5603 } 5604 5605 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5606 uint64_t Address, const void *Decoder) { 5607 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5608 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5609 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5610 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5611 5612 if (pred == 0xF) 5613 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5614 5615 DecodeStatus S = MCDisassembler::Success; 5616 5617 if (Rt == Rn || Rn == Rt2) 5618 S = MCDisassembler::SoftFail; 5619 5620 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5621 return MCDisassembler::Fail; 5622 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5623 return MCDisassembler::Fail; 5624 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5625 return MCDisassembler::Fail; 5626 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5627 return MCDisassembler::Fail; 5628 5629 return S; 5630 } 5631 5632 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5633 uint64_t Address, const void *Decoder) { 5634 const FeatureBitset &featureBits = 5635 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5636 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5637 5638 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5639 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5640 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5641 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5642 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5643 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5644 unsigned op = fieldFromInstruction(Insn, 5, 1); 5645 5646 DecodeStatus S = MCDisassembler::Success; 5647 5648 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5649 if (!(imm & 0x38)) { 5650 if (cmode == 0xF) { 5651 if (op == 1) return MCDisassembler::Fail; 5652 Inst.setOpcode(ARM::VMOVv2f32); 5653 } 5654 if (hasFullFP16) { 5655 if (cmode == 0xE) { 5656 if (op == 1) { 5657 Inst.setOpcode(ARM::VMOVv1i64); 5658 } else { 5659 Inst.setOpcode(ARM::VMOVv8i8); 5660 } 5661 } 5662 if (cmode == 0xD) { 5663 if (op == 1) { 5664 Inst.setOpcode(ARM::VMVNv2i32); 5665 } else { 5666 Inst.setOpcode(ARM::VMOVv2i32); 5667 } 5668 } 5669 if (cmode == 0xC) { 5670 if (op == 1) { 5671 Inst.setOpcode(ARM::VMVNv2i32); 5672 } else { 5673 Inst.setOpcode(ARM::VMOVv2i32); 5674 } 5675 } 5676 } 5677 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5678 } 5679 5680 if (!(imm & 0x20)) return MCDisassembler::Fail; 5681 5682 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5683 return MCDisassembler::Fail; 5684 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5685 return MCDisassembler::Fail; 5686 Inst.addOperand(MCOperand::createImm(64 - imm)); 5687 5688 return S; 5689 } 5690 5691 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5692 uint64_t Address, const void *Decoder) { 5693 const FeatureBitset &featureBits = 5694 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5695 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5696 5697 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5698 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5699 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5700 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5701 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5702 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5703 unsigned op = fieldFromInstruction(Insn, 5, 1); 5704 5705 DecodeStatus S = MCDisassembler::Success; 5706 5707 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5708 if (!(imm & 0x38)) { 5709 if (cmode == 0xF) { 5710 if (op == 1) return MCDisassembler::Fail; 5711 Inst.setOpcode(ARM::VMOVv4f32); 5712 } 5713 if (hasFullFP16) { 5714 if (cmode == 0xE) { 5715 if (op == 1) { 5716 Inst.setOpcode(ARM::VMOVv2i64); 5717 } else { 5718 Inst.setOpcode(ARM::VMOVv16i8); 5719 } 5720 } 5721 if (cmode == 0xD) { 5722 if (op == 1) { 5723 Inst.setOpcode(ARM::VMVNv4i32); 5724 } else { 5725 Inst.setOpcode(ARM::VMOVv4i32); 5726 } 5727 } 5728 if (cmode == 0xC) { 5729 if (op == 1) { 5730 Inst.setOpcode(ARM::VMVNv4i32); 5731 } else { 5732 Inst.setOpcode(ARM::VMOVv4i32); 5733 } 5734 } 5735 } 5736 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5737 } 5738 5739 if (!(imm & 0x20)) return MCDisassembler::Fail; 5740 5741 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5742 return MCDisassembler::Fail; 5743 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5744 return MCDisassembler::Fail; 5745 Inst.addOperand(MCOperand::createImm(64 - imm)); 5746 5747 return S; 5748 } 5749 5750 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5751 unsigned Insn, 5752 uint64_t Address, 5753 const void *Decoder) { 5754 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5755 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5756 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5757 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5758 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5759 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5760 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5761 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5762 5763 DecodeStatus S = MCDisassembler::Success; 5764 5765 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5766 5767 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5768 return MCDisassembler::Fail; 5769 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5770 return MCDisassembler::Fail; 5771 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5772 return MCDisassembler::Fail; 5773 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5774 return MCDisassembler::Fail; 5775 // The lane index does not have any bits in the encoding, because it can only 5776 // be 0. 5777 Inst.addOperand(MCOperand::createImm(0)); 5778 Inst.addOperand(MCOperand::createImm(rotate)); 5779 5780 return S; 5781 } 5782 5783 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5784 uint64_t Address, const void *Decoder) { 5785 DecodeStatus S = MCDisassembler::Success; 5786 5787 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5788 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5789 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5790 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5791 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5792 5793 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5794 S = MCDisassembler::SoftFail; 5795 5796 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5797 return MCDisassembler::Fail; 5798 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5799 return MCDisassembler::Fail; 5800 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5801 return MCDisassembler::Fail; 5802 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5803 return MCDisassembler::Fail; 5804 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5805 return MCDisassembler::Fail; 5806 5807 return S; 5808 } 5809 5810 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5811 uint64_t Address, const void *Decoder) { 5812 DecodeStatus S = MCDisassembler::Success; 5813 5814 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5815 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5816 unsigned cop = fieldFromInstruction(Val, 8, 4); 5817 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5818 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5819 5820 if ((cop & ~0x1) == 0xa) 5821 return MCDisassembler::Fail; 5822 5823 if (Rt == Rt2) 5824 S = MCDisassembler::SoftFail; 5825 5826 // We have to check if the instruction is MRRC2 5827 // or MCRR2 when constructing the operands for 5828 // Inst. Reason is because MRRC2 stores to two 5829 // registers so it's tablegen desc has has two 5830 // outputs whereas MCRR doesn't store to any 5831 // registers so all of it's operands are listed 5832 // as inputs, therefore the operand order for 5833 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5834 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5835 5836 if (Inst.getOpcode() == ARM::MRRC2) { 5837 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5838 return MCDisassembler::Fail; 5839 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5840 return MCDisassembler::Fail; 5841 } 5842 Inst.addOperand(MCOperand::createImm(cop)); 5843 Inst.addOperand(MCOperand::createImm(opc1)); 5844 if (Inst.getOpcode() == ARM::MCRR2) { 5845 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5846 return MCDisassembler::Fail; 5847 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5848 return MCDisassembler::Fail; 5849 } 5850 Inst.addOperand(MCOperand::createImm(CRm)); 5851 5852 return S; 5853 } 5854 5855 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5856 uint64_t Address, 5857 const void *Decoder) { 5858 const FeatureBitset &featureBits = 5859 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5860 DecodeStatus S = MCDisassembler::Success; 5861 5862 // Add explicit operand for the destination sysreg, for cases where 5863 // we have to model it for code generation purposes. 5864 switch (Inst.getOpcode()) { 5865 case ARM::VMSR_FPSCR_NZCVQC: 5866 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5867 break; 5868 case ARM::VMSR_P0: 5869 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5870 break; 5871 } 5872 5873 if (Inst.getOpcode() != ARM::FMSTAT) { 5874 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5875 5876 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5877 if (Rt == 13 || Rt == 15) 5878 S = MCDisassembler::SoftFail; 5879 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5880 } else 5881 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5882 } 5883 5884 // Add explicit operand for the source sysreg, similarly to above. 5885 switch (Inst.getOpcode()) { 5886 case ARM::VMRS_FPSCR_NZCVQC: 5887 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5888 break; 5889 case ARM::VMRS_P0: 5890 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5891 break; 5892 } 5893 5894 if (featureBits[ARM::ModeThumb]) { 5895 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5896 Inst.addOperand(MCOperand::createReg(0)); 5897 } else { 5898 unsigned pred = fieldFromInstruction(Val, 28, 4); 5899 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5900 return MCDisassembler::Fail; 5901 } 5902 5903 return S; 5904 } 5905 5906 template <bool isSigned, bool isNeg, int size> 5907 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5908 uint64_t Address, 5909 const void *Decoder) { 5910 DecodeStatus S = MCDisassembler::Success; 5911 if (Val == 0) 5912 S = MCDisassembler::SoftFail; 5913 5914 uint64_t DecVal; 5915 if (isSigned) 5916 DecVal = SignExtend32<size + 1>(Val << 1); 5917 else 5918 DecVal = (Val << 1); 5919 5920 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5921 Decoder)) 5922 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5923 return S; 5924 } 5925 5926 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5927 uint64_t Address, 5928 const void *Decoder) { 5929 5930 uint64_t LocImm = Inst.getOperand(0).getImm(); 5931 Val = LocImm + (2 << Val); 5932 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5933 Decoder)) 5934 Inst.addOperand(MCOperand::createImm(Val)); 5935 return MCDisassembler::Success; 5936 } 5937 5938 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5939 uint64_t Address, 5940 const void *Decoder) { 5941 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5942 return MCDisassembler::Fail; 5943 Inst.addOperand(MCOperand::createImm(Val)); 5944 return MCDisassembler::Success; 5945 } 5946 5947 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5948 const void *Decoder) { 5949 DecodeStatus S = MCDisassembler::Success; 5950 5951 if (Inst.getOpcode() == ARM::MVE_LCTP) 5952 return S; 5953 5954 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5955 fieldFromInstruction(Insn, 1, 10) << 1; 5956 switch (Inst.getOpcode()) { 5957 case ARM::t2LEUpdate: 5958 case ARM::MVE_LETP: 5959 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5960 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5961 LLVM_FALLTHROUGH; 5962 case ARM::t2LE: 5963 if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address, 5964 Decoder))) 5965 return MCDisassembler::Fail; 5966 break; 5967 case ARM::t2WLS: 5968 case ARM::MVE_WLSTP_8: 5969 case ARM::MVE_WLSTP_16: 5970 case ARM::MVE_WLSTP_32: 5971 case ARM::MVE_WLSTP_64: 5972 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5973 if (!Check(S, 5974 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5975 Address, Decoder)) || 5976 !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address, 5977 Decoder))) 5978 return MCDisassembler::Fail; 5979 break; 5980 case ARM::t2DLS: 5981 case ARM::MVE_DLSTP_8: 5982 case ARM::MVE_DLSTP_16: 5983 case ARM::MVE_DLSTP_32: 5984 case ARM::MVE_DLSTP_64: 5985 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5986 if (Rn == 0xF) { 5987 // Enforce all the rest of the instruction bits in LCTP, which 5988 // won't have been reliably checked based on LCTP's own tablegen 5989 // record, because we came to this decode by a roundabout route. 5990 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 5991 if ((Insn & ~SBZMask) != CanonicalLCTP) 5992 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 5993 if (Insn != CanonicalLCTP) 5994 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 5995 5996 Inst.setOpcode(ARM::MVE_LCTP); 5997 } else { 5998 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5999 if (!Check(S, DecoderGPRRegisterClass(Inst, 6000 fieldFromInstruction(Insn, 16, 4), 6001 Address, Decoder))) 6002 return MCDisassembler::Fail; 6003 } 6004 break; 6005 } 6006 return S; 6007 } 6008 6009 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6010 uint64_t Address, 6011 const void *Decoder) { 6012 DecodeStatus S = MCDisassembler::Success; 6013 6014 if (Val == 0) 6015 Val = 32; 6016 6017 Inst.addOperand(MCOperand::createImm(Val)); 6018 6019 return S; 6020 } 6021 6022 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6023 uint64_t Address, const void *Decoder) { 6024 if ((RegNo) + 1 > 11) 6025 return MCDisassembler::Fail; 6026 6027 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6028 Inst.addOperand(MCOperand::createReg(Register)); 6029 return MCDisassembler::Success; 6030 } 6031 6032 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6033 uint64_t Address, const void *Decoder) { 6034 if ((RegNo) > 14) 6035 return MCDisassembler::Fail; 6036 6037 unsigned Register = GPRDecoderTable[(RegNo)]; 6038 Inst.addOperand(MCOperand::createReg(Register)); 6039 return MCDisassembler::Success; 6040 } 6041 6042 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6043 const void *Decoder) { 6044 DecodeStatus S = MCDisassembler::Success; 6045 6046 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6047 Inst.addOperand(MCOperand::createReg(0)); 6048 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6049 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6050 (fieldFromInstruction(Insn, 12, 4) << 8) | 6051 (fieldFromInstruction(Insn, 22, 1) << 12); 6052 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6053 return MCDisassembler::Fail; 6054 } 6055 } else { 6056 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6057 (fieldFromInstruction(Insn, 22, 1) << 8) | 6058 (fieldFromInstruction(Insn, 12, 4) << 9); 6059 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6060 return MCDisassembler::Fail; 6061 } 6062 } 6063 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6064 6065 return S; 6066 } 6067 6068 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6069 uint64_t Address, 6070 const void *Decoder) { 6071 if (RegNo > 7) 6072 return MCDisassembler::Fail; 6073 6074 unsigned Register = QPRDecoderTable[RegNo]; 6075 Inst.addOperand(MCOperand::createReg(Register)); 6076 return MCDisassembler::Success; 6077 } 6078 6079 static const uint16_t QQPRDecoderTable[] = { 6080 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6081 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6082 }; 6083 6084 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6085 uint64_t Address, 6086 const void *Decoder) { 6087 if (RegNo > 6) 6088 return MCDisassembler::Fail; 6089 6090 unsigned Register = QQPRDecoderTable[RegNo]; 6091 Inst.addOperand(MCOperand::createReg(Register)); 6092 return MCDisassembler::Success; 6093 } 6094 6095 static const uint16_t QQQQPRDecoderTable[] = { 6096 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6097 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6098 }; 6099 6100 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6101 uint64_t Address, 6102 const void *Decoder) { 6103 if (RegNo > 4) 6104 return MCDisassembler::Fail; 6105 6106 unsigned Register = QQQQPRDecoderTable[RegNo]; 6107 Inst.addOperand(MCOperand::createReg(Register)); 6108 return MCDisassembler::Success; 6109 } 6110 6111 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6112 uint64_t Address, 6113 const void *Decoder) { 6114 DecodeStatus S = MCDisassembler::Success; 6115 6116 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6117 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6118 // 't' as 0 and finish with a 1. 6119 unsigned Imm = 0; 6120 // We always start with a 't'. 6121 unsigned CurBit = 0; 6122 for (int i = 3; i >= 0; --i) { 6123 // If the bit we are looking at is not the same as last one, invert the 6124 // CurBit, if it is the same leave it as is. 6125 CurBit ^= (Val >> i) & 1U; 6126 6127 // Encode the CurBit at the right place in the immediate. 6128 Imm |= (CurBit << i); 6129 6130 // If we are done, finish the encoding with a 1. 6131 if ((Val & ~(~0U << i)) == 0) { 6132 Imm |= 1U << i; 6133 break; 6134 } 6135 } 6136 6137 Inst.addOperand(MCOperand::createImm(Imm)); 6138 6139 return S; 6140 } 6141 6142 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6143 uint64_t Address, const void *Decoder) { 6144 // The vpred_r operand type includes an MQPR register field derived 6145 // from the encoding. But we don't actually want to add an operand 6146 // to the MCInst at this stage, because AddThumbPredicate will do it 6147 // later, and will infer the register number from the TIED_TO 6148 // constraint. So this is a deliberately empty decoder method that 6149 // will inhibit the auto-generated disassembly code from adding an 6150 // operand at all. 6151 return MCDisassembler::Success; 6152 } 6153 6154 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6155 unsigned Val, 6156 uint64_t Address, 6157 const void *Decoder) { 6158 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6159 return MCDisassembler::Success; 6160 } 6161 6162 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6163 unsigned Val, 6164 uint64_t Address, 6165 const void *Decoder) { 6166 unsigned Code; 6167 switch (Val & 0x3) { 6168 case 0: 6169 Code = ARMCC::GE; 6170 break; 6171 case 1: 6172 Code = ARMCC::LT; 6173 break; 6174 case 2: 6175 Code = ARMCC::GT; 6176 break; 6177 case 3: 6178 Code = ARMCC::LE; 6179 break; 6180 } 6181 Inst.addOperand(MCOperand::createImm(Code)); 6182 return MCDisassembler::Success; 6183 } 6184 6185 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6186 unsigned Val, 6187 uint64_t Address, 6188 const void *Decoder) { 6189 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6190 return MCDisassembler::Success; 6191 } 6192 6193 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6194 uint64_t Address, 6195 const void *Decoder) { 6196 unsigned Code; 6197 switch (Val) { 6198 default: 6199 return MCDisassembler::Fail; 6200 case 0: 6201 Code = ARMCC::EQ; 6202 break; 6203 case 1: 6204 Code = ARMCC::NE; 6205 break; 6206 case 4: 6207 Code = ARMCC::GE; 6208 break; 6209 case 5: 6210 Code = ARMCC::LT; 6211 break; 6212 case 6: 6213 Code = ARMCC::GT; 6214 break; 6215 case 7: 6216 Code = ARMCC::LE; 6217 break; 6218 } 6219 6220 Inst.addOperand(MCOperand::createImm(Code)); 6221 return MCDisassembler::Success; 6222 } 6223 6224 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6225 uint64_t Address, const void *Decoder) { 6226 DecodeStatus S = MCDisassembler::Success; 6227 6228 unsigned DecodedVal = 64 - Val; 6229 6230 switch (Inst.getOpcode()) { 6231 case ARM::MVE_VCVTf16s16_fix: 6232 case ARM::MVE_VCVTs16f16_fix: 6233 case ARM::MVE_VCVTf16u16_fix: 6234 case ARM::MVE_VCVTu16f16_fix: 6235 if (DecodedVal > 16) 6236 return MCDisassembler::Fail; 6237 break; 6238 case ARM::MVE_VCVTf32s32_fix: 6239 case ARM::MVE_VCVTs32f32_fix: 6240 case ARM::MVE_VCVTf32u32_fix: 6241 case ARM::MVE_VCVTu32f32_fix: 6242 if (DecodedVal > 32) 6243 return MCDisassembler::Fail; 6244 break; 6245 } 6246 6247 Inst.addOperand(MCOperand::createImm(64 - Val)); 6248 6249 return S; 6250 } 6251 6252 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6253 switch (Opcode) { 6254 case ARM::VSTR_P0_off: 6255 case ARM::VSTR_P0_pre: 6256 case ARM::VSTR_P0_post: 6257 case ARM::VLDR_P0_off: 6258 case ARM::VLDR_P0_pre: 6259 case ARM::VLDR_P0_post: 6260 return ARM::P0; 6261 default: 6262 return 0; 6263 } 6264 } 6265 6266 template<bool Writeback> 6267 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6268 uint64_t Address, 6269 const void *Decoder) { 6270 switch (Inst.getOpcode()) { 6271 case ARM::VSTR_FPSCR_pre: 6272 case ARM::VSTR_FPSCR_NZCVQC_pre: 6273 case ARM::VLDR_FPSCR_pre: 6274 case ARM::VLDR_FPSCR_NZCVQC_pre: 6275 case ARM::VSTR_FPSCR_off: 6276 case ARM::VSTR_FPSCR_NZCVQC_off: 6277 case ARM::VLDR_FPSCR_off: 6278 case ARM::VLDR_FPSCR_NZCVQC_off: 6279 case ARM::VSTR_FPSCR_post: 6280 case ARM::VSTR_FPSCR_NZCVQC_post: 6281 case ARM::VLDR_FPSCR_post: 6282 case ARM::VLDR_FPSCR_NZCVQC_post: 6283 const FeatureBitset &featureBits = 6284 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6285 6286 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6287 return MCDisassembler::Fail; 6288 } 6289 6290 DecodeStatus S = MCDisassembler::Success; 6291 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6292 Inst.addOperand(MCOperand::createReg(Sysreg)); 6293 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6294 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6295 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6296 6297 if (Writeback) { 6298 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6299 return MCDisassembler::Fail; 6300 } 6301 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6302 return MCDisassembler::Fail; 6303 6304 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6305 Inst.addOperand(MCOperand::createReg(0)); 6306 6307 return S; 6308 } 6309 6310 static inline DecodeStatus DecodeMVE_MEM_pre( 6311 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6312 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6313 DecodeStatus S = MCDisassembler::Success; 6314 6315 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6316 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6317 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6318 6319 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6320 return MCDisassembler::Fail; 6321 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6322 return MCDisassembler::Fail; 6323 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6324 return MCDisassembler::Fail; 6325 6326 return S; 6327 } 6328 6329 template <int shift> 6330 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6331 uint64_t Address, const void *Decoder) { 6332 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6333 fieldFromInstruction(Val, 16, 3), 6334 DecodetGPRRegisterClass, 6335 DecodeTAddrModeImm7<shift>); 6336 } 6337 6338 template <int shift> 6339 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6340 uint64_t Address, const void *Decoder) { 6341 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6342 fieldFromInstruction(Val, 16, 4), 6343 DecoderGPRRegisterClass, 6344 DecodeT2AddrModeImm7<shift,1>); 6345 } 6346 6347 template <int shift> 6348 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6349 uint64_t Address, const void *Decoder) { 6350 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6351 fieldFromInstruction(Val, 17, 3), 6352 DecodeMQPRRegisterClass, 6353 DecodeMveAddrModeQ<shift>); 6354 } 6355 6356 template<unsigned MinLog, unsigned MaxLog> 6357 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6358 uint64_t Address, 6359 const void *Decoder) { 6360 DecodeStatus S = MCDisassembler::Success; 6361 6362 if (Val < MinLog || Val > MaxLog) 6363 return MCDisassembler::Fail; 6364 6365 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6366 return S; 6367 } 6368 6369 template <int shift> 6370 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6371 uint64_t Address, 6372 const void *Decoder) { 6373 Val <<= shift; 6374 6375 Inst.addOperand(MCOperand::createImm(Val)); 6376 return MCDisassembler::Success; 6377 } 6378 6379 template<unsigned start> 6380 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6381 uint64_t Address, 6382 const void *Decoder) { 6383 DecodeStatus S = MCDisassembler::Success; 6384 6385 Inst.addOperand(MCOperand::createImm(start + Val)); 6386 6387 return S; 6388 } 6389 6390 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6391 uint64_t Address, const void *Decoder) { 6392 DecodeStatus S = MCDisassembler::Success; 6393 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6394 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6395 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6396 fieldFromInstruction(Insn, 13, 3)); 6397 unsigned index = fieldFromInstruction(Insn, 4, 1); 6398 6399 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6400 return MCDisassembler::Fail; 6401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6402 return MCDisassembler::Fail; 6403 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6404 return MCDisassembler::Fail; 6405 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6406 return MCDisassembler::Fail; 6407 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6408 return MCDisassembler::Fail; 6409 6410 return S; 6411 } 6412 6413 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6414 uint64_t Address, const void *Decoder) { 6415 DecodeStatus S = MCDisassembler::Success; 6416 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6417 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6418 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6419 fieldFromInstruction(Insn, 13, 3)); 6420 unsigned index = fieldFromInstruction(Insn, 4, 1); 6421 6422 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6423 return MCDisassembler::Fail; 6424 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6425 return MCDisassembler::Fail; 6426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6427 return MCDisassembler::Fail; 6428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6429 return MCDisassembler::Fail; 6430 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6431 return MCDisassembler::Fail; 6432 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6433 return MCDisassembler::Fail; 6434 6435 return S; 6436 } 6437 6438 static DecodeStatus DecodeMVEOverlappingLongShift( 6439 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6440 DecodeStatus S = MCDisassembler::Success; 6441 6442 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6443 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6444 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6445 6446 if (RdaHi == 14) { 6447 // This value of RdaHi (really indicating pc, because RdaHi has to 6448 // be an odd-numbered register, so the low bit will be set by the 6449 // decode function below) indicates that we must decode as SQRSHR 6450 // or UQRSHL, which both have a single Rda register field with all 6451 // four bits. 6452 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6453 6454 switch (Inst.getOpcode()) { 6455 case ARM::MVE_ASRLr: 6456 case ARM::MVE_SQRSHRL: 6457 Inst.setOpcode(ARM::MVE_SQRSHR); 6458 break; 6459 case ARM::MVE_LSLLr: 6460 case ARM::MVE_UQRSHLL: 6461 Inst.setOpcode(ARM::MVE_UQRSHL); 6462 break; 6463 default: 6464 llvm_unreachable("Unexpected starting opcode!"); 6465 } 6466 6467 // Rda as output parameter 6468 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6469 return MCDisassembler::Fail; 6470 6471 // Rda again as input parameter 6472 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6473 return MCDisassembler::Fail; 6474 6475 // Rm, the amount to shift by 6476 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6477 return MCDisassembler::Fail; 6478 6479 return S; 6480 } 6481 6482 // Otherwise, we decode as whichever opcode our caller has already 6483 // put into Inst. Those all look the same: 6484 6485 // RdaLo,RdaHi as output parameters 6486 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6487 return MCDisassembler::Fail; 6488 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6489 return MCDisassembler::Fail; 6490 6491 // RdaLo,RdaHi again as input parameters 6492 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6493 return MCDisassembler::Fail; 6494 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6495 return MCDisassembler::Fail; 6496 6497 // Rm, the amount to shift by 6498 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6499 return MCDisassembler::Fail; 6500 6501 return S; 6502 } 6503 6504 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6505 const void *Decoder) { 6506 DecodeStatus S = MCDisassembler::Success; 6507 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6508 fieldFromInstruction(Insn, 13, 3)); 6509 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6510 fieldFromInstruction(Insn, 1, 3)); 6511 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6512 6513 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6514 return MCDisassembler::Fail; 6515 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6516 return MCDisassembler::Fail; 6517 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6518 return MCDisassembler::Fail; 6519 6520 return S; 6521 } 6522 6523 template<bool scalar, OperandDecoder predicate_decoder> 6524 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6525 const void *Decoder) { 6526 DecodeStatus S = MCDisassembler::Success; 6527 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6528 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6529 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6530 return MCDisassembler::Fail; 6531 6532 unsigned fc; 6533 6534 if (scalar) { 6535 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6536 fieldFromInstruction(Insn, 7, 1) | 6537 fieldFromInstruction(Insn, 5, 1) << 1; 6538 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6539 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6540 return MCDisassembler::Fail; 6541 } else { 6542 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6543 fieldFromInstruction(Insn, 7, 1) | 6544 fieldFromInstruction(Insn, 0, 1) << 1; 6545 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6546 fieldFromInstruction(Insn, 1, 3); 6547 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6548 return MCDisassembler::Fail; 6549 } 6550 6551 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6552 return MCDisassembler::Fail; 6553 6554 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6555 Inst.addOperand(MCOperand::createReg(0)); 6556 Inst.addOperand(MCOperand::createImm(0)); 6557 6558 return S; 6559 } 6560 6561 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6562 const void *Decoder) { 6563 DecodeStatus S = MCDisassembler::Success; 6564 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6565 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6566 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6567 return MCDisassembler::Fail; 6568 return S; 6569 } 6570