1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/ARMAddressingModes.h" 10 #include "MCTargetDesc/ARMBaseInfo.h" 11 #include "MCTargetDesc/ARMMCTargetDesc.h" 12 #include "TargetInfo/ARMTargetInfo.h" 13 #include "Utils/ARMBaseInfo.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 16 #include "llvm/MC/MCFixedLenDisassembler.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/MC/SubtargetFeature.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/MathExtras.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <algorithm> 27 #include <cassert> 28 #include <cstdint> 29 #include <vector> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "arm-disassembler" 34 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 namespace { 38 39 // Handles the condition code status of instructions in IT blocks 40 class ITStatus 41 { 42 public: 43 // Returns the condition code for instruction in IT block 44 unsigned getITCC() { 45 unsigned CC = ARMCC::AL; 46 if (instrInITBlock()) 47 CC = ITStates.back(); 48 return CC; 49 } 50 51 // Advances the IT block state to the next T or E 52 void advanceITState() { 53 ITStates.pop_back(); 54 } 55 56 // Returns true if the current instruction is in an IT block 57 bool instrInITBlock() { 58 return !ITStates.empty(); 59 } 60 61 // Returns true if current instruction is the last instruction in an IT block 62 bool instrLastInITBlock() { 63 return ITStates.size() == 1; 64 } 65 66 // Called when decoding an IT instruction. Sets the IT state for 67 // the following instructions that for the IT block. Firstcond 68 // corresponds to the field in the IT instruction encoding; Mask 69 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 70 void setITState(char Firstcond, char Mask) { 71 // (3 - the number of trailing zeros) is the number of then / else. 72 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 73 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 74 assert(NumTZ <= 3 && "Invalid IT mask!"); 75 // push condition codes onto the stack the correct order for the pops 76 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 77 unsigned Else = (Mask >> Pos) & 1; 78 ITStates.push_back(CCBits ^ Else); 79 } 80 ITStates.push_back(CCBits); 81 } 82 83 private: 84 std::vector<unsigned char> ITStates; 85 }; 86 87 /// ARM disassembler for all ARM platforms. 88 class ARMDisassembler : public MCDisassembler { 89 public: 90 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 91 MCDisassembler(STI, Ctx) { 92 } 93 94 ~ARMDisassembler() override = default; 95 96 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 97 ArrayRef<uint8_t> Bytes, uint64_t Address, 98 raw_ostream &VStream, 99 raw_ostream &CStream) const override; 100 }; 101 102 /// Thumb disassembler for all Thumb platforms. 103 class ThumbDisassembler : public MCDisassembler { 104 public: 105 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 106 MCDisassembler(STI, Ctx) { 107 } 108 109 ~ThumbDisassembler() override = default; 110 111 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 112 ArrayRef<uint8_t> Bytes, uint64_t Address, 113 raw_ostream &VStream, 114 raw_ostream &CStream) const override; 115 116 private: 117 mutable ITStatus ITBlock; 118 119 DecodeStatus AddThumbPredicate(MCInst&) const; 120 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 121 }; 122 123 } // end anonymous namespace 124 125 static bool Check(DecodeStatus &Out, DecodeStatus In) { 126 switch (In) { 127 case MCDisassembler::Success: 128 // Out stays the same. 129 return true; 130 case MCDisassembler::SoftFail: 131 Out = In; 132 return true; 133 case MCDisassembler::Fail: 134 Out = In; 135 return false; 136 } 137 llvm_unreachable("Invalid DecodeStatus!"); 138 } 139 140 // Forward declare these because the autogenerated code will reference them. 141 // Definitions are further down. 142 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 147 uint64_t Address, const void *Decoder); 148 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 151 unsigned RegNo, uint64_t Address, 152 const void *Decoder); 153 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 154 unsigned RegNo, uint64_t Address, 155 const void *Decoder); 156 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 157 unsigned RegNo, uint64_t Address, 158 const void *Decoder); 159 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 172 uint64_t Address, const void *Decoder); 173 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 174 uint64_t Address, const void *Decoder); 175 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 178 unsigned RegNo, 179 uint64_t Address, 180 const void *Decoder); 181 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 186 unsigned RegNo, uint64_t Address, 187 const void *Decoder); 188 189 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 200 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 205 unsigned Insn, 206 uint64_t Address, 207 const void *Decoder); 208 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 217 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 218 unsigned Insn, 219 uint64_t Adddress, 220 const void *Decoder); 221 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 336 unsigned Val, 337 uint64_t Address, 338 const void *Decoder); 339 340 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 361 uint64_t Address, const void* Decoder); 362 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 363 uint64_t Address, const void* Decoder); 364 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 365 uint64_t Address, const void* Decoder); 366 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 367 uint64_t Address, const void* Decoder); 368 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 375 uint64_t Address, 376 const void *Decoder); 377 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 408 uint64_t Address, const void *Decoder); 409 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 410 uint64_t Address, const void *Decoder); 411 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 412 uint64_t Address, const void *Decoder); 413 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 414 uint64_t Address, const void *Decoder); 415 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 416 uint64_t Address, const void *Decoder); 417 418 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 419 uint64_t Address, const void *Decoder); 420 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 421 uint64_t Address, const void *Decoder); 422 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 423 uint64_t Address, const void *Decoder); 424 425 template <bool isSigned, bool isNeg, int size> 426 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 427 uint64_t Address, const void *Decoder); 428 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 429 uint64_t Address, 430 const void *Decoder); 431 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 432 uint64_t Address, 433 const void *Decoder); 434 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 435 const void *Decoder); 436 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 437 uint64_t Address, 438 const void *Decoder); 439 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 440 const void *Decoder); 441 template<bool Writeback> 442 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 443 uint64_t Address, 444 const void *Decoder); 445 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 446 uint64_t Address, 447 const void *Decoder); 448 #include "ARMGenDisassemblerTables.inc" 449 450 static MCDisassembler *createARMDisassembler(const Target &T, 451 const MCSubtargetInfo &STI, 452 MCContext &Ctx) { 453 return new ARMDisassembler(STI, Ctx); 454 } 455 456 static MCDisassembler *createThumbDisassembler(const Target &T, 457 const MCSubtargetInfo &STI, 458 MCContext &Ctx) { 459 return new ThumbDisassembler(STI, Ctx); 460 } 461 462 // Post-decoding checks 463 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 464 uint64_t Address, raw_ostream &OS, 465 raw_ostream &CS, 466 uint32_t Insn, 467 DecodeStatus Result) { 468 switch (MI.getOpcode()) { 469 case ARM::HVC: { 470 // HVC is undefined if condition = 0xf otherwise upredictable 471 // if condition != 0xe 472 uint32_t Cond = (Insn >> 28) & 0xF; 473 if (Cond == 0xF) 474 return MCDisassembler::Fail; 475 if (Cond != 0xE) 476 return MCDisassembler::SoftFail; 477 return Result; 478 } 479 case ARM::t2ADDri: 480 case ARM::t2ADDri12: 481 case ARM::t2ADDrr: 482 case ARM::t2ADDrs: 483 case ARM::t2SUBri: 484 case ARM::t2SUBri12: 485 case ARM::t2SUBrr: 486 case ARM::t2SUBrs: 487 if (MI.getOperand(0).getReg() == ARM::SP && 488 MI.getOperand(1).getReg() != ARM::SP) 489 return MCDisassembler::SoftFail; 490 return Result; 491 default: return Result; 492 } 493 } 494 495 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 496 ArrayRef<uint8_t> Bytes, 497 uint64_t Address, raw_ostream &OS, 498 raw_ostream &CS) const { 499 CommentStream = &CS; 500 501 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 502 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 503 "mode!"); 504 505 // We want to read exactly 4 bytes of data. 506 if (Bytes.size() < 4) { 507 Size = 0; 508 return MCDisassembler::Fail; 509 } 510 511 // Encoded as a small-endian 32-bit word in the stream. 512 uint32_t Insn = 513 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 514 515 // Calling the auto-generated decoder function. 516 DecodeStatus Result = 517 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 518 if (Result != MCDisassembler::Fail) { 519 Size = 4; 520 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 521 } 522 523 struct DecodeTable { 524 const uint8_t *P; 525 bool DecodePred; 526 }; 527 528 const DecodeTable Tables[] = { 529 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 530 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 531 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 532 {DecoderTablev8Crypto32, false}, 533 }; 534 535 for (auto Table : Tables) { 536 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 537 if (Result != MCDisassembler::Fail) { 538 Size = 4; 539 // Add a fake predicate operand, because we share these instruction 540 // definitions with Thumb2 where these instructions are predicable. 541 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 542 return MCDisassembler::Fail; 543 return Result; 544 } 545 } 546 547 Result = 548 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 549 if (Result != MCDisassembler::Fail) { 550 Size = 4; 551 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 552 } 553 554 Size = 4; 555 return MCDisassembler::Fail; 556 } 557 558 namespace llvm { 559 560 extern const MCInstrDesc ARMInsts[]; 561 562 } // end namespace llvm 563 564 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 565 /// immediate Value in the MCInst. The immediate Value has had any PC 566 /// adjustment made by the caller. If the instruction is a branch instruction 567 /// then isBranch is true, else false. If the getOpInfo() function was set as 568 /// part of the setupForSymbolicDisassembly() call then that function is called 569 /// to get any symbolic information at the Address for this instruction. If 570 /// that returns non-zero then the symbolic information it returns is used to 571 /// create an MCExpr and that is added as an operand to the MCInst. If 572 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 573 /// Value is done and if a symbol is found an MCExpr is created with that, else 574 /// an MCExpr with Value is created. This function returns true if it adds an 575 /// operand to the MCInst and false otherwise. 576 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 577 bool isBranch, uint64_t InstSize, 578 MCInst &MI, const void *Decoder) { 579 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 580 // FIXME: Does it make sense for value to be negative? 581 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 582 /* Offset */ 0, InstSize); 583 } 584 585 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 586 /// referenced by a load instruction with the base register that is the Pc. 587 /// These can often be values in a literal pool near the Address of the 588 /// instruction. The Address of the instruction and its immediate Value are 589 /// used as a possible literal pool entry. The SymbolLookUp call back will 590 /// return the name of a symbol referenced by the literal pool's entry if 591 /// the referenced address is that of a symbol. Or it will return a pointer to 592 /// a literal 'C' string if the referenced address of the literal pool's entry 593 /// is an address into a section with 'C' string literals. 594 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 595 const void *Decoder) { 596 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 597 Dis->tryAddingPcLoadReferenceComment(Value, Address); 598 } 599 600 // Thumb1 instructions don't have explicit S bits. Rather, they 601 // implicitly set CPSR. Since it's not represented in the encoding, the 602 // auto-generated decoder won't inject the CPSR operand. We need to fix 603 // that as a post-pass. 604 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 605 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 606 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 607 MCInst::iterator I = MI.begin(); 608 for (unsigned i = 0; i < NumOps; ++i, ++I) { 609 if (I == MI.end()) break; 610 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 611 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 612 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 613 return; 614 } 615 } 616 617 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 618 } 619 620 // Most Thumb instructions don't have explicit predicates in the 621 // encoding, but rather get their predicates from IT context. We need 622 // to fix up the predicate operands using this context information as a 623 // post-pass. 624 MCDisassembler::DecodeStatus 625 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 626 MCDisassembler::DecodeStatus S = Success; 627 628 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 629 630 // A few instructions actually have predicates encoded in them. Don't 631 // try to overwrite it if we're seeing one of those. 632 switch (MI.getOpcode()) { 633 case ARM::tBcc: 634 case ARM::t2Bcc: 635 case ARM::tCBZ: 636 case ARM::tCBNZ: 637 case ARM::tCPS: 638 case ARM::t2CPS3p: 639 case ARM::t2CPS2p: 640 case ARM::t2CPS1p: 641 case ARM::t2CSEL: 642 case ARM::t2CSINC: 643 case ARM::t2CSINV: 644 case ARM::t2CSNEG: 645 case ARM::tMOVSr: 646 case ARM::tSETEND: 647 // Some instructions (mostly conditional branches) are not 648 // allowed in IT blocks. 649 if (ITBlock.instrInITBlock()) 650 S = SoftFail; 651 else 652 return Success; 653 break; 654 case ARM::t2HINT: 655 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 656 S = SoftFail; 657 break; 658 case ARM::tB: 659 case ARM::t2B: 660 case ARM::t2TBB: 661 case ARM::t2TBH: 662 // Some instructions (mostly unconditional branches) can 663 // only appears at the end of, or outside of, an IT. 664 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 665 S = SoftFail; 666 break; 667 default: 668 break; 669 } 670 671 // If we're in an IT block, base the predicate on that. Otherwise, 672 // assume a predicate of AL. 673 unsigned CC; 674 CC = ITBlock.getITCC(); 675 if (CC == 0xF) 676 CC = ARMCC::AL; 677 if (ITBlock.instrInITBlock()) 678 ITBlock.advanceITState(); 679 680 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 681 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 682 MCInst::iterator I = MI.begin(); 683 for (unsigned i = 0; i < NumOps; ++i, ++I) { 684 if (I == MI.end()) break; 685 if (OpInfo[i].isPredicate()) { 686 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 687 Check(S, SoftFail); 688 I = MI.insert(I, MCOperand::createImm(CC)); 689 ++I; 690 if (CC == ARMCC::AL) 691 MI.insert(I, MCOperand::createReg(0)); 692 else 693 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 694 return S; 695 } 696 } 697 698 I = MI.insert(I, MCOperand::createImm(CC)); 699 ++I; 700 if (CC == ARMCC::AL) 701 MI.insert(I, MCOperand::createReg(0)); 702 else 703 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 704 705 return S; 706 } 707 708 // Thumb VFP instructions are a special case. Because we share their 709 // encodings between ARM and Thumb modes, and they are predicable in ARM 710 // mode, the auto-generated decoder will give them an (incorrect) 711 // predicate operand. We need to rewrite these operands based on the IT 712 // context as a post-pass. 713 void ThumbDisassembler::UpdateThumbVFPPredicate( 714 DecodeStatus &S, MCInst &MI) const { 715 unsigned CC; 716 CC = ITBlock.getITCC(); 717 if (CC == 0xF) 718 CC = ARMCC::AL; 719 if (ITBlock.instrInITBlock()) 720 ITBlock.advanceITState(); 721 722 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 723 MCInst::iterator I = MI.begin(); 724 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 725 for (unsigned i = 0; i < NumOps; ++i, ++I) { 726 if (OpInfo[i].isPredicate() ) { 727 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 728 Check(S, SoftFail); 729 I->setImm(CC); 730 ++I; 731 if (CC == ARMCC::AL) 732 I->setReg(0); 733 else 734 I->setReg(ARM::CPSR); 735 return; 736 } 737 } 738 } 739 740 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 741 ArrayRef<uint8_t> Bytes, 742 uint64_t Address, 743 raw_ostream &OS, 744 raw_ostream &CS) const { 745 CommentStream = &CS; 746 747 assert(STI.getFeatureBits()[ARM::ModeThumb] && 748 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 749 750 // We want to read exactly 2 bytes of data. 751 if (Bytes.size() < 2) { 752 Size = 0; 753 return MCDisassembler::Fail; 754 } 755 756 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 757 DecodeStatus Result = 758 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 759 if (Result != MCDisassembler::Fail) { 760 Size = 2; 761 Check(Result, AddThumbPredicate(MI)); 762 return Result; 763 } 764 765 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 766 STI); 767 if (Result) { 768 Size = 2; 769 bool InITBlock = ITBlock.instrInITBlock(); 770 Check(Result, AddThumbPredicate(MI)); 771 AddThumb1SBit(MI, InITBlock); 772 return Result; 773 } 774 775 Result = 776 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 777 if (Result != MCDisassembler::Fail) { 778 Size = 2; 779 780 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 781 // the Thumb predicate. 782 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 783 Result = MCDisassembler::SoftFail; 784 785 Check(Result, AddThumbPredicate(MI)); 786 787 // If we find an IT instruction, we need to parse its condition 788 // code and mask operands so that we can apply them correctly 789 // to the subsequent instructions. 790 if (MI.getOpcode() == ARM::t2IT) { 791 unsigned Firstcond = MI.getOperand(0).getImm(); 792 unsigned Mask = MI.getOperand(1).getImm(); 793 ITBlock.setITState(Firstcond, Mask); 794 795 // An IT instruction that would give a 'NV' predicate is unpredictable. 796 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 797 CS << "unpredictable IT predicate sequence"; 798 } 799 800 return Result; 801 } 802 803 // We want to read exactly 4 bytes of data. 804 if (Bytes.size() < 4) { 805 Size = 0; 806 return MCDisassembler::Fail; 807 } 808 809 uint32_t Insn32 = 810 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 811 812 Result = 813 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 814 if (Result != MCDisassembler::Fail) { 815 Size = 4; 816 Check(Result, AddThumbPredicate(MI)); 817 return Result; 818 } 819 820 Result = 821 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 822 if (Result != MCDisassembler::Fail) { 823 Size = 4; 824 bool InITBlock = ITBlock.instrInITBlock(); 825 Check(Result, AddThumbPredicate(MI)); 826 AddThumb1SBit(MI, InITBlock); 827 return Result; 828 } 829 830 Result = 831 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 832 if (Result != MCDisassembler::Fail) { 833 Size = 4; 834 Check(Result, AddThumbPredicate(MI)); 835 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 836 } 837 838 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 839 Result = 840 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 841 if (Result != MCDisassembler::Fail) { 842 Size = 4; 843 UpdateThumbVFPPredicate(Result, MI); 844 return Result; 845 } 846 } 847 848 Result = 849 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 850 if (Result != MCDisassembler::Fail) { 851 Size = 4; 852 return Result; 853 } 854 855 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 856 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 857 STI); 858 if (Result != MCDisassembler::Fail) { 859 Size = 4; 860 Check(Result, AddThumbPredicate(MI)); 861 return Result; 862 } 863 } 864 865 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 866 uint32_t NEONLdStInsn = Insn32; 867 NEONLdStInsn &= 0xF0FFFFFF; 868 NEONLdStInsn |= 0x04000000; 869 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 870 Address, this, STI); 871 if (Result != MCDisassembler::Fail) { 872 Size = 4; 873 Check(Result, AddThumbPredicate(MI)); 874 return Result; 875 } 876 } 877 878 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 879 uint32_t NEONDataInsn = Insn32; 880 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 881 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 882 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 883 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 884 Address, this, STI); 885 if (Result != MCDisassembler::Fail) { 886 Size = 4; 887 Check(Result, AddThumbPredicate(MI)); 888 return Result; 889 } 890 891 uint32_t NEONCryptoInsn = Insn32; 892 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 893 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 894 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 895 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 896 Address, this, STI); 897 if (Result != MCDisassembler::Fail) { 898 Size = 4; 899 return Result; 900 } 901 902 uint32_t NEONv8Insn = Insn32; 903 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 904 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 905 this, STI); 906 if (Result != MCDisassembler::Fail) { 907 Size = 4; 908 return Result; 909 } 910 } 911 912 Result = 913 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 914 if (Result != MCDisassembler::Fail) { 915 Size = 4; 916 Check(Result, AddThumbPredicate(MI)); 917 return Result; 918 } 919 920 Size = 0; 921 return MCDisassembler::Fail; 922 } 923 924 extern "C" void LLVMInitializeARMDisassembler() { 925 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 926 createARMDisassembler); 927 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 928 createARMDisassembler); 929 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 930 createThumbDisassembler); 931 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 932 createThumbDisassembler); 933 } 934 935 static const uint16_t GPRDecoderTable[] = { 936 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 937 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 938 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 939 ARM::R12, ARM::SP, ARM::LR, ARM::PC 940 }; 941 942 static const uint16_t CLRMGPRDecoderTable[] = { 943 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 944 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 945 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 946 ARM::R12, 0, ARM::LR, ARM::APSR 947 }; 948 949 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 950 uint64_t Address, const void *Decoder) { 951 if (RegNo > 15) 952 return MCDisassembler::Fail; 953 954 unsigned Register = GPRDecoderTable[RegNo]; 955 Inst.addOperand(MCOperand::createReg(Register)); 956 return MCDisassembler::Success; 957 } 958 959 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 960 uint64_t Address, 961 const void *Decoder) { 962 if (RegNo > 15) 963 return MCDisassembler::Fail; 964 965 unsigned Register = CLRMGPRDecoderTable[RegNo]; 966 if (Register == 0) 967 return MCDisassembler::Fail; 968 969 Inst.addOperand(MCOperand::createReg(Register)); 970 return MCDisassembler::Success; 971 } 972 973 static DecodeStatus 974 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 975 uint64_t Address, const void *Decoder) { 976 DecodeStatus S = MCDisassembler::Success; 977 978 if (RegNo == 15) 979 S = MCDisassembler::SoftFail; 980 981 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 982 983 return S; 984 } 985 986 static DecodeStatus 987 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 988 uint64_t Address, const void *Decoder) { 989 DecodeStatus S = MCDisassembler::Success; 990 991 if (RegNo == 15) 992 { 993 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 994 return MCDisassembler::Success; 995 } 996 997 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 998 return S; 999 } 1000 1001 static DecodeStatus 1002 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1003 uint64_t Address, const void *Decoder) { 1004 DecodeStatus S = MCDisassembler::Success; 1005 1006 if (RegNo == 15) 1007 { 1008 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1009 return MCDisassembler::Success; 1010 } 1011 1012 if (RegNo == 13) 1013 S = MCDisassembler::SoftFail; 1014 1015 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1016 return S; 1017 } 1018 1019 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1020 uint64_t Address, const void *Decoder) { 1021 if (RegNo > 7) 1022 return MCDisassembler::Fail; 1023 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1024 } 1025 1026 static const uint16_t GPRPairDecoderTable[] = { 1027 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1028 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1029 }; 1030 1031 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1032 uint64_t Address, const void *Decoder) { 1033 DecodeStatus S = MCDisassembler::Success; 1034 1035 if (RegNo > 13) 1036 return MCDisassembler::Fail; 1037 1038 if ((RegNo & 1) || RegNo == 0xe) 1039 S = MCDisassembler::SoftFail; 1040 1041 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1042 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1043 return S; 1044 } 1045 1046 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1047 uint64_t Address, const void *Decoder) { 1048 unsigned Register = 0; 1049 switch (RegNo) { 1050 case 0: 1051 Register = ARM::R0; 1052 break; 1053 case 1: 1054 Register = ARM::R1; 1055 break; 1056 case 2: 1057 Register = ARM::R2; 1058 break; 1059 case 3: 1060 Register = ARM::R3; 1061 break; 1062 case 9: 1063 Register = ARM::R9; 1064 break; 1065 case 12: 1066 Register = ARM::R12; 1067 break; 1068 default: 1069 return MCDisassembler::Fail; 1070 } 1071 1072 Inst.addOperand(MCOperand::createReg(Register)); 1073 return MCDisassembler::Success; 1074 } 1075 1076 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1077 uint64_t Address, const void *Decoder) { 1078 DecodeStatus S = MCDisassembler::Success; 1079 1080 const FeatureBitset &featureBits = 1081 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1082 1083 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1084 S = MCDisassembler::SoftFail; 1085 1086 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1087 return S; 1088 } 1089 1090 static const uint16_t SPRDecoderTable[] = { 1091 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1092 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1093 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1094 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1095 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1096 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1097 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1098 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1099 }; 1100 1101 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1102 uint64_t Address, const void *Decoder) { 1103 if (RegNo > 31) 1104 return MCDisassembler::Fail; 1105 1106 unsigned Register = SPRDecoderTable[RegNo]; 1107 Inst.addOperand(MCOperand::createReg(Register)); 1108 return MCDisassembler::Success; 1109 } 1110 1111 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1112 uint64_t Address, const void *Decoder) { 1113 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1114 } 1115 1116 static const uint16_t DPRDecoderTable[] = { 1117 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1118 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1119 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1120 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1121 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1122 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1123 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1124 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1125 }; 1126 1127 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1128 uint64_t Address, const void *Decoder) { 1129 const FeatureBitset &featureBits = 1130 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1131 1132 bool hasD32 = featureBits[ARM::FeatureD32]; 1133 1134 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1135 return MCDisassembler::Fail; 1136 1137 unsigned Register = DPRDecoderTable[RegNo]; 1138 Inst.addOperand(MCOperand::createReg(Register)); 1139 return MCDisassembler::Success; 1140 } 1141 1142 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1143 uint64_t Address, const void *Decoder) { 1144 if (RegNo > 7) 1145 return MCDisassembler::Fail; 1146 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1147 } 1148 1149 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1150 uint64_t Address, const void *Decoder) { 1151 if (RegNo > 15) 1152 return MCDisassembler::Fail; 1153 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1154 } 1155 1156 static DecodeStatus 1157 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1158 uint64_t Address, const void *Decoder) { 1159 if (RegNo > 15) 1160 return MCDisassembler::Fail; 1161 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1162 } 1163 1164 static const uint16_t QPRDecoderTable[] = { 1165 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1166 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1167 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1168 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1169 }; 1170 1171 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1172 uint64_t Address, const void *Decoder) { 1173 if (RegNo > 31 || (RegNo & 1) != 0) 1174 return MCDisassembler::Fail; 1175 RegNo >>= 1; 1176 1177 unsigned Register = QPRDecoderTable[RegNo]; 1178 Inst.addOperand(MCOperand::createReg(Register)); 1179 return MCDisassembler::Success; 1180 } 1181 1182 static const uint16_t DPairDecoderTable[] = { 1183 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1184 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1185 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1186 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1187 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1188 ARM::Q15 1189 }; 1190 1191 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1192 uint64_t Address, const void *Decoder) { 1193 if (RegNo > 30) 1194 return MCDisassembler::Fail; 1195 1196 unsigned Register = DPairDecoderTable[RegNo]; 1197 Inst.addOperand(MCOperand::createReg(Register)); 1198 return MCDisassembler::Success; 1199 } 1200 1201 static const uint16_t DPairSpacedDecoderTable[] = { 1202 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1203 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1204 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1205 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1206 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1207 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1208 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1209 ARM::D28_D30, ARM::D29_D31 1210 }; 1211 1212 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1213 unsigned RegNo, 1214 uint64_t Address, 1215 const void *Decoder) { 1216 if (RegNo > 29) 1217 return MCDisassembler::Fail; 1218 1219 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1220 Inst.addOperand(MCOperand::createReg(Register)); 1221 return MCDisassembler::Success; 1222 } 1223 1224 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1225 uint64_t Address, const void *Decoder) { 1226 DecodeStatus S = MCDisassembler::Success; 1227 if (Val == 0xF) return MCDisassembler::Fail; 1228 // AL predicate is not allowed on Thumb1 branches. 1229 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1230 return MCDisassembler::Fail; 1231 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1232 Check(S, MCDisassembler::SoftFail); 1233 Inst.addOperand(MCOperand::createImm(Val)); 1234 if (Val == ARMCC::AL) { 1235 Inst.addOperand(MCOperand::createReg(0)); 1236 } else 1237 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1238 return S; 1239 } 1240 1241 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1242 uint64_t Address, const void *Decoder) { 1243 if (Val) 1244 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1245 else 1246 Inst.addOperand(MCOperand::createReg(0)); 1247 return MCDisassembler::Success; 1248 } 1249 1250 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1251 uint64_t Address, const void *Decoder) { 1252 DecodeStatus S = MCDisassembler::Success; 1253 1254 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1255 unsigned type = fieldFromInstruction(Val, 5, 2); 1256 unsigned imm = fieldFromInstruction(Val, 7, 5); 1257 1258 // Register-immediate 1259 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1260 return MCDisassembler::Fail; 1261 1262 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1263 switch (type) { 1264 case 0: 1265 Shift = ARM_AM::lsl; 1266 break; 1267 case 1: 1268 Shift = ARM_AM::lsr; 1269 break; 1270 case 2: 1271 Shift = ARM_AM::asr; 1272 break; 1273 case 3: 1274 Shift = ARM_AM::ror; 1275 break; 1276 } 1277 1278 if (Shift == ARM_AM::ror && imm == 0) 1279 Shift = ARM_AM::rrx; 1280 1281 unsigned Op = Shift | (imm << 3); 1282 Inst.addOperand(MCOperand::createImm(Op)); 1283 1284 return S; 1285 } 1286 1287 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1288 uint64_t Address, const void *Decoder) { 1289 DecodeStatus S = MCDisassembler::Success; 1290 1291 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1292 unsigned type = fieldFromInstruction(Val, 5, 2); 1293 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1294 1295 // Register-register 1296 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1297 return MCDisassembler::Fail; 1298 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1299 return MCDisassembler::Fail; 1300 1301 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1302 switch (type) { 1303 case 0: 1304 Shift = ARM_AM::lsl; 1305 break; 1306 case 1: 1307 Shift = ARM_AM::lsr; 1308 break; 1309 case 2: 1310 Shift = ARM_AM::asr; 1311 break; 1312 case 3: 1313 Shift = ARM_AM::ror; 1314 break; 1315 } 1316 1317 Inst.addOperand(MCOperand::createImm(Shift)); 1318 1319 return S; 1320 } 1321 1322 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1323 uint64_t Address, const void *Decoder) { 1324 DecodeStatus S = MCDisassembler::Success; 1325 1326 bool NeedDisjointWriteback = false; 1327 unsigned WritebackReg = 0; 1328 bool CLRM = false; 1329 switch (Inst.getOpcode()) { 1330 default: 1331 break; 1332 case ARM::LDMIA_UPD: 1333 case ARM::LDMDB_UPD: 1334 case ARM::LDMIB_UPD: 1335 case ARM::LDMDA_UPD: 1336 case ARM::t2LDMIA_UPD: 1337 case ARM::t2LDMDB_UPD: 1338 case ARM::t2STMIA_UPD: 1339 case ARM::t2STMDB_UPD: 1340 NeedDisjointWriteback = true; 1341 WritebackReg = Inst.getOperand(0).getReg(); 1342 break; 1343 case ARM::t2CLRM: 1344 CLRM = true; 1345 break; 1346 } 1347 1348 // Empty register lists are not allowed. 1349 if (Val == 0) return MCDisassembler::Fail; 1350 for (unsigned i = 0; i < 16; ++i) { 1351 if (Val & (1 << i)) { 1352 if (CLRM) { 1353 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1354 return MCDisassembler::Fail; 1355 } 1356 } else { 1357 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1358 return MCDisassembler::Fail; 1359 // Writeback not allowed if Rn is in the target list. 1360 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1361 Check(S, MCDisassembler::SoftFail); 1362 } 1363 } 1364 } 1365 1366 return S; 1367 } 1368 1369 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1370 uint64_t Address, const void *Decoder) { 1371 DecodeStatus S = MCDisassembler::Success; 1372 1373 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1374 unsigned regs = fieldFromInstruction(Val, 0, 8); 1375 1376 // In case of unpredictable encoding, tweak the operands. 1377 if (regs == 0 || (Vd + regs) > 32) { 1378 regs = Vd + regs > 32 ? 32 - Vd : regs; 1379 regs = std::max( 1u, regs); 1380 S = MCDisassembler::SoftFail; 1381 } 1382 1383 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1384 return MCDisassembler::Fail; 1385 for (unsigned i = 0; i < (regs - 1); ++i) { 1386 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1387 return MCDisassembler::Fail; 1388 } 1389 1390 return S; 1391 } 1392 1393 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1394 uint64_t Address, const void *Decoder) { 1395 DecodeStatus S = MCDisassembler::Success; 1396 1397 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1398 unsigned regs = fieldFromInstruction(Val, 1, 7); 1399 1400 // In case of unpredictable encoding, tweak the operands. 1401 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1402 regs = Vd + regs > 32 ? 32 - Vd : regs; 1403 regs = std::max( 1u, regs); 1404 regs = std::min(16u, regs); 1405 S = MCDisassembler::SoftFail; 1406 } 1407 1408 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1409 return MCDisassembler::Fail; 1410 for (unsigned i = 0; i < (regs - 1); ++i) { 1411 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1412 return MCDisassembler::Fail; 1413 } 1414 1415 return S; 1416 } 1417 1418 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1419 uint64_t Address, const void *Decoder) { 1420 // This operand encodes a mask of contiguous zeros between a specified MSB 1421 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1422 // the mask of all bits LSB-and-lower, and then xor them to create 1423 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1424 // create the final mask. 1425 unsigned msb = fieldFromInstruction(Val, 5, 5); 1426 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1427 1428 DecodeStatus S = MCDisassembler::Success; 1429 if (lsb > msb) { 1430 Check(S, MCDisassembler::SoftFail); 1431 // The check above will cause the warning for the "potentially undefined 1432 // instruction encoding" but we can't build a bad MCOperand value here 1433 // with a lsb > msb or else printing the MCInst will cause a crash. 1434 lsb = msb; 1435 } 1436 1437 uint32_t msb_mask = 0xFFFFFFFF; 1438 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1439 uint32_t lsb_mask = (1U << lsb) - 1; 1440 1441 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1442 return S; 1443 } 1444 1445 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1446 uint64_t Address, const void *Decoder) { 1447 DecodeStatus S = MCDisassembler::Success; 1448 1449 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1450 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1451 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1452 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1453 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1454 unsigned U = fieldFromInstruction(Insn, 23, 1); 1455 const FeatureBitset &featureBits = 1456 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1457 1458 switch (Inst.getOpcode()) { 1459 case ARM::LDC_OFFSET: 1460 case ARM::LDC_PRE: 1461 case ARM::LDC_POST: 1462 case ARM::LDC_OPTION: 1463 case ARM::LDCL_OFFSET: 1464 case ARM::LDCL_PRE: 1465 case ARM::LDCL_POST: 1466 case ARM::LDCL_OPTION: 1467 case ARM::STC_OFFSET: 1468 case ARM::STC_PRE: 1469 case ARM::STC_POST: 1470 case ARM::STC_OPTION: 1471 case ARM::STCL_OFFSET: 1472 case ARM::STCL_PRE: 1473 case ARM::STCL_POST: 1474 case ARM::STCL_OPTION: 1475 case ARM::t2LDC_OFFSET: 1476 case ARM::t2LDC_PRE: 1477 case ARM::t2LDC_POST: 1478 case ARM::t2LDC_OPTION: 1479 case ARM::t2LDCL_OFFSET: 1480 case ARM::t2LDCL_PRE: 1481 case ARM::t2LDCL_POST: 1482 case ARM::t2LDCL_OPTION: 1483 case ARM::t2STC_OFFSET: 1484 case ARM::t2STC_PRE: 1485 case ARM::t2STC_POST: 1486 case ARM::t2STC_OPTION: 1487 case ARM::t2STCL_OFFSET: 1488 case ARM::t2STCL_PRE: 1489 case ARM::t2STCL_POST: 1490 case ARM::t2STCL_OPTION: 1491 case ARM::t2LDC2_OFFSET: 1492 case ARM::t2LDC2L_OFFSET: 1493 case ARM::t2LDC2_PRE: 1494 case ARM::t2LDC2L_PRE: 1495 case ARM::t2STC2_OFFSET: 1496 case ARM::t2STC2L_OFFSET: 1497 case ARM::t2STC2_PRE: 1498 case ARM::t2STC2L_PRE: 1499 case ARM::LDC2_OFFSET: 1500 case ARM::LDC2L_OFFSET: 1501 case ARM::LDC2_PRE: 1502 case ARM::LDC2L_PRE: 1503 case ARM::STC2_OFFSET: 1504 case ARM::STC2L_OFFSET: 1505 case ARM::STC2_PRE: 1506 case ARM::STC2L_PRE: 1507 case ARM::t2LDC2_OPTION: 1508 case ARM::t2STC2_OPTION: 1509 case ARM::t2LDC2_POST: 1510 case ARM::t2LDC2L_POST: 1511 case ARM::t2STC2_POST: 1512 case ARM::t2STC2L_POST: 1513 case ARM::LDC2_POST: 1514 case ARM::LDC2L_POST: 1515 case ARM::STC2_POST: 1516 case ARM::STC2L_POST: 1517 if (coproc == 0xA || coproc == 0xB || 1518 (featureBits[ARM::HasV8_1MMainlineOps] && 1519 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1520 coproc == 0xE || coproc == 0xF))) 1521 return MCDisassembler::Fail; 1522 break; 1523 default: 1524 break; 1525 } 1526 1527 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1528 return MCDisassembler::Fail; 1529 1530 Inst.addOperand(MCOperand::createImm(coproc)); 1531 Inst.addOperand(MCOperand::createImm(CRd)); 1532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1533 return MCDisassembler::Fail; 1534 1535 switch (Inst.getOpcode()) { 1536 case ARM::t2LDC2_OFFSET: 1537 case ARM::t2LDC2L_OFFSET: 1538 case ARM::t2LDC2_PRE: 1539 case ARM::t2LDC2L_PRE: 1540 case ARM::t2STC2_OFFSET: 1541 case ARM::t2STC2L_OFFSET: 1542 case ARM::t2STC2_PRE: 1543 case ARM::t2STC2L_PRE: 1544 case ARM::LDC2_OFFSET: 1545 case ARM::LDC2L_OFFSET: 1546 case ARM::LDC2_PRE: 1547 case ARM::LDC2L_PRE: 1548 case ARM::STC2_OFFSET: 1549 case ARM::STC2L_OFFSET: 1550 case ARM::STC2_PRE: 1551 case ARM::STC2L_PRE: 1552 case ARM::t2LDC_OFFSET: 1553 case ARM::t2LDCL_OFFSET: 1554 case ARM::t2LDC_PRE: 1555 case ARM::t2LDCL_PRE: 1556 case ARM::t2STC_OFFSET: 1557 case ARM::t2STCL_OFFSET: 1558 case ARM::t2STC_PRE: 1559 case ARM::t2STCL_PRE: 1560 case ARM::LDC_OFFSET: 1561 case ARM::LDCL_OFFSET: 1562 case ARM::LDC_PRE: 1563 case ARM::LDCL_PRE: 1564 case ARM::STC_OFFSET: 1565 case ARM::STCL_OFFSET: 1566 case ARM::STC_PRE: 1567 case ARM::STCL_PRE: 1568 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1569 Inst.addOperand(MCOperand::createImm(imm)); 1570 break; 1571 case ARM::t2LDC2_POST: 1572 case ARM::t2LDC2L_POST: 1573 case ARM::t2STC2_POST: 1574 case ARM::t2STC2L_POST: 1575 case ARM::LDC2_POST: 1576 case ARM::LDC2L_POST: 1577 case ARM::STC2_POST: 1578 case ARM::STC2L_POST: 1579 case ARM::t2LDC_POST: 1580 case ARM::t2LDCL_POST: 1581 case ARM::t2STC_POST: 1582 case ARM::t2STCL_POST: 1583 case ARM::LDC_POST: 1584 case ARM::LDCL_POST: 1585 case ARM::STC_POST: 1586 case ARM::STCL_POST: 1587 imm |= U << 8; 1588 LLVM_FALLTHROUGH; 1589 default: 1590 // The 'option' variant doesn't encode 'U' in the immediate since 1591 // the immediate is unsigned [0,255]. 1592 Inst.addOperand(MCOperand::createImm(imm)); 1593 break; 1594 } 1595 1596 switch (Inst.getOpcode()) { 1597 case ARM::LDC_OFFSET: 1598 case ARM::LDC_PRE: 1599 case ARM::LDC_POST: 1600 case ARM::LDC_OPTION: 1601 case ARM::LDCL_OFFSET: 1602 case ARM::LDCL_PRE: 1603 case ARM::LDCL_POST: 1604 case ARM::LDCL_OPTION: 1605 case ARM::STC_OFFSET: 1606 case ARM::STC_PRE: 1607 case ARM::STC_POST: 1608 case ARM::STC_OPTION: 1609 case ARM::STCL_OFFSET: 1610 case ARM::STCL_PRE: 1611 case ARM::STCL_POST: 1612 case ARM::STCL_OPTION: 1613 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1614 return MCDisassembler::Fail; 1615 break; 1616 default: 1617 break; 1618 } 1619 1620 return S; 1621 } 1622 1623 static DecodeStatus 1624 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1625 uint64_t Address, const void *Decoder) { 1626 DecodeStatus S = MCDisassembler::Success; 1627 1628 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1629 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1630 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1631 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1632 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1633 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1634 unsigned P = fieldFromInstruction(Insn, 24, 1); 1635 unsigned W = fieldFromInstruction(Insn, 21, 1); 1636 1637 // On stores, the writeback operand precedes Rt. 1638 switch (Inst.getOpcode()) { 1639 case ARM::STR_POST_IMM: 1640 case ARM::STR_POST_REG: 1641 case ARM::STRB_POST_IMM: 1642 case ARM::STRB_POST_REG: 1643 case ARM::STRT_POST_REG: 1644 case ARM::STRT_POST_IMM: 1645 case ARM::STRBT_POST_REG: 1646 case ARM::STRBT_POST_IMM: 1647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1648 return MCDisassembler::Fail; 1649 break; 1650 default: 1651 break; 1652 } 1653 1654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1655 return MCDisassembler::Fail; 1656 1657 // On loads, the writeback operand comes after Rt. 1658 switch (Inst.getOpcode()) { 1659 case ARM::LDR_POST_IMM: 1660 case ARM::LDR_POST_REG: 1661 case ARM::LDRB_POST_IMM: 1662 case ARM::LDRB_POST_REG: 1663 case ARM::LDRBT_POST_REG: 1664 case ARM::LDRBT_POST_IMM: 1665 case ARM::LDRT_POST_REG: 1666 case ARM::LDRT_POST_IMM: 1667 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1668 return MCDisassembler::Fail; 1669 break; 1670 default: 1671 break; 1672 } 1673 1674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1675 return MCDisassembler::Fail; 1676 1677 ARM_AM::AddrOpc Op = ARM_AM::add; 1678 if (!fieldFromInstruction(Insn, 23, 1)) 1679 Op = ARM_AM::sub; 1680 1681 bool writeback = (P == 0) || (W == 1); 1682 unsigned idx_mode = 0; 1683 if (P && writeback) 1684 idx_mode = ARMII::IndexModePre; 1685 else if (!P && writeback) 1686 idx_mode = ARMII::IndexModePost; 1687 1688 if (writeback && (Rn == 15 || Rn == Rt)) 1689 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1690 1691 if (reg) { 1692 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1693 return MCDisassembler::Fail; 1694 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1695 switch( fieldFromInstruction(Insn, 5, 2)) { 1696 case 0: 1697 Opc = ARM_AM::lsl; 1698 break; 1699 case 1: 1700 Opc = ARM_AM::lsr; 1701 break; 1702 case 2: 1703 Opc = ARM_AM::asr; 1704 break; 1705 case 3: 1706 Opc = ARM_AM::ror; 1707 break; 1708 default: 1709 return MCDisassembler::Fail; 1710 } 1711 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1712 if (Opc == ARM_AM::ror && amt == 0) 1713 Opc = ARM_AM::rrx; 1714 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1715 1716 Inst.addOperand(MCOperand::createImm(imm)); 1717 } else { 1718 Inst.addOperand(MCOperand::createReg(0)); 1719 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1720 Inst.addOperand(MCOperand::createImm(tmp)); 1721 } 1722 1723 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1724 return MCDisassembler::Fail; 1725 1726 return S; 1727 } 1728 1729 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1730 uint64_t Address, const void *Decoder) { 1731 DecodeStatus S = MCDisassembler::Success; 1732 1733 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1734 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1735 unsigned type = fieldFromInstruction(Val, 5, 2); 1736 unsigned imm = fieldFromInstruction(Val, 7, 5); 1737 unsigned U = fieldFromInstruction(Val, 12, 1); 1738 1739 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1740 switch (type) { 1741 case 0: 1742 ShOp = ARM_AM::lsl; 1743 break; 1744 case 1: 1745 ShOp = ARM_AM::lsr; 1746 break; 1747 case 2: 1748 ShOp = ARM_AM::asr; 1749 break; 1750 case 3: 1751 ShOp = ARM_AM::ror; 1752 break; 1753 } 1754 1755 if (ShOp == ARM_AM::ror && imm == 0) 1756 ShOp = ARM_AM::rrx; 1757 1758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1759 return MCDisassembler::Fail; 1760 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1761 return MCDisassembler::Fail; 1762 unsigned shift; 1763 if (U) 1764 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1765 else 1766 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1767 Inst.addOperand(MCOperand::createImm(shift)); 1768 1769 return S; 1770 } 1771 1772 static DecodeStatus 1773 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1774 uint64_t Address, const void *Decoder) { 1775 DecodeStatus S = MCDisassembler::Success; 1776 1777 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1778 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1779 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1780 unsigned type = fieldFromInstruction(Insn, 22, 1); 1781 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1782 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1783 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1784 unsigned W = fieldFromInstruction(Insn, 21, 1); 1785 unsigned P = fieldFromInstruction(Insn, 24, 1); 1786 unsigned Rt2 = Rt + 1; 1787 1788 bool writeback = (W == 1) | (P == 0); 1789 1790 // For {LD,ST}RD, Rt must be even, else undefined. 1791 switch (Inst.getOpcode()) { 1792 case ARM::STRD: 1793 case ARM::STRD_PRE: 1794 case ARM::STRD_POST: 1795 case ARM::LDRD: 1796 case ARM::LDRD_PRE: 1797 case ARM::LDRD_POST: 1798 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1799 break; 1800 default: 1801 break; 1802 } 1803 switch (Inst.getOpcode()) { 1804 case ARM::STRD: 1805 case ARM::STRD_PRE: 1806 case ARM::STRD_POST: 1807 if (P == 0 && W == 1) 1808 S = MCDisassembler::SoftFail; 1809 1810 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1811 S = MCDisassembler::SoftFail; 1812 if (type && Rm == 15) 1813 S = MCDisassembler::SoftFail; 1814 if (Rt2 == 15) 1815 S = MCDisassembler::SoftFail; 1816 if (!type && fieldFromInstruction(Insn, 8, 4)) 1817 S = MCDisassembler::SoftFail; 1818 break; 1819 case ARM::STRH: 1820 case ARM::STRH_PRE: 1821 case ARM::STRH_POST: 1822 if (Rt == 15) 1823 S = MCDisassembler::SoftFail; 1824 if (writeback && (Rn == 15 || Rn == Rt)) 1825 S = MCDisassembler::SoftFail; 1826 if (!type && Rm == 15) 1827 S = MCDisassembler::SoftFail; 1828 break; 1829 case ARM::LDRD: 1830 case ARM::LDRD_PRE: 1831 case ARM::LDRD_POST: 1832 if (type && Rn == 15) { 1833 if (Rt2 == 15) 1834 S = MCDisassembler::SoftFail; 1835 break; 1836 } 1837 if (P == 0 && W == 1) 1838 S = MCDisassembler::SoftFail; 1839 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1840 S = MCDisassembler::SoftFail; 1841 if (!type && writeback && Rn == 15) 1842 S = MCDisassembler::SoftFail; 1843 if (writeback && (Rn == Rt || Rn == Rt2)) 1844 S = MCDisassembler::SoftFail; 1845 break; 1846 case ARM::LDRH: 1847 case ARM::LDRH_PRE: 1848 case ARM::LDRH_POST: 1849 if (type && Rn == 15) { 1850 if (Rt == 15) 1851 S = MCDisassembler::SoftFail; 1852 break; 1853 } 1854 if (Rt == 15) 1855 S = MCDisassembler::SoftFail; 1856 if (!type && Rm == 15) 1857 S = MCDisassembler::SoftFail; 1858 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1859 S = MCDisassembler::SoftFail; 1860 break; 1861 case ARM::LDRSH: 1862 case ARM::LDRSH_PRE: 1863 case ARM::LDRSH_POST: 1864 case ARM::LDRSB: 1865 case ARM::LDRSB_PRE: 1866 case ARM::LDRSB_POST: 1867 if (type && Rn == 15) { 1868 if (Rt == 15) 1869 S = MCDisassembler::SoftFail; 1870 break; 1871 } 1872 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1873 S = MCDisassembler::SoftFail; 1874 if (!type && (Rt == 15 || Rm == 15)) 1875 S = MCDisassembler::SoftFail; 1876 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1877 S = MCDisassembler::SoftFail; 1878 break; 1879 default: 1880 break; 1881 } 1882 1883 if (writeback) { // Writeback 1884 if (P) 1885 U |= ARMII::IndexModePre << 9; 1886 else 1887 U |= ARMII::IndexModePost << 9; 1888 1889 // On stores, the writeback operand precedes Rt. 1890 switch (Inst.getOpcode()) { 1891 case ARM::STRD: 1892 case ARM::STRD_PRE: 1893 case ARM::STRD_POST: 1894 case ARM::STRH: 1895 case ARM::STRH_PRE: 1896 case ARM::STRH_POST: 1897 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1898 return MCDisassembler::Fail; 1899 break; 1900 default: 1901 break; 1902 } 1903 } 1904 1905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1906 return MCDisassembler::Fail; 1907 switch (Inst.getOpcode()) { 1908 case ARM::STRD: 1909 case ARM::STRD_PRE: 1910 case ARM::STRD_POST: 1911 case ARM::LDRD: 1912 case ARM::LDRD_PRE: 1913 case ARM::LDRD_POST: 1914 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1915 return MCDisassembler::Fail; 1916 break; 1917 default: 1918 break; 1919 } 1920 1921 if (writeback) { 1922 // On loads, the writeback operand comes after Rt. 1923 switch (Inst.getOpcode()) { 1924 case ARM::LDRD: 1925 case ARM::LDRD_PRE: 1926 case ARM::LDRD_POST: 1927 case ARM::LDRH: 1928 case ARM::LDRH_PRE: 1929 case ARM::LDRH_POST: 1930 case ARM::LDRSH: 1931 case ARM::LDRSH_PRE: 1932 case ARM::LDRSH_POST: 1933 case ARM::LDRSB: 1934 case ARM::LDRSB_PRE: 1935 case ARM::LDRSB_POST: 1936 case ARM::LDRHTr: 1937 case ARM::LDRSBTr: 1938 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1939 return MCDisassembler::Fail; 1940 break; 1941 default: 1942 break; 1943 } 1944 } 1945 1946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1947 return MCDisassembler::Fail; 1948 1949 if (type) { 1950 Inst.addOperand(MCOperand::createReg(0)); 1951 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1952 } else { 1953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1954 return MCDisassembler::Fail; 1955 Inst.addOperand(MCOperand::createImm(U)); 1956 } 1957 1958 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1959 return MCDisassembler::Fail; 1960 1961 return S; 1962 } 1963 1964 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1965 uint64_t Address, const void *Decoder) { 1966 DecodeStatus S = MCDisassembler::Success; 1967 1968 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1969 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1970 1971 switch (mode) { 1972 case 0: 1973 mode = ARM_AM::da; 1974 break; 1975 case 1: 1976 mode = ARM_AM::ia; 1977 break; 1978 case 2: 1979 mode = ARM_AM::db; 1980 break; 1981 case 3: 1982 mode = ARM_AM::ib; 1983 break; 1984 } 1985 1986 Inst.addOperand(MCOperand::createImm(mode)); 1987 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1988 return MCDisassembler::Fail; 1989 1990 return S; 1991 } 1992 1993 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1994 uint64_t Address, const void *Decoder) { 1995 DecodeStatus S = MCDisassembler::Success; 1996 1997 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1998 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1999 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2000 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2001 2002 if (pred == 0xF) 2003 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2004 2005 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2006 return MCDisassembler::Fail; 2007 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2008 return MCDisassembler::Fail; 2009 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2010 return MCDisassembler::Fail; 2011 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2012 return MCDisassembler::Fail; 2013 return S; 2014 } 2015 2016 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2017 unsigned Insn, 2018 uint64_t Address, const void *Decoder) { 2019 DecodeStatus S = MCDisassembler::Success; 2020 2021 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2022 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2023 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2024 2025 if (pred == 0xF) { 2026 // Ambiguous with RFE and SRS 2027 switch (Inst.getOpcode()) { 2028 case ARM::LDMDA: 2029 Inst.setOpcode(ARM::RFEDA); 2030 break; 2031 case ARM::LDMDA_UPD: 2032 Inst.setOpcode(ARM::RFEDA_UPD); 2033 break; 2034 case ARM::LDMDB: 2035 Inst.setOpcode(ARM::RFEDB); 2036 break; 2037 case ARM::LDMDB_UPD: 2038 Inst.setOpcode(ARM::RFEDB_UPD); 2039 break; 2040 case ARM::LDMIA: 2041 Inst.setOpcode(ARM::RFEIA); 2042 break; 2043 case ARM::LDMIA_UPD: 2044 Inst.setOpcode(ARM::RFEIA_UPD); 2045 break; 2046 case ARM::LDMIB: 2047 Inst.setOpcode(ARM::RFEIB); 2048 break; 2049 case ARM::LDMIB_UPD: 2050 Inst.setOpcode(ARM::RFEIB_UPD); 2051 break; 2052 case ARM::STMDA: 2053 Inst.setOpcode(ARM::SRSDA); 2054 break; 2055 case ARM::STMDA_UPD: 2056 Inst.setOpcode(ARM::SRSDA_UPD); 2057 break; 2058 case ARM::STMDB: 2059 Inst.setOpcode(ARM::SRSDB); 2060 break; 2061 case ARM::STMDB_UPD: 2062 Inst.setOpcode(ARM::SRSDB_UPD); 2063 break; 2064 case ARM::STMIA: 2065 Inst.setOpcode(ARM::SRSIA); 2066 break; 2067 case ARM::STMIA_UPD: 2068 Inst.setOpcode(ARM::SRSIA_UPD); 2069 break; 2070 case ARM::STMIB: 2071 Inst.setOpcode(ARM::SRSIB); 2072 break; 2073 case ARM::STMIB_UPD: 2074 Inst.setOpcode(ARM::SRSIB_UPD); 2075 break; 2076 default: 2077 return MCDisassembler::Fail; 2078 } 2079 2080 // For stores (which become SRS's, the only operand is the mode. 2081 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2082 // Check SRS encoding constraints 2083 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2084 fieldFromInstruction(Insn, 20, 1) == 0)) 2085 return MCDisassembler::Fail; 2086 2087 Inst.addOperand( 2088 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2089 return S; 2090 } 2091 2092 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2093 } 2094 2095 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2096 return MCDisassembler::Fail; 2097 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2098 return MCDisassembler::Fail; // Tied 2099 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2100 return MCDisassembler::Fail; 2101 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2102 return MCDisassembler::Fail; 2103 2104 return S; 2105 } 2106 2107 // Check for UNPREDICTABLE predicated ESB instruction 2108 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2109 uint64_t Address, const void *Decoder) { 2110 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2111 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2112 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2113 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2114 2115 DecodeStatus S = MCDisassembler::Success; 2116 2117 Inst.addOperand(MCOperand::createImm(imm8)); 2118 2119 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2120 return MCDisassembler::Fail; 2121 2122 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2123 // so all predicates should be allowed. 2124 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2125 S = MCDisassembler::SoftFail; 2126 2127 return S; 2128 } 2129 2130 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2131 uint64_t Address, const void *Decoder) { 2132 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2133 unsigned M = fieldFromInstruction(Insn, 17, 1); 2134 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2135 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2136 2137 DecodeStatus S = MCDisassembler::Success; 2138 2139 // This decoder is called from multiple location that do not check 2140 // the full encoding is valid before they do. 2141 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2142 fieldFromInstruction(Insn, 16, 1) != 0 || 2143 fieldFromInstruction(Insn, 20, 8) != 0x10) 2144 return MCDisassembler::Fail; 2145 2146 // imod == '01' --> UNPREDICTABLE 2147 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2148 // return failure here. The '01' imod value is unprintable, so there's 2149 // nothing useful we could do even if we returned UNPREDICTABLE. 2150 2151 if (imod == 1) return MCDisassembler::Fail; 2152 2153 if (imod && M) { 2154 Inst.setOpcode(ARM::CPS3p); 2155 Inst.addOperand(MCOperand::createImm(imod)); 2156 Inst.addOperand(MCOperand::createImm(iflags)); 2157 Inst.addOperand(MCOperand::createImm(mode)); 2158 } else if (imod && !M) { 2159 Inst.setOpcode(ARM::CPS2p); 2160 Inst.addOperand(MCOperand::createImm(imod)); 2161 Inst.addOperand(MCOperand::createImm(iflags)); 2162 if (mode) S = MCDisassembler::SoftFail; 2163 } else if (!imod && M) { 2164 Inst.setOpcode(ARM::CPS1p); 2165 Inst.addOperand(MCOperand::createImm(mode)); 2166 if (iflags) S = MCDisassembler::SoftFail; 2167 } else { 2168 // imod == '00' && M == '0' --> UNPREDICTABLE 2169 Inst.setOpcode(ARM::CPS1p); 2170 Inst.addOperand(MCOperand::createImm(mode)); 2171 S = MCDisassembler::SoftFail; 2172 } 2173 2174 return S; 2175 } 2176 2177 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2178 uint64_t Address, const void *Decoder) { 2179 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2180 unsigned M = fieldFromInstruction(Insn, 8, 1); 2181 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2182 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2183 2184 DecodeStatus S = MCDisassembler::Success; 2185 2186 // imod == '01' --> UNPREDICTABLE 2187 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2188 // return failure here. The '01' imod value is unprintable, so there's 2189 // nothing useful we could do even if we returned UNPREDICTABLE. 2190 2191 if (imod == 1) return MCDisassembler::Fail; 2192 2193 if (imod && M) { 2194 Inst.setOpcode(ARM::t2CPS3p); 2195 Inst.addOperand(MCOperand::createImm(imod)); 2196 Inst.addOperand(MCOperand::createImm(iflags)); 2197 Inst.addOperand(MCOperand::createImm(mode)); 2198 } else if (imod && !M) { 2199 Inst.setOpcode(ARM::t2CPS2p); 2200 Inst.addOperand(MCOperand::createImm(imod)); 2201 Inst.addOperand(MCOperand::createImm(iflags)); 2202 if (mode) S = MCDisassembler::SoftFail; 2203 } else if (!imod && M) { 2204 Inst.setOpcode(ARM::t2CPS1p); 2205 Inst.addOperand(MCOperand::createImm(mode)); 2206 if (iflags) S = MCDisassembler::SoftFail; 2207 } else { 2208 // imod == '00' && M == '0' --> this is a HINT instruction 2209 int imm = fieldFromInstruction(Insn, 0, 8); 2210 // HINT are defined only for immediate in [0..4] 2211 if(imm > 4) return MCDisassembler::Fail; 2212 Inst.setOpcode(ARM::t2HINT); 2213 Inst.addOperand(MCOperand::createImm(imm)); 2214 } 2215 2216 return S; 2217 } 2218 2219 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2220 uint64_t Address, const void *Decoder) { 2221 DecodeStatus S = MCDisassembler::Success; 2222 2223 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2224 unsigned imm = 0; 2225 2226 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2227 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2228 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2229 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2230 2231 if (Inst.getOpcode() == ARM::t2MOVTi16) 2232 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2233 return MCDisassembler::Fail; 2234 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2235 return MCDisassembler::Fail; 2236 2237 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2238 Inst.addOperand(MCOperand::createImm(imm)); 2239 2240 return S; 2241 } 2242 2243 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2244 uint64_t Address, const void *Decoder) { 2245 DecodeStatus S = MCDisassembler::Success; 2246 2247 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2248 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2249 unsigned imm = 0; 2250 2251 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2252 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2253 2254 if (Inst.getOpcode() == ARM::MOVTi16) 2255 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2256 return MCDisassembler::Fail; 2257 2258 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2259 return MCDisassembler::Fail; 2260 2261 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2262 Inst.addOperand(MCOperand::createImm(imm)); 2263 2264 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2265 return MCDisassembler::Fail; 2266 2267 return S; 2268 } 2269 2270 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2271 uint64_t Address, const void *Decoder) { 2272 DecodeStatus S = MCDisassembler::Success; 2273 2274 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2275 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2276 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2277 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2278 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2279 2280 if (pred == 0xF) 2281 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2282 2283 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2284 return MCDisassembler::Fail; 2285 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2286 return MCDisassembler::Fail; 2287 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2288 return MCDisassembler::Fail; 2289 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2290 return MCDisassembler::Fail; 2291 2292 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2293 return MCDisassembler::Fail; 2294 2295 return S; 2296 } 2297 2298 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2299 uint64_t Address, const void *Decoder) { 2300 DecodeStatus S = MCDisassembler::Success; 2301 2302 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2303 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2304 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2305 2306 if (Pred == 0xF) 2307 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2308 2309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2310 return MCDisassembler::Fail; 2311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2312 return MCDisassembler::Fail; 2313 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2314 return MCDisassembler::Fail; 2315 2316 return S; 2317 } 2318 2319 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2320 uint64_t Address, const void *Decoder) { 2321 DecodeStatus S = MCDisassembler::Success; 2322 2323 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2324 2325 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2326 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2327 2328 if (!FeatureBits[ARM::HasV8_1aOps] || 2329 !FeatureBits[ARM::HasV8Ops]) 2330 return MCDisassembler::Fail; 2331 2332 // Decoder can be called from DecodeTST, which does not check the full 2333 // encoding is valid. 2334 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2335 fieldFromInstruction(Insn, 4,4) != 0) 2336 return MCDisassembler::Fail; 2337 if (fieldFromInstruction(Insn, 10,10) != 0 || 2338 fieldFromInstruction(Insn, 0,4) != 0) 2339 S = MCDisassembler::SoftFail; 2340 2341 Inst.setOpcode(ARM::SETPAN); 2342 Inst.addOperand(MCOperand::createImm(Imm)); 2343 2344 return S; 2345 } 2346 2347 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2348 uint64_t Address, const void *Decoder) { 2349 DecodeStatus S = MCDisassembler::Success; 2350 2351 unsigned add = fieldFromInstruction(Val, 12, 1); 2352 unsigned imm = fieldFromInstruction(Val, 0, 12); 2353 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2354 2355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2356 return MCDisassembler::Fail; 2357 2358 if (!add) imm *= -1; 2359 if (imm == 0 && !add) imm = INT32_MIN; 2360 Inst.addOperand(MCOperand::createImm(imm)); 2361 if (Rn == 15) 2362 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2363 2364 return S; 2365 } 2366 2367 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2368 uint64_t Address, const void *Decoder) { 2369 DecodeStatus S = MCDisassembler::Success; 2370 2371 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2372 // U == 1 to add imm, 0 to subtract it. 2373 unsigned U = fieldFromInstruction(Val, 8, 1); 2374 unsigned imm = fieldFromInstruction(Val, 0, 8); 2375 2376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2377 return MCDisassembler::Fail; 2378 2379 if (U) 2380 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2381 else 2382 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2383 2384 return S; 2385 } 2386 2387 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2388 uint64_t Address, const void *Decoder) { 2389 DecodeStatus S = MCDisassembler::Success; 2390 2391 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2392 // U == 1 to add imm, 0 to subtract it. 2393 unsigned U = fieldFromInstruction(Val, 8, 1); 2394 unsigned imm = fieldFromInstruction(Val, 0, 8); 2395 2396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2397 return MCDisassembler::Fail; 2398 2399 if (U) 2400 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2401 else 2402 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2403 2404 return S; 2405 } 2406 2407 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2408 uint64_t Address, const void *Decoder) { 2409 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2410 } 2411 2412 static DecodeStatus 2413 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2414 uint64_t Address, const void *Decoder) { 2415 DecodeStatus Status = MCDisassembler::Success; 2416 2417 // Note the J1 and J2 values are from the encoded instruction. So here 2418 // change them to I1 and I2 values via as documented: 2419 // I1 = NOT(J1 EOR S); 2420 // I2 = NOT(J2 EOR S); 2421 // and build the imm32 with one trailing zero as documented: 2422 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2423 unsigned S = fieldFromInstruction(Insn, 26, 1); 2424 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2425 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2426 unsigned I1 = !(J1 ^ S); 2427 unsigned I2 = !(J2 ^ S); 2428 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2429 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2430 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2431 int imm32 = SignExtend32<25>(tmp << 1); 2432 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2433 true, 4, Inst, Decoder)) 2434 Inst.addOperand(MCOperand::createImm(imm32)); 2435 2436 return Status; 2437 } 2438 2439 static DecodeStatus 2440 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2441 uint64_t Address, const void *Decoder) { 2442 DecodeStatus S = MCDisassembler::Success; 2443 2444 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2445 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2446 2447 if (pred == 0xF) { 2448 Inst.setOpcode(ARM::BLXi); 2449 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2450 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2451 true, 4, Inst, Decoder)) 2452 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2453 return S; 2454 } 2455 2456 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2457 true, 4, Inst, Decoder)) 2458 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2459 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2460 return MCDisassembler::Fail; 2461 2462 return S; 2463 } 2464 2465 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2466 uint64_t Address, const void *Decoder) { 2467 DecodeStatus S = MCDisassembler::Success; 2468 2469 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2470 unsigned align = fieldFromInstruction(Val, 4, 2); 2471 2472 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2473 return MCDisassembler::Fail; 2474 if (!align) 2475 Inst.addOperand(MCOperand::createImm(0)); 2476 else 2477 Inst.addOperand(MCOperand::createImm(4 << align)); 2478 2479 return S; 2480 } 2481 2482 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2483 uint64_t Address, const void *Decoder) { 2484 DecodeStatus S = MCDisassembler::Success; 2485 2486 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2487 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2488 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2489 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2490 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2491 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2492 2493 // First output register 2494 switch (Inst.getOpcode()) { 2495 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2496 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2497 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2498 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2499 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2500 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2501 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2502 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2503 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2504 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2505 return MCDisassembler::Fail; 2506 break; 2507 case ARM::VLD2b16: 2508 case ARM::VLD2b32: 2509 case ARM::VLD2b8: 2510 case ARM::VLD2b16wb_fixed: 2511 case ARM::VLD2b16wb_register: 2512 case ARM::VLD2b32wb_fixed: 2513 case ARM::VLD2b32wb_register: 2514 case ARM::VLD2b8wb_fixed: 2515 case ARM::VLD2b8wb_register: 2516 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2517 return MCDisassembler::Fail; 2518 break; 2519 default: 2520 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2521 return MCDisassembler::Fail; 2522 } 2523 2524 // Second output register 2525 switch (Inst.getOpcode()) { 2526 case ARM::VLD3d8: 2527 case ARM::VLD3d16: 2528 case ARM::VLD3d32: 2529 case ARM::VLD3d8_UPD: 2530 case ARM::VLD3d16_UPD: 2531 case ARM::VLD3d32_UPD: 2532 case ARM::VLD4d8: 2533 case ARM::VLD4d16: 2534 case ARM::VLD4d32: 2535 case ARM::VLD4d8_UPD: 2536 case ARM::VLD4d16_UPD: 2537 case ARM::VLD4d32_UPD: 2538 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2539 return MCDisassembler::Fail; 2540 break; 2541 case ARM::VLD3q8: 2542 case ARM::VLD3q16: 2543 case ARM::VLD3q32: 2544 case ARM::VLD3q8_UPD: 2545 case ARM::VLD3q16_UPD: 2546 case ARM::VLD3q32_UPD: 2547 case ARM::VLD4q8: 2548 case ARM::VLD4q16: 2549 case ARM::VLD4q32: 2550 case ARM::VLD4q8_UPD: 2551 case ARM::VLD4q16_UPD: 2552 case ARM::VLD4q32_UPD: 2553 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2554 return MCDisassembler::Fail; 2555 break; 2556 default: 2557 break; 2558 } 2559 2560 // Third output register 2561 switch(Inst.getOpcode()) { 2562 case ARM::VLD3d8: 2563 case ARM::VLD3d16: 2564 case ARM::VLD3d32: 2565 case ARM::VLD3d8_UPD: 2566 case ARM::VLD3d16_UPD: 2567 case ARM::VLD3d32_UPD: 2568 case ARM::VLD4d8: 2569 case ARM::VLD4d16: 2570 case ARM::VLD4d32: 2571 case ARM::VLD4d8_UPD: 2572 case ARM::VLD4d16_UPD: 2573 case ARM::VLD4d32_UPD: 2574 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2575 return MCDisassembler::Fail; 2576 break; 2577 case ARM::VLD3q8: 2578 case ARM::VLD3q16: 2579 case ARM::VLD3q32: 2580 case ARM::VLD3q8_UPD: 2581 case ARM::VLD3q16_UPD: 2582 case ARM::VLD3q32_UPD: 2583 case ARM::VLD4q8: 2584 case ARM::VLD4q16: 2585 case ARM::VLD4q32: 2586 case ARM::VLD4q8_UPD: 2587 case ARM::VLD4q16_UPD: 2588 case ARM::VLD4q32_UPD: 2589 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2590 return MCDisassembler::Fail; 2591 break; 2592 default: 2593 break; 2594 } 2595 2596 // Fourth output register 2597 switch (Inst.getOpcode()) { 2598 case ARM::VLD4d8: 2599 case ARM::VLD4d16: 2600 case ARM::VLD4d32: 2601 case ARM::VLD4d8_UPD: 2602 case ARM::VLD4d16_UPD: 2603 case ARM::VLD4d32_UPD: 2604 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2605 return MCDisassembler::Fail; 2606 break; 2607 case ARM::VLD4q8: 2608 case ARM::VLD4q16: 2609 case ARM::VLD4q32: 2610 case ARM::VLD4q8_UPD: 2611 case ARM::VLD4q16_UPD: 2612 case ARM::VLD4q32_UPD: 2613 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2614 return MCDisassembler::Fail; 2615 break; 2616 default: 2617 break; 2618 } 2619 2620 // Writeback operand 2621 switch (Inst.getOpcode()) { 2622 case ARM::VLD1d8wb_fixed: 2623 case ARM::VLD1d16wb_fixed: 2624 case ARM::VLD1d32wb_fixed: 2625 case ARM::VLD1d64wb_fixed: 2626 case ARM::VLD1d8wb_register: 2627 case ARM::VLD1d16wb_register: 2628 case ARM::VLD1d32wb_register: 2629 case ARM::VLD1d64wb_register: 2630 case ARM::VLD1q8wb_fixed: 2631 case ARM::VLD1q16wb_fixed: 2632 case ARM::VLD1q32wb_fixed: 2633 case ARM::VLD1q64wb_fixed: 2634 case ARM::VLD1q8wb_register: 2635 case ARM::VLD1q16wb_register: 2636 case ARM::VLD1q32wb_register: 2637 case ARM::VLD1q64wb_register: 2638 case ARM::VLD1d8Twb_fixed: 2639 case ARM::VLD1d8Twb_register: 2640 case ARM::VLD1d16Twb_fixed: 2641 case ARM::VLD1d16Twb_register: 2642 case ARM::VLD1d32Twb_fixed: 2643 case ARM::VLD1d32Twb_register: 2644 case ARM::VLD1d64Twb_fixed: 2645 case ARM::VLD1d64Twb_register: 2646 case ARM::VLD1d8Qwb_fixed: 2647 case ARM::VLD1d8Qwb_register: 2648 case ARM::VLD1d16Qwb_fixed: 2649 case ARM::VLD1d16Qwb_register: 2650 case ARM::VLD1d32Qwb_fixed: 2651 case ARM::VLD1d32Qwb_register: 2652 case ARM::VLD1d64Qwb_fixed: 2653 case ARM::VLD1d64Qwb_register: 2654 case ARM::VLD2d8wb_fixed: 2655 case ARM::VLD2d16wb_fixed: 2656 case ARM::VLD2d32wb_fixed: 2657 case ARM::VLD2q8wb_fixed: 2658 case ARM::VLD2q16wb_fixed: 2659 case ARM::VLD2q32wb_fixed: 2660 case ARM::VLD2d8wb_register: 2661 case ARM::VLD2d16wb_register: 2662 case ARM::VLD2d32wb_register: 2663 case ARM::VLD2q8wb_register: 2664 case ARM::VLD2q16wb_register: 2665 case ARM::VLD2q32wb_register: 2666 case ARM::VLD2b8wb_fixed: 2667 case ARM::VLD2b16wb_fixed: 2668 case ARM::VLD2b32wb_fixed: 2669 case ARM::VLD2b8wb_register: 2670 case ARM::VLD2b16wb_register: 2671 case ARM::VLD2b32wb_register: 2672 Inst.addOperand(MCOperand::createImm(0)); 2673 break; 2674 case ARM::VLD3d8_UPD: 2675 case ARM::VLD3d16_UPD: 2676 case ARM::VLD3d32_UPD: 2677 case ARM::VLD3q8_UPD: 2678 case ARM::VLD3q16_UPD: 2679 case ARM::VLD3q32_UPD: 2680 case ARM::VLD4d8_UPD: 2681 case ARM::VLD4d16_UPD: 2682 case ARM::VLD4d32_UPD: 2683 case ARM::VLD4q8_UPD: 2684 case ARM::VLD4q16_UPD: 2685 case ARM::VLD4q32_UPD: 2686 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2687 return MCDisassembler::Fail; 2688 break; 2689 default: 2690 break; 2691 } 2692 2693 // AddrMode6 Base (register+alignment) 2694 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2695 return MCDisassembler::Fail; 2696 2697 // AddrMode6 Offset (register) 2698 switch (Inst.getOpcode()) { 2699 default: 2700 // The below have been updated to have explicit am6offset split 2701 // between fixed and register offset. For those instructions not 2702 // yet updated, we need to add an additional reg0 operand for the 2703 // fixed variant. 2704 // 2705 // The fixed offset encodes as Rm == 0xd, so we check for that. 2706 if (Rm == 0xd) { 2707 Inst.addOperand(MCOperand::createReg(0)); 2708 break; 2709 } 2710 // Fall through to handle the register offset variant. 2711 LLVM_FALLTHROUGH; 2712 case ARM::VLD1d8wb_fixed: 2713 case ARM::VLD1d16wb_fixed: 2714 case ARM::VLD1d32wb_fixed: 2715 case ARM::VLD1d64wb_fixed: 2716 case ARM::VLD1d8Twb_fixed: 2717 case ARM::VLD1d16Twb_fixed: 2718 case ARM::VLD1d32Twb_fixed: 2719 case ARM::VLD1d64Twb_fixed: 2720 case ARM::VLD1d8Qwb_fixed: 2721 case ARM::VLD1d16Qwb_fixed: 2722 case ARM::VLD1d32Qwb_fixed: 2723 case ARM::VLD1d64Qwb_fixed: 2724 case ARM::VLD1d8wb_register: 2725 case ARM::VLD1d16wb_register: 2726 case ARM::VLD1d32wb_register: 2727 case ARM::VLD1d64wb_register: 2728 case ARM::VLD1q8wb_fixed: 2729 case ARM::VLD1q16wb_fixed: 2730 case ARM::VLD1q32wb_fixed: 2731 case ARM::VLD1q64wb_fixed: 2732 case ARM::VLD1q8wb_register: 2733 case ARM::VLD1q16wb_register: 2734 case ARM::VLD1q32wb_register: 2735 case ARM::VLD1q64wb_register: 2736 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2737 // variant encodes Rm == 0xf. Anything else is a register offset post- 2738 // increment and we need to add the register operand to the instruction. 2739 if (Rm != 0xD && Rm != 0xF && 2740 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2741 return MCDisassembler::Fail; 2742 break; 2743 case ARM::VLD2d8wb_fixed: 2744 case ARM::VLD2d16wb_fixed: 2745 case ARM::VLD2d32wb_fixed: 2746 case ARM::VLD2b8wb_fixed: 2747 case ARM::VLD2b16wb_fixed: 2748 case ARM::VLD2b32wb_fixed: 2749 case ARM::VLD2q8wb_fixed: 2750 case ARM::VLD2q16wb_fixed: 2751 case ARM::VLD2q32wb_fixed: 2752 break; 2753 } 2754 2755 return S; 2756 } 2757 2758 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2759 uint64_t Address, const void *Decoder) { 2760 unsigned type = fieldFromInstruction(Insn, 8, 4); 2761 unsigned align = fieldFromInstruction(Insn, 4, 2); 2762 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2763 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2764 if (type == 10 && align == 3) return MCDisassembler::Fail; 2765 2766 unsigned load = fieldFromInstruction(Insn, 21, 1); 2767 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2768 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2769 } 2770 2771 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2772 uint64_t Address, const void *Decoder) { 2773 unsigned size = fieldFromInstruction(Insn, 6, 2); 2774 if (size == 3) return MCDisassembler::Fail; 2775 2776 unsigned type = fieldFromInstruction(Insn, 8, 4); 2777 unsigned align = fieldFromInstruction(Insn, 4, 2); 2778 if (type == 8 && align == 3) return MCDisassembler::Fail; 2779 if (type == 9 && align == 3) return MCDisassembler::Fail; 2780 2781 unsigned load = fieldFromInstruction(Insn, 21, 1); 2782 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2783 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2784 } 2785 2786 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2787 uint64_t Address, const void *Decoder) { 2788 unsigned size = fieldFromInstruction(Insn, 6, 2); 2789 if (size == 3) return MCDisassembler::Fail; 2790 2791 unsigned align = fieldFromInstruction(Insn, 4, 2); 2792 if (align & 2) return MCDisassembler::Fail; 2793 2794 unsigned load = fieldFromInstruction(Insn, 21, 1); 2795 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2796 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2797 } 2798 2799 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2800 uint64_t Address, const void *Decoder) { 2801 unsigned size = fieldFromInstruction(Insn, 6, 2); 2802 if (size == 3) return MCDisassembler::Fail; 2803 2804 unsigned load = fieldFromInstruction(Insn, 21, 1); 2805 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2806 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2807 } 2808 2809 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2810 uint64_t Address, const void *Decoder) { 2811 DecodeStatus S = MCDisassembler::Success; 2812 2813 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2814 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2815 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2816 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2817 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2818 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2819 2820 // Writeback Operand 2821 switch (Inst.getOpcode()) { 2822 case ARM::VST1d8wb_fixed: 2823 case ARM::VST1d16wb_fixed: 2824 case ARM::VST1d32wb_fixed: 2825 case ARM::VST1d64wb_fixed: 2826 case ARM::VST1d8wb_register: 2827 case ARM::VST1d16wb_register: 2828 case ARM::VST1d32wb_register: 2829 case ARM::VST1d64wb_register: 2830 case ARM::VST1q8wb_fixed: 2831 case ARM::VST1q16wb_fixed: 2832 case ARM::VST1q32wb_fixed: 2833 case ARM::VST1q64wb_fixed: 2834 case ARM::VST1q8wb_register: 2835 case ARM::VST1q16wb_register: 2836 case ARM::VST1q32wb_register: 2837 case ARM::VST1q64wb_register: 2838 case ARM::VST1d8Twb_fixed: 2839 case ARM::VST1d16Twb_fixed: 2840 case ARM::VST1d32Twb_fixed: 2841 case ARM::VST1d64Twb_fixed: 2842 case ARM::VST1d8Twb_register: 2843 case ARM::VST1d16Twb_register: 2844 case ARM::VST1d32Twb_register: 2845 case ARM::VST1d64Twb_register: 2846 case ARM::VST1d8Qwb_fixed: 2847 case ARM::VST1d16Qwb_fixed: 2848 case ARM::VST1d32Qwb_fixed: 2849 case ARM::VST1d64Qwb_fixed: 2850 case ARM::VST1d8Qwb_register: 2851 case ARM::VST1d16Qwb_register: 2852 case ARM::VST1d32Qwb_register: 2853 case ARM::VST1d64Qwb_register: 2854 case ARM::VST2d8wb_fixed: 2855 case ARM::VST2d16wb_fixed: 2856 case ARM::VST2d32wb_fixed: 2857 case ARM::VST2d8wb_register: 2858 case ARM::VST2d16wb_register: 2859 case ARM::VST2d32wb_register: 2860 case ARM::VST2q8wb_fixed: 2861 case ARM::VST2q16wb_fixed: 2862 case ARM::VST2q32wb_fixed: 2863 case ARM::VST2q8wb_register: 2864 case ARM::VST2q16wb_register: 2865 case ARM::VST2q32wb_register: 2866 case ARM::VST2b8wb_fixed: 2867 case ARM::VST2b16wb_fixed: 2868 case ARM::VST2b32wb_fixed: 2869 case ARM::VST2b8wb_register: 2870 case ARM::VST2b16wb_register: 2871 case ARM::VST2b32wb_register: 2872 if (Rm == 0xF) 2873 return MCDisassembler::Fail; 2874 Inst.addOperand(MCOperand::createImm(0)); 2875 break; 2876 case ARM::VST3d8_UPD: 2877 case ARM::VST3d16_UPD: 2878 case ARM::VST3d32_UPD: 2879 case ARM::VST3q8_UPD: 2880 case ARM::VST3q16_UPD: 2881 case ARM::VST3q32_UPD: 2882 case ARM::VST4d8_UPD: 2883 case ARM::VST4d16_UPD: 2884 case ARM::VST4d32_UPD: 2885 case ARM::VST4q8_UPD: 2886 case ARM::VST4q16_UPD: 2887 case ARM::VST4q32_UPD: 2888 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2889 return MCDisassembler::Fail; 2890 break; 2891 default: 2892 break; 2893 } 2894 2895 // AddrMode6 Base (register+alignment) 2896 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2897 return MCDisassembler::Fail; 2898 2899 // AddrMode6 Offset (register) 2900 switch (Inst.getOpcode()) { 2901 default: 2902 if (Rm == 0xD) 2903 Inst.addOperand(MCOperand::createReg(0)); 2904 else if (Rm != 0xF) { 2905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2906 return MCDisassembler::Fail; 2907 } 2908 break; 2909 case ARM::VST1d8wb_fixed: 2910 case ARM::VST1d16wb_fixed: 2911 case ARM::VST1d32wb_fixed: 2912 case ARM::VST1d64wb_fixed: 2913 case ARM::VST1q8wb_fixed: 2914 case ARM::VST1q16wb_fixed: 2915 case ARM::VST1q32wb_fixed: 2916 case ARM::VST1q64wb_fixed: 2917 case ARM::VST1d8Twb_fixed: 2918 case ARM::VST1d16Twb_fixed: 2919 case ARM::VST1d32Twb_fixed: 2920 case ARM::VST1d64Twb_fixed: 2921 case ARM::VST1d8Qwb_fixed: 2922 case ARM::VST1d16Qwb_fixed: 2923 case ARM::VST1d32Qwb_fixed: 2924 case ARM::VST1d64Qwb_fixed: 2925 case ARM::VST2d8wb_fixed: 2926 case ARM::VST2d16wb_fixed: 2927 case ARM::VST2d32wb_fixed: 2928 case ARM::VST2q8wb_fixed: 2929 case ARM::VST2q16wb_fixed: 2930 case ARM::VST2q32wb_fixed: 2931 case ARM::VST2b8wb_fixed: 2932 case ARM::VST2b16wb_fixed: 2933 case ARM::VST2b32wb_fixed: 2934 break; 2935 } 2936 2937 // First input register 2938 switch (Inst.getOpcode()) { 2939 case ARM::VST1q16: 2940 case ARM::VST1q32: 2941 case ARM::VST1q64: 2942 case ARM::VST1q8: 2943 case ARM::VST1q16wb_fixed: 2944 case ARM::VST1q16wb_register: 2945 case ARM::VST1q32wb_fixed: 2946 case ARM::VST1q32wb_register: 2947 case ARM::VST1q64wb_fixed: 2948 case ARM::VST1q64wb_register: 2949 case ARM::VST1q8wb_fixed: 2950 case ARM::VST1q8wb_register: 2951 case ARM::VST2d16: 2952 case ARM::VST2d32: 2953 case ARM::VST2d8: 2954 case ARM::VST2d16wb_fixed: 2955 case ARM::VST2d16wb_register: 2956 case ARM::VST2d32wb_fixed: 2957 case ARM::VST2d32wb_register: 2958 case ARM::VST2d8wb_fixed: 2959 case ARM::VST2d8wb_register: 2960 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2961 return MCDisassembler::Fail; 2962 break; 2963 case ARM::VST2b16: 2964 case ARM::VST2b32: 2965 case ARM::VST2b8: 2966 case ARM::VST2b16wb_fixed: 2967 case ARM::VST2b16wb_register: 2968 case ARM::VST2b32wb_fixed: 2969 case ARM::VST2b32wb_register: 2970 case ARM::VST2b8wb_fixed: 2971 case ARM::VST2b8wb_register: 2972 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2973 return MCDisassembler::Fail; 2974 break; 2975 default: 2976 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2977 return MCDisassembler::Fail; 2978 } 2979 2980 // Second input register 2981 switch (Inst.getOpcode()) { 2982 case ARM::VST3d8: 2983 case ARM::VST3d16: 2984 case ARM::VST3d32: 2985 case ARM::VST3d8_UPD: 2986 case ARM::VST3d16_UPD: 2987 case ARM::VST3d32_UPD: 2988 case ARM::VST4d8: 2989 case ARM::VST4d16: 2990 case ARM::VST4d32: 2991 case ARM::VST4d8_UPD: 2992 case ARM::VST4d16_UPD: 2993 case ARM::VST4d32_UPD: 2994 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2995 return MCDisassembler::Fail; 2996 break; 2997 case ARM::VST3q8: 2998 case ARM::VST3q16: 2999 case ARM::VST3q32: 3000 case ARM::VST3q8_UPD: 3001 case ARM::VST3q16_UPD: 3002 case ARM::VST3q32_UPD: 3003 case ARM::VST4q8: 3004 case ARM::VST4q16: 3005 case ARM::VST4q32: 3006 case ARM::VST4q8_UPD: 3007 case ARM::VST4q16_UPD: 3008 case ARM::VST4q32_UPD: 3009 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3010 return MCDisassembler::Fail; 3011 break; 3012 default: 3013 break; 3014 } 3015 3016 // Third input register 3017 switch (Inst.getOpcode()) { 3018 case ARM::VST3d8: 3019 case ARM::VST3d16: 3020 case ARM::VST3d32: 3021 case ARM::VST3d8_UPD: 3022 case ARM::VST3d16_UPD: 3023 case ARM::VST3d32_UPD: 3024 case ARM::VST4d8: 3025 case ARM::VST4d16: 3026 case ARM::VST4d32: 3027 case ARM::VST4d8_UPD: 3028 case ARM::VST4d16_UPD: 3029 case ARM::VST4d32_UPD: 3030 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3031 return MCDisassembler::Fail; 3032 break; 3033 case ARM::VST3q8: 3034 case ARM::VST3q16: 3035 case ARM::VST3q32: 3036 case ARM::VST3q8_UPD: 3037 case ARM::VST3q16_UPD: 3038 case ARM::VST3q32_UPD: 3039 case ARM::VST4q8: 3040 case ARM::VST4q16: 3041 case ARM::VST4q32: 3042 case ARM::VST4q8_UPD: 3043 case ARM::VST4q16_UPD: 3044 case ARM::VST4q32_UPD: 3045 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3046 return MCDisassembler::Fail; 3047 break; 3048 default: 3049 break; 3050 } 3051 3052 // Fourth input register 3053 switch (Inst.getOpcode()) { 3054 case ARM::VST4d8: 3055 case ARM::VST4d16: 3056 case ARM::VST4d32: 3057 case ARM::VST4d8_UPD: 3058 case ARM::VST4d16_UPD: 3059 case ARM::VST4d32_UPD: 3060 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3061 return MCDisassembler::Fail; 3062 break; 3063 case ARM::VST4q8: 3064 case ARM::VST4q16: 3065 case ARM::VST4q32: 3066 case ARM::VST4q8_UPD: 3067 case ARM::VST4q16_UPD: 3068 case ARM::VST4q32_UPD: 3069 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3070 return MCDisassembler::Fail; 3071 break; 3072 default: 3073 break; 3074 } 3075 3076 return S; 3077 } 3078 3079 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3080 uint64_t Address, const void *Decoder) { 3081 DecodeStatus S = MCDisassembler::Success; 3082 3083 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3084 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3085 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3086 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3087 unsigned align = fieldFromInstruction(Insn, 4, 1); 3088 unsigned size = fieldFromInstruction(Insn, 6, 2); 3089 3090 if (size == 0 && align == 1) 3091 return MCDisassembler::Fail; 3092 align *= (1 << size); 3093 3094 switch (Inst.getOpcode()) { 3095 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3096 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3097 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3098 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3099 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3100 return MCDisassembler::Fail; 3101 break; 3102 default: 3103 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3104 return MCDisassembler::Fail; 3105 break; 3106 } 3107 if (Rm != 0xF) { 3108 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3109 return MCDisassembler::Fail; 3110 } 3111 3112 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3113 return MCDisassembler::Fail; 3114 Inst.addOperand(MCOperand::createImm(align)); 3115 3116 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3117 // variant encodes Rm == 0xf. Anything else is a register offset post- 3118 // increment and we need to add the register operand to the instruction. 3119 if (Rm != 0xD && Rm != 0xF && 3120 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3121 return MCDisassembler::Fail; 3122 3123 return S; 3124 } 3125 3126 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3127 uint64_t Address, const void *Decoder) { 3128 DecodeStatus S = MCDisassembler::Success; 3129 3130 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3131 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3132 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3133 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3134 unsigned align = fieldFromInstruction(Insn, 4, 1); 3135 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3136 align *= 2*size; 3137 3138 switch (Inst.getOpcode()) { 3139 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3140 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3141 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3142 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3143 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3144 return MCDisassembler::Fail; 3145 break; 3146 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3147 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3148 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3149 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3150 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3151 return MCDisassembler::Fail; 3152 break; 3153 default: 3154 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3155 return MCDisassembler::Fail; 3156 break; 3157 } 3158 3159 if (Rm != 0xF) 3160 Inst.addOperand(MCOperand::createImm(0)); 3161 3162 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3163 return MCDisassembler::Fail; 3164 Inst.addOperand(MCOperand::createImm(align)); 3165 3166 if (Rm != 0xD && Rm != 0xF) { 3167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3168 return MCDisassembler::Fail; 3169 } 3170 3171 return S; 3172 } 3173 3174 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3175 uint64_t Address, const void *Decoder) { 3176 DecodeStatus S = MCDisassembler::Success; 3177 3178 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3179 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3180 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3181 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3182 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3183 3184 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3185 return MCDisassembler::Fail; 3186 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3189 return MCDisassembler::Fail; 3190 if (Rm != 0xF) { 3191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3192 return MCDisassembler::Fail; 3193 } 3194 3195 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3196 return MCDisassembler::Fail; 3197 Inst.addOperand(MCOperand::createImm(0)); 3198 3199 if (Rm == 0xD) 3200 Inst.addOperand(MCOperand::createReg(0)); 3201 else if (Rm != 0xF) { 3202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3203 return MCDisassembler::Fail; 3204 } 3205 3206 return S; 3207 } 3208 3209 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3210 uint64_t Address, const void *Decoder) { 3211 DecodeStatus S = MCDisassembler::Success; 3212 3213 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3214 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3215 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3216 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3217 unsigned size = fieldFromInstruction(Insn, 6, 2); 3218 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3219 unsigned align = fieldFromInstruction(Insn, 4, 1); 3220 3221 if (size == 0x3) { 3222 if (align == 0) 3223 return MCDisassembler::Fail; 3224 align = 16; 3225 } else { 3226 if (size == 2) { 3227 align *= 8; 3228 } else { 3229 size = 1 << size; 3230 align *= 4*size; 3231 } 3232 } 3233 3234 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3235 return MCDisassembler::Fail; 3236 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3237 return MCDisassembler::Fail; 3238 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3239 return MCDisassembler::Fail; 3240 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3241 return MCDisassembler::Fail; 3242 if (Rm != 0xF) { 3243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3244 return MCDisassembler::Fail; 3245 } 3246 3247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3248 return MCDisassembler::Fail; 3249 Inst.addOperand(MCOperand::createImm(align)); 3250 3251 if (Rm == 0xD) 3252 Inst.addOperand(MCOperand::createReg(0)); 3253 else if (Rm != 0xF) { 3254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3255 return MCDisassembler::Fail; 3256 } 3257 3258 return S; 3259 } 3260 3261 static DecodeStatus 3262 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3263 uint64_t Address, const void *Decoder) { 3264 DecodeStatus S = MCDisassembler::Success; 3265 3266 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3267 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3268 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3269 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3270 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3271 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3272 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3273 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3274 3275 if (Q) { 3276 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3277 return MCDisassembler::Fail; 3278 } else { 3279 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3280 return MCDisassembler::Fail; 3281 } 3282 3283 Inst.addOperand(MCOperand::createImm(imm)); 3284 3285 switch (Inst.getOpcode()) { 3286 case ARM::VORRiv4i16: 3287 case ARM::VORRiv2i32: 3288 case ARM::VBICiv4i16: 3289 case ARM::VBICiv2i32: 3290 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3291 return MCDisassembler::Fail; 3292 break; 3293 case ARM::VORRiv8i16: 3294 case ARM::VORRiv4i32: 3295 case ARM::VBICiv8i16: 3296 case ARM::VBICiv4i32: 3297 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3298 return MCDisassembler::Fail; 3299 break; 3300 default: 3301 break; 3302 } 3303 3304 return S; 3305 } 3306 3307 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3308 uint64_t Address, const void *Decoder) { 3309 DecodeStatus S = MCDisassembler::Success; 3310 3311 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3312 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3313 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3314 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3315 unsigned size = fieldFromInstruction(Insn, 18, 2); 3316 3317 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3318 return MCDisassembler::Fail; 3319 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3320 return MCDisassembler::Fail; 3321 Inst.addOperand(MCOperand::createImm(8 << size)); 3322 3323 return S; 3324 } 3325 3326 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3327 uint64_t Address, const void *Decoder) { 3328 Inst.addOperand(MCOperand::createImm(8 - Val)); 3329 return MCDisassembler::Success; 3330 } 3331 3332 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3333 uint64_t Address, const void *Decoder) { 3334 Inst.addOperand(MCOperand::createImm(16 - Val)); 3335 return MCDisassembler::Success; 3336 } 3337 3338 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3339 uint64_t Address, const void *Decoder) { 3340 Inst.addOperand(MCOperand::createImm(32 - Val)); 3341 return MCDisassembler::Success; 3342 } 3343 3344 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3345 uint64_t Address, const void *Decoder) { 3346 Inst.addOperand(MCOperand::createImm(64 - Val)); 3347 return MCDisassembler::Success; 3348 } 3349 3350 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3351 uint64_t Address, const void *Decoder) { 3352 DecodeStatus S = MCDisassembler::Success; 3353 3354 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3355 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3356 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3357 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3358 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3359 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3360 unsigned op = fieldFromInstruction(Insn, 6, 1); 3361 3362 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3363 return MCDisassembler::Fail; 3364 if (op) { 3365 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3366 return MCDisassembler::Fail; // Writeback 3367 } 3368 3369 switch (Inst.getOpcode()) { 3370 case ARM::VTBL2: 3371 case ARM::VTBX2: 3372 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3373 return MCDisassembler::Fail; 3374 break; 3375 default: 3376 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3377 return MCDisassembler::Fail; 3378 } 3379 3380 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3381 return MCDisassembler::Fail; 3382 3383 return S; 3384 } 3385 3386 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3387 uint64_t Address, const void *Decoder) { 3388 DecodeStatus S = MCDisassembler::Success; 3389 3390 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3391 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3392 3393 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3394 return MCDisassembler::Fail; 3395 3396 switch(Inst.getOpcode()) { 3397 default: 3398 return MCDisassembler::Fail; 3399 case ARM::tADR: 3400 break; // tADR does not explicitly represent the PC as an operand. 3401 case ARM::tADDrSPi: 3402 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3403 break; 3404 } 3405 3406 Inst.addOperand(MCOperand::createImm(imm)); 3407 return S; 3408 } 3409 3410 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3411 uint64_t Address, const void *Decoder) { 3412 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3413 true, 2, Inst, Decoder)) 3414 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3415 return MCDisassembler::Success; 3416 } 3417 3418 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3419 uint64_t Address, const void *Decoder) { 3420 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3421 true, 4, Inst, Decoder)) 3422 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3423 return MCDisassembler::Success; 3424 } 3425 3426 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3427 uint64_t Address, const void *Decoder) { 3428 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3429 true, 2, Inst, Decoder)) 3430 Inst.addOperand(MCOperand::createImm(Val << 1)); 3431 return MCDisassembler::Success; 3432 } 3433 3434 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3435 uint64_t Address, const void *Decoder) { 3436 DecodeStatus S = MCDisassembler::Success; 3437 3438 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3439 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3440 3441 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3444 return MCDisassembler::Fail; 3445 3446 return S; 3447 } 3448 3449 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3450 uint64_t Address, const void *Decoder) { 3451 DecodeStatus S = MCDisassembler::Success; 3452 3453 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3454 unsigned imm = fieldFromInstruction(Val, 3, 5); 3455 3456 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3457 return MCDisassembler::Fail; 3458 Inst.addOperand(MCOperand::createImm(imm)); 3459 3460 return S; 3461 } 3462 3463 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3464 uint64_t Address, const void *Decoder) { 3465 unsigned imm = Val << 2; 3466 3467 Inst.addOperand(MCOperand::createImm(imm)); 3468 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3469 3470 return MCDisassembler::Success; 3471 } 3472 3473 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3474 uint64_t Address, const void *Decoder) { 3475 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3476 Inst.addOperand(MCOperand::createImm(Val)); 3477 3478 return MCDisassembler::Success; 3479 } 3480 3481 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3482 uint64_t Address, const void *Decoder) { 3483 DecodeStatus S = MCDisassembler::Success; 3484 3485 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3486 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3487 unsigned imm = fieldFromInstruction(Val, 0, 2); 3488 3489 // Thumb stores cannot use PC as dest register. 3490 switch (Inst.getOpcode()) { 3491 case ARM::t2STRHs: 3492 case ARM::t2STRBs: 3493 case ARM::t2STRs: 3494 if (Rn == 15) 3495 return MCDisassembler::Fail; 3496 break; 3497 default: 3498 break; 3499 } 3500 3501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3502 return MCDisassembler::Fail; 3503 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3504 return MCDisassembler::Fail; 3505 Inst.addOperand(MCOperand::createImm(imm)); 3506 3507 return S; 3508 } 3509 3510 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3511 uint64_t Address, const void *Decoder) { 3512 DecodeStatus S = MCDisassembler::Success; 3513 3514 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3515 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3516 3517 const FeatureBitset &featureBits = 3518 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3519 3520 bool hasMP = featureBits[ARM::FeatureMP]; 3521 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3522 3523 if (Rn == 15) { 3524 switch (Inst.getOpcode()) { 3525 case ARM::t2LDRBs: 3526 Inst.setOpcode(ARM::t2LDRBpci); 3527 break; 3528 case ARM::t2LDRHs: 3529 Inst.setOpcode(ARM::t2LDRHpci); 3530 break; 3531 case ARM::t2LDRSHs: 3532 Inst.setOpcode(ARM::t2LDRSHpci); 3533 break; 3534 case ARM::t2LDRSBs: 3535 Inst.setOpcode(ARM::t2LDRSBpci); 3536 break; 3537 case ARM::t2LDRs: 3538 Inst.setOpcode(ARM::t2LDRpci); 3539 break; 3540 case ARM::t2PLDs: 3541 Inst.setOpcode(ARM::t2PLDpci); 3542 break; 3543 case ARM::t2PLIs: 3544 Inst.setOpcode(ARM::t2PLIpci); 3545 break; 3546 default: 3547 return MCDisassembler::Fail; 3548 } 3549 3550 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3551 } 3552 3553 if (Rt == 15) { 3554 switch (Inst.getOpcode()) { 3555 case ARM::t2LDRSHs: 3556 return MCDisassembler::Fail; 3557 case ARM::t2LDRHs: 3558 Inst.setOpcode(ARM::t2PLDWs); 3559 break; 3560 case ARM::t2LDRSBs: 3561 Inst.setOpcode(ARM::t2PLIs); 3562 break; 3563 default: 3564 break; 3565 } 3566 } 3567 3568 switch (Inst.getOpcode()) { 3569 case ARM::t2PLDs: 3570 break; 3571 case ARM::t2PLIs: 3572 if (!hasV7Ops) 3573 return MCDisassembler::Fail; 3574 break; 3575 case ARM::t2PLDWs: 3576 if (!hasV7Ops || !hasMP) 3577 return MCDisassembler::Fail; 3578 break; 3579 default: 3580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3581 return MCDisassembler::Fail; 3582 } 3583 3584 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3585 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3586 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3587 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3588 return MCDisassembler::Fail; 3589 3590 return S; 3591 } 3592 3593 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3594 uint64_t Address, const void* Decoder) { 3595 DecodeStatus S = MCDisassembler::Success; 3596 3597 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3598 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3599 unsigned U = fieldFromInstruction(Insn, 9, 1); 3600 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3601 imm |= (U << 8); 3602 imm |= (Rn << 9); 3603 unsigned add = fieldFromInstruction(Insn, 9, 1); 3604 3605 const FeatureBitset &featureBits = 3606 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3607 3608 bool hasMP = featureBits[ARM::FeatureMP]; 3609 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3610 3611 if (Rn == 15) { 3612 switch (Inst.getOpcode()) { 3613 case ARM::t2LDRi8: 3614 Inst.setOpcode(ARM::t2LDRpci); 3615 break; 3616 case ARM::t2LDRBi8: 3617 Inst.setOpcode(ARM::t2LDRBpci); 3618 break; 3619 case ARM::t2LDRSBi8: 3620 Inst.setOpcode(ARM::t2LDRSBpci); 3621 break; 3622 case ARM::t2LDRHi8: 3623 Inst.setOpcode(ARM::t2LDRHpci); 3624 break; 3625 case ARM::t2LDRSHi8: 3626 Inst.setOpcode(ARM::t2LDRSHpci); 3627 break; 3628 case ARM::t2PLDi8: 3629 Inst.setOpcode(ARM::t2PLDpci); 3630 break; 3631 case ARM::t2PLIi8: 3632 Inst.setOpcode(ARM::t2PLIpci); 3633 break; 3634 default: 3635 return MCDisassembler::Fail; 3636 } 3637 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3638 } 3639 3640 if (Rt == 15) { 3641 switch (Inst.getOpcode()) { 3642 case ARM::t2LDRSHi8: 3643 return MCDisassembler::Fail; 3644 case ARM::t2LDRHi8: 3645 if (!add) 3646 Inst.setOpcode(ARM::t2PLDWi8); 3647 break; 3648 case ARM::t2LDRSBi8: 3649 Inst.setOpcode(ARM::t2PLIi8); 3650 break; 3651 default: 3652 break; 3653 } 3654 } 3655 3656 switch (Inst.getOpcode()) { 3657 case ARM::t2PLDi8: 3658 break; 3659 case ARM::t2PLIi8: 3660 if (!hasV7Ops) 3661 return MCDisassembler::Fail; 3662 break; 3663 case ARM::t2PLDWi8: 3664 if (!hasV7Ops || !hasMP) 3665 return MCDisassembler::Fail; 3666 break; 3667 default: 3668 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3669 return MCDisassembler::Fail; 3670 } 3671 3672 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3673 return MCDisassembler::Fail; 3674 return S; 3675 } 3676 3677 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3678 uint64_t Address, const void* Decoder) { 3679 DecodeStatus S = MCDisassembler::Success; 3680 3681 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3682 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3683 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3684 imm |= (Rn << 13); 3685 3686 const FeatureBitset &featureBits = 3687 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3688 3689 bool hasMP = featureBits[ARM::FeatureMP]; 3690 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3691 3692 if (Rn == 15) { 3693 switch (Inst.getOpcode()) { 3694 case ARM::t2LDRi12: 3695 Inst.setOpcode(ARM::t2LDRpci); 3696 break; 3697 case ARM::t2LDRHi12: 3698 Inst.setOpcode(ARM::t2LDRHpci); 3699 break; 3700 case ARM::t2LDRSHi12: 3701 Inst.setOpcode(ARM::t2LDRSHpci); 3702 break; 3703 case ARM::t2LDRBi12: 3704 Inst.setOpcode(ARM::t2LDRBpci); 3705 break; 3706 case ARM::t2LDRSBi12: 3707 Inst.setOpcode(ARM::t2LDRSBpci); 3708 break; 3709 case ARM::t2PLDi12: 3710 Inst.setOpcode(ARM::t2PLDpci); 3711 break; 3712 case ARM::t2PLIi12: 3713 Inst.setOpcode(ARM::t2PLIpci); 3714 break; 3715 default: 3716 return MCDisassembler::Fail; 3717 } 3718 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3719 } 3720 3721 if (Rt == 15) { 3722 switch (Inst.getOpcode()) { 3723 case ARM::t2LDRSHi12: 3724 return MCDisassembler::Fail; 3725 case ARM::t2LDRHi12: 3726 Inst.setOpcode(ARM::t2PLDWi12); 3727 break; 3728 case ARM::t2LDRSBi12: 3729 Inst.setOpcode(ARM::t2PLIi12); 3730 break; 3731 default: 3732 break; 3733 } 3734 } 3735 3736 switch (Inst.getOpcode()) { 3737 case ARM::t2PLDi12: 3738 break; 3739 case ARM::t2PLIi12: 3740 if (!hasV7Ops) 3741 return MCDisassembler::Fail; 3742 break; 3743 case ARM::t2PLDWi12: 3744 if (!hasV7Ops || !hasMP) 3745 return MCDisassembler::Fail; 3746 break; 3747 default: 3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3749 return MCDisassembler::Fail; 3750 } 3751 3752 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3753 return MCDisassembler::Fail; 3754 return S; 3755 } 3756 3757 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3758 uint64_t Address, const void* Decoder) { 3759 DecodeStatus S = MCDisassembler::Success; 3760 3761 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3762 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3763 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3764 imm |= (Rn << 9); 3765 3766 if (Rn == 15) { 3767 switch (Inst.getOpcode()) { 3768 case ARM::t2LDRT: 3769 Inst.setOpcode(ARM::t2LDRpci); 3770 break; 3771 case ARM::t2LDRBT: 3772 Inst.setOpcode(ARM::t2LDRBpci); 3773 break; 3774 case ARM::t2LDRHT: 3775 Inst.setOpcode(ARM::t2LDRHpci); 3776 break; 3777 case ARM::t2LDRSBT: 3778 Inst.setOpcode(ARM::t2LDRSBpci); 3779 break; 3780 case ARM::t2LDRSHT: 3781 Inst.setOpcode(ARM::t2LDRSHpci); 3782 break; 3783 default: 3784 return MCDisassembler::Fail; 3785 } 3786 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3787 } 3788 3789 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3790 return MCDisassembler::Fail; 3791 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3792 return MCDisassembler::Fail; 3793 return S; 3794 } 3795 3796 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3797 uint64_t Address, const void* Decoder) { 3798 DecodeStatus S = MCDisassembler::Success; 3799 3800 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3801 unsigned U = fieldFromInstruction(Insn, 23, 1); 3802 int imm = fieldFromInstruction(Insn, 0, 12); 3803 3804 const FeatureBitset &featureBits = 3805 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3806 3807 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3808 3809 if (Rt == 15) { 3810 switch (Inst.getOpcode()) { 3811 case ARM::t2LDRBpci: 3812 case ARM::t2LDRHpci: 3813 Inst.setOpcode(ARM::t2PLDpci); 3814 break; 3815 case ARM::t2LDRSBpci: 3816 Inst.setOpcode(ARM::t2PLIpci); 3817 break; 3818 case ARM::t2LDRSHpci: 3819 return MCDisassembler::Fail; 3820 default: 3821 break; 3822 } 3823 } 3824 3825 switch(Inst.getOpcode()) { 3826 case ARM::t2PLDpci: 3827 break; 3828 case ARM::t2PLIpci: 3829 if (!hasV7Ops) 3830 return MCDisassembler::Fail; 3831 break; 3832 default: 3833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3834 return MCDisassembler::Fail; 3835 } 3836 3837 if (!U) { 3838 // Special case for #-0. 3839 if (imm == 0) 3840 imm = INT32_MIN; 3841 else 3842 imm = -imm; 3843 } 3844 Inst.addOperand(MCOperand::createImm(imm)); 3845 3846 return S; 3847 } 3848 3849 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3850 uint64_t Address, const void *Decoder) { 3851 if (Val == 0) 3852 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3853 else { 3854 int imm = Val & 0xFF; 3855 3856 if (!(Val & 0x100)) imm *= -1; 3857 Inst.addOperand(MCOperand::createImm(imm * 4)); 3858 } 3859 3860 return MCDisassembler::Success; 3861 } 3862 3863 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 3864 const void *Decoder) { 3865 if (Val == 0) 3866 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3867 else { 3868 int imm = Val & 0x7F; 3869 3870 if (!(Val & 0x80)) 3871 imm *= -1; 3872 Inst.addOperand(MCOperand::createImm(imm * 4)); 3873 } 3874 3875 return MCDisassembler::Success; 3876 } 3877 3878 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3879 uint64_t Address, const void *Decoder) { 3880 DecodeStatus S = MCDisassembler::Success; 3881 3882 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3883 unsigned imm = fieldFromInstruction(Val, 0, 9); 3884 3885 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3886 return MCDisassembler::Fail; 3887 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3888 return MCDisassembler::Fail; 3889 3890 return S; 3891 } 3892 3893 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 3894 uint64_t Address, 3895 const void *Decoder) { 3896 DecodeStatus S = MCDisassembler::Success; 3897 3898 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3899 unsigned imm = fieldFromInstruction(Val, 0, 8); 3900 3901 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3902 return MCDisassembler::Fail; 3903 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 3904 return MCDisassembler::Fail; 3905 3906 return S; 3907 } 3908 3909 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3910 uint64_t Address, const void *Decoder) { 3911 DecodeStatus S = MCDisassembler::Success; 3912 3913 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3914 unsigned imm = fieldFromInstruction(Val, 0, 8); 3915 3916 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3917 return MCDisassembler::Fail; 3918 3919 Inst.addOperand(MCOperand::createImm(imm)); 3920 3921 return S; 3922 } 3923 3924 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3925 uint64_t Address, const void *Decoder) { 3926 int imm = Val & 0xFF; 3927 if (Val == 0) 3928 imm = INT32_MIN; 3929 else if (!(Val & 0x100)) 3930 imm *= -1; 3931 Inst.addOperand(MCOperand::createImm(imm)); 3932 3933 return MCDisassembler::Success; 3934 } 3935 3936 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3937 uint64_t Address, const void *Decoder) { 3938 DecodeStatus S = MCDisassembler::Success; 3939 3940 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3941 unsigned imm = fieldFromInstruction(Val, 0, 9); 3942 3943 // Thumb stores cannot use PC as dest register. 3944 switch (Inst.getOpcode()) { 3945 case ARM::t2STRT: 3946 case ARM::t2STRBT: 3947 case ARM::t2STRHT: 3948 case ARM::t2STRi8: 3949 case ARM::t2STRHi8: 3950 case ARM::t2STRBi8: 3951 if (Rn == 15) 3952 return MCDisassembler::Fail; 3953 break; 3954 default: 3955 break; 3956 } 3957 3958 // Some instructions always use an additive offset. 3959 switch (Inst.getOpcode()) { 3960 case ARM::t2LDRT: 3961 case ARM::t2LDRBT: 3962 case ARM::t2LDRHT: 3963 case ARM::t2LDRSBT: 3964 case ARM::t2LDRSHT: 3965 case ARM::t2STRT: 3966 case ARM::t2STRBT: 3967 case ARM::t2STRHT: 3968 imm |= 0x100; 3969 break; 3970 default: 3971 break; 3972 } 3973 3974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3975 return MCDisassembler::Fail; 3976 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3977 return MCDisassembler::Fail; 3978 3979 return S; 3980 } 3981 3982 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3983 uint64_t Address, const void *Decoder) { 3984 DecodeStatus S = MCDisassembler::Success; 3985 3986 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3987 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3988 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3989 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3990 addr |= Rn << 9; 3991 unsigned load = fieldFromInstruction(Insn, 20, 1); 3992 3993 if (Rn == 15) { 3994 switch (Inst.getOpcode()) { 3995 case ARM::t2LDR_PRE: 3996 case ARM::t2LDR_POST: 3997 Inst.setOpcode(ARM::t2LDRpci); 3998 break; 3999 case ARM::t2LDRB_PRE: 4000 case ARM::t2LDRB_POST: 4001 Inst.setOpcode(ARM::t2LDRBpci); 4002 break; 4003 case ARM::t2LDRH_PRE: 4004 case ARM::t2LDRH_POST: 4005 Inst.setOpcode(ARM::t2LDRHpci); 4006 break; 4007 case ARM::t2LDRSB_PRE: 4008 case ARM::t2LDRSB_POST: 4009 if (Rt == 15) 4010 Inst.setOpcode(ARM::t2PLIpci); 4011 else 4012 Inst.setOpcode(ARM::t2LDRSBpci); 4013 break; 4014 case ARM::t2LDRSH_PRE: 4015 case ARM::t2LDRSH_POST: 4016 Inst.setOpcode(ARM::t2LDRSHpci); 4017 break; 4018 default: 4019 return MCDisassembler::Fail; 4020 } 4021 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4022 } 4023 4024 if (!load) { 4025 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4026 return MCDisassembler::Fail; 4027 } 4028 4029 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4030 return MCDisassembler::Fail; 4031 4032 if (load) { 4033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4034 return MCDisassembler::Fail; 4035 } 4036 4037 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4038 return MCDisassembler::Fail; 4039 4040 return S; 4041 } 4042 4043 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4044 uint64_t Address, const void *Decoder) { 4045 DecodeStatus S = MCDisassembler::Success; 4046 4047 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4048 unsigned imm = fieldFromInstruction(Val, 0, 12); 4049 4050 // Thumb stores cannot use PC as dest register. 4051 switch (Inst.getOpcode()) { 4052 case ARM::t2STRi12: 4053 case ARM::t2STRBi12: 4054 case ARM::t2STRHi12: 4055 if (Rn == 15) 4056 return MCDisassembler::Fail; 4057 break; 4058 default: 4059 break; 4060 } 4061 4062 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4063 return MCDisassembler::Fail; 4064 Inst.addOperand(MCOperand::createImm(imm)); 4065 4066 return S; 4067 } 4068 4069 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4070 uint64_t Address, const void *Decoder) { 4071 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4072 4073 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4074 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4075 Inst.addOperand(MCOperand::createImm(imm)); 4076 4077 return MCDisassembler::Success; 4078 } 4079 4080 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4081 uint64_t Address, const void *Decoder) { 4082 DecodeStatus S = MCDisassembler::Success; 4083 4084 if (Inst.getOpcode() == ARM::tADDrSP) { 4085 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4086 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4087 4088 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4089 return MCDisassembler::Fail; 4090 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4092 return MCDisassembler::Fail; 4093 } else if (Inst.getOpcode() == ARM::tADDspr) { 4094 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4095 4096 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4097 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4098 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4099 return MCDisassembler::Fail; 4100 } 4101 4102 return S; 4103 } 4104 4105 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4106 uint64_t Address, const void *Decoder) { 4107 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4108 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4109 4110 Inst.addOperand(MCOperand::createImm(imod)); 4111 Inst.addOperand(MCOperand::createImm(flags)); 4112 4113 return MCDisassembler::Success; 4114 } 4115 4116 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4117 uint64_t Address, const void *Decoder) { 4118 DecodeStatus S = MCDisassembler::Success; 4119 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4120 unsigned add = fieldFromInstruction(Insn, 4, 1); 4121 4122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4123 return MCDisassembler::Fail; 4124 Inst.addOperand(MCOperand::createImm(add)); 4125 4126 return S; 4127 } 4128 4129 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4130 uint64_t Address, const void *Decoder) { 4131 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4132 // Note only one trailing zero not two. Also the J1 and J2 values are from 4133 // the encoded instruction. So here change to I1 and I2 values via: 4134 // I1 = NOT(J1 EOR S); 4135 // I2 = NOT(J2 EOR S); 4136 // and build the imm32 with two trailing zeros as documented: 4137 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4138 unsigned S = (Val >> 23) & 1; 4139 unsigned J1 = (Val >> 22) & 1; 4140 unsigned J2 = (Val >> 21) & 1; 4141 unsigned I1 = !(J1 ^ S); 4142 unsigned I2 = !(J2 ^ S); 4143 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4144 int imm32 = SignExtend32<25>(tmp << 1); 4145 4146 if (!tryAddingSymbolicOperand(Address, 4147 (Address & ~2u) + imm32 + 4, 4148 true, 4, Inst, Decoder)) 4149 Inst.addOperand(MCOperand::createImm(imm32)); 4150 return MCDisassembler::Success; 4151 } 4152 4153 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4154 uint64_t Address, const void *Decoder) { 4155 if (Val == 0xA || Val == 0xB) 4156 return MCDisassembler::Fail; 4157 4158 const FeatureBitset &featureBits = 4159 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4160 4161 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4162 return MCDisassembler::Fail; 4163 4164 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should 4165 // decode as VFP/MVE instructions. 4166 if (featureBits[ARM::HasV8_1MMainlineOps] && 4167 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || 4168 (Val & 0xE) == 0xE)) 4169 return MCDisassembler::Fail; 4170 4171 Inst.addOperand(MCOperand::createImm(Val)); 4172 return MCDisassembler::Success; 4173 } 4174 4175 static DecodeStatus 4176 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4177 uint64_t Address, const void *Decoder) { 4178 DecodeStatus S = MCDisassembler::Success; 4179 4180 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4181 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4182 4183 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4185 return MCDisassembler::Fail; 4186 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4187 return MCDisassembler::Fail; 4188 return S; 4189 } 4190 4191 static DecodeStatus 4192 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4193 uint64_t Address, const void *Decoder) { 4194 DecodeStatus S = MCDisassembler::Success; 4195 4196 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4197 if (pred == 0xE || pred == 0xF) { 4198 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4199 switch (opc) { 4200 default: 4201 return MCDisassembler::Fail; 4202 case 0xf3bf8f4: 4203 Inst.setOpcode(ARM::t2DSB); 4204 break; 4205 case 0xf3bf8f5: 4206 Inst.setOpcode(ARM::t2DMB); 4207 break; 4208 case 0xf3bf8f6: 4209 Inst.setOpcode(ARM::t2ISB); 4210 break; 4211 } 4212 4213 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4214 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4215 } 4216 4217 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4218 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4219 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4220 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4221 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4222 4223 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4224 return MCDisassembler::Fail; 4225 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4226 return MCDisassembler::Fail; 4227 4228 return S; 4229 } 4230 4231 // Decode a shifted immediate operand. These basically consist 4232 // of an 8-bit value, and a 4-bit directive that specifies either 4233 // a splat operation or a rotation. 4234 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4235 uint64_t Address, const void *Decoder) { 4236 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4237 if (ctrl == 0) { 4238 unsigned byte = fieldFromInstruction(Val, 8, 2); 4239 unsigned imm = fieldFromInstruction(Val, 0, 8); 4240 switch (byte) { 4241 case 0: 4242 Inst.addOperand(MCOperand::createImm(imm)); 4243 break; 4244 case 1: 4245 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4246 break; 4247 case 2: 4248 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4249 break; 4250 case 3: 4251 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4252 (imm << 8) | imm)); 4253 break; 4254 } 4255 } else { 4256 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4257 unsigned rot = fieldFromInstruction(Val, 7, 5); 4258 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4259 Inst.addOperand(MCOperand::createImm(imm)); 4260 } 4261 4262 return MCDisassembler::Success; 4263 } 4264 4265 static DecodeStatus 4266 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4267 uint64_t Address, const void *Decoder) { 4268 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4269 true, 2, Inst, Decoder)) 4270 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4271 return MCDisassembler::Success; 4272 } 4273 4274 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4275 uint64_t Address, 4276 const void *Decoder) { 4277 // Val is passed in as S:J1:J2:imm10:imm11 4278 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4279 // the encoded instruction. So here change to I1 and I2 values via: 4280 // I1 = NOT(J1 EOR S); 4281 // I2 = NOT(J2 EOR S); 4282 // and build the imm32 with one trailing zero as documented: 4283 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4284 unsigned S = (Val >> 23) & 1; 4285 unsigned J1 = (Val >> 22) & 1; 4286 unsigned J2 = (Val >> 21) & 1; 4287 unsigned I1 = !(J1 ^ S); 4288 unsigned I2 = !(J2 ^ S); 4289 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4290 int imm32 = SignExtend32<25>(tmp << 1); 4291 4292 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4293 true, 4, Inst, Decoder)) 4294 Inst.addOperand(MCOperand::createImm(imm32)); 4295 return MCDisassembler::Success; 4296 } 4297 4298 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4299 uint64_t Address, const void *Decoder) { 4300 if (Val & ~0xf) 4301 return MCDisassembler::Fail; 4302 4303 Inst.addOperand(MCOperand::createImm(Val)); 4304 return MCDisassembler::Success; 4305 } 4306 4307 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4308 uint64_t Address, const void *Decoder) { 4309 if (Val & ~0xf) 4310 return MCDisassembler::Fail; 4311 4312 Inst.addOperand(MCOperand::createImm(Val)); 4313 return MCDisassembler::Success; 4314 } 4315 4316 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4317 uint64_t Address, const void *Decoder) { 4318 DecodeStatus S = MCDisassembler::Success; 4319 const FeatureBitset &FeatureBits = 4320 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4321 4322 if (FeatureBits[ARM::FeatureMClass]) { 4323 unsigned ValLow = Val & 0xff; 4324 4325 // Validate the SYSm value first. 4326 switch (ValLow) { 4327 case 0: // apsr 4328 case 1: // iapsr 4329 case 2: // eapsr 4330 case 3: // xpsr 4331 case 5: // ipsr 4332 case 6: // epsr 4333 case 7: // iepsr 4334 case 8: // msp 4335 case 9: // psp 4336 case 16: // primask 4337 case 20: // control 4338 break; 4339 case 17: // basepri 4340 case 18: // basepri_max 4341 case 19: // faultmask 4342 if (!(FeatureBits[ARM::HasV7Ops])) 4343 // Values basepri, basepri_max and faultmask are only valid for v7m. 4344 return MCDisassembler::Fail; 4345 break; 4346 case 0x8a: // msplim_ns 4347 case 0x8b: // psplim_ns 4348 case 0x91: // basepri_ns 4349 case 0x93: // faultmask_ns 4350 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4351 return MCDisassembler::Fail; 4352 LLVM_FALLTHROUGH; 4353 case 10: // msplim 4354 case 11: // psplim 4355 case 0x88: // msp_ns 4356 case 0x89: // psp_ns 4357 case 0x90: // primask_ns 4358 case 0x94: // control_ns 4359 case 0x98: // sp_ns 4360 if (!(FeatureBits[ARM::Feature8MSecExt])) 4361 return MCDisassembler::Fail; 4362 break; 4363 default: 4364 // Architecturally defined as unpredictable 4365 S = MCDisassembler::SoftFail; 4366 break; 4367 } 4368 4369 if (Inst.getOpcode() == ARM::t2MSR_M) { 4370 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4371 if (!(FeatureBits[ARM::HasV7Ops])) { 4372 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4373 // unpredictable. 4374 if (Mask != 2) 4375 S = MCDisassembler::SoftFail; 4376 } 4377 else { 4378 // The ARMv7-M architecture stores an additional 2-bit mask value in 4379 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4380 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4381 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4382 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4383 // only if the processor includes the DSP extension. 4384 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4385 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4386 S = MCDisassembler::SoftFail; 4387 } 4388 } 4389 } else { 4390 // A/R class 4391 if (Val == 0) 4392 return MCDisassembler::Fail; 4393 } 4394 Inst.addOperand(MCOperand::createImm(Val)); 4395 return S; 4396 } 4397 4398 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4399 uint64_t Address, const void *Decoder) { 4400 unsigned R = fieldFromInstruction(Val, 5, 1); 4401 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4402 4403 // The table of encodings for these banked registers comes from B9.2.3 of the 4404 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4405 // neater. So by fiat, these values are UNPREDICTABLE: 4406 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4407 return MCDisassembler::Fail; 4408 4409 Inst.addOperand(MCOperand::createImm(Val)); 4410 return MCDisassembler::Success; 4411 } 4412 4413 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4414 uint64_t Address, const void *Decoder) { 4415 DecodeStatus S = MCDisassembler::Success; 4416 4417 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4418 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4419 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4420 4421 if (Rn == 0xF) 4422 S = MCDisassembler::SoftFail; 4423 4424 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4425 return MCDisassembler::Fail; 4426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4427 return MCDisassembler::Fail; 4428 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4429 return MCDisassembler::Fail; 4430 4431 return S; 4432 } 4433 4434 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4435 uint64_t Address, 4436 const void *Decoder) { 4437 DecodeStatus S = MCDisassembler::Success; 4438 4439 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4440 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4441 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4442 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4443 4444 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4445 return MCDisassembler::Fail; 4446 4447 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4448 S = MCDisassembler::SoftFail; 4449 4450 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4451 return MCDisassembler::Fail; 4452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4453 return MCDisassembler::Fail; 4454 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4455 return MCDisassembler::Fail; 4456 4457 return S; 4458 } 4459 4460 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4461 uint64_t Address, const void *Decoder) { 4462 DecodeStatus S = MCDisassembler::Success; 4463 4464 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4465 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4466 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4467 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4468 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4469 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4470 4471 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4472 4473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4474 return MCDisassembler::Fail; 4475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4476 return MCDisassembler::Fail; 4477 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4478 return MCDisassembler::Fail; 4479 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4480 return MCDisassembler::Fail; 4481 4482 return S; 4483 } 4484 4485 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4486 uint64_t Address, const void *Decoder) { 4487 DecodeStatus S = MCDisassembler::Success; 4488 4489 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4490 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4491 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4492 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4493 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4494 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4495 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4496 4497 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4498 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4499 4500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4501 return MCDisassembler::Fail; 4502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4503 return MCDisassembler::Fail; 4504 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4505 return MCDisassembler::Fail; 4506 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4507 return MCDisassembler::Fail; 4508 4509 return S; 4510 } 4511 4512 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4513 uint64_t Address, const void *Decoder) { 4514 DecodeStatus S = MCDisassembler::Success; 4515 4516 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4517 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4518 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4519 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4520 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4521 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4522 4523 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4524 4525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4526 return MCDisassembler::Fail; 4527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4528 return MCDisassembler::Fail; 4529 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4530 return MCDisassembler::Fail; 4531 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4532 return MCDisassembler::Fail; 4533 4534 return S; 4535 } 4536 4537 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4538 uint64_t Address, const void *Decoder) { 4539 DecodeStatus S = MCDisassembler::Success; 4540 4541 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4542 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4543 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4544 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4545 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4546 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4547 4548 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4549 4550 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4551 return MCDisassembler::Fail; 4552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4553 return MCDisassembler::Fail; 4554 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4555 return MCDisassembler::Fail; 4556 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4557 return MCDisassembler::Fail; 4558 4559 return S; 4560 } 4561 4562 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4563 uint64_t Address, const void *Decoder) { 4564 DecodeStatus S = MCDisassembler::Success; 4565 4566 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4567 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4568 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4569 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4570 unsigned size = fieldFromInstruction(Insn, 10, 2); 4571 4572 unsigned align = 0; 4573 unsigned index = 0; 4574 switch (size) { 4575 default: 4576 return MCDisassembler::Fail; 4577 case 0: 4578 if (fieldFromInstruction(Insn, 4, 1)) 4579 return MCDisassembler::Fail; // UNDEFINED 4580 index = fieldFromInstruction(Insn, 5, 3); 4581 break; 4582 case 1: 4583 if (fieldFromInstruction(Insn, 5, 1)) 4584 return MCDisassembler::Fail; // UNDEFINED 4585 index = fieldFromInstruction(Insn, 6, 2); 4586 if (fieldFromInstruction(Insn, 4, 1)) 4587 align = 2; 4588 break; 4589 case 2: 4590 if (fieldFromInstruction(Insn, 6, 1)) 4591 return MCDisassembler::Fail; // UNDEFINED 4592 index = fieldFromInstruction(Insn, 7, 1); 4593 4594 switch (fieldFromInstruction(Insn, 4, 2)) { 4595 case 0 : 4596 align = 0; break; 4597 case 3: 4598 align = 4; break; 4599 default: 4600 return MCDisassembler::Fail; 4601 } 4602 break; 4603 } 4604 4605 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4606 return MCDisassembler::Fail; 4607 if (Rm != 0xF) { // Writeback 4608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4609 return MCDisassembler::Fail; 4610 } 4611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4612 return MCDisassembler::Fail; 4613 Inst.addOperand(MCOperand::createImm(align)); 4614 if (Rm != 0xF) { 4615 if (Rm != 0xD) { 4616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4617 return MCDisassembler::Fail; 4618 } else 4619 Inst.addOperand(MCOperand::createReg(0)); 4620 } 4621 4622 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4623 return MCDisassembler::Fail; 4624 Inst.addOperand(MCOperand::createImm(index)); 4625 4626 return S; 4627 } 4628 4629 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4630 uint64_t Address, const void *Decoder) { 4631 DecodeStatus S = MCDisassembler::Success; 4632 4633 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4634 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4635 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4636 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4637 unsigned size = fieldFromInstruction(Insn, 10, 2); 4638 4639 unsigned align = 0; 4640 unsigned index = 0; 4641 switch (size) { 4642 default: 4643 return MCDisassembler::Fail; 4644 case 0: 4645 if (fieldFromInstruction(Insn, 4, 1)) 4646 return MCDisassembler::Fail; // UNDEFINED 4647 index = fieldFromInstruction(Insn, 5, 3); 4648 break; 4649 case 1: 4650 if (fieldFromInstruction(Insn, 5, 1)) 4651 return MCDisassembler::Fail; // UNDEFINED 4652 index = fieldFromInstruction(Insn, 6, 2); 4653 if (fieldFromInstruction(Insn, 4, 1)) 4654 align = 2; 4655 break; 4656 case 2: 4657 if (fieldFromInstruction(Insn, 6, 1)) 4658 return MCDisassembler::Fail; // UNDEFINED 4659 index = fieldFromInstruction(Insn, 7, 1); 4660 4661 switch (fieldFromInstruction(Insn, 4, 2)) { 4662 case 0: 4663 align = 0; break; 4664 case 3: 4665 align = 4; break; 4666 default: 4667 return MCDisassembler::Fail; 4668 } 4669 break; 4670 } 4671 4672 if (Rm != 0xF) { // Writeback 4673 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4674 return MCDisassembler::Fail; 4675 } 4676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4677 return MCDisassembler::Fail; 4678 Inst.addOperand(MCOperand::createImm(align)); 4679 if (Rm != 0xF) { 4680 if (Rm != 0xD) { 4681 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4682 return MCDisassembler::Fail; 4683 } else 4684 Inst.addOperand(MCOperand::createReg(0)); 4685 } 4686 4687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4688 return MCDisassembler::Fail; 4689 Inst.addOperand(MCOperand::createImm(index)); 4690 4691 return S; 4692 } 4693 4694 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4695 uint64_t Address, const void *Decoder) { 4696 DecodeStatus S = MCDisassembler::Success; 4697 4698 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4699 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4700 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4701 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4702 unsigned size = fieldFromInstruction(Insn, 10, 2); 4703 4704 unsigned align = 0; 4705 unsigned index = 0; 4706 unsigned inc = 1; 4707 switch (size) { 4708 default: 4709 return MCDisassembler::Fail; 4710 case 0: 4711 index = fieldFromInstruction(Insn, 5, 3); 4712 if (fieldFromInstruction(Insn, 4, 1)) 4713 align = 2; 4714 break; 4715 case 1: 4716 index = fieldFromInstruction(Insn, 6, 2); 4717 if (fieldFromInstruction(Insn, 4, 1)) 4718 align = 4; 4719 if (fieldFromInstruction(Insn, 5, 1)) 4720 inc = 2; 4721 break; 4722 case 2: 4723 if (fieldFromInstruction(Insn, 5, 1)) 4724 return MCDisassembler::Fail; // UNDEFINED 4725 index = fieldFromInstruction(Insn, 7, 1); 4726 if (fieldFromInstruction(Insn, 4, 1) != 0) 4727 align = 8; 4728 if (fieldFromInstruction(Insn, 6, 1)) 4729 inc = 2; 4730 break; 4731 } 4732 4733 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4734 return MCDisassembler::Fail; 4735 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4736 return MCDisassembler::Fail; 4737 if (Rm != 0xF) { // Writeback 4738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4739 return MCDisassembler::Fail; 4740 } 4741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4742 return MCDisassembler::Fail; 4743 Inst.addOperand(MCOperand::createImm(align)); 4744 if (Rm != 0xF) { 4745 if (Rm != 0xD) { 4746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4747 return MCDisassembler::Fail; 4748 } else 4749 Inst.addOperand(MCOperand::createReg(0)); 4750 } 4751 4752 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4753 return MCDisassembler::Fail; 4754 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4755 return MCDisassembler::Fail; 4756 Inst.addOperand(MCOperand::createImm(index)); 4757 4758 return S; 4759 } 4760 4761 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4762 uint64_t Address, const void *Decoder) { 4763 DecodeStatus S = MCDisassembler::Success; 4764 4765 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4766 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4767 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4768 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4769 unsigned size = fieldFromInstruction(Insn, 10, 2); 4770 4771 unsigned align = 0; 4772 unsigned index = 0; 4773 unsigned inc = 1; 4774 switch (size) { 4775 default: 4776 return MCDisassembler::Fail; 4777 case 0: 4778 index = fieldFromInstruction(Insn, 5, 3); 4779 if (fieldFromInstruction(Insn, 4, 1)) 4780 align = 2; 4781 break; 4782 case 1: 4783 index = fieldFromInstruction(Insn, 6, 2); 4784 if (fieldFromInstruction(Insn, 4, 1)) 4785 align = 4; 4786 if (fieldFromInstruction(Insn, 5, 1)) 4787 inc = 2; 4788 break; 4789 case 2: 4790 if (fieldFromInstruction(Insn, 5, 1)) 4791 return MCDisassembler::Fail; // UNDEFINED 4792 index = fieldFromInstruction(Insn, 7, 1); 4793 if (fieldFromInstruction(Insn, 4, 1) != 0) 4794 align = 8; 4795 if (fieldFromInstruction(Insn, 6, 1)) 4796 inc = 2; 4797 break; 4798 } 4799 4800 if (Rm != 0xF) { // Writeback 4801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4802 return MCDisassembler::Fail; 4803 } 4804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4805 return MCDisassembler::Fail; 4806 Inst.addOperand(MCOperand::createImm(align)); 4807 if (Rm != 0xF) { 4808 if (Rm != 0xD) { 4809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4810 return MCDisassembler::Fail; 4811 } else 4812 Inst.addOperand(MCOperand::createReg(0)); 4813 } 4814 4815 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4816 return MCDisassembler::Fail; 4817 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4818 return MCDisassembler::Fail; 4819 Inst.addOperand(MCOperand::createImm(index)); 4820 4821 return S; 4822 } 4823 4824 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4825 uint64_t Address, const void *Decoder) { 4826 DecodeStatus S = MCDisassembler::Success; 4827 4828 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4829 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4830 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4831 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4832 unsigned size = fieldFromInstruction(Insn, 10, 2); 4833 4834 unsigned align = 0; 4835 unsigned index = 0; 4836 unsigned inc = 1; 4837 switch (size) { 4838 default: 4839 return MCDisassembler::Fail; 4840 case 0: 4841 if (fieldFromInstruction(Insn, 4, 1)) 4842 return MCDisassembler::Fail; // UNDEFINED 4843 index = fieldFromInstruction(Insn, 5, 3); 4844 break; 4845 case 1: 4846 if (fieldFromInstruction(Insn, 4, 1)) 4847 return MCDisassembler::Fail; // UNDEFINED 4848 index = fieldFromInstruction(Insn, 6, 2); 4849 if (fieldFromInstruction(Insn, 5, 1)) 4850 inc = 2; 4851 break; 4852 case 2: 4853 if (fieldFromInstruction(Insn, 4, 2)) 4854 return MCDisassembler::Fail; // UNDEFINED 4855 index = fieldFromInstruction(Insn, 7, 1); 4856 if (fieldFromInstruction(Insn, 6, 1)) 4857 inc = 2; 4858 break; 4859 } 4860 4861 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4862 return MCDisassembler::Fail; 4863 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4864 return MCDisassembler::Fail; 4865 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4866 return MCDisassembler::Fail; 4867 4868 if (Rm != 0xF) { // Writeback 4869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4870 return MCDisassembler::Fail; 4871 } 4872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4873 return MCDisassembler::Fail; 4874 Inst.addOperand(MCOperand::createImm(align)); 4875 if (Rm != 0xF) { 4876 if (Rm != 0xD) { 4877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4878 return MCDisassembler::Fail; 4879 } else 4880 Inst.addOperand(MCOperand::createReg(0)); 4881 } 4882 4883 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4884 return MCDisassembler::Fail; 4885 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4886 return MCDisassembler::Fail; 4887 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4888 return MCDisassembler::Fail; 4889 Inst.addOperand(MCOperand::createImm(index)); 4890 4891 return S; 4892 } 4893 4894 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4895 uint64_t Address, const void *Decoder) { 4896 DecodeStatus S = MCDisassembler::Success; 4897 4898 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4899 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4900 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4901 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4902 unsigned size = fieldFromInstruction(Insn, 10, 2); 4903 4904 unsigned align = 0; 4905 unsigned index = 0; 4906 unsigned inc = 1; 4907 switch (size) { 4908 default: 4909 return MCDisassembler::Fail; 4910 case 0: 4911 if (fieldFromInstruction(Insn, 4, 1)) 4912 return MCDisassembler::Fail; // UNDEFINED 4913 index = fieldFromInstruction(Insn, 5, 3); 4914 break; 4915 case 1: 4916 if (fieldFromInstruction(Insn, 4, 1)) 4917 return MCDisassembler::Fail; // UNDEFINED 4918 index = fieldFromInstruction(Insn, 6, 2); 4919 if (fieldFromInstruction(Insn, 5, 1)) 4920 inc = 2; 4921 break; 4922 case 2: 4923 if (fieldFromInstruction(Insn, 4, 2)) 4924 return MCDisassembler::Fail; // UNDEFINED 4925 index = fieldFromInstruction(Insn, 7, 1); 4926 if (fieldFromInstruction(Insn, 6, 1)) 4927 inc = 2; 4928 break; 4929 } 4930 4931 if (Rm != 0xF) { // Writeback 4932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4933 return MCDisassembler::Fail; 4934 } 4935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4936 return MCDisassembler::Fail; 4937 Inst.addOperand(MCOperand::createImm(align)); 4938 if (Rm != 0xF) { 4939 if (Rm != 0xD) { 4940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4941 return MCDisassembler::Fail; 4942 } else 4943 Inst.addOperand(MCOperand::createReg(0)); 4944 } 4945 4946 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4947 return MCDisassembler::Fail; 4948 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4949 return MCDisassembler::Fail; 4950 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4951 return MCDisassembler::Fail; 4952 Inst.addOperand(MCOperand::createImm(index)); 4953 4954 return S; 4955 } 4956 4957 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4958 uint64_t Address, const void *Decoder) { 4959 DecodeStatus S = MCDisassembler::Success; 4960 4961 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4962 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4963 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4964 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4965 unsigned size = fieldFromInstruction(Insn, 10, 2); 4966 4967 unsigned align = 0; 4968 unsigned index = 0; 4969 unsigned inc = 1; 4970 switch (size) { 4971 default: 4972 return MCDisassembler::Fail; 4973 case 0: 4974 if (fieldFromInstruction(Insn, 4, 1)) 4975 align = 4; 4976 index = fieldFromInstruction(Insn, 5, 3); 4977 break; 4978 case 1: 4979 if (fieldFromInstruction(Insn, 4, 1)) 4980 align = 8; 4981 index = fieldFromInstruction(Insn, 6, 2); 4982 if (fieldFromInstruction(Insn, 5, 1)) 4983 inc = 2; 4984 break; 4985 case 2: 4986 switch (fieldFromInstruction(Insn, 4, 2)) { 4987 case 0: 4988 align = 0; break; 4989 case 3: 4990 return MCDisassembler::Fail; 4991 default: 4992 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4993 } 4994 4995 index = fieldFromInstruction(Insn, 7, 1); 4996 if (fieldFromInstruction(Insn, 6, 1)) 4997 inc = 2; 4998 break; 4999 } 5000 5001 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5002 return MCDisassembler::Fail; 5003 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5004 return MCDisassembler::Fail; 5005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5006 return MCDisassembler::Fail; 5007 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5008 return MCDisassembler::Fail; 5009 5010 if (Rm != 0xF) { // Writeback 5011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5012 return MCDisassembler::Fail; 5013 } 5014 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5015 return MCDisassembler::Fail; 5016 Inst.addOperand(MCOperand::createImm(align)); 5017 if (Rm != 0xF) { 5018 if (Rm != 0xD) { 5019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5020 return MCDisassembler::Fail; 5021 } else 5022 Inst.addOperand(MCOperand::createReg(0)); 5023 } 5024 5025 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5026 return MCDisassembler::Fail; 5027 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5028 return MCDisassembler::Fail; 5029 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5030 return MCDisassembler::Fail; 5031 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5032 return MCDisassembler::Fail; 5033 Inst.addOperand(MCOperand::createImm(index)); 5034 5035 return S; 5036 } 5037 5038 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5039 uint64_t Address, const void *Decoder) { 5040 DecodeStatus S = MCDisassembler::Success; 5041 5042 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5043 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5044 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5045 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5046 unsigned size = fieldFromInstruction(Insn, 10, 2); 5047 5048 unsigned align = 0; 5049 unsigned index = 0; 5050 unsigned inc = 1; 5051 switch (size) { 5052 default: 5053 return MCDisassembler::Fail; 5054 case 0: 5055 if (fieldFromInstruction(Insn, 4, 1)) 5056 align = 4; 5057 index = fieldFromInstruction(Insn, 5, 3); 5058 break; 5059 case 1: 5060 if (fieldFromInstruction(Insn, 4, 1)) 5061 align = 8; 5062 index = fieldFromInstruction(Insn, 6, 2); 5063 if (fieldFromInstruction(Insn, 5, 1)) 5064 inc = 2; 5065 break; 5066 case 2: 5067 switch (fieldFromInstruction(Insn, 4, 2)) { 5068 case 0: 5069 align = 0; break; 5070 case 3: 5071 return MCDisassembler::Fail; 5072 default: 5073 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5074 } 5075 5076 index = fieldFromInstruction(Insn, 7, 1); 5077 if (fieldFromInstruction(Insn, 6, 1)) 5078 inc = 2; 5079 break; 5080 } 5081 5082 if (Rm != 0xF) { // Writeback 5083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5084 return MCDisassembler::Fail; 5085 } 5086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5087 return MCDisassembler::Fail; 5088 Inst.addOperand(MCOperand::createImm(align)); 5089 if (Rm != 0xF) { 5090 if (Rm != 0xD) { 5091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5092 return MCDisassembler::Fail; 5093 } else 5094 Inst.addOperand(MCOperand::createReg(0)); 5095 } 5096 5097 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5098 return MCDisassembler::Fail; 5099 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5100 return MCDisassembler::Fail; 5101 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5102 return MCDisassembler::Fail; 5103 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5104 return MCDisassembler::Fail; 5105 Inst.addOperand(MCOperand::createImm(index)); 5106 5107 return S; 5108 } 5109 5110 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5111 uint64_t Address, const void *Decoder) { 5112 DecodeStatus S = MCDisassembler::Success; 5113 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5114 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5115 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5116 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5117 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5118 5119 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5120 S = MCDisassembler::SoftFail; 5121 5122 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5123 return MCDisassembler::Fail; 5124 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5125 return MCDisassembler::Fail; 5126 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5127 return MCDisassembler::Fail; 5128 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5129 return MCDisassembler::Fail; 5130 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5131 return MCDisassembler::Fail; 5132 5133 return S; 5134 } 5135 5136 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5137 uint64_t Address, const void *Decoder) { 5138 DecodeStatus S = MCDisassembler::Success; 5139 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5140 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5141 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5142 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5143 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5144 5145 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5146 S = MCDisassembler::SoftFail; 5147 5148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5149 return MCDisassembler::Fail; 5150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5151 return MCDisassembler::Fail; 5152 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5153 return MCDisassembler::Fail; 5154 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5155 return MCDisassembler::Fail; 5156 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5157 return MCDisassembler::Fail; 5158 5159 return S; 5160 } 5161 5162 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5163 uint64_t Address, const void *Decoder) { 5164 DecodeStatus S = MCDisassembler::Success; 5165 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5166 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5167 5168 if (pred == 0xF) { 5169 pred = 0xE; 5170 S = MCDisassembler::SoftFail; 5171 } 5172 5173 if (mask == 0x0) 5174 return MCDisassembler::Fail; 5175 5176 // IT masks are encoded as a sequence of replacement low-order bits 5177 // for the condition code. So if the low bit of the starting 5178 // condition code is 1, then we have to flip all the bits above the 5179 // terminating bit (which is the lowest 1 bit). 5180 if (pred & 1) { 5181 unsigned LowBit = mask & -mask; 5182 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5183 mask ^= BitsAboveLowBit; 5184 } 5185 5186 Inst.addOperand(MCOperand::createImm(pred)); 5187 Inst.addOperand(MCOperand::createImm(mask)); 5188 return S; 5189 } 5190 5191 static DecodeStatus 5192 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5193 uint64_t Address, const void *Decoder) { 5194 DecodeStatus S = MCDisassembler::Success; 5195 5196 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5197 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5198 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5199 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5200 unsigned W = fieldFromInstruction(Insn, 21, 1); 5201 unsigned U = fieldFromInstruction(Insn, 23, 1); 5202 unsigned P = fieldFromInstruction(Insn, 24, 1); 5203 bool writeback = (W == 1) | (P == 0); 5204 5205 addr |= (U << 8) | (Rn << 9); 5206 5207 if (writeback && (Rn == Rt || Rn == Rt2)) 5208 Check(S, MCDisassembler::SoftFail); 5209 if (Rt == Rt2) 5210 Check(S, MCDisassembler::SoftFail); 5211 5212 // Rt 5213 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5214 return MCDisassembler::Fail; 5215 // Rt2 5216 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5217 return MCDisassembler::Fail; 5218 // Writeback operand 5219 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5220 return MCDisassembler::Fail; 5221 // addr 5222 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5223 return MCDisassembler::Fail; 5224 5225 return S; 5226 } 5227 5228 static DecodeStatus 5229 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5230 uint64_t Address, const void *Decoder) { 5231 DecodeStatus S = MCDisassembler::Success; 5232 5233 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5234 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5235 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5236 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5237 unsigned W = fieldFromInstruction(Insn, 21, 1); 5238 unsigned U = fieldFromInstruction(Insn, 23, 1); 5239 unsigned P = fieldFromInstruction(Insn, 24, 1); 5240 bool writeback = (W == 1) | (P == 0); 5241 5242 addr |= (U << 8) | (Rn << 9); 5243 5244 if (writeback && (Rn == Rt || Rn == Rt2)) 5245 Check(S, MCDisassembler::SoftFail); 5246 5247 // Writeback operand 5248 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5249 return MCDisassembler::Fail; 5250 // Rt 5251 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5252 return MCDisassembler::Fail; 5253 // Rt2 5254 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5255 return MCDisassembler::Fail; 5256 // addr 5257 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5258 return MCDisassembler::Fail; 5259 5260 return S; 5261 } 5262 5263 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5264 uint64_t Address, const void *Decoder) { 5265 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5266 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5267 if (sign1 != sign2) return MCDisassembler::Fail; 5268 5269 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5270 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5271 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5272 Val |= sign1 << 12; 5273 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5274 5275 return MCDisassembler::Success; 5276 } 5277 5278 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5279 uint64_t Address, 5280 const void *Decoder) { 5281 DecodeStatus S = MCDisassembler::Success; 5282 5283 // Shift of "asr #32" is not allowed in Thumb2 mode. 5284 if (Val == 0x20) S = MCDisassembler::Fail; 5285 Inst.addOperand(MCOperand::createImm(Val)); 5286 return S; 5287 } 5288 5289 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5290 uint64_t Address, const void *Decoder) { 5291 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5292 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5293 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5294 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5295 5296 if (pred == 0xF) 5297 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5298 5299 DecodeStatus S = MCDisassembler::Success; 5300 5301 if (Rt == Rn || Rn == Rt2) 5302 S = MCDisassembler::SoftFail; 5303 5304 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5305 return MCDisassembler::Fail; 5306 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5307 return MCDisassembler::Fail; 5308 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5309 return MCDisassembler::Fail; 5310 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5311 return MCDisassembler::Fail; 5312 5313 return S; 5314 } 5315 5316 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5317 uint64_t Address, const void *Decoder) { 5318 const FeatureBitset &featureBits = 5319 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5320 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5321 5322 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5323 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5324 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5325 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5326 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5327 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5328 unsigned op = fieldFromInstruction(Insn, 5, 1); 5329 5330 DecodeStatus S = MCDisassembler::Success; 5331 5332 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5333 if (!(imm & 0x38)) { 5334 if (cmode == 0xF) { 5335 if (op == 1) return MCDisassembler::Fail; 5336 Inst.setOpcode(ARM::VMOVv2f32); 5337 } 5338 if (hasFullFP16) { 5339 if (cmode == 0xE) { 5340 if (op == 1) { 5341 Inst.setOpcode(ARM::VMOVv1i64); 5342 } else { 5343 Inst.setOpcode(ARM::VMOVv8i8); 5344 } 5345 } 5346 if (cmode == 0xD) { 5347 if (op == 1) { 5348 Inst.setOpcode(ARM::VMVNv2i32); 5349 } else { 5350 Inst.setOpcode(ARM::VMOVv2i32); 5351 } 5352 } 5353 if (cmode == 0xC) { 5354 if (op == 1) { 5355 Inst.setOpcode(ARM::VMVNv2i32); 5356 } else { 5357 Inst.setOpcode(ARM::VMOVv2i32); 5358 } 5359 } 5360 } 5361 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5362 } 5363 5364 if (!(imm & 0x20)) return MCDisassembler::Fail; 5365 5366 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5367 return MCDisassembler::Fail; 5368 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5369 return MCDisassembler::Fail; 5370 Inst.addOperand(MCOperand::createImm(64 - imm)); 5371 5372 return S; 5373 } 5374 5375 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5376 uint64_t Address, const void *Decoder) { 5377 const FeatureBitset &featureBits = 5378 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5379 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5380 5381 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5382 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5383 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5384 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5385 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5386 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5387 unsigned op = fieldFromInstruction(Insn, 5, 1); 5388 5389 DecodeStatus S = MCDisassembler::Success; 5390 5391 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5392 if (!(imm & 0x38)) { 5393 if (cmode == 0xF) { 5394 if (op == 1) return MCDisassembler::Fail; 5395 Inst.setOpcode(ARM::VMOVv4f32); 5396 } 5397 if (hasFullFP16) { 5398 if (cmode == 0xE) { 5399 if (op == 1) { 5400 Inst.setOpcode(ARM::VMOVv2i64); 5401 } else { 5402 Inst.setOpcode(ARM::VMOVv16i8); 5403 } 5404 } 5405 if (cmode == 0xD) { 5406 if (op == 1) { 5407 Inst.setOpcode(ARM::VMVNv4i32); 5408 } else { 5409 Inst.setOpcode(ARM::VMOVv4i32); 5410 } 5411 } 5412 if (cmode == 0xC) { 5413 if (op == 1) { 5414 Inst.setOpcode(ARM::VMVNv4i32); 5415 } else { 5416 Inst.setOpcode(ARM::VMOVv4i32); 5417 } 5418 } 5419 } 5420 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5421 } 5422 5423 if (!(imm & 0x20)) return MCDisassembler::Fail; 5424 5425 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5426 return MCDisassembler::Fail; 5427 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5428 return MCDisassembler::Fail; 5429 Inst.addOperand(MCOperand::createImm(64 - imm)); 5430 5431 return S; 5432 } 5433 5434 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5435 unsigned Insn, 5436 uint64_t Address, 5437 const void *Decoder) { 5438 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5439 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5440 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5441 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5442 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5443 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5444 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5445 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5446 5447 DecodeStatus S = MCDisassembler::Success; 5448 5449 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5450 5451 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5452 return MCDisassembler::Fail; 5453 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5454 return MCDisassembler::Fail; 5455 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5456 return MCDisassembler::Fail; 5457 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5458 return MCDisassembler::Fail; 5459 // The lane index does not have any bits in the encoding, because it can only 5460 // be 0. 5461 Inst.addOperand(MCOperand::createImm(0)); 5462 Inst.addOperand(MCOperand::createImm(rotate)); 5463 5464 return S; 5465 } 5466 5467 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5468 uint64_t Address, const void *Decoder) { 5469 DecodeStatus S = MCDisassembler::Success; 5470 5471 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5472 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5473 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5474 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5475 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5476 5477 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5478 S = MCDisassembler::SoftFail; 5479 5480 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5481 return MCDisassembler::Fail; 5482 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5483 return MCDisassembler::Fail; 5484 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5485 return MCDisassembler::Fail; 5486 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5487 return MCDisassembler::Fail; 5488 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5489 return MCDisassembler::Fail; 5490 5491 return S; 5492 } 5493 5494 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5495 uint64_t Address, const void *Decoder) { 5496 DecodeStatus S = MCDisassembler::Success; 5497 5498 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5499 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5500 unsigned cop = fieldFromInstruction(Val, 8, 4); 5501 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5502 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5503 5504 if ((cop & ~0x1) == 0xa) 5505 return MCDisassembler::Fail; 5506 5507 if (Rt == Rt2) 5508 S = MCDisassembler::SoftFail; 5509 5510 // We have to check if the instruction is MRRC2 5511 // or MCRR2 when constructing the operands for 5512 // Inst. Reason is because MRRC2 stores to two 5513 // registers so it's tablegen desc has has two 5514 // outputs whereas MCRR doesn't store to any 5515 // registers so all of it's operands are listed 5516 // as inputs, therefore the operand order for 5517 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5518 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5519 5520 if (Inst.getOpcode() == ARM::MRRC2) { 5521 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5522 return MCDisassembler::Fail; 5523 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5524 return MCDisassembler::Fail; 5525 } 5526 Inst.addOperand(MCOperand::createImm(cop)); 5527 Inst.addOperand(MCOperand::createImm(opc1)); 5528 if (Inst.getOpcode() == ARM::MCRR2) { 5529 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5530 return MCDisassembler::Fail; 5531 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5532 return MCDisassembler::Fail; 5533 } 5534 Inst.addOperand(MCOperand::createImm(CRm)); 5535 5536 return S; 5537 } 5538 5539 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5540 uint64_t Address, 5541 const void *Decoder) { 5542 const FeatureBitset &featureBits = 5543 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5544 DecodeStatus S = MCDisassembler::Success; 5545 5546 // Add explicit operand for the destination sysreg, for cases where 5547 // we have to model it for code generation purposes. 5548 switch (Inst.getOpcode()) { 5549 case ARM::VMSR_FPSCR_NZCVQC: 5550 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5551 break; 5552 case ARM::VMSR_P0: 5553 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5554 break; 5555 } 5556 5557 if (Inst.getOpcode() != ARM::FMSTAT) { 5558 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5559 5560 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5561 if (Rt == 13 || Rt == 15) 5562 S = MCDisassembler::SoftFail; 5563 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5564 } else 5565 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5566 } 5567 5568 // Add explicit operand for the source sysreg, similarly to above. 5569 switch (Inst.getOpcode()) { 5570 case ARM::VMRS_FPSCR_NZCVQC: 5571 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5572 break; 5573 case ARM::VMRS_P0: 5574 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5575 break; 5576 } 5577 5578 if (featureBits[ARM::ModeThumb]) { 5579 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5580 Inst.addOperand(MCOperand::createReg(0)); 5581 } else { 5582 unsigned pred = fieldFromInstruction(Val, 28, 4); 5583 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5584 return MCDisassembler::Fail; 5585 } 5586 5587 return S; 5588 } 5589 5590 template <bool isSigned, bool isNeg, int size> 5591 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5592 uint64_t Address, 5593 const void *Decoder) { 5594 DecodeStatus S = MCDisassembler::Success; 5595 if (Val == 0) 5596 S = MCDisassembler::SoftFail; 5597 5598 uint64_t DecVal; 5599 if (isSigned) 5600 DecVal = SignExtend32<size + 1>(Val << 1); 5601 else 5602 DecVal = (Val << 1); 5603 5604 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5605 Decoder)) 5606 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5607 return S; 5608 } 5609 5610 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5611 uint64_t Address, 5612 const void *Decoder) { 5613 5614 uint64_t LocImm = Inst.getOperand(0).getImm(); 5615 Val = LocImm + (2 << Val); 5616 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5617 Decoder)) 5618 Inst.addOperand(MCOperand::createImm(Val)); 5619 return MCDisassembler::Success; 5620 } 5621 5622 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5623 uint64_t Address, 5624 const void *Decoder) { 5625 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5626 return MCDisassembler::Fail; 5627 Inst.addOperand(MCOperand::createImm(Val)); 5628 return MCDisassembler::Success; 5629 } 5630 5631 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5632 const void *Decoder) { 5633 DecodeStatus S = MCDisassembler::Success; 5634 5635 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5636 fieldFromInstruction(Insn, 1, 10) << 1; 5637 switch (Inst.getOpcode()) { 5638 case ARM::t2LEUpdate: 5639 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5640 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5641 LLVM_FALLTHROUGH; 5642 case ARM::t2LE: 5643 if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address, 5644 Decoder))) 5645 return MCDisassembler::Fail; 5646 break; 5647 case ARM::t2WLS: 5648 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5649 if (!Check(S, 5650 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5651 Address, Decoder)) || 5652 !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address, 5653 Decoder))) 5654 return MCDisassembler::Fail; 5655 break; 5656 case ARM::t2DLS: 5657 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5658 if (Rn == 0xF) { 5659 return MCDisassembler::Fail; 5660 } else { 5661 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5662 if (!Check(S, DecoderGPRRegisterClass(Inst, 5663 fieldFromInstruction(Insn, 16, 4), 5664 Address, Decoder))) 5665 return MCDisassembler::Fail; 5666 } 5667 break; 5668 } 5669 return S; 5670 } 5671 5672 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 5673 uint64_t Address, 5674 const void *Decoder) { 5675 DecodeStatus S = MCDisassembler::Success; 5676 5677 if (Val == 0) 5678 Val = 32; 5679 5680 Inst.addOperand(MCOperand::createImm(Val)); 5681 5682 return S; 5683 } 5684 5685 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 5686 uint64_t Address, const void *Decoder) { 5687 if ((RegNo) + 1 > 11) 5688 return MCDisassembler::Fail; 5689 5690 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 5691 Inst.addOperand(MCOperand::createReg(Register)); 5692 return MCDisassembler::Success; 5693 } 5694 5695 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 5696 uint64_t Address, const void *Decoder) { 5697 if ((RegNo) > 14) 5698 return MCDisassembler::Fail; 5699 5700 unsigned Register = GPRDecoderTable[(RegNo)]; 5701 Inst.addOperand(MCOperand::createReg(Register)); 5702 return MCDisassembler::Success; 5703 } 5704 5705 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 5706 const void *Decoder) { 5707 DecodeStatus S = MCDisassembler::Success; 5708 5709 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5710 Inst.addOperand(MCOperand::createReg(0)); 5711 if (Inst.getOpcode() == ARM::VSCCLRMD) { 5712 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 5713 (fieldFromInstruction(Insn, 12, 4) << 8) | 5714 (fieldFromInstruction(Insn, 22, 1) << 12); 5715 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 5716 return MCDisassembler::Fail; 5717 } 5718 } else { 5719 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 5720 (fieldFromInstruction(Insn, 22, 1) << 8) | 5721 (fieldFromInstruction(Insn, 12, 4) << 9); 5722 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 5723 return MCDisassembler::Fail; 5724 } 5725 } 5726 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5727 5728 return S; 5729 } 5730 5731 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 5732 switch (Opcode) { 5733 case ARM::VSTR_P0_off: 5734 case ARM::VSTR_P0_pre: 5735 case ARM::VSTR_P0_post: 5736 case ARM::VLDR_P0_off: 5737 case ARM::VLDR_P0_pre: 5738 case ARM::VLDR_P0_post: 5739 return ARM::P0; 5740 default: 5741 return 0; 5742 } 5743 } 5744 5745 template<bool Writeback> 5746 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 5747 uint64_t Address, 5748 const void *Decoder) { 5749 switch (Inst.getOpcode()) { 5750 case ARM::VSTR_FPSCR_pre: 5751 case ARM::VSTR_FPSCR_NZCVQC_pre: 5752 case ARM::VLDR_FPSCR_pre: 5753 case ARM::VLDR_FPSCR_NZCVQC_pre: 5754 case ARM::VSTR_FPSCR_off: 5755 case ARM::VSTR_FPSCR_NZCVQC_off: 5756 case ARM::VLDR_FPSCR_off: 5757 case ARM::VLDR_FPSCR_NZCVQC_off: 5758 case ARM::VSTR_FPSCR_post: 5759 case ARM::VSTR_FPSCR_NZCVQC_post: 5760 case ARM::VLDR_FPSCR_post: 5761 case ARM::VLDR_FPSCR_NZCVQC_post: 5762 const FeatureBitset &featureBits = 5763 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5764 5765 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 5766 return MCDisassembler::Fail; 5767 } 5768 5769 DecodeStatus S = MCDisassembler::Success; 5770 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 5771 Inst.addOperand(MCOperand::createReg(Sysreg)); 5772 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5773 unsigned addr = fieldFromInstruction(Val, 0, 7) | 5774 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 5775 5776 if (Writeback) { 5777 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5778 return MCDisassembler::Fail; 5779 } 5780 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 5781 return MCDisassembler::Fail; 5782 5783 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5784 Inst.addOperand(MCOperand::createReg(0)); 5785 5786 return S; 5787 } 5788 5789 static DecodeStatus DecodeMVEOverlappingLongShift( 5790 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 5791 DecodeStatus S = MCDisassembler::Success; 5792 5793 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 5794 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 5795 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 5796 5797 if (RdaHi == 14) { 5798 // This value of RdaHi (really indicating pc, because RdaHi has to 5799 // be an odd-numbered register, so the low bit will be set by the 5800 // decode function below) indicates that we must decode as SQRSHR 5801 // or UQRSHL, which both have a single Rda register field with all 5802 // four bits. 5803 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 5804 5805 switch (Inst.getOpcode()) { 5806 case ARM::t2ASRLr: 5807 case ARM::t2SQRSHRL: 5808 Inst.setOpcode(ARM::t2SQRSHR); 5809 break; 5810 case ARM::t2LSLLr: 5811 case ARM::t2UQRSHLL: 5812 Inst.setOpcode(ARM::t2UQRSHL); 5813 break; 5814 default: 5815 llvm_unreachable("Unexpected starting opcode!"); 5816 } 5817 5818 // Rda as output parameter 5819 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 5820 return MCDisassembler::Fail; 5821 5822 // Rda again as input parameter 5823 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 5824 return MCDisassembler::Fail; 5825 5826 // Rm, the amount to shift by 5827 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 5828 return MCDisassembler::Fail; 5829 5830 return S; 5831 } 5832 5833 // Otherwise, we decode as whichever opcode our caller has already 5834 // put into Inst. Those all look the same: 5835 5836 // RdaLo,RdaHi as output parameters 5837 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 5838 return MCDisassembler::Fail; 5839 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 5840 return MCDisassembler::Fail; 5841 5842 // RdaLo,RdaHi again as input parameters 5843 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 5844 return MCDisassembler::Fail; 5845 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 5846 return MCDisassembler::Fail; 5847 5848 // Rm, the amount to shift by 5849 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 5850 return MCDisassembler::Fail; 5851 5852 return S; 5853 } 5854