1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &VStream, 141 raw_ostream &CStream) const override; 142 143 private: 144 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 145 ArrayRef<uint8_t> Bytes, uint64_t Address, 146 raw_ostream &VStream, 147 raw_ostream &CStream) const; 148 149 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 150 ArrayRef<uint8_t> Bytes, uint64_t Address, 151 raw_ostream &VStream, 152 raw_ostream &CStream) const; 153 154 mutable ITStatus ITBlock; 155 mutable VPTStatus VPTBlock; 156 157 DecodeStatus AddThumbPredicate(MCInst&) const; 158 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 159 }; 160 161 } // end anonymous namespace 162 163 static bool Check(DecodeStatus &Out, DecodeStatus In) { 164 switch (In) { 165 case MCDisassembler::Success: 166 // Out stays the same. 167 return true; 168 case MCDisassembler::SoftFail: 169 Out = In; 170 return true; 171 case MCDisassembler::Fail: 172 Out = In; 173 return false; 174 } 175 llvm_unreachable("Invalid DecodeStatus!"); 176 } 177 178 // Forward declare these because the autogenerated code will reference them. 179 // Definitions are further down. 180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 216 unsigned RegNo, 217 uint64_t Address, 218 const void *Decoder); 219 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 226 unsigned RegNo, uint64_t Address, 227 const void *Decoder); 228 229 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 240 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 245 unsigned Insn, 246 uint64_t Address, 247 const void *Decoder); 248 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 257 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 258 unsigned Insn, 259 uint64_t Adddress, 260 const void *Decoder); 261 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 380 unsigned Val, 381 uint64_t Address, 382 const void *Decoder); 383 384 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 403 uint64_t Address, const void *Decoder); 404 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 405 uint64_t Address, const void* Decoder); 406 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 407 uint64_t Address, const void* Decoder); 408 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 409 uint64_t Address, const void* Decoder); 410 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 411 uint64_t Address, const void* Decoder); 412 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 417 uint64_t Address, const void *Decoder); 418 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 419 uint64_t Address, 420 const void *Decoder); 421 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 422 uint64_t Address, const void *Decoder); 423 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 424 uint64_t Address, const void *Decoder); 425 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 426 uint64_t Address, const void *Decoder); 427 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 428 uint64_t Address, const void *Decoder); 429 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 430 uint64_t Address, const void *Decoder); 431 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 432 uint64_t Address, const void *Decoder); 433 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 434 uint64_t Address, const void *Decoder); 435 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 436 uint64_t Address, const void *Decoder); 437 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 438 uint64_t Address, const void *Decoder); 439 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 440 uint64_t Address, const void *Decoder); 441 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 442 uint64_t Address, const void *Decoder); 443 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 444 uint64_t Address, const void *Decoder); 445 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 446 uint64_t Address, const void *Decoder); 447 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 448 uint64_t Address, const void *Decoder); 449 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 450 uint64_t Address, const void *Decoder); 451 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 452 uint64_t Address, const void *Decoder); 453 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 454 uint64_t Address, const void *Decoder); 455 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 456 uint64_t Address, const void *Decoder); 457 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 458 uint64_t Address, const void *Decoder); 459 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 460 uint64_t Address, const void *Decoder); 461 462 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 463 uint64_t Address, const void *Decoder); 464 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 465 uint64_t Address, const void *Decoder); 466 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 467 uint64_t Address, const void *Decoder); 468 469 template <bool isSigned, bool isNeg, int size> 470 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 471 uint64_t Address, const void *Decoder); 472 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 473 uint64_t Address, 474 const void *Decoder); 475 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 476 uint64_t Address, 477 const void *Decoder); 478 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 479 const void *Decoder); 480 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 481 uint64_t Address, 482 const void *Decoder); 483 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 484 const void *Decoder); 485 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 486 uint64_t Address, const void *Decoder); 487 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 488 uint64_t Address, const void *Decoder); 489 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 490 uint64_t Address, 491 const void *Decoder); 492 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 493 uint64_t Address, 494 const void *Decoder); 495 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 496 uint64_t Address, 497 const void *Decoder); 498 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 499 unsigned Val, 500 uint64_t Address, 501 const void *Decoder); 502 template<bool Writeback> 503 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 504 uint64_t Address, 505 const void *Decoder); 506 template <int shift> 507 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 508 uint64_t Address, 509 const void *Decoder); 510 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 511 uint64_t Address, const void *Decoder); 512 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 513 uint64_t Address, const void *Decoder); 514 template<bool scalar, OperandDecoder predicate_decoder> 515 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 516 uint64_t Address, const void *Decoder); 517 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 518 uint64_t Address, 519 const void *Decoder); 520 #include "ARMGenDisassemblerTables.inc" 521 522 static MCDisassembler *createARMDisassembler(const Target &T, 523 const MCSubtargetInfo &STI, 524 MCContext &Ctx) { 525 return new ARMDisassembler(STI, Ctx); 526 } 527 528 // Post-decoding checks 529 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 530 uint64_t Address, raw_ostream &OS, 531 raw_ostream &CS, 532 uint32_t Insn, 533 DecodeStatus Result) { 534 switch (MI.getOpcode()) { 535 case ARM::HVC: { 536 // HVC is undefined if condition = 0xf otherwise upredictable 537 // if condition != 0xe 538 uint32_t Cond = (Insn >> 28) & 0xF; 539 if (Cond == 0xF) 540 return MCDisassembler::Fail; 541 if (Cond != 0xE) 542 return MCDisassembler::SoftFail; 543 return Result; 544 } 545 case ARM::t2ADDri: 546 case ARM::t2ADDri12: 547 case ARM::t2ADDrr: 548 case ARM::t2ADDrs: 549 case ARM::t2SUBri: 550 case ARM::t2SUBri12: 551 case ARM::t2SUBrr: 552 case ARM::t2SUBrs: 553 if (MI.getOperand(0).getReg() == ARM::SP && 554 MI.getOperand(1).getReg() != ARM::SP) 555 return MCDisassembler::SoftFail; 556 return Result; 557 default: return Result; 558 } 559 } 560 561 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 562 ArrayRef<uint8_t> Bytes, 563 uint64_t Address, raw_ostream &OS, 564 raw_ostream &CS) const { 565 if (STI.getFeatureBits()[ARM::ModeThumb]) 566 return getThumbInstruction(MI, Size, Bytes, Address, OS, CS); 567 return getARMInstruction(MI, Size, Bytes, Address, OS, CS); 568 } 569 570 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 571 ArrayRef<uint8_t> Bytes, 572 uint64_t Address, 573 raw_ostream &OS, 574 raw_ostream &CS) const { 575 CommentStream = &CS; 576 577 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 578 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 579 "mode!"); 580 581 // We want to read exactly 4 bytes of data. 582 if (Bytes.size() < 4) { 583 Size = 0; 584 return MCDisassembler::Fail; 585 } 586 587 // Encoded as a small-endian 32-bit word in the stream. 588 uint32_t Insn = 589 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 590 591 // Calling the auto-generated decoder function. 592 DecodeStatus Result = 593 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 594 if (Result != MCDisassembler::Fail) { 595 Size = 4; 596 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 597 } 598 599 struct DecodeTable { 600 const uint8_t *P; 601 bool DecodePred; 602 }; 603 604 const DecodeTable Tables[] = { 605 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 606 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 607 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 608 {DecoderTablev8Crypto32, false}, 609 }; 610 611 for (auto Table : Tables) { 612 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 613 if (Result != MCDisassembler::Fail) { 614 Size = 4; 615 // Add a fake predicate operand, because we share these instruction 616 // definitions with Thumb2 where these instructions are predicable. 617 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 618 return MCDisassembler::Fail; 619 return Result; 620 } 621 } 622 623 Result = 624 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 625 if (Result != MCDisassembler::Fail) { 626 Size = 4; 627 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 628 } 629 630 Size = 4; 631 return MCDisassembler::Fail; 632 } 633 634 namespace llvm { 635 636 extern const MCInstrDesc ARMInsts[]; 637 638 } // end namespace llvm 639 640 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 641 /// immediate Value in the MCInst. The immediate Value has had any PC 642 /// adjustment made by the caller. If the instruction is a branch instruction 643 /// then isBranch is true, else false. If the getOpInfo() function was set as 644 /// part of the setupForSymbolicDisassembly() call then that function is called 645 /// to get any symbolic information at the Address for this instruction. If 646 /// that returns non-zero then the symbolic information it returns is used to 647 /// create an MCExpr and that is added as an operand to the MCInst. If 648 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 649 /// Value is done and if a symbol is found an MCExpr is created with that, else 650 /// an MCExpr with Value is created. This function returns true if it adds an 651 /// operand to the MCInst and false otherwise. 652 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 653 bool isBranch, uint64_t InstSize, 654 MCInst &MI, const void *Decoder) { 655 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 656 // FIXME: Does it make sense for value to be negative? 657 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 658 /* Offset */ 0, InstSize); 659 } 660 661 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 662 /// referenced by a load instruction with the base register that is the Pc. 663 /// These can often be values in a literal pool near the Address of the 664 /// instruction. The Address of the instruction and its immediate Value are 665 /// used as a possible literal pool entry. The SymbolLookUp call back will 666 /// return the name of a symbol referenced by the literal pool's entry if 667 /// the referenced address is that of a symbol. Or it will return a pointer to 668 /// a literal 'C' string if the referenced address of the literal pool's entry 669 /// is an address into a section with 'C' string literals. 670 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 671 const void *Decoder) { 672 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 673 Dis->tryAddingPcLoadReferenceComment(Value, Address); 674 } 675 676 // Thumb1 instructions don't have explicit S bits. Rather, they 677 // implicitly set CPSR. Since it's not represented in the encoding, the 678 // auto-generated decoder won't inject the CPSR operand. We need to fix 679 // that as a post-pass. 680 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 681 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 682 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 683 MCInst::iterator I = MI.begin(); 684 for (unsigned i = 0; i < NumOps; ++i, ++I) { 685 if (I == MI.end()) break; 686 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 687 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 688 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 689 return; 690 } 691 } 692 693 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 694 } 695 696 static bool isVectorPredicable(unsigned Opcode) { 697 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 698 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 699 for (unsigned i = 0; i < NumOps; ++i) { 700 if (ARM::isVpred(OpInfo[i].OperandType)) 701 return true; 702 } 703 return false; 704 } 705 706 // Most Thumb instructions don't have explicit predicates in the 707 // encoding, but rather get their predicates from IT context. We need 708 // to fix up the predicate operands using this context information as a 709 // post-pass. 710 MCDisassembler::DecodeStatus 711 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 712 MCDisassembler::DecodeStatus S = Success; 713 714 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 715 716 // A few instructions actually have predicates encoded in them. Don't 717 // try to overwrite it if we're seeing one of those. 718 switch (MI.getOpcode()) { 719 case ARM::tBcc: 720 case ARM::t2Bcc: 721 case ARM::tCBZ: 722 case ARM::tCBNZ: 723 case ARM::tCPS: 724 case ARM::t2CPS3p: 725 case ARM::t2CPS2p: 726 case ARM::t2CPS1p: 727 case ARM::t2CSEL: 728 case ARM::t2CSINC: 729 case ARM::t2CSINV: 730 case ARM::t2CSNEG: 731 case ARM::tMOVSr: 732 case ARM::tSETEND: 733 // Some instructions (mostly conditional branches) are not 734 // allowed in IT blocks. 735 if (ITBlock.instrInITBlock()) 736 S = SoftFail; 737 else 738 return Success; 739 break; 740 case ARM::t2HINT: 741 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 742 S = SoftFail; 743 break; 744 case ARM::tB: 745 case ARM::t2B: 746 case ARM::t2TBB: 747 case ARM::t2TBH: 748 // Some instructions (mostly unconditional branches) can 749 // only appears at the end of, or outside of, an IT. 750 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 751 S = SoftFail; 752 break; 753 default: 754 break; 755 } 756 757 // Warn on non-VPT predicable instruction in a VPT block and a VPT 758 // predicable instruction in an IT block 759 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 760 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 761 S = SoftFail; 762 763 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 764 // assume a predicate of AL. 765 unsigned CC = ARMCC::AL; 766 unsigned VCC = ARMVCC::None; 767 if (ITBlock.instrInITBlock()) { 768 CC = ITBlock.getITCC(); 769 ITBlock.advanceITState(); 770 } else if (VPTBlock.instrInVPTBlock()) { 771 VCC = VPTBlock.getVPTPred(); 772 VPTBlock.advanceVPTState(); 773 } 774 775 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 776 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 777 778 MCInst::iterator CCI = MI.begin(); 779 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 780 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 781 } 782 783 if (ARMInsts[MI.getOpcode()].isPredicable()) { 784 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 785 ++CCI; 786 if (CC == ARMCC::AL) 787 MI.insert(CCI, MCOperand::createReg(0)); 788 else 789 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 790 } else if (CC != ARMCC::AL) { 791 Check(S, SoftFail); 792 } 793 794 MCInst::iterator VCCI = MI.begin(); 795 unsigned VCCPos; 796 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 797 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 798 } 799 800 if (isVectorPredicable(MI.getOpcode())) { 801 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 802 ++VCCI; 803 if (VCC == ARMVCC::None) 804 MI.insert(VCCI, MCOperand::createReg(0)); 805 else 806 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 807 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 808 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 809 VCCPos + 2, MCOI::TIED_TO); 810 assert(TiedOp >= 0 && 811 "Inactive register in vpred_r is not tied to an output!"); 812 MI.insert(VCCI, MI.getOperand(TiedOp)); 813 } 814 } else if (VCC != ARMVCC::None) { 815 Check(S, SoftFail); 816 } 817 818 return S; 819 } 820 821 // Thumb VFP instructions are a special case. Because we share their 822 // encodings between ARM and Thumb modes, and they are predicable in ARM 823 // mode, the auto-generated decoder will give them an (incorrect) 824 // predicate operand. We need to rewrite these operands based on the IT 825 // context as a post-pass. 826 void ARMDisassembler::UpdateThumbVFPPredicate( 827 DecodeStatus &S, MCInst &MI) const { 828 unsigned CC; 829 CC = ITBlock.getITCC(); 830 if (CC == 0xF) 831 CC = ARMCC::AL; 832 if (ITBlock.instrInITBlock()) 833 ITBlock.advanceITState(); 834 else if (VPTBlock.instrInVPTBlock()) { 835 CC = VPTBlock.getVPTPred(); 836 VPTBlock.advanceVPTState(); 837 } 838 839 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 840 MCInst::iterator I = MI.begin(); 841 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 842 for (unsigned i = 0; i < NumOps; ++i, ++I) { 843 if (OpInfo[i].isPredicate() ) { 844 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 845 Check(S, SoftFail); 846 I->setImm(CC); 847 ++I; 848 if (CC == ARMCC::AL) 849 I->setReg(0); 850 else 851 I->setReg(ARM::CPSR); 852 return; 853 } 854 } 855 } 856 857 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 858 ArrayRef<uint8_t> Bytes, 859 uint64_t Address, 860 raw_ostream &OS, 861 raw_ostream &CS) const { 862 CommentStream = &CS; 863 864 assert(STI.getFeatureBits()[ARM::ModeThumb] && 865 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 866 867 // We want to read exactly 2 bytes of data. 868 if (Bytes.size() < 2) { 869 Size = 0; 870 return MCDisassembler::Fail; 871 } 872 873 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 874 DecodeStatus Result = 875 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 876 if (Result != MCDisassembler::Fail) { 877 Size = 2; 878 Check(Result, AddThumbPredicate(MI)); 879 return Result; 880 } 881 882 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 883 STI); 884 if (Result) { 885 Size = 2; 886 bool InITBlock = ITBlock.instrInITBlock(); 887 Check(Result, AddThumbPredicate(MI)); 888 AddThumb1SBit(MI, InITBlock); 889 return Result; 890 } 891 892 Result = 893 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 894 if (Result != MCDisassembler::Fail) { 895 Size = 2; 896 897 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 898 // the Thumb predicate. 899 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 900 Result = MCDisassembler::SoftFail; 901 902 Check(Result, AddThumbPredicate(MI)); 903 904 // If we find an IT instruction, we need to parse its condition 905 // code and mask operands so that we can apply them correctly 906 // to the subsequent instructions. 907 if (MI.getOpcode() == ARM::t2IT) { 908 unsigned Firstcond = MI.getOperand(0).getImm(); 909 unsigned Mask = MI.getOperand(1).getImm(); 910 ITBlock.setITState(Firstcond, Mask); 911 912 // An IT instruction that would give a 'NV' predicate is unpredictable. 913 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 914 CS << "unpredictable IT predicate sequence"; 915 } 916 917 return Result; 918 } 919 920 // We want to read exactly 4 bytes of data. 921 if (Bytes.size() < 4) { 922 Size = 0; 923 return MCDisassembler::Fail; 924 } 925 926 uint32_t Insn32 = 927 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 928 929 Result = 930 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 931 if (Result != MCDisassembler::Fail) { 932 Size = 4; 933 934 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 935 // the VPT predicate. 936 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 937 Result = MCDisassembler::SoftFail; 938 939 Check(Result, AddThumbPredicate(MI)); 940 941 if (isVPTOpcode(MI.getOpcode())) { 942 unsigned Mask = MI.getOperand(0).getImm(); 943 VPTBlock.setVPTState(Mask); 944 } 945 946 return Result; 947 } 948 949 Result = 950 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 951 if (Result != MCDisassembler::Fail) { 952 Size = 4; 953 bool InITBlock = ITBlock.instrInITBlock(); 954 Check(Result, AddThumbPredicate(MI)); 955 AddThumb1SBit(MI, InITBlock); 956 return Result; 957 } 958 959 Result = 960 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 961 if (Result != MCDisassembler::Fail) { 962 Size = 4; 963 Check(Result, AddThumbPredicate(MI)); 964 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 965 } 966 967 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 968 Result = 969 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 970 if (Result != MCDisassembler::Fail) { 971 Size = 4; 972 UpdateThumbVFPPredicate(Result, MI); 973 return Result; 974 } 975 } 976 977 Result = 978 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 979 if (Result != MCDisassembler::Fail) { 980 Size = 4; 981 return Result; 982 } 983 984 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 985 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 986 STI); 987 if (Result != MCDisassembler::Fail) { 988 Size = 4; 989 Check(Result, AddThumbPredicate(MI)); 990 return Result; 991 } 992 } 993 994 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 995 uint32_t NEONLdStInsn = Insn32; 996 NEONLdStInsn &= 0xF0FFFFFF; 997 NEONLdStInsn |= 0x04000000; 998 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 999 Address, this, STI); 1000 if (Result != MCDisassembler::Fail) { 1001 Size = 4; 1002 Check(Result, AddThumbPredicate(MI)); 1003 return Result; 1004 } 1005 } 1006 1007 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1008 uint32_t NEONDataInsn = Insn32; 1009 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1010 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1011 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1012 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1013 Address, this, STI); 1014 if (Result != MCDisassembler::Fail) { 1015 Size = 4; 1016 Check(Result, AddThumbPredicate(MI)); 1017 return Result; 1018 } 1019 1020 uint32_t NEONCryptoInsn = Insn32; 1021 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1022 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1023 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1024 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1025 Address, this, STI); 1026 if (Result != MCDisassembler::Fail) { 1027 Size = 4; 1028 return Result; 1029 } 1030 1031 uint32_t NEONv8Insn = Insn32; 1032 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1033 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1034 this, STI); 1035 if (Result != MCDisassembler::Fail) { 1036 Size = 4; 1037 return Result; 1038 } 1039 } 1040 1041 Result = 1042 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1043 if (Result != MCDisassembler::Fail) { 1044 Size = 4; 1045 Check(Result, AddThumbPredicate(MI)); 1046 return Result; 1047 } 1048 1049 Size = 0; 1050 return MCDisassembler::Fail; 1051 } 1052 1053 extern "C" void LLVMInitializeARMDisassembler() { 1054 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1055 createARMDisassembler); 1056 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1057 createARMDisassembler); 1058 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1059 createARMDisassembler); 1060 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1061 createARMDisassembler); 1062 } 1063 1064 static const uint16_t GPRDecoderTable[] = { 1065 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1066 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1067 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1068 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1069 }; 1070 1071 static const uint16_t CLRMGPRDecoderTable[] = { 1072 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1073 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1074 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1075 ARM::R12, 0, ARM::LR, ARM::APSR 1076 }; 1077 1078 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1079 uint64_t Address, const void *Decoder) { 1080 if (RegNo > 15) 1081 return MCDisassembler::Fail; 1082 1083 unsigned Register = GPRDecoderTable[RegNo]; 1084 Inst.addOperand(MCOperand::createReg(Register)); 1085 return MCDisassembler::Success; 1086 } 1087 1088 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1089 uint64_t Address, 1090 const void *Decoder) { 1091 if (RegNo > 15) 1092 return MCDisassembler::Fail; 1093 1094 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1095 if (Register == 0) 1096 return MCDisassembler::Fail; 1097 1098 Inst.addOperand(MCOperand::createReg(Register)); 1099 return MCDisassembler::Success; 1100 } 1101 1102 static DecodeStatus 1103 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1104 uint64_t Address, const void *Decoder) { 1105 DecodeStatus S = MCDisassembler::Success; 1106 1107 if (RegNo == 15) 1108 S = MCDisassembler::SoftFail; 1109 1110 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1111 1112 return S; 1113 } 1114 1115 static DecodeStatus 1116 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1117 uint64_t Address, const void *Decoder) { 1118 DecodeStatus S = MCDisassembler::Success; 1119 1120 if (RegNo == 15) 1121 { 1122 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1123 return MCDisassembler::Success; 1124 } 1125 1126 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1127 return S; 1128 } 1129 1130 static DecodeStatus 1131 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1132 uint64_t Address, const void *Decoder) { 1133 DecodeStatus S = MCDisassembler::Success; 1134 1135 if (RegNo == 15) 1136 { 1137 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1138 return MCDisassembler::Success; 1139 } 1140 1141 if (RegNo == 13) 1142 S = MCDisassembler::SoftFail; 1143 1144 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1145 return S; 1146 } 1147 1148 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1149 uint64_t Address, const void *Decoder) { 1150 if (RegNo > 7) 1151 return MCDisassembler::Fail; 1152 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1153 } 1154 1155 static const uint16_t GPRPairDecoderTable[] = { 1156 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1157 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1158 }; 1159 1160 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1161 uint64_t Address, const void *Decoder) { 1162 DecodeStatus S = MCDisassembler::Success; 1163 1164 if (RegNo > 13) 1165 return MCDisassembler::Fail; 1166 1167 if ((RegNo & 1) || RegNo == 0xe) 1168 S = MCDisassembler::SoftFail; 1169 1170 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1171 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1172 return S; 1173 } 1174 1175 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1176 uint64_t Address, const void *Decoder) { 1177 unsigned Register = 0; 1178 switch (RegNo) { 1179 case 0: 1180 Register = ARM::R0; 1181 break; 1182 case 1: 1183 Register = ARM::R1; 1184 break; 1185 case 2: 1186 Register = ARM::R2; 1187 break; 1188 case 3: 1189 Register = ARM::R3; 1190 break; 1191 case 9: 1192 Register = ARM::R9; 1193 break; 1194 case 12: 1195 Register = ARM::R12; 1196 break; 1197 default: 1198 return MCDisassembler::Fail; 1199 } 1200 1201 Inst.addOperand(MCOperand::createReg(Register)); 1202 return MCDisassembler::Success; 1203 } 1204 1205 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1206 uint64_t Address, const void *Decoder) { 1207 DecodeStatus S = MCDisassembler::Success; 1208 1209 const FeatureBitset &featureBits = 1210 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1211 1212 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1213 S = MCDisassembler::SoftFail; 1214 1215 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1216 return S; 1217 } 1218 1219 static const uint16_t SPRDecoderTable[] = { 1220 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1221 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1222 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1223 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1224 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1225 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1226 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1227 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1228 }; 1229 1230 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1231 uint64_t Address, const void *Decoder) { 1232 if (RegNo > 31) 1233 return MCDisassembler::Fail; 1234 1235 unsigned Register = SPRDecoderTable[RegNo]; 1236 Inst.addOperand(MCOperand::createReg(Register)); 1237 return MCDisassembler::Success; 1238 } 1239 1240 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1241 uint64_t Address, const void *Decoder) { 1242 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1243 } 1244 1245 static const uint16_t DPRDecoderTable[] = { 1246 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1247 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1248 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1249 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1250 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1251 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1252 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1253 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1254 }; 1255 1256 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1257 uint64_t Address, const void *Decoder) { 1258 const FeatureBitset &featureBits = 1259 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1260 1261 bool hasD32 = featureBits[ARM::FeatureD32]; 1262 1263 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1264 return MCDisassembler::Fail; 1265 1266 unsigned Register = DPRDecoderTable[RegNo]; 1267 Inst.addOperand(MCOperand::createReg(Register)); 1268 return MCDisassembler::Success; 1269 } 1270 1271 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1272 uint64_t Address, const void *Decoder) { 1273 if (RegNo > 7) 1274 return MCDisassembler::Fail; 1275 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1276 } 1277 1278 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1279 uint64_t Address, const void *Decoder) { 1280 if (RegNo > 15) 1281 return MCDisassembler::Fail; 1282 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1283 } 1284 1285 static DecodeStatus 1286 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1287 uint64_t Address, const void *Decoder) { 1288 if (RegNo > 15) 1289 return MCDisassembler::Fail; 1290 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1291 } 1292 1293 static const uint16_t QPRDecoderTable[] = { 1294 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1295 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1296 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1297 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1298 }; 1299 1300 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1301 uint64_t Address, const void *Decoder) { 1302 if (RegNo > 31 || (RegNo & 1) != 0) 1303 return MCDisassembler::Fail; 1304 RegNo >>= 1; 1305 1306 unsigned Register = QPRDecoderTable[RegNo]; 1307 Inst.addOperand(MCOperand::createReg(Register)); 1308 return MCDisassembler::Success; 1309 } 1310 1311 static const uint16_t DPairDecoderTable[] = { 1312 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1313 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1314 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1315 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1316 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1317 ARM::Q15 1318 }; 1319 1320 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1321 uint64_t Address, const void *Decoder) { 1322 if (RegNo > 30) 1323 return MCDisassembler::Fail; 1324 1325 unsigned Register = DPairDecoderTable[RegNo]; 1326 Inst.addOperand(MCOperand::createReg(Register)); 1327 return MCDisassembler::Success; 1328 } 1329 1330 static const uint16_t DPairSpacedDecoderTable[] = { 1331 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1332 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1333 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1334 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1335 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1336 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1337 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1338 ARM::D28_D30, ARM::D29_D31 1339 }; 1340 1341 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1342 unsigned RegNo, 1343 uint64_t Address, 1344 const void *Decoder) { 1345 if (RegNo > 29) 1346 return MCDisassembler::Fail; 1347 1348 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1349 Inst.addOperand(MCOperand::createReg(Register)); 1350 return MCDisassembler::Success; 1351 } 1352 1353 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1354 uint64_t Address, const void *Decoder) { 1355 DecodeStatus S = MCDisassembler::Success; 1356 if (Val == 0xF) return MCDisassembler::Fail; 1357 // AL predicate is not allowed on Thumb1 branches. 1358 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1359 return MCDisassembler::Fail; 1360 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1361 Check(S, MCDisassembler::SoftFail); 1362 Inst.addOperand(MCOperand::createImm(Val)); 1363 if (Val == ARMCC::AL) { 1364 Inst.addOperand(MCOperand::createReg(0)); 1365 } else 1366 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1367 return S; 1368 } 1369 1370 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1371 uint64_t Address, const void *Decoder) { 1372 if (Val) 1373 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1374 else 1375 Inst.addOperand(MCOperand::createReg(0)); 1376 return MCDisassembler::Success; 1377 } 1378 1379 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1380 uint64_t Address, const void *Decoder) { 1381 DecodeStatus S = MCDisassembler::Success; 1382 1383 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1384 unsigned type = fieldFromInstruction(Val, 5, 2); 1385 unsigned imm = fieldFromInstruction(Val, 7, 5); 1386 1387 // Register-immediate 1388 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1389 return MCDisassembler::Fail; 1390 1391 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1392 switch (type) { 1393 case 0: 1394 Shift = ARM_AM::lsl; 1395 break; 1396 case 1: 1397 Shift = ARM_AM::lsr; 1398 break; 1399 case 2: 1400 Shift = ARM_AM::asr; 1401 break; 1402 case 3: 1403 Shift = ARM_AM::ror; 1404 break; 1405 } 1406 1407 if (Shift == ARM_AM::ror && imm == 0) 1408 Shift = ARM_AM::rrx; 1409 1410 unsigned Op = Shift | (imm << 3); 1411 Inst.addOperand(MCOperand::createImm(Op)); 1412 1413 return S; 1414 } 1415 1416 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1417 uint64_t Address, const void *Decoder) { 1418 DecodeStatus S = MCDisassembler::Success; 1419 1420 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1421 unsigned type = fieldFromInstruction(Val, 5, 2); 1422 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1423 1424 // Register-register 1425 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1426 return MCDisassembler::Fail; 1427 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1428 return MCDisassembler::Fail; 1429 1430 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1431 switch (type) { 1432 case 0: 1433 Shift = ARM_AM::lsl; 1434 break; 1435 case 1: 1436 Shift = ARM_AM::lsr; 1437 break; 1438 case 2: 1439 Shift = ARM_AM::asr; 1440 break; 1441 case 3: 1442 Shift = ARM_AM::ror; 1443 break; 1444 } 1445 1446 Inst.addOperand(MCOperand::createImm(Shift)); 1447 1448 return S; 1449 } 1450 1451 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1452 uint64_t Address, const void *Decoder) { 1453 DecodeStatus S = MCDisassembler::Success; 1454 1455 bool NeedDisjointWriteback = false; 1456 unsigned WritebackReg = 0; 1457 bool CLRM = false; 1458 switch (Inst.getOpcode()) { 1459 default: 1460 break; 1461 case ARM::LDMIA_UPD: 1462 case ARM::LDMDB_UPD: 1463 case ARM::LDMIB_UPD: 1464 case ARM::LDMDA_UPD: 1465 case ARM::t2LDMIA_UPD: 1466 case ARM::t2LDMDB_UPD: 1467 case ARM::t2STMIA_UPD: 1468 case ARM::t2STMDB_UPD: 1469 NeedDisjointWriteback = true; 1470 WritebackReg = Inst.getOperand(0).getReg(); 1471 break; 1472 case ARM::t2CLRM: 1473 CLRM = true; 1474 break; 1475 } 1476 1477 // Empty register lists are not allowed. 1478 if (Val == 0) return MCDisassembler::Fail; 1479 for (unsigned i = 0; i < 16; ++i) { 1480 if (Val & (1 << i)) { 1481 if (CLRM) { 1482 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1483 return MCDisassembler::Fail; 1484 } 1485 } else { 1486 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1487 return MCDisassembler::Fail; 1488 // Writeback not allowed if Rn is in the target list. 1489 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1490 Check(S, MCDisassembler::SoftFail); 1491 } 1492 } 1493 } 1494 1495 return S; 1496 } 1497 1498 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1499 uint64_t Address, const void *Decoder) { 1500 DecodeStatus S = MCDisassembler::Success; 1501 1502 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1503 unsigned regs = fieldFromInstruction(Val, 0, 8); 1504 1505 // In case of unpredictable encoding, tweak the operands. 1506 if (regs == 0 || (Vd + regs) > 32) { 1507 regs = Vd + regs > 32 ? 32 - Vd : regs; 1508 regs = std::max( 1u, regs); 1509 S = MCDisassembler::SoftFail; 1510 } 1511 1512 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1513 return MCDisassembler::Fail; 1514 for (unsigned i = 0; i < (regs - 1); ++i) { 1515 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1516 return MCDisassembler::Fail; 1517 } 1518 1519 return S; 1520 } 1521 1522 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1523 uint64_t Address, const void *Decoder) { 1524 DecodeStatus S = MCDisassembler::Success; 1525 1526 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1527 unsigned regs = fieldFromInstruction(Val, 1, 7); 1528 1529 // In case of unpredictable encoding, tweak the operands. 1530 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1531 regs = Vd + regs > 32 ? 32 - Vd : regs; 1532 regs = std::max( 1u, regs); 1533 regs = std::min(16u, regs); 1534 S = MCDisassembler::SoftFail; 1535 } 1536 1537 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1538 return MCDisassembler::Fail; 1539 for (unsigned i = 0; i < (regs - 1); ++i) { 1540 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1541 return MCDisassembler::Fail; 1542 } 1543 1544 return S; 1545 } 1546 1547 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1548 uint64_t Address, const void *Decoder) { 1549 // This operand encodes a mask of contiguous zeros between a specified MSB 1550 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1551 // the mask of all bits LSB-and-lower, and then xor them to create 1552 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1553 // create the final mask. 1554 unsigned msb = fieldFromInstruction(Val, 5, 5); 1555 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1556 1557 DecodeStatus S = MCDisassembler::Success; 1558 if (lsb > msb) { 1559 Check(S, MCDisassembler::SoftFail); 1560 // The check above will cause the warning for the "potentially undefined 1561 // instruction encoding" but we can't build a bad MCOperand value here 1562 // with a lsb > msb or else printing the MCInst will cause a crash. 1563 lsb = msb; 1564 } 1565 1566 uint32_t msb_mask = 0xFFFFFFFF; 1567 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1568 uint32_t lsb_mask = (1U << lsb) - 1; 1569 1570 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1571 return S; 1572 } 1573 1574 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1575 uint64_t Address, const void *Decoder) { 1576 DecodeStatus S = MCDisassembler::Success; 1577 1578 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1579 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1580 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1581 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1582 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1583 unsigned U = fieldFromInstruction(Insn, 23, 1); 1584 const FeatureBitset &featureBits = 1585 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1586 1587 switch (Inst.getOpcode()) { 1588 case ARM::LDC_OFFSET: 1589 case ARM::LDC_PRE: 1590 case ARM::LDC_POST: 1591 case ARM::LDC_OPTION: 1592 case ARM::LDCL_OFFSET: 1593 case ARM::LDCL_PRE: 1594 case ARM::LDCL_POST: 1595 case ARM::LDCL_OPTION: 1596 case ARM::STC_OFFSET: 1597 case ARM::STC_PRE: 1598 case ARM::STC_POST: 1599 case ARM::STC_OPTION: 1600 case ARM::STCL_OFFSET: 1601 case ARM::STCL_PRE: 1602 case ARM::STCL_POST: 1603 case ARM::STCL_OPTION: 1604 case ARM::t2LDC_OFFSET: 1605 case ARM::t2LDC_PRE: 1606 case ARM::t2LDC_POST: 1607 case ARM::t2LDC_OPTION: 1608 case ARM::t2LDCL_OFFSET: 1609 case ARM::t2LDCL_PRE: 1610 case ARM::t2LDCL_POST: 1611 case ARM::t2LDCL_OPTION: 1612 case ARM::t2STC_OFFSET: 1613 case ARM::t2STC_PRE: 1614 case ARM::t2STC_POST: 1615 case ARM::t2STC_OPTION: 1616 case ARM::t2STCL_OFFSET: 1617 case ARM::t2STCL_PRE: 1618 case ARM::t2STCL_POST: 1619 case ARM::t2STCL_OPTION: 1620 case ARM::t2LDC2_OFFSET: 1621 case ARM::t2LDC2L_OFFSET: 1622 case ARM::t2LDC2_PRE: 1623 case ARM::t2LDC2L_PRE: 1624 case ARM::t2STC2_OFFSET: 1625 case ARM::t2STC2L_OFFSET: 1626 case ARM::t2STC2_PRE: 1627 case ARM::t2STC2L_PRE: 1628 case ARM::LDC2_OFFSET: 1629 case ARM::LDC2L_OFFSET: 1630 case ARM::LDC2_PRE: 1631 case ARM::LDC2L_PRE: 1632 case ARM::STC2_OFFSET: 1633 case ARM::STC2L_OFFSET: 1634 case ARM::STC2_PRE: 1635 case ARM::STC2L_PRE: 1636 case ARM::t2LDC2_OPTION: 1637 case ARM::t2STC2_OPTION: 1638 case ARM::t2LDC2_POST: 1639 case ARM::t2LDC2L_POST: 1640 case ARM::t2STC2_POST: 1641 case ARM::t2STC2L_POST: 1642 case ARM::LDC2_POST: 1643 case ARM::LDC2L_POST: 1644 case ARM::STC2_POST: 1645 case ARM::STC2L_POST: 1646 if (coproc == 0xA || coproc == 0xB || 1647 (featureBits[ARM::HasV8_1MMainlineOps] && 1648 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1649 coproc == 0xE || coproc == 0xF))) 1650 return MCDisassembler::Fail; 1651 break; 1652 default: 1653 break; 1654 } 1655 1656 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1657 return MCDisassembler::Fail; 1658 1659 Inst.addOperand(MCOperand::createImm(coproc)); 1660 Inst.addOperand(MCOperand::createImm(CRd)); 1661 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1662 return MCDisassembler::Fail; 1663 1664 switch (Inst.getOpcode()) { 1665 case ARM::t2LDC2_OFFSET: 1666 case ARM::t2LDC2L_OFFSET: 1667 case ARM::t2LDC2_PRE: 1668 case ARM::t2LDC2L_PRE: 1669 case ARM::t2STC2_OFFSET: 1670 case ARM::t2STC2L_OFFSET: 1671 case ARM::t2STC2_PRE: 1672 case ARM::t2STC2L_PRE: 1673 case ARM::LDC2_OFFSET: 1674 case ARM::LDC2L_OFFSET: 1675 case ARM::LDC2_PRE: 1676 case ARM::LDC2L_PRE: 1677 case ARM::STC2_OFFSET: 1678 case ARM::STC2L_OFFSET: 1679 case ARM::STC2_PRE: 1680 case ARM::STC2L_PRE: 1681 case ARM::t2LDC_OFFSET: 1682 case ARM::t2LDCL_OFFSET: 1683 case ARM::t2LDC_PRE: 1684 case ARM::t2LDCL_PRE: 1685 case ARM::t2STC_OFFSET: 1686 case ARM::t2STCL_OFFSET: 1687 case ARM::t2STC_PRE: 1688 case ARM::t2STCL_PRE: 1689 case ARM::LDC_OFFSET: 1690 case ARM::LDCL_OFFSET: 1691 case ARM::LDC_PRE: 1692 case ARM::LDCL_PRE: 1693 case ARM::STC_OFFSET: 1694 case ARM::STCL_OFFSET: 1695 case ARM::STC_PRE: 1696 case ARM::STCL_PRE: 1697 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1698 Inst.addOperand(MCOperand::createImm(imm)); 1699 break; 1700 case ARM::t2LDC2_POST: 1701 case ARM::t2LDC2L_POST: 1702 case ARM::t2STC2_POST: 1703 case ARM::t2STC2L_POST: 1704 case ARM::LDC2_POST: 1705 case ARM::LDC2L_POST: 1706 case ARM::STC2_POST: 1707 case ARM::STC2L_POST: 1708 case ARM::t2LDC_POST: 1709 case ARM::t2LDCL_POST: 1710 case ARM::t2STC_POST: 1711 case ARM::t2STCL_POST: 1712 case ARM::LDC_POST: 1713 case ARM::LDCL_POST: 1714 case ARM::STC_POST: 1715 case ARM::STCL_POST: 1716 imm |= U << 8; 1717 LLVM_FALLTHROUGH; 1718 default: 1719 // The 'option' variant doesn't encode 'U' in the immediate since 1720 // the immediate is unsigned [0,255]. 1721 Inst.addOperand(MCOperand::createImm(imm)); 1722 break; 1723 } 1724 1725 switch (Inst.getOpcode()) { 1726 case ARM::LDC_OFFSET: 1727 case ARM::LDC_PRE: 1728 case ARM::LDC_POST: 1729 case ARM::LDC_OPTION: 1730 case ARM::LDCL_OFFSET: 1731 case ARM::LDCL_PRE: 1732 case ARM::LDCL_POST: 1733 case ARM::LDCL_OPTION: 1734 case ARM::STC_OFFSET: 1735 case ARM::STC_PRE: 1736 case ARM::STC_POST: 1737 case ARM::STC_OPTION: 1738 case ARM::STCL_OFFSET: 1739 case ARM::STCL_PRE: 1740 case ARM::STCL_POST: 1741 case ARM::STCL_OPTION: 1742 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1743 return MCDisassembler::Fail; 1744 break; 1745 default: 1746 break; 1747 } 1748 1749 return S; 1750 } 1751 1752 static DecodeStatus 1753 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1754 uint64_t Address, const void *Decoder) { 1755 DecodeStatus S = MCDisassembler::Success; 1756 1757 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1758 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1759 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1760 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1761 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1762 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1763 unsigned P = fieldFromInstruction(Insn, 24, 1); 1764 unsigned W = fieldFromInstruction(Insn, 21, 1); 1765 1766 // On stores, the writeback operand precedes Rt. 1767 switch (Inst.getOpcode()) { 1768 case ARM::STR_POST_IMM: 1769 case ARM::STR_POST_REG: 1770 case ARM::STRB_POST_IMM: 1771 case ARM::STRB_POST_REG: 1772 case ARM::STRT_POST_REG: 1773 case ARM::STRT_POST_IMM: 1774 case ARM::STRBT_POST_REG: 1775 case ARM::STRBT_POST_IMM: 1776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1777 return MCDisassembler::Fail; 1778 break; 1779 default: 1780 break; 1781 } 1782 1783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1784 return MCDisassembler::Fail; 1785 1786 // On loads, the writeback operand comes after Rt. 1787 switch (Inst.getOpcode()) { 1788 case ARM::LDR_POST_IMM: 1789 case ARM::LDR_POST_REG: 1790 case ARM::LDRB_POST_IMM: 1791 case ARM::LDRB_POST_REG: 1792 case ARM::LDRBT_POST_REG: 1793 case ARM::LDRBT_POST_IMM: 1794 case ARM::LDRT_POST_REG: 1795 case ARM::LDRT_POST_IMM: 1796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1797 return MCDisassembler::Fail; 1798 break; 1799 default: 1800 break; 1801 } 1802 1803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1804 return MCDisassembler::Fail; 1805 1806 ARM_AM::AddrOpc Op = ARM_AM::add; 1807 if (!fieldFromInstruction(Insn, 23, 1)) 1808 Op = ARM_AM::sub; 1809 1810 bool writeback = (P == 0) || (W == 1); 1811 unsigned idx_mode = 0; 1812 if (P && writeback) 1813 idx_mode = ARMII::IndexModePre; 1814 else if (!P && writeback) 1815 idx_mode = ARMII::IndexModePost; 1816 1817 if (writeback && (Rn == 15 || Rn == Rt)) 1818 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1819 1820 if (reg) { 1821 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1822 return MCDisassembler::Fail; 1823 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1824 switch( fieldFromInstruction(Insn, 5, 2)) { 1825 case 0: 1826 Opc = ARM_AM::lsl; 1827 break; 1828 case 1: 1829 Opc = ARM_AM::lsr; 1830 break; 1831 case 2: 1832 Opc = ARM_AM::asr; 1833 break; 1834 case 3: 1835 Opc = ARM_AM::ror; 1836 break; 1837 default: 1838 return MCDisassembler::Fail; 1839 } 1840 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1841 if (Opc == ARM_AM::ror && amt == 0) 1842 Opc = ARM_AM::rrx; 1843 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1844 1845 Inst.addOperand(MCOperand::createImm(imm)); 1846 } else { 1847 Inst.addOperand(MCOperand::createReg(0)); 1848 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1849 Inst.addOperand(MCOperand::createImm(tmp)); 1850 } 1851 1852 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1853 return MCDisassembler::Fail; 1854 1855 return S; 1856 } 1857 1858 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1859 uint64_t Address, const void *Decoder) { 1860 DecodeStatus S = MCDisassembler::Success; 1861 1862 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1863 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1864 unsigned type = fieldFromInstruction(Val, 5, 2); 1865 unsigned imm = fieldFromInstruction(Val, 7, 5); 1866 unsigned U = fieldFromInstruction(Val, 12, 1); 1867 1868 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1869 switch (type) { 1870 case 0: 1871 ShOp = ARM_AM::lsl; 1872 break; 1873 case 1: 1874 ShOp = ARM_AM::lsr; 1875 break; 1876 case 2: 1877 ShOp = ARM_AM::asr; 1878 break; 1879 case 3: 1880 ShOp = ARM_AM::ror; 1881 break; 1882 } 1883 1884 if (ShOp == ARM_AM::ror && imm == 0) 1885 ShOp = ARM_AM::rrx; 1886 1887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1888 return MCDisassembler::Fail; 1889 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1890 return MCDisassembler::Fail; 1891 unsigned shift; 1892 if (U) 1893 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1894 else 1895 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1896 Inst.addOperand(MCOperand::createImm(shift)); 1897 1898 return S; 1899 } 1900 1901 static DecodeStatus 1902 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1903 uint64_t Address, const void *Decoder) { 1904 DecodeStatus S = MCDisassembler::Success; 1905 1906 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1907 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1908 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1909 unsigned type = fieldFromInstruction(Insn, 22, 1); 1910 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1911 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1912 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1913 unsigned W = fieldFromInstruction(Insn, 21, 1); 1914 unsigned P = fieldFromInstruction(Insn, 24, 1); 1915 unsigned Rt2 = Rt + 1; 1916 1917 bool writeback = (W == 1) | (P == 0); 1918 1919 // For {LD,ST}RD, Rt must be even, else undefined. 1920 switch (Inst.getOpcode()) { 1921 case ARM::STRD: 1922 case ARM::STRD_PRE: 1923 case ARM::STRD_POST: 1924 case ARM::LDRD: 1925 case ARM::LDRD_PRE: 1926 case ARM::LDRD_POST: 1927 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1928 break; 1929 default: 1930 break; 1931 } 1932 switch (Inst.getOpcode()) { 1933 case ARM::STRD: 1934 case ARM::STRD_PRE: 1935 case ARM::STRD_POST: 1936 if (P == 0 && W == 1) 1937 S = MCDisassembler::SoftFail; 1938 1939 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1940 S = MCDisassembler::SoftFail; 1941 if (type && Rm == 15) 1942 S = MCDisassembler::SoftFail; 1943 if (Rt2 == 15) 1944 S = MCDisassembler::SoftFail; 1945 if (!type && fieldFromInstruction(Insn, 8, 4)) 1946 S = MCDisassembler::SoftFail; 1947 break; 1948 case ARM::STRH: 1949 case ARM::STRH_PRE: 1950 case ARM::STRH_POST: 1951 if (Rt == 15) 1952 S = MCDisassembler::SoftFail; 1953 if (writeback && (Rn == 15 || Rn == Rt)) 1954 S = MCDisassembler::SoftFail; 1955 if (!type && Rm == 15) 1956 S = MCDisassembler::SoftFail; 1957 break; 1958 case ARM::LDRD: 1959 case ARM::LDRD_PRE: 1960 case ARM::LDRD_POST: 1961 if (type && Rn == 15) { 1962 if (Rt2 == 15) 1963 S = MCDisassembler::SoftFail; 1964 break; 1965 } 1966 if (P == 0 && W == 1) 1967 S = MCDisassembler::SoftFail; 1968 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1969 S = MCDisassembler::SoftFail; 1970 if (!type && writeback && Rn == 15) 1971 S = MCDisassembler::SoftFail; 1972 if (writeback && (Rn == Rt || Rn == Rt2)) 1973 S = MCDisassembler::SoftFail; 1974 break; 1975 case ARM::LDRH: 1976 case ARM::LDRH_PRE: 1977 case ARM::LDRH_POST: 1978 if (type && Rn == 15) { 1979 if (Rt == 15) 1980 S = MCDisassembler::SoftFail; 1981 break; 1982 } 1983 if (Rt == 15) 1984 S = MCDisassembler::SoftFail; 1985 if (!type && Rm == 15) 1986 S = MCDisassembler::SoftFail; 1987 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1988 S = MCDisassembler::SoftFail; 1989 break; 1990 case ARM::LDRSH: 1991 case ARM::LDRSH_PRE: 1992 case ARM::LDRSH_POST: 1993 case ARM::LDRSB: 1994 case ARM::LDRSB_PRE: 1995 case ARM::LDRSB_POST: 1996 if (type && Rn == 15) { 1997 if (Rt == 15) 1998 S = MCDisassembler::SoftFail; 1999 break; 2000 } 2001 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2002 S = MCDisassembler::SoftFail; 2003 if (!type && (Rt == 15 || Rm == 15)) 2004 S = MCDisassembler::SoftFail; 2005 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2006 S = MCDisassembler::SoftFail; 2007 break; 2008 default: 2009 break; 2010 } 2011 2012 if (writeback) { // Writeback 2013 if (P) 2014 U |= ARMII::IndexModePre << 9; 2015 else 2016 U |= ARMII::IndexModePost << 9; 2017 2018 // On stores, the writeback operand precedes Rt. 2019 switch (Inst.getOpcode()) { 2020 case ARM::STRD: 2021 case ARM::STRD_PRE: 2022 case ARM::STRD_POST: 2023 case ARM::STRH: 2024 case ARM::STRH_PRE: 2025 case ARM::STRH_POST: 2026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2027 return MCDisassembler::Fail; 2028 break; 2029 default: 2030 break; 2031 } 2032 } 2033 2034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2035 return MCDisassembler::Fail; 2036 switch (Inst.getOpcode()) { 2037 case ARM::STRD: 2038 case ARM::STRD_PRE: 2039 case ARM::STRD_POST: 2040 case ARM::LDRD: 2041 case ARM::LDRD_PRE: 2042 case ARM::LDRD_POST: 2043 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2044 return MCDisassembler::Fail; 2045 break; 2046 default: 2047 break; 2048 } 2049 2050 if (writeback) { 2051 // On loads, the writeback operand comes after Rt. 2052 switch (Inst.getOpcode()) { 2053 case ARM::LDRD: 2054 case ARM::LDRD_PRE: 2055 case ARM::LDRD_POST: 2056 case ARM::LDRH: 2057 case ARM::LDRH_PRE: 2058 case ARM::LDRH_POST: 2059 case ARM::LDRSH: 2060 case ARM::LDRSH_PRE: 2061 case ARM::LDRSH_POST: 2062 case ARM::LDRSB: 2063 case ARM::LDRSB_PRE: 2064 case ARM::LDRSB_POST: 2065 case ARM::LDRHTr: 2066 case ARM::LDRSBTr: 2067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2068 return MCDisassembler::Fail; 2069 break; 2070 default: 2071 break; 2072 } 2073 } 2074 2075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2076 return MCDisassembler::Fail; 2077 2078 if (type) { 2079 Inst.addOperand(MCOperand::createReg(0)); 2080 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2081 } else { 2082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2083 return MCDisassembler::Fail; 2084 Inst.addOperand(MCOperand::createImm(U)); 2085 } 2086 2087 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2088 return MCDisassembler::Fail; 2089 2090 return S; 2091 } 2092 2093 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2094 uint64_t Address, const void *Decoder) { 2095 DecodeStatus S = MCDisassembler::Success; 2096 2097 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2098 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2099 2100 switch (mode) { 2101 case 0: 2102 mode = ARM_AM::da; 2103 break; 2104 case 1: 2105 mode = ARM_AM::ia; 2106 break; 2107 case 2: 2108 mode = ARM_AM::db; 2109 break; 2110 case 3: 2111 mode = ARM_AM::ib; 2112 break; 2113 } 2114 2115 Inst.addOperand(MCOperand::createImm(mode)); 2116 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2117 return MCDisassembler::Fail; 2118 2119 return S; 2120 } 2121 2122 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2123 uint64_t Address, const void *Decoder) { 2124 DecodeStatus S = MCDisassembler::Success; 2125 2126 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2127 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2128 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2129 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2130 2131 if (pred == 0xF) 2132 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2133 2134 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2135 return MCDisassembler::Fail; 2136 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2137 return MCDisassembler::Fail; 2138 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2139 return MCDisassembler::Fail; 2140 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2141 return MCDisassembler::Fail; 2142 return S; 2143 } 2144 2145 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2146 unsigned Insn, 2147 uint64_t Address, const void *Decoder) { 2148 DecodeStatus S = MCDisassembler::Success; 2149 2150 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2151 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2152 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2153 2154 if (pred == 0xF) { 2155 // Ambiguous with RFE and SRS 2156 switch (Inst.getOpcode()) { 2157 case ARM::LDMDA: 2158 Inst.setOpcode(ARM::RFEDA); 2159 break; 2160 case ARM::LDMDA_UPD: 2161 Inst.setOpcode(ARM::RFEDA_UPD); 2162 break; 2163 case ARM::LDMDB: 2164 Inst.setOpcode(ARM::RFEDB); 2165 break; 2166 case ARM::LDMDB_UPD: 2167 Inst.setOpcode(ARM::RFEDB_UPD); 2168 break; 2169 case ARM::LDMIA: 2170 Inst.setOpcode(ARM::RFEIA); 2171 break; 2172 case ARM::LDMIA_UPD: 2173 Inst.setOpcode(ARM::RFEIA_UPD); 2174 break; 2175 case ARM::LDMIB: 2176 Inst.setOpcode(ARM::RFEIB); 2177 break; 2178 case ARM::LDMIB_UPD: 2179 Inst.setOpcode(ARM::RFEIB_UPD); 2180 break; 2181 case ARM::STMDA: 2182 Inst.setOpcode(ARM::SRSDA); 2183 break; 2184 case ARM::STMDA_UPD: 2185 Inst.setOpcode(ARM::SRSDA_UPD); 2186 break; 2187 case ARM::STMDB: 2188 Inst.setOpcode(ARM::SRSDB); 2189 break; 2190 case ARM::STMDB_UPD: 2191 Inst.setOpcode(ARM::SRSDB_UPD); 2192 break; 2193 case ARM::STMIA: 2194 Inst.setOpcode(ARM::SRSIA); 2195 break; 2196 case ARM::STMIA_UPD: 2197 Inst.setOpcode(ARM::SRSIA_UPD); 2198 break; 2199 case ARM::STMIB: 2200 Inst.setOpcode(ARM::SRSIB); 2201 break; 2202 case ARM::STMIB_UPD: 2203 Inst.setOpcode(ARM::SRSIB_UPD); 2204 break; 2205 default: 2206 return MCDisassembler::Fail; 2207 } 2208 2209 // For stores (which become SRS's, the only operand is the mode. 2210 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2211 // Check SRS encoding constraints 2212 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2213 fieldFromInstruction(Insn, 20, 1) == 0)) 2214 return MCDisassembler::Fail; 2215 2216 Inst.addOperand( 2217 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2218 return S; 2219 } 2220 2221 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2222 } 2223 2224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2225 return MCDisassembler::Fail; 2226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2227 return MCDisassembler::Fail; // Tied 2228 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2229 return MCDisassembler::Fail; 2230 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2231 return MCDisassembler::Fail; 2232 2233 return S; 2234 } 2235 2236 // Check for UNPREDICTABLE predicated ESB instruction 2237 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2238 uint64_t Address, const void *Decoder) { 2239 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2240 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2241 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2242 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2243 2244 DecodeStatus S = MCDisassembler::Success; 2245 2246 Inst.addOperand(MCOperand::createImm(imm8)); 2247 2248 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2249 return MCDisassembler::Fail; 2250 2251 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2252 // so all predicates should be allowed. 2253 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2254 S = MCDisassembler::SoftFail; 2255 2256 return S; 2257 } 2258 2259 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2260 uint64_t Address, const void *Decoder) { 2261 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2262 unsigned M = fieldFromInstruction(Insn, 17, 1); 2263 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2264 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2265 2266 DecodeStatus S = MCDisassembler::Success; 2267 2268 // This decoder is called from multiple location that do not check 2269 // the full encoding is valid before they do. 2270 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2271 fieldFromInstruction(Insn, 16, 1) != 0 || 2272 fieldFromInstruction(Insn, 20, 8) != 0x10) 2273 return MCDisassembler::Fail; 2274 2275 // imod == '01' --> UNPREDICTABLE 2276 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2277 // return failure here. The '01' imod value is unprintable, so there's 2278 // nothing useful we could do even if we returned UNPREDICTABLE. 2279 2280 if (imod == 1) return MCDisassembler::Fail; 2281 2282 if (imod && M) { 2283 Inst.setOpcode(ARM::CPS3p); 2284 Inst.addOperand(MCOperand::createImm(imod)); 2285 Inst.addOperand(MCOperand::createImm(iflags)); 2286 Inst.addOperand(MCOperand::createImm(mode)); 2287 } else if (imod && !M) { 2288 Inst.setOpcode(ARM::CPS2p); 2289 Inst.addOperand(MCOperand::createImm(imod)); 2290 Inst.addOperand(MCOperand::createImm(iflags)); 2291 if (mode) S = MCDisassembler::SoftFail; 2292 } else if (!imod && M) { 2293 Inst.setOpcode(ARM::CPS1p); 2294 Inst.addOperand(MCOperand::createImm(mode)); 2295 if (iflags) S = MCDisassembler::SoftFail; 2296 } else { 2297 // imod == '00' && M == '0' --> UNPREDICTABLE 2298 Inst.setOpcode(ARM::CPS1p); 2299 Inst.addOperand(MCOperand::createImm(mode)); 2300 S = MCDisassembler::SoftFail; 2301 } 2302 2303 return S; 2304 } 2305 2306 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2307 uint64_t Address, const void *Decoder) { 2308 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2309 unsigned M = fieldFromInstruction(Insn, 8, 1); 2310 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2311 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2312 2313 DecodeStatus S = MCDisassembler::Success; 2314 2315 // imod == '01' --> UNPREDICTABLE 2316 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2317 // return failure here. The '01' imod value is unprintable, so there's 2318 // nothing useful we could do even if we returned UNPREDICTABLE. 2319 2320 if (imod == 1) return MCDisassembler::Fail; 2321 2322 if (imod && M) { 2323 Inst.setOpcode(ARM::t2CPS3p); 2324 Inst.addOperand(MCOperand::createImm(imod)); 2325 Inst.addOperand(MCOperand::createImm(iflags)); 2326 Inst.addOperand(MCOperand::createImm(mode)); 2327 } else if (imod && !M) { 2328 Inst.setOpcode(ARM::t2CPS2p); 2329 Inst.addOperand(MCOperand::createImm(imod)); 2330 Inst.addOperand(MCOperand::createImm(iflags)); 2331 if (mode) S = MCDisassembler::SoftFail; 2332 } else if (!imod && M) { 2333 Inst.setOpcode(ARM::t2CPS1p); 2334 Inst.addOperand(MCOperand::createImm(mode)); 2335 if (iflags) S = MCDisassembler::SoftFail; 2336 } else { 2337 // imod == '00' && M == '0' --> this is a HINT instruction 2338 int imm = fieldFromInstruction(Insn, 0, 8); 2339 // HINT are defined only for immediate in [0..4] 2340 if(imm > 4) return MCDisassembler::Fail; 2341 Inst.setOpcode(ARM::t2HINT); 2342 Inst.addOperand(MCOperand::createImm(imm)); 2343 } 2344 2345 return S; 2346 } 2347 2348 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2349 uint64_t Address, const void *Decoder) { 2350 DecodeStatus S = MCDisassembler::Success; 2351 2352 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2353 unsigned imm = 0; 2354 2355 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2356 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2357 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2358 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2359 2360 if (Inst.getOpcode() == ARM::t2MOVTi16) 2361 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2362 return MCDisassembler::Fail; 2363 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2364 return MCDisassembler::Fail; 2365 2366 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2367 Inst.addOperand(MCOperand::createImm(imm)); 2368 2369 return S; 2370 } 2371 2372 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2373 uint64_t Address, const void *Decoder) { 2374 DecodeStatus S = MCDisassembler::Success; 2375 2376 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2377 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2378 unsigned imm = 0; 2379 2380 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2381 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2382 2383 if (Inst.getOpcode() == ARM::MOVTi16) 2384 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2385 return MCDisassembler::Fail; 2386 2387 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2388 return MCDisassembler::Fail; 2389 2390 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2391 Inst.addOperand(MCOperand::createImm(imm)); 2392 2393 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2394 return MCDisassembler::Fail; 2395 2396 return S; 2397 } 2398 2399 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2400 uint64_t Address, const void *Decoder) { 2401 DecodeStatus S = MCDisassembler::Success; 2402 2403 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2404 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2405 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2406 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2407 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2408 2409 if (pred == 0xF) 2410 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2411 2412 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2413 return MCDisassembler::Fail; 2414 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2415 return MCDisassembler::Fail; 2416 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2417 return MCDisassembler::Fail; 2418 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2419 return MCDisassembler::Fail; 2420 2421 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2422 return MCDisassembler::Fail; 2423 2424 return S; 2425 } 2426 2427 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2428 uint64_t Address, const void *Decoder) { 2429 DecodeStatus S = MCDisassembler::Success; 2430 2431 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2432 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2433 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2434 2435 if (Pred == 0xF) 2436 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2437 2438 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2439 return MCDisassembler::Fail; 2440 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2441 return MCDisassembler::Fail; 2442 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2443 return MCDisassembler::Fail; 2444 2445 return S; 2446 } 2447 2448 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2449 uint64_t Address, const void *Decoder) { 2450 DecodeStatus S = MCDisassembler::Success; 2451 2452 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2453 2454 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2455 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2456 2457 if (!FeatureBits[ARM::HasV8_1aOps] || 2458 !FeatureBits[ARM::HasV8Ops]) 2459 return MCDisassembler::Fail; 2460 2461 // Decoder can be called from DecodeTST, which does not check the full 2462 // encoding is valid. 2463 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2464 fieldFromInstruction(Insn, 4,4) != 0) 2465 return MCDisassembler::Fail; 2466 if (fieldFromInstruction(Insn, 10,10) != 0 || 2467 fieldFromInstruction(Insn, 0,4) != 0) 2468 S = MCDisassembler::SoftFail; 2469 2470 Inst.setOpcode(ARM::SETPAN); 2471 Inst.addOperand(MCOperand::createImm(Imm)); 2472 2473 return S; 2474 } 2475 2476 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2477 uint64_t Address, const void *Decoder) { 2478 DecodeStatus S = MCDisassembler::Success; 2479 2480 unsigned add = fieldFromInstruction(Val, 12, 1); 2481 unsigned imm = fieldFromInstruction(Val, 0, 12); 2482 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2483 2484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2485 return MCDisassembler::Fail; 2486 2487 if (!add) imm *= -1; 2488 if (imm == 0 && !add) imm = INT32_MIN; 2489 Inst.addOperand(MCOperand::createImm(imm)); 2490 if (Rn == 15) 2491 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2492 2493 return S; 2494 } 2495 2496 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2497 uint64_t Address, const void *Decoder) { 2498 DecodeStatus S = MCDisassembler::Success; 2499 2500 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2501 // U == 1 to add imm, 0 to subtract it. 2502 unsigned U = fieldFromInstruction(Val, 8, 1); 2503 unsigned imm = fieldFromInstruction(Val, 0, 8); 2504 2505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2506 return MCDisassembler::Fail; 2507 2508 if (U) 2509 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2510 else 2511 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2512 2513 return S; 2514 } 2515 2516 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2517 uint64_t Address, const void *Decoder) { 2518 DecodeStatus S = MCDisassembler::Success; 2519 2520 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2521 // U == 1 to add imm, 0 to subtract it. 2522 unsigned U = fieldFromInstruction(Val, 8, 1); 2523 unsigned imm = fieldFromInstruction(Val, 0, 8); 2524 2525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2526 return MCDisassembler::Fail; 2527 2528 if (U) 2529 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2530 else 2531 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2532 2533 return S; 2534 } 2535 2536 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2537 uint64_t Address, const void *Decoder) { 2538 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2539 } 2540 2541 static DecodeStatus 2542 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2543 uint64_t Address, const void *Decoder) { 2544 DecodeStatus Status = MCDisassembler::Success; 2545 2546 // Note the J1 and J2 values are from the encoded instruction. So here 2547 // change them to I1 and I2 values via as documented: 2548 // I1 = NOT(J1 EOR S); 2549 // I2 = NOT(J2 EOR S); 2550 // and build the imm32 with one trailing zero as documented: 2551 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2552 unsigned S = fieldFromInstruction(Insn, 26, 1); 2553 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2554 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2555 unsigned I1 = !(J1 ^ S); 2556 unsigned I2 = !(J2 ^ S); 2557 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2558 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2559 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2560 int imm32 = SignExtend32<25>(tmp << 1); 2561 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2562 true, 4, Inst, Decoder)) 2563 Inst.addOperand(MCOperand::createImm(imm32)); 2564 2565 return Status; 2566 } 2567 2568 static DecodeStatus 2569 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2570 uint64_t Address, const void *Decoder) { 2571 DecodeStatus S = MCDisassembler::Success; 2572 2573 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2574 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2575 2576 if (pred == 0xF) { 2577 Inst.setOpcode(ARM::BLXi); 2578 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2579 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2580 true, 4, Inst, Decoder)) 2581 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2582 return S; 2583 } 2584 2585 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2586 true, 4, Inst, Decoder)) 2587 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2588 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2589 return MCDisassembler::Fail; 2590 2591 return S; 2592 } 2593 2594 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2595 uint64_t Address, const void *Decoder) { 2596 DecodeStatus S = MCDisassembler::Success; 2597 2598 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2599 unsigned align = fieldFromInstruction(Val, 4, 2); 2600 2601 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2602 return MCDisassembler::Fail; 2603 if (!align) 2604 Inst.addOperand(MCOperand::createImm(0)); 2605 else 2606 Inst.addOperand(MCOperand::createImm(4 << align)); 2607 2608 return S; 2609 } 2610 2611 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2612 uint64_t Address, const void *Decoder) { 2613 DecodeStatus S = MCDisassembler::Success; 2614 2615 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2616 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2617 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2618 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2619 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2620 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2621 2622 // First output register 2623 switch (Inst.getOpcode()) { 2624 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2625 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2626 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2627 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2628 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2629 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2630 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2631 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2632 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2633 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2634 return MCDisassembler::Fail; 2635 break; 2636 case ARM::VLD2b16: 2637 case ARM::VLD2b32: 2638 case ARM::VLD2b8: 2639 case ARM::VLD2b16wb_fixed: 2640 case ARM::VLD2b16wb_register: 2641 case ARM::VLD2b32wb_fixed: 2642 case ARM::VLD2b32wb_register: 2643 case ARM::VLD2b8wb_fixed: 2644 case ARM::VLD2b8wb_register: 2645 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2646 return MCDisassembler::Fail; 2647 break; 2648 default: 2649 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2650 return MCDisassembler::Fail; 2651 } 2652 2653 // Second output register 2654 switch (Inst.getOpcode()) { 2655 case ARM::VLD3d8: 2656 case ARM::VLD3d16: 2657 case ARM::VLD3d32: 2658 case ARM::VLD3d8_UPD: 2659 case ARM::VLD3d16_UPD: 2660 case ARM::VLD3d32_UPD: 2661 case ARM::VLD4d8: 2662 case ARM::VLD4d16: 2663 case ARM::VLD4d32: 2664 case ARM::VLD4d8_UPD: 2665 case ARM::VLD4d16_UPD: 2666 case ARM::VLD4d32_UPD: 2667 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2668 return MCDisassembler::Fail; 2669 break; 2670 case ARM::VLD3q8: 2671 case ARM::VLD3q16: 2672 case ARM::VLD3q32: 2673 case ARM::VLD3q8_UPD: 2674 case ARM::VLD3q16_UPD: 2675 case ARM::VLD3q32_UPD: 2676 case ARM::VLD4q8: 2677 case ARM::VLD4q16: 2678 case ARM::VLD4q32: 2679 case ARM::VLD4q8_UPD: 2680 case ARM::VLD4q16_UPD: 2681 case ARM::VLD4q32_UPD: 2682 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2683 return MCDisassembler::Fail; 2684 break; 2685 default: 2686 break; 2687 } 2688 2689 // Third output register 2690 switch(Inst.getOpcode()) { 2691 case ARM::VLD3d8: 2692 case ARM::VLD3d16: 2693 case ARM::VLD3d32: 2694 case ARM::VLD3d8_UPD: 2695 case ARM::VLD3d16_UPD: 2696 case ARM::VLD3d32_UPD: 2697 case ARM::VLD4d8: 2698 case ARM::VLD4d16: 2699 case ARM::VLD4d32: 2700 case ARM::VLD4d8_UPD: 2701 case ARM::VLD4d16_UPD: 2702 case ARM::VLD4d32_UPD: 2703 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2704 return MCDisassembler::Fail; 2705 break; 2706 case ARM::VLD3q8: 2707 case ARM::VLD3q16: 2708 case ARM::VLD3q32: 2709 case ARM::VLD3q8_UPD: 2710 case ARM::VLD3q16_UPD: 2711 case ARM::VLD3q32_UPD: 2712 case ARM::VLD4q8: 2713 case ARM::VLD4q16: 2714 case ARM::VLD4q32: 2715 case ARM::VLD4q8_UPD: 2716 case ARM::VLD4q16_UPD: 2717 case ARM::VLD4q32_UPD: 2718 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2719 return MCDisassembler::Fail; 2720 break; 2721 default: 2722 break; 2723 } 2724 2725 // Fourth output register 2726 switch (Inst.getOpcode()) { 2727 case ARM::VLD4d8: 2728 case ARM::VLD4d16: 2729 case ARM::VLD4d32: 2730 case ARM::VLD4d8_UPD: 2731 case ARM::VLD4d16_UPD: 2732 case ARM::VLD4d32_UPD: 2733 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2734 return MCDisassembler::Fail; 2735 break; 2736 case ARM::VLD4q8: 2737 case ARM::VLD4q16: 2738 case ARM::VLD4q32: 2739 case ARM::VLD4q8_UPD: 2740 case ARM::VLD4q16_UPD: 2741 case ARM::VLD4q32_UPD: 2742 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2743 return MCDisassembler::Fail; 2744 break; 2745 default: 2746 break; 2747 } 2748 2749 // Writeback operand 2750 switch (Inst.getOpcode()) { 2751 case ARM::VLD1d8wb_fixed: 2752 case ARM::VLD1d16wb_fixed: 2753 case ARM::VLD1d32wb_fixed: 2754 case ARM::VLD1d64wb_fixed: 2755 case ARM::VLD1d8wb_register: 2756 case ARM::VLD1d16wb_register: 2757 case ARM::VLD1d32wb_register: 2758 case ARM::VLD1d64wb_register: 2759 case ARM::VLD1q8wb_fixed: 2760 case ARM::VLD1q16wb_fixed: 2761 case ARM::VLD1q32wb_fixed: 2762 case ARM::VLD1q64wb_fixed: 2763 case ARM::VLD1q8wb_register: 2764 case ARM::VLD1q16wb_register: 2765 case ARM::VLD1q32wb_register: 2766 case ARM::VLD1q64wb_register: 2767 case ARM::VLD1d8Twb_fixed: 2768 case ARM::VLD1d8Twb_register: 2769 case ARM::VLD1d16Twb_fixed: 2770 case ARM::VLD1d16Twb_register: 2771 case ARM::VLD1d32Twb_fixed: 2772 case ARM::VLD1d32Twb_register: 2773 case ARM::VLD1d64Twb_fixed: 2774 case ARM::VLD1d64Twb_register: 2775 case ARM::VLD1d8Qwb_fixed: 2776 case ARM::VLD1d8Qwb_register: 2777 case ARM::VLD1d16Qwb_fixed: 2778 case ARM::VLD1d16Qwb_register: 2779 case ARM::VLD1d32Qwb_fixed: 2780 case ARM::VLD1d32Qwb_register: 2781 case ARM::VLD1d64Qwb_fixed: 2782 case ARM::VLD1d64Qwb_register: 2783 case ARM::VLD2d8wb_fixed: 2784 case ARM::VLD2d16wb_fixed: 2785 case ARM::VLD2d32wb_fixed: 2786 case ARM::VLD2q8wb_fixed: 2787 case ARM::VLD2q16wb_fixed: 2788 case ARM::VLD2q32wb_fixed: 2789 case ARM::VLD2d8wb_register: 2790 case ARM::VLD2d16wb_register: 2791 case ARM::VLD2d32wb_register: 2792 case ARM::VLD2q8wb_register: 2793 case ARM::VLD2q16wb_register: 2794 case ARM::VLD2q32wb_register: 2795 case ARM::VLD2b8wb_fixed: 2796 case ARM::VLD2b16wb_fixed: 2797 case ARM::VLD2b32wb_fixed: 2798 case ARM::VLD2b8wb_register: 2799 case ARM::VLD2b16wb_register: 2800 case ARM::VLD2b32wb_register: 2801 Inst.addOperand(MCOperand::createImm(0)); 2802 break; 2803 case ARM::VLD3d8_UPD: 2804 case ARM::VLD3d16_UPD: 2805 case ARM::VLD3d32_UPD: 2806 case ARM::VLD3q8_UPD: 2807 case ARM::VLD3q16_UPD: 2808 case ARM::VLD3q32_UPD: 2809 case ARM::VLD4d8_UPD: 2810 case ARM::VLD4d16_UPD: 2811 case ARM::VLD4d32_UPD: 2812 case ARM::VLD4q8_UPD: 2813 case ARM::VLD4q16_UPD: 2814 case ARM::VLD4q32_UPD: 2815 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2816 return MCDisassembler::Fail; 2817 break; 2818 default: 2819 break; 2820 } 2821 2822 // AddrMode6 Base (register+alignment) 2823 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2824 return MCDisassembler::Fail; 2825 2826 // AddrMode6 Offset (register) 2827 switch (Inst.getOpcode()) { 2828 default: 2829 // The below have been updated to have explicit am6offset split 2830 // between fixed and register offset. For those instructions not 2831 // yet updated, we need to add an additional reg0 operand for the 2832 // fixed variant. 2833 // 2834 // The fixed offset encodes as Rm == 0xd, so we check for that. 2835 if (Rm == 0xd) { 2836 Inst.addOperand(MCOperand::createReg(0)); 2837 break; 2838 } 2839 // Fall through to handle the register offset variant. 2840 LLVM_FALLTHROUGH; 2841 case ARM::VLD1d8wb_fixed: 2842 case ARM::VLD1d16wb_fixed: 2843 case ARM::VLD1d32wb_fixed: 2844 case ARM::VLD1d64wb_fixed: 2845 case ARM::VLD1d8Twb_fixed: 2846 case ARM::VLD1d16Twb_fixed: 2847 case ARM::VLD1d32Twb_fixed: 2848 case ARM::VLD1d64Twb_fixed: 2849 case ARM::VLD1d8Qwb_fixed: 2850 case ARM::VLD1d16Qwb_fixed: 2851 case ARM::VLD1d32Qwb_fixed: 2852 case ARM::VLD1d64Qwb_fixed: 2853 case ARM::VLD1d8wb_register: 2854 case ARM::VLD1d16wb_register: 2855 case ARM::VLD1d32wb_register: 2856 case ARM::VLD1d64wb_register: 2857 case ARM::VLD1q8wb_fixed: 2858 case ARM::VLD1q16wb_fixed: 2859 case ARM::VLD1q32wb_fixed: 2860 case ARM::VLD1q64wb_fixed: 2861 case ARM::VLD1q8wb_register: 2862 case ARM::VLD1q16wb_register: 2863 case ARM::VLD1q32wb_register: 2864 case ARM::VLD1q64wb_register: 2865 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2866 // variant encodes Rm == 0xf. Anything else is a register offset post- 2867 // increment and we need to add the register operand to the instruction. 2868 if (Rm != 0xD && Rm != 0xF && 2869 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2870 return MCDisassembler::Fail; 2871 break; 2872 case ARM::VLD2d8wb_fixed: 2873 case ARM::VLD2d16wb_fixed: 2874 case ARM::VLD2d32wb_fixed: 2875 case ARM::VLD2b8wb_fixed: 2876 case ARM::VLD2b16wb_fixed: 2877 case ARM::VLD2b32wb_fixed: 2878 case ARM::VLD2q8wb_fixed: 2879 case ARM::VLD2q16wb_fixed: 2880 case ARM::VLD2q32wb_fixed: 2881 break; 2882 } 2883 2884 return S; 2885 } 2886 2887 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2888 uint64_t Address, const void *Decoder) { 2889 unsigned type = fieldFromInstruction(Insn, 8, 4); 2890 unsigned align = fieldFromInstruction(Insn, 4, 2); 2891 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2892 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2893 if (type == 10 && align == 3) return MCDisassembler::Fail; 2894 2895 unsigned load = fieldFromInstruction(Insn, 21, 1); 2896 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2897 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2898 } 2899 2900 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2901 uint64_t Address, const void *Decoder) { 2902 unsigned size = fieldFromInstruction(Insn, 6, 2); 2903 if (size == 3) return MCDisassembler::Fail; 2904 2905 unsigned type = fieldFromInstruction(Insn, 8, 4); 2906 unsigned align = fieldFromInstruction(Insn, 4, 2); 2907 if (type == 8 && align == 3) return MCDisassembler::Fail; 2908 if (type == 9 && align == 3) return MCDisassembler::Fail; 2909 2910 unsigned load = fieldFromInstruction(Insn, 21, 1); 2911 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2912 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2913 } 2914 2915 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2916 uint64_t Address, const void *Decoder) { 2917 unsigned size = fieldFromInstruction(Insn, 6, 2); 2918 if (size == 3) return MCDisassembler::Fail; 2919 2920 unsigned align = fieldFromInstruction(Insn, 4, 2); 2921 if (align & 2) return MCDisassembler::Fail; 2922 2923 unsigned load = fieldFromInstruction(Insn, 21, 1); 2924 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2925 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2926 } 2927 2928 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2929 uint64_t Address, const void *Decoder) { 2930 unsigned size = fieldFromInstruction(Insn, 6, 2); 2931 if (size == 3) return MCDisassembler::Fail; 2932 2933 unsigned load = fieldFromInstruction(Insn, 21, 1); 2934 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2935 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2936 } 2937 2938 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2939 uint64_t Address, const void *Decoder) { 2940 DecodeStatus S = MCDisassembler::Success; 2941 2942 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2943 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2944 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2945 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2946 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2947 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2948 2949 // Writeback Operand 2950 switch (Inst.getOpcode()) { 2951 case ARM::VST1d8wb_fixed: 2952 case ARM::VST1d16wb_fixed: 2953 case ARM::VST1d32wb_fixed: 2954 case ARM::VST1d64wb_fixed: 2955 case ARM::VST1d8wb_register: 2956 case ARM::VST1d16wb_register: 2957 case ARM::VST1d32wb_register: 2958 case ARM::VST1d64wb_register: 2959 case ARM::VST1q8wb_fixed: 2960 case ARM::VST1q16wb_fixed: 2961 case ARM::VST1q32wb_fixed: 2962 case ARM::VST1q64wb_fixed: 2963 case ARM::VST1q8wb_register: 2964 case ARM::VST1q16wb_register: 2965 case ARM::VST1q32wb_register: 2966 case ARM::VST1q64wb_register: 2967 case ARM::VST1d8Twb_fixed: 2968 case ARM::VST1d16Twb_fixed: 2969 case ARM::VST1d32Twb_fixed: 2970 case ARM::VST1d64Twb_fixed: 2971 case ARM::VST1d8Twb_register: 2972 case ARM::VST1d16Twb_register: 2973 case ARM::VST1d32Twb_register: 2974 case ARM::VST1d64Twb_register: 2975 case ARM::VST1d8Qwb_fixed: 2976 case ARM::VST1d16Qwb_fixed: 2977 case ARM::VST1d32Qwb_fixed: 2978 case ARM::VST1d64Qwb_fixed: 2979 case ARM::VST1d8Qwb_register: 2980 case ARM::VST1d16Qwb_register: 2981 case ARM::VST1d32Qwb_register: 2982 case ARM::VST1d64Qwb_register: 2983 case ARM::VST2d8wb_fixed: 2984 case ARM::VST2d16wb_fixed: 2985 case ARM::VST2d32wb_fixed: 2986 case ARM::VST2d8wb_register: 2987 case ARM::VST2d16wb_register: 2988 case ARM::VST2d32wb_register: 2989 case ARM::VST2q8wb_fixed: 2990 case ARM::VST2q16wb_fixed: 2991 case ARM::VST2q32wb_fixed: 2992 case ARM::VST2q8wb_register: 2993 case ARM::VST2q16wb_register: 2994 case ARM::VST2q32wb_register: 2995 case ARM::VST2b8wb_fixed: 2996 case ARM::VST2b16wb_fixed: 2997 case ARM::VST2b32wb_fixed: 2998 case ARM::VST2b8wb_register: 2999 case ARM::VST2b16wb_register: 3000 case ARM::VST2b32wb_register: 3001 if (Rm == 0xF) 3002 return MCDisassembler::Fail; 3003 Inst.addOperand(MCOperand::createImm(0)); 3004 break; 3005 case ARM::VST3d8_UPD: 3006 case ARM::VST3d16_UPD: 3007 case ARM::VST3d32_UPD: 3008 case ARM::VST3q8_UPD: 3009 case ARM::VST3q16_UPD: 3010 case ARM::VST3q32_UPD: 3011 case ARM::VST4d8_UPD: 3012 case ARM::VST4d16_UPD: 3013 case ARM::VST4d32_UPD: 3014 case ARM::VST4q8_UPD: 3015 case ARM::VST4q16_UPD: 3016 case ARM::VST4q32_UPD: 3017 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3018 return MCDisassembler::Fail; 3019 break; 3020 default: 3021 break; 3022 } 3023 3024 // AddrMode6 Base (register+alignment) 3025 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3026 return MCDisassembler::Fail; 3027 3028 // AddrMode6 Offset (register) 3029 switch (Inst.getOpcode()) { 3030 default: 3031 if (Rm == 0xD) 3032 Inst.addOperand(MCOperand::createReg(0)); 3033 else if (Rm != 0xF) { 3034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3035 return MCDisassembler::Fail; 3036 } 3037 break; 3038 case ARM::VST1d8wb_fixed: 3039 case ARM::VST1d16wb_fixed: 3040 case ARM::VST1d32wb_fixed: 3041 case ARM::VST1d64wb_fixed: 3042 case ARM::VST1q8wb_fixed: 3043 case ARM::VST1q16wb_fixed: 3044 case ARM::VST1q32wb_fixed: 3045 case ARM::VST1q64wb_fixed: 3046 case ARM::VST1d8Twb_fixed: 3047 case ARM::VST1d16Twb_fixed: 3048 case ARM::VST1d32Twb_fixed: 3049 case ARM::VST1d64Twb_fixed: 3050 case ARM::VST1d8Qwb_fixed: 3051 case ARM::VST1d16Qwb_fixed: 3052 case ARM::VST1d32Qwb_fixed: 3053 case ARM::VST1d64Qwb_fixed: 3054 case ARM::VST2d8wb_fixed: 3055 case ARM::VST2d16wb_fixed: 3056 case ARM::VST2d32wb_fixed: 3057 case ARM::VST2q8wb_fixed: 3058 case ARM::VST2q16wb_fixed: 3059 case ARM::VST2q32wb_fixed: 3060 case ARM::VST2b8wb_fixed: 3061 case ARM::VST2b16wb_fixed: 3062 case ARM::VST2b32wb_fixed: 3063 break; 3064 } 3065 3066 // First input register 3067 switch (Inst.getOpcode()) { 3068 case ARM::VST1q16: 3069 case ARM::VST1q32: 3070 case ARM::VST1q64: 3071 case ARM::VST1q8: 3072 case ARM::VST1q16wb_fixed: 3073 case ARM::VST1q16wb_register: 3074 case ARM::VST1q32wb_fixed: 3075 case ARM::VST1q32wb_register: 3076 case ARM::VST1q64wb_fixed: 3077 case ARM::VST1q64wb_register: 3078 case ARM::VST1q8wb_fixed: 3079 case ARM::VST1q8wb_register: 3080 case ARM::VST2d16: 3081 case ARM::VST2d32: 3082 case ARM::VST2d8: 3083 case ARM::VST2d16wb_fixed: 3084 case ARM::VST2d16wb_register: 3085 case ARM::VST2d32wb_fixed: 3086 case ARM::VST2d32wb_register: 3087 case ARM::VST2d8wb_fixed: 3088 case ARM::VST2d8wb_register: 3089 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3090 return MCDisassembler::Fail; 3091 break; 3092 case ARM::VST2b16: 3093 case ARM::VST2b32: 3094 case ARM::VST2b8: 3095 case ARM::VST2b16wb_fixed: 3096 case ARM::VST2b16wb_register: 3097 case ARM::VST2b32wb_fixed: 3098 case ARM::VST2b32wb_register: 3099 case ARM::VST2b8wb_fixed: 3100 case ARM::VST2b8wb_register: 3101 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3102 return MCDisassembler::Fail; 3103 break; 3104 default: 3105 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3106 return MCDisassembler::Fail; 3107 } 3108 3109 // Second input register 3110 switch (Inst.getOpcode()) { 3111 case ARM::VST3d8: 3112 case ARM::VST3d16: 3113 case ARM::VST3d32: 3114 case ARM::VST3d8_UPD: 3115 case ARM::VST3d16_UPD: 3116 case ARM::VST3d32_UPD: 3117 case ARM::VST4d8: 3118 case ARM::VST4d16: 3119 case ARM::VST4d32: 3120 case ARM::VST4d8_UPD: 3121 case ARM::VST4d16_UPD: 3122 case ARM::VST4d32_UPD: 3123 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3124 return MCDisassembler::Fail; 3125 break; 3126 case ARM::VST3q8: 3127 case ARM::VST3q16: 3128 case ARM::VST3q32: 3129 case ARM::VST3q8_UPD: 3130 case ARM::VST3q16_UPD: 3131 case ARM::VST3q32_UPD: 3132 case ARM::VST4q8: 3133 case ARM::VST4q16: 3134 case ARM::VST4q32: 3135 case ARM::VST4q8_UPD: 3136 case ARM::VST4q16_UPD: 3137 case ARM::VST4q32_UPD: 3138 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3139 return MCDisassembler::Fail; 3140 break; 3141 default: 3142 break; 3143 } 3144 3145 // Third input register 3146 switch (Inst.getOpcode()) { 3147 case ARM::VST3d8: 3148 case ARM::VST3d16: 3149 case ARM::VST3d32: 3150 case ARM::VST3d8_UPD: 3151 case ARM::VST3d16_UPD: 3152 case ARM::VST3d32_UPD: 3153 case ARM::VST4d8: 3154 case ARM::VST4d16: 3155 case ARM::VST4d32: 3156 case ARM::VST4d8_UPD: 3157 case ARM::VST4d16_UPD: 3158 case ARM::VST4d32_UPD: 3159 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3160 return MCDisassembler::Fail; 3161 break; 3162 case ARM::VST3q8: 3163 case ARM::VST3q16: 3164 case ARM::VST3q32: 3165 case ARM::VST3q8_UPD: 3166 case ARM::VST3q16_UPD: 3167 case ARM::VST3q32_UPD: 3168 case ARM::VST4q8: 3169 case ARM::VST4q16: 3170 case ARM::VST4q32: 3171 case ARM::VST4q8_UPD: 3172 case ARM::VST4q16_UPD: 3173 case ARM::VST4q32_UPD: 3174 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3175 return MCDisassembler::Fail; 3176 break; 3177 default: 3178 break; 3179 } 3180 3181 // Fourth input register 3182 switch (Inst.getOpcode()) { 3183 case ARM::VST4d8: 3184 case ARM::VST4d16: 3185 case ARM::VST4d32: 3186 case ARM::VST4d8_UPD: 3187 case ARM::VST4d16_UPD: 3188 case ARM::VST4d32_UPD: 3189 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3190 return MCDisassembler::Fail; 3191 break; 3192 case ARM::VST4q8: 3193 case ARM::VST4q16: 3194 case ARM::VST4q32: 3195 case ARM::VST4q8_UPD: 3196 case ARM::VST4q16_UPD: 3197 case ARM::VST4q32_UPD: 3198 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3199 return MCDisassembler::Fail; 3200 break; 3201 default: 3202 break; 3203 } 3204 3205 return S; 3206 } 3207 3208 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3209 uint64_t Address, const void *Decoder) { 3210 DecodeStatus S = MCDisassembler::Success; 3211 3212 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3213 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3214 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3215 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3216 unsigned align = fieldFromInstruction(Insn, 4, 1); 3217 unsigned size = fieldFromInstruction(Insn, 6, 2); 3218 3219 if (size == 0 && align == 1) 3220 return MCDisassembler::Fail; 3221 align *= (1 << size); 3222 3223 switch (Inst.getOpcode()) { 3224 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3225 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3226 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3227 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3228 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 break; 3231 default: 3232 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3233 return MCDisassembler::Fail; 3234 break; 3235 } 3236 if (Rm != 0xF) { 3237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3238 return MCDisassembler::Fail; 3239 } 3240 3241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3242 return MCDisassembler::Fail; 3243 Inst.addOperand(MCOperand::createImm(align)); 3244 3245 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3246 // variant encodes Rm == 0xf. Anything else is a register offset post- 3247 // increment and we need to add the register operand to the instruction. 3248 if (Rm != 0xD && Rm != 0xF && 3249 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3250 return MCDisassembler::Fail; 3251 3252 return S; 3253 } 3254 3255 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3256 uint64_t Address, const void *Decoder) { 3257 DecodeStatus S = MCDisassembler::Success; 3258 3259 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3260 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3261 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3262 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3263 unsigned align = fieldFromInstruction(Insn, 4, 1); 3264 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3265 align *= 2*size; 3266 3267 switch (Inst.getOpcode()) { 3268 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3269 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3270 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3271 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3272 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3273 return MCDisassembler::Fail; 3274 break; 3275 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3276 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3277 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3278 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3279 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3280 return MCDisassembler::Fail; 3281 break; 3282 default: 3283 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3284 return MCDisassembler::Fail; 3285 break; 3286 } 3287 3288 if (Rm != 0xF) 3289 Inst.addOperand(MCOperand::createImm(0)); 3290 3291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 Inst.addOperand(MCOperand::createImm(align)); 3294 3295 if (Rm != 0xD && Rm != 0xF) { 3296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3297 return MCDisassembler::Fail; 3298 } 3299 3300 return S; 3301 } 3302 3303 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3304 uint64_t Address, const void *Decoder) { 3305 DecodeStatus S = MCDisassembler::Success; 3306 3307 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3308 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3309 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3310 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3311 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3312 3313 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3314 return MCDisassembler::Fail; 3315 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3316 return MCDisassembler::Fail; 3317 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3318 return MCDisassembler::Fail; 3319 if (Rm != 0xF) { 3320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3321 return MCDisassembler::Fail; 3322 } 3323 3324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3325 return MCDisassembler::Fail; 3326 Inst.addOperand(MCOperand::createImm(0)); 3327 3328 if (Rm == 0xD) 3329 Inst.addOperand(MCOperand::createReg(0)); 3330 else if (Rm != 0xF) { 3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 } 3334 3335 return S; 3336 } 3337 3338 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3339 uint64_t Address, const void *Decoder) { 3340 DecodeStatus S = MCDisassembler::Success; 3341 3342 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3343 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3344 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3345 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3346 unsigned size = fieldFromInstruction(Insn, 6, 2); 3347 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3348 unsigned align = fieldFromInstruction(Insn, 4, 1); 3349 3350 if (size == 0x3) { 3351 if (align == 0) 3352 return MCDisassembler::Fail; 3353 align = 16; 3354 } else { 3355 if (size == 2) { 3356 align *= 8; 3357 } else { 3358 size = 1 << size; 3359 align *= 4*size; 3360 } 3361 } 3362 3363 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3364 return MCDisassembler::Fail; 3365 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3366 return MCDisassembler::Fail; 3367 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3368 return MCDisassembler::Fail; 3369 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3370 return MCDisassembler::Fail; 3371 if (Rm != 0xF) { 3372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3373 return MCDisassembler::Fail; 3374 } 3375 3376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3377 return MCDisassembler::Fail; 3378 Inst.addOperand(MCOperand::createImm(align)); 3379 3380 if (Rm == 0xD) 3381 Inst.addOperand(MCOperand::createReg(0)); 3382 else if (Rm != 0xF) { 3383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3384 return MCDisassembler::Fail; 3385 } 3386 3387 return S; 3388 } 3389 3390 static DecodeStatus 3391 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3392 uint64_t Address, const void *Decoder) { 3393 DecodeStatus S = MCDisassembler::Success; 3394 3395 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3396 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3397 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3398 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3399 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3400 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3401 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3402 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3403 3404 if (Q) { 3405 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3406 return MCDisassembler::Fail; 3407 } else { 3408 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 } 3411 3412 Inst.addOperand(MCOperand::createImm(imm)); 3413 3414 switch (Inst.getOpcode()) { 3415 case ARM::VORRiv4i16: 3416 case ARM::VORRiv2i32: 3417 case ARM::VBICiv4i16: 3418 case ARM::VBICiv2i32: 3419 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3420 return MCDisassembler::Fail; 3421 break; 3422 case ARM::VORRiv8i16: 3423 case ARM::VORRiv4i32: 3424 case ARM::VBICiv8i16: 3425 case ARM::VBICiv4i32: 3426 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3427 return MCDisassembler::Fail; 3428 break; 3429 default: 3430 break; 3431 } 3432 3433 return S; 3434 } 3435 3436 static DecodeStatus 3437 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3438 uint64_t Address, const void *Decoder) { 3439 DecodeStatus S = MCDisassembler::Success; 3440 3441 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3442 fieldFromInstruction(Insn, 13, 3)); 3443 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3444 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3445 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3446 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3447 imm |= cmode << 8; 3448 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3449 3450 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3451 return MCDisassembler::Fail; 3452 3453 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3454 return MCDisassembler::Fail; 3455 3456 Inst.addOperand(MCOperand::createImm(imm)); 3457 3458 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3459 Inst.addOperand(MCOperand::createReg(0)); 3460 Inst.addOperand(MCOperand::createImm(0)); 3461 3462 return S; 3463 } 3464 3465 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3466 uint64_t Address, const void *Decoder) { 3467 DecodeStatus S = MCDisassembler::Success; 3468 3469 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3470 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3471 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3472 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3473 unsigned size = fieldFromInstruction(Insn, 18, 2); 3474 3475 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3476 return MCDisassembler::Fail; 3477 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3478 return MCDisassembler::Fail; 3479 Inst.addOperand(MCOperand::createImm(8 << size)); 3480 3481 return S; 3482 } 3483 3484 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3485 uint64_t Address, const void *Decoder) { 3486 Inst.addOperand(MCOperand::createImm(8 - Val)); 3487 return MCDisassembler::Success; 3488 } 3489 3490 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3491 uint64_t Address, const void *Decoder) { 3492 Inst.addOperand(MCOperand::createImm(16 - Val)); 3493 return MCDisassembler::Success; 3494 } 3495 3496 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3497 uint64_t Address, const void *Decoder) { 3498 Inst.addOperand(MCOperand::createImm(32 - Val)); 3499 return MCDisassembler::Success; 3500 } 3501 3502 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3503 uint64_t Address, const void *Decoder) { 3504 Inst.addOperand(MCOperand::createImm(64 - Val)); 3505 return MCDisassembler::Success; 3506 } 3507 3508 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3509 uint64_t Address, const void *Decoder) { 3510 DecodeStatus S = MCDisassembler::Success; 3511 3512 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3513 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3514 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3515 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3516 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3517 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3518 unsigned op = fieldFromInstruction(Insn, 6, 1); 3519 3520 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3521 return MCDisassembler::Fail; 3522 if (op) { 3523 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3524 return MCDisassembler::Fail; // Writeback 3525 } 3526 3527 switch (Inst.getOpcode()) { 3528 case ARM::VTBL2: 3529 case ARM::VTBX2: 3530 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 break; 3533 default: 3534 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3535 return MCDisassembler::Fail; 3536 } 3537 3538 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3539 return MCDisassembler::Fail; 3540 3541 return S; 3542 } 3543 3544 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3545 uint64_t Address, const void *Decoder) { 3546 DecodeStatus S = MCDisassembler::Success; 3547 3548 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3549 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3550 3551 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3552 return MCDisassembler::Fail; 3553 3554 switch(Inst.getOpcode()) { 3555 default: 3556 return MCDisassembler::Fail; 3557 case ARM::tADR: 3558 break; // tADR does not explicitly represent the PC as an operand. 3559 case ARM::tADDrSPi: 3560 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3561 break; 3562 } 3563 3564 Inst.addOperand(MCOperand::createImm(imm)); 3565 return S; 3566 } 3567 3568 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3569 uint64_t Address, const void *Decoder) { 3570 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3571 true, 2, Inst, Decoder)) 3572 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3573 return MCDisassembler::Success; 3574 } 3575 3576 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3577 uint64_t Address, const void *Decoder) { 3578 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3579 true, 4, Inst, Decoder)) 3580 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3581 return MCDisassembler::Success; 3582 } 3583 3584 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3585 uint64_t Address, const void *Decoder) { 3586 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3587 true, 2, Inst, Decoder)) 3588 Inst.addOperand(MCOperand::createImm(Val << 1)); 3589 return MCDisassembler::Success; 3590 } 3591 3592 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3593 uint64_t Address, const void *Decoder) { 3594 DecodeStatus S = MCDisassembler::Success; 3595 3596 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3597 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3598 3599 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3600 return MCDisassembler::Fail; 3601 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3602 return MCDisassembler::Fail; 3603 3604 return S; 3605 } 3606 3607 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3608 uint64_t Address, const void *Decoder) { 3609 DecodeStatus S = MCDisassembler::Success; 3610 3611 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3612 unsigned imm = fieldFromInstruction(Val, 3, 5); 3613 3614 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3615 return MCDisassembler::Fail; 3616 Inst.addOperand(MCOperand::createImm(imm)); 3617 3618 return S; 3619 } 3620 3621 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3622 uint64_t Address, const void *Decoder) { 3623 unsigned imm = Val << 2; 3624 3625 Inst.addOperand(MCOperand::createImm(imm)); 3626 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3627 3628 return MCDisassembler::Success; 3629 } 3630 3631 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3632 uint64_t Address, const void *Decoder) { 3633 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3634 Inst.addOperand(MCOperand::createImm(Val)); 3635 3636 return MCDisassembler::Success; 3637 } 3638 3639 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3640 uint64_t Address, const void *Decoder) { 3641 DecodeStatus S = MCDisassembler::Success; 3642 3643 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3644 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3645 unsigned imm = fieldFromInstruction(Val, 0, 2); 3646 3647 // Thumb stores cannot use PC as dest register. 3648 switch (Inst.getOpcode()) { 3649 case ARM::t2STRHs: 3650 case ARM::t2STRBs: 3651 case ARM::t2STRs: 3652 if (Rn == 15) 3653 return MCDisassembler::Fail; 3654 break; 3655 default: 3656 break; 3657 } 3658 3659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3660 return MCDisassembler::Fail; 3661 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3662 return MCDisassembler::Fail; 3663 Inst.addOperand(MCOperand::createImm(imm)); 3664 3665 return S; 3666 } 3667 3668 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3669 uint64_t Address, const void *Decoder) { 3670 DecodeStatus S = MCDisassembler::Success; 3671 3672 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3673 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3674 3675 const FeatureBitset &featureBits = 3676 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3677 3678 bool hasMP = featureBits[ARM::FeatureMP]; 3679 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3680 3681 if (Rn == 15) { 3682 switch (Inst.getOpcode()) { 3683 case ARM::t2LDRBs: 3684 Inst.setOpcode(ARM::t2LDRBpci); 3685 break; 3686 case ARM::t2LDRHs: 3687 Inst.setOpcode(ARM::t2LDRHpci); 3688 break; 3689 case ARM::t2LDRSHs: 3690 Inst.setOpcode(ARM::t2LDRSHpci); 3691 break; 3692 case ARM::t2LDRSBs: 3693 Inst.setOpcode(ARM::t2LDRSBpci); 3694 break; 3695 case ARM::t2LDRs: 3696 Inst.setOpcode(ARM::t2LDRpci); 3697 break; 3698 case ARM::t2PLDs: 3699 Inst.setOpcode(ARM::t2PLDpci); 3700 break; 3701 case ARM::t2PLIs: 3702 Inst.setOpcode(ARM::t2PLIpci); 3703 break; 3704 default: 3705 return MCDisassembler::Fail; 3706 } 3707 3708 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3709 } 3710 3711 if (Rt == 15) { 3712 switch (Inst.getOpcode()) { 3713 case ARM::t2LDRSHs: 3714 return MCDisassembler::Fail; 3715 case ARM::t2LDRHs: 3716 Inst.setOpcode(ARM::t2PLDWs); 3717 break; 3718 case ARM::t2LDRSBs: 3719 Inst.setOpcode(ARM::t2PLIs); 3720 break; 3721 default: 3722 break; 3723 } 3724 } 3725 3726 switch (Inst.getOpcode()) { 3727 case ARM::t2PLDs: 3728 break; 3729 case ARM::t2PLIs: 3730 if (!hasV7Ops) 3731 return MCDisassembler::Fail; 3732 break; 3733 case ARM::t2PLDWs: 3734 if (!hasV7Ops || !hasMP) 3735 return MCDisassembler::Fail; 3736 break; 3737 default: 3738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3739 return MCDisassembler::Fail; 3740 } 3741 3742 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3743 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3744 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3745 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3746 return MCDisassembler::Fail; 3747 3748 return S; 3749 } 3750 3751 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3752 uint64_t Address, const void* Decoder) { 3753 DecodeStatus S = MCDisassembler::Success; 3754 3755 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3756 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3757 unsigned U = fieldFromInstruction(Insn, 9, 1); 3758 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3759 imm |= (U << 8); 3760 imm |= (Rn << 9); 3761 unsigned add = fieldFromInstruction(Insn, 9, 1); 3762 3763 const FeatureBitset &featureBits = 3764 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3765 3766 bool hasMP = featureBits[ARM::FeatureMP]; 3767 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3768 3769 if (Rn == 15) { 3770 switch (Inst.getOpcode()) { 3771 case ARM::t2LDRi8: 3772 Inst.setOpcode(ARM::t2LDRpci); 3773 break; 3774 case ARM::t2LDRBi8: 3775 Inst.setOpcode(ARM::t2LDRBpci); 3776 break; 3777 case ARM::t2LDRSBi8: 3778 Inst.setOpcode(ARM::t2LDRSBpci); 3779 break; 3780 case ARM::t2LDRHi8: 3781 Inst.setOpcode(ARM::t2LDRHpci); 3782 break; 3783 case ARM::t2LDRSHi8: 3784 Inst.setOpcode(ARM::t2LDRSHpci); 3785 break; 3786 case ARM::t2PLDi8: 3787 Inst.setOpcode(ARM::t2PLDpci); 3788 break; 3789 case ARM::t2PLIi8: 3790 Inst.setOpcode(ARM::t2PLIpci); 3791 break; 3792 default: 3793 return MCDisassembler::Fail; 3794 } 3795 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3796 } 3797 3798 if (Rt == 15) { 3799 switch (Inst.getOpcode()) { 3800 case ARM::t2LDRSHi8: 3801 return MCDisassembler::Fail; 3802 case ARM::t2LDRHi8: 3803 if (!add) 3804 Inst.setOpcode(ARM::t2PLDWi8); 3805 break; 3806 case ARM::t2LDRSBi8: 3807 Inst.setOpcode(ARM::t2PLIi8); 3808 break; 3809 default: 3810 break; 3811 } 3812 } 3813 3814 switch (Inst.getOpcode()) { 3815 case ARM::t2PLDi8: 3816 break; 3817 case ARM::t2PLIi8: 3818 if (!hasV7Ops) 3819 return MCDisassembler::Fail; 3820 break; 3821 case ARM::t2PLDWi8: 3822 if (!hasV7Ops || !hasMP) 3823 return MCDisassembler::Fail; 3824 break; 3825 default: 3826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3827 return MCDisassembler::Fail; 3828 } 3829 3830 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3831 return MCDisassembler::Fail; 3832 return S; 3833 } 3834 3835 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3836 uint64_t Address, const void* Decoder) { 3837 DecodeStatus S = MCDisassembler::Success; 3838 3839 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3840 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3841 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3842 imm |= (Rn << 13); 3843 3844 const FeatureBitset &featureBits = 3845 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3846 3847 bool hasMP = featureBits[ARM::FeatureMP]; 3848 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3849 3850 if (Rn == 15) { 3851 switch (Inst.getOpcode()) { 3852 case ARM::t2LDRi12: 3853 Inst.setOpcode(ARM::t2LDRpci); 3854 break; 3855 case ARM::t2LDRHi12: 3856 Inst.setOpcode(ARM::t2LDRHpci); 3857 break; 3858 case ARM::t2LDRSHi12: 3859 Inst.setOpcode(ARM::t2LDRSHpci); 3860 break; 3861 case ARM::t2LDRBi12: 3862 Inst.setOpcode(ARM::t2LDRBpci); 3863 break; 3864 case ARM::t2LDRSBi12: 3865 Inst.setOpcode(ARM::t2LDRSBpci); 3866 break; 3867 case ARM::t2PLDi12: 3868 Inst.setOpcode(ARM::t2PLDpci); 3869 break; 3870 case ARM::t2PLIi12: 3871 Inst.setOpcode(ARM::t2PLIpci); 3872 break; 3873 default: 3874 return MCDisassembler::Fail; 3875 } 3876 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3877 } 3878 3879 if (Rt == 15) { 3880 switch (Inst.getOpcode()) { 3881 case ARM::t2LDRSHi12: 3882 return MCDisassembler::Fail; 3883 case ARM::t2LDRHi12: 3884 Inst.setOpcode(ARM::t2PLDWi12); 3885 break; 3886 case ARM::t2LDRSBi12: 3887 Inst.setOpcode(ARM::t2PLIi12); 3888 break; 3889 default: 3890 break; 3891 } 3892 } 3893 3894 switch (Inst.getOpcode()) { 3895 case ARM::t2PLDi12: 3896 break; 3897 case ARM::t2PLIi12: 3898 if (!hasV7Ops) 3899 return MCDisassembler::Fail; 3900 break; 3901 case ARM::t2PLDWi12: 3902 if (!hasV7Ops || !hasMP) 3903 return MCDisassembler::Fail; 3904 break; 3905 default: 3906 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3907 return MCDisassembler::Fail; 3908 } 3909 3910 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3911 return MCDisassembler::Fail; 3912 return S; 3913 } 3914 3915 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3916 uint64_t Address, const void* Decoder) { 3917 DecodeStatus S = MCDisassembler::Success; 3918 3919 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3920 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3921 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3922 imm |= (Rn << 9); 3923 3924 if (Rn == 15) { 3925 switch (Inst.getOpcode()) { 3926 case ARM::t2LDRT: 3927 Inst.setOpcode(ARM::t2LDRpci); 3928 break; 3929 case ARM::t2LDRBT: 3930 Inst.setOpcode(ARM::t2LDRBpci); 3931 break; 3932 case ARM::t2LDRHT: 3933 Inst.setOpcode(ARM::t2LDRHpci); 3934 break; 3935 case ARM::t2LDRSBT: 3936 Inst.setOpcode(ARM::t2LDRSBpci); 3937 break; 3938 case ARM::t2LDRSHT: 3939 Inst.setOpcode(ARM::t2LDRSHpci); 3940 break; 3941 default: 3942 return MCDisassembler::Fail; 3943 } 3944 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3945 } 3946 3947 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3948 return MCDisassembler::Fail; 3949 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3950 return MCDisassembler::Fail; 3951 return S; 3952 } 3953 3954 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3955 uint64_t Address, const void* Decoder) { 3956 DecodeStatus S = MCDisassembler::Success; 3957 3958 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3959 unsigned U = fieldFromInstruction(Insn, 23, 1); 3960 int imm = fieldFromInstruction(Insn, 0, 12); 3961 3962 const FeatureBitset &featureBits = 3963 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3964 3965 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3966 3967 if (Rt == 15) { 3968 switch (Inst.getOpcode()) { 3969 case ARM::t2LDRBpci: 3970 case ARM::t2LDRHpci: 3971 Inst.setOpcode(ARM::t2PLDpci); 3972 break; 3973 case ARM::t2LDRSBpci: 3974 Inst.setOpcode(ARM::t2PLIpci); 3975 break; 3976 case ARM::t2LDRSHpci: 3977 return MCDisassembler::Fail; 3978 default: 3979 break; 3980 } 3981 } 3982 3983 switch(Inst.getOpcode()) { 3984 case ARM::t2PLDpci: 3985 break; 3986 case ARM::t2PLIpci: 3987 if (!hasV7Ops) 3988 return MCDisassembler::Fail; 3989 break; 3990 default: 3991 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3992 return MCDisassembler::Fail; 3993 } 3994 3995 if (!U) { 3996 // Special case for #-0. 3997 if (imm == 0) 3998 imm = INT32_MIN; 3999 else 4000 imm = -imm; 4001 } 4002 Inst.addOperand(MCOperand::createImm(imm)); 4003 4004 return S; 4005 } 4006 4007 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4008 uint64_t Address, const void *Decoder) { 4009 if (Val == 0) 4010 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4011 else { 4012 int imm = Val & 0xFF; 4013 4014 if (!(Val & 0x100)) imm *= -1; 4015 Inst.addOperand(MCOperand::createImm(imm * 4)); 4016 } 4017 4018 return MCDisassembler::Success; 4019 } 4020 4021 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4022 const void *Decoder) { 4023 if (Val == 0) 4024 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4025 else { 4026 int imm = Val & 0x7F; 4027 4028 if (!(Val & 0x80)) 4029 imm *= -1; 4030 Inst.addOperand(MCOperand::createImm(imm * 4)); 4031 } 4032 4033 return MCDisassembler::Success; 4034 } 4035 4036 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4037 uint64_t Address, const void *Decoder) { 4038 DecodeStatus S = MCDisassembler::Success; 4039 4040 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4041 unsigned imm = fieldFromInstruction(Val, 0, 9); 4042 4043 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4044 return MCDisassembler::Fail; 4045 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4046 return MCDisassembler::Fail; 4047 4048 return S; 4049 } 4050 4051 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4052 uint64_t Address, 4053 const void *Decoder) { 4054 DecodeStatus S = MCDisassembler::Success; 4055 4056 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4057 unsigned imm = fieldFromInstruction(Val, 0, 8); 4058 4059 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4060 return MCDisassembler::Fail; 4061 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4062 return MCDisassembler::Fail; 4063 4064 return S; 4065 } 4066 4067 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4068 uint64_t Address, const void *Decoder) { 4069 DecodeStatus S = MCDisassembler::Success; 4070 4071 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4072 unsigned imm = fieldFromInstruction(Val, 0, 8); 4073 4074 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4075 return MCDisassembler::Fail; 4076 4077 Inst.addOperand(MCOperand::createImm(imm)); 4078 4079 return S; 4080 } 4081 4082 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4083 uint64_t Address, const void *Decoder) { 4084 int imm = Val & 0xFF; 4085 if (Val == 0) 4086 imm = INT32_MIN; 4087 else if (!(Val & 0x100)) 4088 imm *= -1; 4089 Inst.addOperand(MCOperand::createImm(imm)); 4090 4091 return MCDisassembler::Success; 4092 } 4093 4094 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4095 uint64_t Address, const void *Decoder) { 4096 DecodeStatus S = MCDisassembler::Success; 4097 4098 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4099 unsigned imm = fieldFromInstruction(Val, 0, 9); 4100 4101 // Thumb stores cannot use PC as dest register. 4102 switch (Inst.getOpcode()) { 4103 case ARM::t2STRT: 4104 case ARM::t2STRBT: 4105 case ARM::t2STRHT: 4106 case ARM::t2STRi8: 4107 case ARM::t2STRHi8: 4108 case ARM::t2STRBi8: 4109 if (Rn == 15) 4110 return MCDisassembler::Fail; 4111 break; 4112 default: 4113 break; 4114 } 4115 4116 // Some instructions always use an additive offset. 4117 switch (Inst.getOpcode()) { 4118 case ARM::t2LDRT: 4119 case ARM::t2LDRBT: 4120 case ARM::t2LDRHT: 4121 case ARM::t2LDRSBT: 4122 case ARM::t2LDRSHT: 4123 case ARM::t2STRT: 4124 case ARM::t2STRBT: 4125 case ARM::t2STRHT: 4126 imm |= 0x100; 4127 break; 4128 default: 4129 break; 4130 } 4131 4132 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4133 return MCDisassembler::Fail; 4134 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4135 return MCDisassembler::Fail; 4136 4137 return S; 4138 } 4139 4140 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4141 uint64_t Address, const void *Decoder) { 4142 DecodeStatus S = MCDisassembler::Success; 4143 4144 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4145 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4146 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4147 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4148 addr |= Rn << 9; 4149 unsigned load = fieldFromInstruction(Insn, 20, 1); 4150 4151 if (Rn == 15) { 4152 switch (Inst.getOpcode()) { 4153 case ARM::t2LDR_PRE: 4154 case ARM::t2LDR_POST: 4155 Inst.setOpcode(ARM::t2LDRpci); 4156 break; 4157 case ARM::t2LDRB_PRE: 4158 case ARM::t2LDRB_POST: 4159 Inst.setOpcode(ARM::t2LDRBpci); 4160 break; 4161 case ARM::t2LDRH_PRE: 4162 case ARM::t2LDRH_POST: 4163 Inst.setOpcode(ARM::t2LDRHpci); 4164 break; 4165 case ARM::t2LDRSB_PRE: 4166 case ARM::t2LDRSB_POST: 4167 if (Rt == 15) 4168 Inst.setOpcode(ARM::t2PLIpci); 4169 else 4170 Inst.setOpcode(ARM::t2LDRSBpci); 4171 break; 4172 case ARM::t2LDRSH_PRE: 4173 case ARM::t2LDRSH_POST: 4174 Inst.setOpcode(ARM::t2LDRSHpci); 4175 break; 4176 default: 4177 return MCDisassembler::Fail; 4178 } 4179 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4180 } 4181 4182 if (!load) { 4183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4184 return MCDisassembler::Fail; 4185 } 4186 4187 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4188 return MCDisassembler::Fail; 4189 4190 if (load) { 4191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4192 return MCDisassembler::Fail; 4193 } 4194 4195 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4196 return MCDisassembler::Fail; 4197 4198 return S; 4199 } 4200 4201 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4202 uint64_t Address, const void *Decoder) { 4203 DecodeStatus S = MCDisassembler::Success; 4204 4205 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4206 unsigned imm = fieldFromInstruction(Val, 0, 12); 4207 4208 // Thumb stores cannot use PC as dest register. 4209 switch (Inst.getOpcode()) { 4210 case ARM::t2STRi12: 4211 case ARM::t2STRBi12: 4212 case ARM::t2STRHi12: 4213 if (Rn == 15) 4214 return MCDisassembler::Fail; 4215 break; 4216 default: 4217 break; 4218 } 4219 4220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4221 return MCDisassembler::Fail; 4222 Inst.addOperand(MCOperand::createImm(imm)); 4223 4224 return S; 4225 } 4226 4227 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4228 uint64_t Address, const void *Decoder) { 4229 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4230 4231 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4232 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4233 Inst.addOperand(MCOperand::createImm(imm)); 4234 4235 return MCDisassembler::Success; 4236 } 4237 4238 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4239 uint64_t Address, const void *Decoder) { 4240 DecodeStatus S = MCDisassembler::Success; 4241 4242 if (Inst.getOpcode() == ARM::tADDrSP) { 4243 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4244 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4245 4246 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4247 return MCDisassembler::Fail; 4248 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4250 return MCDisassembler::Fail; 4251 } else if (Inst.getOpcode() == ARM::tADDspr) { 4252 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4253 4254 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4255 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4257 return MCDisassembler::Fail; 4258 } 4259 4260 return S; 4261 } 4262 4263 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4264 uint64_t Address, const void *Decoder) { 4265 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4266 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4267 4268 Inst.addOperand(MCOperand::createImm(imod)); 4269 Inst.addOperand(MCOperand::createImm(flags)); 4270 4271 return MCDisassembler::Success; 4272 } 4273 4274 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4275 uint64_t Address, const void *Decoder) { 4276 DecodeStatus S = MCDisassembler::Success; 4277 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4278 unsigned add = fieldFromInstruction(Insn, 4, 1); 4279 4280 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4281 return MCDisassembler::Fail; 4282 Inst.addOperand(MCOperand::createImm(add)); 4283 4284 return S; 4285 } 4286 4287 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4288 uint64_t Address, const void *Decoder) { 4289 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4290 // Note only one trailing zero not two. Also the J1 and J2 values are from 4291 // the encoded instruction. So here change to I1 and I2 values via: 4292 // I1 = NOT(J1 EOR S); 4293 // I2 = NOT(J2 EOR S); 4294 // and build the imm32 with two trailing zeros as documented: 4295 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4296 unsigned S = (Val >> 23) & 1; 4297 unsigned J1 = (Val >> 22) & 1; 4298 unsigned J2 = (Val >> 21) & 1; 4299 unsigned I1 = !(J1 ^ S); 4300 unsigned I2 = !(J2 ^ S); 4301 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4302 int imm32 = SignExtend32<25>(tmp << 1); 4303 4304 if (!tryAddingSymbolicOperand(Address, 4305 (Address & ~2u) + imm32 + 4, 4306 true, 4, Inst, Decoder)) 4307 Inst.addOperand(MCOperand::createImm(imm32)); 4308 return MCDisassembler::Success; 4309 } 4310 4311 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4312 uint64_t Address, const void *Decoder) { 4313 if (Val == 0xA || Val == 0xB) 4314 return MCDisassembler::Fail; 4315 4316 const FeatureBitset &featureBits = 4317 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4318 4319 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4320 return MCDisassembler::Fail; 4321 4322 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should 4323 // decode as VFP/MVE instructions. 4324 if (featureBits[ARM::HasV8_1MMainlineOps] && 4325 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || 4326 (Val & 0xE) == 0xE)) 4327 return MCDisassembler::Fail; 4328 4329 Inst.addOperand(MCOperand::createImm(Val)); 4330 return MCDisassembler::Success; 4331 } 4332 4333 static DecodeStatus 4334 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4335 uint64_t Address, const void *Decoder) { 4336 DecodeStatus S = MCDisassembler::Success; 4337 4338 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4339 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4340 4341 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4345 return MCDisassembler::Fail; 4346 return S; 4347 } 4348 4349 static DecodeStatus 4350 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4351 uint64_t Address, const void *Decoder) { 4352 DecodeStatus S = MCDisassembler::Success; 4353 4354 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4355 if (pred == 0xE || pred == 0xF) { 4356 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4357 switch (opc) { 4358 default: 4359 return MCDisassembler::Fail; 4360 case 0xf3bf8f4: 4361 Inst.setOpcode(ARM::t2DSB); 4362 break; 4363 case 0xf3bf8f5: 4364 Inst.setOpcode(ARM::t2DMB); 4365 break; 4366 case 0xf3bf8f6: 4367 Inst.setOpcode(ARM::t2ISB); 4368 break; 4369 } 4370 4371 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4372 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4373 } 4374 4375 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4376 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4377 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4378 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4379 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4380 4381 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4382 return MCDisassembler::Fail; 4383 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4384 return MCDisassembler::Fail; 4385 4386 return S; 4387 } 4388 4389 // Decode a shifted immediate operand. These basically consist 4390 // of an 8-bit value, and a 4-bit directive that specifies either 4391 // a splat operation or a rotation. 4392 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4393 uint64_t Address, const void *Decoder) { 4394 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4395 if (ctrl == 0) { 4396 unsigned byte = fieldFromInstruction(Val, 8, 2); 4397 unsigned imm = fieldFromInstruction(Val, 0, 8); 4398 switch (byte) { 4399 case 0: 4400 Inst.addOperand(MCOperand::createImm(imm)); 4401 break; 4402 case 1: 4403 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4404 break; 4405 case 2: 4406 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4407 break; 4408 case 3: 4409 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4410 (imm << 8) | imm)); 4411 break; 4412 } 4413 } else { 4414 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4415 unsigned rot = fieldFromInstruction(Val, 7, 5); 4416 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4417 Inst.addOperand(MCOperand::createImm(imm)); 4418 } 4419 4420 return MCDisassembler::Success; 4421 } 4422 4423 static DecodeStatus 4424 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4425 uint64_t Address, const void *Decoder) { 4426 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4427 true, 2, Inst, Decoder)) 4428 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4429 return MCDisassembler::Success; 4430 } 4431 4432 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4433 uint64_t Address, 4434 const void *Decoder) { 4435 // Val is passed in as S:J1:J2:imm10:imm11 4436 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4437 // the encoded instruction. So here change to I1 and I2 values via: 4438 // I1 = NOT(J1 EOR S); 4439 // I2 = NOT(J2 EOR S); 4440 // and build the imm32 with one trailing zero as documented: 4441 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4442 unsigned S = (Val >> 23) & 1; 4443 unsigned J1 = (Val >> 22) & 1; 4444 unsigned J2 = (Val >> 21) & 1; 4445 unsigned I1 = !(J1 ^ S); 4446 unsigned I2 = !(J2 ^ S); 4447 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4448 int imm32 = SignExtend32<25>(tmp << 1); 4449 4450 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4451 true, 4, Inst, Decoder)) 4452 Inst.addOperand(MCOperand::createImm(imm32)); 4453 return MCDisassembler::Success; 4454 } 4455 4456 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4457 uint64_t Address, const void *Decoder) { 4458 if (Val & ~0xf) 4459 return MCDisassembler::Fail; 4460 4461 Inst.addOperand(MCOperand::createImm(Val)); 4462 return MCDisassembler::Success; 4463 } 4464 4465 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4466 uint64_t Address, const void *Decoder) { 4467 if (Val & ~0xf) 4468 return MCDisassembler::Fail; 4469 4470 Inst.addOperand(MCOperand::createImm(Val)); 4471 return MCDisassembler::Success; 4472 } 4473 4474 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4475 uint64_t Address, const void *Decoder) { 4476 DecodeStatus S = MCDisassembler::Success; 4477 const FeatureBitset &FeatureBits = 4478 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4479 4480 if (FeatureBits[ARM::FeatureMClass]) { 4481 unsigned ValLow = Val & 0xff; 4482 4483 // Validate the SYSm value first. 4484 switch (ValLow) { 4485 case 0: // apsr 4486 case 1: // iapsr 4487 case 2: // eapsr 4488 case 3: // xpsr 4489 case 5: // ipsr 4490 case 6: // epsr 4491 case 7: // iepsr 4492 case 8: // msp 4493 case 9: // psp 4494 case 16: // primask 4495 case 20: // control 4496 break; 4497 case 17: // basepri 4498 case 18: // basepri_max 4499 case 19: // faultmask 4500 if (!(FeatureBits[ARM::HasV7Ops])) 4501 // Values basepri, basepri_max and faultmask are only valid for v7m. 4502 return MCDisassembler::Fail; 4503 break; 4504 case 0x8a: // msplim_ns 4505 case 0x8b: // psplim_ns 4506 case 0x91: // basepri_ns 4507 case 0x93: // faultmask_ns 4508 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4509 return MCDisassembler::Fail; 4510 LLVM_FALLTHROUGH; 4511 case 10: // msplim 4512 case 11: // psplim 4513 case 0x88: // msp_ns 4514 case 0x89: // psp_ns 4515 case 0x90: // primask_ns 4516 case 0x94: // control_ns 4517 case 0x98: // sp_ns 4518 if (!(FeatureBits[ARM::Feature8MSecExt])) 4519 return MCDisassembler::Fail; 4520 break; 4521 default: 4522 // Architecturally defined as unpredictable 4523 S = MCDisassembler::SoftFail; 4524 break; 4525 } 4526 4527 if (Inst.getOpcode() == ARM::t2MSR_M) { 4528 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4529 if (!(FeatureBits[ARM::HasV7Ops])) { 4530 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4531 // unpredictable. 4532 if (Mask != 2) 4533 S = MCDisassembler::SoftFail; 4534 } 4535 else { 4536 // The ARMv7-M architecture stores an additional 2-bit mask value in 4537 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4538 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4539 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4540 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4541 // only if the processor includes the DSP extension. 4542 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4543 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4544 S = MCDisassembler::SoftFail; 4545 } 4546 } 4547 } else { 4548 // A/R class 4549 if (Val == 0) 4550 return MCDisassembler::Fail; 4551 } 4552 Inst.addOperand(MCOperand::createImm(Val)); 4553 return S; 4554 } 4555 4556 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4557 uint64_t Address, const void *Decoder) { 4558 unsigned R = fieldFromInstruction(Val, 5, 1); 4559 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4560 4561 // The table of encodings for these banked registers comes from B9.2.3 of the 4562 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4563 // neater. So by fiat, these values are UNPREDICTABLE: 4564 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4565 return MCDisassembler::Fail; 4566 4567 Inst.addOperand(MCOperand::createImm(Val)); 4568 return MCDisassembler::Success; 4569 } 4570 4571 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4572 uint64_t Address, const void *Decoder) { 4573 DecodeStatus S = MCDisassembler::Success; 4574 4575 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4576 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4577 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4578 4579 if (Rn == 0xF) 4580 S = MCDisassembler::SoftFail; 4581 4582 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4583 return MCDisassembler::Fail; 4584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4585 return MCDisassembler::Fail; 4586 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4587 return MCDisassembler::Fail; 4588 4589 return S; 4590 } 4591 4592 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4593 uint64_t Address, 4594 const void *Decoder) { 4595 DecodeStatus S = MCDisassembler::Success; 4596 4597 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4598 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4599 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4600 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4601 4602 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4603 return MCDisassembler::Fail; 4604 4605 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4606 S = MCDisassembler::SoftFail; 4607 4608 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4609 return MCDisassembler::Fail; 4610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4611 return MCDisassembler::Fail; 4612 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4613 return MCDisassembler::Fail; 4614 4615 return S; 4616 } 4617 4618 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4619 uint64_t Address, const void *Decoder) { 4620 DecodeStatus S = MCDisassembler::Success; 4621 4622 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4623 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4624 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4625 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4626 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4627 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4628 4629 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4630 4631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4632 return MCDisassembler::Fail; 4633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4634 return MCDisassembler::Fail; 4635 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4636 return MCDisassembler::Fail; 4637 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4638 return MCDisassembler::Fail; 4639 4640 return S; 4641 } 4642 4643 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4644 uint64_t Address, const void *Decoder) { 4645 DecodeStatus S = MCDisassembler::Success; 4646 4647 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4648 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4649 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4650 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4651 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4652 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4653 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4654 4655 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4656 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4657 4658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4659 return MCDisassembler::Fail; 4660 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4661 return MCDisassembler::Fail; 4662 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4663 return MCDisassembler::Fail; 4664 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4665 return MCDisassembler::Fail; 4666 4667 return S; 4668 } 4669 4670 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4671 uint64_t Address, const void *Decoder) { 4672 DecodeStatus S = MCDisassembler::Success; 4673 4674 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4675 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4676 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4677 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4678 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4679 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4680 4681 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4682 4683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4684 return MCDisassembler::Fail; 4685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4686 return MCDisassembler::Fail; 4687 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4688 return MCDisassembler::Fail; 4689 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4690 return MCDisassembler::Fail; 4691 4692 return S; 4693 } 4694 4695 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4696 uint64_t Address, const void *Decoder) { 4697 DecodeStatus S = MCDisassembler::Success; 4698 4699 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4700 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4701 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4702 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4703 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4704 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4705 4706 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4707 4708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4709 return MCDisassembler::Fail; 4710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4711 return MCDisassembler::Fail; 4712 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4713 return MCDisassembler::Fail; 4714 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4715 return MCDisassembler::Fail; 4716 4717 return S; 4718 } 4719 4720 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4721 uint64_t Address, const void *Decoder) { 4722 DecodeStatus S = MCDisassembler::Success; 4723 4724 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4725 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4726 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4727 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4728 unsigned size = fieldFromInstruction(Insn, 10, 2); 4729 4730 unsigned align = 0; 4731 unsigned index = 0; 4732 switch (size) { 4733 default: 4734 return MCDisassembler::Fail; 4735 case 0: 4736 if (fieldFromInstruction(Insn, 4, 1)) 4737 return MCDisassembler::Fail; // UNDEFINED 4738 index = fieldFromInstruction(Insn, 5, 3); 4739 break; 4740 case 1: 4741 if (fieldFromInstruction(Insn, 5, 1)) 4742 return MCDisassembler::Fail; // UNDEFINED 4743 index = fieldFromInstruction(Insn, 6, 2); 4744 if (fieldFromInstruction(Insn, 4, 1)) 4745 align = 2; 4746 break; 4747 case 2: 4748 if (fieldFromInstruction(Insn, 6, 1)) 4749 return MCDisassembler::Fail; // UNDEFINED 4750 index = fieldFromInstruction(Insn, 7, 1); 4751 4752 switch (fieldFromInstruction(Insn, 4, 2)) { 4753 case 0 : 4754 align = 0; break; 4755 case 3: 4756 align = 4; break; 4757 default: 4758 return MCDisassembler::Fail; 4759 } 4760 break; 4761 } 4762 4763 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4764 return MCDisassembler::Fail; 4765 if (Rm != 0xF) { // Writeback 4766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4767 return MCDisassembler::Fail; 4768 } 4769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4770 return MCDisassembler::Fail; 4771 Inst.addOperand(MCOperand::createImm(align)); 4772 if (Rm != 0xF) { 4773 if (Rm != 0xD) { 4774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4775 return MCDisassembler::Fail; 4776 } else 4777 Inst.addOperand(MCOperand::createReg(0)); 4778 } 4779 4780 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4781 return MCDisassembler::Fail; 4782 Inst.addOperand(MCOperand::createImm(index)); 4783 4784 return S; 4785 } 4786 4787 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4788 uint64_t Address, const void *Decoder) { 4789 DecodeStatus S = MCDisassembler::Success; 4790 4791 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4792 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4793 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4794 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4795 unsigned size = fieldFromInstruction(Insn, 10, 2); 4796 4797 unsigned align = 0; 4798 unsigned index = 0; 4799 switch (size) { 4800 default: 4801 return MCDisassembler::Fail; 4802 case 0: 4803 if (fieldFromInstruction(Insn, 4, 1)) 4804 return MCDisassembler::Fail; // UNDEFINED 4805 index = fieldFromInstruction(Insn, 5, 3); 4806 break; 4807 case 1: 4808 if (fieldFromInstruction(Insn, 5, 1)) 4809 return MCDisassembler::Fail; // UNDEFINED 4810 index = fieldFromInstruction(Insn, 6, 2); 4811 if (fieldFromInstruction(Insn, 4, 1)) 4812 align = 2; 4813 break; 4814 case 2: 4815 if (fieldFromInstruction(Insn, 6, 1)) 4816 return MCDisassembler::Fail; // UNDEFINED 4817 index = fieldFromInstruction(Insn, 7, 1); 4818 4819 switch (fieldFromInstruction(Insn, 4, 2)) { 4820 case 0: 4821 align = 0; break; 4822 case 3: 4823 align = 4; break; 4824 default: 4825 return MCDisassembler::Fail; 4826 } 4827 break; 4828 } 4829 4830 if (Rm != 0xF) { // Writeback 4831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4832 return MCDisassembler::Fail; 4833 } 4834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4835 return MCDisassembler::Fail; 4836 Inst.addOperand(MCOperand::createImm(align)); 4837 if (Rm != 0xF) { 4838 if (Rm != 0xD) { 4839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4840 return MCDisassembler::Fail; 4841 } else 4842 Inst.addOperand(MCOperand::createReg(0)); 4843 } 4844 4845 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4846 return MCDisassembler::Fail; 4847 Inst.addOperand(MCOperand::createImm(index)); 4848 4849 return S; 4850 } 4851 4852 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4853 uint64_t Address, const void *Decoder) { 4854 DecodeStatus S = MCDisassembler::Success; 4855 4856 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4857 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4858 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4859 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4860 unsigned size = fieldFromInstruction(Insn, 10, 2); 4861 4862 unsigned align = 0; 4863 unsigned index = 0; 4864 unsigned inc = 1; 4865 switch (size) { 4866 default: 4867 return MCDisassembler::Fail; 4868 case 0: 4869 index = fieldFromInstruction(Insn, 5, 3); 4870 if (fieldFromInstruction(Insn, 4, 1)) 4871 align = 2; 4872 break; 4873 case 1: 4874 index = fieldFromInstruction(Insn, 6, 2); 4875 if (fieldFromInstruction(Insn, 4, 1)) 4876 align = 4; 4877 if (fieldFromInstruction(Insn, 5, 1)) 4878 inc = 2; 4879 break; 4880 case 2: 4881 if (fieldFromInstruction(Insn, 5, 1)) 4882 return MCDisassembler::Fail; // UNDEFINED 4883 index = fieldFromInstruction(Insn, 7, 1); 4884 if (fieldFromInstruction(Insn, 4, 1) != 0) 4885 align = 8; 4886 if (fieldFromInstruction(Insn, 6, 1)) 4887 inc = 2; 4888 break; 4889 } 4890 4891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4892 return MCDisassembler::Fail; 4893 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4894 return MCDisassembler::Fail; 4895 if (Rm != 0xF) { // Writeback 4896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4897 return MCDisassembler::Fail; 4898 } 4899 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4900 return MCDisassembler::Fail; 4901 Inst.addOperand(MCOperand::createImm(align)); 4902 if (Rm != 0xF) { 4903 if (Rm != 0xD) { 4904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4905 return MCDisassembler::Fail; 4906 } else 4907 Inst.addOperand(MCOperand::createReg(0)); 4908 } 4909 4910 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4911 return MCDisassembler::Fail; 4912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4913 return MCDisassembler::Fail; 4914 Inst.addOperand(MCOperand::createImm(index)); 4915 4916 return S; 4917 } 4918 4919 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4920 uint64_t Address, const void *Decoder) { 4921 DecodeStatus S = MCDisassembler::Success; 4922 4923 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4924 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4925 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4926 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4927 unsigned size = fieldFromInstruction(Insn, 10, 2); 4928 4929 unsigned align = 0; 4930 unsigned index = 0; 4931 unsigned inc = 1; 4932 switch (size) { 4933 default: 4934 return MCDisassembler::Fail; 4935 case 0: 4936 index = fieldFromInstruction(Insn, 5, 3); 4937 if (fieldFromInstruction(Insn, 4, 1)) 4938 align = 2; 4939 break; 4940 case 1: 4941 index = fieldFromInstruction(Insn, 6, 2); 4942 if (fieldFromInstruction(Insn, 4, 1)) 4943 align = 4; 4944 if (fieldFromInstruction(Insn, 5, 1)) 4945 inc = 2; 4946 break; 4947 case 2: 4948 if (fieldFromInstruction(Insn, 5, 1)) 4949 return MCDisassembler::Fail; // UNDEFINED 4950 index = fieldFromInstruction(Insn, 7, 1); 4951 if (fieldFromInstruction(Insn, 4, 1) != 0) 4952 align = 8; 4953 if (fieldFromInstruction(Insn, 6, 1)) 4954 inc = 2; 4955 break; 4956 } 4957 4958 if (Rm != 0xF) { // Writeback 4959 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4960 return MCDisassembler::Fail; 4961 } 4962 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4963 return MCDisassembler::Fail; 4964 Inst.addOperand(MCOperand::createImm(align)); 4965 if (Rm != 0xF) { 4966 if (Rm != 0xD) { 4967 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4968 return MCDisassembler::Fail; 4969 } else 4970 Inst.addOperand(MCOperand::createReg(0)); 4971 } 4972 4973 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4974 return MCDisassembler::Fail; 4975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4976 return MCDisassembler::Fail; 4977 Inst.addOperand(MCOperand::createImm(index)); 4978 4979 return S; 4980 } 4981 4982 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4983 uint64_t Address, const void *Decoder) { 4984 DecodeStatus S = MCDisassembler::Success; 4985 4986 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4987 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4988 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4989 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4990 unsigned size = fieldFromInstruction(Insn, 10, 2); 4991 4992 unsigned align = 0; 4993 unsigned index = 0; 4994 unsigned inc = 1; 4995 switch (size) { 4996 default: 4997 return MCDisassembler::Fail; 4998 case 0: 4999 if (fieldFromInstruction(Insn, 4, 1)) 5000 return MCDisassembler::Fail; // UNDEFINED 5001 index = fieldFromInstruction(Insn, 5, 3); 5002 break; 5003 case 1: 5004 if (fieldFromInstruction(Insn, 4, 1)) 5005 return MCDisassembler::Fail; // UNDEFINED 5006 index = fieldFromInstruction(Insn, 6, 2); 5007 if (fieldFromInstruction(Insn, 5, 1)) 5008 inc = 2; 5009 break; 5010 case 2: 5011 if (fieldFromInstruction(Insn, 4, 2)) 5012 return MCDisassembler::Fail; // UNDEFINED 5013 index = fieldFromInstruction(Insn, 7, 1); 5014 if (fieldFromInstruction(Insn, 6, 1)) 5015 inc = 2; 5016 break; 5017 } 5018 5019 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5020 return MCDisassembler::Fail; 5021 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5022 return MCDisassembler::Fail; 5023 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5024 return MCDisassembler::Fail; 5025 5026 if (Rm != 0xF) { // Writeback 5027 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5028 return MCDisassembler::Fail; 5029 } 5030 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5031 return MCDisassembler::Fail; 5032 Inst.addOperand(MCOperand::createImm(align)); 5033 if (Rm != 0xF) { 5034 if (Rm != 0xD) { 5035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5036 return MCDisassembler::Fail; 5037 } else 5038 Inst.addOperand(MCOperand::createReg(0)); 5039 } 5040 5041 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5042 return MCDisassembler::Fail; 5043 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5044 return MCDisassembler::Fail; 5045 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5046 return MCDisassembler::Fail; 5047 Inst.addOperand(MCOperand::createImm(index)); 5048 5049 return S; 5050 } 5051 5052 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5053 uint64_t Address, const void *Decoder) { 5054 DecodeStatus S = MCDisassembler::Success; 5055 5056 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5057 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5058 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5059 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5060 unsigned size = fieldFromInstruction(Insn, 10, 2); 5061 5062 unsigned align = 0; 5063 unsigned index = 0; 5064 unsigned inc = 1; 5065 switch (size) { 5066 default: 5067 return MCDisassembler::Fail; 5068 case 0: 5069 if (fieldFromInstruction(Insn, 4, 1)) 5070 return MCDisassembler::Fail; // UNDEFINED 5071 index = fieldFromInstruction(Insn, 5, 3); 5072 break; 5073 case 1: 5074 if (fieldFromInstruction(Insn, 4, 1)) 5075 return MCDisassembler::Fail; // UNDEFINED 5076 index = fieldFromInstruction(Insn, 6, 2); 5077 if (fieldFromInstruction(Insn, 5, 1)) 5078 inc = 2; 5079 break; 5080 case 2: 5081 if (fieldFromInstruction(Insn, 4, 2)) 5082 return MCDisassembler::Fail; // UNDEFINED 5083 index = fieldFromInstruction(Insn, 7, 1); 5084 if (fieldFromInstruction(Insn, 6, 1)) 5085 inc = 2; 5086 break; 5087 } 5088 5089 if (Rm != 0xF) { // Writeback 5090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5091 return MCDisassembler::Fail; 5092 } 5093 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5094 return MCDisassembler::Fail; 5095 Inst.addOperand(MCOperand::createImm(align)); 5096 if (Rm != 0xF) { 5097 if (Rm != 0xD) { 5098 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5099 return MCDisassembler::Fail; 5100 } else 5101 Inst.addOperand(MCOperand::createReg(0)); 5102 } 5103 5104 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5105 return MCDisassembler::Fail; 5106 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5107 return MCDisassembler::Fail; 5108 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5109 return MCDisassembler::Fail; 5110 Inst.addOperand(MCOperand::createImm(index)); 5111 5112 return S; 5113 } 5114 5115 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5116 uint64_t Address, const void *Decoder) { 5117 DecodeStatus S = MCDisassembler::Success; 5118 5119 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5120 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5121 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5122 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5123 unsigned size = fieldFromInstruction(Insn, 10, 2); 5124 5125 unsigned align = 0; 5126 unsigned index = 0; 5127 unsigned inc = 1; 5128 switch (size) { 5129 default: 5130 return MCDisassembler::Fail; 5131 case 0: 5132 if (fieldFromInstruction(Insn, 4, 1)) 5133 align = 4; 5134 index = fieldFromInstruction(Insn, 5, 3); 5135 break; 5136 case 1: 5137 if (fieldFromInstruction(Insn, 4, 1)) 5138 align = 8; 5139 index = fieldFromInstruction(Insn, 6, 2); 5140 if (fieldFromInstruction(Insn, 5, 1)) 5141 inc = 2; 5142 break; 5143 case 2: 5144 switch (fieldFromInstruction(Insn, 4, 2)) { 5145 case 0: 5146 align = 0; break; 5147 case 3: 5148 return MCDisassembler::Fail; 5149 default: 5150 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5151 } 5152 5153 index = fieldFromInstruction(Insn, 7, 1); 5154 if (fieldFromInstruction(Insn, 6, 1)) 5155 inc = 2; 5156 break; 5157 } 5158 5159 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5160 return MCDisassembler::Fail; 5161 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5162 return MCDisassembler::Fail; 5163 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5164 return MCDisassembler::Fail; 5165 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5166 return MCDisassembler::Fail; 5167 5168 if (Rm != 0xF) { // Writeback 5169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5170 return MCDisassembler::Fail; 5171 } 5172 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5173 return MCDisassembler::Fail; 5174 Inst.addOperand(MCOperand::createImm(align)); 5175 if (Rm != 0xF) { 5176 if (Rm != 0xD) { 5177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5178 return MCDisassembler::Fail; 5179 } else 5180 Inst.addOperand(MCOperand::createReg(0)); 5181 } 5182 5183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5184 return MCDisassembler::Fail; 5185 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5186 return MCDisassembler::Fail; 5187 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5188 return MCDisassembler::Fail; 5189 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5190 return MCDisassembler::Fail; 5191 Inst.addOperand(MCOperand::createImm(index)); 5192 5193 return S; 5194 } 5195 5196 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5197 uint64_t Address, const void *Decoder) { 5198 DecodeStatus S = MCDisassembler::Success; 5199 5200 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5201 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5202 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5203 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5204 unsigned size = fieldFromInstruction(Insn, 10, 2); 5205 5206 unsigned align = 0; 5207 unsigned index = 0; 5208 unsigned inc = 1; 5209 switch (size) { 5210 default: 5211 return MCDisassembler::Fail; 5212 case 0: 5213 if (fieldFromInstruction(Insn, 4, 1)) 5214 align = 4; 5215 index = fieldFromInstruction(Insn, 5, 3); 5216 break; 5217 case 1: 5218 if (fieldFromInstruction(Insn, 4, 1)) 5219 align = 8; 5220 index = fieldFromInstruction(Insn, 6, 2); 5221 if (fieldFromInstruction(Insn, 5, 1)) 5222 inc = 2; 5223 break; 5224 case 2: 5225 switch (fieldFromInstruction(Insn, 4, 2)) { 5226 case 0: 5227 align = 0; break; 5228 case 3: 5229 return MCDisassembler::Fail; 5230 default: 5231 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5232 } 5233 5234 index = fieldFromInstruction(Insn, 7, 1); 5235 if (fieldFromInstruction(Insn, 6, 1)) 5236 inc = 2; 5237 break; 5238 } 5239 5240 if (Rm != 0xF) { // Writeback 5241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5242 return MCDisassembler::Fail; 5243 } 5244 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5245 return MCDisassembler::Fail; 5246 Inst.addOperand(MCOperand::createImm(align)); 5247 if (Rm != 0xF) { 5248 if (Rm != 0xD) { 5249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5250 return MCDisassembler::Fail; 5251 } else 5252 Inst.addOperand(MCOperand::createReg(0)); 5253 } 5254 5255 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5256 return MCDisassembler::Fail; 5257 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5258 return MCDisassembler::Fail; 5259 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5260 return MCDisassembler::Fail; 5261 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5262 return MCDisassembler::Fail; 5263 Inst.addOperand(MCOperand::createImm(index)); 5264 5265 return S; 5266 } 5267 5268 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5269 uint64_t Address, const void *Decoder) { 5270 DecodeStatus S = MCDisassembler::Success; 5271 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5272 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5273 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5274 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5275 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5276 5277 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5278 S = MCDisassembler::SoftFail; 5279 5280 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5281 return MCDisassembler::Fail; 5282 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5283 return MCDisassembler::Fail; 5284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5285 return MCDisassembler::Fail; 5286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5287 return MCDisassembler::Fail; 5288 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5289 return MCDisassembler::Fail; 5290 5291 return S; 5292 } 5293 5294 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5295 uint64_t Address, const void *Decoder) { 5296 DecodeStatus S = MCDisassembler::Success; 5297 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5298 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5299 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5300 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5301 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5302 5303 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5304 S = MCDisassembler::SoftFail; 5305 5306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5307 return MCDisassembler::Fail; 5308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5309 return MCDisassembler::Fail; 5310 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5311 return MCDisassembler::Fail; 5312 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5313 return MCDisassembler::Fail; 5314 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5315 return MCDisassembler::Fail; 5316 5317 return S; 5318 } 5319 5320 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5321 uint64_t Address, const void *Decoder) { 5322 DecodeStatus S = MCDisassembler::Success; 5323 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5324 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5325 5326 if (pred == 0xF) { 5327 pred = 0xE; 5328 S = MCDisassembler::SoftFail; 5329 } 5330 5331 if (mask == 0x0) 5332 return MCDisassembler::Fail; 5333 5334 // IT masks are encoded as a sequence of replacement low-order bits 5335 // for the condition code. So if the low bit of the starting 5336 // condition code is 1, then we have to flip all the bits above the 5337 // terminating bit (which is the lowest 1 bit). 5338 if (pred & 1) { 5339 unsigned LowBit = mask & -mask; 5340 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5341 mask ^= BitsAboveLowBit; 5342 } 5343 5344 Inst.addOperand(MCOperand::createImm(pred)); 5345 Inst.addOperand(MCOperand::createImm(mask)); 5346 return S; 5347 } 5348 5349 static DecodeStatus 5350 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5351 uint64_t Address, const void *Decoder) { 5352 DecodeStatus S = MCDisassembler::Success; 5353 5354 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5355 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5356 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5357 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5358 unsigned W = fieldFromInstruction(Insn, 21, 1); 5359 unsigned U = fieldFromInstruction(Insn, 23, 1); 5360 unsigned P = fieldFromInstruction(Insn, 24, 1); 5361 bool writeback = (W == 1) | (P == 0); 5362 5363 addr |= (U << 8) | (Rn << 9); 5364 5365 if (writeback && (Rn == Rt || Rn == Rt2)) 5366 Check(S, MCDisassembler::SoftFail); 5367 if (Rt == Rt2) 5368 Check(S, MCDisassembler::SoftFail); 5369 5370 // Rt 5371 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5372 return MCDisassembler::Fail; 5373 // Rt2 5374 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5375 return MCDisassembler::Fail; 5376 // Writeback operand 5377 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5378 return MCDisassembler::Fail; 5379 // addr 5380 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5381 return MCDisassembler::Fail; 5382 5383 return S; 5384 } 5385 5386 static DecodeStatus 5387 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5388 uint64_t Address, const void *Decoder) { 5389 DecodeStatus S = MCDisassembler::Success; 5390 5391 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5392 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5393 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5394 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5395 unsigned W = fieldFromInstruction(Insn, 21, 1); 5396 unsigned U = fieldFromInstruction(Insn, 23, 1); 5397 unsigned P = fieldFromInstruction(Insn, 24, 1); 5398 bool writeback = (W == 1) | (P == 0); 5399 5400 addr |= (U << 8) | (Rn << 9); 5401 5402 if (writeback && (Rn == Rt || Rn == Rt2)) 5403 Check(S, MCDisassembler::SoftFail); 5404 5405 // Writeback operand 5406 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5407 return MCDisassembler::Fail; 5408 // Rt 5409 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5410 return MCDisassembler::Fail; 5411 // Rt2 5412 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5413 return MCDisassembler::Fail; 5414 // addr 5415 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5416 return MCDisassembler::Fail; 5417 5418 return S; 5419 } 5420 5421 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5422 uint64_t Address, const void *Decoder) { 5423 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5424 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5425 if (sign1 != sign2) return MCDisassembler::Fail; 5426 5427 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5428 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5429 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5430 Val |= sign1 << 12; 5431 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5432 5433 return MCDisassembler::Success; 5434 } 5435 5436 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5437 uint64_t Address, 5438 const void *Decoder) { 5439 DecodeStatus S = MCDisassembler::Success; 5440 5441 // Shift of "asr #32" is not allowed in Thumb2 mode. 5442 if (Val == 0x20) S = MCDisassembler::Fail; 5443 Inst.addOperand(MCOperand::createImm(Val)); 5444 return S; 5445 } 5446 5447 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5448 uint64_t Address, const void *Decoder) { 5449 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5450 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5451 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5452 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5453 5454 if (pred == 0xF) 5455 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5456 5457 DecodeStatus S = MCDisassembler::Success; 5458 5459 if (Rt == Rn || Rn == Rt2) 5460 S = MCDisassembler::SoftFail; 5461 5462 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5463 return MCDisassembler::Fail; 5464 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5465 return MCDisassembler::Fail; 5466 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5467 return MCDisassembler::Fail; 5468 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5469 return MCDisassembler::Fail; 5470 5471 return S; 5472 } 5473 5474 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5475 uint64_t Address, const void *Decoder) { 5476 const FeatureBitset &featureBits = 5477 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5478 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5479 5480 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5481 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5482 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5483 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5484 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5485 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5486 unsigned op = fieldFromInstruction(Insn, 5, 1); 5487 5488 DecodeStatus S = MCDisassembler::Success; 5489 5490 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5491 if (!(imm & 0x38)) { 5492 if (cmode == 0xF) { 5493 if (op == 1) return MCDisassembler::Fail; 5494 Inst.setOpcode(ARM::VMOVv2f32); 5495 } 5496 if (hasFullFP16) { 5497 if (cmode == 0xE) { 5498 if (op == 1) { 5499 Inst.setOpcode(ARM::VMOVv1i64); 5500 } else { 5501 Inst.setOpcode(ARM::VMOVv8i8); 5502 } 5503 } 5504 if (cmode == 0xD) { 5505 if (op == 1) { 5506 Inst.setOpcode(ARM::VMVNv2i32); 5507 } else { 5508 Inst.setOpcode(ARM::VMOVv2i32); 5509 } 5510 } 5511 if (cmode == 0xC) { 5512 if (op == 1) { 5513 Inst.setOpcode(ARM::VMVNv2i32); 5514 } else { 5515 Inst.setOpcode(ARM::VMOVv2i32); 5516 } 5517 } 5518 } 5519 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5520 } 5521 5522 if (!(imm & 0x20)) return MCDisassembler::Fail; 5523 5524 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5525 return MCDisassembler::Fail; 5526 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5527 return MCDisassembler::Fail; 5528 Inst.addOperand(MCOperand::createImm(64 - imm)); 5529 5530 return S; 5531 } 5532 5533 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5534 uint64_t Address, const void *Decoder) { 5535 const FeatureBitset &featureBits = 5536 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5537 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5538 5539 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5540 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5541 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5542 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5543 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5544 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5545 unsigned op = fieldFromInstruction(Insn, 5, 1); 5546 5547 DecodeStatus S = MCDisassembler::Success; 5548 5549 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5550 if (!(imm & 0x38)) { 5551 if (cmode == 0xF) { 5552 if (op == 1) return MCDisassembler::Fail; 5553 Inst.setOpcode(ARM::VMOVv4f32); 5554 } 5555 if (hasFullFP16) { 5556 if (cmode == 0xE) { 5557 if (op == 1) { 5558 Inst.setOpcode(ARM::VMOVv2i64); 5559 } else { 5560 Inst.setOpcode(ARM::VMOVv16i8); 5561 } 5562 } 5563 if (cmode == 0xD) { 5564 if (op == 1) { 5565 Inst.setOpcode(ARM::VMVNv4i32); 5566 } else { 5567 Inst.setOpcode(ARM::VMOVv4i32); 5568 } 5569 } 5570 if (cmode == 0xC) { 5571 if (op == 1) { 5572 Inst.setOpcode(ARM::VMVNv4i32); 5573 } else { 5574 Inst.setOpcode(ARM::VMOVv4i32); 5575 } 5576 } 5577 } 5578 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5579 } 5580 5581 if (!(imm & 0x20)) return MCDisassembler::Fail; 5582 5583 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5584 return MCDisassembler::Fail; 5585 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5586 return MCDisassembler::Fail; 5587 Inst.addOperand(MCOperand::createImm(64 - imm)); 5588 5589 return S; 5590 } 5591 5592 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5593 unsigned Insn, 5594 uint64_t Address, 5595 const void *Decoder) { 5596 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5597 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5598 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5599 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5600 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5601 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5602 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5603 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5604 5605 DecodeStatus S = MCDisassembler::Success; 5606 5607 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5608 5609 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5610 return MCDisassembler::Fail; 5611 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5612 return MCDisassembler::Fail; 5613 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5614 return MCDisassembler::Fail; 5615 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5616 return MCDisassembler::Fail; 5617 // The lane index does not have any bits in the encoding, because it can only 5618 // be 0. 5619 Inst.addOperand(MCOperand::createImm(0)); 5620 Inst.addOperand(MCOperand::createImm(rotate)); 5621 5622 return S; 5623 } 5624 5625 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5626 uint64_t Address, const void *Decoder) { 5627 DecodeStatus S = MCDisassembler::Success; 5628 5629 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5630 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5631 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5632 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5633 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5634 5635 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5636 S = MCDisassembler::SoftFail; 5637 5638 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5639 return MCDisassembler::Fail; 5640 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5641 return MCDisassembler::Fail; 5642 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5643 return MCDisassembler::Fail; 5644 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5645 return MCDisassembler::Fail; 5646 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5647 return MCDisassembler::Fail; 5648 5649 return S; 5650 } 5651 5652 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5653 uint64_t Address, const void *Decoder) { 5654 DecodeStatus S = MCDisassembler::Success; 5655 5656 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5657 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5658 unsigned cop = fieldFromInstruction(Val, 8, 4); 5659 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5660 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5661 5662 if ((cop & ~0x1) == 0xa) 5663 return MCDisassembler::Fail; 5664 5665 if (Rt == Rt2) 5666 S = MCDisassembler::SoftFail; 5667 5668 // We have to check if the instruction is MRRC2 5669 // or MCRR2 when constructing the operands for 5670 // Inst. Reason is because MRRC2 stores to two 5671 // registers so it's tablegen desc has has two 5672 // outputs whereas MCRR doesn't store to any 5673 // registers so all of it's operands are listed 5674 // as inputs, therefore the operand order for 5675 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5676 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5677 5678 if (Inst.getOpcode() == ARM::MRRC2) { 5679 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5680 return MCDisassembler::Fail; 5681 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5682 return MCDisassembler::Fail; 5683 } 5684 Inst.addOperand(MCOperand::createImm(cop)); 5685 Inst.addOperand(MCOperand::createImm(opc1)); 5686 if (Inst.getOpcode() == ARM::MCRR2) { 5687 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5688 return MCDisassembler::Fail; 5689 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5690 return MCDisassembler::Fail; 5691 } 5692 Inst.addOperand(MCOperand::createImm(CRm)); 5693 5694 return S; 5695 } 5696 5697 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5698 uint64_t Address, 5699 const void *Decoder) { 5700 const FeatureBitset &featureBits = 5701 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5702 DecodeStatus S = MCDisassembler::Success; 5703 5704 // Add explicit operand for the destination sysreg, for cases where 5705 // we have to model it for code generation purposes. 5706 switch (Inst.getOpcode()) { 5707 case ARM::VMSR_FPSCR_NZCVQC: 5708 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5709 break; 5710 case ARM::VMSR_P0: 5711 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5712 break; 5713 } 5714 5715 if (Inst.getOpcode() != ARM::FMSTAT) { 5716 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5717 5718 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5719 if (Rt == 13 || Rt == 15) 5720 S = MCDisassembler::SoftFail; 5721 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5722 } else 5723 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5724 } 5725 5726 // Add explicit operand for the source sysreg, similarly to above. 5727 switch (Inst.getOpcode()) { 5728 case ARM::VMRS_FPSCR_NZCVQC: 5729 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5730 break; 5731 case ARM::VMRS_P0: 5732 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5733 break; 5734 } 5735 5736 if (featureBits[ARM::ModeThumb]) { 5737 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5738 Inst.addOperand(MCOperand::createReg(0)); 5739 } else { 5740 unsigned pred = fieldFromInstruction(Val, 28, 4); 5741 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5742 return MCDisassembler::Fail; 5743 } 5744 5745 return S; 5746 } 5747 5748 template <bool isSigned, bool isNeg, int size> 5749 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5750 uint64_t Address, 5751 const void *Decoder) { 5752 DecodeStatus S = MCDisassembler::Success; 5753 if (Val == 0) 5754 S = MCDisassembler::SoftFail; 5755 5756 uint64_t DecVal; 5757 if (isSigned) 5758 DecVal = SignExtend32<size + 1>(Val << 1); 5759 else 5760 DecVal = (Val << 1); 5761 5762 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5763 Decoder)) 5764 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5765 return S; 5766 } 5767 5768 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5769 uint64_t Address, 5770 const void *Decoder) { 5771 5772 uint64_t LocImm = Inst.getOperand(0).getImm(); 5773 Val = LocImm + (2 << Val); 5774 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5775 Decoder)) 5776 Inst.addOperand(MCOperand::createImm(Val)); 5777 return MCDisassembler::Success; 5778 } 5779 5780 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5781 uint64_t Address, 5782 const void *Decoder) { 5783 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5784 return MCDisassembler::Fail; 5785 Inst.addOperand(MCOperand::createImm(Val)); 5786 return MCDisassembler::Success; 5787 } 5788 5789 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5790 const void *Decoder) { 5791 DecodeStatus S = MCDisassembler::Success; 5792 5793 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5794 fieldFromInstruction(Insn, 1, 10) << 1; 5795 switch (Inst.getOpcode()) { 5796 case ARM::t2LEUpdate: 5797 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5798 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5799 LLVM_FALLTHROUGH; 5800 case ARM::t2LE: 5801 if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address, 5802 Decoder))) 5803 return MCDisassembler::Fail; 5804 break; 5805 case ARM::t2WLS: 5806 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5807 if (!Check(S, 5808 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5809 Address, Decoder)) || 5810 !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address, 5811 Decoder))) 5812 return MCDisassembler::Fail; 5813 break; 5814 case ARM::t2DLS: 5815 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5816 if (Rn == 0xF) { 5817 return MCDisassembler::Fail; 5818 } else { 5819 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5820 if (!Check(S, DecoderGPRRegisterClass(Inst, 5821 fieldFromInstruction(Insn, 16, 4), 5822 Address, Decoder))) 5823 return MCDisassembler::Fail; 5824 } 5825 break; 5826 } 5827 return S; 5828 } 5829 5830 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 5831 uint64_t Address, 5832 const void *Decoder) { 5833 DecodeStatus S = MCDisassembler::Success; 5834 5835 if (Val == 0) 5836 Val = 32; 5837 5838 Inst.addOperand(MCOperand::createImm(Val)); 5839 5840 return S; 5841 } 5842 5843 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 5844 uint64_t Address, const void *Decoder) { 5845 if ((RegNo) + 1 > 11) 5846 return MCDisassembler::Fail; 5847 5848 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 5849 Inst.addOperand(MCOperand::createReg(Register)); 5850 return MCDisassembler::Success; 5851 } 5852 5853 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 5854 uint64_t Address, const void *Decoder) { 5855 if ((RegNo) > 14) 5856 return MCDisassembler::Fail; 5857 5858 unsigned Register = GPRDecoderTable[(RegNo)]; 5859 Inst.addOperand(MCOperand::createReg(Register)); 5860 return MCDisassembler::Success; 5861 } 5862 5863 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 5864 const void *Decoder) { 5865 DecodeStatus S = MCDisassembler::Success; 5866 5867 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5868 Inst.addOperand(MCOperand::createReg(0)); 5869 if (Inst.getOpcode() == ARM::VSCCLRMD) { 5870 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 5871 (fieldFromInstruction(Insn, 12, 4) << 8) | 5872 (fieldFromInstruction(Insn, 22, 1) << 12); 5873 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 5874 return MCDisassembler::Fail; 5875 } 5876 } else { 5877 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 5878 (fieldFromInstruction(Insn, 22, 1) << 8) | 5879 (fieldFromInstruction(Insn, 12, 4) << 9); 5880 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 5881 return MCDisassembler::Fail; 5882 } 5883 } 5884 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5885 5886 return S; 5887 } 5888 5889 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 5890 uint64_t Address, 5891 const void *Decoder) { 5892 if (RegNo > 7) 5893 return MCDisassembler::Fail; 5894 5895 unsigned Register = QPRDecoderTable[RegNo]; 5896 Inst.addOperand(MCOperand::createReg(Register)); 5897 return MCDisassembler::Success; 5898 } 5899 5900 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 5901 uint64_t Address, 5902 const void *Decoder) { 5903 DecodeStatus S = MCDisassembler::Success; 5904 5905 // Parse VPT mask and encode it in the MCInst as an immediate with the same 5906 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 5907 // 't' as 0 and finish with a 1. 5908 unsigned Imm = 0; 5909 // We always start with a 't'. 5910 unsigned CurBit = 0; 5911 for (int i = 3; i >= 0; --i) { 5912 // If the bit we are looking at is not the same as last one, invert the 5913 // CurBit, if it is the same leave it as is. 5914 CurBit ^= (Val >> i) & 1U; 5915 5916 // Encode the CurBit at the right place in the immediate. 5917 Imm |= (CurBit << i); 5918 5919 // If we are done, finish the encoding with a 1. 5920 if ((Val & ~(~0U << i)) == 0) { 5921 Imm |= 1U << i; 5922 break; 5923 } 5924 } 5925 5926 Inst.addOperand(MCOperand::createImm(Imm)); 5927 5928 return S; 5929 } 5930 5931 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 5932 uint64_t Address, const void *Decoder) { 5933 // The vpred_r operand type includes an MQPR register field derived 5934 // from the encoding. But we don't actually want to add an operand 5935 // to the MCInst at this stage, because AddThumbPredicate will do it 5936 // later, and will infer the register number from the TIED_TO 5937 // constraint. So this is a deliberately empty decoder method that 5938 // will inhibit the auto-generated disassembly code from adding an 5939 // operand at all. 5940 return MCDisassembler::Success; 5941 } 5942 5943 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 5944 unsigned Val, 5945 uint64_t Address, 5946 const void *Decoder) { 5947 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 5948 return MCDisassembler::Success; 5949 } 5950 5951 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 5952 unsigned Val, 5953 uint64_t Address, 5954 const void *Decoder) { 5955 unsigned Code; 5956 switch (Val & 0x3) { 5957 case 0: 5958 Code = ARMCC::GE; 5959 break; 5960 case 1: 5961 Code = ARMCC::LT; 5962 break; 5963 case 2: 5964 Code = ARMCC::GT; 5965 break; 5966 case 3: 5967 Code = ARMCC::LE; 5968 break; 5969 } 5970 Inst.addOperand(MCOperand::createImm(Code)); 5971 return MCDisassembler::Success; 5972 } 5973 5974 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 5975 unsigned Val, 5976 uint64_t Address, 5977 const void *Decoder) { 5978 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 5979 return MCDisassembler::Success; 5980 } 5981 5982 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 5983 uint64_t Address, 5984 const void *Decoder) { 5985 unsigned Code; 5986 switch (Val) { 5987 default: 5988 return MCDisassembler::Fail; 5989 case 0: 5990 Code = ARMCC::EQ; 5991 break; 5992 case 1: 5993 Code = ARMCC::NE; 5994 break; 5995 case 4: 5996 Code = ARMCC::GE; 5997 break; 5998 case 5: 5999 Code = ARMCC::LT; 6000 break; 6001 case 6: 6002 Code = ARMCC::GT; 6003 break; 6004 case 7: 6005 Code = ARMCC::LE; 6006 break; 6007 } 6008 6009 Inst.addOperand(MCOperand::createImm(Code)); 6010 return MCDisassembler::Success; 6011 } 6012 6013 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6014 uint64_t Address, const void *Decoder) { 6015 DecodeStatus S = MCDisassembler::Success; 6016 6017 unsigned DecodedVal = 64 - Val; 6018 6019 switch (Inst.getOpcode()) { 6020 case ARM::MVE_VCVTf16s16_fix: 6021 case ARM::MVE_VCVTs16f16_fix: 6022 case ARM::MVE_VCVTf16u16_fix: 6023 case ARM::MVE_VCVTu16f16_fix: 6024 if (DecodedVal > 16) 6025 return MCDisassembler::Fail; 6026 case ARM::MVE_VCVTf32s32_fix: 6027 case ARM::MVE_VCVTs32f32_fix: 6028 case ARM::MVE_VCVTf32u32_fix: 6029 case ARM::MVE_VCVTu32f32_fix: 6030 if (DecodedVal > 32) 6031 return MCDisassembler::Fail; 6032 } 6033 6034 Inst.addOperand(MCOperand::createImm(64 - Val)); 6035 6036 return S; 6037 } 6038 6039 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6040 switch (Opcode) { 6041 case ARM::VSTR_P0_off: 6042 case ARM::VSTR_P0_pre: 6043 case ARM::VSTR_P0_post: 6044 case ARM::VLDR_P0_off: 6045 case ARM::VLDR_P0_pre: 6046 case ARM::VLDR_P0_post: 6047 return ARM::P0; 6048 default: 6049 return 0; 6050 } 6051 } 6052 6053 template<bool Writeback> 6054 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6055 uint64_t Address, 6056 const void *Decoder) { 6057 switch (Inst.getOpcode()) { 6058 case ARM::VSTR_FPSCR_pre: 6059 case ARM::VSTR_FPSCR_NZCVQC_pre: 6060 case ARM::VLDR_FPSCR_pre: 6061 case ARM::VLDR_FPSCR_NZCVQC_pre: 6062 case ARM::VSTR_FPSCR_off: 6063 case ARM::VSTR_FPSCR_NZCVQC_off: 6064 case ARM::VLDR_FPSCR_off: 6065 case ARM::VLDR_FPSCR_NZCVQC_off: 6066 case ARM::VSTR_FPSCR_post: 6067 case ARM::VSTR_FPSCR_NZCVQC_post: 6068 case ARM::VLDR_FPSCR_post: 6069 case ARM::VLDR_FPSCR_NZCVQC_post: 6070 const FeatureBitset &featureBits = 6071 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6072 6073 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6074 return MCDisassembler::Fail; 6075 } 6076 6077 DecodeStatus S = MCDisassembler::Success; 6078 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6079 Inst.addOperand(MCOperand::createReg(Sysreg)); 6080 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6081 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6082 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6083 6084 if (Writeback) { 6085 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6086 return MCDisassembler::Fail; 6087 } 6088 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6089 return MCDisassembler::Fail; 6090 6091 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6092 Inst.addOperand(MCOperand::createReg(0)); 6093 6094 return S; 6095 } 6096 6097 template <int shift> 6098 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6099 uint64_t Address, 6100 const void *Decoder) { 6101 Val <<= shift; 6102 6103 Inst.addOperand(MCOperand::createImm(Val)); 6104 return MCDisassembler::Success; 6105 } 6106 6107 static DecodeStatus DecodeMVEOverlappingLongShift( 6108 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6109 DecodeStatus S = MCDisassembler::Success; 6110 6111 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6112 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6113 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6114 6115 if (RdaHi == 14) { 6116 // This value of RdaHi (really indicating pc, because RdaHi has to 6117 // be an odd-numbered register, so the low bit will be set by the 6118 // decode function below) indicates that we must decode as SQRSHR 6119 // or UQRSHL, which both have a single Rda register field with all 6120 // four bits. 6121 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6122 6123 switch (Inst.getOpcode()) { 6124 case ARM::MVE_ASRLr: 6125 case ARM::MVE_SQRSHRL: 6126 Inst.setOpcode(ARM::MVE_SQRSHR); 6127 break; 6128 case ARM::MVE_LSLLr: 6129 case ARM::MVE_UQRSHLL: 6130 Inst.setOpcode(ARM::MVE_UQRSHL); 6131 break; 6132 default: 6133 llvm_unreachable("Unexpected starting opcode!"); 6134 } 6135 6136 // Rda as output parameter 6137 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6138 return MCDisassembler::Fail; 6139 6140 // Rda again as input parameter 6141 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6142 return MCDisassembler::Fail; 6143 6144 // Rm, the amount to shift by 6145 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6146 return MCDisassembler::Fail; 6147 6148 return S; 6149 } 6150 6151 // Otherwise, we decode as whichever opcode our caller has already 6152 // put into Inst. Those all look the same: 6153 6154 // RdaLo,RdaHi as output parameters 6155 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6156 return MCDisassembler::Fail; 6157 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6158 return MCDisassembler::Fail; 6159 6160 // RdaLo,RdaHi again as input parameters 6161 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6162 return MCDisassembler::Fail; 6163 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6164 return MCDisassembler::Fail; 6165 6166 // Rm, the amount to shift by 6167 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6168 return MCDisassembler::Fail; 6169 6170 return S; 6171 } 6172 6173 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6174 const void *Decoder) { 6175 DecodeStatus S = MCDisassembler::Success; 6176 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6177 fieldFromInstruction(Insn, 13, 3)); 6178 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6179 fieldFromInstruction(Insn, 1, 3)); 6180 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6181 6182 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6183 return MCDisassembler::Fail; 6184 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6185 return MCDisassembler::Fail; 6186 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6187 return MCDisassembler::Fail; 6188 6189 return S; 6190 } 6191 6192 template<bool scalar, OperandDecoder predicate_decoder> 6193 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6194 const void *Decoder) { 6195 DecodeStatus S = MCDisassembler::Success; 6196 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6197 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6198 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6199 return MCDisassembler::Fail; 6200 6201 unsigned fc; 6202 6203 if (scalar) { 6204 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6205 fieldFromInstruction(Insn, 7, 1) | 6206 fieldFromInstruction(Insn, 5, 1) << 1; 6207 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6208 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6209 return MCDisassembler::Fail; 6210 } else { 6211 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6212 fieldFromInstruction(Insn, 7, 1) | 6213 fieldFromInstruction(Insn, 0, 1) << 1; 6214 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6215 fieldFromInstruction(Insn, 1, 3); 6216 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6217 return MCDisassembler::Fail; 6218 } 6219 6220 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6221 return MCDisassembler::Fail; 6222 6223 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6224 Inst.addOperand(MCOperand::createReg(0)); 6225 Inst.addOperand(MCOperand::createImm(0)); 6226 6227 return S; 6228 } 6229