1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142 private: 143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 144 ArrayRef<uint8_t> Bytes, uint64_t Address, 145 raw_ostream &CStream) const; 146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 148 ArrayRef<uint8_t> Bytes, uint64_t Address, 149 raw_ostream &CStream) const; 150 151 mutable ITStatus ITBlock; 152 mutable VPTStatus VPTBlock; 153 154 DecodeStatus AddThumbPredicate(MCInst&) const; 155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 156 }; 157 158 } // end anonymous namespace 159 160 static bool Check(DecodeStatus &Out, DecodeStatus In) { 161 switch (In) { 162 case MCDisassembler::Success: 163 // Out stays the same. 164 return true; 165 case MCDisassembler::SoftFail: 166 Out = In; 167 return true; 168 case MCDisassembler::Fail: 169 Out = In; 170 return false; 171 } 172 llvm_unreachable("Invalid DecodeStatus!"); 173 } 174 175 // Forward declare these because the autogenerated code will reference them. 176 // Definitions are further down. 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 186 unsigned RegNo, uint64_t Address, 187 const void *Decoder); 188 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRnospRegisterClass( 195 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 215 unsigned RegNo, 216 uint64_t Address, 217 const void *Decoder); 218 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 229 unsigned RegNo, uint64_t Address, 230 const void *Decoder); 231 232 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 243 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 248 unsigned Insn, 249 uint64_t Address, 250 const void *Decoder); 251 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 258 uint64_t Address, const void *Decoder); 259 260 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 261 unsigned Insn, 262 uint64_t Adddress, 263 const void *Decoder); 264 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 335 uint64_t Address, const void *Decoder); 336 template<int shift> 337 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 390 unsigned Val, 391 uint64_t Address, 392 const void *Decoder); 393 394 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 399 uint64_t Address, const void *Decoder); 400 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 401 uint64_t Address, const void *Decoder); 402 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 403 uint64_t Address, const void *Decoder); 404 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 415 uint64_t Address, const void* Decoder); 416 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 417 uint64_t Address, const void* Decoder); 418 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 419 uint64_t Address, const void* Decoder); 420 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 421 uint64_t Address, const void* Decoder); 422 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 423 uint64_t Address, const void *Decoder); 424 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 425 uint64_t Address, const void *Decoder); 426 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 427 uint64_t Address, const void *Decoder); 428 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 429 uint64_t Address, 430 const void *Decoder); 431 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 432 uint64_t Address, const void *Decoder); 433 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 434 uint64_t Address, const void *Decoder); 435 template<int shift> 436 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 437 uint64_t Address, const void *Decoder); 438 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 439 uint64_t Address, const void *Decoder); 440 template<int shift> 441 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 442 uint64_t Address, const void *Decoder); 443 template<int shift, int WriteBack> 444 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 447 uint64_t Address, const void *Decoder); 448 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 449 uint64_t Address, const void *Decoder); 450 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 451 uint64_t Address, const void *Decoder); 452 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 453 uint64_t Address, const void *Decoder); 454 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 455 uint64_t Address, const void *Decoder); 456 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 457 uint64_t Address, const void *Decoder); 458 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 459 uint64_t Address, const void *Decoder); 460 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 461 uint64_t Address, const void *Decoder); 462 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 463 uint64_t Address, const void *Decoder); 464 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 465 uint64_t Address, const void *Decoder); 466 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 467 uint64_t Address, const void *Decoder); 468 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 469 uint64_t Address, const void *Decoder); 470 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 471 uint64_t Address, const void *Decoder); 472 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 473 uint64_t Address, const void *Decoder); 474 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 475 uint64_t Address, const void *Decoder); 476 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 477 uint64_t Address, const void *Decoder); 478 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 479 uint64_t Address, const void *Decoder); 480 481 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 482 uint64_t Address, const void *Decoder); 483 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 484 uint64_t Address, const void *Decoder); 485 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 486 uint64_t Address, const void *Decoder); 487 488 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 489 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 490 uint64_t Address, const void *Decoder); 491 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 492 uint64_t Address, 493 const void *Decoder); 494 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 495 uint64_t Address, 496 const void *Decoder); 497 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 498 const void *Decoder); 499 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 500 uint64_t Address, 501 const void *Decoder); 502 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 503 const void *Decoder); 504 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 505 uint64_t Address, const void *Decoder); 506 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 507 uint64_t Address, const void *Decoder); 508 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 509 uint64_t Address, 510 const void *Decoder); 511 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 512 uint64_t Address, 513 const void *Decoder); 514 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 515 uint64_t Address, 516 const void *Decoder); 517 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 518 unsigned Val, 519 uint64_t Address, 520 const void *Decoder); 521 template<bool Writeback> 522 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 523 uint64_t Address, 524 const void *Decoder); 525 template<int shift> 526 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 527 uint64_t Address, const void *Decoder); 528 template<int shift> 529 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 530 uint64_t Address, const void *Decoder); 531 template<int shift> 532 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 533 uint64_t Address, const void *Decoder); 534 template<unsigned MinLog, unsigned MaxLog> 535 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 536 uint64_t Address, 537 const void *Decoder); 538 template <int shift> 539 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 540 uint64_t Address, 541 const void *Decoder); 542 template<unsigned start> 543 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 544 uint64_t Address, 545 const void *Decoder); 546 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 547 uint64_t Address, 548 const void *Decoder); 549 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 550 uint64_t Address, 551 const void *Decoder); 552 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 553 uint64_t Address, const void *Decoder); 554 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 555 uint64_t Address, const void *Decoder); 556 template<bool scalar, OperandDecoder predicate_decoder> 557 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 558 uint64_t Address, const void *Decoder); 559 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 560 uint64_t Address, const void *Decoder); 561 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 562 uint64_t Address, const void *Decoder); 563 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 564 uint64_t Address, 565 const void *Decoder); 566 #include "ARMGenDisassemblerTables.inc" 567 568 static MCDisassembler *createARMDisassembler(const Target &T, 569 const MCSubtargetInfo &STI, 570 MCContext &Ctx) { 571 return new ARMDisassembler(STI, Ctx); 572 } 573 574 // Post-decoding checks 575 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 576 uint64_t Address, raw_ostream &CS, 577 uint32_t Insn, 578 DecodeStatus Result) { 579 switch (MI.getOpcode()) { 580 case ARM::HVC: { 581 // HVC is undefined if condition = 0xf otherwise upredictable 582 // if condition != 0xe 583 uint32_t Cond = (Insn >> 28) & 0xF; 584 if (Cond == 0xF) 585 return MCDisassembler::Fail; 586 if (Cond != 0xE) 587 return MCDisassembler::SoftFail; 588 return Result; 589 } 590 case ARM::t2ADDri: 591 case ARM::t2ADDri12: 592 case ARM::t2ADDrr: 593 case ARM::t2ADDrs: 594 case ARM::t2SUBri: 595 case ARM::t2SUBri12: 596 case ARM::t2SUBrr: 597 case ARM::t2SUBrs: 598 if (MI.getOperand(0).getReg() == ARM::SP && 599 MI.getOperand(1).getReg() != ARM::SP) 600 return MCDisassembler::SoftFail; 601 return Result; 602 default: return Result; 603 } 604 } 605 606 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 607 ArrayRef<uint8_t> Bytes, 608 uint64_t Address, 609 raw_ostream &CS) const { 610 if (STI.getFeatureBits()[ARM::ModeThumb]) 611 return getThumbInstruction(MI, Size, Bytes, Address, CS); 612 return getARMInstruction(MI, Size, Bytes, Address, CS); 613 } 614 615 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 616 ArrayRef<uint8_t> Bytes, 617 uint64_t Address, 618 raw_ostream &CS) const { 619 CommentStream = &CS; 620 621 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 622 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 623 "mode!"); 624 625 // We want to read exactly 4 bytes of data. 626 if (Bytes.size() < 4) { 627 Size = 0; 628 return MCDisassembler::Fail; 629 } 630 631 // Encoded as a small-endian 32-bit word in the stream. 632 uint32_t Insn = 633 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 634 635 // Calling the auto-generated decoder function. 636 DecodeStatus Result = 637 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 638 if (Result != MCDisassembler::Fail) { 639 Size = 4; 640 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 641 } 642 643 struct DecodeTable { 644 const uint8_t *P; 645 bool DecodePred; 646 }; 647 648 const DecodeTable Tables[] = { 649 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 650 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 651 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 652 {DecoderTablev8Crypto32, false}, 653 }; 654 655 for (auto Table : Tables) { 656 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 657 if (Result != MCDisassembler::Fail) { 658 Size = 4; 659 // Add a fake predicate operand, because we share these instruction 660 // definitions with Thumb2 where these instructions are predicable. 661 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 662 return MCDisassembler::Fail; 663 return Result; 664 } 665 } 666 667 Result = 668 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 669 if (Result != MCDisassembler::Fail) { 670 Size = 4; 671 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 672 } 673 674 Size = 4; 675 return MCDisassembler::Fail; 676 } 677 678 namespace llvm { 679 680 extern const MCInstrDesc ARMInsts[]; 681 682 } // end namespace llvm 683 684 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 685 /// immediate Value in the MCInst. The immediate Value has had any PC 686 /// adjustment made by the caller. If the instruction is a branch instruction 687 /// then isBranch is true, else false. If the getOpInfo() function was set as 688 /// part of the setupForSymbolicDisassembly() call then that function is called 689 /// to get any symbolic information at the Address for this instruction. If 690 /// that returns non-zero then the symbolic information it returns is used to 691 /// create an MCExpr and that is added as an operand to the MCInst. If 692 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 693 /// Value is done and if a symbol is found an MCExpr is created with that, else 694 /// an MCExpr with Value is created. This function returns true if it adds an 695 /// operand to the MCInst and false otherwise. 696 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 697 bool isBranch, uint64_t InstSize, 698 MCInst &MI, const void *Decoder) { 699 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 700 // FIXME: Does it make sense for value to be negative? 701 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 702 /* Offset */ 0, InstSize); 703 } 704 705 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 706 /// referenced by a load instruction with the base register that is the Pc. 707 /// These can often be values in a literal pool near the Address of the 708 /// instruction. The Address of the instruction and its immediate Value are 709 /// used as a possible literal pool entry. The SymbolLookUp call back will 710 /// return the name of a symbol referenced by the literal pool's entry if 711 /// the referenced address is that of a symbol. Or it will return a pointer to 712 /// a literal 'C' string if the referenced address of the literal pool's entry 713 /// is an address into a section with 'C' string literals. 714 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 715 const void *Decoder) { 716 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 717 Dis->tryAddingPcLoadReferenceComment(Value, Address); 718 } 719 720 // Thumb1 instructions don't have explicit S bits. Rather, they 721 // implicitly set CPSR. Since it's not represented in the encoding, the 722 // auto-generated decoder won't inject the CPSR operand. We need to fix 723 // that as a post-pass. 724 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 725 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 726 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 727 MCInst::iterator I = MI.begin(); 728 for (unsigned i = 0; i < NumOps; ++i, ++I) { 729 if (I == MI.end()) break; 730 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 731 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 732 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 733 return; 734 } 735 } 736 737 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 738 } 739 740 static bool isVectorPredicable(unsigned Opcode) { 741 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 742 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 743 for (unsigned i = 0; i < NumOps; ++i) { 744 if (ARM::isVpred(OpInfo[i].OperandType)) 745 return true; 746 } 747 return false; 748 } 749 750 // Most Thumb instructions don't have explicit predicates in the 751 // encoding, but rather get their predicates from IT context. We need 752 // to fix up the predicate operands using this context information as a 753 // post-pass. 754 MCDisassembler::DecodeStatus 755 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 756 MCDisassembler::DecodeStatus S = Success; 757 758 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 759 760 // A few instructions actually have predicates encoded in them. Don't 761 // try to overwrite it if we're seeing one of those. 762 switch (MI.getOpcode()) { 763 case ARM::tBcc: 764 case ARM::t2Bcc: 765 case ARM::tCBZ: 766 case ARM::tCBNZ: 767 case ARM::tCPS: 768 case ARM::t2CPS3p: 769 case ARM::t2CPS2p: 770 case ARM::t2CPS1p: 771 case ARM::t2CSEL: 772 case ARM::t2CSINC: 773 case ARM::t2CSINV: 774 case ARM::t2CSNEG: 775 case ARM::tMOVSr: 776 case ARM::tSETEND: 777 // Some instructions (mostly conditional branches) are not 778 // allowed in IT blocks. 779 if (ITBlock.instrInITBlock()) 780 S = SoftFail; 781 else 782 return Success; 783 break; 784 case ARM::t2HINT: 785 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 786 S = SoftFail; 787 break; 788 case ARM::tB: 789 case ARM::t2B: 790 case ARM::t2TBB: 791 case ARM::t2TBH: 792 // Some instructions (mostly unconditional branches) can 793 // only appears at the end of, or outside of, an IT. 794 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 795 S = SoftFail; 796 break; 797 default: 798 break; 799 } 800 801 // Warn on non-VPT predicable instruction in a VPT block and a VPT 802 // predicable instruction in an IT block 803 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 804 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 805 S = SoftFail; 806 807 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 808 // assume a predicate of AL. 809 unsigned CC = ARMCC::AL; 810 unsigned VCC = ARMVCC::None; 811 if (ITBlock.instrInITBlock()) { 812 CC = ITBlock.getITCC(); 813 ITBlock.advanceITState(); 814 } else if (VPTBlock.instrInVPTBlock()) { 815 VCC = VPTBlock.getVPTPred(); 816 VPTBlock.advanceVPTState(); 817 } 818 819 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 820 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 821 822 MCInst::iterator CCI = MI.begin(); 823 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 824 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 825 } 826 827 if (ARMInsts[MI.getOpcode()].isPredicable()) { 828 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 829 ++CCI; 830 if (CC == ARMCC::AL) 831 MI.insert(CCI, MCOperand::createReg(0)); 832 else 833 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 834 } else if (CC != ARMCC::AL) { 835 Check(S, SoftFail); 836 } 837 838 MCInst::iterator VCCI = MI.begin(); 839 unsigned VCCPos; 840 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 841 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 842 } 843 844 if (isVectorPredicable(MI.getOpcode())) { 845 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 846 ++VCCI; 847 if (VCC == ARMVCC::None) 848 MI.insert(VCCI, MCOperand::createReg(0)); 849 else 850 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 851 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 852 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 853 VCCPos + 2, MCOI::TIED_TO); 854 assert(TiedOp >= 0 && 855 "Inactive register in vpred_r is not tied to an output!"); 856 MI.insert(VCCI, MI.getOperand(TiedOp)); 857 } 858 } else if (VCC != ARMVCC::None) { 859 Check(S, SoftFail); 860 } 861 862 return S; 863 } 864 865 // Thumb VFP instructions are a special case. Because we share their 866 // encodings between ARM and Thumb modes, and they are predicable in ARM 867 // mode, the auto-generated decoder will give them an (incorrect) 868 // predicate operand. We need to rewrite these operands based on the IT 869 // context as a post-pass. 870 void ARMDisassembler::UpdateThumbVFPPredicate( 871 DecodeStatus &S, MCInst &MI) const { 872 unsigned CC; 873 CC = ITBlock.getITCC(); 874 if (CC == 0xF) 875 CC = ARMCC::AL; 876 if (ITBlock.instrInITBlock()) 877 ITBlock.advanceITState(); 878 else if (VPTBlock.instrInVPTBlock()) { 879 CC = VPTBlock.getVPTPred(); 880 VPTBlock.advanceVPTState(); 881 } 882 883 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 884 MCInst::iterator I = MI.begin(); 885 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 886 for (unsigned i = 0; i < NumOps; ++i, ++I) { 887 if (OpInfo[i].isPredicate() ) { 888 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 889 Check(S, SoftFail); 890 I->setImm(CC); 891 ++I; 892 if (CC == ARMCC::AL) 893 I->setReg(0); 894 else 895 I->setReg(ARM::CPSR); 896 return; 897 } 898 } 899 } 900 901 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 902 ArrayRef<uint8_t> Bytes, 903 uint64_t Address, 904 raw_ostream &CS) const { 905 CommentStream = &CS; 906 907 assert(STI.getFeatureBits()[ARM::ModeThumb] && 908 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 909 910 // We want to read exactly 2 bytes of data. 911 if (Bytes.size() < 2) { 912 Size = 0; 913 return MCDisassembler::Fail; 914 } 915 916 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 917 DecodeStatus Result = 918 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 919 if (Result != MCDisassembler::Fail) { 920 Size = 2; 921 Check(Result, AddThumbPredicate(MI)); 922 return Result; 923 } 924 925 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 926 STI); 927 if (Result) { 928 Size = 2; 929 bool InITBlock = ITBlock.instrInITBlock(); 930 Check(Result, AddThumbPredicate(MI)); 931 AddThumb1SBit(MI, InITBlock); 932 return Result; 933 } 934 935 Result = 936 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 937 if (Result != MCDisassembler::Fail) { 938 Size = 2; 939 940 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 941 // the Thumb predicate. 942 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 943 Result = MCDisassembler::SoftFail; 944 945 Check(Result, AddThumbPredicate(MI)); 946 947 // If we find an IT instruction, we need to parse its condition 948 // code and mask operands so that we can apply them correctly 949 // to the subsequent instructions. 950 if (MI.getOpcode() == ARM::t2IT) { 951 unsigned Firstcond = MI.getOperand(0).getImm(); 952 unsigned Mask = MI.getOperand(1).getImm(); 953 ITBlock.setITState(Firstcond, Mask); 954 955 // An IT instruction that would give a 'NV' predicate is unpredictable. 956 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 957 CS << "unpredictable IT predicate sequence"; 958 } 959 960 return Result; 961 } 962 963 // We want to read exactly 4 bytes of data. 964 if (Bytes.size() < 4) { 965 Size = 0; 966 return MCDisassembler::Fail; 967 } 968 969 uint32_t Insn32 = 970 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 971 972 Result = 973 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 974 if (Result != MCDisassembler::Fail) { 975 Size = 4; 976 977 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 978 // the VPT predicate. 979 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 980 Result = MCDisassembler::SoftFail; 981 982 Check(Result, AddThumbPredicate(MI)); 983 984 if (isVPTOpcode(MI.getOpcode())) { 985 unsigned Mask = MI.getOperand(0).getImm(); 986 VPTBlock.setVPTState(Mask); 987 } 988 989 return Result; 990 } 991 992 Result = 993 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 994 if (Result != MCDisassembler::Fail) { 995 Size = 4; 996 bool InITBlock = ITBlock.instrInITBlock(); 997 Check(Result, AddThumbPredicate(MI)); 998 AddThumb1SBit(MI, InITBlock); 999 return Result; 1000 } 1001 1002 Result = 1003 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1004 if (Result != MCDisassembler::Fail) { 1005 Size = 4; 1006 Check(Result, AddThumbPredicate(MI)); 1007 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1008 } 1009 1010 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1011 Result = 1012 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1013 if (Result != MCDisassembler::Fail) { 1014 Size = 4; 1015 UpdateThumbVFPPredicate(Result, MI); 1016 return Result; 1017 } 1018 } 1019 1020 Result = 1021 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1022 if (Result != MCDisassembler::Fail) { 1023 Size = 4; 1024 return Result; 1025 } 1026 1027 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1028 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1029 STI); 1030 if (Result != MCDisassembler::Fail) { 1031 Size = 4; 1032 Check(Result, AddThumbPredicate(MI)); 1033 return Result; 1034 } 1035 } 1036 1037 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1038 uint32_t NEONLdStInsn = Insn32; 1039 NEONLdStInsn &= 0xF0FFFFFF; 1040 NEONLdStInsn |= 0x04000000; 1041 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1042 Address, this, STI); 1043 if (Result != MCDisassembler::Fail) { 1044 Size = 4; 1045 Check(Result, AddThumbPredicate(MI)); 1046 return Result; 1047 } 1048 } 1049 1050 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1051 uint32_t NEONDataInsn = Insn32; 1052 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1053 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1054 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1055 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1056 Address, this, STI); 1057 if (Result != MCDisassembler::Fail) { 1058 Size = 4; 1059 Check(Result, AddThumbPredicate(MI)); 1060 return Result; 1061 } 1062 1063 uint32_t NEONCryptoInsn = Insn32; 1064 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1065 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1066 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1067 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1068 Address, this, STI); 1069 if (Result != MCDisassembler::Fail) { 1070 Size = 4; 1071 return Result; 1072 } 1073 1074 uint32_t NEONv8Insn = Insn32; 1075 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1076 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1077 this, STI); 1078 if (Result != MCDisassembler::Fail) { 1079 Size = 4; 1080 return Result; 1081 } 1082 } 1083 1084 Result = 1085 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1086 if (Result != MCDisassembler::Fail) { 1087 Size = 4; 1088 Check(Result, AddThumbPredicate(MI)); 1089 return Result; 1090 } 1091 1092 Size = 0; 1093 return MCDisassembler::Fail; 1094 } 1095 1096 extern "C" void LLVMInitializeARMDisassembler() { 1097 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1098 createARMDisassembler); 1099 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1100 createARMDisassembler); 1101 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1102 createARMDisassembler); 1103 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1104 createARMDisassembler); 1105 } 1106 1107 static const uint16_t GPRDecoderTable[] = { 1108 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1109 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1110 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1111 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1112 }; 1113 1114 static const uint16_t CLRMGPRDecoderTable[] = { 1115 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1116 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1117 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1118 ARM::R12, 0, ARM::LR, ARM::APSR 1119 }; 1120 1121 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1122 uint64_t Address, const void *Decoder) { 1123 if (RegNo > 15) 1124 return MCDisassembler::Fail; 1125 1126 unsigned Register = GPRDecoderTable[RegNo]; 1127 Inst.addOperand(MCOperand::createReg(Register)); 1128 return MCDisassembler::Success; 1129 } 1130 1131 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1132 uint64_t Address, 1133 const void *Decoder) { 1134 if (RegNo > 15) 1135 return MCDisassembler::Fail; 1136 1137 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1138 if (Register == 0) 1139 return MCDisassembler::Fail; 1140 1141 Inst.addOperand(MCOperand::createReg(Register)); 1142 return MCDisassembler::Success; 1143 } 1144 1145 static DecodeStatus 1146 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1147 uint64_t Address, const void *Decoder) { 1148 DecodeStatus S = MCDisassembler::Success; 1149 1150 if (RegNo == 15) 1151 S = MCDisassembler::SoftFail; 1152 1153 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1154 1155 return S; 1156 } 1157 1158 static DecodeStatus 1159 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1160 uint64_t Address, const void *Decoder) { 1161 DecodeStatus S = MCDisassembler::Success; 1162 1163 if (RegNo == 15) 1164 { 1165 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1166 return MCDisassembler::Success; 1167 } 1168 1169 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1170 return S; 1171 } 1172 1173 static DecodeStatus 1174 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1175 uint64_t Address, const void *Decoder) { 1176 DecodeStatus S = MCDisassembler::Success; 1177 1178 if (RegNo == 15) 1179 { 1180 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1181 return MCDisassembler::Success; 1182 } 1183 1184 if (RegNo == 13) 1185 Check(S, MCDisassembler::SoftFail); 1186 1187 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1188 return S; 1189 } 1190 1191 static DecodeStatus 1192 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1193 uint64_t Address, const void *Decoder) { 1194 DecodeStatus S = MCDisassembler::Success; 1195 if (RegNo == 13) 1196 return MCDisassembler::Fail; 1197 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1198 return S; 1199 } 1200 1201 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1202 uint64_t Address, const void *Decoder) { 1203 if (RegNo > 7) 1204 return MCDisassembler::Fail; 1205 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1206 } 1207 1208 static const uint16_t GPRPairDecoderTable[] = { 1209 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1210 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1211 }; 1212 1213 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1214 uint64_t Address, const void *Decoder) { 1215 DecodeStatus S = MCDisassembler::Success; 1216 1217 if (RegNo > 13) 1218 return MCDisassembler::Fail; 1219 1220 if ((RegNo & 1) || RegNo == 0xe) 1221 S = MCDisassembler::SoftFail; 1222 1223 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1224 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1225 return S; 1226 } 1227 1228 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1229 uint64_t Address, const void *Decoder) { 1230 unsigned Register = 0; 1231 switch (RegNo) { 1232 case 0: 1233 Register = ARM::R0; 1234 break; 1235 case 1: 1236 Register = ARM::R1; 1237 break; 1238 case 2: 1239 Register = ARM::R2; 1240 break; 1241 case 3: 1242 Register = ARM::R3; 1243 break; 1244 case 9: 1245 Register = ARM::R9; 1246 break; 1247 case 12: 1248 Register = ARM::R12; 1249 break; 1250 default: 1251 return MCDisassembler::Fail; 1252 } 1253 1254 Inst.addOperand(MCOperand::createReg(Register)); 1255 return MCDisassembler::Success; 1256 } 1257 1258 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1259 uint64_t Address, const void *Decoder) { 1260 DecodeStatus S = MCDisassembler::Success; 1261 1262 const FeatureBitset &featureBits = 1263 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1264 1265 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1266 S = MCDisassembler::SoftFail; 1267 1268 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1269 return S; 1270 } 1271 1272 static const uint16_t SPRDecoderTable[] = { 1273 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1274 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1275 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1276 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1277 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1278 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1279 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1280 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1281 }; 1282 1283 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1284 uint64_t Address, const void *Decoder) { 1285 if (RegNo > 31) 1286 return MCDisassembler::Fail; 1287 1288 unsigned Register = SPRDecoderTable[RegNo]; 1289 Inst.addOperand(MCOperand::createReg(Register)); 1290 return MCDisassembler::Success; 1291 } 1292 1293 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1294 uint64_t Address, const void *Decoder) { 1295 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1296 } 1297 1298 static const uint16_t DPRDecoderTable[] = { 1299 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1300 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1301 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1302 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1303 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1304 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1305 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1306 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1307 }; 1308 1309 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1310 uint64_t Address, const void *Decoder) { 1311 const FeatureBitset &featureBits = 1312 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1313 1314 bool hasD32 = featureBits[ARM::FeatureD32]; 1315 1316 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1317 return MCDisassembler::Fail; 1318 1319 unsigned Register = DPRDecoderTable[RegNo]; 1320 Inst.addOperand(MCOperand::createReg(Register)); 1321 return MCDisassembler::Success; 1322 } 1323 1324 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1325 uint64_t Address, const void *Decoder) { 1326 if (RegNo > 7) 1327 return MCDisassembler::Fail; 1328 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1329 } 1330 1331 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1332 uint64_t Address, const void *Decoder) { 1333 if (RegNo > 15) 1334 return MCDisassembler::Fail; 1335 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1336 } 1337 1338 static DecodeStatus 1339 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1340 uint64_t Address, const void *Decoder) { 1341 if (RegNo > 15) 1342 return MCDisassembler::Fail; 1343 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1344 } 1345 1346 static const uint16_t QPRDecoderTable[] = { 1347 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1348 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1349 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1350 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1351 }; 1352 1353 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1354 uint64_t Address, const void *Decoder) { 1355 if (RegNo > 31 || (RegNo & 1) != 0) 1356 return MCDisassembler::Fail; 1357 RegNo >>= 1; 1358 1359 unsigned Register = QPRDecoderTable[RegNo]; 1360 Inst.addOperand(MCOperand::createReg(Register)); 1361 return MCDisassembler::Success; 1362 } 1363 1364 static const uint16_t DPairDecoderTable[] = { 1365 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1366 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1367 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1368 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1369 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1370 ARM::Q15 1371 }; 1372 1373 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1374 uint64_t Address, const void *Decoder) { 1375 if (RegNo > 30) 1376 return MCDisassembler::Fail; 1377 1378 unsigned Register = DPairDecoderTable[RegNo]; 1379 Inst.addOperand(MCOperand::createReg(Register)); 1380 return MCDisassembler::Success; 1381 } 1382 1383 static const uint16_t DPairSpacedDecoderTable[] = { 1384 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1385 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1386 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1387 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1388 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1389 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1390 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1391 ARM::D28_D30, ARM::D29_D31 1392 }; 1393 1394 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1395 unsigned RegNo, 1396 uint64_t Address, 1397 const void *Decoder) { 1398 if (RegNo > 29) 1399 return MCDisassembler::Fail; 1400 1401 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1402 Inst.addOperand(MCOperand::createReg(Register)); 1403 return MCDisassembler::Success; 1404 } 1405 1406 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1407 uint64_t Address, const void *Decoder) { 1408 DecodeStatus S = MCDisassembler::Success; 1409 if (Val == 0xF) return MCDisassembler::Fail; 1410 // AL predicate is not allowed on Thumb1 branches. 1411 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1412 return MCDisassembler::Fail; 1413 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1414 Check(S, MCDisassembler::SoftFail); 1415 Inst.addOperand(MCOperand::createImm(Val)); 1416 if (Val == ARMCC::AL) { 1417 Inst.addOperand(MCOperand::createReg(0)); 1418 } else 1419 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1420 return S; 1421 } 1422 1423 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1424 uint64_t Address, const void *Decoder) { 1425 if (Val) 1426 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1427 else 1428 Inst.addOperand(MCOperand::createReg(0)); 1429 return MCDisassembler::Success; 1430 } 1431 1432 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1433 uint64_t Address, const void *Decoder) { 1434 DecodeStatus S = MCDisassembler::Success; 1435 1436 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1437 unsigned type = fieldFromInstruction(Val, 5, 2); 1438 unsigned imm = fieldFromInstruction(Val, 7, 5); 1439 1440 // Register-immediate 1441 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1442 return MCDisassembler::Fail; 1443 1444 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1445 switch (type) { 1446 case 0: 1447 Shift = ARM_AM::lsl; 1448 break; 1449 case 1: 1450 Shift = ARM_AM::lsr; 1451 break; 1452 case 2: 1453 Shift = ARM_AM::asr; 1454 break; 1455 case 3: 1456 Shift = ARM_AM::ror; 1457 break; 1458 } 1459 1460 if (Shift == ARM_AM::ror && imm == 0) 1461 Shift = ARM_AM::rrx; 1462 1463 unsigned Op = Shift | (imm << 3); 1464 Inst.addOperand(MCOperand::createImm(Op)); 1465 1466 return S; 1467 } 1468 1469 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1470 uint64_t Address, const void *Decoder) { 1471 DecodeStatus S = MCDisassembler::Success; 1472 1473 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1474 unsigned type = fieldFromInstruction(Val, 5, 2); 1475 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1476 1477 // Register-register 1478 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1479 return MCDisassembler::Fail; 1480 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1481 return MCDisassembler::Fail; 1482 1483 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1484 switch (type) { 1485 case 0: 1486 Shift = ARM_AM::lsl; 1487 break; 1488 case 1: 1489 Shift = ARM_AM::lsr; 1490 break; 1491 case 2: 1492 Shift = ARM_AM::asr; 1493 break; 1494 case 3: 1495 Shift = ARM_AM::ror; 1496 break; 1497 } 1498 1499 Inst.addOperand(MCOperand::createImm(Shift)); 1500 1501 return S; 1502 } 1503 1504 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1505 uint64_t Address, const void *Decoder) { 1506 DecodeStatus S = MCDisassembler::Success; 1507 1508 bool NeedDisjointWriteback = false; 1509 unsigned WritebackReg = 0; 1510 bool CLRM = false; 1511 switch (Inst.getOpcode()) { 1512 default: 1513 break; 1514 case ARM::LDMIA_UPD: 1515 case ARM::LDMDB_UPD: 1516 case ARM::LDMIB_UPD: 1517 case ARM::LDMDA_UPD: 1518 case ARM::t2LDMIA_UPD: 1519 case ARM::t2LDMDB_UPD: 1520 case ARM::t2STMIA_UPD: 1521 case ARM::t2STMDB_UPD: 1522 NeedDisjointWriteback = true; 1523 WritebackReg = Inst.getOperand(0).getReg(); 1524 break; 1525 case ARM::t2CLRM: 1526 CLRM = true; 1527 break; 1528 } 1529 1530 // Empty register lists are not allowed. 1531 if (Val == 0) return MCDisassembler::Fail; 1532 for (unsigned i = 0; i < 16; ++i) { 1533 if (Val & (1 << i)) { 1534 if (CLRM) { 1535 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1536 return MCDisassembler::Fail; 1537 } 1538 } else { 1539 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1540 return MCDisassembler::Fail; 1541 // Writeback not allowed if Rn is in the target list. 1542 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1543 Check(S, MCDisassembler::SoftFail); 1544 } 1545 } 1546 } 1547 1548 return S; 1549 } 1550 1551 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1552 uint64_t Address, const void *Decoder) { 1553 DecodeStatus S = MCDisassembler::Success; 1554 1555 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1556 unsigned regs = fieldFromInstruction(Val, 0, 8); 1557 1558 // In case of unpredictable encoding, tweak the operands. 1559 if (regs == 0 || (Vd + regs) > 32) { 1560 regs = Vd + regs > 32 ? 32 - Vd : regs; 1561 regs = std::max( 1u, regs); 1562 S = MCDisassembler::SoftFail; 1563 } 1564 1565 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1566 return MCDisassembler::Fail; 1567 for (unsigned i = 0; i < (regs - 1); ++i) { 1568 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1569 return MCDisassembler::Fail; 1570 } 1571 1572 return S; 1573 } 1574 1575 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1576 uint64_t Address, const void *Decoder) { 1577 DecodeStatus S = MCDisassembler::Success; 1578 1579 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1580 unsigned regs = fieldFromInstruction(Val, 1, 7); 1581 1582 // In case of unpredictable encoding, tweak the operands. 1583 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1584 regs = Vd + regs > 32 ? 32 - Vd : regs; 1585 regs = std::max( 1u, regs); 1586 regs = std::min(16u, regs); 1587 S = MCDisassembler::SoftFail; 1588 } 1589 1590 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1591 return MCDisassembler::Fail; 1592 for (unsigned i = 0; i < (regs - 1); ++i) { 1593 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1594 return MCDisassembler::Fail; 1595 } 1596 1597 return S; 1598 } 1599 1600 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1601 uint64_t Address, const void *Decoder) { 1602 // This operand encodes a mask of contiguous zeros between a specified MSB 1603 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1604 // the mask of all bits LSB-and-lower, and then xor them to create 1605 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1606 // create the final mask. 1607 unsigned msb = fieldFromInstruction(Val, 5, 5); 1608 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1609 1610 DecodeStatus S = MCDisassembler::Success; 1611 if (lsb > msb) { 1612 Check(S, MCDisassembler::SoftFail); 1613 // The check above will cause the warning for the "potentially undefined 1614 // instruction encoding" but we can't build a bad MCOperand value here 1615 // with a lsb > msb or else printing the MCInst will cause a crash. 1616 lsb = msb; 1617 } 1618 1619 uint32_t msb_mask = 0xFFFFFFFF; 1620 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1621 uint32_t lsb_mask = (1U << lsb) - 1; 1622 1623 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1624 return S; 1625 } 1626 1627 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1628 uint64_t Address, const void *Decoder) { 1629 DecodeStatus S = MCDisassembler::Success; 1630 1631 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1632 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1633 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1634 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1635 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1636 unsigned U = fieldFromInstruction(Insn, 23, 1); 1637 const FeatureBitset &featureBits = 1638 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1639 1640 switch (Inst.getOpcode()) { 1641 case ARM::LDC_OFFSET: 1642 case ARM::LDC_PRE: 1643 case ARM::LDC_POST: 1644 case ARM::LDC_OPTION: 1645 case ARM::LDCL_OFFSET: 1646 case ARM::LDCL_PRE: 1647 case ARM::LDCL_POST: 1648 case ARM::LDCL_OPTION: 1649 case ARM::STC_OFFSET: 1650 case ARM::STC_PRE: 1651 case ARM::STC_POST: 1652 case ARM::STC_OPTION: 1653 case ARM::STCL_OFFSET: 1654 case ARM::STCL_PRE: 1655 case ARM::STCL_POST: 1656 case ARM::STCL_OPTION: 1657 case ARM::t2LDC_OFFSET: 1658 case ARM::t2LDC_PRE: 1659 case ARM::t2LDC_POST: 1660 case ARM::t2LDC_OPTION: 1661 case ARM::t2LDCL_OFFSET: 1662 case ARM::t2LDCL_PRE: 1663 case ARM::t2LDCL_POST: 1664 case ARM::t2LDCL_OPTION: 1665 case ARM::t2STC_OFFSET: 1666 case ARM::t2STC_PRE: 1667 case ARM::t2STC_POST: 1668 case ARM::t2STC_OPTION: 1669 case ARM::t2STCL_OFFSET: 1670 case ARM::t2STCL_PRE: 1671 case ARM::t2STCL_POST: 1672 case ARM::t2STCL_OPTION: 1673 case ARM::t2LDC2_OFFSET: 1674 case ARM::t2LDC2L_OFFSET: 1675 case ARM::t2LDC2_PRE: 1676 case ARM::t2LDC2L_PRE: 1677 case ARM::t2STC2_OFFSET: 1678 case ARM::t2STC2L_OFFSET: 1679 case ARM::t2STC2_PRE: 1680 case ARM::t2STC2L_PRE: 1681 case ARM::LDC2_OFFSET: 1682 case ARM::LDC2L_OFFSET: 1683 case ARM::LDC2_PRE: 1684 case ARM::LDC2L_PRE: 1685 case ARM::STC2_OFFSET: 1686 case ARM::STC2L_OFFSET: 1687 case ARM::STC2_PRE: 1688 case ARM::STC2L_PRE: 1689 case ARM::t2LDC2_OPTION: 1690 case ARM::t2STC2_OPTION: 1691 case ARM::t2LDC2_POST: 1692 case ARM::t2LDC2L_POST: 1693 case ARM::t2STC2_POST: 1694 case ARM::t2STC2L_POST: 1695 case ARM::LDC2_POST: 1696 case ARM::LDC2L_POST: 1697 case ARM::STC2_POST: 1698 case ARM::STC2L_POST: 1699 if (coproc == 0xA || coproc == 0xB || 1700 (featureBits[ARM::HasV8_1MMainlineOps] && 1701 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1702 coproc == 0xE || coproc == 0xF))) 1703 return MCDisassembler::Fail; 1704 break; 1705 default: 1706 break; 1707 } 1708 1709 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1710 return MCDisassembler::Fail; 1711 1712 Inst.addOperand(MCOperand::createImm(coproc)); 1713 Inst.addOperand(MCOperand::createImm(CRd)); 1714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1715 return MCDisassembler::Fail; 1716 1717 switch (Inst.getOpcode()) { 1718 case ARM::t2LDC2_OFFSET: 1719 case ARM::t2LDC2L_OFFSET: 1720 case ARM::t2LDC2_PRE: 1721 case ARM::t2LDC2L_PRE: 1722 case ARM::t2STC2_OFFSET: 1723 case ARM::t2STC2L_OFFSET: 1724 case ARM::t2STC2_PRE: 1725 case ARM::t2STC2L_PRE: 1726 case ARM::LDC2_OFFSET: 1727 case ARM::LDC2L_OFFSET: 1728 case ARM::LDC2_PRE: 1729 case ARM::LDC2L_PRE: 1730 case ARM::STC2_OFFSET: 1731 case ARM::STC2L_OFFSET: 1732 case ARM::STC2_PRE: 1733 case ARM::STC2L_PRE: 1734 case ARM::t2LDC_OFFSET: 1735 case ARM::t2LDCL_OFFSET: 1736 case ARM::t2LDC_PRE: 1737 case ARM::t2LDCL_PRE: 1738 case ARM::t2STC_OFFSET: 1739 case ARM::t2STCL_OFFSET: 1740 case ARM::t2STC_PRE: 1741 case ARM::t2STCL_PRE: 1742 case ARM::LDC_OFFSET: 1743 case ARM::LDCL_OFFSET: 1744 case ARM::LDC_PRE: 1745 case ARM::LDCL_PRE: 1746 case ARM::STC_OFFSET: 1747 case ARM::STCL_OFFSET: 1748 case ARM::STC_PRE: 1749 case ARM::STCL_PRE: 1750 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1751 Inst.addOperand(MCOperand::createImm(imm)); 1752 break; 1753 case ARM::t2LDC2_POST: 1754 case ARM::t2LDC2L_POST: 1755 case ARM::t2STC2_POST: 1756 case ARM::t2STC2L_POST: 1757 case ARM::LDC2_POST: 1758 case ARM::LDC2L_POST: 1759 case ARM::STC2_POST: 1760 case ARM::STC2L_POST: 1761 case ARM::t2LDC_POST: 1762 case ARM::t2LDCL_POST: 1763 case ARM::t2STC_POST: 1764 case ARM::t2STCL_POST: 1765 case ARM::LDC_POST: 1766 case ARM::LDCL_POST: 1767 case ARM::STC_POST: 1768 case ARM::STCL_POST: 1769 imm |= U << 8; 1770 LLVM_FALLTHROUGH; 1771 default: 1772 // The 'option' variant doesn't encode 'U' in the immediate since 1773 // the immediate is unsigned [0,255]. 1774 Inst.addOperand(MCOperand::createImm(imm)); 1775 break; 1776 } 1777 1778 switch (Inst.getOpcode()) { 1779 case ARM::LDC_OFFSET: 1780 case ARM::LDC_PRE: 1781 case ARM::LDC_POST: 1782 case ARM::LDC_OPTION: 1783 case ARM::LDCL_OFFSET: 1784 case ARM::LDCL_PRE: 1785 case ARM::LDCL_POST: 1786 case ARM::LDCL_OPTION: 1787 case ARM::STC_OFFSET: 1788 case ARM::STC_PRE: 1789 case ARM::STC_POST: 1790 case ARM::STC_OPTION: 1791 case ARM::STCL_OFFSET: 1792 case ARM::STCL_PRE: 1793 case ARM::STCL_POST: 1794 case ARM::STCL_OPTION: 1795 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1796 return MCDisassembler::Fail; 1797 break; 1798 default: 1799 break; 1800 } 1801 1802 return S; 1803 } 1804 1805 static DecodeStatus 1806 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1807 uint64_t Address, const void *Decoder) { 1808 DecodeStatus S = MCDisassembler::Success; 1809 1810 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1811 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1812 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1813 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1814 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1815 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1816 unsigned P = fieldFromInstruction(Insn, 24, 1); 1817 unsigned W = fieldFromInstruction(Insn, 21, 1); 1818 1819 // On stores, the writeback operand precedes Rt. 1820 switch (Inst.getOpcode()) { 1821 case ARM::STR_POST_IMM: 1822 case ARM::STR_POST_REG: 1823 case ARM::STRB_POST_IMM: 1824 case ARM::STRB_POST_REG: 1825 case ARM::STRT_POST_REG: 1826 case ARM::STRT_POST_IMM: 1827 case ARM::STRBT_POST_REG: 1828 case ARM::STRBT_POST_IMM: 1829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1830 return MCDisassembler::Fail; 1831 break; 1832 default: 1833 break; 1834 } 1835 1836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1837 return MCDisassembler::Fail; 1838 1839 // On loads, the writeback operand comes after Rt. 1840 switch (Inst.getOpcode()) { 1841 case ARM::LDR_POST_IMM: 1842 case ARM::LDR_POST_REG: 1843 case ARM::LDRB_POST_IMM: 1844 case ARM::LDRB_POST_REG: 1845 case ARM::LDRBT_POST_REG: 1846 case ARM::LDRBT_POST_IMM: 1847 case ARM::LDRT_POST_REG: 1848 case ARM::LDRT_POST_IMM: 1849 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1850 return MCDisassembler::Fail; 1851 break; 1852 default: 1853 break; 1854 } 1855 1856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1857 return MCDisassembler::Fail; 1858 1859 ARM_AM::AddrOpc Op = ARM_AM::add; 1860 if (!fieldFromInstruction(Insn, 23, 1)) 1861 Op = ARM_AM::sub; 1862 1863 bool writeback = (P == 0) || (W == 1); 1864 unsigned idx_mode = 0; 1865 if (P && writeback) 1866 idx_mode = ARMII::IndexModePre; 1867 else if (!P && writeback) 1868 idx_mode = ARMII::IndexModePost; 1869 1870 if (writeback && (Rn == 15 || Rn == Rt)) 1871 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1872 1873 if (reg) { 1874 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1875 return MCDisassembler::Fail; 1876 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1877 switch( fieldFromInstruction(Insn, 5, 2)) { 1878 case 0: 1879 Opc = ARM_AM::lsl; 1880 break; 1881 case 1: 1882 Opc = ARM_AM::lsr; 1883 break; 1884 case 2: 1885 Opc = ARM_AM::asr; 1886 break; 1887 case 3: 1888 Opc = ARM_AM::ror; 1889 break; 1890 default: 1891 return MCDisassembler::Fail; 1892 } 1893 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1894 if (Opc == ARM_AM::ror && amt == 0) 1895 Opc = ARM_AM::rrx; 1896 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1897 1898 Inst.addOperand(MCOperand::createImm(imm)); 1899 } else { 1900 Inst.addOperand(MCOperand::createReg(0)); 1901 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1902 Inst.addOperand(MCOperand::createImm(tmp)); 1903 } 1904 1905 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1906 return MCDisassembler::Fail; 1907 1908 return S; 1909 } 1910 1911 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1912 uint64_t Address, const void *Decoder) { 1913 DecodeStatus S = MCDisassembler::Success; 1914 1915 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1916 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1917 unsigned type = fieldFromInstruction(Val, 5, 2); 1918 unsigned imm = fieldFromInstruction(Val, 7, 5); 1919 unsigned U = fieldFromInstruction(Val, 12, 1); 1920 1921 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1922 switch (type) { 1923 case 0: 1924 ShOp = ARM_AM::lsl; 1925 break; 1926 case 1: 1927 ShOp = ARM_AM::lsr; 1928 break; 1929 case 2: 1930 ShOp = ARM_AM::asr; 1931 break; 1932 case 3: 1933 ShOp = ARM_AM::ror; 1934 break; 1935 } 1936 1937 if (ShOp == ARM_AM::ror && imm == 0) 1938 ShOp = ARM_AM::rrx; 1939 1940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1941 return MCDisassembler::Fail; 1942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1943 return MCDisassembler::Fail; 1944 unsigned shift; 1945 if (U) 1946 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1947 else 1948 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1949 Inst.addOperand(MCOperand::createImm(shift)); 1950 1951 return S; 1952 } 1953 1954 static DecodeStatus 1955 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1956 uint64_t Address, const void *Decoder) { 1957 DecodeStatus S = MCDisassembler::Success; 1958 1959 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1960 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1961 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1962 unsigned type = fieldFromInstruction(Insn, 22, 1); 1963 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1964 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1965 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1966 unsigned W = fieldFromInstruction(Insn, 21, 1); 1967 unsigned P = fieldFromInstruction(Insn, 24, 1); 1968 unsigned Rt2 = Rt + 1; 1969 1970 bool writeback = (W == 1) | (P == 0); 1971 1972 // For {LD,ST}RD, Rt must be even, else undefined. 1973 switch (Inst.getOpcode()) { 1974 case ARM::STRD: 1975 case ARM::STRD_PRE: 1976 case ARM::STRD_POST: 1977 case ARM::LDRD: 1978 case ARM::LDRD_PRE: 1979 case ARM::LDRD_POST: 1980 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1981 break; 1982 default: 1983 break; 1984 } 1985 switch (Inst.getOpcode()) { 1986 case ARM::STRD: 1987 case ARM::STRD_PRE: 1988 case ARM::STRD_POST: 1989 if (P == 0 && W == 1) 1990 S = MCDisassembler::SoftFail; 1991 1992 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1993 S = MCDisassembler::SoftFail; 1994 if (type && Rm == 15) 1995 S = MCDisassembler::SoftFail; 1996 if (Rt2 == 15) 1997 S = MCDisassembler::SoftFail; 1998 if (!type && fieldFromInstruction(Insn, 8, 4)) 1999 S = MCDisassembler::SoftFail; 2000 break; 2001 case ARM::STRH: 2002 case ARM::STRH_PRE: 2003 case ARM::STRH_POST: 2004 if (Rt == 15) 2005 S = MCDisassembler::SoftFail; 2006 if (writeback && (Rn == 15 || Rn == Rt)) 2007 S = MCDisassembler::SoftFail; 2008 if (!type && Rm == 15) 2009 S = MCDisassembler::SoftFail; 2010 break; 2011 case ARM::LDRD: 2012 case ARM::LDRD_PRE: 2013 case ARM::LDRD_POST: 2014 if (type && Rn == 15) { 2015 if (Rt2 == 15) 2016 S = MCDisassembler::SoftFail; 2017 break; 2018 } 2019 if (P == 0 && W == 1) 2020 S = MCDisassembler::SoftFail; 2021 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2022 S = MCDisassembler::SoftFail; 2023 if (!type && writeback && Rn == 15) 2024 S = MCDisassembler::SoftFail; 2025 if (writeback && (Rn == Rt || Rn == Rt2)) 2026 S = MCDisassembler::SoftFail; 2027 break; 2028 case ARM::LDRH: 2029 case ARM::LDRH_PRE: 2030 case ARM::LDRH_POST: 2031 if (type && Rn == 15) { 2032 if (Rt == 15) 2033 S = MCDisassembler::SoftFail; 2034 break; 2035 } 2036 if (Rt == 15) 2037 S = MCDisassembler::SoftFail; 2038 if (!type && Rm == 15) 2039 S = MCDisassembler::SoftFail; 2040 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2041 S = MCDisassembler::SoftFail; 2042 break; 2043 case ARM::LDRSH: 2044 case ARM::LDRSH_PRE: 2045 case ARM::LDRSH_POST: 2046 case ARM::LDRSB: 2047 case ARM::LDRSB_PRE: 2048 case ARM::LDRSB_POST: 2049 if (type && Rn == 15) { 2050 if (Rt == 15) 2051 S = MCDisassembler::SoftFail; 2052 break; 2053 } 2054 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2055 S = MCDisassembler::SoftFail; 2056 if (!type && (Rt == 15 || Rm == 15)) 2057 S = MCDisassembler::SoftFail; 2058 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2059 S = MCDisassembler::SoftFail; 2060 break; 2061 default: 2062 break; 2063 } 2064 2065 if (writeback) { // Writeback 2066 if (P) 2067 U |= ARMII::IndexModePre << 9; 2068 else 2069 U |= ARMII::IndexModePost << 9; 2070 2071 // On stores, the writeback operand precedes Rt. 2072 switch (Inst.getOpcode()) { 2073 case ARM::STRD: 2074 case ARM::STRD_PRE: 2075 case ARM::STRD_POST: 2076 case ARM::STRH: 2077 case ARM::STRH_PRE: 2078 case ARM::STRH_POST: 2079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2080 return MCDisassembler::Fail; 2081 break; 2082 default: 2083 break; 2084 } 2085 } 2086 2087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2088 return MCDisassembler::Fail; 2089 switch (Inst.getOpcode()) { 2090 case ARM::STRD: 2091 case ARM::STRD_PRE: 2092 case ARM::STRD_POST: 2093 case ARM::LDRD: 2094 case ARM::LDRD_PRE: 2095 case ARM::LDRD_POST: 2096 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2097 return MCDisassembler::Fail; 2098 break; 2099 default: 2100 break; 2101 } 2102 2103 if (writeback) { 2104 // On loads, the writeback operand comes after Rt. 2105 switch (Inst.getOpcode()) { 2106 case ARM::LDRD: 2107 case ARM::LDRD_PRE: 2108 case ARM::LDRD_POST: 2109 case ARM::LDRH: 2110 case ARM::LDRH_PRE: 2111 case ARM::LDRH_POST: 2112 case ARM::LDRSH: 2113 case ARM::LDRSH_PRE: 2114 case ARM::LDRSH_POST: 2115 case ARM::LDRSB: 2116 case ARM::LDRSB_PRE: 2117 case ARM::LDRSB_POST: 2118 case ARM::LDRHTr: 2119 case ARM::LDRSBTr: 2120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2121 return MCDisassembler::Fail; 2122 break; 2123 default: 2124 break; 2125 } 2126 } 2127 2128 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2129 return MCDisassembler::Fail; 2130 2131 if (type) { 2132 Inst.addOperand(MCOperand::createReg(0)); 2133 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2134 } else { 2135 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2136 return MCDisassembler::Fail; 2137 Inst.addOperand(MCOperand::createImm(U)); 2138 } 2139 2140 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2141 return MCDisassembler::Fail; 2142 2143 return S; 2144 } 2145 2146 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2147 uint64_t Address, const void *Decoder) { 2148 DecodeStatus S = MCDisassembler::Success; 2149 2150 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2151 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2152 2153 switch (mode) { 2154 case 0: 2155 mode = ARM_AM::da; 2156 break; 2157 case 1: 2158 mode = ARM_AM::ia; 2159 break; 2160 case 2: 2161 mode = ARM_AM::db; 2162 break; 2163 case 3: 2164 mode = ARM_AM::ib; 2165 break; 2166 } 2167 2168 Inst.addOperand(MCOperand::createImm(mode)); 2169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2170 return MCDisassembler::Fail; 2171 2172 return S; 2173 } 2174 2175 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2176 uint64_t Address, const void *Decoder) { 2177 DecodeStatus S = MCDisassembler::Success; 2178 2179 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2180 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2181 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2182 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2183 2184 if (pred == 0xF) 2185 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2186 2187 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2188 return MCDisassembler::Fail; 2189 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2190 return MCDisassembler::Fail; 2191 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2192 return MCDisassembler::Fail; 2193 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2194 return MCDisassembler::Fail; 2195 return S; 2196 } 2197 2198 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2199 unsigned Insn, 2200 uint64_t Address, const void *Decoder) { 2201 DecodeStatus S = MCDisassembler::Success; 2202 2203 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2204 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2205 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2206 2207 if (pred == 0xF) { 2208 // Ambiguous with RFE and SRS 2209 switch (Inst.getOpcode()) { 2210 case ARM::LDMDA: 2211 Inst.setOpcode(ARM::RFEDA); 2212 break; 2213 case ARM::LDMDA_UPD: 2214 Inst.setOpcode(ARM::RFEDA_UPD); 2215 break; 2216 case ARM::LDMDB: 2217 Inst.setOpcode(ARM::RFEDB); 2218 break; 2219 case ARM::LDMDB_UPD: 2220 Inst.setOpcode(ARM::RFEDB_UPD); 2221 break; 2222 case ARM::LDMIA: 2223 Inst.setOpcode(ARM::RFEIA); 2224 break; 2225 case ARM::LDMIA_UPD: 2226 Inst.setOpcode(ARM::RFEIA_UPD); 2227 break; 2228 case ARM::LDMIB: 2229 Inst.setOpcode(ARM::RFEIB); 2230 break; 2231 case ARM::LDMIB_UPD: 2232 Inst.setOpcode(ARM::RFEIB_UPD); 2233 break; 2234 case ARM::STMDA: 2235 Inst.setOpcode(ARM::SRSDA); 2236 break; 2237 case ARM::STMDA_UPD: 2238 Inst.setOpcode(ARM::SRSDA_UPD); 2239 break; 2240 case ARM::STMDB: 2241 Inst.setOpcode(ARM::SRSDB); 2242 break; 2243 case ARM::STMDB_UPD: 2244 Inst.setOpcode(ARM::SRSDB_UPD); 2245 break; 2246 case ARM::STMIA: 2247 Inst.setOpcode(ARM::SRSIA); 2248 break; 2249 case ARM::STMIA_UPD: 2250 Inst.setOpcode(ARM::SRSIA_UPD); 2251 break; 2252 case ARM::STMIB: 2253 Inst.setOpcode(ARM::SRSIB); 2254 break; 2255 case ARM::STMIB_UPD: 2256 Inst.setOpcode(ARM::SRSIB_UPD); 2257 break; 2258 default: 2259 return MCDisassembler::Fail; 2260 } 2261 2262 // For stores (which become SRS's, the only operand is the mode. 2263 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2264 // Check SRS encoding constraints 2265 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2266 fieldFromInstruction(Insn, 20, 1) == 0)) 2267 return MCDisassembler::Fail; 2268 2269 Inst.addOperand( 2270 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2271 return S; 2272 } 2273 2274 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2275 } 2276 2277 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2278 return MCDisassembler::Fail; 2279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2280 return MCDisassembler::Fail; // Tied 2281 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2282 return MCDisassembler::Fail; 2283 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2284 return MCDisassembler::Fail; 2285 2286 return S; 2287 } 2288 2289 // Check for UNPREDICTABLE predicated ESB instruction 2290 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2291 uint64_t Address, const void *Decoder) { 2292 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2293 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2294 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2295 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2296 2297 DecodeStatus S = MCDisassembler::Success; 2298 2299 Inst.addOperand(MCOperand::createImm(imm8)); 2300 2301 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2302 return MCDisassembler::Fail; 2303 2304 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2305 // so all predicates should be allowed. 2306 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2307 S = MCDisassembler::SoftFail; 2308 2309 return S; 2310 } 2311 2312 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2313 uint64_t Address, const void *Decoder) { 2314 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2315 unsigned M = fieldFromInstruction(Insn, 17, 1); 2316 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2317 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2318 2319 DecodeStatus S = MCDisassembler::Success; 2320 2321 // This decoder is called from multiple location that do not check 2322 // the full encoding is valid before they do. 2323 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2324 fieldFromInstruction(Insn, 16, 1) != 0 || 2325 fieldFromInstruction(Insn, 20, 8) != 0x10) 2326 return MCDisassembler::Fail; 2327 2328 // imod == '01' --> UNPREDICTABLE 2329 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2330 // return failure here. The '01' imod value is unprintable, so there's 2331 // nothing useful we could do even if we returned UNPREDICTABLE. 2332 2333 if (imod == 1) return MCDisassembler::Fail; 2334 2335 if (imod && M) { 2336 Inst.setOpcode(ARM::CPS3p); 2337 Inst.addOperand(MCOperand::createImm(imod)); 2338 Inst.addOperand(MCOperand::createImm(iflags)); 2339 Inst.addOperand(MCOperand::createImm(mode)); 2340 } else if (imod && !M) { 2341 Inst.setOpcode(ARM::CPS2p); 2342 Inst.addOperand(MCOperand::createImm(imod)); 2343 Inst.addOperand(MCOperand::createImm(iflags)); 2344 if (mode) S = MCDisassembler::SoftFail; 2345 } else if (!imod && M) { 2346 Inst.setOpcode(ARM::CPS1p); 2347 Inst.addOperand(MCOperand::createImm(mode)); 2348 if (iflags) S = MCDisassembler::SoftFail; 2349 } else { 2350 // imod == '00' && M == '0' --> UNPREDICTABLE 2351 Inst.setOpcode(ARM::CPS1p); 2352 Inst.addOperand(MCOperand::createImm(mode)); 2353 S = MCDisassembler::SoftFail; 2354 } 2355 2356 return S; 2357 } 2358 2359 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2360 uint64_t Address, const void *Decoder) { 2361 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2362 unsigned M = fieldFromInstruction(Insn, 8, 1); 2363 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2364 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2365 2366 DecodeStatus S = MCDisassembler::Success; 2367 2368 // imod == '01' --> UNPREDICTABLE 2369 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2370 // return failure here. The '01' imod value is unprintable, so there's 2371 // nothing useful we could do even if we returned UNPREDICTABLE. 2372 2373 if (imod == 1) return MCDisassembler::Fail; 2374 2375 if (imod && M) { 2376 Inst.setOpcode(ARM::t2CPS3p); 2377 Inst.addOperand(MCOperand::createImm(imod)); 2378 Inst.addOperand(MCOperand::createImm(iflags)); 2379 Inst.addOperand(MCOperand::createImm(mode)); 2380 } else if (imod && !M) { 2381 Inst.setOpcode(ARM::t2CPS2p); 2382 Inst.addOperand(MCOperand::createImm(imod)); 2383 Inst.addOperand(MCOperand::createImm(iflags)); 2384 if (mode) S = MCDisassembler::SoftFail; 2385 } else if (!imod && M) { 2386 Inst.setOpcode(ARM::t2CPS1p); 2387 Inst.addOperand(MCOperand::createImm(mode)); 2388 if (iflags) S = MCDisassembler::SoftFail; 2389 } else { 2390 // imod == '00' && M == '0' --> this is a HINT instruction 2391 int imm = fieldFromInstruction(Insn, 0, 8); 2392 // HINT are defined only for immediate in [0..4] 2393 if(imm > 4) return MCDisassembler::Fail; 2394 Inst.setOpcode(ARM::t2HINT); 2395 Inst.addOperand(MCOperand::createImm(imm)); 2396 } 2397 2398 return S; 2399 } 2400 2401 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2402 uint64_t Address, const void *Decoder) { 2403 DecodeStatus S = MCDisassembler::Success; 2404 2405 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2406 unsigned imm = 0; 2407 2408 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2409 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2410 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2411 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2412 2413 if (Inst.getOpcode() == ARM::t2MOVTi16) 2414 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2415 return MCDisassembler::Fail; 2416 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2417 return MCDisassembler::Fail; 2418 2419 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2420 Inst.addOperand(MCOperand::createImm(imm)); 2421 2422 return S; 2423 } 2424 2425 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2426 uint64_t Address, const void *Decoder) { 2427 DecodeStatus S = MCDisassembler::Success; 2428 2429 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2430 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2431 unsigned imm = 0; 2432 2433 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2434 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2435 2436 if (Inst.getOpcode() == ARM::MOVTi16) 2437 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2438 return MCDisassembler::Fail; 2439 2440 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2441 return MCDisassembler::Fail; 2442 2443 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2444 Inst.addOperand(MCOperand::createImm(imm)); 2445 2446 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2447 return MCDisassembler::Fail; 2448 2449 return S; 2450 } 2451 2452 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2453 uint64_t Address, const void *Decoder) { 2454 DecodeStatus S = MCDisassembler::Success; 2455 2456 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2457 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2458 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2459 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2460 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2461 2462 if (pred == 0xF) 2463 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2464 2465 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2466 return MCDisassembler::Fail; 2467 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2468 return MCDisassembler::Fail; 2469 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2470 return MCDisassembler::Fail; 2471 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2472 return MCDisassembler::Fail; 2473 2474 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2475 return MCDisassembler::Fail; 2476 2477 return S; 2478 } 2479 2480 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2481 uint64_t Address, const void *Decoder) { 2482 DecodeStatus S = MCDisassembler::Success; 2483 2484 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2485 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2486 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2487 2488 if (Pred == 0xF) 2489 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2490 2491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2492 return MCDisassembler::Fail; 2493 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2494 return MCDisassembler::Fail; 2495 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2496 return MCDisassembler::Fail; 2497 2498 return S; 2499 } 2500 2501 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2502 uint64_t Address, const void *Decoder) { 2503 DecodeStatus S = MCDisassembler::Success; 2504 2505 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2506 2507 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2508 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2509 2510 if (!FeatureBits[ARM::HasV8_1aOps] || 2511 !FeatureBits[ARM::HasV8Ops]) 2512 return MCDisassembler::Fail; 2513 2514 // Decoder can be called from DecodeTST, which does not check the full 2515 // encoding is valid. 2516 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2517 fieldFromInstruction(Insn, 4,4) != 0) 2518 return MCDisassembler::Fail; 2519 if (fieldFromInstruction(Insn, 10,10) != 0 || 2520 fieldFromInstruction(Insn, 0,4) != 0) 2521 S = MCDisassembler::SoftFail; 2522 2523 Inst.setOpcode(ARM::SETPAN); 2524 Inst.addOperand(MCOperand::createImm(Imm)); 2525 2526 return S; 2527 } 2528 2529 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2530 uint64_t Address, const void *Decoder) { 2531 DecodeStatus S = MCDisassembler::Success; 2532 2533 unsigned add = fieldFromInstruction(Val, 12, 1); 2534 unsigned imm = fieldFromInstruction(Val, 0, 12); 2535 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2536 2537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2538 return MCDisassembler::Fail; 2539 2540 if (!add) imm *= -1; 2541 if (imm == 0 && !add) imm = INT32_MIN; 2542 Inst.addOperand(MCOperand::createImm(imm)); 2543 if (Rn == 15) 2544 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2545 2546 return S; 2547 } 2548 2549 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2550 uint64_t Address, const void *Decoder) { 2551 DecodeStatus S = MCDisassembler::Success; 2552 2553 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2554 // U == 1 to add imm, 0 to subtract it. 2555 unsigned U = fieldFromInstruction(Val, 8, 1); 2556 unsigned imm = fieldFromInstruction(Val, 0, 8); 2557 2558 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2559 return MCDisassembler::Fail; 2560 2561 if (U) 2562 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2563 else 2564 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2565 2566 return S; 2567 } 2568 2569 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2570 uint64_t Address, const void *Decoder) { 2571 DecodeStatus S = MCDisassembler::Success; 2572 2573 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2574 // U == 1 to add imm, 0 to subtract it. 2575 unsigned U = fieldFromInstruction(Val, 8, 1); 2576 unsigned imm = fieldFromInstruction(Val, 0, 8); 2577 2578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2579 return MCDisassembler::Fail; 2580 2581 if (U) 2582 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2583 else 2584 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2585 2586 return S; 2587 } 2588 2589 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2590 uint64_t Address, const void *Decoder) { 2591 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2592 } 2593 2594 static DecodeStatus 2595 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2596 uint64_t Address, const void *Decoder) { 2597 DecodeStatus Status = MCDisassembler::Success; 2598 2599 // Note the J1 and J2 values are from the encoded instruction. So here 2600 // change them to I1 and I2 values via as documented: 2601 // I1 = NOT(J1 EOR S); 2602 // I2 = NOT(J2 EOR S); 2603 // and build the imm32 with one trailing zero as documented: 2604 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2605 unsigned S = fieldFromInstruction(Insn, 26, 1); 2606 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2607 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2608 unsigned I1 = !(J1 ^ S); 2609 unsigned I2 = !(J2 ^ S); 2610 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2611 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2612 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2613 int imm32 = SignExtend32<25>(tmp << 1); 2614 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2615 true, 4, Inst, Decoder)) 2616 Inst.addOperand(MCOperand::createImm(imm32)); 2617 2618 return Status; 2619 } 2620 2621 static DecodeStatus 2622 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2623 uint64_t Address, const void *Decoder) { 2624 DecodeStatus S = MCDisassembler::Success; 2625 2626 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2627 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2628 2629 if (pred == 0xF) { 2630 Inst.setOpcode(ARM::BLXi); 2631 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2632 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2633 true, 4, Inst, Decoder)) 2634 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2635 return S; 2636 } 2637 2638 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2639 true, 4, Inst, Decoder)) 2640 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2641 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2642 return MCDisassembler::Fail; 2643 2644 return S; 2645 } 2646 2647 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2648 uint64_t Address, const void *Decoder) { 2649 DecodeStatus S = MCDisassembler::Success; 2650 2651 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2652 unsigned align = fieldFromInstruction(Val, 4, 2); 2653 2654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2655 return MCDisassembler::Fail; 2656 if (!align) 2657 Inst.addOperand(MCOperand::createImm(0)); 2658 else 2659 Inst.addOperand(MCOperand::createImm(4 << align)); 2660 2661 return S; 2662 } 2663 2664 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2665 uint64_t Address, const void *Decoder) { 2666 DecodeStatus S = MCDisassembler::Success; 2667 2668 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2669 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2670 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2671 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2672 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2673 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2674 2675 // First output register 2676 switch (Inst.getOpcode()) { 2677 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2678 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2679 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2680 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2681 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2682 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2683 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2684 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2685 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2686 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2687 return MCDisassembler::Fail; 2688 break; 2689 case ARM::VLD2b16: 2690 case ARM::VLD2b32: 2691 case ARM::VLD2b8: 2692 case ARM::VLD2b16wb_fixed: 2693 case ARM::VLD2b16wb_register: 2694 case ARM::VLD2b32wb_fixed: 2695 case ARM::VLD2b32wb_register: 2696 case ARM::VLD2b8wb_fixed: 2697 case ARM::VLD2b8wb_register: 2698 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2699 return MCDisassembler::Fail; 2700 break; 2701 default: 2702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2703 return MCDisassembler::Fail; 2704 } 2705 2706 // Second output register 2707 switch (Inst.getOpcode()) { 2708 case ARM::VLD3d8: 2709 case ARM::VLD3d16: 2710 case ARM::VLD3d32: 2711 case ARM::VLD3d8_UPD: 2712 case ARM::VLD3d16_UPD: 2713 case ARM::VLD3d32_UPD: 2714 case ARM::VLD4d8: 2715 case ARM::VLD4d16: 2716 case ARM::VLD4d32: 2717 case ARM::VLD4d8_UPD: 2718 case ARM::VLD4d16_UPD: 2719 case ARM::VLD4d32_UPD: 2720 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2721 return MCDisassembler::Fail; 2722 break; 2723 case ARM::VLD3q8: 2724 case ARM::VLD3q16: 2725 case ARM::VLD3q32: 2726 case ARM::VLD3q8_UPD: 2727 case ARM::VLD3q16_UPD: 2728 case ARM::VLD3q32_UPD: 2729 case ARM::VLD4q8: 2730 case ARM::VLD4q16: 2731 case ARM::VLD4q32: 2732 case ARM::VLD4q8_UPD: 2733 case ARM::VLD4q16_UPD: 2734 case ARM::VLD4q32_UPD: 2735 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2736 return MCDisassembler::Fail; 2737 break; 2738 default: 2739 break; 2740 } 2741 2742 // Third output register 2743 switch(Inst.getOpcode()) { 2744 case ARM::VLD3d8: 2745 case ARM::VLD3d16: 2746 case ARM::VLD3d32: 2747 case ARM::VLD3d8_UPD: 2748 case ARM::VLD3d16_UPD: 2749 case ARM::VLD3d32_UPD: 2750 case ARM::VLD4d8: 2751 case ARM::VLD4d16: 2752 case ARM::VLD4d32: 2753 case ARM::VLD4d8_UPD: 2754 case ARM::VLD4d16_UPD: 2755 case ARM::VLD4d32_UPD: 2756 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2757 return MCDisassembler::Fail; 2758 break; 2759 case ARM::VLD3q8: 2760 case ARM::VLD3q16: 2761 case ARM::VLD3q32: 2762 case ARM::VLD3q8_UPD: 2763 case ARM::VLD3q16_UPD: 2764 case ARM::VLD3q32_UPD: 2765 case ARM::VLD4q8: 2766 case ARM::VLD4q16: 2767 case ARM::VLD4q32: 2768 case ARM::VLD4q8_UPD: 2769 case ARM::VLD4q16_UPD: 2770 case ARM::VLD4q32_UPD: 2771 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2772 return MCDisassembler::Fail; 2773 break; 2774 default: 2775 break; 2776 } 2777 2778 // Fourth output register 2779 switch (Inst.getOpcode()) { 2780 case ARM::VLD4d8: 2781 case ARM::VLD4d16: 2782 case ARM::VLD4d32: 2783 case ARM::VLD4d8_UPD: 2784 case ARM::VLD4d16_UPD: 2785 case ARM::VLD4d32_UPD: 2786 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2787 return MCDisassembler::Fail; 2788 break; 2789 case ARM::VLD4q8: 2790 case ARM::VLD4q16: 2791 case ARM::VLD4q32: 2792 case ARM::VLD4q8_UPD: 2793 case ARM::VLD4q16_UPD: 2794 case ARM::VLD4q32_UPD: 2795 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2796 return MCDisassembler::Fail; 2797 break; 2798 default: 2799 break; 2800 } 2801 2802 // Writeback operand 2803 switch (Inst.getOpcode()) { 2804 case ARM::VLD1d8wb_fixed: 2805 case ARM::VLD1d16wb_fixed: 2806 case ARM::VLD1d32wb_fixed: 2807 case ARM::VLD1d64wb_fixed: 2808 case ARM::VLD1d8wb_register: 2809 case ARM::VLD1d16wb_register: 2810 case ARM::VLD1d32wb_register: 2811 case ARM::VLD1d64wb_register: 2812 case ARM::VLD1q8wb_fixed: 2813 case ARM::VLD1q16wb_fixed: 2814 case ARM::VLD1q32wb_fixed: 2815 case ARM::VLD1q64wb_fixed: 2816 case ARM::VLD1q8wb_register: 2817 case ARM::VLD1q16wb_register: 2818 case ARM::VLD1q32wb_register: 2819 case ARM::VLD1q64wb_register: 2820 case ARM::VLD1d8Twb_fixed: 2821 case ARM::VLD1d8Twb_register: 2822 case ARM::VLD1d16Twb_fixed: 2823 case ARM::VLD1d16Twb_register: 2824 case ARM::VLD1d32Twb_fixed: 2825 case ARM::VLD1d32Twb_register: 2826 case ARM::VLD1d64Twb_fixed: 2827 case ARM::VLD1d64Twb_register: 2828 case ARM::VLD1d8Qwb_fixed: 2829 case ARM::VLD1d8Qwb_register: 2830 case ARM::VLD1d16Qwb_fixed: 2831 case ARM::VLD1d16Qwb_register: 2832 case ARM::VLD1d32Qwb_fixed: 2833 case ARM::VLD1d32Qwb_register: 2834 case ARM::VLD1d64Qwb_fixed: 2835 case ARM::VLD1d64Qwb_register: 2836 case ARM::VLD2d8wb_fixed: 2837 case ARM::VLD2d16wb_fixed: 2838 case ARM::VLD2d32wb_fixed: 2839 case ARM::VLD2q8wb_fixed: 2840 case ARM::VLD2q16wb_fixed: 2841 case ARM::VLD2q32wb_fixed: 2842 case ARM::VLD2d8wb_register: 2843 case ARM::VLD2d16wb_register: 2844 case ARM::VLD2d32wb_register: 2845 case ARM::VLD2q8wb_register: 2846 case ARM::VLD2q16wb_register: 2847 case ARM::VLD2q32wb_register: 2848 case ARM::VLD2b8wb_fixed: 2849 case ARM::VLD2b16wb_fixed: 2850 case ARM::VLD2b32wb_fixed: 2851 case ARM::VLD2b8wb_register: 2852 case ARM::VLD2b16wb_register: 2853 case ARM::VLD2b32wb_register: 2854 Inst.addOperand(MCOperand::createImm(0)); 2855 break; 2856 case ARM::VLD3d8_UPD: 2857 case ARM::VLD3d16_UPD: 2858 case ARM::VLD3d32_UPD: 2859 case ARM::VLD3q8_UPD: 2860 case ARM::VLD3q16_UPD: 2861 case ARM::VLD3q32_UPD: 2862 case ARM::VLD4d8_UPD: 2863 case ARM::VLD4d16_UPD: 2864 case ARM::VLD4d32_UPD: 2865 case ARM::VLD4q8_UPD: 2866 case ARM::VLD4q16_UPD: 2867 case ARM::VLD4q32_UPD: 2868 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2869 return MCDisassembler::Fail; 2870 break; 2871 default: 2872 break; 2873 } 2874 2875 // AddrMode6 Base (register+alignment) 2876 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2877 return MCDisassembler::Fail; 2878 2879 // AddrMode6 Offset (register) 2880 switch (Inst.getOpcode()) { 2881 default: 2882 // The below have been updated to have explicit am6offset split 2883 // between fixed and register offset. For those instructions not 2884 // yet updated, we need to add an additional reg0 operand for the 2885 // fixed variant. 2886 // 2887 // The fixed offset encodes as Rm == 0xd, so we check for that. 2888 if (Rm == 0xd) { 2889 Inst.addOperand(MCOperand::createReg(0)); 2890 break; 2891 } 2892 // Fall through to handle the register offset variant. 2893 LLVM_FALLTHROUGH; 2894 case ARM::VLD1d8wb_fixed: 2895 case ARM::VLD1d16wb_fixed: 2896 case ARM::VLD1d32wb_fixed: 2897 case ARM::VLD1d64wb_fixed: 2898 case ARM::VLD1d8Twb_fixed: 2899 case ARM::VLD1d16Twb_fixed: 2900 case ARM::VLD1d32Twb_fixed: 2901 case ARM::VLD1d64Twb_fixed: 2902 case ARM::VLD1d8Qwb_fixed: 2903 case ARM::VLD1d16Qwb_fixed: 2904 case ARM::VLD1d32Qwb_fixed: 2905 case ARM::VLD1d64Qwb_fixed: 2906 case ARM::VLD1d8wb_register: 2907 case ARM::VLD1d16wb_register: 2908 case ARM::VLD1d32wb_register: 2909 case ARM::VLD1d64wb_register: 2910 case ARM::VLD1q8wb_fixed: 2911 case ARM::VLD1q16wb_fixed: 2912 case ARM::VLD1q32wb_fixed: 2913 case ARM::VLD1q64wb_fixed: 2914 case ARM::VLD1q8wb_register: 2915 case ARM::VLD1q16wb_register: 2916 case ARM::VLD1q32wb_register: 2917 case ARM::VLD1q64wb_register: 2918 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2919 // variant encodes Rm == 0xf. Anything else is a register offset post- 2920 // increment and we need to add the register operand to the instruction. 2921 if (Rm != 0xD && Rm != 0xF && 2922 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2923 return MCDisassembler::Fail; 2924 break; 2925 case ARM::VLD2d8wb_fixed: 2926 case ARM::VLD2d16wb_fixed: 2927 case ARM::VLD2d32wb_fixed: 2928 case ARM::VLD2b8wb_fixed: 2929 case ARM::VLD2b16wb_fixed: 2930 case ARM::VLD2b32wb_fixed: 2931 case ARM::VLD2q8wb_fixed: 2932 case ARM::VLD2q16wb_fixed: 2933 case ARM::VLD2q32wb_fixed: 2934 break; 2935 } 2936 2937 return S; 2938 } 2939 2940 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2941 uint64_t Address, const void *Decoder) { 2942 unsigned type = fieldFromInstruction(Insn, 8, 4); 2943 unsigned align = fieldFromInstruction(Insn, 4, 2); 2944 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2945 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2946 if (type == 10 && align == 3) return MCDisassembler::Fail; 2947 2948 unsigned load = fieldFromInstruction(Insn, 21, 1); 2949 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2950 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2951 } 2952 2953 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2954 uint64_t Address, const void *Decoder) { 2955 unsigned size = fieldFromInstruction(Insn, 6, 2); 2956 if (size == 3) return MCDisassembler::Fail; 2957 2958 unsigned type = fieldFromInstruction(Insn, 8, 4); 2959 unsigned align = fieldFromInstruction(Insn, 4, 2); 2960 if (type == 8 && align == 3) return MCDisassembler::Fail; 2961 if (type == 9 && align == 3) return MCDisassembler::Fail; 2962 2963 unsigned load = fieldFromInstruction(Insn, 21, 1); 2964 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2965 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2966 } 2967 2968 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2969 uint64_t Address, const void *Decoder) { 2970 unsigned size = fieldFromInstruction(Insn, 6, 2); 2971 if (size == 3) return MCDisassembler::Fail; 2972 2973 unsigned align = fieldFromInstruction(Insn, 4, 2); 2974 if (align & 2) return MCDisassembler::Fail; 2975 2976 unsigned load = fieldFromInstruction(Insn, 21, 1); 2977 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2978 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2979 } 2980 2981 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2982 uint64_t Address, const void *Decoder) { 2983 unsigned size = fieldFromInstruction(Insn, 6, 2); 2984 if (size == 3) return MCDisassembler::Fail; 2985 2986 unsigned load = fieldFromInstruction(Insn, 21, 1); 2987 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2988 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2989 } 2990 2991 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2992 uint64_t Address, const void *Decoder) { 2993 DecodeStatus S = MCDisassembler::Success; 2994 2995 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2996 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2997 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2998 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2999 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3000 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3001 3002 // Writeback Operand 3003 switch (Inst.getOpcode()) { 3004 case ARM::VST1d8wb_fixed: 3005 case ARM::VST1d16wb_fixed: 3006 case ARM::VST1d32wb_fixed: 3007 case ARM::VST1d64wb_fixed: 3008 case ARM::VST1d8wb_register: 3009 case ARM::VST1d16wb_register: 3010 case ARM::VST1d32wb_register: 3011 case ARM::VST1d64wb_register: 3012 case ARM::VST1q8wb_fixed: 3013 case ARM::VST1q16wb_fixed: 3014 case ARM::VST1q32wb_fixed: 3015 case ARM::VST1q64wb_fixed: 3016 case ARM::VST1q8wb_register: 3017 case ARM::VST1q16wb_register: 3018 case ARM::VST1q32wb_register: 3019 case ARM::VST1q64wb_register: 3020 case ARM::VST1d8Twb_fixed: 3021 case ARM::VST1d16Twb_fixed: 3022 case ARM::VST1d32Twb_fixed: 3023 case ARM::VST1d64Twb_fixed: 3024 case ARM::VST1d8Twb_register: 3025 case ARM::VST1d16Twb_register: 3026 case ARM::VST1d32Twb_register: 3027 case ARM::VST1d64Twb_register: 3028 case ARM::VST1d8Qwb_fixed: 3029 case ARM::VST1d16Qwb_fixed: 3030 case ARM::VST1d32Qwb_fixed: 3031 case ARM::VST1d64Qwb_fixed: 3032 case ARM::VST1d8Qwb_register: 3033 case ARM::VST1d16Qwb_register: 3034 case ARM::VST1d32Qwb_register: 3035 case ARM::VST1d64Qwb_register: 3036 case ARM::VST2d8wb_fixed: 3037 case ARM::VST2d16wb_fixed: 3038 case ARM::VST2d32wb_fixed: 3039 case ARM::VST2d8wb_register: 3040 case ARM::VST2d16wb_register: 3041 case ARM::VST2d32wb_register: 3042 case ARM::VST2q8wb_fixed: 3043 case ARM::VST2q16wb_fixed: 3044 case ARM::VST2q32wb_fixed: 3045 case ARM::VST2q8wb_register: 3046 case ARM::VST2q16wb_register: 3047 case ARM::VST2q32wb_register: 3048 case ARM::VST2b8wb_fixed: 3049 case ARM::VST2b16wb_fixed: 3050 case ARM::VST2b32wb_fixed: 3051 case ARM::VST2b8wb_register: 3052 case ARM::VST2b16wb_register: 3053 case ARM::VST2b32wb_register: 3054 if (Rm == 0xF) 3055 return MCDisassembler::Fail; 3056 Inst.addOperand(MCOperand::createImm(0)); 3057 break; 3058 case ARM::VST3d8_UPD: 3059 case ARM::VST3d16_UPD: 3060 case ARM::VST3d32_UPD: 3061 case ARM::VST3q8_UPD: 3062 case ARM::VST3q16_UPD: 3063 case ARM::VST3q32_UPD: 3064 case ARM::VST4d8_UPD: 3065 case ARM::VST4d16_UPD: 3066 case ARM::VST4d32_UPD: 3067 case ARM::VST4q8_UPD: 3068 case ARM::VST4q16_UPD: 3069 case ARM::VST4q32_UPD: 3070 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3071 return MCDisassembler::Fail; 3072 break; 3073 default: 3074 break; 3075 } 3076 3077 // AddrMode6 Base (register+alignment) 3078 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3079 return MCDisassembler::Fail; 3080 3081 // AddrMode6 Offset (register) 3082 switch (Inst.getOpcode()) { 3083 default: 3084 if (Rm == 0xD) 3085 Inst.addOperand(MCOperand::createReg(0)); 3086 else if (Rm != 0xF) { 3087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3088 return MCDisassembler::Fail; 3089 } 3090 break; 3091 case ARM::VST1d8wb_fixed: 3092 case ARM::VST1d16wb_fixed: 3093 case ARM::VST1d32wb_fixed: 3094 case ARM::VST1d64wb_fixed: 3095 case ARM::VST1q8wb_fixed: 3096 case ARM::VST1q16wb_fixed: 3097 case ARM::VST1q32wb_fixed: 3098 case ARM::VST1q64wb_fixed: 3099 case ARM::VST1d8Twb_fixed: 3100 case ARM::VST1d16Twb_fixed: 3101 case ARM::VST1d32Twb_fixed: 3102 case ARM::VST1d64Twb_fixed: 3103 case ARM::VST1d8Qwb_fixed: 3104 case ARM::VST1d16Qwb_fixed: 3105 case ARM::VST1d32Qwb_fixed: 3106 case ARM::VST1d64Qwb_fixed: 3107 case ARM::VST2d8wb_fixed: 3108 case ARM::VST2d16wb_fixed: 3109 case ARM::VST2d32wb_fixed: 3110 case ARM::VST2q8wb_fixed: 3111 case ARM::VST2q16wb_fixed: 3112 case ARM::VST2q32wb_fixed: 3113 case ARM::VST2b8wb_fixed: 3114 case ARM::VST2b16wb_fixed: 3115 case ARM::VST2b32wb_fixed: 3116 break; 3117 } 3118 3119 // First input register 3120 switch (Inst.getOpcode()) { 3121 case ARM::VST1q16: 3122 case ARM::VST1q32: 3123 case ARM::VST1q64: 3124 case ARM::VST1q8: 3125 case ARM::VST1q16wb_fixed: 3126 case ARM::VST1q16wb_register: 3127 case ARM::VST1q32wb_fixed: 3128 case ARM::VST1q32wb_register: 3129 case ARM::VST1q64wb_fixed: 3130 case ARM::VST1q64wb_register: 3131 case ARM::VST1q8wb_fixed: 3132 case ARM::VST1q8wb_register: 3133 case ARM::VST2d16: 3134 case ARM::VST2d32: 3135 case ARM::VST2d8: 3136 case ARM::VST2d16wb_fixed: 3137 case ARM::VST2d16wb_register: 3138 case ARM::VST2d32wb_fixed: 3139 case ARM::VST2d32wb_register: 3140 case ARM::VST2d8wb_fixed: 3141 case ARM::VST2d8wb_register: 3142 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3143 return MCDisassembler::Fail; 3144 break; 3145 case ARM::VST2b16: 3146 case ARM::VST2b32: 3147 case ARM::VST2b8: 3148 case ARM::VST2b16wb_fixed: 3149 case ARM::VST2b16wb_register: 3150 case ARM::VST2b32wb_fixed: 3151 case ARM::VST2b32wb_register: 3152 case ARM::VST2b8wb_fixed: 3153 case ARM::VST2b8wb_register: 3154 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3155 return MCDisassembler::Fail; 3156 break; 3157 default: 3158 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3159 return MCDisassembler::Fail; 3160 } 3161 3162 // Second input register 3163 switch (Inst.getOpcode()) { 3164 case ARM::VST3d8: 3165 case ARM::VST3d16: 3166 case ARM::VST3d32: 3167 case ARM::VST3d8_UPD: 3168 case ARM::VST3d16_UPD: 3169 case ARM::VST3d32_UPD: 3170 case ARM::VST4d8: 3171 case ARM::VST4d16: 3172 case ARM::VST4d32: 3173 case ARM::VST4d8_UPD: 3174 case ARM::VST4d16_UPD: 3175 case ARM::VST4d32_UPD: 3176 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3177 return MCDisassembler::Fail; 3178 break; 3179 case ARM::VST3q8: 3180 case ARM::VST3q16: 3181 case ARM::VST3q32: 3182 case ARM::VST3q8_UPD: 3183 case ARM::VST3q16_UPD: 3184 case ARM::VST3q32_UPD: 3185 case ARM::VST4q8: 3186 case ARM::VST4q16: 3187 case ARM::VST4q32: 3188 case ARM::VST4q8_UPD: 3189 case ARM::VST4q16_UPD: 3190 case ARM::VST4q32_UPD: 3191 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3192 return MCDisassembler::Fail; 3193 break; 3194 default: 3195 break; 3196 } 3197 3198 // Third input register 3199 switch (Inst.getOpcode()) { 3200 case ARM::VST3d8: 3201 case ARM::VST3d16: 3202 case ARM::VST3d32: 3203 case ARM::VST3d8_UPD: 3204 case ARM::VST3d16_UPD: 3205 case ARM::VST3d32_UPD: 3206 case ARM::VST4d8: 3207 case ARM::VST4d16: 3208 case ARM::VST4d32: 3209 case ARM::VST4d8_UPD: 3210 case ARM::VST4d16_UPD: 3211 case ARM::VST4d32_UPD: 3212 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3213 return MCDisassembler::Fail; 3214 break; 3215 case ARM::VST3q8: 3216 case ARM::VST3q16: 3217 case ARM::VST3q32: 3218 case ARM::VST3q8_UPD: 3219 case ARM::VST3q16_UPD: 3220 case ARM::VST3q32_UPD: 3221 case ARM::VST4q8: 3222 case ARM::VST4q16: 3223 case ARM::VST4q32: 3224 case ARM::VST4q8_UPD: 3225 case ARM::VST4q16_UPD: 3226 case ARM::VST4q32_UPD: 3227 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 break; 3230 default: 3231 break; 3232 } 3233 3234 // Fourth input register 3235 switch (Inst.getOpcode()) { 3236 case ARM::VST4d8: 3237 case ARM::VST4d16: 3238 case ARM::VST4d32: 3239 case ARM::VST4d8_UPD: 3240 case ARM::VST4d16_UPD: 3241 case ARM::VST4d32_UPD: 3242 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3243 return MCDisassembler::Fail; 3244 break; 3245 case ARM::VST4q8: 3246 case ARM::VST4q16: 3247 case ARM::VST4q32: 3248 case ARM::VST4q8_UPD: 3249 case ARM::VST4q16_UPD: 3250 case ARM::VST4q32_UPD: 3251 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3252 return MCDisassembler::Fail; 3253 break; 3254 default: 3255 break; 3256 } 3257 3258 return S; 3259 } 3260 3261 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3262 uint64_t Address, const void *Decoder) { 3263 DecodeStatus S = MCDisassembler::Success; 3264 3265 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3266 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3267 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3268 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3269 unsigned align = fieldFromInstruction(Insn, 4, 1); 3270 unsigned size = fieldFromInstruction(Insn, 6, 2); 3271 3272 if (size == 0 && align == 1) 3273 return MCDisassembler::Fail; 3274 align *= (1 << size); 3275 3276 switch (Inst.getOpcode()) { 3277 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3278 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3279 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3280 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3281 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3282 return MCDisassembler::Fail; 3283 break; 3284 default: 3285 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3286 return MCDisassembler::Fail; 3287 break; 3288 } 3289 if (Rm != 0xF) { 3290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3291 return MCDisassembler::Fail; 3292 } 3293 3294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3295 return MCDisassembler::Fail; 3296 Inst.addOperand(MCOperand::createImm(align)); 3297 3298 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3299 // variant encodes Rm == 0xf. Anything else is a register offset post- 3300 // increment and we need to add the register operand to the instruction. 3301 if (Rm != 0xD && Rm != 0xF && 3302 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3303 return MCDisassembler::Fail; 3304 3305 return S; 3306 } 3307 3308 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3309 uint64_t Address, const void *Decoder) { 3310 DecodeStatus S = MCDisassembler::Success; 3311 3312 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3313 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3314 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3315 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3316 unsigned align = fieldFromInstruction(Insn, 4, 1); 3317 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3318 align *= 2*size; 3319 3320 switch (Inst.getOpcode()) { 3321 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3322 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3323 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3324 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3325 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3326 return MCDisassembler::Fail; 3327 break; 3328 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3329 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3330 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3331 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3332 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3333 return MCDisassembler::Fail; 3334 break; 3335 default: 3336 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3337 return MCDisassembler::Fail; 3338 break; 3339 } 3340 3341 if (Rm != 0xF) 3342 Inst.addOperand(MCOperand::createImm(0)); 3343 3344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3345 return MCDisassembler::Fail; 3346 Inst.addOperand(MCOperand::createImm(align)); 3347 3348 if (Rm != 0xD && Rm != 0xF) { 3349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3350 return MCDisassembler::Fail; 3351 } 3352 3353 return S; 3354 } 3355 3356 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3357 uint64_t Address, const void *Decoder) { 3358 DecodeStatus S = MCDisassembler::Success; 3359 3360 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3361 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3362 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3363 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3364 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3365 3366 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3367 return MCDisassembler::Fail; 3368 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3369 return MCDisassembler::Fail; 3370 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3371 return MCDisassembler::Fail; 3372 if (Rm != 0xF) { 3373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3374 return MCDisassembler::Fail; 3375 } 3376 3377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3378 return MCDisassembler::Fail; 3379 Inst.addOperand(MCOperand::createImm(0)); 3380 3381 if (Rm == 0xD) 3382 Inst.addOperand(MCOperand::createReg(0)); 3383 else if (Rm != 0xF) { 3384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3385 return MCDisassembler::Fail; 3386 } 3387 3388 return S; 3389 } 3390 3391 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3392 uint64_t Address, const void *Decoder) { 3393 DecodeStatus S = MCDisassembler::Success; 3394 3395 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3396 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3397 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3398 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3399 unsigned size = fieldFromInstruction(Insn, 6, 2); 3400 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3401 unsigned align = fieldFromInstruction(Insn, 4, 1); 3402 3403 if (size == 0x3) { 3404 if (align == 0) 3405 return MCDisassembler::Fail; 3406 align = 16; 3407 } else { 3408 if (size == 2) { 3409 align *= 8; 3410 } else { 3411 size = 1 << size; 3412 align *= 4*size; 3413 } 3414 } 3415 3416 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3417 return MCDisassembler::Fail; 3418 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3419 return MCDisassembler::Fail; 3420 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3421 return MCDisassembler::Fail; 3422 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3423 return MCDisassembler::Fail; 3424 if (Rm != 0xF) { 3425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3426 return MCDisassembler::Fail; 3427 } 3428 3429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3430 return MCDisassembler::Fail; 3431 Inst.addOperand(MCOperand::createImm(align)); 3432 3433 if (Rm == 0xD) 3434 Inst.addOperand(MCOperand::createReg(0)); 3435 else if (Rm != 0xF) { 3436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3437 return MCDisassembler::Fail; 3438 } 3439 3440 return S; 3441 } 3442 3443 static DecodeStatus 3444 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3445 uint64_t Address, const void *Decoder) { 3446 DecodeStatus S = MCDisassembler::Success; 3447 3448 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3449 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3450 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3451 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3452 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3453 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3454 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3455 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3456 3457 if (Q) { 3458 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3459 return MCDisassembler::Fail; 3460 } else { 3461 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3462 return MCDisassembler::Fail; 3463 } 3464 3465 Inst.addOperand(MCOperand::createImm(imm)); 3466 3467 switch (Inst.getOpcode()) { 3468 case ARM::VORRiv4i16: 3469 case ARM::VORRiv2i32: 3470 case ARM::VBICiv4i16: 3471 case ARM::VBICiv2i32: 3472 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3473 return MCDisassembler::Fail; 3474 break; 3475 case ARM::VORRiv8i16: 3476 case ARM::VORRiv4i32: 3477 case ARM::VBICiv8i16: 3478 case ARM::VBICiv4i32: 3479 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3480 return MCDisassembler::Fail; 3481 break; 3482 default: 3483 break; 3484 } 3485 3486 return S; 3487 } 3488 3489 static DecodeStatus 3490 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3491 uint64_t Address, const void *Decoder) { 3492 DecodeStatus S = MCDisassembler::Success; 3493 3494 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3495 fieldFromInstruction(Insn, 13, 3)); 3496 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3497 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3498 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3499 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3500 imm |= cmode << 8; 3501 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3502 3503 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3504 return MCDisassembler::Fail; 3505 3506 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3507 return MCDisassembler::Fail; 3508 3509 Inst.addOperand(MCOperand::createImm(imm)); 3510 3511 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3512 Inst.addOperand(MCOperand::createReg(0)); 3513 Inst.addOperand(MCOperand::createImm(0)); 3514 3515 return S; 3516 } 3517 3518 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3519 uint64_t Address, const void *Decoder) { 3520 DecodeStatus S = MCDisassembler::Success; 3521 3522 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3523 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3524 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3525 return MCDisassembler::Fail; 3526 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3527 3528 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3529 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3530 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3533 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3534 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3535 return MCDisassembler::Fail; 3536 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3537 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3538 Inst.addOperand(MCOperand::createImm(Qd)); 3539 3540 return S; 3541 } 3542 3543 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3544 uint64_t Address, const void *Decoder) { 3545 DecodeStatus S = MCDisassembler::Success; 3546 3547 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3548 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3549 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3550 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3551 unsigned size = fieldFromInstruction(Insn, 18, 2); 3552 3553 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3554 return MCDisassembler::Fail; 3555 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3556 return MCDisassembler::Fail; 3557 Inst.addOperand(MCOperand::createImm(8 << size)); 3558 3559 return S; 3560 } 3561 3562 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3563 uint64_t Address, const void *Decoder) { 3564 Inst.addOperand(MCOperand::createImm(8 - Val)); 3565 return MCDisassembler::Success; 3566 } 3567 3568 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3569 uint64_t Address, const void *Decoder) { 3570 Inst.addOperand(MCOperand::createImm(16 - Val)); 3571 return MCDisassembler::Success; 3572 } 3573 3574 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3575 uint64_t Address, const void *Decoder) { 3576 Inst.addOperand(MCOperand::createImm(32 - Val)); 3577 return MCDisassembler::Success; 3578 } 3579 3580 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3581 uint64_t Address, const void *Decoder) { 3582 Inst.addOperand(MCOperand::createImm(64 - Val)); 3583 return MCDisassembler::Success; 3584 } 3585 3586 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3587 uint64_t Address, const void *Decoder) { 3588 DecodeStatus S = MCDisassembler::Success; 3589 3590 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3591 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3592 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3593 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3594 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3595 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3596 unsigned op = fieldFromInstruction(Insn, 6, 1); 3597 3598 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3599 return MCDisassembler::Fail; 3600 if (op) { 3601 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3602 return MCDisassembler::Fail; // Writeback 3603 } 3604 3605 switch (Inst.getOpcode()) { 3606 case ARM::VTBL2: 3607 case ARM::VTBX2: 3608 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3609 return MCDisassembler::Fail; 3610 break; 3611 default: 3612 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3613 return MCDisassembler::Fail; 3614 } 3615 3616 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3617 return MCDisassembler::Fail; 3618 3619 return S; 3620 } 3621 3622 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3623 uint64_t Address, const void *Decoder) { 3624 DecodeStatus S = MCDisassembler::Success; 3625 3626 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3627 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3628 3629 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3630 return MCDisassembler::Fail; 3631 3632 switch(Inst.getOpcode()) { 3633 default: 3634 return MCDisassembler::Fail; 3635 case ARM::tADR: 3636 break; // tADR does not explicitly represent the PC as an operand. 3637 case ARM::tADDrSPi: 3638 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3639 break; 3640 } 3641 3642 Inst.addOperand(MCOperand::createImm(imm)); 3643 return S; 3644 } 3645 3646 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3647 uint64_t Address, const void *Decoder) { 3648 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3649 true, 2, Inst, Decoder)) 3650 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3651 return MCDisassembler::Success; 3652 } 3653 3654 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3655 uint64_t Address, const void *Decoder) { 3656 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3657 true, 4, Inst, Decoder)) 3658 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3659 return MCDisassembler::Success; 3660 } 3661 3662 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3663 uint64_t Address, const void *Decoder) { 3664 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3665 true, 2, Inst, Decoder)) 3666 Inst.addOperand(MCOperand::createImm(Val << 1)); 3667 return MCDisassembler::Success; 3668 } 3669 3670 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3671 uint64_t Address, const void *Decoder) { 3672 DecodeStatus S = MCDisassembler::Success; 3673 3674 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3675 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3676 3677 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3678 return MCDisassembler::Fail; 3679 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 3682 return S; 3683 } 3684 3685 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3686 uint64_t Address, const void *Decoder) { 3687 DecodeStatus S = MCDisassembler::Success; 3688 3689 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3690 unsigned imm = fieldFromInstruction(Val, 3, 5); 3691 3692 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3693 return MCDisassembler::Fail; 3694 Inst.addOperand(MCOperand::createImm(imm)); 3695 3696 return S; 3697 } 3698 3699 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3700 uint64_t Address, const void *Decoder) { 3701 unsigned imm = Val << 2; 3702 3703 Inst.addOperand(MCOperand::createImm(imm)); 3704 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3705 3706 return MCDisassembler::Success; 3707 } 3708 3709 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3710 uint64_t Address, const void *Decoder) { 3711 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3712 Inst.addOperand(MCOperand::createImm(Val)); 3713 3714 return MCDisassembler::Success; 3715 } 3716 3717 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3718 uint64_t Address, const void *Decoder) { 3719 DecodeStatus S = MCDisassembler::Success; 3720 3721 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3722 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3723 unsigned imm = fieldFromInstruction(Val, 0, 2); 3724 3725 // Thumb stores cannot use PC as dest register. 3726 switch (Inst.getOpcode()) { 3727 case ARM::t2STRHs: 3728 case ARM::t2STRBs: 3729 case ARM::t2STRs: 3730 if (Rn == 15) 3731 return MCDisassembler::Fail; 3732 break; 3733 default: 3734 break; 3735 } 3736 3737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3738 return MCDisassembler::Fail; 3739 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3740 return MCDisassembler::Fail; 3741 Inst.addOperand(MCOperand::createImm(imm)); 3742 3743 return S; 3744 } 3745 3746 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3747 uint64_t Address, const void *Decoder) { 3748 DecodeStatus S = MCDisassembler::Success; 3749 3750 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3751 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3752 3753 const FeatureBitset &featureBits = 3754 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3755 3756 bool hasMP = featureBits[ARM::FeatureMP]; 3757 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3758 3759 if (Rn == 15) { 3760 switch (Inst.getOpcode()) { 3761 case ARM::t2LDRBs: 3762 Inst.setOpcode(ARM::t2LDRBpci); 3763 break; 3764 case ARM::t2LDRHs: 3765 Inst.setOpcode(ARM::t2LDRHpci); 3766 break; 3767 case ARM::t2LDRSHs: 3768 Inst.setOpcode(ARM::t2LDRSHpci); 3769 break; 3770 case ARM::t2LDRSBs: 3771 Inst.setOpcode(ARM::t2LDRSBpci); 3772 break; 3773 case ARM::t2LDRs: 3774 Inst.setOpcode(ARM::t2LDRpci); 3775 break; 3776 case ARM::t2PLDs: 3777 Inst.setOpcode(ARM::t2PLDpci); 3778 break; 3779 case ARM::t2PLIs: 3780 Inst.setOpcode(ARM::t2PLIpci); 3781 break; 3782 default: 3783 return MCDisassembler::Fail; 3784 } 3785 3786 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3787 } 3788 3789 if (Rt == 15) { 3790 switch (Inst.getOpcode()) { 3791 case ARM::t2LDRSHs: 3792 return MCDisassembler::Fail; 3793 case ARM::t2LDRHs: 3794 Inst.setOpcode(ARM::t2PLDWs); 3795 break; 3796 case ARM::t2LDRSBs: 3797 Inst.setOpcode(ARM::t2PLIs); 3798 break; 3799 default: 3800 break; 3801 } 3802 } 3803 3804 switch (Inst.getOpcode()) { 3805 case ARM::t2PLDs: 3806 break; 3807 case ARM::t2PLIs: 3808 if (!hasV7Ops) 3809 return MCDisassembler::Fail; 3810 break; 3811 case ARM::t2PLDWs: 3812 if (!hasV7Ops || !hasMP) 3813 return MCDisassembler::Fail; 3814 break; 3815 default: 3816 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3817 return MCDisassembler::Fail; 3818 } 3819 3820 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3821 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3822 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3823 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3824 return MCDisassembler::Fail; 3825 3826 return S; 3827 } 3828 3829 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3830 uint64_t Address, const void* Decoder) { 3831 DecodeStatus S = MCDisassembler::Success; 3832 3833 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3834 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3835 unsigned U = fieldFromInstruction(Insn, 9, 1); 3836 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3837 imm |= (U << 8); 3838 imm |= (Rn << 9); 3839 unsigned add = fieldFromInstruction(Insn, 9, 1); 3840 3841 const FeatureBitset &featureBits = 3842 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3843 3844 bool hasMP = featureBits[ARM::FeatureMP]; 3845 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3846 3847 if (Rn == 15) { 3848 switch (Inst.getOpcode()) { 3849 case ARM::t2LDRi8: 3850 Inst.setOpcode(ARM::t2LDRpci); 3851 break; 3852 case ARM::t2LDRBi8: 3853 Inst.setOpcode(ARM::t2LDRBpci); 3854 break; 3855 case ARM::t2LDRSBi8: 3856 Inst.setOpcode(ARM::t2LDRSBpci); 3857 break; 3858 case ARM::t2LDRHi8: 3859 Inst.setOpcode(ARM::t2LDRHpci); 3860 break; 3861 case ARM::t2LDRSHi8: 3862 Inst.setOpcode(ARM::t2LDRSHpci); 3863 break; 3864 case ARM::t2PLDi8: 3865 Inst.setOpcode(ARM::t2PLDpci); 3866 break; 3867 case ARM::t2PLIi8: 3868 Inst.setOpcode(ARM::t2PLIpci); 3869 break; 3870 default: 3871 return MCDisassembler::Fail; 3872 } 3873 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3874 } 3875 3876 if (Rt == 15) { 3877 switch (Inst.getOpcode()) { 3878 case ARM::t2LDRSHi8: 3879 return MCDisassembler::Fail; 3880 case ARM::t2LDRHi8: 3881 if (!add) 3882 Inst.setOpcode(ARM::t2PLDWi8); 3883 break; 3884 case ARM::t2LDRSBi8: 3885 Inst.setOpcode(ARM::t2PLIi8); 3886 break; 3887 default: 3888 break; 3889 } 3890 } 3891 3892 switch (Inst.getOpcode()) { 3893 case ARM::t2PLDi8: 3894 break; 3895 case ARM::t2PLIi8: 3896 if (!hasV7Ops) 3897 return MCDisassembler::Fail; 3898 break; 3899 case ARM::t2PLDWi8: 3900 if (!hasV7Ops || !hasMP) 3901 return MCDisassembler::Fail; 3902 break; 3903 default: 3904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3905 return MCDisassembler::Fail; 3906 } 3907 3908 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3909 return MCDisassembler::Fail; 3910 return S; 3911 } 3912 3913 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3914 uint64_t Address, const void* Decoder) { 3915 DecodeStatus S = MCDisassembler::Success; 3916 3917 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3918 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3919 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3920 imm |= (Rn << 13); 3921 3922 const FeatureBitset &featureBits = 3923 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3924 3925 bool hasMP = featureBits[ARM::FeatureMP]; 3926 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3927 3928 if (Rn == 15) { 3929 switch (Inst.getOpcode()) { 3930 case ARM::t2LDRi12: 3931 Inst.setOpcode(ARM::t2LDRpci); 3932 break; 3933 case ARM::t2LDRHi12: 3934 Inst.setOpcode(ARM::t2LDRHpci); 3935 break; 3936 case ARM::t2LDRSHi12: 3937 Inst.setOpcode(ARM::t2LDRSHpci); 3938 break; 3939 case ARM::t2LDRBi12: 3940 Inst.setOpcode(ARM::t2LDRBpci); 3941 break; 3942 case ARM::t2LDRSBi12: 3943 Inst.setOpcode(ARM::t2LDRSBpci); 3944 break; 3945 case ARM::t2PLDi12: 3946 Inst.setOpcode(ARM::t2PLDpci); 3947 break; 3948 case ARM::t2PLIi12: 3949 Inst.setOpcode(ARM::t2PLIpci); 3950 break; 3951 default: 3952 return MCDisassembler::Fail; 3953 } 3954 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3955 } 3956 3957 if (Rt == 15) { 3958 switch (Inst.getOpcode()) { 3959 case ARM::t2LDRSHi12: 3960 return MCDisassembler::Fail; 3961 case ARM::t2LDRHi12: 3962 Inst.setOpcode(ARM::t2PLDWi12); 3963 break; 3964 case ARM::t2LDRSBi12: 3965 Inst.setOpcode(ARM::t2PLIi12); 3966 break; 3967 default: 3968 break; 3969 } 3970 } 3971 3972 switch (Inst.getOpcode()) { 3973 case ARM::t2PLDi12: 3974 break; 3975 case ARM::t2PLIi12: 3976 if (!hasV7Ops) 3977 return MCDisassembler::Fail; 3978 break; 3979 case ARM::t2PLDWi12: 3980 if (!hasV7Ops || !hasMP) 3981 return MCDisassembler::Fail; 3982 break; 3983 default: 3984 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3985 return MCDisassembler::Fail; 3986 } 3987 3988 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3989 return MCDisassembler::Fail; 3990 return S; 3991 } 3992 3993 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3994 uint64_t Address, const void* Decoder) { 3995 DecodeStatus S = MCDisassembler::Success; 3996 3997 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3998 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3999 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4000 imm |= (Rn << 9); 4001 4002 if (Rn == 15) { 4003 switch (Inst.getOpcode()) { 4004 case ARM::t2LDRT: 4005 Inst.setOpcode(ARM::t2LDRpci); 4006 break; 4007 case ARM::t2LDRBT: 4008 Inst.setOpcode(ARM::t2LDRBpci); 4009 break; 4010 case ARM::t2LDRHT: 4011 Inst.setOpcode(ARM::t2LDRHpci); 4012 break; 4013 case ARM::t2LDRSBT: 4014 Inst.setOpcode(ARM::t2LDRSBpci); 4015 break; 4016 case ARM::t2LDRSHT: 4017 Inst.setOpcode(ARM::t2LDRSHpci); 4018 break; 4019 default: 4020 return MCDisassembler::Fail; 4021 } 4022 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4023 } 4024 4025 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4026 return MCDisassembler::Fail; 4027 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4028 return MCDisassembler::Fail; 4029 return S; 4030 } 4031 4032 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4033 uint64_t Address, const void* Decoder) { 4034 DecodeStatus S = MCDisassembler::Success; 4035 4036 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4037 unsigned U = fieldFromInstruction(Insn, 23, 1); 4038 int imm = fieldFromInstruction(Insn, 0, 12); 4039 4040 const FeatureBitset &featureBits = 4041 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4042 4043 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4044 4045 if (Rt == 15) { 4046 switch (Inst.getOpcode()) { 4047 case ARM::t2LDRBpci: 4048 case ARM::t2LDRHpci: 4049 Inst.setOpcode(ARM::t2PLDpci); 4050 break; 4051 case ARM::t2LDRSBpci: 4052 Inst.setOpcode(ARM::t2PLIpci); 4053 break; 4054 case ARM::t2LDRSHpci: 4055 return MCDisassembler::Fail; 4056 default: 4057 break; 4058 } 4059 } 4060 4061 switch(Inst.getOpcode()) { 4062 case ARM::t2PLDpci: 4063 break; 4064 case ARM::t2PLIpci: 4065 if (!hasV7Ops) 4066 return MCDisassembler::Fail; 4067 break; 4068 default: 4069 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4070 return MCDisassembler::Fail; 4071 } 4072 4073 if (!U) { 4074 // Special case for #-0. 4075 if (imm == 0) 4076 imm = INT32_MIN; 4077 else 4078 imm = -imm; 4079 } 4080 Inst.addOperand(MCOperand::createImm(imm)); 4081 4082 return S; 4083 } 4084 4085 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4086 uint64_t Address, const void *Decoder) { 4087 if (Val == 0) 4088 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4089 else { 4090 int imm = Val & 0xFF; 4091 4092 if (!(Val & 0x100)) imm *= -1; 4093 Inst.addOperand(MCOperand::createImm(imm * 4)); 4094 } 4095 4096 return MCDisassembler::Success; 4097 } 4098 4099 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4100 const void *Decoder) { 4101 if (Val == 0) 4102 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4103 else { 4104 int imm = Val & 0x7F; 4105 4106 if (!(Val & 0x80)) 4107 imm *= -1; 4108 Inst.addOperand(MCOperand::createImm(imm * 4)); 4109 } 4110 4111 return MCDisassembler::Success; 4112 } 4113 4114 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4115 uint64_t Address, const void *Decoder) { 4116 DecodeStatus S = MCDisassembler::Success; 4117 4118 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4119 unsigned imm = fieldFromInstruction(Val, 0, 9); 4120 4121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4122 return MCDisassembler::Fail; 4123 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4124 return MCDisassembler::Fail; 4125 4126 return S; 4127 } 4128 4129 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4130 uint64_t Address, 4131 const void *Decoder) { 4132 DecodeStatus S = MCDisassembler::Success; 4133 4134 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4135 unsigned imm = fieldFromInstruction(Val, 0, 8); 4136 4137 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4138 return MCDisassembler::Fail; 4139 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4140 return MCDisassembler::Fail; 4141 4142 return S; 4143 } 4144 4145 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4146 uint64_t Address, const void *Decoder) { 4147 DecodeStatus S = MCDisassembler::Success; 4148 4149 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4150 unsigned imm = fieldFromInstruction(Val, 0, 8); 4151 4152 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4153 return MCDisassembler::Fail; 4154 4155 Inst.addOperand(MCOperand::createImm(imm)); 4156 4157 return S; 4158 } 4159 4160 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4161 uint64_t Address, const void *Decoder) { 4162 int imm = Val & 0xFF; 4163 if (Val == 0) 4164 imm = INT32_MIN; 4165 else if (!(Val & 0x100)) 4166 imm *= -1; 4167 Inst.addOperand(MCOperand::createImm(imm)); 4168 4169 return MCDisassembler::Success; 4170 } 4171 4172 template<int shift> 4173 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4174 uint64_t Address, const void *Decoder) { 4175 int imm = Val & 0x7F; 4176 if (Val == 0) 4177 imm = INT32_MIN; 4178 else if (!(Val & 0x80)) 4179 imm *= -1; 4180 if (imm != INT32_MIN) 4181 imm *= (1U << shift); 4182 Inst.addOperand(MCOperand::createImm(imm)); 4183 4184 return MCDisassembler::Success; 4185 } 4186 4187 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4188 uint64_t Address, const void *Decoder) { 4189 DecodeStatus S = MCDisassembler::Success; 4190 4191 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4192 unsigned imm = fieldFromInstruction(Val, 0, 9); 4193 4194 // Thumb stores cannot use PC as dest register. 4195 switch (Inst.getOpcode()) { 4196 case ARM::t2STRT: 4197 case ARM::t2STRBT: 4198 case ARM::t2STRHT: 4199 case ARM::t2STRi8: 4200 case ARM::t2STRHi8: 4201 case ARM::t2STRBi8: 4202 if (Rn == 15) 4203 return MCDisassembler::Fail; 4204 break; 4205 default: 4206 break; 4207 } 4208 4209 // Some instructions always use an additive offset. 4210 switch (Inst.getOpcode()) { 4211 case ARM::t2LDRT: 4212 case ARM::t2LDRBT: 4213 case ARM::t2LDRHT: 4214 case ARM::t2LDRSBT: 4215 case ARM::t2LDRSHT: 4216 case ARM::t2STRT: 4217 case ARM::t2STRBT: 4218 case ARM::t2STRHT: 4219 imm |= 0x100; 4220 break; 4221 default: 4222 break; 4223 } 4224 4225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4226 return MCDisassembler::Fail; 4227 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4228 return MCDisassembler::Fail; 4229 4230 return S; 4231 } 4232 4233 template<int shift> 4234 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4235 uint64_t Address, 4236 const void *Decoder) { 4237 DecodeStatus S = MCDisassembler::Success; 4238 4239 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4240 unsigned imm = fieldFromInstruction(Val, 0, 8); 4241 4242 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4243 return MCDisassembler::Fail; 4244 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4245 return MCDisassembler::Fail; 4246 4247 return S; 4248 } 4249 4250 template<int shift, int WriteBack> 4251 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4252 uint64_t Address, 4253 const void *Decoder) { 4254 DecodeStatus S = MCDisassembler::Success; 4255 4256 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4257 unsigned imm = fieldFromInstruction(Val, 0, 8); 4258 if (WriteBack) { 4259 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4260 return MCDisassembler::Fail; 4261 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4262 return MCDisassembler::Fail; 4263 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4264 return MCDisassembler::Fail; 4265 4266 return S; 4267 } 4268 4269 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4270 uint64_t Address, const void *Decoder) { 4271 DecodeStatus S = MCDisassembler::Success; 4272 4273 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4274 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4275 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4276 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4277 addr |= Rn << 9; 4278 unsigned load = fieldFromInstruction(Insn, 20, 1); 4279 4280 if (Rn == 15) { 4281 switch (Inst.getOpcode()) { 4282 case ARM::t2LDR_PRE: 4283 case ARM::t2LDR_POST: 4284 Inst.setOpcode(ARM::t2LDRpci); 4285 break; 4286 case ARM::t2LDRB_PRE: 4287 case ARM::t2LDRB_POST: 4288 Inst.setOpcode(ARM::t2LDRBpci); 4289 break; 4290 case ARM::t2LDRH_PRE: 4291 case ARM::t2LDRH_POST: 4292 Inst.setOpcode(ARM::t2LDRHpci); 4293 break; 4294 case ARM::t2LDRSB_PRE: 4295 case ARM::t2LDRSB_POST: 4296 if (Rt == 15) 4297 Inst.setOpcode(ARM::t2PLIpci); 4298 else 4299 Inst.setOpcode(ARM::t2LDRSBpci); 4300 break; 4301 case ARM::t2LDRSH_PRE: 4302 case ARM::t2LDRSH_POST: 4303 Inst.setOpcode(ARM::t2LDRSHpci); 4304 break; 4305 default: 4306 return MCDisassembler::Fail; 4307 } 4308 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4309 } 4310 4311 if (!load) { 4312 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4313 return MCDisassembler::Fail; 4314 } 4315 4316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4317 return MCDisassembler::Fail; 4318 4319 if (load) { 4320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4321 return MCDisassembler::Fail; 4322 } 4323 4324 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4325 return MCDisassembler::Fail; 4326 4327 return S; 4328 } 4329 4330 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4331 uint64_t Address, const void *Decoder) { 4332 DecodeStatus S = MCDisassembler::Success; 4333 4334 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4335 unsigned imm = fieldFromInstruction(Val, 0, 12); 4336 4337 // Thumb stores cannot use PC as dest register. 4338 switch (Inst.getOpcode()) { 4339 case ARM::t2STRi12: 4340 case ARM::t2STRBi12: 4341 case ARM::t2STRHi12: 4342 if (Rn == 15) 4343 return MCDisassembler::Fail; 4344 break; 4345 default: 4346 break; 4347 } 4348 4349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4350 return MCDisassembler::Fail; 4351 Inst.addOperand(MCOperand::createImm(imm)); 4352 4353 return S; 4354 } 4355 4356 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4357 uint64_t Address, const void *Decoder) { 4358 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4359 4360 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4361 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4362 Inst.addOperand(MCOperand::createImm(imm)); 4363 4364 return MCDisassembler::Success; 4365 } 4366 4367 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4368 uint64_t Address, const void *Decoder) { 4369 DecodeStatus S = MCDisassembler::Success; 4370 4371 if (Inst.getOpcode() == ARM::tADDrSP) { 4372 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4373 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4374 4375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4376 return MCDisassembler::Fail; 4377 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4379 return MCDisassembler::Fail; 4380 } else if (Inst.getOpcode() == ARM::tADDspr) { 4381 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4382 4383 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4384 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4386 return MCDisassembler::Fail; 4387 } 4388 4389 return S; 4390 } 4391 4392 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4393 uint64_t Address, const void *Decoder) { 4394 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4395 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4396 4397 Inst.addOperand(MCOperand::createImm(imod)); 4398 Inst.addOperand(MCOperand::createImm(flags)); 4399 4400 return MCDisassembler::Success; 4401 } 4402 4403 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4404 uint64_t Address, const void *Decoder) { 4405 DecodeStatus S = MCDisassembler::Success; 4406 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4407 unsigned add = fieldFromInstruction(Insn, 4, 1); 4408 4409 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4410 return MCDisassembler::Fail; 4411 Inst.addOperand(MCOperand::createImm(add)); 4412 4413 return S; 4414 } 4415 4416 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4417 uint64_t Address, const void *Decoder) { 4418 DecodeStatus S = MCDisassembler::Success; 4419 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4420 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4421 4422 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4423 return MCDisassembler::Fail; 4424 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4425 return MCDisassembler::Fail; 4426 4427 return S; 4428 } 4429 4430 template<int shift> 4431 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4432 uint64_t Address, const void *Decoder) { 4433 DecodeStatus S = MCDisassembler::Success; 4434 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4435 int imm = fieldFromInstruction(Insn, 0, 7); 4436 4437 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4438 return MCDisassembler::Fail; 4439 4440 if(!fieldFromInstruction(Insn, 7, 1)) { 4441 if (imm == 0) 4442 imm = INT32_MIN; // indicate -0 4443 else 4444 imm *= -1; 4445 } 4446 if (imm != INT32_MIN) 4447 imm *= (1U << shift); 4448 Inst.addOperand(MCOperand::createImm(imm)); 4449 4450 return S; 4451 } 4452 4453 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4454 uint64_t Address, const void *Decoder) { 4455 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4456 // Note only one trailing zero not two. Also the J1 and J2 values are from 4457 // the encoded instruction. So here change to I1 and I2 values via: 4458 // I1 = NOT(J1 EOR S); 4459 // I2 = NOT(J2 EOR S); 4460 // and build the imm32 with two trailing zeros as documented: 4461 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4462 unsigned S = (Val >> 23) & 1; 4463 unsigned J1 = (Val >> 22) & 1; 4464 unsigned J2 = (Val >> 21) & 1; 4465 unsigned I1 = !(J1 ^ S); 4466 unsigned I2 = !(J2 ^ S); 4467 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4468 int imm32 = SignExtend32<25>(tmp << 1); 4469 4470 if (!tryAddingSymbolicOperand(Address, 4471 (Address & ~2u) + imm32 + 4, 4472 true, 4, Inst, Decoder)) 4473 Inst.addOperand(MCOperand::createImm(imm32)); 4474 return MCDisassembler::Success; 4475 } 4476 4477 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4478 uint64_t Address, const void *Decoder) { 4479 if (Val == 0xA || Val == 0xB) 4480 return MCDisassembler::Fail; 4481 4482 const FeatureBitset &featureBits = 4483 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4484 4485 if (!isValidCoprocessorNumber(Val, featureBits)) 4486 return MCDisassembler::Fail; 4487 4488 Inst.addOperand(MCOperand::createImm(Val)); 4489 return MCDisassembler::Success; 4490 } 4491 4492 static DecodeStatus 4493 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4494 uint64_t Address, const void *Decoder) { 4495 DecodeStatus S = MCDisassembler::Success; 4496 4497 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4498 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4499 4500 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4502 return MCDisassembler::Fail; 4503 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4504 return MCDisassembler::Fail; 4505 return S; 4506 } 4507 4508 static DecodeStatus 4509 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4510 uint64_t Address, const void *Decoder) { 4511 DecodeStatus S = MCDisassembler::Success; 4512 4513 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4514 if (pred == 0xE || pred == 0xF) { 4515 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4516 switch (opc) { 4517 default: 4518 return MCDisassembler::Fail; 4519 case 0xf3bf8f4: 4520 Inst.setOpcode(ARM::t2DSB); 4521 break; 4522 case 0xf3bf8f5: 4523 Inst.setOpcode(ARM::t2DMB); 4524 break; 4525 case 0xf3bf8f6: 4526 Inst.setOpcode(ARM::t2ISB); 4527 break; 4528 } 4529 4530 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4531 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4532 } 4533 4534 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4535 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4536 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4537 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4538 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4539 4540 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4541 return MCDisassembler::Fail; 4542 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4543 return MCDisassembler::Fail; 4544 4545 return S; 4546 } 4547 4548 // Decode a shifted immediate operand. These basically consist 4549 // of an 8-bit value, and a 4-bit directive that specifies either 4550 // a splat operation or a rotation. 4551 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4552 uint64_t Address, const void *Decoder) { 4553 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4554 if (ctrl == 0) { 4555 unsigned byte = fieldFromInstruction(Val, 8, 2); 4556 unsigned imm = fieldFromInstruction(Val, 0, 8); 4557 switch (byte) { 4558 case 0: 4559 Inst.addOperand(MCOperand::createImm(imm)); 4560 break; 4561 case 1: 4562 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4563 break; 4564 case 2: 4565 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4566 break; 4567 case 3: 4568 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4569 (imm << 8) | imm)); 4570 break; 4571 } 4572 } else { 4573 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4574 unsigned rot = fieldFromInstruction(Val, 7, 5); 4575 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4576 Inst.addOperand(MCOperand::createImm(imm)); 4577 } 4578 4579 return MCDisassembler::Success; 4580 } 4581 4582 static DecodeStatus 4583 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4584 uint64_t Address, const void *Decoder) { 4585 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4586 true, 2, Inst, Decoder)) 4587 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4588 return MCDisassembler::Success; 4589 } 4590 4591 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4592 uint64_t Address, 4593 const void *Decoder) { 4594 // Val is passed in as S:J1:J2:imm10:imm11 4595 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4596 // the encoded instruction. So here change to I1 and I2 values via: 4597 // I1 = NOT(J1 EOR S); 4598 // I2 = NOT(J2 EOR S); 4599 // and build the imm32 with one trailing zero as documented: 4600 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4601 unsigned S = (Val >> 23) & 1; 4602 unsigned J1 = (Val >> 22) & 1; 4603 unsigned J2 = (Val >> 21) & 1; 4604 unsigned I1 = !(J1 ^ S); 4605 unsigned I2 = !(J2 ^ S); 4606 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4607 int imm32 = SignExtend32<25>(tmp << 1); 4608 4609 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4610 true, 4, Inst, Decoder)) 4611 Inst.addOperand(MCOperand::createImm(imm32)); 4612 return MCDisassembler::Success; 4613 } 4614 4615 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4616 uint64_t Address, const void *Decoder) { 4617 if (Val & ~0xf) 4618 return MCDisassembler::Fail; 4619 4620 Inst.addOperand(MCOperand::createImm(Val)); 4621 return MCDisassembler::Success; 4622 } 4623 4624 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4625 uint64_t Address, const void *Decoder) { 4626 if (Val & ~0xf) 4627 return MCDisassembler::Fail; 4628 4629 Inst.addOperand(MCOperand::createImm(Val)); 4630 return MCDisassembler::Success; 4631 } 4632 4633 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4634 uint64_t Address, const void *Decoder) { 4635 DecodeStatus S = MCDisassembler::Success; 4636 const FeatureBitset &FeatureBits = 4637 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4638 4639 if (FeatureBits[ARM::FeatureMClass]) { 4640 unsigned ValLow = Val & 0xff; 4641 4642 // Validate the SYSm value first. 4643 switch (ValLow) { 4644 case 0: // apsr 4645 case 1: // iapsr 4646 case 2: // eapsr 4647 case 3: // xpsr 4648 case 5: // ipsr 4649 case 6: // epsr 4650 case 7: // iepsr 4651 case 8: // msp 4652 case 9: // psp 4653 case 16: // primask 4654 case 20: // control 4655 break; 4656 case 17: // basepri 4657 case 18: // basepri_max 4658 case 19: // faultmask 4659 if (!(FeatureBits[ARM::HasV7Ops])) 4660 // Values basepri, basepri_max and faultmask are only valid for v7m. 4661 return MCDisassembler::Fail; 4662 break; 4663 case 0x8a: // msplim_ns 4664 case 0x8b: // psplim_ns 4665 case 0x91: // basepri_ns 4666 case 0x93: // faultmask_ns 4667 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4668 return MCDisassembler::Fail; 4669 LLVM_FALLTHROUGH; 4670 case 10: // msplim 4671 case 11: // psplim 4672 case 0x88: // msp_ns 4673 case 0x89: // psp_ns 4674 case 0x90: // primask_ns 4675 case 0x94: // control_ns 4676 case 0x98: // sp_ns 4677 if (!(FeatureBits[ARM::Feature8MSecExt])) 4678 return MCDisassembler::Fail; 4679 break; 4680 default: 4681 // Architecturally defined as unpredictable 4682 S = MCDisassembler::SoftFail; 4683 break; 4684 } 4685 4686 if (Inst.getOpcode() == ARM::t2MSR_M) { 4687 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4688 if (!(FeatureBits[ARM::HasV7Ops])) { 4689 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4690 // unpredictable. 4691 if (Mask != 2) 4692 S = MCDisassembler::SoftFail; 4693 } 4694 else { 4695 // The ARMv7-M architecture stores an additional 2-bit mask value in 4696 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4697 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4698 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4699 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4700 // only if the processor includes the DSP extension. 4701 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4702 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4703 S = MCDisassembler::SoftFail; 4704 } 4705 } 4706 } else { 4707 // A/R class 4708 if (Val == 0) 4709 return MCDisassembler::Fail; 4710 } 4711 Inst.addOperand(MCOperand::createImm(Val)); 4712 return S; 4713 } 4714 4715 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4716 uint64_t Address, const void *Decoder) { 4717 unsigned R = fieldFromInstruction(Val, 5, 1); 4718 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4719 4720 // The table of encodings for these banked registers comes from B9.2.3 of the 4721 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4722 // neater. So by fiat, these values are UNPREDICTABLE: 4723 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4724 return MCDisassembler::Fail; 4725 4726 Inst.addOperand(MCOperand::createImm(Val)); 4727 return MCDisassembler::Success; 4728 } 4729 4730 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4731 uint64_t Address, const void *Decoder) { 4732 DecodeStatus S = MCDisassembler::Success; 4733 4734 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4735 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4736 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4737 4738 if (Rn == 0xF) 4739 S = MCDisassembler::SoftFail; 4740 4741 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4742 return MCDisassembler::Fail; 4743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4744 return MCDisassembler::Fail; 4745 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4746 return MCDisassembler::Fail; 4747 4748 return S; 4749 } 4750 4751 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4752 uint64_t Address, 4753 const void *Decoder) { 4754 DecodeStatus S = MCDisassembler::Success; 4755 4756 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4757 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4758 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4759 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4760 4761 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4762 return MCDisassembler::Fail; 4763 4764 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4765 S = MCDisassembler::SoftFail; 4766 4767 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4768 return MCDisassembler::Fail; 4769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4770 return MCDisassembler::Fail; 4771 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4772 return MCDisassembler::Fail; 4773 4774 return S; 4775 } 4776 4777 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4778 uint64_t Address, const void *Decoder) { 4779 DecodeStatus S = MCDisassembler::Success; 4780 4781 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4782 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4783 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4784 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4785 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4786 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4787 4788 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4789 4790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4791 return MCDisassembler::Fail; 4792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4793 return MCDisassembler::Fail; 4794 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4795 return MCDisassembler::Fail; 4796 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4797 return MCDisassembler::Fail; 4798 4799 return S; 4800 } 4801 4802 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4803 uint64_t Address, const void *Decoder) { 4804 DecodeStatus S = MCDisassembler::Success; 4805 4806 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4807 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4808 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4809 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4810 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4811 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4812 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4813 4814 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4815 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4816 4817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4818 return MCDisassembler::Fail; 4819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4820 return MCDisassembler::Fail; 4821 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4822 return MCDisassembler::Fail; 4823 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4824 return MCDisassembler::Fail; 4825 4826 return S; 4827 } 4828 4829 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4830 uint64_t Address, const void *Decoder) { 4831 DecodeStatus S = MCDisassembler::Success; 4832 4833 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4834 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4835 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4836 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4837 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4838 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4839 4840 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4841 4842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4843 return MCDisassembler::Fail; 4844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4845 return MCDisassembler::Fail; 4846 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4847 return MCDisassembler::Fail; 4848 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4849 return MCDisassembler::Fail; 4850 4851 return S; 4852 } 4853 4854 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4855 uint64_t Address, const void *Decoder) { 4856 DecodeStatus S = MCDisassembler::Success; 4857 4858 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4859 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4860 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4861 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4862 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4863 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4864 4865 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4866 4867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4868 return MCDisassembler::Fail; 4869 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4870 return MCDisassembler::Fail; 4871 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4872 return MCDisassembler::Fail; 4873 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4874 return MCDisassembler::Fail; 4875 4876 return S; 4877 } 4878 4879 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4880 uint64_t Address, const void *Decoder) { 4881 DecodeStatus S = MCDisassembler::Success; 4882 4883 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4884 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4885 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4886 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4887 unsigned size = fieldFromInstruction(Insn, 10, 2); 4888 4889 unsigned align = 0; 4890 unsigned index = 0; 4891 switch (size) { 4892 default: 4893 return MCDisassembler::Fail; 4894 case 0: 4895 if (fieldFromInstruction(Insn, 4, 1)) 4896 return MCDisassembler::Fail; // UNDEFINED 4897 index = fieldFromInstruction(Insn, 5, 3); 4898 break; 4899 case 1: 4900 if (fieldFromInstruction(Insn, 5, 1)) 4901 return MCDisassembler::Fail; // UNDEFINED 4902 index = fieldFromInstruction(Insn, 6, 2); 4903 if (fieldFromInstruction(Insn, 4, 1)) 4904 align = 2; 4905 break; 4906 case 2: 4907 if (fieldFromInstruction(Insn, 6, 1)) 4908 return MCDisassembler::Fail; // UNDEFINED 4909 index = fieldFromInstruction(Insn, 7, 1); 4910 4911 switch (fieldFromInstruction(Insn, 4, 2)) { 4912 case 0 : 4913 align = 0; break; 4914 case 3: 4915 align = 4; break; 4916 default: 4917 return MCDisassembler::Fail; 4918 } 4919 break; 4920 } 4921 4922 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4923 return MCDisassembler::Fail; 4924 if (Rm != 0xF) { // Writeback 4925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4926 return MCDisassembler::Fail; 4927 } 4928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4929 return MCDisassembler::Fail; 4930 Inst.addOperand(MCOperand::createImm(align)); 4931 if (Rm != 0xF) { 4932 if (Rm != 0xD) { 4933 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4934 return MCDisassembler::Fail; 4935 } else 4936 Inst.addOperand(MCOperand::createReg(0)); 4937 } 4938 4939 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4940 return MCDisassembler::Fail; 4941 Inst.addOperand(MCOperand::createImm(index)); 4942 4943 return S; 4944 } 4945 4946 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4947 uint64_t Address, const void *Decoder) { 4948 DecodeStatus S = MCDisassembler::Success; 4949 4950 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4951 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4952 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4953 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4954 unsigned size = fieldFromInstruction(Insn, 10, 2); 4955 4956 unsigned align = 0; 4957 unsigned index = 0; 4958 switch (size) { 4959 default: 4960 return MCDisassembler::Fail; 4961 case 0: 4962 if (fieldFromInstruction(Insn, 4, 1)) 4963 return MCDisassembler::Fail; // UNDEFINED 4964 index = fieldFromInstruction(Insn, 5, 3); 4965 break; 4966 case 1: 4967 if (fieldFromInstruction(Insn, 5, 1)) 4968 return MCDisassembler::Fail; // UNDEFINED 4969 index = fieldFromInstruction(Insn, 6, 2); 4970 if (fieldFromInstruction(Insn, 4, 1)) 4971 align = 2; 4972 break; 4973 case 2: 4974 if (fieldFromInstruction(Insn, 6, 1)) 4975 return MCDisassembler::Fail; // UNDEFINED 4976 index = fieldFromInstruction(Insn, 7, 1); 4977 4978 switch (fieldFromInstruction(Insn, 4, 2)) { 4979 case 0: 4980 align = 0; break; 4981 case 3: 4982 align = 4; break; 4983 default: 4984 return MCDisassembler::Fail; 4985 } 4986 break; 4987 } 4988 4989 if (Rm != 0xF) { // Writeback 4990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4991 return MCDisassembler::Fail; 4992 } 4993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4994 return MCDisassembler::Fail; 4995 Inst.addOperand(MCOperand::createImm(align)); 4996 if (Rm != 0xF) { 4997 if (Rm != 0xD) { 4998 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4999 return MCDisassembler::Fail; 5000 } else 5001 Inst.addOperand(MCOperand::createReg(0)); 5002 } 5003 5004 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5005 return MCDisassembler::Fail; 5006 Inst.addOperand(MCOperand::createImm(index)); 5007 5008 return S; 5009 } 5010 5011 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5012 uint64_t Address, const void *Decoder) { 5013 DecodeStatus S = MCDisassembler::Success; 5014 5015 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5016 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5017 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5018 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5019 unsigned size = fieldFromInstruction(Insn, 10, 2); 5020 5021 unsigned align = 0; 5022 unsigned index = 0; 5023 unsigned inc = 1; 5024 switch (size) { 5025 default: 5026 return MCDisassembler::Fail; 5027 case 0: 5028 index = fieldFromInstruction(Insn, 5, 3); 5029 if (fieldFromInstruction(Insn, 4, 1)) 5030 align = 2; 5031 break; 5032 case 1: 5033 index = fieldFromInstruction(Insn, 6, 2); 5034 if (fieldFromInstruction(Insn, 4, 1)) 5035 align = 4; 5036 if (fieldFromInstruction(Insn, 5, 1)) 5037 inc = 2; 5038 break; 5039 case 2: 5040 if (fieldFromInstruction(Insn, 5, 1)) 5041 return MCDisassembler::Fail; // UNDEFINED 5042 index = fieldFromInstruction(Insn, 7, 1); 5043 if (fieldFromInstruction(Insn, 4, 1) != 0) 5044 align = 8; 5045 if (fieldFromInstruction(Insn, 6, 1)) 5046 inc = 2; 5047 break; 5048 } 5049 5050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5051 return MCDisassembler::Fail; 5052 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5053 return MCDisassembler::Fail; 5054 if (Rm != 0xF) { // Writeback 5055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5056 return MCDisassembler::Fail; 5057 } 5058 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5059 return MCDisassembler::Fail; 5060 Inst.addOperand(MCOperand::createImm(align)); 5061 if (Rm != 0xF) { 5062 if (Rm != 0xD) { 5063 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5064 return MCDisassembler::Fail; 5065 } else 5066 Inst.addOperand(MCOperand::createReg(0)); 5067 } 5068 5069 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5070 return MCDisassembler::Fail; 5071 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5072 return MCDisassembler::Fail; 5073 Inst.addOperand(MCOperand::createImm(index)); 5074 5075 return S; 5076 } 5077 5078 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5079 uint64_t Address, const void *Decoder) { 5080 DecodeStatus S = MCDisassembler::Success; 5081 5082 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5083 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5084 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5085 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5086 unsigned size = fieldFromInstruction(Insn, 10, 2); 5087 5088 unsigned align = 0; 5089 unsigned index = 0; 5090 unsigned inc = 1; 5091 switch (size) { 5092 default: 5093 return MCDisassembler::Fail; 5094 case 0: 5095 index = fieldFromInstruction(Insn, 5, 3); 5096 if (fieldFromInstruction(Insn, 4, 1)) 5097 align = 2; 5098 break; 5099 case 1: 5100 index = fieldFromInstruction(Insn, 6, 2); 5101 if (fieldFromInstruction(Insn, 4, 1)) 5102 align = 4; 5103 if (fieldFromInstruction(Insn, 5, 1)) 5104 inc = 2; 5105 break; 5106 case 2: 5107 if (fieldFromInstruction(Insn, 5, 1)) 5108 return MCDisassembler::Fail; // UNDEFINED 5109 index = fieldFromInstruction(Insn, 7, 1); 5110 if (fieldFromInstruction(Insn, 4, 1) != 0) 5111 align = 8; 5112 if (fieldFromInstruction(Insn, 6, 1)) 5113 inc = 2; 5114 break; 5115 } 5116 5117 if (Rm != 0xF) { // Writeback 5118 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5119 return MCDisassembler::Fail; 5120 } 5121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5122 return MCDisassembler::Fail; 5123 Inst.addOperand(MCOperand::createImm(align)); 5124 if (Rm != 0xF) { 5125 if (Rm != 0xD) { 5126 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5127 return MCDisassembler::Fail; 5128 } else 5129 Inst.addOperand(MCOperand::createReg(0)); 5130 } 5131 5132 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5133 return MCDisassembler::Fail; 5134 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5135 return MCDisassembler::Fail; 5136 Inst.addOperand(MCOperand::createImm(index)); 5137 5138 return S; 5139 } 5140 5141 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5142 uint64_t Address, const void *Decoder) { 5143 DecodeStatus S = MCDisassembler::Success; 5144 5145 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5146 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5147 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5148 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5149 unsigned size = fieldFromInstruction(Insn, 10, 2); 5150 5151 unsigned align = 0; 5152 unsigned index = 0; 5153 unsigned inc = 1; 5154 switch (size) { 5155 default: 5156 return MCDisassembler::Fail; 5157 case 0: 5158 if (fieldFromInstruction(Insn, 4, 1)) 5159 return MCDisassembler::Fail; // UNDEFINED 5160 index = fieldFromInstruction(Insn, 5, 3); 5161 break; 5162 case 1: 5163 if (fieldFromInstruction(Insn, 4, 1)) 5164 return MCDisassembler::Fail; // UNDEFINED 5165 index = fieldFromInstruction(Insn, 6, 2); 5166 if (fieldFromInstruction(Insn, 5, 1)) 5167 inc = 2; 5168 break; 5169 case 2: 5170 if (fieldFromInstruction(Insn, 4, 2)) 5171 return MCDisassembler::Fail; // UNDEFINED 5172 index = fieldFromInstruction(Insn, 7, 1); 5173 if (fieldFromInstruction(Insn, 6, 1)) 5174 inc = 2; 5175 break; 5176 } 5177 5178 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5179 return MCDisassembler::Fail; 5180 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5181 return MCDisassembler::Fail; 5182 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5183 return MCDisassembler::Fail; 5184 5185 if (Rm != 0xF) { // Writeback 5186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5187 return MCDisassembler::Fail; 5188 } 5189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5190 return MCDisassembler::Fail; 5191 Inst.addOperand(MCOperand::createImm(align)); 5192 if (Rm != 0xF) { 5193 if (Rm != 0xD) { 5194 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5195 return MCDisassembler::Fail; 5196 } else 5197 Inst.addOperand(MCOperand::createReg(0)); 5198 } 5199 5200 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5201 return MCDisassembler::Fail; 5202 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5203 return MCDisassembler::Fail; 5204 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5205 return MCDisassembler::Fail; 5206 Inst.addOperand(MCOperand::createImm(index)); 5207 5208 return S; 5209 } 5210 5211 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5212 uint64_t Address, const void *Decoder) { 5213 DecodeStatus S = MCDisassembler::Success; 5214 5215 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5216 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5217 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5218 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5219 unsigned size = fieldFromInstruction(Insn, 10, 2); 5220 5221 unsigned align = 0; 5222 unsigned index = 0; 5223 unsigned inc = 1; 5224 switch (size) { 5225 default: 5226 return MCDisassembler::Fail; 5227 case 0: 5228 if (fieldFromInstruction(Insn, 4, 1)) 5229 return MCDisassembler::Fail; // UNDEFINED 5230 index = fieldFromInstruction(Insn, 5, 3); 5231 break; 5232 case 1: 5233 if (fieldFromInstruction(Insn, 4, 1)) 5234 return MCDisassembler::Fail; // UNDEFINED 5235 index = fieldFromInstruction(Insn, 6, 2); 5236 if (fieldFromInstruction(Insn, 5, 1)) 5237 inc = 2; 5238 break; 5239 case 2: 5240 if (fieldFromInstruction(Insn, 4, 2)) 5241 return MCDisassembler::Fail; // UNDEFINED 5242 index = fieldFromInstruction(Insn, 7, 1); 5243 if (fieldFromInstruction(Insn, 6, 1)) 5244 inc = 2; 5245 break; 5246 } 5247 5248 if (Rm != 0xF) { // Writeback 5249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5250 return MCDisassembler::Fail; 5251 } 5252 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5253 return MCDisassembler::Fail; 5254 Inst.addOperand(MCOperand::createImm(align)); 5255 if (Rm != 0xF) { 5256 if (Rm != 0xD) { 5257 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5258 return MCDisassembler::Fail; 5259 } else 5260 Inst.addOperand(MCOperand::createReg(0)); 5261 } 5262 5263 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5264 return MCDisassembler::Fail; 5265 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5266 return MCDisassembler::Fail; 5267 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5268 return MCDisassembler::Fail; 5269 Inst.addOperand(MCOperand::createImm(index)); 5270 5271 return S; 5272 } 5273 5274 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5275 uint64_t Address, const void *Decoder) { 5276 DecodeStatus S = MCDisassembler::Success; 5277 5278 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5279 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5280 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5281 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5282 unsigned size = fieldFromInstruction(Insn, 10, 2); 5283 5284 unsigned align = 0; 5285 unsigned index = 0; 5286 unsigned inc = 1; 5287 switch (size) { 5288 default: 5289 return MCDisassembler::Fail; 5290 case 0: 5291 if (fieldFromInstruction(Insn, 4, 1)) 5292 align = 4; 5293 index = fieldFromInstruction(Insn, 5, 3); 5294 break; 5295 case 1: 5296 if (fieldFromInstruction(Insn, 4, 1)) 5297 align = 8; 5298 index = fieldFromInstruction(Insn, 6, 2); 5299 if (fieldFromInstruction(Insn, 5, 1)) 5300 inc = 2; 5301 break; 5302 case 2: 5303 switch (fieldFromInstruction(Insn, 4, 2)) { 5304 case 0: 5305 align = 0; break; 5306 case 3: 5307 return MCDisassembler::Fail; 5308 default: 5309 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5310 } 5311 5312 index = fieldFromInstruction(Insn, 7, 1); 5313 if (fieldFromInstruction(Insn, 6, 1)) 5314 inc = 2; 5315 break; 5316 } 5317 5318 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5319 return MCDisassembler::Fail; 5320 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5321 return MCDisassembler::Fail; 5322 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5323 return MCDisassembler::Fail; 5324 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5325 return MCDisassembler::Fail; 5326 5327 if (Rm != 0xF) { // Writeback 5328 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5329 return MCDisassembler::Fail; 5330 } 5331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5332 return MCDisassembler::Fail; 5333 Inst.addOperand(MCOperand::createImm(align)); 5334 if (Rm != 0xF) { 5335 if (Rm != 0xD) { 5336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5337 return MCDisassembler::Fail; 5338 } else 5339 Inst.addOperand(MCOperand::createReg(0)); 5340 } 5341 5342 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5343 return MCDisassembler::Fail; 5344 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5345 return MCDisassembler::Fail; 5346 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5347 return MCDisassembler::Fail; 5348 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5349 return MCDisassembler::Fail; 5350 Inst.addOperand(MCOperand::createImm(index)); 5351 5352 return S; 5353 } 5354 5355 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5356 uint64_t Address, const void *Decoder) { 5357 DecodeStatus S = MCDisassembler::Success; 5358 5359 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5360 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5361 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5362 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5363 unsigned size = fieldFromInstruction(Insn, 10, 2); 5364 5365 unsigned align = 0; 5366 unsigned index = 0; 5367 unsigned inc = 1; 5368 switch (size) { 5369 default: 5370 return MCDisassembler::Fail; 5371 case 0: 5372 if (fieldFromInstruction(Insn, 4, 1)) 5373 align = 4; 5374 index = fieldFromInstruction(Insn, 5, 3); 5375 break; 5376 case 1: 5377 if (fieldFromInstruction(Insn, 4, 1)) 5378 align = 8; 5379 index = fieldFromInstruction(Insn, 6, 2); 5380 if (fieldFromInstruction(Insn, 5, 1)) 5381 inc = 2; 5382 break; 5383 case 2: 5384 switch (fieldFromInstruction(Insn, 4, 2)) { 5385 case 0: 5386 align = 0; break; 5387 case 3: 5388 return MCDisassembler::Fail; 5389 default: 5390 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5391 } 5392 5393 index = fieldFromInstruction(Insn, 7, 1); 5394 if (fieldFromInstruction(Insn, 6, 1)) 5395 inc = 2; 5396 break; 5397 } 5398 5399 if (Rm != 0xF) { // Writeback 5400 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5401 return MCDisassembler::Fail; 5402 } 5403 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5404 return MCDisassembler::Fail; 5405 Inst.addOperand(MCOperand::createImm(align)); 5406 if (Rm != 0xF) { 5407 if (Rm != 0xD) { 5408 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5409 return MCDisassembler::Fail; 5410 } else 5411 Inst.addOperand(MCOperand::createReg(0)); 5412 } 5413 5414 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5415 return MCDisassembler::Fail; 5416 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5417 return MCDisassembler::Fail; 5418 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5419 return MCDisassembler::Fail; 5420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5421 return MCDisassembler::Fail; 5422 Inst.addOperand(MCOperand::createImm(index)); 5423 5424 return S; 5425 } 5426 5427 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5428 uint64_t Address, const void *Decoder) { 5429 DecodeStatus S = MCDisassembler::Success; 5430 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5431 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5432 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5433 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5434 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5435 5436 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5437 S = MCDisassembler::SoftFail; 5438 5439 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5440 return MCDisassembler::Fail; 5441 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5442 return MCDisassembler::Fail; 5443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5444 return MCDisassembler::Fail; 5445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5446 return MCDisassembler::Fail; 5447 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5448 return MCDisassembler::Fail; 5449 5450 return S; 5451 } 5452 5453 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5454 uint64_t Address, const void *Decoder) { 5455 DecodeStatus S = MCDisassembler::Success; 5456 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5457 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5458 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5459 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5460 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5461 5462 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5463 S = MCDisassembler::SoftFail; 5464 5465 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5466 return MCDisassembler::Fail; 5467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5468 return MCDisassembler::Fail; 5469 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5470 return MCDisassembler::Fail; 5471 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5472 return MCDisassembler::Fail; 5473 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5474 return MCDisassembler::Fail; 5475 5476 return S; 5477 } 5478 5479 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5480 uint64_t Address, const void *Decoder) { 5481 DecodeStatus S = MCDisassembler::Success; 5482 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5483 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5484 5485 if (pred == 0xF) { 5486 pred = 0xE; 5487 S = MCDisassembler::SoftFail; 5488 } 5489 5490 if (mask == 0x0) 5491 return MCDisassembler::Fail; 5492 5493 // IT masks are encoded as a sequence of replacement low-order bits 5494 // for the condition code. So if the low bit of the starting 5495 // condition code is 1, then we have to flip all the bits above the 5496 // terminating bit (which is the lowest 1 bit). 5497 if (pred & 1) { 5498 unsigned LowBit = mask & -mask; 5499 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5500 mask ^= BitsAboveLowBit; 5501 } 5502 5503 Inst.addOperand(MCOperand::createImm(pred)); 5504 Inst.addOperand(MCOperand::createImm(mask)); 5505 return S; 5506 } 5507 5508 static DecodeStatus 5509 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5510 uint64_t Address, const void *Decoder) { 5511 DecodeStatus S = MCDisassembler::Success; 5512 5513 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5514 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5515 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5516 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5517 unsigned W = fieldFromInstruction(Insn, 21, 1); 5518 unsigned U = fieldFromInstruction(Insn, 23, 1); 5519 unsigned P = fieldFromInstruction(Insn, 24, 1); 5520 bool writeback = (W == 1) | (P == 0); 5521 5522 addr |= (U << 8) | (Rn << 9); 5523 5524 if (writeback && (Rn == Rt || Rn == Rt2)) 5525 Check(S, MCDisassembler::SoftFail); 5526 if (Rt == Rt2) 5527 Check(S, MCDisassembler::SoftFail); 5528 5529 // Rt 5530 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5531 return MCDisassembler::Fail; 5532 // Rt2 5533 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5534 return MCDisassembler::Fail; 5535 // Writeback operand 5536 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5537 return MCDisassembler::Fail; 5538 // addr 5539 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5540 return MCDisassembler::Fail; 5541 5542 return S; 5543 } 5544 5545 static DecodeStatus 5546 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5547 uint64_t Address, const void *Decoder) { 5548 DecodeStatus S = MCDisassembler::Success; 5549 5550 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5551 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5552 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5553 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5554 unsigned W = fieldFromInstruction(Insn, 21, 1); 5555 unsigned U = fieldFromInstruction(Insn, 23, 1); 5556 unsigned P = fieldFromInstruction(Insn, 24, 1); 5557 bool writeback = (W == 1) | (P == 0); 5558 5559 addr |= (U << 8) | (Rn << 9); 5560 5561 if (writeback && (Rn == Rt || Rn == Rt2)) 5562 Check(S, MCDisassembler::SoftFail); 5563 5564 // Writeback operand 5565 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5566 return MCDisassembler::Fail; 5567 // Rt 5568 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5569 return MCDisassembler::Fail; 5570 // Rt2 5571 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5572 return MCDisassembler::Fail; 5573 // addr 5574 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5575 return MCDisassembler::Fail; 5576 5577 return S; 5578 } 5579 5580 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5581 uint64_t Address, const void *Decoder) { 5582 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5583 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5584 if (sign1 != sign2) return MCDisassembler::Fail; 5585 5586 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5587 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5588 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5589 Val |= sign1 << 12; 5590 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5591 5592 return MCDisassembler::Success; 5593 } 5594 5595 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5596 uint64_t Address, 5597 const void *Decoder) { 5598 DecodeStatus S = MCDisassembler::Success; 5599 5600 // Shift of "asr #32" is not allowed in Thumb2 mode. 5601 if (Val == 0x20) S = MCDisassembler::Fail; 5602 Inst.addOperand(MCOperand::createImm(Val)); 5603 return S; 5604 } 5605 5606 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5607 uint64_t Address, const void *Decoder) { 5608 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5609 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5610 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5611 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5612 5613 if (pred == 0xF) 5614 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5615 5616 DecodeStatus S = MCDisassembler::Success; 5617 5618 if (Rt == Rn || Rn == Rt2) 5619 S = MCDisassembler::SoftFail; 5620 5621 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5622 return MCDisassembler::Fail; 5623 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5624 return MCDisassembler::Fail; 5625 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5626 return MCDisassembler::Fail; 5627 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5628 return MCDisassembler::Fail; 5629 5630 return S; 5631 } 5632 5633 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5634 uint64_t Address, const void *Decoder) { 5635 const FeatureBitset &featureBits = 5636 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5637 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5638 5639 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5640 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5641 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5642 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5643 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5644 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5645 unsigned op = fieldFromInstruction(Insn, 5, 1); 5646 5647 DecodeStatus S = MCDisassembler::Success; 5648 5649 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5650 if (!(imm & 0x38)) { 5651 if (cmode == 0xF) { 5652 if (op == 1) return MCDisassembler::Fail; 5653 Inst.setOpcode(ARM::VMOVv2f32); 5654 } 5655 if (hasFullFP16) { 5656 if (cmode == 0xE) { 5657 if (op == 1) { 5658 Inst.setOpcode(ARM::VMOVv1i64); 5659 } else { 5660 Inst.setOpcode(ARM::VMOVv8i8); 5661 } 5662 } 5663 if (cmode == 0xD) { 5664 if (op == 1) { 5665 Inst.setOpcode(ARM::VMVNv2i32); 5666 } else { 5667 Inst.setOpcode(ARM::VMOVv2i32); 5668 } 5669 } 5670 if (cmode == 0xC) { 5671 if (op == 1) { 5672 Inst.setOpcode(ARM::VMVNv2i32); 5673 } else { 5674 Inst.setOpcode(ARM::VMOVv2i32); 5675 } 5676 } 5677 } 5678 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5679 } 5680 5681 if (!(imm & 0x20)) return MCDisassembler::Fail; 5682 5683 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5684 return MCDisassembler::Fail; 5685 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5686 return MCDisassembler::Fail; 5687 Inst.addOperand(MCOperand::createImm(64 - imm)); 5688 5689 return S; 5690 } 5691 5692 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5693 uint64_t Address, const void *Decoder) { 5694 const FeatureBitset &featureBits = 5695 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5696 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5697 5698 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5699 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5700 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5701 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5702 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5703 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5704 unsigned op = fieldFromInstruction(Insn, 5, 1); 5705 5706 DecodeStatus S = MCDisassembler::Success; 5707 5708 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5709 if (!(imm & 0x38)) { 5710 if (cmode == 0xF) { 5711 if (op == 1) return MCDisassembler::Fail; 5712 Inst.setOpcode(ARM::VMOVv4f32); 5713 } 5714 if (hasFullFP16) { 5715 if (cmode == 0xE) { 5716 if (op == 1) { 5717 Inst.setOpcode(ARM::VMOVv2i64); 5718 } else { 5719 Inst.setOpcode(ARM::VMOVv16i8); 5720 } 5721 } 5722 if (cmode == 0xD) { 5723 if (op == 1) { 5724 Inst.setOpcode(ARM::VMVNv4i32); 5725 } else { 5726 Inst.setOpcode(ARM::VMOVv4i32); 5727 } 5728 } 5729 if (cmode == 0xC) { 5730 if (op == 1) { 5731 Inst.setOpcode(ARM::VMVNv4i32); 5732 } else { 5733 Inst.setOpcode(ARM::VMOVv4i32); 5734 } 5735 } 5736 } 5737 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5738 } 5739 5740 if (!(imm & 0x20)) return MCDisassembler::Fail; 5741 5742 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5743 return MCDisassembler::Fail; 5744 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5745 return MCDisassembler::Fail; 5746 Inst.addOperand(MCOperand::createImm(64 - imm)); 5747 5748 return S; 5749 } 5750 5751 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5752 unsigned Insn, 5753 uint64_t Address, 5754 const void *Decoder) { 5755 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5756 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5757 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5758 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5759 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5760 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5761 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5762 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5763 5764 DecodeStatus S = MCDisassembler::Success; 5765 5766 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5767 5768 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5769 return MCDisassembler::Fail; 5770 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5771 return MCDisassembler::Fail; 5772 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5773 return MCDisassembler::Fail; 5774 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5775 return MCDisassembler::Fail; 5776 // The lane index does not have any bits in the encoding, because it can only 5777 // be 0. 5778 Inst.addOperand(MCOperand::createImm(0)); 5779 Inst.addOperand(MCOperand::createImm(rotate)); 5780 5781 return S; 5782 } 5783 5784 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5785 uint64_t Address, const void *Decoder) { 5786 DecodeStatus S = MCDisassembler::Success; 5787 5788 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5789 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5790 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5791 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5792 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5793 5794 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5795 S = MCDisassembler::SoftFail; 5796 5797 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5798 return MCDisassembler::Fail; 5799 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5800 return MCDisassembler::Fail; 5801 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5802 return MCDisassembler::Fail; 5803 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5804 return MCDisassembler::Fail; 5805 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5806 return MCDisassembler::Fail; 5807 5808 return S; 5809 } 5810 5811 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5812 uint64_t Address, const void *Decoder) { 5813 DecodeStatus S = MCDisassembler::Success; 5814 5815 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5816 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5817 unsigned cop = fieldFromInstruction(Val, 8, 4); 5818 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5819 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5820 5821 if ((cop & ~0x1) == 0xa) 5822 return MCDisassembler::Fail; 5823 5824 if (Rt == Rt2) 5825 S = MCDisassembler::SoftFail; 5826 5827 // We have to check if the instruction is MRRC2 5828 // or MCRR2 when constructing the operands for 5829 // Inst. Reason is because MRRC2 stores to two 5830 // registers so it's tablegen desc has has two 5831 // outputs whereas MCRR doesn't store to any 5832 // registers so all of it's operands are listed 5833 // as inputs, therefore the operand order for 5834 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5835 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5836 5837 if (Inst.getOpcode() == ARM::MRRC2) { 5838 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5839 return MCDisassembler::Fail; 5840 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5841 return MCDisassembler::Fail; 5842 } 5843 Inst.addOperand(MCOperand::createImm(cop)); 5844 Inst.addOperand(MCOperand::createImm(opc1)); 5845 if (Inst.getOpcode() == ARM::MCRR2) { 5846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5847 return MCDisassembler::Fail; 5848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5849 return MCDisassembler::Fail; 5850 } 5851 Inst.addOperand(MCOperand::createImm(CRm)); 5852 5853 return S; 5854 } 5855 5856 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5857 uint64_t Address, 5858 const void *Decoder) { 5859 const FeatureBitset &featureBits = 5860 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5861 DecodeStatus S = MCDisassembler::Success; 5862 5863 // Add explicit operand for the destination sysreg, for cases where 5864 // we have to model it for code generation purposes. 5865 switch (Inst.getOpcode()) { 5866 case ARM::VMSR_FPSCR_NZCVQC: 5867 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5868 break; 5869 case ARM::VMSR_P0: 5870 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5871 break; 5872 } 5873 5874 if (Inst.getOpcode() != ARM::FMSTAT) { 5875 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5876 5877 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5878 if (Rt == 13 || Rt == 15) 5879 S = MCDisassembler::SoftFail; 5880 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5881 } else 5882 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5883 } 5884 5885 // Add explicit operand for the source sysreg, similarly to above. 5886 switch (Inst.getOpcode()) { 5887 case ARM::VMRS_FPSCR_NZCVQC: 5888 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5889 break; 5890 case ARM::VMRS_P0: 5891 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5892 break; 5893 } 5894 5895 if (featureBits[ARM::ModeThumb]) { 5896 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5897 Inst.addOperand(MCOperand::createReg(0)); 5898 } else { 5899 unsigned pred = fieldFromInstruction(Val, 28, 4); 5900 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5901 return MCDisassembler::Fail; 5902 } 5903 5904 return S; 5905 } 5906 5907 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 5908 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5909 uint64_t Address, 5910 const void *Decoder) { 5911 DecodeStatus S = MCDisassembler::Success; 5912 if (Val == 0 && !zeroPermitted) 5913 S = MCDisassembler::Fail; 5914 5915 uint64_t DecVal; 5916 if (isSigned) 5917 DecVal = SignExtend32<size + 1>(Val << 1); 5918 else 5919 DecVal = (Val << 1); 5920 5921 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5922 Decoder)) 5923 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5924 return S; 5925 } 5926 5927 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5928 uint64_t Address, 5929 const void *Decoder) { 5930 5931 uint64_t LocImm = Inst.getOperand(0).getImm(); 5932 Val = LocImm + (2 << Val); 5933 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5934 Decoder)) 5935 Inst.addOperand(MCOperand::createImm(Val)); 5936 return MCDisassembler::Success; 5937 } 5938 5939 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5940 uint64_t Address, 5941 const void *Decoder) { 5942 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5943 return MCDisassembler::Fail; 5944 Inst.addOperand(MCOperand::createImm(Val)); 5945 return MCDisassembler::Success; 5946 } 5947 5948 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5949 const void *Decoder) { 5950 DecodeStatus S = MCDisassembler::Success; 5951 5952 if (Inst.getOpcode() == ARM::MVE_LCTP) 5953 return S; 5954 5955 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5956 fieldFromInstruction(Insn, 1, 10) << 1; 5957 switch (Inst.getOpcode()) { 5958 case ARM::t2LEUpdate: 5959 case ARM::MVE_LETP: 5960 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5961 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5962 LLVM_FALLTHROUGH; 5963 case ARM::t2LE: 5964 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 5965 Inst, Imm, Address, Decoder))) 5966 return MCDisassembler::Fail; 5967 break; 5968 case ARM::t2WLS: 5969 case ARM::MVE_WLSTP_8: 5970 case ARM::MVE_WLSTP_16: 5971 case ARM::MVE_WLSTP_32: 5972 case ARM::MVE_WLSTP_64: 5973 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5974 if (!Check(S, 5975 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5976 Address, Decoder)) || 5977 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 5978 Inst, Imm, Address, Decoder))) 5979 return MCDisassembler::Fail; 5980 break; 5981 case ARM::t2DLS: 5982 case ARM::MVE_DLSTP_8: 5983 case ARM::MVE_DLSTP_16: 5984 case ARM::MVE_DLSTP_32: 5985 case ARM::MVE_DLSTP_64: 5986 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5987 if (Rn == 0xF) { 5988 // Enforce all the rest of the instruction bits in LCTP, which 5989 // won't have been reliably checked based on LCTP's own tablegen 5990 // record, because we came to this decode by a roundabout route. 5991 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 5992 if ((Insn & ~SBZMask) != CanonicalLCTP) 5993 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 5994 if (Insn != CanonicalLCTP) 5995 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 5996 5997 Inst.setOpcode(ARM::MVE_LCTP); 5998 } else { 5999 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6000 if (!Check(S, DecoderGPRRegisterClass(Inst, 6001 fieldFromInstruction(Insn, 16, 4), 6002 Address, Decoder))) 6003 return MCDisassembler::Fail; 6004 } 6005 break; 6006 } 6007 return S; 6008 } 6009 6010 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6011 uint64_t Address, 6012 const void *Decoder) { 6013 DecodeStatus S = MCDisassembler::Success; 6014 6015 if (Val == 0) 6016 Val = 32; 6017 6018 Inst.addOperand(MCOperand::createImm(Val)); 6019 6020 return S; 6021 } 6022 6023 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6024 uint64_t Address, const void *Decoder) { 6025 if ((RegNo) + 1 > 11) 6026 return MCDisassembler::Fail; 6027 6028 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6029 Inst.addOperand(MCOperand::createReg(Register)); 6030 return MCDisassembler::Success; 6031 } 6032 6033 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6034 uint64_t Address, const void *Decoder) { 6035 if ((RegNo) > 14) 6036 return MCDisassembler::Fail; 6037 6038 unsigned Register = GPRDecoderTable[(RegNo)]; 6039 Inst.addOperand(MCOperand::createReg(Register)); 6040 return MCDisassembler::Success; 6041 } 6042 6043 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6044 const void *Decoder) { 6045 DecodeStatus S = MCDisassembler::Success; 6046 6047 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6048 Inst.addOperand(MCOperand::createReg(0)); 6049 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6050 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6051 (fieldFromInstruction(Insn, 12, 4) << 8) | 6052 (fieldFromInstruction(Insn, 22, 1) << 12); 6053 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6054 return MCDisassembler::Fail; 6055 } 6056 } else { 6057 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6058 (fieldFromInstruction(Insn, 22, 1) << 8) | 6059 (fieldFromInstruction(Insn, 12, 4) << 9); 6060 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6061 return MCDisassembler::Fail; 6062 } 6063 } 6064 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6065 6066 return S; 6067 } 6068 6069 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6070 uint64_t Address, 6071 const void *Decoder) { 6072 if (RegNo > 7) 6073 return MCDisassembler::Fail; 6074 6075 unsigned Register = QPRDecoderTable[RegNo]; 6076 Inst.addOperand(MCOperand::createReg(Register)); 6077 return MCDisassembler::Success; 6078 } 6079 6080 static const uint16_t QQPRDecoderTable[] = { 6081 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6082 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6083 }; 6084 6085 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6086 uint64_t Address, 6087 const void *Decoder) { 6088 if (RegNo > 6) 6089 return MCDisassembler::Fail; 6090 6091 unsigned Register = QQPRDecoderTable[RegNo]; 6092 Inst.addOperand(MCOperand::createReg(Register)); 6093 return MCDisassembler::Success; 6094 } 6095 6096 static const uint16_t QQQQPRDecoderTable[] = { 6097 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6098 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6099 }; 6100 6101 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6102 uint64_t Address, 6103 const void *Decoder) { 6104 if (RegNo > 4) 6105 return MCDisassembler::Fail; 6106 6107 unsigned Register = QQQQPRDecoderTable[RegNo]; 6108 Inst.addOperand(MCOperand::createReg(Register)); 6109 return MCDisassembler::Success; 6110 } 6111 6112 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6113 uint64_t Address, 6114 const void *Decoder) { 6115 DecodeStatus S = MCDisassembler::Success; 6116 6117 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6118 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6119 // 't' as 0 and finish with a 1. 6120 unsigned Imm = 0; 6121 // We always start with a 't'. 6122 unsigned CurBit = 0; 6123 for (int i = 3; i >= 0; --i) { 6124 // If the bit we are looking at is not the same as last one, invert the 6125 // CurBit, if it is the same leave it as is. 6126 CurBit ^= (Val >> i) & 1U; 6127 6128 // Encode the CurBit at the right place in the immediate. 6129 Imm |= (CurBit << i); 6130 6131 // If we are done, finish the encoding with a 1. 6132 if ((Val & ~(~0U << i)) == 0) { 6133 Imm |= 1U << i; 6134 break; 6135 } 6136 } 6137 6138 Inst.addOperand(MCOperand::createImm(Imm)); 6139 6140 return S; 6141 } 6142 6143 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6144 uint64_t Address, const void *Decoder) { 6145 // The vpred_r operand type includes an MQPR register field derived 6146 // from the encoding. But we don't actually want to add an operand 6147 // to the MCInst at this stage, because AddThumbPredicate will do it 6148 // later, and will infer the register number from the TIED_TO 6149 // constraint. So this is a deliberately empty decoder method that 6150 // will inhibit the auto-generated disassembly code from adding an 6151 // operand at all. 6152 return MCDisassembler::Success; 6153 } 6154 6155 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6156 unsigned Val, 6157 uint64_t Address, 6158 const void *Decoder) { 6159 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6160 return MCDisassembler::Success; 6161 } 6162 6163 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6164 unsigned Val, 6165 uint64_t Address, 6166 const void *Decoder) { 6167 unsigned Code; 6168 switch (Val & 0x3) { 6169 case 0: 6170 Code = ARMCC::GE; 6171 break; 6172 case 1: 6173 Code = ARMCC::LT; 6174 break; 6175 case 2: 6176 Code = ARMCC::GT; 6177 break; 6178 case 3: 6179 Code = ARMCC::LE; 6180 break; 6181 } 6182 Inst.addOperand(MCOperand::createImm(Code)); 6183 return MCDisassembler::Success; 6184 } 6185 6186 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6187 unsigned Val, 6188 uint64_t Address, 6189 const void *Decoder) { 6190 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6191 return MCDisassembler::Success; 6192 } 6193 6194 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6195 uint64_t Address, 6196 const void *Decoder) { 6197 unsigned Code; 6198 switch (Val) { 6199 default: 6200 return MCDisassembler::Fail; 6201 case 0: 6202 Code = ARMCC::EQ; 6203 break; 6204 case 1: 6205 Code = ARMCC::NE; 6206 break; 6207 case 4: 6208 Code = ARMCC::GE; 6209 break; 6210 case 5: 6211 Code = ARMCC::LT; 6212 break; 6213 case 6: 6214 Code = ARMCC::GT; 6215 break; 6216 case 7: 6217 Code = ARMCC::LE; 6218 break; 6219 } 6220 6221 Inst.addOperand(MCOperand::createImm(Code)); 6222 return MCDisassembler::Success; 6223 } 6224 6225 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6226 uint64_t Address, const void *Decoder) { 6227 DecodeStatus S = MCDisassembler::Success; 6228 6229 unsigned DecodedVal = 64 - Val; 6230 6231 switch (Inst.getOpcode()) { 6232 case ARM::MVE_VCVTf16s16_fix: 6233 case ARM::MVE_VCVTs16f16_fix: 6234 case ARM::MVE_VCVTf16u16_fix: 6235 case ARM::MVE_VCVTu16f16_fix: 6236 if (DecodedVal > 16) 6237 return MCDisassembler::Fail; 6238 break; 6239 case ARM::MVE_VCVTf32s32_fix: 6240 case ARM::MVE_VCVTs32f32_fix: 6241 case ARM::MVE_VCVTf32u32_fix: 6242 case ARM::MVE_VCVTu32f32_fix: 6243 if (DecodedVal > 32) 6244 return MCDisassembler::Fail; 6245 break; 6246 } 6247 6248 Inst.addOperand(MCOperand::createImm(64 - Val)); 6249 6250 return S; 6251 } 6252 6253 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6254 switch (Opcode) { 6255 case ARM::VSTR_P0_off: 6256 case ARM::VSTR_P0_pre: 6257 case ARM::VSTR_P0_post: 6258 case ARM::VLDR_P0_off: 6259 case ARM::VLDR_P0_pre: 6260 case ARM::VLDR_P0_post: 6261 return ARM::P0; 6262 default: 6263 return 0; 6264 } 6265 } 6266 6267 template<bool Writeback> 6268 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6269 uint64_t Address, 6270 const void *Decoder) { 6271 switch (Inst.getOpcode()) { 6272 case ARM::VSTR_FPSCR_pre: 6273 case ARM::VSTR_FPSCR_NZCVQC_pre: 6274 case ARM::VLDR_FPSCR_pre: 6275 case ARM::VLDR_FPSCR_NZCVQC_pre: 6276 case ARM::VSTR_FPSCR_off: 6277 case ARM::VSTR_FPSCR_NZCVQC_off: 6278 case ARM::VLDR_FPSCR_off: 6279 case ARM::VLDR_FPSCR_NZCVQC_off: 6280 case ARM::VSTR_FPSCR_post: 6281 case ARM::VSTR_FPSCR_NZCVQC_post: 6282 case ARM::VLDR_FPSCR_post: 6283 case ARM::VLDR_FPSCR_NZCVQC_post: 6284 const FeatureBitset &featureBits = 6285 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6286 6287 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6288 return MCDisassembler::Fail; 6289 } 6290 6291 DecodeStatus S = MCDisassembler::Success; 6292 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6293 Inst.addOperand(MCOperand::createReg(Sysreg)); 6294 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6295 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6296 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6297 6298 if (Writeback) { 6299 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6300 return MCDisassembler::Fail; 6301 } 6302 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6303 return MCDisassembler::Fail; 6304 6305 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6306 Inst.addOperand(MCOperand::createReg(0)); 6307 6308 return S; 6309 } 6310 6311 static inline DecodeStatus DecodeMVE_MEM_pre( 6312 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6313 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6314 DecodeStatus S = MCDisassembler::Success; 6315 6316 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6317 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6318 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6319 6320 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6321 return MCDisassembler::Fail; 6322 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6323 return MCDisassembler::Fail; 6324 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6325 return MCDisassembler::Fail; 6326 6327 return S; 6328 } 6329 6330 template <int shift> 6331 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6332 uint64_t Address, const void *Decoder) { 6333 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6334 fieldFromInstruction(Val, 16, 3), 6335 DecodetGPRRegisterClass, 6336 DecodeTAddrModeImm7<shift>); 6337 } 6338 6339 template <int shift> 6340 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6341 uint64_t Address, const void *Decoder) { 6342 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6343 fieldFromInstruction(Val, 16, 4), 6344 DecoderGPRRegisterClass, 6345 DecodeT2AddrModeImm7<shift,1>); 6346 } 6347 6348 template <int shift> 6349 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6350 uint64_t Address, const void *Decoder) { 6351 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6352 fieldFromInstruction(Val, 17, 3), 6353 DecodeMQPRRegisterClass, 6354 DecodeMveAddrModeQ<shift>); 6355 } 6356 6357 template<unsigned MinLog, unsigned MaxLog> 6358 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6359 uint64_t Address, 6360 const void *Decoder) { 6361 DecodeStatus S = MCDisassembler::Success; 6362 6363 if (Val < MinLog || Val > MaxLog) 6364 return MCDisassembler::Fail; 6365 6366 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6367 return S; 6368 } 6369 6370 template <int shift> 6371 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6372 uint64_t Address, 6373 const void *Decoder) { 6374 Val <<= shift; 6375 6376 Inst.addOperand(MCOperand::createImm(Val)); 6377 return MCDisassembler::Success; 6378 } 6379 6380 template<unsigned start> 6381 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6382 uint64_t Address, 6383 const void *Decoder) { 6384 DecodeStatus S = MCDisassembler::Success; 6385 6386 Inst.addOperand(MCOperand::createImm(start + Val)); 6387 6388 return S; 6389 } 6390 6391 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6392 uint64_t Address, const void *Decoder) { 6393 DecodeStatus S = MCDisassembler::Success; 6394 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6395 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6396 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6397 fieldFromInstruction(Insn, 13, 3)); 6398 unsigned index = fieldFromInstruction(Insn, 4, 1); 6399 6400 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6401 return MCDisassembler::Fail; 6402 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6403 return MCDisassembler::Fail; 6404 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6405 return MCDisassembler::Fail; 6406 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6407 return MCDisassembler::Fail; 6408 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6409 return MCDisassembler::Fail; 6410 6411 return S; 6412 } 6413 6414 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6415 uint64_t Address, const void *Decoder) { 6416 DecodeStatus S = MCDisassembler::Success; 6417 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6418 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6419 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6420 fieldFromInstruction(Insn, 13, 3)); 6421 unsigned index = fieldFromInstruction(Insn, 4, 1); 6422 6423 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6424 return MCDisassembler::Fail; 6425 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6426 return MCDisassembler::Fail; 6427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6428 return MCDisassembler::Fail; 6429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6430 return MCDisassembler::Fail; 6431 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6432 return MCDisassembler::Fail; 6433 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6434 return MCDisassembler::Fail; 6435 6436 return S; 6437 } 6438 6439 static DecodeStatus DecodeMVEOverlappingLongShift( 6440 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6441 DecodeStatus S = MCDisassembler::Success; 6442 6443 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6444 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6445 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6446 6447 if (RdaHi == 14) { 6448 // This value of RdaHi (really indicating pc, because RdaHi has to 6449 // be an odd-numbered register, so the low bit will be set by the 6450 // decode function below) indicates that we must decode as SQRSHR 6451 // or UQRSHL, which both have a single Rda register field with all 6452 // four bits. 6453 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6454 6455 switch (Inst.getOpcode()) { 6456 case ARM::MVE_ASRLr: 6457 case ARM::MVE_SQRSHRL: 6458 Inst.setOpcode(ARM::MVE_SQRSHR); 6459 break; 6460 case ARM::MVE_LSLLr: 6461 case ARM::MVE_UQRSHLL: 6462 Inst.setOpcode(ARM::MVE_UQRSHL); 6463 break; 6464 default: 6465 llvm_unreachable("Unexpected starting opcode!"); 6466 } 6467 6468 // Rda as output parameter 6469 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6470 return MCDisassembler::Fail; 6471 6472 // Rda again as input parameter 6473 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6474 return MCDisassembler::Fail; 6475 6476 // Rm, the amount to shift by 6477 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6478 return MCDisassembler::Fail; 6479 6480 if (fieldFromInstruction (Insn, 6, 3) != 4) 6481 return MCDisassembler::SoftFail; 6482 6483 if (Rda == Rm) 6484 return MCDisassembler::SoftFail; 6485 6486 return S; 6487 } 6488 6489 // Otherwise, we decode as whichever opcode our caller has already 6490 // put into Inst. Those all look the same: 6491 6492 // RdaLo,RdaHi as output parameters 6493 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6494 return MCDisassembler::Fail; 6495 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6496 return MCDisassembler::Fail; 6497 6498 // RdaLo,RdaHi again as input parameters 6499 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6500 return MCDisassembler::Fail; 6501 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6502 return MCDisassembler::Fail; 6503 6504 // Rm, the amount to shift by 6505 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6506 return MCDisassembler::Fail; 6507 6508 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6509 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6510 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6511 // Saturate, the bit position for saturation 6512 Inst.addOperand(MCOperand::createImm(Saturate)); 6513 } 6514 6515 return S; 6516 } 6517 6518 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6519 const void *Decoder) { 6520 DecodeStatus S = MCDisassembler::Success; 6521 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6522 fieldFromInstruction(Insn, 13, 3)); 6523 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6524 fieldFromInstruction(Insn, 1, 3)); 6525 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6526 6527 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6528 return MCDisassembler::Fail; 6529 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6530 return MCDisassembler::Fail; 6531 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6532 return MCDisassembler::Fail; 6533 6534 return S; 6535 } 6536 6537 template<bool scalar, OperandDecoder predicate_decoder> 6538 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6539 const void *Decoder) { 6540 DecodeStatus S = MCDisassembler::Success; 6541 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6542 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6543 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6544 return MCDisassembler::Fail; 6545 6546 unsigned fc; 6547 6548 if (scalar) { 6549 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6550 fieldFromInstruction(Insn, 7, 1) | 6551 fieldFromInstruction(Insn, 5, 1) << 1; 6552 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6553 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6554 return MCDisassembler::Fail; 6555 } else { 6556 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6557 fieldFromInstruction(Insn, 7, 1) | 6558 fieldFromInstruction(Insn, 0, 1) << 1; 6559 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6560 fieldFromInstruction(Insn, 1, 3); 6561 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6562 return MCDisassembler::Fail; 6563 } 6564 6565 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6566 return MCDisassembler::Fail; 6567 6568 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6569 Inst.addOperand(MCOperand::createReg(0)); 6570 Inst.addOperand(MCOperand::createImm(0)); 6571 6572 return S; 6573 } 6574 6575 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6576 const void *Decoder) { 6577 DecodeStatus S = MCDisassembler::Success; 6578 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6579 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6580 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6581 return MCDisassembler::Fail; 6582 return S; 6583 } 6584 6585 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6586 const void *Decoder) { 6587 DecodeStatus S = MCDisassembler::Success; 6588 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6589 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6590 return S; 6591 } 6592