1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/ARMAddressingModes.h" 10 #include "MCTargetDesc/ARMBaseInfo.h" 11 #include "MCTargetDesc/ARMMCTargetDesc.h" 12 #include "Utils/ARMBaseInfo.h" 13 #include "llvm/MC/MCContext.h" 14 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 15 #include "llvm/MC/MCFixedLenDisassembler.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include "llvm/MC/MCSubtargetInfo.h" 19 #include "llvm/MC/SubtargetFeature.h" 20 #include "llvm/Support/Compiler.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <algorithm> 26 #include <cassert> 27 #include <cstdint> 28 #include <vector> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "arm-disassembler" 33 34 using DecodeStatus = MCDisassembler::DecodeStatus; 35 36 namespace { 37 38 // Handles the condition code status of instructions in IT blocks 39 class ITStatus 40 { 41 public: 42 // Returns the condition code for instruction in IT block 43 unsigned getITCC() { 44 unsigned CC = ARMCC::AL; 45 if (instrInITBlock()) 46 CC = ITStates.back(); 47 return CC; 48 } 49 50 // Advances the IT block state to the next T or E 51 void advanceITState() { 52 ITStates.pop_back(); 53 } 54 55 // Returns true if the current instruction is in an IT block 56 bool instrInITBlock() { 57 return !ITStates.empty(); 58 } 59 60 // Returns true if current instruction is the last instruction in an IT block 61 bool instrLastInITBlock() { 62 return ITStates.size() == 1; 63 } 64 65 // Called when decoding an IT instruction. Sets the IT state for the following 66 // instructions that for the IT block. Firstcond and Mask correspond to the 67 // fields in the IT instruction encoding. 68 void setITState(char Firstcond, char Mask) { 69 // (3 - the number of trailing zeros) is the number of then / else. 70 unsigned CondBit0 = Firstcond & 1; 71 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 72 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 73 assert(NumTZ <= 3 && "Invalid IT mask!"); 74 // push condition codes onto the stack the correct order for the pops 75 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 76 bool T = ((Mask >> Pos) & 1) == CondBit0; 77 if (T) 78 ITStates.push_back(CCBits); 79 else 80 ITStates.push_back(CCBits ^ 1); 81 } 82 ITStates.push_back(CCBits); 83 } 84 85 private: 86 std::vector<unsigned char> ITStates; 87 }; 88 89 /// ARM disassembler for all ARM platforms. 90 class ARMDisassembler : public MCDisassembler { 91 public: 92 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 93 MCDisassembler(STI, Ctx) { 94 } 95 96 ~ARMDisassembler() override = default; 97 98 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 99 ArrayRef<uint8_t> Bytes, uint64_t Address, 100 raw_ostream &VStream, 101 raw_ostream &CStream) const override; 102 }; 103 104 /// Thumb disassembler for all Thumb platforms. 105 class ThumbDisassembler : public MCDisassembler { 106 public: 107 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 108 MCDisassembler(STI, Ctx) { 109 } 110 111 ~ThumbDisassembler() override = default; 112 113 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 114 ArrayRef<uint8_t> Bytes, uint64_t Address, 115 raw_ostream &VStream, 116 raw_ostream &CStream) const override; 117 118 private: 119 mutable ITStatus ITBlock; 120 121 DecodeStatus AddThumbPredicate(MCInst&) const; 122 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 123 }; 124 125 } // end anonymous namespace 126 127 static bool Check(DecodeStatus &Out, DecodeStatus In) { 128 switch (In) { 129 case MCDisassembler::Success: 130 // Out stays the same. 131 return true; 132 case MCDisassembler::SoftFail: 133 Out = In; 134 return true; 135 case MCDisassembler::Fail: 136 Out = In; 137 return false; 138 } 139 llvm_unreachable("Invalid DecodeStatus!"); 140 } 141 142 // Forward declare these because the autogenerated code will reference them. 143 // Definitions are further down. 144 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 147 unsigned RegNo, uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 150 unsigned RegNo, uint64_t Address, 151 const void *Decoder); 152 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 171 unsigned RegNo, 172 uint64_t Address, 173 const void *Decoder); 174 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 179 unsigned RegNo, uint64_t Address, 180 const void *Decoder); 181 182 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 193 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 198 unsigned Insn, 199 uint64_t Address, 200 const void *Decoder); 201 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 210 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 211 unsigned Insn, 212 uint64_t Adddress, 213 const void *Decoder); 214 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 329 unsigned Val, 330 uint64_t Address, 331 const void *Decoder); 332 333 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 338 uint64_t Address, const void *Decoder); 339 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 340 uint64_t Address, const void *Decoder); 341 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 342 uint64_t Address, const void *Decoder); 343 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void* Decoder); 355 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void* Decoder); 357 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void* Decoder); 359 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void* Decoder); 361 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 406 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 413 #include "ARMGenDisassemblerTables.inc" 414 415 static MCDisassembler *createARMDisassembler(const Target &T, 416 const MCSubtargetInfo &STI, 417 MCContext &Ctx) { 418 return new ARMDisassembler(STI, Ctx); 419 } 420 421 static MCDisassembler *createThumbDisassembler(const Target &T, 422 const MCSubtargetInfo &STI, 423 MCContext &Ctx) { 424 return new ThumbDisassembler(STI, Ctx); 425 } 426 427 // Post-decoding checks 428 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 429 uint64_t Address, raw_ostream &OS, 430 raw_ostream &CS, 431 uint32_t Insn, 432 DecodeStatus Result) { 433 switch (MI.getOpcode()) { 434 case ARM::HVC: { 435 // HVC is undefined if condition = 0xf otherwise upredictable 436 // if condition != 0xe 437 uint32_t Cond = (Insn >> 28) & 0xF; 438 if (Cond == 0xF) 439 return MCDisassembler::Fail; 440 if (Cond != 0xE) 441 return MCDisassembler::SoftFail; 442 return Result; 443 } 444 case ARM::t2ADDri: 445 case ARM::t2ADDri12: 446 case ARM::t2ADDrr: 447 case ARM::t2ADDrs: 448 case ARM::t2SUBri: 449 case ARM::t2SUBri12: 450 case ARM::t2SUBrr: 451 case ARM::t2SUBrs: 452 if (MI.getOperand(0).getReg() == ARM::SP && 453 MI.getOperand(1).getReg() != ARM::SP) 454 return MCDisassembler::SoftFail; 455 return Result; 456 default: return Result; 457 } 458 } 459 460 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 461 ArrayRef<uint8_t> Bytes, 462 uint64_t Address, raw_ostream &OS, 463 raw_ostream &CS) const { 464 CommentStream = &CS; 465 466 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 467 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 468 "mode!"); 469 470 // We want to read exactly 4 bytes of data. 471 if (Bytes.size() < 4) { 472 Size = 0; 473 return MCDisassembler::Fail; 474 } 475 476 // Encoded as a small-endian 32-bit word in the stream. 477 uint32_t Insn = 478 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 479 480 // Calling the auto-generated decoder function. 481 DecodeStatus Result = 482 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 483 if (Result != MCDisassembler::Fail) { 484 Size = 4; 485 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 486 } 487 488 struct DecodeTable { 489 const uint8_t *P; 490 bool DecodePred; 491 }; 492 493 const DecodeTable Tables[] = { 494 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 495 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 496 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 497 {DecoderTablev8Crypto32, false}, 498 }; 499 500 for (auto Table : Tables) { 501 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 502 if (Result != MCDisassembler::Fail) { 503 Size = 4; 504 // Add a fake predicate operand, because we share these instruction 505 // definitions with Thumb2 where these instructions are predicable. 506 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 507 return MCDisassembler::Fail; 508 return Result; 509 } 510 } 511 512 Result = 513 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 514 if (Result != MCDisassembler::Fail) { 515 Size = 4; 516 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 517 } 518 519 Size = 4; 520 return MCDisassembler::Fail; 521 } 522 523 namespace llvm { 524 525 extern const MCInstrDesc ARMInsts[]; 526 527 } // end namespace llvm 528 529 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 530 /// immediate Value in the MCInst. The immediate Value has had any PC 531 /// adjustment made by the caller. If the instruction is a branch instruction 532 /// then isBranch is true, else false. If the getOpInfo() function was set as 533 /// part of the setupForSymbolicDisassembly() call then that function is called 534 /// to get any symbolic information at the Address for this instruction. If 535 /// that returns non-zero then the symbolic information it returns is used to 536 /// create an MCExpr and that is added as an operand to the MCInst. If 537 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 538 /// Value is done and if a symbol is found an MCExpr is created with that, else 539 /// an MCExpr with Value is created. This function returns true if it adds an 540 /// operand to the MCInst and false otherwise. 541 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 542 bool isBranch, uint64_t InstSize, 543 MCInst &MI, const void *Decoder) { 544 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 545 // FIXME: Does it make sense for value to be negative? 546 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 547 /* Offset */ 0, InstSize); 548 } 549 550 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 551 /// referenced by a load instruction with the base register that is the Pc. 552 /// These can often be values in a literal pool near the Address of the 553 /// instruction. The Address of the instruction and its immediate Value are 554 /// used as a possible literal pool entry. The SymbolLookUp call back will 555 /// return the name of a symbol referenced by the literal pool's entry if 556 /// the referenced address is that of a symbol. Or it will return a pointer to 557 /// a literal 'C' string if the referenced address of the literal pool's entry 558 /// is an address into a section with 'C' string literals. 559 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 560 const void *Decoder) { 561 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 562 Dis->tryAddingPcLoadReferenceComment(Value, Address); 563 } 564 565 // Thumb1 instructions don't have explicit S bits. Rather, they 566 // implicitly set CPSR. Since it's not represented in the encoding, the 567 // auto-generated decoder won't inject the CPSR operand. We need to fix 568 // that as a post-pass. 569 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 570 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 571 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 572 MCInst::iterator I = MI.begin(); 573 for (unsigned i = 0; i < NumOps; ++i, ++I) { 574 if (I == MI.end()) break; 575 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 576 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 577 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 578 return; 579 } 580 } 581 582 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 583 } 584 585 // Most Thumb instructions don't have explicit predicates in the 586 // encoding, but rather get their predicates from IT context. We need 587 // to fix up the predicate operands using this context information as a 588 // post-pass. 589 MCDisassembler::DecodeStatus 590 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 591 MCDisassembler::DecodeStatus S = Success; 592 593 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 594 595 // A few instructions actually have predicates encoded in them. Don't 596 // try to overwrite it if we're seeing one of those. 597 switch (MI.getOpcode()) { 598 case ARM::tBcc: 599 case ARM::t2Bcc: 600 case ARM::tCBZ: 601 case ARM::tCBNZ: 602 case ARM::tCPS: 603 case ARM::t2CPS3p: 604 case ARM::t2CPS2p: 605 case ARM::t2CPS1p: 606 case ARM::tMOVSr: 607 case ARM::tSETEND: 608 // Some instructions (mostly conditional branches) are not 609 // allowed in IT blocks. 610 if (ITBlock.instrInITBlock()) 611 S = SoftFail; 612 else 613 return Success; 614 break; 615 case ARM::t2HINT: 616 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 617 S = SoftFail; 618 break; 619 case ARM::tB: 620 case ARM::t2B: 621 case ARM::t2TBB: 622 case ARM::t2TBH: 623 // Some instructions (mostly unconditional branches) can 624 // only appears at the end of, or outside of, an IT. 625 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 626 S = SoftFail; 627 break; 628 default: 629 break; 630 } 631 632 // If we're in an IT block, base the predicate on that. Otherwise, 633 // assume a predicate of AL. 634 unsigned CC; 635 CC = ITBlock.getITCC(); 636 if (CC == 0xF) 637 CC = ARMCC::AL; 638 if (ITBlock.instrInITBlock()) 639 ITBlock.advanceITState(); 640 641 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 642 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 643 MCInst::iterator I = MI.begin(); 644 for (unsigned i = 0; i < NumOps; ++i, ++I) { 645 if (I == MI.end()) break; 646 if (OpInfo[i].isPredicate()) { 647 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 648 Check(S, SoftFail); 649 I = MI.insert(I, MCOperand::createImm(CC)); 650 ++I; 651 if (CC == ARMCC::AL) 652 MI.insert(I, MCOperand::createReg(0)); 653 else 654 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 655 return S; 656 } 657 } 658 659 I = MI.insert(I, MCOperand::createImm(CC)); 660 ++I; 661 if (CC == ARMCC::AL) 662 MI.insert(I, MCOperand::createReg(0)); 663 else 664 MI.insert(I, MCOperand::createReg(ARM::CPSR)); 665 666 return S; 667 } 668 669 // Thumb VFP instructions are a special case. Because we share their 670 // encodings between ARM and Thumb modes, and they are predicable in ARM 671 // mode, the auto-generated decoder will give them an (incorrect) 672 // predicate operand. We need to rewrite these operands based on the IT 673 // context as a post-pass. 674 void ThumbDisassembler::UpdateThumbVFPPredicate( 675 DecodeStatus &S, MCInst &MI) const { 676 unsigned CC; 677 CC = ITBlock.getITCC(); 678 if (CC == 0xF) 679 CC = ARMCC::AL; 680 if (ITBlock.instrInITBlock()) 681 ITBlock.advanceITState(); 682 683 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 684 MCInst::iterator I = MI.begin(); 685 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 686 for (unsigned i = 0; i < NumOps; ++i, ++I) { 687 if (OpInfo[i].isPredicate() ) { 688 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 689 Check(S, SoftFail); 690 I->setImm(CC); 691 ++I; 692 if (CC == ARMCC::AL) 693 I->setReg(0); 694 else 695 I->setReg(ARM::CPSR); 696 return; 697 } 698 } 699 } 700 701 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 702 ArrayRef<uint8_t> Bytes, 703 uint64_t Address, 704 raw_ostream &OS, 705 raw_ostream &CS) const { 706 CommentStream = &CS; 707 708 assert(STI.getFeatureBits()[ARM::ModeThumb] && 709 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 710 711 // We want to read exactly 2 bytes of data. 712 if (Bytes.size() < 2) { 713 Size = 0; 714 return MCDisassembler::Fail; 715 } 716 717 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 718 DecodeStatus Result = 719 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 720 if (Result != MCDisassembler::Fail) { 721 Size = 2; 722 Check(Result, AddThumbPredicate(MI)); 723 return Result; 724 } 725 726 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 727 STI); 728 if (Result) { 729 Size = 2; 730 bool InITBlock = ITBlock.instrInITBlock(); 731 Check(Result, AddThumbPredicate(MI)); 732 AddThumb1SBit(MI, InITBlock); 733 return Result; 734 } 735 736 Result = 737 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 738 if (Result != MCDisassembler::Fail) { 739 Size = 2; 740 741 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 742 // the Thumb predicate. 743 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 744 Result = MCDisassembler::SoftFail; 745 746 Check(Result, AddThumbPredicate(MI)); 747 748 // If we find an IT instruction, we need to parse its condition 749 // code and mask operands so that we can apply them correctly 750 // to the subsequent instructions. 751 if (MI.getOpcode() == ARM::t2IT) { 752 unsigned Firstcond = MI.getOperand(0).getImm(); 753 unsigned Mask = MI.getOperand(1).getImm(); 754 ITBlock.setITState(Firstcond, Mask); 755 756 // An IT instruction that would give a 'NV' predicate is unpredictable. 757 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 758 CS << "unpredictable IT predicate sequence"; 759 } 760 761 return Result; 762 } 763 764 // We want to read exactly 4 bytes of data. 765 if (Bytes.size() < 4) { 766 Size = 0; 767 return MCDisassembler::Fail; 768 } 769 770 uint32_t Insn32 = 771 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 772 Result = 773 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 774 if (Result != MCDisassembler::Fail) { 775 Size = 4; 776 bool InITBlock = ITBlock.instrInITBlock(); 777 Check(Result, AddThumbPredicate(MI)); 778 AddThumb1SBit(MI, InITBlock); 779 return Result; 780 } 781 782 Result = 783 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 784 if (Result != MCDisassembler::Fail) { 785 Size = 4; 786 Check(Result, AddThumbPredicate(MI)); 787 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 788 } 789 790 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 791 Result = 792 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 793 if (Result != MCDisassembler::Fail) { 794 Size = 4; 795 UpdateThumbVFPPredicate(Result, MI); 796 return Result; 797 } 798 } 799 800 Result = 801 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 802 if (Result != MCDisassembler::Fail) { 803 Size = 4; 804 return Result; 805 } 806 807 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 808 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 809 STI); 810 if (Result != MCDisassembler::Fail) { 811 Size = 4; 812 Check(Result, AddThumbPredicate(MI)); 813 return Result; 814 } 815 } 816 817 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 818 uint32_t NEONLdStInsn = Insn32; 819 NEONLdStInsn &= 0xF0FFFFFF; 820 NEONLdStInsn |= 0x04000000; 821 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 822 Address, this, STI); 823 if (Result != MCDisassembler::Fail) { 824 Size = 4; 825 Check(Result, AddThumbPredicate(MI)); 826 return Result; 827 } 828 } 829 830 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 831 uint32_t NEONDataInsn = Insn32; 832 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 833 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 834 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 835 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 836 Address, this, STI); 837 if (Result != MCDisassembler::Fail) { 838 Size = 4; 839 Check(Result, AddThumbPredicate(MI)); 840 return Result; 841 } 842 843 uint32_t NEONCryptoInsn = Insn32; 844 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 845 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 846 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 847 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 848 Address, this, STI); 849 if (Result != MCDisassembler::Fail) { 850 Size = 4; 851 return Result; 852 } 853 854 uint32_t NEONv8Insn = Insn32; 855 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 856 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 857 this, STI); 858 if (Result != MCDisassembler::Fail) { 859 Size = 4; 860 return Result; 861 } 862 } 863 864 Result = 865 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 866 if (Result != MCDisassembler::Fail) { 867 Size = 4; 868 Check(Result, AddThumbPredicate(MI)); 869 return Result; 870 } 871 872 Size = 0; 873 return MCDisassembler::Fail; 874 } 875 876 extern "C" void LLVMInitializeARMDisassembler() { 877 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 878 createARMDisassembler); 879 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 880 createARMDisassembler); 881 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 882 createThumbDisassembler); 883 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 884 createThumbDisassembler); 885 } 886 887 static const uint16_t GPRDecoderTable[] = { 888 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 889 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 890 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 891 ARM::R12, ARM::SP, ARM::LR, ARM::PC 892 }; 893 894 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 895 uint64_t Address, const void *Decoder) { 896 if (RegNo > 15) 897 return MCDisassembler::Fail; 898 899 unsigned Register = GPRDecoderTable[RegNo]; 900 Inst.addOperand(MCOperand::createReg(Register)); 901 return MCDisassembler::Success; 902 } 903 904 static DecodeStatus 905 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 906 uint64_t Address, const void *Decoder) { 907 DecodeStatus S = MCDisassembler::Success; 908 909 if (RegNo == 15) 910 S = MCDisassembler::SoftFail; 911 912 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 913 914 return S; 915 } 916 917 static DecodeStatus 918 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 919 uint64_t Address, const void *Decoder) { 920 DecodeStatus S = MCDisassembler::Success; 921 922 if (RegNo == 15) 923 { 924 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 925 return MCDisassembler::Success; 926 } 927 928 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 929 return S; 930 } 931 932 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 933 uint64_t Address, const void *Decoder) { 934 if (RegNo > 7) 935 return MCDisassembler::Fail; 936 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 937 } 938 939 static const uint16_t GPRPairDecoderTable[] = { 940 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 941 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 942 }; 943 944 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 945 uint64_t Address, const void *Decoder) { 946 DecodeStatus S = MCDisassembler::Success; 947 948 if (RegNo > 13) 949 return MCDisassembler::Fail; 950 951 if ((RegNo & 1) || RegNo == 0xe) 952 S = MCDisassembler::SoftFail; 953 954 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 955 Inst.addOperand(MCOperand::createReg(RegisterPair)); 956 return S; 957 } 958 959 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 960 uint64_t Address, const void *Decoder) { 961 unsigned Register = 0; 962 switch (RegNo) { 963 case 0: 964 Register = ARM::R0; 965 break; 966 case 1: 967 Register = ARM::R1; 968 break; 969 case 2: 970 Register = ARM::R2; 971 break; 972 case 3: 973 Register = ARM::R3; 974 break; 975 case 9: 976 Register = ARM::R9; 977 break; 978 case 12: 979 Register = ARM::R12; 980 break; 981 default: 982 return MCDisassembler::Fail; 983 } 984 985 Inst.addOperand(MCOperand::createReg(Register)); 986 return MCDisassembler::Success; 987 } 988 989 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 990 uint64_t Address, const void *Decoder) { 991 DecodeStatus S = MCDisassembler::Success; 992 993 const FeatureBitset &featureBits = 994 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 995 996 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 997 S = MCDisassembler::SoftFail; 998 999 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1000 return S; 1001 } 1002 1003 static const uint16_t SPRDecoderTable[] = { 1004 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1005 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1006 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1007 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1008 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1009 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1010 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1011 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1012 }; 1013 1014 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1015 uint64_t Address, const void *Decoder) { 1016 if (RegNo > 31) 1017 return MCDisassembler::Fail; 1018 1019 unsigned Register = SPRDecoderTable[RegNo]; 1020 Inst.addOperand(MCOperand::createReg(Register)); 1021 return MCDisassembler::Success; 1022 } 1023 1024 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1025 uint64_t Address, const void *Decoder) { 1026 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1027 } 1028 1029 static const uint16_t DPRDecoderTable[] = { 1030 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1031 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1032 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1033 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1034 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1035 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1036 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1037 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1038 }; 1039 1040 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1041 uint64_t Address, const void *Decoder) { 1042 const FeatureBitset &featureBits = 1043 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1044 1045 bool hasD16 = featureBits[ARM::FeatureD16]; 1046 1047 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1048 return MCDisassembler::Fail; 1049 1050 unsigned Register = DPRDecoderTable[RegNo]; 1051 Inst.addOperand(MCOperand::createReg(Register)); 1052 return MCDisassembler::Success; 1053 } 1054 1055 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1056 uint64_t Address, const void *Decoder) { 1057 if (RegNo > 7) 1058 return MCDisassembler::Fail; 1059 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1060 } 1061 1062 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1063 uint64_t Address, const void *Decoder) { 1064 if (RegNo > 15) 1065 return MCDisassembler::Fail; 1066 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1067 } 1068 1069 static DecodeStatus 1070 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1071 uint64_t Address, const void *Decoder) { 1072 if (RegNo > 15) 1073 return MCDisassembler::Fail; 1074 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1075 } 1076 1077 static const uint16_t QPRDecoderTable[] = { 1078 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1079 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1080 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1081 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1082 }; 1083 1084 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1085 uint64_t Address, const void *Decoder) { 1086 if (RegNo > 31 || (RegNo & 1) != 0) 1087 return MCDisassembler::Fail; 1088 RegNo >>= 1; 1089 1090 unsigned Register = QPRDecoderTable[RegNo]; 1091 Inst.addOperand(MCOperand::createReg(Register)); 1092 return MCDisassembler::Success; 1093 } 1094 1095 static const uint16_t DPairDecoderTable[] = { 1096 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1097 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1098 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1099 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1100 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1101 ARM::Q15 1102 }; 1103 1104 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1105 uint64_t Address, const void *Decoder) { 1106 if (RegNo > 30) 1107 return MCDisassembler::Fail; 1108 1109 unsigned Register = DPairDecoderTable[RegNo]; 1110 Inst.addOperand(MCOperand::createReg(Register)); 1111 return MCDisassembler::Success; 1112 } 1113 1114 static const uint16_t DPairSpacedDecoderTable[] = { 1115 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1116 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1117 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1118 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1119 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1120 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1121 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1122 ARM::D28_D30, ARM::D29_D31 1123 }; 1124 1125 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1126 unsigned RegNo, 1127 uint64_t Address, 1128 const void *Decoder) { 1129 if (RegNo > 29) 1130 return MCDisassembler::Fail; 1131 1132 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1133 Inst.addOperand(MCOperand::createReg(Register)); 1134 return MCDisassembler::Success; 1135 } 1136 1137 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1138 uint64_t Address, const void *Decoder) { 1139 DecodeStatus S = MCDisassembler::Success; 1140 if (Val == 0xF) return MCDisassembler::Fail; 1141 // AL predicate is not allowed on Thumb1 branches. 1142 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1143 return MCDisassembler::Fail; 1144 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1145 Check(S, MCDisassembler::SoftFail); 1146 Inst.addOperand(MCOperand::createImm(Val)); 1147 if (Val == ARMCC::AL) { 1148 Inst.addOperand(MCOperand::createReg(0)); 1149 } else 1150 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1151 return S; 1152 } 1153 1154 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1155 uint64_t Address, const void *Decoder) { 1156 if (Val) 1157 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1158 else 1159 Inst.addOperand(MCOperand::createReg(0)); 1160 return MCDisassembler::Success; 1161 } 1162 1163 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1164 uint64_t Address, const void *Decoder) { 1165 DecodeStatus S = MCDisassembler::Success; 1166 1167 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1168 unsigned type = fieldFromInstruction(Val, 5, 2); 1169 unsigned imm = fieldFromInstruction(Val, 7, 5); 1170 1171 // Register-immediate 1172 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1173 return MCDisassembler::Fail; 1174 1175 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1176 switch (type) { 1177 case 0: 1178 Shift = ARM_AM::lsl; 1179 break; 1180 case 1: 1181 Shift = ARM_AM::lsr; 1182 break; 1183 case 2: 1184 Shift = ARM_AM::asr; 1185 break; 1186 case 3: 1187 Shift = ARM_AM::ror; 1188 break; 1189 } 1190 1191 if (Shift == ARM_AM::ror && imm == 0) 1192 Shift = ARM_AM::rrx; 1193 1194 unsigned Op = Shift | (imm << 3); 1195 Inst.addOperand(MCOperand::createImm(Op)); 1196 1197 return S; 1198 } 1199 1200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1201 uint64_t Address, const void *Decoder) { 1202 DecodeStatus S = MCDisassembler::Success; 1203 1204 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1205 unsigned type = fieldFromInstruction(Val, 5, 2); 1206 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1207 1208 // Register-register 1209 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1210 return MCDisassembler::Fail; 1211 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1212 return MCDisassembler::Fail; 1213 1214 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1215 switch (type) { 1216 case 0: 1217 Shift = ARM_AM::lsl; 1218 break; 1219 case 1: 1220 Shift = ARM_AM::lsr; 1221 break; 1222 case 2: 1223 Shift = ARM_AM::asr; 1224 break; 1225 case 3: 1226 Shift = ARM_AM::ror; 1227 break; 1228 } 1229 1230 Inst.addOperand(MCOperand::createImm(Shift)); 1231 1232 return S; 1233 } 1234 1235 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1236 uint64_t Address, const void *Decoder) { 1237 DecodeStatus S = MCDisassembler::Success; 1238 1239 bool NeedDisjointWriteback = false; 1240 unsigned WritebackReg = 0; 1241 switch (Inst.getOpcode()) { 1242 default: 1243 break; 1244 case ARM::LDMIA_UPD: 1245 case ARM::LDMDB_UPD: 1246 case ARM::LDMIB_UPD: 1247 case ARM::LDMDA_UPD: 1248 case ARM::t2LDMIA_UPD: 1249 case ARM::t2LDMDB_UPD: 1250 case ARM::t2STMIA_UPD: 1251 case ARM::t2STMDB_UPD: 1252 NeedDisjointWriteback = true; 1253 WritebackReg = Inst.getOperand(0).getReg(); 1254 break; 1255 } 1256 1257 // Empty register lists are not allowed. 1258 if (Val == 0) return MCDisassembler::Fail; 1259 for (unsigned i = 0; i < 16; ++i) { 1260 if (Val & (1 << i)) { 1261 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1262 return MCDisassembler::Fail; 1263 // Writeback not allowed if Rn is in the target list. 1264 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1265 Check(S, MCDisassembler::SoftFail); 1266 } 1267 } 1268 1269 return S; 1270 } 1271 1272 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1273 uint64_t Address, const void *Decoder) { 1274 DecodeStatus S = MCDisassembler::Success; 1275 1276 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1277 unsigned regs = fieldFromInstruction(Val, 0, 8); 1278 1279 // In case of unpredictable encoding, tweak the operands. 1280 if (regs == 0 || (Vd + regs) > 32) { 1281 regs = Vd + regs > 32 ? 32 - Vd : regs; 1282 regs = std::max( 1u, regs); 1283 S = MCDisassembler::SoftFail; 1284 } 1285 1286 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1287 return MCDisassembler::Fail; 1288 for (unsigned i = 0; i < (regs - 1); ++i) { 1289 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1290 return MCDisassembler::Fail; 1291 } 1292 1293 return S; 1294 } 1295 1296 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1297 uint64_t Address, const void *Decoder) { 1298 DecodeStatus S = MCDisassembler::Success; 1299 1300 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1301 unsigned regs = fieldFromInstruction(Val, 1, 7); 1302 1303 // In case of unpredictable encoding, tweak the operands. 1304 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1305 regs = Vd + regs > 32 ? 32 - Vd : regs; 1306 regs = std::max( 1u, regs); 1307 regs = std::min(16u, regs); 1308 S = MCDisassembler::SoftFail; 1309 } 1310 1311 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1312 return MCDisassembler::Fail; 1313 for (unsigned i = 0; i < (regs - 1); ++i) { 1314 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1315 return MCDisassembler::Fail; 1316 } 1317 1318 return S; 1319 } 1320 1321 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1322 uint64_t Address, const void *Decoder) { 1323 // This operand encodes a mask of contiguous zeros between a specified MSB 1324 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1325 // the mask of all bits LSB-and-lower, and then xor them to create 1326 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1327 // create the final mask. 1328 unsigned msb = fieldFromInstruction(Val, 5, 5); 1329 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1330 1331 DecodeStatus S = MCDisassembler::Success; 1332 if (lsb > msb) { 1333 Check(S, MCDisassembler::SoftFail); 1334 // The check above will cause the warning for the "potentially undefined 1335 // instruction encoding" but we can't build a bad MCOperand value here 1336 // with a lsb > msb or else printing the MCInst will cause a crash. 1337 lsb = msb; 1338 } 1339 1340 uint32_t msb_mask = 0xFFFFFFFF; 1341 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1342 uint32_t lsb_mask = (1U << lsb) - 1; 1343 1344 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1345 return S; 1346 } 1347 1348 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1349 uint64_t Address, const void *Decoder) { 1350 DecodeStatus S = MCDisassembler::Success; 1351 1352 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1353 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1354 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1355 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1356 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1357 unsigned U = fieldFromInstruction(Insn, 23, 1); 1358 1359 switch (Inst.getOpcode()) { 1360 case ARM::LDC_OFFSET: 1361 case ARM::LDC_PRE: 1362 case ARM::LDC_POST: 1363 case ARM::LDC_OPTION: 1364 case ARM::LDCL_OFFSET: 1365 case ARM::LDCL_PRE: 1366 case ARM::LDCL_POST: 1367 case ARM::LDCL_OPTION: 1368 case ARM::STC_OFFSET: 1369 case ARM::STC_PRE: 1370 case ARM::STC_POST: 1371 case ARM::STC_OPTION: 1372 case ARM::STCL_OFFSET: 1373 case ARM::STCL_PRE: 1374 case ARM::STCL_POST: 1375 case ARM::STCL_OPTION: 1376 case ARM::t2LDC_OFFSET: 1377 case ARM::t2LDC_PRE: 1378 case ARM::t2LDC_POST: 1379 case ARM::t2LDC_OPTION: 1380 case ARM::t2LDCL_OFFSET: 1381 case ARM::t2LDCL_PRE: 1382 case ARM::t2LDCL_POST: 1383 case ARM::t2LDCL_OPTION: 1384 case ARM::t2STC_OFFSET: 1385 case ARM::t2STC_PRE: 1386 case ARM::t2STC_POST: 1387 case ARM::t2STC_OPTION: 1388 case ARM::t2STCL_OFFSET: 1389 case ARM::t2STCL_PRE: 1390 case ARM::t2STCL_POST: 1391 case ARM::t2STCL_OPTION: 1392 if (coproc == 0xA || coproc == 0xB) 1393 return MCDisassembler::Fail; 1394 break; 1395 default: 1396 break; 1397 } 1398 1399 const FeatureBitset &featureBits = 1400 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1401 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1402 return MCDisassembler::Fail; 1403 1404 Inst.addOperand(MCOperand::createImm(coproc)); 1405 Inst.addOperand(MCOperand::createImm(CRd)); 1406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1407 return MCDisassembler::Fail; 1408 1409 switch (Inst.getOpcode()) { 1410 case ARM::t2LDC2_OFFSET: 1411 case ARM::t2LDC2L_OFFSET: 1412 case ARM::t2LDC2_PRE: 1413 case ARM::t2LDC2L_PRE: 1414 case ARM::t2STC2_OFFSET: 1415 case ARM::t2STC2L_OFFSET: 1416 case ARM::t2STC2_PRE: 1417 case ARM::t2STC2L_PRE: 1418 case ARM::LDC2_OFFSET: 1419 case ARM::LDC2L_OFFSET: 1420 case ARM::LDC2_PRE: 1421 case ARM::LDC2L_PRE: 1422 case ARM::STC2_OFFSET: 1423 case ARM::STC2L_OFFSET: 1424 case ARM::STC2_PRE: 1425 case ARM::STC2L_PRE: 1426 case ARM::t2LDC_OFFSET: 1427 case ARM::t2LDCL_OFFSET: 1428 case ARM::t2LDC_PRE: 1429 case ARM::t2LDCL_PRE: 1430 case ARM::t2STC_OFFSET: 1431 case ARM::t2STCL_OFFSET: 1432 case ARM::t2STC_PRE: 1433 case ARM::t2STCL_PRE: 1434 case ARM::LDC_OFFSET: 1435 case ARM::LDCL_OFFSET: 1436 case ARM::LDC_PRE: 1437 case ARM::LDCL_PRE: 1438 case ARM::STC_OFFSET: 1439 case ARM::STCL_OFFSET: 1440 case ARM::STC_PRE: 1441 case ARM::STCL_PRE: 1442 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1443 Inst.addOperand(MCOperand::createImm(imm)); 1444 break; 1445 case ARM::t2LDC2_POST: 1446 case ARM::t2LDC2L_POST: 1447 case ARM::t2STC2_POST: 1448 case ARM::t2STC2L_POST: 1449 case ARM::LDC2_POST: 1450 case ARM::LDC2L_POST: 1451 case ARM::STC2_POST: 1452 case ARM::STC2L_POST: 1453 case ARM::t2LDC_POST: 1454 case ARM::t2LDCL_POST: 1455 case ARM::t2STC_POST: 1456 case ARM::t2STCL_POST: 1457 case ARM::LDC_POST: 1458 case ARM::LDCL_POST: 1459 case ARM::STC_POST: 1460 case ARM::STCL_POST: 1461 imm |= U << 8; 1462 LLVM_FALLTHROUGH; 1463 default: 1464 // The 'option' variant doesn't encode 'U' in the immediate since 1465 // the immediate is unsigned [0,255]. 1466 Inst.addOperand(MCOperand::createImm(imm)); 1467 break; 1468 } 1469 1470 switch (Inst.getOpcode()) { 1471 case ARM::LDC_OFFSET: 1472 case ARM::LDC_PRE: 1473 case ARM::LDC_POST: 1474 case ARM::LDC_OPTION: 1475 case ARM::LDCL_OFFSET: 1476 case ARM::LDCL_PRE: 1477 case ARM::LDCL_POST: 1478 case ARM::LDCL_OPTION: 1479 case ARM::STC_OFFSET: 1480 case ARM::STC_PRE: 1481 case ARM::STC_POST: 1482 case ARM::STC_OPTION: 1483 case ARM::STCL_OFFSET: 1484 case ARM::STCL_PRE: 1485 case ARM::STCL_POST: 1486 case ARM::STCL_OPTION: 1487 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1488 return MCDisassembler::Fail; 1489 break; 1490 default: 1491 break; 1492 } 1493 1494 return S; 1495 } 1496 1497 static DecodeStatus 1498 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1499 uint64_t Address, const void *Decoder) { 1500 DecodeStatus S = MCDisassembler::Success; 1501 1502 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1503 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1504 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1505 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1506 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1507 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1508 unsigned P = fieldFromInstruction(Insn, 24, 1); 1509 unsigned W = fieldFromInstruction(Insn, 21, 1); 1510 1511 // On stores, the writeback operand precedes Rt. 1512 switch (Inst.getOpcode()) { 1513 case ARM::STR_POST_IMM: 1514 case ARM::STR_POST_REG: 1515 case ARM::STRB_POST_IMM: 1516 case ARM::STRB_POST_REG: 1517 case ARM::STRT_POST_REG: 1518 case ARM::STRT_POST_IMM: 1519 case ARM::STRBT_POST_REG: 1520 case ARM::STRBT_POST_IMM: 1521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1522 return MCDisassembler::Fail; 1523 break; 1524 default: 1525 break; 1526 } 1527 1528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1529 return MCDisassembler::Fail; 1530 1531 // On loads, the writeback operand comes after Rt. 1532 switch (Inst.getOpcode()) { 1533 case ARM::LDR_POST_IMM: 1534 case ARM::LDR_POST_REG: 1535 case ARM::LDRB_POST_IMM: 1536 case ARM::LDRB_POST_REG: 1537 case ARM::LDRBT_POST_REG: 1538 case ARM::LDRBT_POST_IMM: 1539 case ARM::LDRT_POST_REG: 1540 case ARM::LDRT_POST_IMM: 1541 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1542 return MCDisassembler::Fail; 1543 break; 1544 default: 1545 break; 1546 } 1547 1548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1549 return MCDisassembler::Fail; 1550 1551 ARM_AM::AddrOpc Op = ARM_AM::add; 1552 if (!fieldFromInstruction(Insn, 23, 1)) 1553 Op = ARM_AM::sub; 1554 1555 bool writeback = (P == 0) || (W == 1); 1556 unsigned idx_mode = 0; 1557 if (P && writeback) 1558 idx_mode = ARMII::IndexModePre; 1559 else if (!P && writeback) 1560 idx_mode = ARMII::IndexModePost; 1561 1562 if (writeback && (Rn == 15 || Rn == Rt)) 1563 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1564 1565 if (reg) { 1566 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1567 return MCDisassembler::Fail; 1568 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1569 switch( fieldFromInstruction(Insn, 5, 2)) { 1570 case 0: 1571 Opc = ARM_AM::lsl; 1572 break; 1573 case 1: 1574 Opc = ARM_AM::lsr; 1575 break; 1576 case 2: 1577 Opc = ARM_AM::asr; 1578 break; 1579 case 3: 1580 Opc = ARM_AM::ror; 1581 break; 1582 default: 1583 return MCDisassembler::Fail; 1584 } 1585 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1586 if (Opc == ARM_AM::ror && amt == 0) 1587 Opc = ARM_AM::rrx; 1588 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1589 1590 Inst.addOperand(MCOperand::createImm(imm)); 1591 } else { 1592 Inst.addOperand(MCOperand::createReg(0)); 1593 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1594 Inst.addOperand(MCOperand::createImm(tmp)); 1595 } 1596 1597 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1598 return MCDisassembler::Fail; 1599 1600 return S; 1601 } 1602 1603 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1604 uint64_t Address, const void *Decoder) { 1605 DecodeStatus S = MCDisassembler::Success; 1606 1607 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1608 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1609 unsigned type = fieldFromInstruction(Val, 5, 2); 1610 unsigned imm = fieldFromInstruction(Val, 7, 5); 1611 unsigned U = fieldFromInstruction(Val, 12, 1); 1612 1613 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1614 switch (type) { 1615 case 0: 1616 ShOp = ARM_AM::lsl; 1617 break; 1618 case 1: 1619 ShOp = ARM_AM::lsr; 1620 break; 1621 case 2: 1622 ShOp = ARM_AM::asr; 1623 break; 1624 case 3: 1625 ShOp = ARM_AM::ror; 1626 break; 1627 } 1628 1629 if (ShOp == ARM_AM::ror && imm == 0) 1630 ShOp = ARM_AM::rrx; 1631 1632 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1633 return MCDisassembler::Fail; 1634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1635 return MCDisassembler::Fail; 1636 unsigned shift; 1637 if (U) 1638 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1639 else 1640 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1641 Inst.addOperand(MCOperand::createImm(shift)); 1642 1643 return S; 1644 } 1645 1646 static DecodeStatus 1647 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1648 uint64_t Address, const void *Decoder) { 1649 DecodeStatus S = MCDisassembler::Success; 1650 1651 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1652 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1653 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1654 unsigned type = fieldFromInstruction(Insn, 22, 1); 1655 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1656 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1657 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1658 unsigned W = fieldFromInstruction(Insn, 21, 1); 1659 unsigned P = fieldFromInstruction(Insn, 24, 1); 1660 unsigned Rt2 = Rt + 1; 1661 1662 bool writeback = (W == 1) | (P == 0); 1663 1664 // For {LD,ST}RD, Rt must be even, else undefined. 1665 switch (Inst.getOpcode()) { 1666 case ARM::STRD: 1667 case ARM::STRD_PRE: 1668 case ARM::STRD_POST: 1669 case ARM::LDRD: 1670 case ARM::LDRD_PRE: 1671 case ARM::LDRD_POST: 1672 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1673 break; 1674 default: 1675 break; 1676 } 1677 switch (Inst.getOpcode()) { 1678 case ARM::STRD: 1679 case ARM::STRD_PRE: 1680 case ARM::STRD_POST: 1681 if (P == 0 && W == 1) 1682 S = MCDisassembler::SoftFail; 1683 1684 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1685 S = MCDisassembler::SoftFail; 1686 if (type && Rm == 15) 1687 S = MCDisassembler::SoftFail; 1688 if (Rt2 == 15) 1689 S = MCDisassembler::SoftFail; 1690 if (!type && fieldFromInstruction(Insn, 8, 4)) 1691 S = MCDisassembler::SoftFail; 1692 break; 1693 case ARM::STRH: 1694 case ARM::STRH_PRE: 1695 case ARM::STRH_POST: 1696 if (Rt == 15) 1697 S = MCDisassembler::SoftFail; 1698 if (writeback && (Rn == 15 || Rn == Rt)) 1699 S = MCDisassembler::SoftFail; 1700 if (!type && Rm == 15) 1701 S = MCDisassembler::SoftFail; 1702 break; 1703 case ARM::LDRD: 1704 case ARM::LDRD_PRE: 1705 case ARM::LDRD_POST: 1706 if (type && Rn == 15) { 1707 if (Rt2 == 15) 1708 S = MCDisassembler::SoftFail; 1709 break; 1710 } 1711 if (P == 0 && W == 1) 1712 S = MCDisassembler::SoftFail; 1713 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1714 S = MCDisassembler::SoftFail; 1715 if (!type && writeback && Rn == 15) 1716 S = MCDisassembler::SoftFail; 1717 if (writeback && (Rn == Rt || Rn == Rt2)) 1718 S = MCDisassembler::SoftFail; 1719 break; 1720 case ARM::LDRH: 1721 case ARM::LDRH_PRE: 1722 case ARM::LDRH_POST: 1723 if (type && Rn == 15) { 1724 if (Rt == 15) 1725 S = MCDisassembler::SoftFail; 1726 break; 1727 } 1728 if (Rt == 15) 1729 S = MCDisassembler::SoftFail; 1730 if (!type && Rm == 15) 1731 S = MCDisassembler::SoftFail; 1732 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1733 S = MCDisassembler::SoftFail; 1734 break; 1735 case ARM::LDRSH: 1736 case ARM::LDRSH_PRE: 1737 case ARM::LDRSH_POST: 1738 case ARM::LDRSB: 1739 case ARM::LDRSB_PRE: 1740 case ARM::LDRSB_POST: 1741 if (type && Rn == 15) { 1742 if (Rt == 15) 1743 S = MCDisassembler::SoftFail; 1744 break; 1745 } 1746 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1747 S = MCDisassembler::SoftFail; 1748 if (!type && (Rt == 15 || Rm == 15)) 1749 S = MCDisassembler::SoftFail; 1750 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1751 S = MCDisassembler::SoftFail; 1752 break; 1753 default: 1754 break; 1755 } 1756 1757 if (writeback) { // Writeback 1758 if (P) 1759 U |= ARMII::IndexModePre << 9; 1760 else 1761 U |= ARMII::IndexModePost << 9; 1762 1763 // On stores, the writeback operand precedes Rt. 1764 switch (Inst.getOpcode()) { 1765 case ARM::STRD: 1766 case ARM::STRD_PRE: 1767 case ARM::STRD_POST: 1768 case ARM::STRH: 1769 case ARM::STRH_PRE: 1770 case ARM::STRH_POST: 1771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1772 return MCDisassembler::Fail; 1773 break; 1774 default: 1775 break; 1776 } 1777 } 1778 1779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1780 return MCDisassembler::Fail; 1781 switch (Inst.getOpcode()) { 1782 case ARM::STRD: 1783 case ARM::STRD_PRE: 1784 case ARM::STRD_POST: 1785 case ARM::LDRD: 1786 case ARM::LDRD_PRE: 1787 case ARM::LDRD_POST: 1788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1789 return MCDisassembler::Fail; 1790 break; 1791 default: 1792 break; 1793 } 1794 1795 if (writeback) { 1796 // On loads, the writeback operand comes after Rt. 1797 switch (Inst.getOpcode()) { 1798 case ARM::LDRD: 1799 case ARM::LDRD_PRE: 1800 case ARM::LDRD_POST: 1801 case ARM::LDRH: 1802 case ARM::LDRH_PRE: 1803 case ARM::LDRH_POST: 1804 case ARM::LDRSH: 1805 case ARM::LDRSH_PRE: 1806 case ARM::LDRSH_POST: 1807 case ARM::LDRSB: 1808 case ARM::LDRSB_PRE: 1809 case ARM::LDRSB_POST: 1810 case ARM::LDRHTr: 1811 case ARM::LDRSBTr: 1812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1813 return MCDisassembler::Fail; 1814 break; 1815 default: 1816 break; 1817 } 1818 } 1819 1820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1821 return MCDisassembler::Fail; 1822 1823 if (type) { 1824 Inst.addOperand(MCOperand::createReg(0)); 1825 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 1826 } else { 1827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1828 return MCDisassembler::Fail; 1829 Inst.addOperand(MCOperand::createImm(U)); 1830 } 1831 1832 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1833 return MCDisassembler::Fail; 1834 1835 return S; 1836 } 1837 1838 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1839 uint64_t Address, const void *Decoder) { 1840 DecodeStatus S = MCDisassembler::Success; 1841 1842 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1843 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1844 1845 switch (mode) { 1846 case 0: 1847 mode = ARM_AM::da; 1848 break; 1849 case 1: 1850 mode = ARM_AM::ia; 1851 break; 1852 case 2: 1853 mode = ARM_AM::db; 1854 break; 1855 case 3: 1856 mode = ARM_AM::ib; 1857 break; 1858 } 1859 1860 Inst.addOperand(MCOperand::createImm(mode)); 1861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1862 return MCDisassembler::Fail; 1863 1864 return S; 1865 } 1866 1867 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1868 uint64_t Address, const void *Decoder) { 1869 DecodeStatus S = MCDisassembler::Success; 1870 1871 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1872 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1873 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1874 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1875 1876 if (pred == 0xF) 1877 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1878 1879 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1880 return MCDisassembler::Fail; 1881 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1882 return MCDisassembler::Fail; 1883 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1884 return MCDisassembler::Fail; 1885 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1886 return MCDisassembler::Fail; 1887 return S; 1888 } 1889 1890 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1891 unsigned Insn, 1892 uint64_t Address, const void *Decoder) { 1893 DecodeStatus S = MCDisassembler::Success; 1894 1895 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1896 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1897 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1898 1899 if (pred == 0xF) { 1900 // Ambiguous with RFE and SRS 1901 switch (Inst.getOpcode()) { 1902 case ARM::LDMDA: 1903 Inst.setOpcode(ARM::RFEDA); 1904 break; 1905 case ARM::LDMDA_UPD: 1906 Inst.setOpcode(ARM::RFEDA_UPD); 1907 break; 1908 case ARM::LDMDB: 1909 Inst.setOpcode(ARM::RFEDB); 1910 break; 1911 case ARM::LDMDB_UPD: 1912 Inst.setOpcode(ARM::RFEDB_UPD); 1913 break; 1914 case ARM::LDMIA: 1915 Inst.setOpcode(ARM::RFEIA); 1916 break; 1917 case ARM::LDMIA_UPD: 1918 Inst.setOpcode(ARM::RFEIA_UPD); 1919 break; 1920 case ARM::LDMIB: 1921 Inst.setOpcode(ARM::RFEIB); 1922 break; 1923 case ARM::LDMIB_UPD: 1924 Inst.setOpcode(ARM::RFEIB_UPD); 1925 break; 1926 case ARM::STMDA: 1927 Inst.setOpcode(ARM::SRSDA); 1928 break; 1929 case ARM::STMDA_UPD: 1930 Inst.setOpcode(ARM::SRSDA_UPD); 1931 break; 1932 case ARM::STMDB: 1933 Inst.setOpcode(ARM::SRSDB); 1934 break; 1935 case ARM::STMDB_UPD: 1936 Inst.setOpcode(ARM::SRSDB_UPD); 1937 break; 1938 case ARM::STMIA: 1939 Inst.setOpcode(ARM::SRSIA); 1940 break; 1941 case ARM::STMIA_UPD: 1942 Inst.setOpcode(ARM::SRSIA_UPD); 1943 break; 1944 case ARM::STMIB: 1945 Inst.setOpcode(ARM::SRSIB); 1946 break; 1947 case ARM::STMIB_UPD: 1948 Inst.setOpcode(ARM::SRSIB_UPD); 1949 break; 1950 default: 1951 return MCDisassembler::Fail; 1952 } 1953 1954 // For stores (which become SRS's, the only operand is the mode. 1955 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1956 // Check SRS encoding constraints 1957 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1958 fieldFromInstruction(Insn, 20, 1) == 0)) 1959 return MCDisassembler::Fail; 1960 1961 Inst.addOperand( 1962 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 1963 return S; 1964 } 1965 1966 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1967 } 1968 1969 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1970 return MCDisassembler::Fail; 1971 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1972 return MCDisassembler::Fail; // Tied 1973 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1976 return MCDisassembler::Fail; 1977 1978 return S; 1979 } 1980 1981 // Check for UNPREDICTABLE predicated ESB instruction 1982 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 1983 uint64_t Address, const void *Decoder) { 1984 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1985 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 1986 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 1987 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 1988 1989 DecodeStatus S = MCDisassembler::Success; 1990 1991 Inst.addOperand(MCOperand::createImm(imm8)); 1992 1993 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1994 return MCDisassembler::Fail; 1995 1996 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 1997 // so all predicates should be allowed. 1998 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 1999 S = MCDisassembler::SoftFail; 2000 2001 return S; 2002 } 2003 2004 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2005 uint64_t Address, const void *Decoder) { 2006 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2007 unsigned M = fieldFromInstruction(Insn, 17, 1); 2008 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2009 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2010 2011 DecodeStatus S = MCDisassembler::Success; 2012 2013 // This decoder is called from multiple location that do not check 2014 // the full encoding is valid before they do. 2015 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2016 fieldFromInstruction(Insn, 16, 1) != 0 || 2017 fieldFromInstruction(Insn, 20, 8) != 0x10) 2018 return MCDisassembler::Fail; 2019 2020 // imod == '01' --> UNPREDICTABLE 2021 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2022 // return failure here. The '01' imod value is unprintable, so there's 2023 // nothing useful we could do even if we returned UNPREDICTABLE. 2024 2025 if (imod == 1) return MCDisassembler::Fail; 2026 2027 if (imod && M) { 2028 Inst.setOpcode(ARM::CPS3p); 2029 Inst.addOperand(MCOperand::createImm(imod)); 2030 Inst.addOperand(MCOperand::createImm(iflags)); 2031 Inst.addOperand(MCOperand::createImm(mode)); 2032 } else if (imod && !M) { 2033 Inst.setOpcode(ARM::CPS2p); 2034 Inst.addOperand(MCOperand::createImm(imod)); 2035 Inst.addOperand(MCOperand::createImm(iflags)); 2036 if (mode) S = MCDisassembler::SoftFail; 2037 } else if (!imod && M) { 2038 Inst.setOpcode(ARM::CPS1p); 2039 Inst.addOperand(MCOperand::createImm(mode)); 2040 if (iflags) S = MCDisassembler::SoftFail; 2041 } else { 2042 // imod == '00' && M == '0' --> UNPREDICTABLE 2043 Inst.setOpcode(ARM::CPS1p); 2044 Inst.addOperand(MCOperand::createImm(mode)); 2045 S = MCDisassembler::SoftFail; 2046 } 2047 2048 return S; 2049 } 2050 2051 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2052 uint64_t Address, const void *Decoder) { 2053 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2054 unsigned M = fieldFromInstruction(Insn, 8, 1); 2055 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2056 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2057 2058 DecodeStatus S = MCDisassembler::Success; 2059 2060 // imod == '01' --> UNPREDICTABLE 2061 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2062 // return failure here. The '01' imod value is unprintable, so there's 2063 // nothing useful we could do even if we returned UNPREDICTABLE. 2064 2065 if (imod == 1) return MCDisassembler::Fail; 2066 2067 if (imod && M) { 2068 Inst.setOpcode(ARM::t2CPS3p); 2069 Inst.addOperand(MCOperand::createImm(imod)); 2070 Inst.addOperand(MCOperand::createImm(iflags)); 2071 Inst.addOperand(MCOperand::createImm(mode)); 2072 } else if (imod && !M) { 2073 Inst.setOpcode(ARM::t2CPS2p); 2074 Inst.addOperand(MCOperand::createImm(imod)); 2075 Inst.addOperand(MCOperand::createImm(iflags)); 2076 if (mode) S = MCDisassembler::SoftFail; 2077 } else if (!imod && M) { 2078 Inst.setOpcode(ARM::t2CPS1p); 2079 Inst.addOperand(MCOperand::createImm(mode)); 2080 if (iflags) S = MCDisassembler::SoftFail; 2081 } else { 2082 // imod == '00' && M == '0' --> this is a HINT instruction 2083 int imm = fieldFromInstruction(Insn, 0, 8); 2084 // HINT are defined only for immediate in [0..4] 2085 if(imm > 4) return MCDisassembler::Fail; 2086 Inst.setOpcode(ARM::t2HINT); 2087 Inst.addOperand(MCOperand::createImm(imm)); 2088 } 2089 2090 return S; 2091 } 2092 2093 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2094 uint64_t Address, const void *Decoder) { 2095 DecodeStatus S = MCDisassembler::Success; 2096 2097 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2098 unsigned imm = 0; 2099 2100 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2101 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2102 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2103 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2104 2105 if (Inst.getOpcode() == ARM::t2MOVTi16) 2106 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2107 return MCDisassembler::Fail; 2108 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2109 return MCDisassembler::Fail; 2110 2111 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2112 Inst.addOperand(MCOperand::createImm(imm)); 2113 2114 return S; 2115 } 2116 2117 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2118 uint64_t Address, const void *Decoder) { 2119 DecodeStatus S = MCDisassembler::Success; 2120 2121 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2122 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2123 unsigned imm = 0; 2124 2125 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2126 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2127 2128 if (Inst.getOpcode() == ARM::MOVTi16) 2129 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2130 return MCDisassembler::Fail; 2131 2132 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2133 return MCDisassembler::Fail; 2134 2135 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2136 Inst.addOperand(MCOperand::createImm(imm)); 2137 2138 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2139 return MCDisassembler::Fail; 2140 2141 return S; 2142 } 2143 2144 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2145 uint64_t Address, const void *Decoder) { 2146 DecodeStatus S = MCDisassembler::Success; 2147 2148 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2149 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2150 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2151 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2152 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2153 2154 if (pred == 0xF) 2155 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2156 2157 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2158 return MCDisassembler::Fail; 2159 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2160 return MCDisassembler::Fail; 2161 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2162 return MCDisassembler::Fail; 2163 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2164 return MCDisassembler::Fail; 2165 2166 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2167 return MCDisassembler::Fail; 2168 2169 return S; 2170 } 2171 2172 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2173 uint64_t Address, const void *Decoder) { 2174 DecodeStatus S = MCDisassembler::Success; 2175 2176 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2177 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2178 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2179 2180 if (Pred == 0xF) 2181 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2182 2183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2184 return MCDisassembler::Fail; 2185 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2186 return MCDisassembler::Fail; 2187 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2188 return MCDisassembler::Fail; 2189 2190 return S; 2191 } 2192 2193 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2194 uint64_t Address, const void *Decoder) { 2195 DecodeStatus S = MCDisassembler::Success; 2196 2197 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2198 2199 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2200 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2201 2202 if (!FeatureBits[ARM::HasV8_1aOps] || 2203 !FeatureBits[ARM::HasV8Ops]) 2204 return MCDisassembler::Fail; 2205 2206 // Decoder can be called from DecodeTST, which does not check the full 2207 // encoding is valid. 2208 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2209 fieldFromInstruction(Insn, 4,4) != 0) 2210 return MCDisassembler::Fail; 2211 if (fieldFromInstruction(Insn, 10,10) != 0 || 2212 fieldFromInstruction(Insn, 0,4) != 0) 2213 S = MCDisassembler::SoftFail; 2214 2215 Inst.setOpcode(ARM::SETPAN); 2216 Inst.addOperand(MCOperand::createImm(Imm)); 2217 2218 return S; 2219 } 2220 2221 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2222 uint64_t Address, const void *Decoder) { 2223 DecodeStatus S = MCDisassembler::Success; 2224 2225 unsigned add = fieldFromInstruction(Val, 12, 1); 2226 unsigned imm = fieldFromInstruction(Val, 0, 12); 2227 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2228 2229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2230 return MCDisassembler::Fail; 2231 2232 if (!add) imm *= -1; 2233 if (imm == 0 && !add) imm = INT32_MIN; 2234 Inst.addOperand(MCOperand::createImm(imm)); 2235 if (Rn == 15) 2236 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2237 2238 return S; 2239 } 2240 2241 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2242 uint64_t Address, const void *Decoder) { 2243 DecodeStatus S = MCDisassembler::Success; 2244 2245 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2246 // U == 1 to add imm, 0 to subtract it. 2247 unsigned U = fieldFromInstruction(Val, 8, 1); 2248 unsigned imm = fieldFromInstruction(Val, 0, 8); 2249 2250 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2251 return MCDisassembler::Fail; 2252 2253 if (U) 2254 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2255 else 2256 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2257 2258 return S; 2259 } 2260 2261 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2262 uint64_t Address, const void *Decoder) { 2263 DecodeStatus S = MCDisassembler::Success; 2264 2265 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2266 // U == 1 to add imm, 0 to subtract it. 2267 unsigned U = fieldFromInstruction(Val, 8, 1); 2268 unsigned imm = fieldFromInstruction(Val, 0, 8); 2269 2270 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2271 return MCDisassembler::Fail; 2272 2273 if (U) 2274 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2275 else 2276 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2277 2278 return S; 2279 } 2280 2281 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2282 uint64_t Address, const void *Decoder) { 2283 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2284 } 2285 2286 static DecodeStatus 2287 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2288 uint64_t Address, const void *Decoder) { 2289 DecodeStatus Status = MCDisassembler::Success; 2290 2291 // Note the J1 and J2 values are from the encoded instruction. So here 2292 // change them to I1 and I2 values via as documented: 2293 // I1 = NOT(J1 EOR S); 2294 // I2 = NOT(J2 EOR S); 2295 // and build the imm32 with one trailing zero as documented: 2296 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2297 unsigned S = fieldFromInstruction(Insn, 26, 1); 2298 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2299 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2300 unsigned I1 = !(J1 ^ S); 2301 unsigned I2 = !(J2 ^ S); 2302 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2303 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2304 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2305 int imm32 = SignExtend32<25>(tmp << 1); 2306 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2307 true, 4, Inst, Decoder)) 2308 Inst.addOperand(MCOperand::createImm(imm32)); 2309 2310 return Status; 2311 } 2312 2313 static DecodeStatus 2314 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2315 uint64_t Address, const void *Decoder) { 2316 DecodeStatus S = MCDisassembler::Success; 2317 2318 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2319 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2320 2321 if (pred == 0xF) { 2322 Inst.setOpcode(ARM::BLXi); 2323 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2324 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2325 true, 4, Inst, Decoder)) 2326 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2327 return S; 2328 } 2329 2330 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2331 true, 4, Inst, Decoder)) 2332 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2333 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2334 return MCDisassembler::Fail; 2335 2336 return S; 2337 } 2338 2339 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2340 uint64_t Address, const void *Decoder) { 2341 DecodeStatus S = MCDisassembler::Success; 2342 2343 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2344 unsigned align = fieldFromInstruction(Val, 4, 2); 2345 2346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2347 return MCDisassembler::Fail; 2348 if (!align) 2349 Inst.addOperand(MCOperand::createImm(0)); 2350 else 2351 Inst.addOperand(MCOperand::createImm(4 << align)); 2352 2353 return S; 2354 } 2355 2356 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2357 uint64_t Address, const void *Decoder) { 2358 DecodeStatus S = MCDisassembler::Success; 2359 2360 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2361 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2362 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2363 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2364 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2365 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2366 2367 // First output register 2368 switch (Inst.getOpcode()) { 2369 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2370 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2371 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2372 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2373 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2374 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2375 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2376 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2377 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2378 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2379 return MCDisassembler::Fail; 2380 break; 2381 case ARM::VLD2b16: 2382 case ARM::VLD2b32: 2383 case ARM::VLD2b8: 2384 case ARM::VLD2b16wb_fixed: 2385 case ARM::VLD2b16wb_register: 2386 case ARM::VLD2b32wb_fixed: 2387 case ARM::VLD2b32wb_register: 2388 case ARM::VLD2b8wb_fixed: 2389 case ARM::VLD2b8wb_register: 2390 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2391 return MCDisassembler::Fail; 2392 break; 2393 default: 2394 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2395 return MCDisassembler::Fail; 2396 } 2397 2398 // Second output register 2399 switch (Inst.getOpcode()) { 2400 case ARM::VLD3d8: 2401 case ARM::VLD3d16: 2402 case ARM::VLD3d32: 2403 case ARM::VLD3d8_UPD: 2404 case ARM::VLD3d16_UPD: 2405 case ARM::VLD3d32_UPD: 2406 case ARM::VLD4d8: 2407 case ARM::VLD4d16: 2408 case ARM::VLD4d32: 2409 case ARM::VLD4d8_UPD: 2410 case ARM::VLD4d16_UPD: 2411 case ARM::VLD4d32_UPD: 2412 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2413 return MCDisassembler::Fail; 2414 break; 2415 case ARM::VLD3q8: 2416 case ARM::VLD3q16: 2417 case ARM::VLD3q32: 2418 case ARM::VLD3q8_UPD: 2419 case ARM::VLD3q16_UPD: 2420 case ARM::VLD3q32_UPD: 2421 case ARM::VLD4q8: 2422 case ARM::VLD4q16: 2423 case ARM::VLD4q32: 2424 case ARM::VLD4q8_UPD: 2425 case ARM::VLD4q16_UPD: 2426 case ARM::VLD4q32_UPD: 2427 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2428 return MCDisassembler::Fail; 2429 break; 2430 default: 2431 break; 2432 } 2433 2434 // Third output register 2435 switch(Inst.getOpcode()) { 2436 case ARM::VLD3d8: 2437 case ARM::VLD3d16: 2438 case ARM::VLD3d32: 2439 case ARM::VLD3d8_UPD: 2440 case ARM::VLD3d16_UPD: 2441 case ARM::VLD3d32_UPD: 2442 case ARM::VLD4d8: 2443 case ARM::VLD4d16: 2444 case ARM::VLD4d32: 2445 case ARM::VLD4d8_UPD: 2446 case ARM::VLD4d16_UPD: 2447 case ARM::VLD4d32_UPD: 2448 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2449 return MCDisassembler::Fail; 2450 break; 2451 case ARM::VLD3q8: 2452 case ARM::VLD3q16: 2453 case ARM::VLD3q32: 2454 case ARM::VLD3q8_UPD: 2455 case ARM::VLD3q16_UPD: 2456 case ARM::VLD3q32_UPD: 2457 case ARM::VLD4q8: 2458 case ARM::VLD4q16: 2459 case ARM::VLD4q32: 2460 case ARM::VLD4q8_UPD: 2461 case ARM::VLD4q16_UPD: 2462 case ARM::VLD4q32_UPD: 2463 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2464 return MCDisassembler::Fail; 2465 break; 2466 default: 2467 break; 2468 } 2469 2470 // Fourth output register 2471 switch (Inst.getOpcode()) { 2472 case ARM::VLD4d8: 2473 case ARM::VLD4d16: 2474 case ARM::VLD4d32: 2475 case ARM::VLD4d8_UPD: 2476 case ARM::VLD4d16_UPD: 2477 case ARM::VLD4d32_UPD: 2478 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2479 return MCDisassembler::Fail; 2480 break; 2481 case ARM::VLD4q8: 2482 case ARM::VLD4q16: 2483 case ARM::VLD4q32: 2484 case ARM::VLD4q8_UPD: 2485 case ARM::VLD4q16_UPD: 2486 case ARM::VLD4q32_UPD: 2487 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2488 return MCDisassembler::Fail; 2489 break; 2490 default: 2491 break; 2492 } 2493 2494 // Writeback operand 2495 switch (Inst.getOpcode()) { 2496 case ARM::VLD1d8wb_fixed: 2497 case ARM::VLD1d16wb_fixed: 2498 case ARM::VLD1d32wb_fixed: 2499 case ARM::VLD1d64wb_fixed: 2500 case ARM::VLD1d8wb_register: 2501 case ARM::VLD1d16wb_register: 2502 case ARM::VLD1d32wb_register: 2503 case ARM::VLD1d64wb_register: 2504 case ARM::VLD1q8wb_fixed: 2505 case ARM::VLD1q16wb_fixed: 2506 case ARM::VLD1q32wb_fixed: 2507 case ARM::VLD1q64wb_fixed: 2508 case ARM::VLD1q8wb_register: 2509 case ARM::VLD1q16wb_register: 2510 case ARM::VLD1q32wb_register: 2511 case ARM::VLD1q64wb_register: 2512 case ARM::VLD1d8Twb_fixed: 2513 case ARM::VLD1d8Twb_register: 2514 case ARM::VLD1d16Twb_fixed: 2515 case ARM::VLD1d16Twb_register: 2516 case ARM::VLD1d32Twb_fixed: 2517 case ARM::VLD1d32Twb_register: 2518 case ARM::VLD1d64Twb_fixed: 2519 case ARM::VLD1d64Twb_register: 2520 case ARM::VLD1d8Qwb_fixed: 2521 case ARM::VLD1d8Qwb_register: 2522 case ARM::VLD1d16Qwb_fixed: 2523 case ARM::VLD1d16Qwb_register: 2524 case ARM::VLD1d32Qwb_fixed: 2525 case ARM::VLD1d32Qwb_register: 2526 case ARM::VLD1d64Qwb_fixed: 2527 case ARM::VLD1d64Qwb_register: 2528 case ARM::VLD2d8wb_fixed: 2529 case ARM::VLD2d16wb_fixed: 2530 case ARM::VLD2d32wb_fixed: 2531 case ARM::VLD2q8wb_fixed: 2532 case ARM::VLD2q16wb_fixed: 2533 case ARM::VLD2q32wb_fixed: 2534 case ARM::VLD2d8wb_register: 2535 case ARM::VLD2d16wb_register: 2536 case ARM::VLD2d32wb_register: 2537 case ARM::VLD2q8wb_register: 2538 case ARM::VLD2q16wb_register: 2539 case ARM::VLD2q32wb_register: 2540 case ARM::VLD2b8wb_fixed: 2541 case ARM::VLD2b16wb_fixed: 2542 case ARM::VLD2b32wb_fixed: 2543 case ARM::VLD2b8wb_register: 2544 case ARM::VLD2b16wb_register: 2545 case ARM::VLD2b32wb_register: 2546 Inst.addOperand(MCOperand::createImm(0)); 2547 break; 2548 case ARM::VLD3d8_UPD: 2549 case ARM::VLD3d16_UPD: 2550 case ARM::VLD3d32_UPD: 2551 case ARM::VLD3q8_UPD: 2552 case ARM::VLD3q16_UPD: 2553 case ARM::VLD3q32_UPD: 2554 case ARM::VLD4d8_UPD: 2555 case ARM::VLD4d16_UPD: 2556 case ARM::VLD4d32_UPD: 2557 case ARM::VLD4q8_UPD: 2558 case ARM::VLD4q16_UPD: 2559 case ARM::VLD4q32_UPD: 2560 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2561 return MCDisassembler::Fail; 2562 break; 2563 default: 2564 break; 2565 } 2566 2567 // AddrMode6 Base (register+alignment) 2568 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2569 return MCDisassembler::Fail; 2570 2571 // AddrMode6 Offset (register) 2572 switch (Inst.getOpcode()) { 2573 default: 2574 // The below have been updated to have explicit am6offset split 2575 // between fixed and register offset. For those instructions not 2576 // yet updated, we need to add an additional reg0 operand for the 2577 // fixed variant. 2578 // 2579 // The fixed offset encodes as Rm == 0xd, so we check for that. 2580 if (Rm == 0xd) { 2581 Inst.addOperand(MCOperand::createReg(0)); 2582 break; 2583 } 2584 // Fall through to handle the register offset variant. 2585 LLVM_FALLTHROUGH; 2586 case ARM::VLD1d8wb_fixed: 2587 case ARM::VLD1d16wb_fixed: 2588 case ARM::VLD1d32wb_fixed: 2589 case ARM::VLD1d64wb_fixed: 2590 case ARM::VLD1d8Twb_fixed: 2591 case ARM::VLD1d16Twb_fixed: 2592 case ARM::VLD1d32Twb_fixed: 2593 case ARM::VLD1d64Twb_fixed: 2594 case ARM::VLD1d8Qwb_fixed: 2595 case ARM::VLD1d16Qwb_fixed: 2596 case ARM::VLD1d32Qwb_fixed: 2597 case ARM::VLD1d64Qwb_fixed: 2598 case ARM::VLD1d8wb_register: 2599 case ARM::VLD1d16wb_register: 2600 case ARM::VLD1d32wb_register: 2601 case ARM::VLD1d64wb_register: 2602 case ARM::VLD1q8wb_fixed: 2603 case ARM::VLD1q16wb_fixed: 2604 case ARM::VLD1q32wb_fixed: 2605 case ARM::VLD1q64wb_fixed: 2606 case ARM::VLD1q8wb_register: 2607 case ARM::VLD1q16wb_register: 2608 case ARM::VLD1q32wb_register: 2609 case ARM::VLD1q64wb_register: 2610 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2611 // variant encodes Rm == 0xf. Anything else is a register offset post- 2612 // increment and we need to add the register operand to the instruction. 2613 if (Rm != 0xD && Rm != 0xF && 2614 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2615 return MCDisassembler::Fail; 2616 break; 2617 case ARM::VLD2d8wb_fixed: 2618 case ARM::VLD2d16wb_fixed: 2619 case ARM::VLD2d32wb_fixed: 2620 case ARM::VLD2b8wb_fixed: 2621 case ARM::VLD2b16wb_fixed: 2622 case ARM::VLD2b32wb_fixed: 2623 case ARM::VLD2q8wb_fixed: 2624 case ARM::VLD2q16wb_fixed: 2625 case ARM::VLD2q32wb_fixed: 2626 break; 2627 } 2628 2629 return S; 2630 } 2631 2632 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2633 uint64_t Address, const void *Decoder) { 2634 unsigned type = fieldFromInstruction(Insn, 8, 4); 2635 unsigned align = fieldFromInstruction(Insn, 4, 2); 2636 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2637 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2638 if (type == 10 && align == 3) return MCDisassembler::Fail; 2639 2640 unsigned load = fieldFromInstruction(Insn, 21, 1); 2641 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2642 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2643 } 2644 2645 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2646 uint64_t Address, const void *Decoder) { 2647 unsigned size = fieldFromInstruction(Insn, 6, 2); 2648 if (size == 3) return MCDisassembler::Fail; 2649 2650 unsigned type = fieldFromInstruction(Insn, 8, 4); 2651 unsigned align = fieldFromInstruction(Insn, 4, 2); 2652 if (type == 8 && align == 3) return MCDisassembler::Fail; 2653 if (type == 9 && align == 3) return MCDisassembler::Fail; 2654 2655 unsigned load = fieldFromInstruction(Insn, 21, 1); 2656 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2657 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2658 } 2659 2660 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2661 uint64_t Address, const void *Decoder) { 2662 unsigned size = fieldFromInstruction(Insn, 6, 2); 2663 if (size == 3) return MCDisassembler::Fail; 2664 2665 unsigned align = fieldFromInstruction(Insn, 4, 2); 2666 if (align & 2) return MCDisassembler::Fail; 2667 2668 unsigned load = fieldFromInstruction(Insn, 21, 1); 2669 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2670 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2671 } 2672 2673 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2674 uint64_t Address, const void *Decoder) { 2675 unsigned size = fieldFromInstruction(Insn, 6, 2); 2676 if (size == 3) return MCDisassembler::Fail; 2677 2678 unsigned load = fieldFromInstruction(Insn, 21, 1); 2679 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2680 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2681 } 2682 2683 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2684 uint64_t Address, const void *Decoder) { 2685 DecodeStatus S = MCDisassembler::Success; 2686 2687 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2688 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2689 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2690 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2691 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2692 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2693 2694 // Writeback Operand 2695 switch (Inst.getOpcode()) { 2696 case ARM::VST1d8wb_fixed: 2697 case ARM::VST1d16wb_fixed: 2698 case ARM::VST1d32wb_fixed: 2699 case ARM::VST1d64wb_fixed: 2700 case ARM::VST1d8wb_register: 2701 case ARM::VST1d16wb_register: 2702 case ARM::VST1d32wb_register: 2703 case ARM::VST1d64wb_register: 2704 case ARM::VST1q8wb_fixed: 2705 case ARM::VST1q16wb_fixed: 2706 case ARM::VST1q32wb_fixed: 2707 case ARM::VST1q64wb_fixed: 2708 case ARM::VST1q8wb_register: 2709 case ARM::VST1q16wb_register: 2710 case ARM::VST1q32wb_register: 2711 case ARM::VST1q64wb_register: 2712 case ARM::VST1d8Twb_fixed: 2713 case ARM::VST1d16Twb_fixed: 2714 case ARM::VST1d32Twb_fixed: 2715 case ARM::VST1d64Twb_fixed: 2716 case ARM::VST1d8Twb_register: 2717 case ARM::VST1d16Twb_register: 2718 case ARM::VST1d32Twb_register: 2719 case ARM::VST1d64Twb_register: 2720 case ARM::VST1d8Qwb_fixed: 2721 case ARM::VST1d16Qwb_fixed: 2722 case ARM::VST1d32Qwb_fixed: 2723 case ARM::VST1d64Qwb_fixed: 2724 case ARM::VST1d8Qwb_register: 2725 case ARM::VST1d16Qwb_register: 2726 case ARM::VST1d32Qwb_register: 2727 case ARM::VST1d64Qwb_register: 2728 case ARM::VST2d8wb_fixed: 2729 case ARM::VST2d16wb_fixed: 2730 case ARM::VST2d32wb_fixed: 2731 case ARM::VST2d8wb_register: 2732 case ARM::VST2d16wb_register: 2733 case ARM::VST2d32wb_register: 2734 case ARM::VST2q8wb_fixed: 2735 case ARM::VST2q16wb_fixed: 2736 case ARM::VST2q32wb_fixed: 2737 case ARM::VST2q8wb_register: 2738 case ARM::VST2q16wb_register: 2739 case ARM::VST2q32wb_register: 2740 case ARM::VST2b8wb_fixed: 2741 case ARM::VST2b16wb_fixed: 2742 case ARM::VST2b32wb_fixed: 2743 case ARM::VST2b8wb_register: 2744 case ARM::VST2b16wb_register: 2745 case ARM::VST2b32wb_register: 2746 if (Rm == 0xF) 2747 return MCDisassembler::Fail; 2748 Inst.addOperand(MCOperand::createImm(0)); 2749 break; 2750 case ARM::VST3d8_UPD: 2751 case ARM::VST3d16_UPD: 2752 case ARM::VST3d32_UPD: 2753 case ARM::VST3q8_UPD: 2754 case ARM::VST3q16_UPD: 2755 case ARM::VST3q32_UPD: 2756 case ARM::VST4d8_UPD: 2757 case ARM::VST4d16_UPD: 2758 case ARM::VST4d32_UPD: 2759 case ARM::VST4q8_UPD: 2760 case ARM::VST4q16_UPD: 2761 case ARM::VST4q32_UPD: 2762 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2763 return MCDisassembler::Fail; 2764 break; 2765 default: 2766 break; 2767 } 2768 2769 // AddrMode6 Base (register+alignment) 2770 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2771 return MCDisassembler::Fail; 2772 2773 // AddrMode6 Offset (register) 2774 switch (Inst.getOpcode()) { 2775 default: 2776 if (Rm == 0xD) 2777 Inst.addOperand(MCOperand::createReg(0)); 2778 else if (Rm != 0xF) { 2779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2780 return MCDisassembler::Fail; 2781 } 2782 break; 2783 case ARM::VST1d8wb_fixed: 2784 case ARM::VST1d16wb_fixed: 2785 case ARM::VST1d32wb_fixed: 2786 case ARM::VST1d64wb_fixed: 2787 case ARM::VST1q8wb_fixed: 2788 case ARM::VST1q16wb_fixed: 2789 case ARM::VST1q32wb_fixed: 2790 case ARM::VST1q64wb_fixed: 2791 case ARM::VST1d8Twb_fixed: 2792 case ARM::VST1d16Twb_fixed: 2793 case ARM::VST1d32Twb_fixed: 2794 case ARM::VST1d64Twb_fixed: 2795 case ARM::VST1d8Qwb_fixed: 2796 case ARM::VST1d16Qwb_fixed: 2797 case ARM::VST1d32Qwb_fixed: 2798 case ARM::VST1d64Qwb_fixed: 2799 case ARM::VST2d8wb_fixed: 2800 case ARM::VST2d16wb_fixed: 2801 case ARM::VST2d32wb_fixed: 2802 case ARM::VST2q8wb_fixed: 2803 case ARM::VST2q16wb_fixed: 2804 case ARM::VST2q32wb_fixed: 2805 case ARM::VST2b8wb_fixed: 2806 case ARM::VST2b16wb_fixed: 2807 case ARM::VST2b32wb_fixed: 2808 break; 2809 } 2810 2811 // First input register 2812 switch (Inst.getOpcode()) { 2813 case ARM::VST1q16: 2814 case ARM::VST1q32: 2815 case ARM::VST1q64: 2816 case ARM::VST1q8: 2817 case ARM::VST1q16wb_fixed: 2818 case ARM::VST1q16wb_register: 2819 case ARM::VST1q32wb_fixed: 2820 case ARM::VST1q32wb_register: 2821 case ARM::VST1q64wb_fixed: 2822 case ARM::VST1q64wb_register: 2823 case ARM::VST1q8wb_fixed: 2824 case ARM::VST1q8wb_register: 2825 case ARM::VST2d16: 2826 case ARM::VST2d32: 2827 case ARM::VST2d8: 2828 case ARM::VST2d16wb_fixed: 2829 case ARM::VST2d16wb_register: 2830 case ARM::VST2d32wb_fixed: 2831 case ARM::VST2d32wb_register: 2832 case ARM::VST2d8wb_fixed: 2833 case ARM::VST2d8wb_register: 2834 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2835 return MCDisassembler::Fail; 2836 break; 2837 case ARM::VST2b16: 2838 case ARM::VST2b32: 2839 case ARM::VST2b8: 2840 case ARM::VST2b16wb_fixed: 2841 case ARM::VST2b16wb_register: 2842 case ARM::VST2b32wb_fixed: 2843 case ARM::VST2b32wb_register: 2844 case ARM::VST2b8wb_fixed: 2845 case ARM::VST2b8wb_register: 2846 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2847 return MCDisassembler::Fail; 2848 break; 2849 default: 2850 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2851 return MCDisassembler::Fail; 2852 } 2853 2854 // Second input register 2855 switch (Inst.getOpcode()) { 2856 case ARM::VST3d8: 2857 case ARM::VST3d16: 2858 case ARM::VST3d32: 2859 case ARM::VST3d8_UPD: 2860 case ARM::VST3d16_UPD: 2861 case ARM::VST3d32_UPD: 2862 case ARM::VST4d8: 2863 case ARM::VST4d16: 2864 case ARM::VST4d32: 2865 case ARM::VST4d8_UPD: 2866 case ARM::VST4d16_UPD: 2867 case ARM::VST4d32_UPD: 2868 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2869 return MCDisassembler::Fail; 2870 break; 2871 case ARM::VST3q8: 2872 case ARM::VST3q16: 2873 case ARM::VST3q32: 2874 case ARM::VST3q8_UPD: 2875 case ARM::VST3q16_UPD: 2876 case ARM::VST3q32_UPD: 2877 case ARM::VST4q8: 2878 case ARM::VST4q16: 2879 case ARM::VST4q32: 2880 case ARM::VST4q8_UPD: 2881 case ARM::VST4q16_UPD: 2882 case ARM::VST4q32_UPD: 2883 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2884 return MCDisassembler::Fail; 2885 break; 2886 default: 2887 break; 2888 } 2889 2890 // Third input register 2891 switch (Inst.getOpcode()) { 2892 case ARM::VST3d8: 2893 case ARM::VST3d16: 2894 case ARM::VST3d32: 2895 case ARM::VST3d8_UPD: 2896 case ARM::VST3d16_UPD: 2897 case ARM::VST3d32_UPD: 2898 case ARM::VST4d8: 2899 case ARM::VST4d16: 2900 case ARM::VST4d32: 2901 case ARM::VST4d8_UPD: 2902 case ARM::VST4d16_UPD: 2903 case ARM::VST4d32_UPD: 2904 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2905 return MCDisassembler::Fail; 2906 break; 2907 case ARM::VST3q8: 2908 case ARM::VST3q16: 2909 case ARM::VST3q32: 2910 case ARM::VST3q8_UPD: 2911 case ARM::VST3q16_UPD: 2912 case ARM::VST3q32_UPD: 2913 case ARM::VST4q8: 2914 case ARM::VST4q16: 2915 case ARM::VST4q32: 2916 case ARM::VST4q8_UPD: 2917 case ARM::VST4q16_UPD: 2918 case ARM::VST4q32_UPD: 2919 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2920 return MCDisassembler::Fail; 2921 break; 2922 default: 2923 break; 2924 } 2925 2926 // Fourth input register 2927 switch (Inst.getOpcode()) { 2928 case ARM::VST4d8: 2929 case ARM::VST4d16: 2930 case ARM::VST4d32: 2931 case ARM::VST4d8_UPD: 2932 case ARM::VST4d16_UPD: 2933 case ARM::VST4d32_UPD: 2934 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2935 return MCDisassembler::Fail; 2936 break; 2937 case ARM::VST4q8: 2938 case ARM::VST4q16: 2939 case ARM::VST4q32: 2940 case ARM::VST4q8_UPD: 2941 case ARM::VST4q16_UPD: 2942 case ARM::VST4q32_UPD: 2943 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2944 return MCDisassembler::Fail; 2945 break; 2946 default: 2947 break; 2948 } 2949 2950 return S; 2951 } 2952 2953 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2954 uint64_t Address, const void *Decoder) { 2955 DecodeStatus S = MCDisassembler::Success; 2956 2957 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2958 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2959 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2960 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2961 unsigned align = fieldFromInstruction(Insn, 4, 1); 2962 unsigned size = fieldFromInstruction(Insn, 6, 2); 2963 2964 if (size == 0 && align == 1) 2965 return MCDisassembler::Fail; 2966 align *= (1 << size); 2967 2968 switch (Inst.getOpcode()) { 2969 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2970 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2971 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2972 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2973 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2974 return MCDisassembler::Fail; 2975 break; 2976 default: 2977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2978 return MCDisassembler::Fail; 2979 break; 2980 } 2981 if (Rm != 0xF) { 2982 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2983 return MCDisassembler::Fail; 2984 } 2985 2986 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2987 return MCDisassembler::Fail; 2988 Inst.addOperand(MCOperand::createImm(align)); 2989 2990 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2991 // variant encodes Rm == 0xf. Anything else is a register offset post- 2992 // increment and we need to add the register operand to the instruction. 2993 if (Rm != 0xD && Rm != 0xF && 2994 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2995 return MCDisassembler::Fail; 2996 2997 return S; 2998 } 2999 3000 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3001 uint64_t Address, const void *Decoder) { 3002 DecodeStatus S = MCDisassembler::Success; 3003 3004 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3005 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3006 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3007 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3008 unsigned align = fieldFromInstruction(Insn, 4, 1); 3009 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3010 align *= 2*size; 3011 3012 switch (Inst.getOpcode()) { 3013 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3014 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3015 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3016 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3017 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3018 return MCDisassembler::Fail; 3019 break; 3020 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3021 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3022 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3023 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3024 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3025 return MCDisassembler::Fail; 3026 break; 3027 default: 3028 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3029 return MCDisassembler::Fail; 3030 break; 3031 } 3032 3033 if (Rm != 0xF) 3034 Inst.addOperand(MCOperand::createImm(0)); 3035 3036 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3037 return MCDisassembler::Fail; 3038 Inst.addOperand(MCOperand::createImm(align)); 3039 3040 if (Rm != 0xD && Rm != 0xF) { 3041 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3042 return MCDisassembler::Fail; 3043 } 3044 3045 return S; 3046 } 3047 3048 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3049 uint64_t Address, const void *Decoder) { 3050 DecodeStatus S = MCDisassembler::Success; 3051 3052 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3053 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3054 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3055 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3056 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3057 3058 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3059 return MCDisassembler::Fail; 3060 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3061 return MCDisassembler::Fail; 3062 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3063 return MCDisassembler::Fail; 3064 if (Rm != 0xF) { 3065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3066 return MCDisassembler::Fail; 3067 } 3068 3069 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3070 return MCDisassembler::Fail; 3071 Inst.addOperand(MCOperand::createImm(0)); 3072 3073 if (Rm == 0xD) 3074 Inst.addOperand(MCOperand::createReg(0)); 3075 else if (Rm != 0xF) { 3076 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3077 return MCDisassembler::Fail; 3078 } 3079 3080 return S; 3081 } 3082 3083 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3084 uint64_t Address, const void *Decoder) { 3085 DecodeStatus S = MCDisassembler::Success; 3086 3087 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3088 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3089 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3090 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3091 unsigned size = fieldFromInstruction(Insn, 6, 2); 3092 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3093 unsigned align = fieldFromInstruction(Insn, 4, 1); 3094 3095 if (size == 0x3) { 3096 if (align == 0) 3097 return MCDisassembler::Fail; 3098 align = 16; 3099 } else { 3100 if (size == 2) { 3101 align *= 8; 3102 } else { 3103 size = 1 << size; 3104 align *= 4*size; 3105 } 3106 } 3107 3108 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3109 return MCDisassembler::Fail; 3110 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3111 return MCDisassembler::Fail; 3112 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3113 return MCDisassembler::Fail; 3114 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3115 return MCDisassembler::Fail; 3116 if (Rm != 0xF) { 3117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3118 return MCDisassembler::Fail; 3119 } 3120 3121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3122 return MCDisassembler::Fail; 3123 Inst.addOperand(MCOperand::createImm(align)); 3124 3125 if (Rm == 0xD) 3126 Inst.addOperand(MCOperand::createReg(0)); 3127 else if (Rm != 0xF) { 3128 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3129 return MCDisassembler::Fail; 3130 } 3131 3132 return S; 3133 } 3134 3135 static DecodeStatus 3136 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3137 uint64_t Address, const void *Decoder) { 3138 DecodeStatus S = MCDisassembler::Success; 3139 3140 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3141 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3142 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3143 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3144 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3145 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3146 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3147 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3148 3149 if (Q) { 3150 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3151 return MCDisassembler::Fail; 3152 } else { 3153 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3154 return MCDisassembler::Fail; 3155 } 3156 3157 Inst.addOperand(MCOperand::createImm(imm)); 3158 3159 switch (Inst.getOpcode()) { 3160 case ARM::VORRiv4i16: 3161 case ARM::VORRiv2i32: 3162 case ARM::VBICiv4i16: 3163 case ARM::VBICiv2i32: 3164 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3165 return MCDisassembler::Fail; 3166 break; 3167 case ARM::VORRiv8i16: 3168 case ARM::VORRiv4i32: 3169 case ARM::VBICiv8i16: 3170 case ARM::VBICiv4i32: 3171 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3172 return MCDisassembler::Fail; 3173 break; 3174 default: 3175 break; 3176 } 3177 3178 return S; 3179 } 3180 3181 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3182 uint64_t Address, const void *Decoder) { 3183 DecodeStatus S = MCDisassembler::Success; 3184 3185 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3186 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3187 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3188 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3189 unsigned size = fieldFromInstruction(Insn, 18, 2); 3190 3191 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3192 return MCDisassembler::Fail; 3193 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3194 return MCDisassembler::Fail; 3195 Inst.addOperand(MCOperand::createImm(8 << size)); 3196 3197 return S; 3198 } 3199 3200 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3201 uint64_t Address, const void *Decoder) { 3202 Inst.addOperand(MCOperand::createImm(8 - Val)); 3203 return MCDisassembler::Success; 3204 } 3205 3206 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3207 uint64_t Address, const void *Decoder) { 3208 Inst.addOperand(MCOperand::createImm(16 - Val)); 3209 return MCDisassembler::Success; 3210 } 3211 3212 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3213 uint64_t Address, const void *Decoder) { 3214 Inst.addOperand(MCOperand::createImm(32 - Val)); 3215 return MCDisassembler::Success; 3216 } 3217 3218 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3219 uint64_t Address, const void *Decoder) { 3220 Inst.addOperand(MCOperand::createImm(64 - Val)); 3221 return MCDisassembler::Success; 3222 } 3223 3224 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3225 uint64_t Address, const void *Decoder) { 3226 DecodeStatus S = MCDisassembler::Success; 3227 3228 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3229 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3230 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3231 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3232 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3233 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3234 unsigned op = fieldFromInstruction(Insn, 6, 1); 3235 3236 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3237 return MCDisassembler::Fail; 3238 if (op) { 3239 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3240 return MCDisassembler::Fail; // Writeback 3241 } 3242 3243 switch (Inst.getOpcode()) { 3244 case ARM::VTBL2: 3245 case ARM::VTBX2: 3246 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3247 return MCDisassembler::Fail; 3248 break; 3249 default: 3250 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3251 return MCDisassembler::Fail; 3252 } 3253 3254 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3255 return MCDisassembler::Fail; 3256 3257 return S; 3258 } 3259 3260 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3261 uint64_t Address, const void *Decoder) { 3262 DecodeStatus S = MCDisassembler::Success; 3263 3264 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3265 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3266 3267 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3268 return MCDisassembler::Fail; 3269 3270 switch(Inst.getOpcode()) { 3271 default: 3272 return MCDisassembler::Fail; 3273 case ARM::tADR: 3274 break; // tADR does not explicitly represent the PC as an operand. 3275 case ARM::tADDrSPi: 3276 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3277 break; 3278 } 3279 3280 Inst.addOperand(MCOperand::createImm(imm)); 3281 return S; 3282 } 3283 3284 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3285 uint64_t Address, const void *Decoder) { 3286 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3287 true, 2, Inst, Decoder)) 3288 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3289 return MCDisassembler::Success; 3290 } 3291 3292 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3293 uint64_t Address, const void *Decoder) { 3294 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3295 true, 4, Inst, Decoder)) 3296 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3297 return MCDisassembler::Success; 3298 } 3299 3300 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3301 uint64_t Address, const void *Decoder) { 3302 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3303 true, 2, Inst, Decoder)) 3304 Inst.addOperand(MCOperand::createImm(Val << 1)); 3305 return MCDisassembler::Success; 3306 } 3307 3308 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3309 uint64_t Address, const void *Decoder) { 3310 DecodeStatus S = MCDisassembler::Success; 3311 3312 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3313 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3314 3315 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3316 return MCDisassembler::Fail; 3317 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3318 return MCDisassembler::Fail; 3319 3320 return S; 3321 } 3322 3323 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3324 uint64_t Address, const void *Decoder) { 3325 DecodeStatus S = MCDisassembler::Success; 3326 3327 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3328 unsigned imm = fieldFromInstruction(Val, 3, 5); 3329 3330 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3331 return MCDisassembler::Fail; 3332 Inst.addOperand(MCOperand::createImm(imm)); 3333 3334 return S; 3335 } 3336 3337 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3338 uint64_t Address, const void *Decoder) { 3339 unsigned imm = Val << 2; 3340 3341 Inst.addOperand(MCOperand::createImm(imm)); 3342 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3343 3344 return MCDisassembler::Success; 3345 } 3346 3347 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3348 uint64_t Address, const void *Decoder) { 3349 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3350 Inst.addOperand(MCOperand::createImm(Val)); 3351 3352 return MCDisassembler::Success; 3353 } 3354 3355 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3356 uint64_t Address, const void *Decoder) { 3357 DecodeStatus S = MCDisassembler::Success; 3358 3359 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3360 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3361 unsigned imm = fieldFromInstruction(Val, 0, 2); 3362 3363 // Thumb stores cannot use PC as dest register. 3364 switch (Inst.getOpcode()) { 3365 case ARM::t2STRHs: 3366 case ARM::t2STRBs: 3367 case ARM::t2STRs: 3368 if (Rn == 15) 3369 return MCDisassembler::Fail; 3370 break; 3371 default: 3372 break; 3373 } 3374 3375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3376 return MCDisassembler::Fail; 3377 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3378 return MCDisassembler::Fail; 3379 Inst.addOperand(MCOperand::createImm(imm)); 3380 3381 return S; 3382 } 3383 3384 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3385 uint64_t Address, const void *Decoder) { 3386 DecodeStatus S = MCDisassembler::Success; 3387 3388 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3389 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3390 3391 const FeatureBitset &featureBits = 3392 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3393 3394 bool hasMP = featureBits[ARM::FeatureMP]; 3395 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3396 3397 if (Rn == 15) { 3398 switch (Inst.getOpcode()) { 3399 case ARM::t2LDRBs: 3400 Inst.setOpcode(ARM::t2LDRBpci); 3401 break; 3402 case ARM::t2LDRHs: 3403 Inst.setOpcode(ARM::t2LDRHpci); 3404 break; 3405 case ARM::t2LDRSHs: 3406 Inst.setOpcode(ARM::t2LDRSHpci); 3407 break; 3408 case ARM::t2LDRSBs: 3409 Inst.setOpcode(ARM::t2LDRSBpci); 3410 break; 3411 case ARM::t2LDRs: 3412 Inst.setOpcode(ARM::t2LDRpci); 3413 break; 3414 case ARM::t2PLDs: 3415 Inst.setOpcode(ARM::t2PLDpci); 3416 break; 3417 case ARM::t2PLIs: 3418 Inst.setOpcode(ARM::t2PLIpci); 3419 break; 3420 default: 3421 return MCDisassembler::Fail; 3422 } 3423 3424 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3425 } 3426 3427 if (Rt == 15) { 3428 switch (Inst.getOpcode()) { 3429 case ARM::t2LDRSHs: 3430 return MCDisassembler::Fail; 3431 case ARM::t2LDRHs: 3432 Inst.setOpcode(ARM::t2PLDWs); 3433 break; 3434 case ARM::t2LDRSBs: 3435 Inst.setOpcode(ARM::t2PLIs); 3436 break; 3437 default: 3438 break; 3439 } 3440 } 3441 3442 switch (Inst.getOpcode()) { 3443 case ARM::t2PLDs: 3444 break; 3445 case ARM::t2PLIs: 3446 if (!hasV7Ops) 3447 return MCDisassembler::Fail; 3448 break; 3449 case ARM::t2PLDWs: 3450 if (!hasV7Ops || !hasMP) 3451 return MCDisassembler::Fail; 3452 break; 3453 default: 3454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3455 return MCDisassembler::Fail; 3456 } 3457 3458 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3459 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3460 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3461 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3462 return MCDisassembler::Fail; 3463 3464 return S; 3465 } 3466 3467 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3468 uint64_t Address, const void* Decoder) { 3469 DecodeStatus S = MCDisassembler::Success; 3470 3471 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3472 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3473 unsigned U = fieldFromInstruction(Insn, 9, 1); 3474 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3475 imm |= (U << 8); 3476 imm |= (Rn << 9); 3477 unsigned add = fieldFromInstruction(Insn, 9, 1); 3478 3479 const FeatureBitset &featureBits = 3480 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3481 3482 bool hasMP = featureBits[ARM::FeatureMP]; 3483 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3484 3485 if (Rn == 15) { 3486 switch (Inst.getOpcode()) { 3487 case ARM::t2LDRi8: 3488 Inst.setOpcode(ARM::t2LDRpci); 3489 break; 3490 case ARM::t2LDRBi8: 3491 Inst.setOpcode(ARM::t2LDRBpci); 3492 break; 3493 case ARM::t2LDRSBi8: 3494 Inst.setOpcode(ARM::t2LDRSBpci); 3495 break; 3496 case ARM::t2LDRHi8: 3497 Inst.setOpcode(ARM::t2LDRHpci); 3498 break; 3499 case ARM::t2LDRSHi8: 3500 Inst.setOpcode(ARM::t2LDRSHpci); 3501 break; 3502 case ARM::t2PLDi8: 3503 Inst.setOpcode(ARM::t2PLDpci); 3504 break; 3505 case ARM::t2PLIi8: 3506 Inst.setOpcode(ARM::t2PLIpci); 3507 break; 3508 default: 3509 return MCDisassembler::Fail; 3510 } 3511 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3512 } 3513 3514 if (Rt == 15) { 3515 switch (Inst.getOpcode()) { 3516 case ARM::t2LDRSHi8: 3517 return MCDisassembler::Fail; 3518 case ARM::t2LDRHi8: 3519 if (!add) 3520 Inst.setOpcode(ARM::t2PLDWi8); 3521 break; 3522 case ARM::t2LDRSBi8: 3523 Inst.setOpcode(ARM::t2PLIi8); 3524 break; 3525 default: 3526 break; 3527 } 3528 } 3529 3530 switch (Inst.getOpcode()) { 3531 case ARM::t2PLDi8: 3532 break; 3533 case ARM::t2PLIi8: 3534 if (!hasV7Ops) 3535 return MCDisassembler::Fail; 3536 break; 3537 case ARM::t2PLDWi8: 3538 if (!hasV7Ops || !hasMP) 3539 return MCDisassembler::Fail; 3540 break; 3541 default: 3542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3543 return MCDisassembler::Fail; 3544 } 3545 3546 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3547 return MCDisassembler::Fail; 3548 return S; 3549 } 3550 3551 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3552 uint64_t Address, const void* Decoder) { 3553 DecodeStatus S = MCDisassembler::Success; 3554 3555 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3556 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3557 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3558 imm |= (Rn << 13); 3559 3560 const FeatureBitset &featureBits = 3561 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3562 3563 bool hasMP = featureBits[ARM::FeatureMP]; 3564 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3565 3566 if (Rn == 15) { 3567 switch (Inst.getOpcode()) { 3568 case ARM::t2LDRi12: 3569 Inst.setOpcode(ARM::t2LDRpci); 3570 break; 3571 case ARM::t2LDRHi12: 3572 Inst.setOpcode(ARM::t2LDRHpci); 3573 break; 3574 case ARM::t2LDRSHi12: 3575 Inst.setOpcode(ARM::t2LDRSHpci); 3576 break; 3577 case ARM::t2LDRBi12: 3578 Inst.setOpcode(ARM::t2LDRBpci); 3579 break; 3580 case ARM::t2LDRSBi12: 3581 Inst.setOpcode(ARM::t2LDRSBpci); 3582 break; 3583 case ARM::t2PLDi12: 3584 Inst.setOpcode(ARM::t2PLDpci); 3585 break; 3586 case ARM::t2PLIi12: 3587 Inst.setOpcode(ARM::t2PLIpci); 3588 break; 3589 default: 3590 return MCDisassembler::Fail; 3591 } 3592 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3593 } 3594 3595 if (Rt == 15) { 3596 switch (Inst.getOpcode()) { 3597 case ARM::t2LDRSHi12: 3598 return MCDisassembler::Fail; 3599 case ARM::t2LDRHi12: 3600 Inst.setOpcode(ARM::t2PLDWi12); 3601 break; 3602 case ARM::t2LDRSBi12: 3603 Inst.setOpcode(ARM::t2PLIi12); 3604 break; 3605 default: 3606 break; 3607 } 3608 } 3609 3610 switch (Inst.getOpcode()) { 3611 case ARM::t2PLDi12: 3612 break; 3613 case ARM::t2PLIi12: 3614 if (!hasV7Ops) 3615 return MCDisassembler::Fail; 3616 break; 3617 case ARM::t2PLDWi12: 3618 if (!hasV7Ops || !hasMP) 3619 return MCDisassembler::Fail; 3620 break; 3621 default: 3622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3623 return MCDisassembler::Fail; 3624 } 3625 3626 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 return S; 3629 } 3630 3631 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3632 uint64_t Address, const void* Decoder) { 3633 DecodeStatus S = MCDisassembler::Success; 3634 3635 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3636 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3637 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3638 imm |= (Rn << 9); 3639 3640 if (Rn == 15) { 3641 switch (Inst.getOpcode()) { 3642 case ARM::t2LDRT: 3643 Inst.setOpcode(ARM::t2LDRpci); 3644 break; 3645 case ARM::t2LDRBT: 3646 Inst.setOpcode(ARM::t2LDRBpci); 3647 break; 3648 case ARM::t2LDRHT: 3649 Inst.setOpcode(ARM::t2LDRHpci); 3650 break; 3651 case ARM::t2LDRSBT: 3652 Inst.setOpcode(ARM::t2LDRSBpci); 3653 break; 3654 case ARM::t2LDRSHT: 3655 Inst.setOpcode(ARM::t2LDRSHpci); 3656 break; 3657 default: 3658 return MCDisassembler::Fail; 3659 } 3660 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3661 } 3662 3663 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3664 return MCDisassembler::Fail; 3665 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3666 return MCDisassembler::Fail; 3667 return S; 3668 } 3669 3670 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3671 uint64_t Address, const void* Decoder) { 3672 DecodeStatus S = MCDisassembler::Success; 3673 3674 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3675 unsigned U = fieldFromInstruction(Insn, 23, 1); 3676 int imm = fieldFromInstruction(Insn, 0, 12); 3677 3678 const FeatureBitset &featureBits = 3679 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3680 3681 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3682 3683 if (Rt == 15) { 3684 switch (Inst.getOpcode()) { 3685 case ARM::t2LDRBpci: 3686 case ARM::t2LDRHpci: 3687 Inst.setOpcode(ARM::t2PLDpci); 3688 break; 3689 case ARM::t2LDRSBpci: 3690 Inst.setOpcode(ARM::t2PLIpci); 3691 break; 3692 case ARM::t2LDRSHpci: 3693 return MCDisassembler::Fail; 3694 default: 3695 break; 3696 } 3697 } 3698 3699 switch(Inst.getOpcode()) { 3700 case ARM::t2PLDpci: 3701 break; 3702 case ARM::t2PLIpci: 3703 if (!hasV7Ops) 3704 return MCDisassembler::Fail; 3705 break; 3706 default: 3707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3708 return MCDisassembler::Fail; 3709 } 3710 3711 if (!U) { 3712 // Special case for #-0. 3713 if (imm == 0) 3714 imm = INT32_MIN; 3715 else 3716 imm = -imm; 3717 } 3718 Inst.addOperand(MCOperand::createImm(imm)); 3719 3720 return S; 3721 } 3722 3723 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3724 uint64_t Address, const void *Decoder) { 3725 if (Val == 0) 3726 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3727 else { 3728 int imm = Val & 0xFF; 3729 3730 if (!(Val & 0x100)) imm *= -1; 3731 Inst.addOperand(MCOperand::createImm(imm * 4)); 3732 } 3733 3734 return MCDisassembler::Success; 3735 } 3736 3737 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3738 uint64_t Address, const void *Decoder) { 3739 DecodeStatus S = MCDisassembler::Success; 3740 3741 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3742 unsigned imm = fieldFromInstruction(Val, 0, 9); 3743 3744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3745 return MCDisassembler::Fail; 3746 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3747 return MCDisassembler::Fail; 3748 3749 return S; 3750 } 3751 3752 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3753 uint64_t Address, const void *Decoder) { 3754 DecodeStatus S = MCDisassembler::Success; 3755 3756 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3757 unsigned imm = fieldFromInstruction(Val, 0, 8); 3758 3759 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 3762 Inst.addOperand(MCOperand::createImm(imm)); 3763 3764 return S; 3765 } 3766 3767 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3768 uint64_t Address, const void *Decoder) { 3769 int imm = Val & 0xFF; 3770 if (Val == 0) 3771 imm = INT32_MIN; 3772 else if (!(Val & 0x100)) 3773 imm *= -1; 3774 Inst.addOperand(MCOperand::createImm(imm)); 3775 3776 return MCDisassembler::Success; 3777 } 3778 3779 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3780 uint64_t Address, const void *Decoder) { 3781 DecodeStatus S = MCDisassembler::Success; 3782 3783 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3784 unsigned imm = fieldFromInstruction(Val, 0, 9); 3785 3786 // Thumb stores cannot use PC as dest register. 3787 switch (Inst.getOpcode()) { 3788 case ARM::t2STRT: 3789 case ARM::t2STRBT: 3790 case ARM::t2STRHT: 3791 case ARM::t2STRi8: 3792 case ARM::t2STRHi8: 3793 case ARM::t2STRBi8: 3794 if (Rn == 15) 3795 return MCDisassembler::Fail; 3796 break; 3797 default: 3798 break; 3799 } 3800 3801 // Some instructions always use an additive offset. 3802 switch (Inst.getOpcode()) { 3803 case ARM::t2LDRT: 3804 case ARM::t2LDRBT: 3805 case ARM::t2LDRHT: 3806 case ARM::t2LDRSBT: 3807 case ARM::t2LDRSHT: 3808 case ARM::t2STRT: 3809 case ARM::t2STRBT: 3810 case ARM::t2STRHT: 3811 imm |= 0x100; 3812 break; 3813 default: 3814 break; 3815 } 3816 3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3818 return MCDisassembler::Fail; 3819 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3820 return MCDisassembler::Fail; 3821 3822 return S; 3823 } 3824 3825 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3826 uint64_t Address, const void *Decoder) { 3827 DecodeStatus S = MCDisassembler::Success; 3828 3829 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3830 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3831 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3832 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3833 addr |= Rn << 9; 3834 unsigned load = fieldFromInstruction(Insn, 20, 1); 3835 3836 if (Rn == 15) { 3837 switch (Inst.getOpcode()) { 3838 case ARM::t2LDR_PRE: 3839 case ARM::t2LDR_POST: 3840 Inst.setOpcode(ARM::t2LDRpci); 3841 break; 3842 case ARM::t2LDRB_PRE: 3843 case ARM::t2LDRB_POST: 3844 Inst.setOpcode(ARM::t2LDRBpci); 3845 break; 3846 case ARM::t2LDRH_PRE: 3847 case ARM::t2LDRH_POST: 3848 Inst.setOpcode(ARM::t2LDRHpci); 3849 break; 3850 case ARM::t2LDRSB_PRE: 3851 case ARM::t2LDRSB_POST: 3852 if (Rt == 15) 3853 Inst.setOpcode(ARM::t2PLIpci); 3854 else 3855 Inst.setOpcode(ARM::t2LDRSBpci); 3856 break; 3857 case ARM::t2LDRSH_PRE: 3858 case ARM::t2LDRSH_POST: 3859 Inst.setOpcode(ARM::t2LDRSHpci); 3860 break; 3861 default: 3862 return MCDisassembler::Fail; 3863 } 3864 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3865 } 3866 3867 if (!load) { 3868 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3869 return MCDisassembler::Fail; 3870 } 3871 3872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3873 return MCDisassembler::Fail; 3874 3875 if (load) { 3876 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3877 return MCDisassembler::Fail; 3878 } 3879 3880 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3881 return MCDisassembler::Fail; 3882 3883 return S; 3884 } 3885 3886 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3887 uint64_t Address, const void *Decoder) { 3888 DecodeStatus S = MCDisassembler::Success; 3889 3890 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3891 unsigned imm = fieldFromInstruction(Val, 0, 12); 3892 3893 // Thumb stores cannot use PC as dest register. 3894 switch (Inst.getOpcode()) { 3895 case ARM::t2STRi12: 3896 case ARM::t2STRBi12: 3897 case ARM::t2STRHi12: 3898 if (Rn == 15) 3899 return MCDisassembler::Fail; 3900 break; 3901 default: 3902 break; 3903 } 3904 3905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3906 return MCDisassembler::Fail; 3907 Inst.addOperand(MCOperand::createImm(imm)); 3908 3909 return S; 3910 } 3911 3912 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3913 uint64_t Address, const void *Decoder) { 3914 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3915 3916 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3917 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3918 Inst.addOperand(MCOperand::createImm(imm)); 3919 3920 return MCDisassembler::Success; 3921 } 3922 3923 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3924 uint64_t Address, const void *Decoder) { 3925 DecodeStatus S = MCDisassembler::Success; 3926 3927 if (Inst.getOpcode() == ARM::tADDrSP) { 3928 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3929 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3930 3931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3932 return MCDisassembler::Fail; 3933 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3935 return MCDisassembler::Fail; 3936 } else if (Inst.getOpcode() == ARM::tADDspr) { 3937 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3938 3939 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3940 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3942 return MCDisassembler::Fail; 3943 } 3944 3945 return S; 3946 } 3947 3948 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3949 uint64_t Address, const void *Decoder) { 3950 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3951 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3952 3953 Inst.addOperand(MCOperand::createImm(imod)); 3954 Inst.addOperand(MCOperand::createImm(flags)); 3955 3956 return MCDisassembler::Success; 3957 } 3958 3959 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3960 uint64_t Address, const void *Decoder) { 3961 DecodeStatus S = MCDisassembler::Success; 3962 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3963 unsigned add = fieldFromInstruction(Insn, 4, 1); 3964 3965 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3966 return MCDisassembler::Fail; 3967 Inst.addOperand(MCOperand::createImm(add)); 3968 3969 return S; 3970 } 3971 3972 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3973 uint64_t Address, const void *Decoder) { 3974 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3975 // Note only one trailing zero not two. Also the J1 and J2 values are from 3976 // the encoded instruction. So here change to I1 and I2 values via: 3977 // I1 = NOT(J1 EOR S); 3978 // I2 = NOT(J2 EOR S); 3979 // and build the imm32 with two trailing zeros as documented: 3980 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3981 unsigned S = (Val >> 23) & 1; 3982 unsigned J1 = (Val >> 22) & 1; 3983 unsigned J2 = (Val >> 21) & 1; 3984 unsigned I1 = !(J1 ^ S); 3985 unsigned I2 = !(J2 ^ S); 3986 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3987 int imm32 = SignExtend32<25>(tmp << 1); 3988 3989 if (!tryAddingSymbolicOperand(Address, 3990 (Address & ~2u) + imm32 + 4, 3991 true, 4, Inst, Decoder)) 3992 Inst.addOperand(MCOperand::createImm(imm32)); 3993 return MCDisassembler::Success; 3994 } 3995 3996 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3997 uint64_t Address, const void *Decoder) { 3998 if (Val == 0xA || Val == 0xB) 3999 return MCDisassembler::Fail; 4000 4001 const FeatureBitset &featureBits = 4002 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4003 4004 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4005 return MCDisassembler::Fail; 4006 4007 Inst.addOperand(MCOperand::createImm(Val)); 4008 return MCDisassembler::Success; 4009 } 4010 4011 static DecodeStatus 4012 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4013 uint64_t Address, const void *Decoder) { 4014 DecodeStatus S = MCDisassembler::Success; 4015 4016 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4017 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4018 4019 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4020 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4021 return MCDisassembler::Fail; 4022 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 return S; 4025 } 4026 4027 static DecodeStatus 4028 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4029 uint64_t Address, const void *Decoder) { 4030 DecodeStatus S = MCDisassembler::Success; 4031 4032 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4033 if (pred == 0xE || pred == 0xF) { 4034 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4035 switch (opc) { 4036 default: 4037 return MCDisassembler::Fail; 4038 case 0xf3bf8f4: 4039 Inst.setOpcode(ARM::t2DSB); 4040 break; 4041 case 0xf3bf8f5: 4042 Inst.setOpcode(ARM::t2DMB); 4043 break; 4044 case 0xf3bf8f6: 4045 Inst.setOpcode(ARM::t2ISB); 4046 break; 4047 } 4048 4049 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4050 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4051 } 4052 4053 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4054 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4055 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4056 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4057 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4058 4059 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4060 return MCDisassembler::Fail; 4061 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4062 return MCDisassembler::Fail; 4063 4064 return S; 4065 } 4066 4067 // Decode a shifted immediate operand. These basically consist 4068 // of an 8-bit value, and a 4-bit directive that specifies either 4069 // a splat operation or a rotation. 4070 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4071 uint64_t Address, const void *Decoder) { 4072 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4073 if (ctrl == 0) { 4074 unsigned byte = fieldFromInstruction(Val, 8, 2); 4075 unsigned imm = fieldFromInstruction(Val, 0, 8); 4076 switch (byte) { 4077 case 0: 4078 Inst.addOperand(MCOperand::createImm(imm)); 4079 break; 4080 case 1: 4081 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4082 break; 4083 case 2: 4084 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4085 break; 4086 case 3: 4087 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4088 (imm << 8) | imm)); 4089 break; 4090 } 4091 } else { 4092 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4093 unsigned rot = fieldFromInstruction(Val, 7, 5); 4094 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4095 Inst.addOperand(MCOperand::createImm(imm)); 4096 } 4097 4098 return MCDisassembler::Success; 4099 } 4100 4101 static DecodeStatus 4102 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4103 uint64_t Address, const void *Decoder) { 4104 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4105 true, 2, Inst, Decoder)) 4106 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4107 return MCDisassembler::Success; 4108 } 4109 4110 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4111 uint64_t Address, 4112 const void *Decoder) { 4113 // Val is passed in as S:J1:J2:imm10:imm11 4114 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4115 // the encoded instruction. So here change to I1 and I2 values via: 4116 // I1 = NOT(J1 EOR S); 4117 // I2 = NOT(J2 EOR S); 4118 // and build the imm32 with one trailing zero as documented: 4119 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4120 unsigned S = (Val >> 23) & 1; 4121 unsigned J1 = (Val >> 22) & 1; 4122 unsigned J2 = (Val >> 21) & 1; 4123 unsigned I1 = !(J1 ^ S); 4124 unsigned I2 = !(J2 ^ S); 4125 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4126 int imm32 = SignExtend32<25>(tmp << 1); 4127 4128 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4129 true, 4, Inst, Decoder)) 4130 Inst.addOperand(MCOperand::createImm(imm32)); 4131 return MCDisassembler::Success; 4132 } 4133 4134 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4135 uint64_t Address, const void *Decoder) { 4136 if (Val & ~0xf) 4137 return MCDisassembler::Fail; 4138 4139 Inst.addOperand(MCOperand::createImm(Val)); 4140 return MCDisassembler::Success; 4141 } 4142 4143 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4144 uint64_t Address, const void *Decoder) { 4145 if (Val & ~0xf) 4146 return MCDisassembler::Fail; 4147 4148 Inst.addOperand(MCOperand::createImm(Val)); 4149 return MCDisassembler::Success; 4150 } 4151 4152 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4153 uint64_t Address, const void *Decoder) { 4154 DecodeStatus S = MCDisassembler::Success; 4155 const FeatureBitset &FeatureBits = 4156 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4157 4158 if (FeatureBits[ARM::FeatureMClass]) { 4159 unsigned ValLow = Val & 0xff; 4160 4161 // Validate the SYSm value first. 4162 switch (ValLow) { 4163 case 0: // apsr 4164 case 1: // iapsr 4165 case 2: // eapsr 4166 case 3: // xpsr 4167 case 5: // ipsr 4168 case 6: // epsr 4169 case 7: // iepsr 4170 case 8: // msp 4171 case 9: // psp 4172 case 16: // primask 4173 case 20: // control 4174 break; 4175 case 17: // basepri 4176 case 18: // basepri_max 4177 case 19: // faultmask 4178 if (!(FeatureBits[ARM::HasV7Ops])) 4179 // Values basepri, basepri_max and faultmask are only valid for v7m. 4180 return MCDisassembler::Fail; 4181 break; 4182 case 0x8a: // msplim_ns 4183 case 0x8b: // psplim_ns 4184 case 0x91: // basepri_ns 4185 case 0x93: // faultmask_ns 4186 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4187 return MCDisassembler::Fail; 4188 LLVM_FALLTHROUGH; 4189 case 10: // msplim 4190 case 11: // psplim 4191 case 0x88: // msp_ns 4192 case 0x89: // psp_ns 4193 case 0x90: // primask_ns 4194 case 0x94: // control_ns 4195 case 0x98: // sp_ns 4196 if (!(FeatureBits[ARM::Feature8MSecExt])) 4197 return MCDisassembler::Fail; 4198 break; 4199 default: 4200 // Architecturally defined as unpredictable 4201 S = MCDisassembler::SoftFail; 4202 break; 4203 } 4204 4205 if (Inst.getOpcode() == ARM::t2MSR_M) { 4206 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4207 if (!(FeatureBits[ARM::HasV7Ops])) { 4208 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4209 // unpredictable. 4210 if (Mask != 2) 4211 S = MCDisassembler::SoftFail; 4212 } 4213 else { 4214 // The ARMv7-M architecture stores an additional 2-bit mask value in 4215 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4216 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4217 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4218 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4219 // only if the processor includes the DSP extension. 4220 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4221 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4222 S = MCDisassembler::SoftFail; 4223 } 4224 } 4225 } else { 4226 // A/R class 4227 if (Val == 0) 4228 return MCDisassembler::Fail; 4229 } 4230 Inst.addOperand(MCOperand::createImm(Val)); 4231 return S; 4232 } 4233 4234 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4235 uint64_t Address, const void *Decoder) { 4236 unsigned R = fieldFromInstruction(Val, 5, 1); 4237 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4238 4239 // The table of encodings for these banked registers comes from B9.2.3 of the 4240 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4241 // neater. So by fiat, these values are UNPREDICTABLE: 4242 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4243 return MCDisassembler::Fail; 4244 4245 Inst.addOperand(MCOperand::createImm(Val)); 4246 return MCDisassembler::Success; 4247 } 4248 4249 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4250 uint64_t Address, const void *Decoder) { 4251 DecodeStatus S = MCDisassembler::Success; 4252 4253 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4254 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4255 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4256 4257 if (Rn == 0xF) 4258 S = MCDisassembler::SoftFail; 4259 4260 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4261 return MCDisassembler::Fail; 4262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4263 return MCDisassembler::Fail; 4264 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4265 return MCDisassembler::Fail; 4266 4267 return S; 4268 } 4269 4270 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4271 uint64_t Address, 4272 const void *Decoder) { 4273 DecodeStatus S = MCDisassembler::Success; 4274 4275 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4276 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4277 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4278 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4279 4280 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4281 return MCDisassembler::Fail; 4282 4283 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4284 S = MCDisassembler::SoftFail; 4285 4286 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4287 return MCDisassembler::Fail; 4288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4289 return MCDisassembler::Fail; 4290 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4291 return MCDisassembler::Fail; 4292 4293 return S; 4294 } 4295 4296 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4297 uint64_t Address, const void *Decoder) { 4298 DecodeStatus S = MCDisassembler::Success; 4299 4300 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4301 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4302 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4303 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4304 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4305 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4306 4307 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4308 4309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4310 return MCDisassembler::Fail; 4311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4312 return MCDisassembler::Fail; 4313 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4314 return MCDisassembler::Fail; 4315 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4316 return MCDisassembler::Fail; 4317 4318 return S; 4319 } 4320 4321 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4322 uint64_t Address, const void *Decoder) { 4323 DecodeStatus S = MCDisassembler::Success; 4324 4325 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4326 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4327 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4328 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4329 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4330 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4331 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4332 4333 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4334 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4335 4336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4337 return MCDisassembler::Fail; 4338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4339 return MCDisassembler::Fail; 4340 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4341 return MCDisassembler::Fail; 4342 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 4345 return S; 4346 } 4347 4348 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4349 uint64_t Address, const void *Decoder) { 4350 DecodeStatus S = MCDisassembler::Success; 4351 4352 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4353 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4354 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4355 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4356 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4357 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4358 4359 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4360 4361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4362 return MCDisassembler::Fail; 4363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4364 return MCDisassembler::Fail; 4365 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4366 return MCDisassembler::Fail; 4367 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4368 return MCDisassembler::Fail; 4369 4370 return S; 4371 } 4372 4373 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4374 uint64_t Address, const void *Decoder) { 4375 DecodeStatus S = MCDisassembler::Success; 4376 4377 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4378 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4379 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4380 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4381 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4382 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4383 4384 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4385 4386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4387 return MCDisassembler::Fail; 4388 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4389 return MCDisassembler::Fail; 4390 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4391 return MCDisassembler::Fail; 4392 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4393 return MCDisassembler::Fail; 4394 4395 return S; 4396 } 4397 4398 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4399 uint64_t Address, const void *Decoder) { 4400 DecodeStatus S = MCDisassembler::Success; 4401 4402 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4403 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4404 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4405 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4406 unsigned size = fieldFromInstruction(Insn, 10, 2); 4407 4408 unsigned align = 0; 4409 unsigned index = 0; 4410 switch (size) { 4411 default: 4412 return MCDisassembler::Fail; 4413 case 0: 4414 if (fieldFromInstruction(Insn, 4, 1)) 4415 return MCDisassembler::Fail; // UNDEFINED 4416 index = fieldFromInstruction(Insn, 5, 3); 4417 break; 4418 case 1: 4419 if (fieldFromInstruction(Insn, 5, 1)) 4420 return MCDisassembler::Fail; // UNDEFINED 4421 index = fieldFromInstruction(Insn, 6, 2); 4422 if (fieldFromInstruction(Insn, 4, 1)) 4423 align = 2; 4424 break; 4425 case 2: 4426 if (fieldFromInstruction(Insn, 6, 1)) 4427 return MCDisassembler::Fail; // UNDEFINED 4428 index = fieldFromInstruction(Insn, 7, 1); 4429 4430 switch (fieldFromInstruction(Insn, 4, 2)) { 4431 case 0 : 4432 align = 0; break; 4433 case 3: 4434 align = 4; break; 4435 default: 4436 return MCDisassembler::Fail; 4437 } 4438 break; 4439 } 4440 4441 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4442 return MCDisassembler::Fail; 4443 if (Rm != 0xF) { // Writeback 4444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4445 return MCDisassembler::Fail; 4446 } 4447 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4448 return MCDisassembler::Fail; 4449 Inst.addOperand(MCOperand::createImm(align)); 4450 if (Rm != 0xF) { 4451 if (Rm != 0xD) { 4452 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4453 return MCDisassembler::Fail; 4454 } else 4455 Inst.addOperand(MCOperand::createReg(0)); 4456 } 4457 4458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4459 return MCDisassembler::Fail; 4460 Inst.addOperand(MCOperand::createImm(index)); 4461 4462 return S; 4463 } 4464 4465 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4466 uint64_t Address, const void *Decoder) { 4467 DecodeStatus S = MCDisassembler::Success; 4468 4469 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4470 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4471 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4472 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4473 unsigned size = fieldFromInstruction(Insn, 10, 2); 4474 4475 unsigned align = 0; 4476 unsigned index = 0; 4477 switch (size) { 4478 default: 4479 return MCDisassembler::Fail; 4480 case 0: 4481 if (fieldFromInstruction(Insn, 4, 1)) 4482 return MCDisassembler::Fail; // UNDEFINED 4483 index = fieldFromInstruction(Insn, 5, 3); 4484 break; 4485 case 1: 4486 if (fieldFromInstruction(Insn, 5, 1)) 4487 return MCDisassembler::Fail; // UNDEFINED 4488 index = fieldFromInstruction(Insn, 6, 2); 4489 if (fieldFromInstruction(Insn, 4, 1)) 4490 align = 2; 4491 break; 4492 case 2: 4493 if (fieldFromInstruction(Insn, 6, 1)) 4494 return MCDisassembler::Fail; // UNDEFINED 4495 index = fieldFromInstruction(Insn, 7, 1); 4496 4497 switch (fieldFromInstruction(Insn, 4, 2)) { 4498 case 0: 4499 align = 0; break; 4500 case 3: 4501 align = 4; break; 4502 default: 4503 return MCDisassembler::Fail; 4504 } 4505 break; 4506 } 4507 4508 if (Rm != 0xF) { // Writeback 4509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4510 return MCDisassembler::Fail; 4511 } 4512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4513 return MCDisassembler::Fail; 4514 Inst.addOperand(MCOperand::createImm(align)); 4515 if (Rm != 0xF) { 4516 if (Rm != 0xD) { 4517 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4518 return MCDisassembler::Fail; 4519 } else 4520 Inst.addOperand(MCOperand::createReg(0)); 4521 } 4522 4523 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4524 return MCDisassembler::Fail; 4525 Inst.addOperand(MCOperand::createImm(index)); 4526 4527 return S; 4528 } 4529 4530 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4531 uint64_t Address, const void *Decoder) { 4532 DecodeStatus S = MCDisassembler::Success; 4533 4534 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4535 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4536 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4537 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4538 unsigned size = fieldFromInstruction(Insn, 10, 2); 4539 4540 unsigned align = 0; 4541 unsigned index = 0; 4542 unsigned inc = 1; 4543 switch (size) { 4544 default: 4545 return MCDisassembler::Fail; 4546 case 0: 4547 index = fieldFromInstruction(Insn, 5, 3); 4548 if (fieldFromInstruction(Insn, 4, 1)) 4549 align = 2; 4550 break; 4551 case 1: 4552 index = fieldFromInstruction(Insn, 6, 2); 4553 if (fieldFromInstruction(Insn, 4, 1)) 4554 align = 4; 4555 if (fieldFromInstruction(Insn, 5, 1)) 4556 inc = 2; 4557 break; 4558 case 2: 4559 if (fieldFromInstruction(Insn, 5, 1)) 4560 return MCDisassembler::Fail; // UNDEFINED 4561 index = fieldFromInstruction(Insn, 7, 1); 4562 if (fieldFromInstruction(Insn, 4, 1) != 0) 4563 align = 8; 4564 if (fieldFromInstruction(Insn, 6, 1)) 4565 inc = 2; 4566 break; 4567 } 4568 4569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4570 return MCDisassembler::Fail; 4571 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4572 return MCDisassembler::Fail; 4573 if (Rm != 0xF) { // Writeback 4574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4575 return MCDisassembler::Fail; 4576 } 4577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4578 return MCDisassembler::Fail; 4579 Inst.addOperand(MCOperand::createImm(align)); 4580 if (Rm != 0xF) { 4581 if (Rm != 0xD) { 4582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4583 return MCDisassembler::Fail; 4584 } else 4585 Inst.addOperand(MCOperand::createReg(0)); 4586 } 4587 4588 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4589 return MCDisassembler::Fail; 4590 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4591 return MCDisassembler::Fail; 4592 Inst.addOperand(MCOperand::createImm(index)); 4593 4594 return S; 4595 } 4596 4597 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4598 uint64_t Address, const void *Decoder) { 4599 DecodeStatus S = MCDisassembler::Success; 4600 4601 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4602 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4603 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4604 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4605 unsigned size = fieldFromInstruction(Insn, 10, 2); 4606 4607 unsigned align = 0; 4608 unsigned index = 0; 4609 unsigned inc = 1; 4610 switch (size) { 4611 default: 4612 return MCDisassembler::Fail; 4613 case 0: 4614 index = fieldFromInstruction(Insn, 5, 3); 4615 if (fieldFromInstruction(Insn, 4, 1)) 4616 align = 2; 4617 break; 4618 case 1: 4619 index = fieldFromInstruction(Insn, 6, 2); 4620 if (fieldFromInstruction(Insn, 4, 1)) 4621 align = 4; 4622 if (fieldFromInstruction(Insn, 5, 1)) 4623 inc = 2; 4624 break; 4625 case 2: 4626 if (fieldFromInstruction(Insn, 5, 1)) 4627 return MCDisassembler::Fail; // UNDEFINED 4628 index = fieldFromInstruction(Insn, 7, 1); 4629 if (fieldFromInstruction(Insn, 4, 1) != 0) 4630 align = 8; 4631 if (fieldFromInstruction(Insn, 6, 1)) 4632 inc = 2; 4633 break; 4634 } 4635 4636 if (Rm != 0xF) { // Writeback 4637 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4638 return MCDisassembler::Fail; 4639 } 4640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4641 return MCDisassembler::Fail; 4642 Inst.addOperand(MCOperand::createImm(align)); 4643 if (Rm != 0xF) { 4644 if (Rm != 0xD) { 4645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4646 return MCDisassembler::Fail; 4647 } else 4648 Inst.addOperand(MCOperand::createReg(0)); 4649 } 4650 4651 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4652 return MCDisassembler::Fail; 4653 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4654 return MCDisassembler::Fail; 4655 Inst.addOperand(MCOperand::createImm(index)); 4656 4657 return S; 4658 } 4659 4660 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4661 uint64_t Address, const void *Decoder) { 4662 DecodeStatus S = MCDisassembler::Success; 4663 4664 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4665 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4666 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4667 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4668 unsigned size = fieldFromInstruction(Insn, 10, 2); 4669 4670 unsigned align = 0; 4671 unsigned index = 0; 4672 unsigned inc = 1; 4673 switch (size) { 4674 default: 4675 return MCDisassembler::Fail; 4676 case 0: 4677 if (fieldFromInstruction(Insn, 4, 1)) 4678 return MCDisassembler::Fail; // UNDEFINED 4679 index = fieldFromInstruction(Insn, 5, 3); 4680 break; 4681 case 1: 4682 if (fieldFromInstruction(Insn, 4, 1)) 4683 return MCDisassembler::Fail; // UNDEFINED 4684 index = fieldFromInstruction(Insn, 6, 2); 4685 if (fieldFromInstruction(Insn, 5, 1)) 4686 inc = 2; 4687 break; 4688 case 2: 4689 if (fieldFromInstruction(Insn, 4, 2)) 4690 return MCDisassembler::Fail; // UNDEFINED 4691 index = fieldFromInstruction(Insn, 7, 1); 4692 if (fieldFromInstruction(Insn, 6, 1)) 4693 inc = 2; 4694 break; 4695 } 4696 4697 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4698 return MCDisassembler::Fail; 4699 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4700 return MCDisassembler::Fail; 4701 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4702 return MCDisassembler::Fail; 4703 4704 if (Rm != 0xF) { // Writeback 4705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4706 return MCDisassembler::Fail; 4707 } 4708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4709 return MCDisassembler::Fail; 4710 Inst.addOperand(MCOperand::createImm(align)); 4711 if (Rm != 0xF) { 4712 if (Rm != 0xD) { 4713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4714 return MCDisassembler::Fail; 4715 } else 4716 Inst.addOperand(MCOperand::createReg(0)); 4717 } 4718 4719 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4720 return MCDisassembler::Fail; 4721 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4722 return MCDisassembler::Fail; 4723 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4724 return MCDisassembler::Fail; 4725 Inst.addOperand(MCOperand::createImm(index)); 4726 4727 return S; 4728 } 4729 4730 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4731 uint64_t Address, const void *Decoder) { 4732 DecodeStatus S = MCDisassembler::Success; 4733 4734 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4735 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4736 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4737 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4738 unsigned size = fieldFromInstruction(Insn, 10, 2); 4739 4740 unsigned align = 0; 4741 unsigned index = 0; 4742 unsigned inc = 1; 4743 switch (size) { 4744 default: 4745 return MCDisassembler::Fail; 4746 case 0: 4747 if (fieldFromInstruction(Insn, 4, 1)) 4748 return MCDisassembler::Fail; // UNDEFINED 4749 index = fieldFromInstruction(Insn, 5, 3); 4750 break; 4751 case 1: 4752 if (fieldFromInstruction(Insn, 4, 1)) 4753 return MCDisassembler::Fail; // UNDEFINED 4754 index = fieldFromInstruction(Insn, 6, 2); 4755 if (fieldFromInstruction(Insn, 5, 1)) 4756 inc = 2; 4757 break; 4758 case 2: 4759 if (fieldFromInstruction(Insn, 4, 2)) 4760 return MCDisassembler::Fail; // UNDEFINED 4761 index = fieldFromInstruction(Insn, 7, 1); 4762 if (fieldFromInstruction(Insn, 6, 1)) 4763 inc = 2; 4764 break; 4765 } 4766 4767 if (Rm != 0xF) { // Writeback 4768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4769 return MCDisassembler::Fail; 4770 } 4771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4772 return MCDisassembler::Fail; 4773 Inst.addOperand(MCOperand::createImm(align)); 4774 if (Rm != 0xF) { 4775 if (Rm != 0xD) { 4776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4777 return MCDisassembler::Fail; 4778 } else 4779 Inst.addOperand(MCOperand::createReg(0)); 4780 } 4781 4782 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4783 return MCDisassembler::Fail; 4784 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4785 return MCDisassembler::Fail; 4786 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4787 return MCDisassembler::Fail; 4788 Inst.addOperand(MCOperand::createImm(index)); 4789 4790 return S; 4791 } 4792 4793 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4794 uint64_t Address, const void *Decoder) { 4795 DecodeStatus S = MCDisassembler::Success; 4796 4797 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4798 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4799 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4800 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4801 unsigned size = fieldFromInstruction(Insn, 10, 2); 4802 4803 unsigned align = 0; 4804 unsigned index = 0; 4805 unsigned inc = 1; 4806 switch (size) { 4807 default: 4808 return MCDisassembler::Fail; 4809 case 0: 4810 if (fieldFromInstruction(Insn, 4, 1)) 4811 align = 4; 4812 index = fieldFromInstruction(Insn, 5, 3); 4813 break; 4814 case 1: 4815 if (fieldFromInstruction(Insn, 4, 1)) 4816 align = 8; 4817 index = fieldFromInstruction(Insn, 6, 2); 4818 if (fieldFromInstruction(Insn, 5, 1)) 4819 inc = 2; 4820 break; 4821 case 2: 4822 switch (fieldFromInstruction(Insn, 4, 2)) { 4823 case 0: 4824 align = 0; break; 4825 case 3: 4826 return MCDisassembler::Fail; 4827 default: 4828 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4829 } 4830 4831 index = fieldFromInstruction(Insn, 7, 1); 4832 if (fieldFromInstruction(Insn, 6, 1)) 4833 inc = 2; 4834 break; 4835 } 4836 4837 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4838 return MCDisassembler::Fail; 4839 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4840 return MCDisassembler::Fail; 4841 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4842 return MCDisassembler::Fail; 4843 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4844 return MCDisassembler::Fail; 4845 4846 if (Rm != 0xF) { // Writeback 4847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4848 return MCDisassembler::Fail; 4849 } 4850 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4851 return MCDisassembler::Fail; 4852 Inst.addOperand(MCOperand::createImm(align)); 4853 if (Rm != 0xF) { 4854 if (Rm != 0xD) { 4855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4856 return MCDisassembler::Fail; 4857 } else 4858 Inst.addOperand(MCOperand::createReg(0)); 4859 } 4860 4861 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4862 return MCDisassembler::Fail; 4863 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4864 return MCDisassembler::Fail; 4865 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4866 return MCDisassembler::Fail; 4867 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4868 return MCDisassembler::Fail; 4869 Inst.addOperand(MCOperand::createImm(index)); 4870 4871 return S; 4872 } 4873 4874 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4875 uint64_t Address, const void *Decoder) { 4876 DecodeStatus S = MCDisassembler::Success; 4877 4878 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4879 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4880 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4881 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4882 unsigned size = fieldFromInstruction(Insn, 10, 2); 4883 4884 unsigned align = 0; 4885 unsigned index = 0; 4886 unsigned inc = 1; 4887 switch (size) { 4888 default: 4889 return MCDisassembler::Fail; 4890 case 0: 4891 if (fieldFromInstruction(Insn, 4, 1)) 4892 align = 4; 4893 index = fieldFromInstruction(Insn, 5, 3); 4894 break; 4895 case 1: 4896 if (fieldFromInstruction(Insn, 4, 1)) 4897 align = 8; 4898 index = fieldFromInstruction(Insn, 6, 2); 4899 if (fieldFromInstruction(Insn, 5, 1)) 4900 inc = 2; 4901 break; 4902 case 2: 4903 switch (fieldFromInstruction(Insn, 4, 2)) { 4904 case 0: 4905 align = 0; break; 4906 case 3: 4907 return MCDisassembler::Fail; 4908 default: 4909 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4910 } 4911 4912 index = fieldFromInstruction(Insn, 7, 1); 4913 if (fieldFromInstruction(Insn, 6, 1)) 4914 inc = 2; 4915 break; 4916 } 4917 4918 if (Rm != 0xF) { // Writeback 4919 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4920 return MCDisassembler::Fail; 4921 } 4922 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4923 return MCDisassembler::Fail; 4924 Inst.addOperand(MCOperand::createImm(align)); 4925 if (Rm != 0xF) { 4926 if (Rm != 0xD) { 4927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4928 return MCDisassembler::Fail; 4929 } else 4930 Inst.addOperand(MCOperand::createReg(0)); 4931 } 4932 4933 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4934 return MCDisassembler::Fail; 4935 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4936 return MCDisassembler::Fail; 4937 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4938 return MCDisassembler::Fail; 4939 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4940 return MCDisassembler::Fail; 4941 Inst.addOperand(MCOperand::createImm(index)); 4942 4943 return S; 4944 } 4945 4946 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4947 uint64_t Address, const void *Decoder) { 4948 DecodeStatus S = MCDisassembler::Success; 4949 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4950 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4951 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4952 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4953 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4954 4955 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4956 S = MCDisassembler::SoftFail; 4957 4958 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4959 return MCDisassembler::Fail; 4960 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4961 return MCDisassembler::Fail; 4962 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4963 return MCDisassembler::Fail; 4964 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4965 return MCDisassembler::Fail; 4966 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4967 return MCDisassembler::Fail; 4968 4969 return S; 4970 } 4971 4972 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4973 uint64_t Address, const void *Decoder) { 4974 DecodeStatus S = MCDisassembler::Success; 4975 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4976 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4977 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4978 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4979 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4980 4981 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4982 S = MCDisassembler::SoftFail; 4983 4984 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4985 return MCDisassembler::Fail; 4986 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4987 return MCDisassembler::Fail; 4988 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4989 return MCDisassembler::Fail; 4990 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4991 return MCDisassembler::Fail; 4992 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4993 return MCDisassembler::Fail; 4994 4995 return S; 4996 } 4997 4998 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4999 uint64_t Address, const void *Decoder) { 5000 DecodeStatus S = MCDisassembler::Success; 5001 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5002 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5003 5004 if (pred == 0xF) { 5005 pred = 0xE; 5006 S = MCDisassembler::SoftFail; 5007 } 5008 5009 if (mask == 0x0) 5010 return MCDisassembler::Fail; 5011 5012 Inst.addOperand(MCOperand::createImm(pred)); 5013 Inst.addOperand(MCOperand::createImm(mask)); 5014 return S; 5015 } 5016 5017 static DecodeStatus 5018 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5019 uint64_t Address, const void *Decoder) { 5020 DecodeStatus S = MCDisassembler::Success; 5021 5022 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5023 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5024 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5025 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5026 unsigned W = fieldFromInstruction(Insn, 21, 1); 5027 unsigned U = fieldFromInstruction(Insn, 23, 1); 5028 unsigned P = fieldFromInstruction(Insn, 24, 1); 5029 bool writeback = (W == 1) | (P == 0); 5030 5031 addr |= (U << 8) | (Rn << 9); 5032 5033 if (writeback && (Rn == Rt || Rn == Rt2)) 5034 Check(S, MCDisassembler::SoftFail); 5035 if (Rt == Rt2) 5036 Check(S, MCDisassembler::SoftFail); 5037 5038 // Rt 5039 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5040 return MCDisassembler::Fail; 5041 // Rt2 5042 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5043 return MCDisassembler::Fail; 5044 // Writeback operand 5045 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5046 return MCDisassembler::Fail; 5047 // addr 5048 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5049 return MCDisassembler::Fail; 5050 5051 return S; 5052 } 5053 5054 static DecodeStatus 5055 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5056 uint64_t Address, const void *Decoder) { 5057 DecodeStatus S = MCDisassembler::Success; 5058 5059 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5060 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5061 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5062 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5063 unsigned W = fieldFromInstruction(Insn, 21, 1); 5064 unsigned U = fieldFromInstruction(Insn, 23, 1); 5065 unsigned P = fieldFromInstruction(Insn, 24, 1); 5066 bool writeback = (W == 1) | (P == 0); 5067 5068 addr |= (U << 8) | (Rn << 9); 5069 5070 if (writeback && (Rn == Rt || Rn == Rt2)) 5071 Check(S, MCDisassembler::SoftFail); 5072 5073 // Writeback operand 5074 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5075 return MCDisassembler::Fail; 5076 // Rt 5077 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5078 return MCDisassembler::Fail; 5079 // Rt2 5080 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5081 return MCDisassembler::Fail; 5082 // addr 5083 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5084 return MCDisassembler::Fail; 5085 5086 return S; 5087 } 5088 5089 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5090 uint64_t Address, const void *Decoder) { 5091 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5092 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5093 if (sign1 != sign2) return MCDisassembler::Fail; 5094 5095 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5096 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5097 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5098 Val |= sign1 << 12; 5099 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5100 5101 return MCDisassembler::Success; 5102 } 5103 5104 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5105 uint64_t Address, 5106 const void *Decoder) { 5107 DecodeStatus S = MCDisassembler::Success; 5108 5109 // Shift of "asr #32" is not allowed in Thumb2 mode. 5110 if (Val == 0x20) S = MCDisassembler::Fail; 5111 Inst.addOperand(MCOperand::createImm(Val)); 5112 return S; 5113 } 5114 5115 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5116 uint64_t Address, const void *Decoder) { 5117 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5118 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5119 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5120 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5121 5122 if (pred == 0xF) 5123 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5124 5125 DecodeStatus S = MCDisassembler::Success; 5126 5127 if (Rt == Rn || Rn == Rt2) 5128 S = MCDisassembler::SoftFail; 5129 5130 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5131 return MCDisassembler::Fail; 5132 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5133 return MCDisassembler::Fail; 5134 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5135 return MCDisassembler::Fail; 5136 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5137 return MCDisassembler::Fail; 5138 5139 return S; 5140 } 5141 5142 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5143 uint64_t Address, const void *Decoder) { 5144 const FeatureBitset &featureBits = 5145 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5146 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5147 5148 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5149 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5150 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5151 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5152 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5153 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5154 unsigned op = fieldFromInstruction(Insn, 5, 1); 5155 5156 DecodeStatus S = MCDisassembler::Success; 5157 5158 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5159 if (!(imm & 0x38)) { 5160 if (cmode == 0xF) { 5161 if (op == 1) return MCDisassembler::Fail; 5162 Inst.setOpcode(ARM::VMOVv2f32); 5163 } 5164 if (hasFullFP16) { 5165 if (cmode == 0xE) { 5166 if (op == 1) { 5167 Inst.setOpcode(ARM::VMOVv1i64); 5168 } else { 5169 Inst.setOpcode(ARM::VMOVv8i8); 5170 } 5171 } 5172 if (cmode == 0xD) { 5173 if (op == 1) { 5174 Inst.setOpcode(ARM::VMVNv2i32); 5175 } else { 5176 Inst.setOpcode(ARM::VMOVv2i32); 5177 } 5178 } 5179 if (cmode == 0xC) { 5180 if (op == 1) { 5181 Inst.setOpcode(ARM::VMVNv2i32); 5182 } else { 5183 Inst.setOpcode(ARM::VMOVv2i32); 5184 } 5185 } 5186 } 5187 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5188 } 5189 5190 if (!(imm & 0x20)) return MCDisassembler::Fail; 5191 5192 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5193 return MCDisassembler::Fail; 5194 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5195 return MCDisassembler::Fail; 5196 Inst.addOperand(MCOperand::createImm(64 - imm)); 5197 5198 return S; 5199 } 5200 5201 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5202 uint64_t Address, const void *Decoder) { 5203 const FeatureBitset &featureBits = 5204 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5205 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5206 5207 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5208 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5209 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5210 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5211 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5212 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5213 unsigned op = fieldFromInstruction(Insn, 5, 1); 5214 5215 DecodeStatus S = MCDisassembler::Success; 5216 5217 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5218 if (!(imm & 0x38)) { 5219 if (cmode == 0xF) { 5220 if (op == 1) return MCDisassembler::Fail; 5221 Inst.setOpcode(ARM::VMOVv4f32); 5222 } 5223 if (hasFullFP16) { 5224 if (cmode == 0xE) { 5225 if (op == 1) { 5226 Inst.setOpcode(ARM::VMOVv2i64); 5227 } else { 5228 Inst.setOpcode(ARM::VMOVv16i8); 5229 } 5230 } 5231 if (cmode == 0xD) { 5232 if (op == 1) { 5233 Inst.setOpcode(ARM::VMVNv4i32); 5234 } else { 5235 Inst.setOpcode(ARM::VMOVv4i32); 5236 } 5237 } 5238 if (cmode == 0xC) { 5239 if (op == 1) { 5240 Inst.setOpcode(ARM::VMVNv4i32); 5241 } else { 5242 Inst.setOpcode(ARM::VMOVv4i32); 5243 } 5244 } 5245 } 5246 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5247 } 5248 5249 if (!(imm & 0x20)) return MCDisassembler::Fail; 5250 5251 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5252 return MCDisassembler::Fail; 5253 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5254 return MCDisassembler::Fail; 5255 Inst.addOperand(MCOperand::createImm(64 - imm)); 5256 5257 return S; 5258 } 5259 5260 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5261 unsigned Insn, 5262 uint64_t Address, 5263 const void *Decoder) { 5264 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5265 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5266 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5267 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5268 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5269 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5270 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5271 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5272 5273 DecodeStatus S = MCDisassembler::Success; 5274 5275 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5276 5277 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5278 return MCDisassembler::Fail; 5279 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5280 return MCDisassembler::Fail; 5281 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5282 return MCDisassembler::Fail; 5283 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5284 return MCDisassembler::Fail; 5285 // The lane index does not have any bits in the encoding, because it can only 5286 // be 0. 5287 Inst.addOperand(MCOperand::createImm(0)); 5288 Inst.addOperand(MCOperand::createImm(rotate)); 5289 5290 return S; 5291 } 5292 5293 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5294 uint64_t Address, const void *Decoder) { 5295 DecodeStatus S = MCDisassembler::Success; 5296 5297 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5298 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5299 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5300 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5301 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5302 5303 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5304 S = MCDisassembler::SoftFail; 5305 5306 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5307 return MCDisassembler::Fail; 5308 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5309 return MCDisassembler::Fail; 5310 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5311 return MCDisassembler::Fail; 5312 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5313 return MCDisassembler::Fail; 5314 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5315 return MCDisassembler::Fail; 5316 5317 return S; 5318 } 5319 5320 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5321 uint64_t Address, const void *Decoder) { 5322 DecodeStatus S = MCDisassembler::Success; 5323 5324 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5325 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5326 unsigned cop = fieldFromInstruction(Val, 8, 4); 5327 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5328 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5329 5330 if ((cop & ~0x1) == 0xa) 5331 return MCDisassembler::Fail; 5332 5333 if (Rt == Rt2) 5334 S = MCDisassembler::SoftFail; 5335 5336 // We have to check if the instruction is MRRC2 5337 // or MCRR2 when constructing the operands for 5338 // Inst. Reason is because MRRC2 stores to two 5339 // registers so it's tablegen desc has has two 5340 // outputs whereas MCRR doesn't store to any 5341 // registers so all of it's operands are listed 5342 // as inputs, therefore the operand order for 5343 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5344 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5345 5346 if (Inst.getOpcode() == ARM::MRRC2) { 5347 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5348 return MCDisassembler::Fail; 5349 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5350 return MCDisassembler::Fail; 5351 } 5352 Inst.addOperand(MCOperand::createImm(cop)); 5353 Inst.addOperand(MCOperand::createImm(opc1)); 5354 if (Inst.getOpcode() == ARM::MCRR2) { 5355 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5356 return MCDisassembler::Fail; 5357 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5358 return MCDisassembler::Fail; 5359 } 5360 Inst.addOperand(MCOperand::createImm(CRm)); 5361 5362 return S; 5363 } 5364 5365 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5366 uint64_t Address, 5367 const void *Decoder) { 5368 const FeatureBitset &featureBits = 5369 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5370 DecodeStatus S = MCDisassembler::Success; 5371 5372 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5373 5374 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5375 if (Rt == 13 || Rt == 15) 5376 S = MCDisassembler::SoftFail; 5377 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5378 } else 5379 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5380 5381 if (featureBits[ARM::ModeThumb]) { 5382 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5383 Inst.addOperand(MCOperand::createReg(0)); 5384 } else { 5385 unsigned pred = fieldFromInstruction(Val, 28, 4); 5386 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5387 return MCDisassembler::Fail; 5388 } 5389 5390 return S; 5391 } 5392