1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Pull DecodeStatus and its enum values into the global namespace. 28 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 29 #define Success llvm::MCDisassembler::Success 30 #define Unpredictable llvm::MCDisassembler::SoftFail 31 #define Fail llvm::MCDisassembler::Fail 32 33 // Helper macro to perform setwise reduction of the current running status 34 // and another status, and return if the new status is Fail. 35 #define CHECK(S,X) do { \ 36 S = (DecodeStatus) ((int)S & (X)); \ 37 if (S == Fail) return Fail; \ 38 } while(0) 39 40 // Forward declare these because the autogenerated code will reference them. 41 // Definitions are further down. 42 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 43 uint64_t Address, const void *Decoder); 44 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 45 unsigned RegNo, uint64_t Address, 46 const void *Decoder); 47 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 50 uint64_t Address, const void *Decoder); 51 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 52 uint64_t Address, const void *Decoder); 53 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 54 uint64_t Address, const void *Decoder); 55 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 56 uint64_t Address, const void *Decoder); 57 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 58 uint64_t Address, const void *Decoder); 59 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 60 unsigned RegNo, 61 uint64_t Address, 62 const void *Decoder); 63 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 64 uint64_t Address, const void *Decoder); 65 66 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 67 uint64_t Address, const void *Decoder); 68 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 69 uint64_t Address, const void *Decoder); 70 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 71 uint64_t Address, const void *Decoder); 72 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 73 uint64_t Address, const void *Decoder); 74 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 75 uint64_t Address, const void *Decoder); 76 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 77 uint64_t Address, const void *Decoder); 78 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 79 uint64_t Address, const void *Decoder); 80 81 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 82 uint64_t Address, const void *Decoder); 83 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 84 uint64_t Address, const void *Decoder); 85 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 86 unsigned Insn, 87 uint64_t Address, 88 const void *Decoder); 89 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 90 uint64_t Address, const void *Decoder); 91 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 92 uint64_t Address, const void *Decoder); 93 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 94 uint64_t Address, const void *Decoder); 95 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 96 uint64_t Address, const void *Decoder); 97 98 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 99 unsigned Insn, 100 uint64_t Adddress, 101 const void *Decoder); 102 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 103 uint64_t Address, const void *Decoder); 104 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 105 uint64_t Address, const void *Decoder); 106 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 113 uint64_t Address, const void *Decoder); 114 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 125 uint64_t Address, const void *Decoder); 126 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 129 uint64_t Address, const void *Decoder); 130 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 147 uint64_t Address, const void *Decoder); 148 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178 179 180 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 225 uint64_t Address, const void *Decoder); 226 227 #include "ARMGenDisassemblerTables.inc" 228 #include "ARMGenInstrInfo.inc" 229 #include "ARMGenEDInfo.inc" 230 231 using namespace llvm; 232 233 static MCDisassembler *createARMDisassembler(const Target &T) { 234 return new ARMDisassembler; 235 } 236 237 static MCDisassembler *createThumbDisassembler(const Target &T) { 238 return new ThumbDisassembler; 239 } 240 241 EDInstInfo *ARMDisassembler::getEDInfo() const { 242 return instInfoARM; 243 } 244 245 EDInstInfo *ThumbDisassembler::getEDInfo() const { 246 return instInfoARM; 247 } 248 249 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 250 const MemoryObject &Region, 251 uint64_t Address, 252 raw_ostream &os) const { 253 uint8_t bytes[4]; 254 255 // We want to read exactly 4 bytes of data. 256 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 257 return Fail; 258 259 // Encoded as a small-endian 32-bit word in the stream. 260 uint32_t insn = (bytes[3] << 24) | 261 (bytes[2] << 16) | 262 (bytes[1] << 8) | 263 (bytes[0] << 0); 264 265 // Calling the auto-generated decoder function. 266 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); 267 if (result != Fail) { 268 Size = 4; 269 return result; 270 } 271 272 // Instructions that are shared between ARM and Thumb modes. 273 // FIXME: This shouldn't really exist. It's an artifact of the 274 // fact that we fail to encode a few instructions properly for Thumb. 275 MI.clear(); 276 result = decodeCommonInstruction32(MI, insn, Address, this); 277 if (result != Fail) { 278 Size = 4; 279 return result; 280 } 281 282 // VFP and NEON instructions, similarly, are shared between ARM 283 // and Thumb modes. 284 MI.clear(); 285 result = decodeVFPInstruction32(MI, insn, Address, this); 286 if (result != Fail) { 287 Size = 4; 288 return result; 289 } 290 291 MI.clear(); 292 result = decodeNEONDataInstruction32(MI, insn, Address, this); 293 if (result != Fail) { 294 Size = 4; 295 // Add a fake predicate operand, because we share these instruction 296 // definitions with Thumb2 where these instructions are predicable. 297 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 298 return result; 299 } 300 301 MI.clear(); 302 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 303 if (result != Fail) { 304 Size = 4; 305 // Add a fake predicate operand, because we share these instruction 306 // definitions with Thumb2 where these instructions are predicable. 307 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 308 return result; 309 } 310 311 MI.clear(); 312 result = decodeNEONDupInstruction32(MI, insn, Address, this); 313 if (result != Fail) { 314 Size = 4; 315 // Add a fake predicate operand, because we share these instruction 316 // definitions with Thumb2 where these instructions are predicable. 317 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 318 return result; 319 } 320 321 MI.clear(); 322 323 return Fail; 324 } 325 326 namespace llvm { 327 extern MCInstrDesc ARMInsts[]; 328 } 329 330 // Thumb1 instructions don't have explicit S bits. Rather, they 331 // implicitly set CPSR. Since it's not represented in the encoding, the 332 // auto-generated decoder won't inject the CPSR operand. We need to fix 333 // that as a post-pass. 334 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 335 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 336 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 337 MCInst::iterator I = MI.begin(); 338 for (unsigned i = 0; i < NumOps; ++i, ++I) { 339 if (I == MI.end()) break; 340 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 341 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 342 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 343 return; 344 } 345 } 346 347 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 348 } 349 350 // Most Thumb instructions don't have explicit predicates in the 351 // encoding, but rather get their predicates from IT context. We need 352 // to fix up the predicate operands using this context information as a 353 // post-pass. 354 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 355 // A few instructions actually have predicates encoded in them. Don't 356 // try to overwrite it if we're seeing one of those. 357 switch (MI.getOpcode()) { 358 case ARM::tBcc: 359 case ARM::t2Bcc: 360 return; 361 default: 362 break; 363 } 364 365 // If we're in an IT block, base the predicate on that. Otherwise, 366 // assume a predicate of AL. 367 unsigned CC; 368 if (!ITBlock.empty()) { 369 CC = ITBlock.back(); 370 ITBlock.pop_back(); 371 } else 372 CC = ARMCC::AL; 373 374 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 375 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 376 MCInst::iterator I = MI.begin(); 377 for (unsigned i = 0; i < NumOps; ++i, ++I) { 378 if (I == MI.end()) break; 379 if (OpInfo[i].isPredicate()) { 380 I = MI.insert(I, MCOperand::CreateImm(CC)); 381 ++I; 382 if (CC == ARMCC::AL) 383 MI.insert(I, MCOperand::CreateReg(0)); 384 else 385 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 386 return; 387 } 388 } 389 390 I = MI.insert(I, MCOperand::CreateImm(CC)); 391 ++I; 392 if (CC == ARMCC::AL) 393 MI.insert(I, MCOperand::CreateReg(0)); 394 else 395 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 396 } 397 398 // Thumb VFP instructions are a special case. Because we share their 399 // encodings between ARM and Thumb modes, and they are predicable in ARM 400 // mode, the auto-generated decoder will give them an (incorrect) 401 // predicate operand. We need to rewrite these operands based on the IT 402 // context as a post-pass. 403 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 404 unsigned CC; 405 if (!ITBlock.empty()) { 406 CC = ITBlock.back(); 407 ITBlock.pop_back(); 408 } else 409 CC = ARMCC::AL; 410 411 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 412 MCInst::iterator I = MI.begin(); 413 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 414 if (OpInfo[i].isPredicate() ) { 415 I->setImm(CC); 416 ++I; 417 if (CC == ARMCC::AL) 418 I->setReg(0); 419 else 420 I->setReg(ARM::CPSR); 421 return; 422 } 423 } 424 } 425 426 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 427 const MemoryObject &Region, 428 uint64_t Address, 429 raw_ostream &os) const { 430 uint8_t bytes[4]; 431 432 // We want to read exactly 2 bytes of data. 433 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 434 return Fail; 435 436 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 437 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); 438 if (result != Fail) { 439 Size = 2; 440 AddThumbPredicate(MI); 441 return result; 442 } 443 444 MI.clear(); 445 result = decodeThumbSBitInstruction16(MI, insn16, Address, this); 446 if (result) { 447 Size = 2; 448 bool InITBlock = !ITBlock.empty(); 449 AddThumbPredicate(MI); 450 AddThumb1SBit(MI, InITBlock); 451 return result; 452 } 453 454 MI.clear(); 455 result = decodeThumb2Instruction16(MI, insn16, Address, this); 456 if (result != Fail) { 457 Size = 2; 458 AddThumbPredicate(MI); 459 460 // If we find an IT instruction, we need to parse its condition 461 // code and mask operands so that we can apply them correctly 462 // to the subsequent instructions. 463 if (MI.getOpcode() == ARM::t2IT) { 464 unsigned firstcond = MI.getOperand(0).getImm(); 465 uint32_t mask = MI.getOperand(1).getImm(); 466 unsigned zeros = CountTrailingZeros_32(mask); 467 mask >>= zeros+1; 468 469 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 470 if (firstcond ^ (mask & 1)) 471 ITBlock.push_back(firstcond ^ 1); 472 else 473 ITBlock.push_back(firstcond); 474 mask >>= 1; 475 } 476 ITBlock.push_back(firstcond); 477 } 478 479 return result; 480 } 481 482 // We want to read exactly 4 bytes of data. 483 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 484 return Fail; 485 486 uint32_t insn32 = (bytes[3] << 8) | 487 (bytes[2] << 0) | 488 (bytes[1] << 24) | 489 (bytes[0] << 16); 490 MI.clear(); 491 result = decodeThumbInstruction32(MI, insn32, Address, this); 492 if (result != Fail) { 493 Size = 4; 494 bool InITBlock = ITBlock.size(); 495 AddThumbPredicate(MI); 496 AddThumb1SBit(MI, InITBlock); 497 return result; 498 } 499 500 MI.clear(); 501 result = decodeThumb2Instruction32(MI, insn32, Address, this); 502 if (result != Fail) { 503 Size = 4; 504 AddThumbPredicate(MI); 505 return result; 506 } 507 508 MI.clear(); 509 result = decodeCommonInstruction32(MI, insn32, Address, this); 510 if (result != Fail) { 511 Size = 4; 512 AddThumbPredicate(MI); 513 return result; 514 } 515 516 MI.clear(); 517 result = decodeVFPInstruction32(MI, insn32, Address, this); 518 if (result != Fail) { 519 Size = 4; 520 UpdateThumbVFPPredicate(MI); 521 return result; 522 } 523 524 MI.clear(); 525 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 526 if (result != Fail) { 527 Size = 4; 528 AddThumbPredicate(MI); 529 return result; 530 } 531 532 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 533 MI.clear(); 534 uint32_t NEONLdStInsn = insn32; 535 NEONLdStInsn &= 0xF0FFFFFF; 536 NEONLdStInsn |= 0x04000000; 537 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 538 if (result != Fail) { 539 Size = 4; 540 AddThumbPredicate(MI); 541 return result; 542 } 543 } 544 545 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 546 MI.clear(); 547 uint32_t NEONDataInsn = insn32; 548 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 549 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 550 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 551 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 552 if (result != Fail) { 553 Size = 4; 554 AddThumbPredicate(MI); 555 return result; 556 } 557 } 558 559 return Fail; 560 } 561 562 563 extern "C" void LLVMInitializeARMDisassembler() { 564 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 565 createARMDisassembler); 566 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 567 createThumbDisassembler); 568 } 569 570 static const unsigned GPRDecoderTable[] = { 571 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 572 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 573 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 574 ARM::R12, ARM::SP, ARM::LR, ARM::PC 575 }; 576 577 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 578 uint64_t Address, const void *Decoder) { 579 if (RegNo > 15) 580 return Fail; 581 582 unsigned Register = GPRDecoderTable[RegNo]; 583 Inst.addOperand(MCOperand::CreateReg(Register)); 584 return Success; 585 } 586 587 static DecodeStatus 588 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 589 uint64_t Address, const void *Decoder) { 590 if (RegNo == 15) return Fail; 591 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 592 } 593 594 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 595 uint64_t Address, const void *Decoder) { 596 if (RegNo > 7) 597 return Fail; 598 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 599 } 600 601 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 602 uint64_t Address, const void *Decoder) { 603 unsigned Register = 0; 604 switch (RegNo) { 605 case 0: 606 Register = ARM::R0; 607 break; 608 case 1: 609 Register = ARM::R1; 610 break; 611 case 2: 612 Register = ARM::R2; 613 break; 614 case 3: 615 Register = ARM::R3; 616 break; 617 case 9: 618 Register = ARM::R9; 619 break; 620 case 12: 621 Register = ARM::R12; 622 break; 623 default: 624 return Fail; 625 } 626 627 Inst.addOperand(MCOperand::CreateReg(Register)); 628 return Success; 629 } 630 631 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 632 uint64_t Address, const void *Decoder) { 633 if (RegNo == 13 || RegNo == 15) return Fail; 634 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 635 } 636 637 static const unsigned SPRDecoderTable[] = { 638 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 639 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 640 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 641 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 642 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 643 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 644 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 645 ARM::S28, ARM::S29, ARM::S30, ARM::S31 646 }; 647 648 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 649 uint64_t Address, const void *Decoder) { 650 if (RegNo > 31) 651 return Fail; 652 653 unsigned Register = SPRDecoderTable[RegNo]; 654 Inst.addOperand(MCOperand::CreateReg(Register)); 655 return Success; 656 } 657 658 static const unsigned DPRDecoderTable[] = { 659 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 660 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 661 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 662 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 663 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 664 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 665 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 666 ARM::D28, ARM::D29, ARM::D30, ARM::D31 667 }; 668 669 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 670 uint64_t Address, const void *Decoder) { 671 if (RegNo > 31) 672 return Fail; 673 674 unsigned Register = DPRDecoderTable[RegNo]; 675 Inst.addOperand(MCOperand::CreateReg(Register)); 676 return Success; 677 } 678 679 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 680 uint64_t Address, const void *Decoder) { 681 if (RegNo > 7) 682 return Fail; 683 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 684 } 685 686 static DecodeStatus 687 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 688 uint64_t Address, const void *Decoder) { 689 if (RegNo > 15) 690 return Fail; 691 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 692 } 693 694 static const unsigned QPRDecoderTable[] = { 695 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 696 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 697 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 698 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 699 }; 700 701 702 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 703 uint64_t Address, const void *Decoder) { 704 if (RegNo > 31) 705 return Fail; 706 RegNo >>= 1; 707 708 unsigned Register = QPRDecoderTable[RegNo]; 709 Inst.addOperand(MCOperand::CreateReg(Register)); 710 return Success; 711 } 712 713 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 714 uint64_t Address, const void *Decoder) { 715 if (Val == 0xF) return Fail; 716 // AL predicate is not allowed on Thumb1 branches. 717 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 718 return Fail; 719 Inst.addOperand(MCOperand::CreateImm(Val)); 720 if (Val == ARMCC::AL) { 721 Inst.addOperand(MCOperand::CreateReg(0)); 722 } else 723 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 724 return Success; 725 } 726 727 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 728 uint64_t Address, const void *Decoder) { 729 if (Val) 730 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 731 else 732 Inst.addOperand(MCOperand::CreateReg(0)); 733 return Success; 734 } 735 736 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 737 uint64_t Address, const void *Decoder) { 738 uint32_t imm = Val & 0xFF; 739 uint32_t rot = (Val & 0xF00) >> 7; 740 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 741 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 742 return Success; 743 } 744 745 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 746 uint64_t Address, const void *Decoder) { 747 Val <<= 2; 748 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 749 return Success; 750 } 751 752 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 753 uint64_t Address, const void *Decoder) { 754 DecodeStatus S = Success; 755 756 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 757 unsigned type = fieldFromInstruction32(Val, 5, 2); 758 unsigned imm = fieldFromInstruction32(Val, 7, 5); 759 760 // Register-immediate 761 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 762 763 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 764 switch (type) { 765 case 0: 766 Shift = ARM_AM::lsl; 767 break; 768 case 1: 769 Shift = ARM_AM::lsr; 770 break; 771 case 2: 772 Shift = ARM_AM::asr; 773 break; 774 case 3: 775 Shift = ARM_AM::ror; 776 break; 777 } 778 779 if (Shift == ARM_AM::ror && imm == 0) 780 Shift = ARM_AM::rrx; 781 782 unsigned Op = Shift | (imm << 3); 783 Inst.addOperand(MCOperand::CreateImm(Op)); 784 785 return S; 786 } 787 788 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 789 uint64_t Address, const void *Decoder) { 790 DecodeStatus S = Success; 791 792 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 793 unsigned type = fieldFromInstruction32(Val, 5, 2); 794 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 795 796 // Register-register 797 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 798 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); 799 800 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 801 switch (type) { 802 case 0: 803 Shift = ARM_AM::lsl; 804 break; 805 case 1: 806 Shift = ARM_AM::lsr; 807 break; 808 case 2: 809 Shift = ARM_AM::asr; 810 break; 811 case 3: 812 Shift = ARM_AM::ror; 813 break; 814 } 815 816 Inst.addOperand(MCOperand::CreateImm(Shift)); 817 818 return S; 819 } 820 821 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 822 uint64_t Address, const void *Decoder) { 823 DecodeStatus S = Success; 824 825 // Empty register lists are not allowed. 826 if (CountPopulation_32(Val) == 0) return Fail; 827 for (unsigned i = 0; i < 16; ++i) { 828 if (Val & (1 << i)) { 829 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); 830 } 831 } 832 833 return S; 834 } 835 836 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 837 uint64_t Address, const void *Decoder) { 838 DecodeStatus S = Success; 839 840 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 841 unsigned regs = Val & 0xFF; 842 843 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); 844 for (unsigned i = 0; i < (regs - 1); ++i) { 845 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); 846 } 847 848 return S; 849 } 850 851 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 852 uint64_t Address, const void *Decoder) { 853 DecodeStatus S = Success; 854 855 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 856 unsigned regs = (Val & 0xFF) / 2; 857 858 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); 859 for (unsigned i = 0; i < (regs - 1); ++i) { 860 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); 861 } 862 863 return S; 864 } 865 866 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 867 uint64_t Address, const void *Decoder) { 868 // This operand encodes a mask of contiguous zeros between a specified MSB 869 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 870 // the mask of all bits LSB-and-lower, and then xor them to create 871 // the mask of that's all ones on [msb, lsb]. Finally we not it to 872 // create the final mask. 873 unsigned msb = fieldFromInstruction32(Val, 5, 5); 874 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 875 uint32_t msb_mask = (1 << (msb+1)) - 1; 876 uint32_t lsb_mask = (1 << lsb) - 1; 877 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 878 return Success; 879 } 880 881 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 882 uint64_t Address, const void *Decoder) { 883 DecodeStatus S = Success; 884 885 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 886 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 887 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 888 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 889 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 890 unsigned U = fieldFromInstruction32(Insn, 23, 1); 891 892 switch (Inst.getOpcode()) { 893 case ARM::LDC_OFFSET: 894 case ARM::LDC_PRE: 895 case ARM::LDC_POST: 896 case ARM::LDC_OPTION: 897 case ARM::LDCL_OFFSET: 898 case ARM::LDCL_PRE: 899 case ARM::LDCL_POST: 900 case ARM::LDCL_OPTION: 901 case ARM::STC_OFFSET: 902 case ARM::STC_PRE: 903 case ARM::STC_POST: 904 case ARM::STC_OPTION: 905 case ARM::STCL_OFFSET: 906 case ARM::STCL_PRE: 907 case ARM::STCL_POST: 908 case ARM::STCL_OPTION: 909 if (coproc == 0xA || coproc == 0xB) 910 return Fail; 911 break; 912 default: 913 break; 914 } 915 916 Inst.addOperand(MCOperand::CreateImm(coproc)); 917 Inst.addOperand(MCOperand::CreateImm(CRd)); 918 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 919 switch (Inst.getOpcode()) { 920 case ARM::LDC_OPTION: 921 case ARM::LDCL_OPTION: 922 case ARM::LDC2_OPTION: 923 case ARM::LDC2L_OPTION: 924 case ARM::STC_OPTION: 925 case ARM::STCL_OPTION: 926 case ARM::STC2_OPTION: 927 case ARM::STC2L_OPTION: 928 case ARM::LDCL_POST: 929 case ARM::STCL_POST: 930 break; 931 default: 932 Inst.addOperand(MCOperand::CreateReg(0)); 933 break; 934 } 935 936 unsigned P = fieldFromInstruction32(Insn, 24, 1); 937 unsigned W = fieldFromInstruction32(Insn, 21, 1); 938 939 bool writeback = (P == 0) || (W == 1); 940 unsigned idx_mode = 0; 941 if (P && writeback) 942 idx_mode = ARMII::IndexModePre; 943 else if (!P && writeback) 944 idx_mode = ARMII::IndexModePost; 945 946 switch (Inst.getOpcode()) { 947 case ARM::LDCL_POST: 948 case ARM::STCL_POST: 949 imm |= U << 8; 950 case ARM::LDC_OPTION: 951 case ARM::LDCL_OPTION: 952 case ARM::LDC2_OPTION: 953 case ARM::LDC2L_OPTION: 954 case ARM::STC_OPTION: 955 case ARM::STCL_OPTION: 956 case ARM::STC2_OPTION: 957 case ARM::STC2L_OPTION: 958 Inst.addOperand(MCOperand::CreateImm(imm)); 959 break; 960 default: 961 if (U) 962 Inst.addOperand(MCOperand::CreateImm( 963 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 964 else 965 Inst.addOperand(MCOperand::CreateImm( 966 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 967 break; 968 } 969 970 switch (Inst.getOpcode()) { 971 case ARM::LDC_OFFSET: 972 case ARM::LDC_PRE: 973 case ARM::LDC_POST: 974 case ARM::LDC_OPTION: 975 case ARM::LDCL_OFFSET: 976 case ARM::LDCL_PRE: 977 case ARM::LDCL_POST: 978 case ARM::LDCL_OPTION: 979 case ARM::STC_OFFSET: 980 case ARM::STC_PRE: 981 case ARM::STC_POST: 982 case ARM::STC_OPTION: 983 case ARM::STCL_OFFSET: 984 case ARM::STCL_PRE: 985 case ARM::STCL_POST: 986 case ARM::STCL_OPTION: 987 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 988 break; 989 default: 990 break; 991 } 992 993 return S; 994 } 995 996 static DecodeStatus 997 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 998 uint64_t Address, const void *Decoder) { 999 DecodeStatus S = Success; 1000 1001 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1002 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1003 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1004 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1005 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1006 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1007 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1008 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1009 1010 // On stores, the writeback operand precedes Rt. 1011 switch (Inst.getOpcode()) { 1012 case ARM::STR_POST_IMM: 1013 case ARM::STR_POST_REG: 1014 case ARM::STRB_POST_IMM: 1015 case ARM::STRB_POST_REG: 1016 case ARM::STRT_POST_REG: 1017 case ARM::STRT_POST_IMM: 1018 case ARM::STRBT_POST_REG: 1019 case ARM::STRBT_POST_IMM: 1020 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1021 break; 1022 default: 1023 break; 1024 } 1025 1026 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1027 1028 // On loads, the writeback operand comes after Rt. 1029 switch (Inst.getOpcode()) { 1030 case ARM::LDR_POST_IMM: 1031 case ARM::LDR_POST_REG: 1032 case ARM::LDRB_POST_IMM: 1033 case ARM::LDRB_POST_REG: 1034 case ARM::LDR_PRE: 1035 case ARM::LDRB_PRE: 1036 case ARM::LDRBT_POST_REG: 1037 case ARM::LDRBT_POST_IMM: 1038 case ARM::LDRT_POST_REG: 1039 case ARM::LDRT_POST_IMM: 1040 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1041 break; 1042 default: 1043 break; 1044 } 1045 1046 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1047 1048 ARM_AM::AddrOpc Op = ARM_AM::add; 1049 if (!fieldFromInstruction32(Insn, 23, 1)) 1050 Op = ARM_AM::sub; 1051 1052 bool writeback = (P == 0) || (W == 1); 1053 unsigned idx_mode = 0; 1054 if (P && writeback) 1055 idx_mode = ARMII::IndexModePre; 1056 else if (!P && writeback) 1057 idx_mode = ARMII::IndexModePost; 1058 1059 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE 1060 1061 if (reg) { 1062 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1063 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1064 switch( fieldFromInstruction32(Insn, 5, 2)) { 1065 case 0: 1066 Opc = ARM_AM::lsl; 1067 break; 1068 case 1: 1069 Opc = ARM_AM::lsr; 1070 break; 1071 case 2: 1072 Opc = ARM_AM::asr; 1073 break; 1074 case 3: 1075 Opc = ARM_AM::ror; 1076 break; 1077 default: 1078 return Fail; 1079 } 1080 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1081 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1082 1083 Inst.addOperand(MCOperand::CreateImm(imm)); 1084 } else { 1085 Inst.addOperand(MCOperand::CreateReg(0)); 1086 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1087 Inst.addOperand(MCOperand::CreateImm(tmp)); 1088 } 1089 1090 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1091 1092 return S; 1093 } 1094 1095 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1096 uint64_t Address, const void *Decoder) { 1097 DecodeStatus S = Success; 1098 1099 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1100 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1101 unsigned type = fieldFromInstruction32(Val, 5, 2); 1102 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1103 unsigned U = fieldFromInstruction32(Val, 12, 1); 1104 1105 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1106 switch (type) { 1107 case 0: 1108 ShOp = ARM_AM::lsl; 1109 break; 1110 case 1: 1111 ShOp = ARM_AM::lsr; 1112 break; 1113 case 2: 1114 ShOp = ARM_AM::asr; 1115 break; 1116 case 3: 1117 ShOp = ARM_AM::ror; 1118 break; 1119 } 1120 1121 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1122 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1123 unsigned shift; 1124 if (U) 1125 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1126 else 1127 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1128 Inst.addOperand(MCOperand::CreateImm(shift)); 1129 1130 return S; 1131 } 1132 1133 static DecodeStatus 1134 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1135 uint64_t Address, const void *Decoder) { 1136 DecodeStatus S = Success; 1137 1138 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1139 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1140 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1141 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1142 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1143 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1144 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1145 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1146 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1147 1148 bool writeback = (W == 1) | (P == 0); 1149 1150 // For {LD,ST}RD, Rt must be even, else undefined. 1151 switch (Inst.getOpcode()) { 1152 case ARM::STRD: 1153 case ARM::STRD_PRE: 1154 case ARM::STRD_POST: 1155 case ARM::LDRD: 1156 case ARM::LDRD_PRE: 1157 case ARM::LDRD_POST: 1158 if (Rt & 0x1) return Fail; 1159 break; 1160 default: 1161 break; 1162 } 1163 1164 if (writeback) { // Writeback 1165 if (P) 1166 U |= ARMII::IndexModePre << 9; 1167 else 1168 U |= ARMII::IndexModePost << 9; 1169 1170 // On stores, the writeback operand precedes Rt. 1171 switch (Inst.getOpcode()) { 1172 case ARM::STRD: 1173 case ARM::STRD_PRE: 1174 case ARM::STRD_POST: 1175 case ARM::STRH: 1176 case ARM::STRH_PRE: 1177 case ARM::STRH_POST: 1178 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1179 break; 1180 default: 1181 break; 1182 } 1183 } 1184 1185 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1186 switch (Inst.getOpcode()) { 1187 case ARM::STRD: 1188 case ARM::STRD_PRE: 1189 case ARM::STRD_POST: 1190 case ARM::LDRD: 1191 case ARM::LDRD_PRE: 1192 case ARM::LDRD_POST: 1193 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 1194 break; 1195 default: 1196 break; 1197 } 1198 1199 if (writeback) { 1200 // On loads, the writeback operand comes after Rt. 1201 switch (Inst.getOpcode()) { 1202 case ARM::LDRD: 1203 case ARM::LDRD_PRE: 1204 case ARM::LDRD_POST: 1205 case ARM::LDRH: 1206 case ARM::LDRH_PRE: 1207 case ARM::LDRH_POST: 1208 case ARM::LDRSH: 1209 case ARM::LDRSH_PRE: 1210 case ARM::LDRSH_POST: 1211 case ARM::LDRSB: 1212 case ARM::LDRSB_PRE: 1213 case ARM::LDRSB_POST: 1214 case ARM::LDRHTr: 1215 case ARM::LDRSBTr: 1216 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1217 break; 1218 default: 1219 break; 1220 } 1221 } 1222 1223 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1224 1225 if (type) { 1226 Inst.addOperand(MCOperand::CreateReg(0)); 1227 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1228 } else { 1229 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1230 Inst.addOperand(MCOperand::CreateImm(U)); 1231 } 1232 1233 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1234 1235 return S; 1236 } 1237 1238 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1239 uint64_t Address, const void *Decoder) { 1240 DecodeStatus S = Success; 1241 1242 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1243 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1244 1245 switch (mode) { 1246 case 0: 1247 mode = ARM_AM::da; 1248 break; 1249 case 1: 1250 mode = ARM_AM::ia; 1251 break; 1252 case 2: 1253 mode = ARM_AM::db; 1254 break; 1255 case 3: 1256 mode = ARM_AM::ib; 1257 break; 1258 } 1259 1260 Inst.addOperand(MCOperand::CreateImm(mode)); 1261 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1262 1263 return S; 1264 } 1265 1266 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1267 unsigned Insn, 1268 uint64_t Address, const void *Decoder) { 1269 DecodeStatus S = Success; 1270 1271 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1272 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1273 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1274 1275 if (pred == 0xF) { 1276 switch (Inst.getOpcode()) { 1277 case ARM::STMDA: 1278 Inst.setOpcode(ARM::RFEDA); 1279 break; 1280 case ARM::STMDA_UPD: 1281 Inst.setOpcode(ARM::RFEDA_UPD); 1282 break; 1283 case ARM::STMDB: 1284 Inst.setOpcode(ARM::RFEDB); 1285 break; 1286 case ARM::STMDB_UPD: 1287 Inst.setOpcode(ARM::RFEDB_UPD); 1288 break; 1289 case ARM::STMIA: 1290 Inst.setOpcode(ARM::RFEIA); 1291 break; 1292 case ARM::STMIA_UPD: 1293 Inst.setOpcode(ARM::RFEIA_UPD); 1294 break; 1295 case ARM::STMIB: 1296 Inst.setOpcode(ARM::RFEIB); 1297 break; 1298 case ARM::STMIB_UPD: 1299 Inst.setOpcode(ARM::RFEIB_UPD); 1300 break; 1301 } 1302 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1303 } 1304 1305 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1306 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied 1307 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1308 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); 1309 1310 return S; 1311 } 1312 1313 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1314 uint64_t Address, const void *Decoder) { 1315 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1316 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1317 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1318 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1319 1320 DecodeStatus S = Success; 1321 1322 // imod == '01' --> UNPREDICTABLE 1323 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1324 // return failure here. The '01' imod value is unprintable, so there's 1325 // nothing useful we could do even if we returned UNPREDICTABLE. 1326 1327 if (imod == 1) CHECK(S, Fail); 1328 1329 if (imod && M) { 1330 Inst.setOpcode(ARM::CPS3p); 1331 Inst.addOperand(MCOperand::CreateImm(imod)); 1332 Inst.addOperand(MCOperand::CreateImm(iflags)); 1333 Inst.addOperand(MCOperand::CreateImm(mode)); 1334 } else if (imod && !M) { 1335 Inst.setOpcode(ARM::CPS2p); 1336 Inst.addOperand(MCOperand::CreateImm(imod)); 1337 Inst.addOperand(MCOperand::CreateImm(iflags)); 1338 if (mode) CHECK(S, Unpredictable); 1339 } else if (!imod && M) { 1340 Inst.setOpcode(ARM::CPS1p); 1341 Inst.addOperand(MCOperand::CreateImm(mode)); 1342 if (iflags) CHECK(S, Unpredictable); 1343 } else 1344 // imod == '00' && M == '0' --> UNPREDICTABLE 1345 CHECK(S, Unpredictable); 1346 1347 return S; 1348 } 1349 1350 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1351 uint64_t Address, const void *Decoder) { 1352 DecodeStatus S = Success; 1353 1354 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1355 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1356 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1357 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1358 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1359 1360 if (pred == 0xF) 1361 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1362 1363 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); 1364 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); 1365 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1366 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); 1367 1368 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1369 1370 return S; 1371 } 1372 1373 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1374 uint64_t Address, const void *Decoder) { 1375 DecodeStatus S = Success; 1376 1377 unsigned add = fieldFromInstruction32(Val, 12, 1); 1378 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1379 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1380 1381 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1382 1383 if (!add) imm *= -1; 1384 if (imm == 0 && !add) imm = INT32_MIN; 1385 Inst.addOperand(MCOperand::CreateImm(imm)); 1386 1387 return S; 1388 } 1389 1390 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1391 uint64_t Address, const void *Decoder) { 1392 DecodeStatus S = Success; 1393 1394 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1395 unsigned U = fieldFromInstruction32(Val, 8, 1); 1396 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1397 1398 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1399 1400 if (U) 1401 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1402 else 1403 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1404 1405 return S; 1406 } 1407 1408 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1409 uint64_t Address, const void *Decoder) { 1410 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1411 } 1412 1413 static DecodeStatus 1414 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1415 uint64_t Address, const void *Decoder) { 1416 DecodeStatus S = Success; 1417 1418 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1419 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1420 1421 if (pred == 0xF) { 1422 Inst.setOpcode(ARM::BLXi); 1423 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1424 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1425 return S; 1426 } 1427 1428 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1429 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1430 1431 return S; 1432 } 1433 1434 1435 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1436 uint64_t Address, const void *Decoder) { 1437 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1438 return Success; 1439 } 1440 1441 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1442 uint64_t Address, const void *Decoder) { 1443 DecodeStatus S = Success; 1444 1445 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1446 unsigned align = fieldFromInstruction32(Val, 4, 2); 1447 1448 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1449 if (!align) 1450 Inst.addOperand(MCOperand::CreateImm(0)); 1451 else 1452 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1453 1454 return S; 1455 } 1456 1457 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1458 uint64_t Address, const void *Decoder) { 1459 DecodeStatus S = Success; 1460 1461 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1462 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1463 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1464 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1465 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1466 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1467 1468 // First output register 1469 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1470 1471 // Second output register 1472 switch (Inst.getOpcode()) { 1473 case ARM::VLD1q8: 1474 case ARM::VLD1q16: 1475 case ARM::VLD1q32: 1476 case ARM::VLD1q64: 1477 case ARM::VLD1q8_UPD: 1478 case ARM::VLD1q16_UPD: 1479 case ARM::VLD1q32_UPD: 1480 case ARM::VLD1q64_UPD: 1481 case ARM::VLD1d8T: 1482 case ARM::VLD1d16T: 1483 case ARM::VLD1d32T: 1484 case ARM::VLD1d64T: 1485 case ARM::VLD1d8T_UPD: 1486 case ARM::VLD1d16T_UPD: 1487 case ARM::VLD1d32T_UPD: 1488 case ARM::VLD1d64T_UPD: 1489 case ARM::VLD1d8Q: 1490 case ARM::VLD1d16Q: 1491 case ARM::VLD1d32Q: 1492 case ARM::VLD1d64Q: 1493 case ARM::VLD1d8Q_UPD: 1494 case ARM::VLD1d16Q_UPD: 1495 case ARM::VLD1d32Q_UPD: 1496 case ARM::VLD1d64Q_UPD: 1497 case ARM::VLD2d8: 1498 case ARM::VLD2d16: 1499 case ARM::VLD2d32: 1500 case ARM::VLD2d8_UPD: 1501 case ARM::VLD2d16_UPD: 1502 case ARM::VLD2d32_UPD: 1503 case ARM::VLD2q8: 1504 case ARM::VLD2q16: 1505 case ARM::VLD2q32: 1506 case ARM::VLD2q8_UPD: 1507 case ARM::VLD2q16_UPD: 1508 case ARM::VLD2q32_UPD: 1509 case ARM::VLD3d8: 1510 case ARM::VLD3d16: 1511 case ARM::VLD3d32: 1512 case ARM::VLD3d8_UPD: 1513 case ARM::VLD3d16_UPD: 1514 case ARM::VLD3d32_UPD: 1515 case ARM::VLD4d8: 1516 case ARM::VLD4d16: 1517 case ARM::VLD4d32: 1518 case ARM::VLD4d8_UPD: 1519 case ARM::VLD4d16_UPD: 1520 case ARM::VLD4d32_UPD: 1521 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1522 break; 1523 case ARM::VLD2b8: 1524 case ARM::VLD2b16: 1525 case ARM::VLD2b32: 1526 case ARM::VLD2b8_UPD: 1527 case ARM::VLD2b16_UPD: 1528 case ARM::VLD2b32_UPD: 1529 case ARM::VLD3q8: 1530 case ARM::VLD3q16: 1531 case ARM::VLD3q32: 1532 case ARM::VLD3q8_UPD: 1533 case ARM::VLD3q16_UPD: 1534 case ARM::VLD3q32_UPD: 1535 case ARM::VLD4q8: 1536 case ARM::VLD4q16: 1537 case ARM::VLD4q32: 1538 case ARM::VLD4q8_UPD: 1539 case ARM::VLD4q16_UPD: 1540 case ARM::VLD4q32_UPD: 1541 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1542 default: 1543 break; 1544 } 1545 1546 // Third output register 1547 switch(Inst.getOpcode()) { 1548 case ARM::VLD1d8T: 1549 case ARM::VLD1d16T: 1550 case ARM::VLD1d32T: 1551 case ARM::VLD1d64T: 1552 case ARM::VLD1d8T_UPD: 1553 case ARM::VLD1d16T_UPD: 1554 case ARM::VLD1d32T_UPD: 1555 case ARM::VLD1d64T_UPD: 1556 case ARM::VLD1d8Q: 1557 case ARM::VLD1d16Q: 1558 case ARM::VLD1d32Q: 1559 case ARM::VLD1d64Q: 1560 case ARM::VLD1d8Q_UPD: 1561 case ARM::VLD1d16Q_UPD: 1562 case ARM::VLD1d32Q_UPD: 1563 case ARM::VLD1d64Q_UPD: 1564 case ARM::VLD2q8: 1565 case ARM::VLD2q16: 1566 case ARM::VLD2q32: 1567 case ARM::VLD2q8_UPD: 1568 case ARM::VLD2q16_UPD: 1569 case ARM::VLD2q32_UPD: 1570 case ARM::VLD3d8: 1571 case ARM::VLD3d16: 1572 case ARM::VLD3d32: 1573 case ARM::VLD3d8_UPD: 1574 case ARM::VLD3d16_UPD: 1575 case ARM::VLD3d32_UPD: 1576 case ARM::VLD4d8: 1577 case ARM::VLD4d16: 1578 case ARM::VLD4d32: 1579 case ARM::VLD4d8_UPD: 1580 case ARM::VLD4d16_UPD: 1581 case ARM::VLD4d32_UPD: 1582 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1583 break; 1584 case ARM::VLD3q8: 1585 case ARM::VLD3q16: 1586 case ARM::VLD3q32: 1587 case ARM::VLD3q8_UPD: 1588 case ARM::VLD3q16_UPD: 1589 case ARM::VLD3q32_UPD: 1590 case ARM::VLD4q8: 1591 case ARM::VLD4q16: 1592 case ARM::VLD4q32: 1593 case ARM::VLD4q8_UPD: 1594 case ARM::VLD4q16_UPD: 1595 case ARM::VLD4q32_UPD: 1596 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1597 break; 1598 default: 1599 break; 1600 } 1601 1602 // Fourth output register 1603 switch (Inst.getOpcode()) { 1604 case ARM::VLD1d8Q: 1605 case ARM::VLD1d16Q: 1606 case ARM::VLD1d32Q: 1607 case ARM::VLD1d64Q: 1608 case ARM::VLD1d8Q_UPD: 1609 case ARM::VLD1d16Q_UPD: 1610 case ARM::VLD1d32Q_UPD: 1611 case ARM::VLD1d64Q_UPD: 1612 case ARM::VLD2q8: 1613 case ARM::VLD2q16: 1614 case ARM::VLD2q32: 1615 case ARM::VLD2q8_UPD: 1616 case ARM::VLD2q16_UPD: 1617 case ARM::VLD2q32_UPD: 1618 case ARM::VLD4d8: 1619 case ARM::VLD4d16: 1620 case ARM::VLD4d32: 1621 case ARM::VLD4d8_UPD: 1622 case ARM::VLD4d16_UPD: 1623 case ARM::VLD4d32_UPD: 1624 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1625 break; 1626 case ARM::VLD4q8: 1627 case ARM::VLD4q16: 1628 case ARM::VLD4q32: 1629 case ARM::VLD4q8_UPD: 1630 case ARM::VLD4q16_UPD: 1631 case ARM::VLD4q32_UPD: 1632 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1633 break; 1634 default: 1635 break; 1636 } 1637 1638 // Writeback operand 1639 switch (Inst.getOpcode()) { 1640 case ARM::VLD1d8_UPD: 1641 case ARM::VLD1d16_UPD: 1642 case ARM::VLD1d32_UPD: 1643 case ARM::VLD1d64_UPD: 1644 case ARM::VLD1q8_UPD: 1645 case ARM::VLD1q16_UPD: 1646 case ARM::VLD1q32_UPD: 1647 case ARM::VLD1q64_UPD: 1648 case ARM::VLD1d8T_UPD: 1649 case ARM::VLD1d16T_UPD: 1650 case ARM::VLD1d32T_UPD: 1651 case ARM::VLD1d64T_UPD: 1652 case ARM::VLD1d8Q_UPD: 1653 case ARM::VLD1d16Q_UPD: 1654 case ARM::VLD1d32Q_UPD: 1655 case ARM::VLD1d64Q_UPD: 1656 case ARM::VLD2d8_UPD: 1657 case ARM::VLD2d16_UPD: 1658 case ARM::VLD2d32_UPD: 1659 case ARM::VLD2q8_UPD: 1660 case ARM::VLD2q16_UPD: 1661 case ARM::VLD2q32_UPD: 1662 case ARM::VLD2b8_UPD: 1663 case ARM::VLD2b16_UPD: 1664 case ARM::VLD2b32_UPD: 1665 case ARM::VLD3d8_UPD: 1666 case ARM::VLD3d16_UPD: 1667 case ARM::VLD3d32_UPD: 1668 case ARM::VLD3q8_UPD: 1669 case ARM::VLD3q16_UPD: 1670 case ARM::VLD3q32_UPD: 1671 case ARM::VLD4d8_UPD: 1672 case ARM::VLD4d16_UPD: 1673 case ARM::VLD4d32_UPD: 1674 case ARM::VLD4q8_UPD: 1675 case ARM::VLD4q16_UPD: 1676 case ARM::VLD4q32_UPD: 1677 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1678 break; 1679 default: 1680 break; 1681 } 1682 1683 // AddrMode6 Base (register+alignment) 1684 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1685 1686 // AddrMode6 Offset (register) 1687 if (Rm == 0xD) 1688 Inst.addOperand(MCOperand::CreateReg(0)); 1689 else if (Rm != 0xF) { 1690 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1691 } 1692 1693 return S; 1694 } 1695 1696 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1697 uint64_t Address, const void *Decoder) { 1698 DecodeStatus S = Success; 1699 1700 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1701 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1702 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1703 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1704 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1705 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1706 1707 // Writeback Operand 1708 switch (Inst.getOpcode()) { 1709 case ARM::VST1d8_UPD: 1710 case ARM::VST1d16_UPD: 1711 case ARM::VST1d32_UPD: 1712 case ARM::VST1d64_UPD: 1713 case ARM::VST1q8_UPD: 1714 case ARM::VST1q16_UPD: 1715 case ARM::VST1q32_UPD: 1716 case ARM::VST1q64_UPD: 1717 case ARM::VST1d8T_UPD: 1718 case ARM::VST1d16T_UPD: 1719 case ARM::VST1d32T_UPD: 1720 case ARM::VST1d64T_UPD: 1721 case ARM::VST1d8Q_UPD: 1722 case ARM::VST1d16Q_UPD: 1723 case ARM::VST1d32Q_UPD: 1724 case ARM::VST1d64Q_UPD: 1725 case ARM::VST2d8_UPD: 1726 case ARM::VST2d16_UPD: 1727 case ARM::VST2d32_UPD: 1728 case ARM::VST2q8_UPD: 1729 case ARM::VST2q16_UPD: 1730 case ARM::VST2q32_UPD: 1731 case ARM::VST2b8_UPD: 1732 case ARM::VST2b16_UPD: 1733 case ARM::VST2b32_UPD: 1734 case ARM::VST3d8_UPD: 1735 case ARM::VST3d16_UPD: 1736 case ARM::VST3d32_UPD: 1737 case ARM::VST3q8_UPD: 1738 case ARM::VST3q16_UPD: 1739 case ARM::VST3q32_UPD: 1740 case ARM::VST4d8_UPD: 1741 case ARM::VST4d16_UPD: 1742 case ARM::VST4d32_UPD: 1743 case ARM::VST4q8_UPD: 1744 case ARM::VST4q16_UPD: 1745 case ARM::VST4q32_UPD: 1746 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1747 break; 1748 default: 1749 break; 1750 } 1751 1752 // AddrMode6 Base (register+alignment) 1753 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1754 1755 // AddrMode6 Offset (register) 1756 if (Rm == 0xD) 1757 Inst.addOperand(MCOperand::CreateReg(0)); 1758 else if (Rm != 0xF) { 1759 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1760 } 1761 1762 // First input register 1763 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1764 1765 // Second input register 1766 switch (Inst.getOpcode()) { 1767 case ARM::VST1q8: 1768 case ARM::VST1q16: 1769 case ARM::VST1q32: 1770 case ARM::VST1q64: 1771 case ARM::VST1q8_UPD: 1772 case ARM::VST1q16_UPD: 1773 case ARM::VST1q32_UPD: 1774 case ARM::VST1q64_UPD: 1775 case ARM::VST1d8T: 1776 case ARM::VST1d16T: 1777 case ARM::VST1d32T: 1778 case ARM::VST1d64T: 1779 case ARM::VST1d8T_UPD: 1780 case ARM::VST1d16T_UPD: 1781 case ARM::VST1d32T_UPD: 1782 case ARM::VST1d64T_UPD: 1783 case ARM::VST1d8Q: 1784 case ARM::VST1d16Q: 1785 case ARM::VST1d32Q: 1786 case ARM::VST1d64Q: 1787 case ARM::VST1d8Q_UPD: 1788 case ARM::VST1d16Q_UPD: 1789 case ARM::VST1d32Q_UPD: 1790 case ARM::VST1d64Q_UPD: 1791 case ARM::VST2d8: 1792 case ARM::VST2d16: 1793 case ARM::VST2d32: 1794 case ARM::VST2d8_UPD: 1795 case ARM::VST2d16_UPD: 1796 case ARM::VST2d32_UPD: 1797 case ARM::VST2q8: 1798 case ARM::VST2q16: 1799 case ARM::VST2q32: 1800 case ARM::VST2q8_UPD: 1801 case ARM::VST2q16_UPD: 1802 case ARM::VST2q32_UPD: 1803 case ARM::VST3d8: 1804 case ARM::VST3d16: 1805 case ARM::VST3d32: 1806 case ARM::VST3d8_UPD: 1807 case ARM::VST3d16_UPD: 1808 case ARM::VST3d32_UPD: 1809 case ARM::VST4d8: 1810 case ARM::VST4d16: 1811 case ARM::VST4d32: 1812 case ARM::VST4d8_UPD: 1813 case ARM::VST4d16_UPD: 1814 case ARM::VST4d32_UPD: 1815 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1816 break; 1817 case ARM::VST2b8: 1818 case ARM::VST2b16: 1819 case ARM::VST2b32: 1820 case ARM::VST2b8_UPD: 1821 case ARM::VST2b16_UPD: 1822 case ARM::VST2b32_UPD: 1823 case ARM::VST3q8: 1824 case ARM::VST3q16: 1825 case ARM::VST3q32: 1826 case ARM::VST3q8_UPD: 1827 case ARM::VST3q16_UPD: 1828 case ARM::VST3q32_UPD: 1829 case ARM::VST4q8: 1830 case ARM::VST4q16: 1831 case ARM::VST4q32: 1832 case ARM::VST4q8_UPD: 1833 case ARM::VST4q16_UPD: 1834 case ARM::VST4q32_UPD: 1835 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1836 break; 1837 default: 1838 break; 1839 } 1840 1841 // Third input register 1842 switch (Inst.getOpcode()) { 1843 case ARM::VST1d8T: 1844 case ARM::VST1d16T: 1845 case ARM::VST1d32T: 1846 case ARM::VST1d64T: 1847 case ARM::VST1d8T_UPD: 1848 case ARM::VST1d16T_UPD: 1849 case ARM::VST1d32T_UPD: 1850 case ARM::VST1d64T_UPD: 1851 case ARM::VST1d8Q: 1852 case ARM::VST1d16Q: 1853 case ARM::VST1d32Q: 1854 case ARM::VST1d64Q: 1855 case ARM::VST1d8Q_UPD: 1856 case ARM::VST1d16Q_UPD: 1857 case ARM::VST1d32Q_UPD: 1858 case ARM::VST1d64Q_UPD: 1859 case ARM::VST2q8: 1860 case ARM::VST2q16: 1861 case ARM::VST2q32: 1862 case ARM::VST2q8_UPD: 1863 case ARM::VST2q16_UPD: 1864 case ARM::VST2q32_UPD: 1865 case ARM::VST3d8: 1866 case ARM::VST3d16: 1867 case ARM::VST3d32: 1868 case ARM::VST3d8_UPD: 1869 case ARM::VST3d16_UPD: 1870 case ARM::VST3d32_UPD: 1871 case ARM::VST4d8: 1872 case ARM::VST4d16: 1873 case ARM::VST4d32: 1874 case ARM::VST4d8_UPD: 1875 case ARM::VST4d16_UPD: 1876 case ARM::VST4d32_UPD: 1877 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1878 break; 1879 case ARM::VST3q8: 1880 case ARM::VST3q16: 1881 case ARM::VST3q32: 1882 case ARM::VST3q8_UPD: 1883 case ARM::VST3q16_UPD: 1884 case ARM::VST3q32_UPD: 1885 case ARM::VST4q8: 1886 case ARM::VST4q16: 1887 case ARM::VST4q32: 1888 case ARM::VST4q8_UPD: 1889 case ARM::VST4q16_UPD: 1890 case ARM::VST4q32_UPD: 1891 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1892 break; 1893 default: 1894 break; 1895 } 1896 1897 // Fourth input register 1898 switch (Inst.getOpcode()) { 1899 case ARM::VST1d8Q: 1900 case ARM::VST1d16Q: 1901 case ARM::VST1d32Q: 1902 case ARM::VST1d64Q: 1903 case ARM::VST1d8Q_UPD: 1904 case ARM::VST1d16Q_UPD: 1905 case ARM::VST1d32Q_UPD: 1906 case ARM::VST1d64Q_UPD: 1907 case ARM::VST2q8: 1908 case ARM::VST2q16: 1909 case ARM::VST2q32: 1910 case ARM::VST2q8_UPD: 1911 case ARM::VST2q16_UPD: 1912 case ARM::VST2q32_UPD: 1913 case ARM::VST4d8: 1914 case ARM::VST4d16: 1915 case ARM::VST4d32: 1916 case ARM::VST4d8_UPD: 1917 case ARM::VST4d16_UPD: 1918 case ARM::VST4d32_UPD: 1919 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1920 break; 1921 case ARM::VST4q8: 1922 case ARM::VST4q16: 1923 case ARM::VST4q32: 1924 case ARM::VST4q8_UPD: 1925 case ARM::VST4q16_UPD: 1926 case ARM::VST4q32_UPD: 1927 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1928 break; 1929 default: 1930 break; 1931 } 1932 1933 return S; 1934 } 1935 1936 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1937 uint64_t Address, const void *Decoder) { 1938 DecodeStatus S = Success; 1939 1940 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1941 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1942 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1943 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1944 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1945 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1946 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1947 1948 align *= (1 << size); 1949 1950 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1951 if (regs == 2) { 1952 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1953 } 1954 if (Rm == 0xD) { 1955 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1956 } 1957 1958 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1959 Inst.addOperand(MCOperand::CreateImm(align)); 1960 1961 if (Rm == 0xD) 1962 Inst.addOperand(MCOperand::CreateReg(0)); 1963 else if (Rm != 0xF) { 1964 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1965 } 1966 1967 return S; 1968 } 1969 1970 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1971 uint64_t Address, const void *Decoder) { 1972 DecodeStatus S = Success; 1973 1974 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1975 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1976 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1977 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1978 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1979 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1980 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1981 align *= 2*size; 1982 1983 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1984 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 1985 if (Rm == 0xD) { 1986 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1987 } 1988 1989 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1990 Inst.addOperand(MCOperand::CreateImm(align)); 1991 1992 if (Rm == 0xD) 1993 Inst.addOperand(MCOperand::CreateReg(0)); 1994 else if (Rm != 0xF) { 1995 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1996 } 1997 1998 return S; 1999 } 2000 2001 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2002 uint64_t Address, const void *Decoder) { 2003 DecodeStatus S = Success; 2004 2005 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2006 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2007 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2008 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2009 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2010 2011 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2012 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2013 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2014 if (Rm == 0xD) { 2015 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2016 } 2017 2018 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2019 Inst.addOperand(MCOperand::CreateImm(0)); 2020 2021 if (Rm == 0xD) 2022 Inst.addOperand(MCOperand::CreateReg(0)); 2023 else if (Rm != 0xF) { 2024 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2025 } 2026 2027 return S; 2028 } 2029 2030 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2031 uint64_t Address, const void *Decoder) { 2032 DecodeStatus S = Success; 2033 2034 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2035 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2036 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2037 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2038 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2039 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2040 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2041 2042 if (size == 0x3) { 2043 size = 4; 2044 align = 16; 2045 } else { 2046 if (size == 2) { 2047 size = 1 << size; 2048 align *= 8; 2049 } else { 2050 size = 1 << size; 2051 align *= 4*size; 2052 } 2053 } 2054 2055 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2056 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2057 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2058 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); 2059 if (Rm == 0xD) { 2060 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2061 } 2062 2063 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2064 Inst.addOperand(MCOperand::CreateImm(align)); 2065 2066 if (Rm == 0xD) 2067 Inst.addOperand(MCOperand::CreateReg(0)); 2068 else if (Rm != 0xF) { 2069 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2070 } 2071 2072 return S; 2073 } 2074 2075 static DecodeStatus 2076 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2077 uint64_t Address, const void *Decoder) { 2078 DecodeStatus S = Success; 2079 2080 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2081 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2082 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2083 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2084 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2085 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2086 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2087 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2088 2089 if (Q) { 2090 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2091 } else { 2092 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2093 } 2094 2095 Inst.addOperand(MCOperand::CreateImm(imm)); 2096 2097 switch (Inst.getOpcode()) { 2098 case ARM::VORRiv4i16: 2099 case ARM::VORRiv2i32: 2100 case ARM::VBICiv4i16: 2101 case ARM::VBICiv2i32: 2102 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2103 break; 2104 case ARM::VORRiv8i16: 2105 case ARM::VORRiv4i32: 2106 case ARM::VBICiv8i16: 2107 case ARM::VBICiv4i32: 2108 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2109 break; 2110 default: 2111 break; 2112 } 2113 2114 return S; 2115 } 2116 2117 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2118 uint64_t Address, const void *Decoder) { 2119 DecodeStatus S = Success; 2120 2121 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2122 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2123 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2124 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2125 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2126 2127 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2128 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2129 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2130 2131 return S; 2132 } 2133 2134 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2135 uint64_t Address, const void *Decoder) { 2136 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2137 return Success; 2138 } 2139 2140 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2141 uint64_t Address, const void *Decoder) { 2142 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2143 return Success; 2144 } 2145 2146 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2147 uint64_t Address, const void *Decoder) { 2148 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2149 return Success; 2150 } 2151 2152 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2153 uint64_t Address, const void *Decoder) { 2154 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2155 return Success; 2156 } 2157 2158 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2159 uint64_t Address, const void *Decoder) { 2160 DecodeStatus S = Success; 2161 2162 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2163 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2164 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2165 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2166 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2167 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2168 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2169 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2170 2171 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2172 if (op) { 2173 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback 2174 } 2175 2176 for (unsigned i = 0; i < length; ++i) { 2177 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)); 2178 } 2179 2180 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2181 2182 return S; 2183 } 2184 2185 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2186 uint64_t Address, const void *Decoder) { 2187 // The immediate needs to be a fully instantiated float. However, the 2188 // auto-generated decoder is only able to fill in some of the bits 2189 // necessary. For instance, the 'b' bit is replicated multiple times, 2190 // and is even present in inverted form in one bit. We do a little 2191 // binary parsing here to fill in those missing bits, and then 2192 // reinterpret it all as a float. 2193 union { 2194 uint32_t integer; 2195 float fp; 2196 } fp_conv; 2197 2198 fp_conv.integer = Val; 2199 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2200 fp_conv.integer |= b << 26; 2201 fp_conv.integer |= b << 27; 2202 fp_conv.integer |= b << 28; 2203 fp_conv.integer |= b << 29; 2204 fp_conv.integer |= (~b & 0x1) << 30; 2205 2206 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2207 return Success; 2208 } 2209 2210 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2211 uint64_t Address, const void *Decoder) { 2212 DecodeStatus S = Success; 2213 2214 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2215 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2216 2217 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); 2218 2219 if (Inst.getOpcode() == ARM::tADR) 2220 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2221 else if (Inst.getOpcode() == ARM::tADDrSPi) 2222 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2223 else 2224 return Fail; 2225 2226 Inst.addOperand(MCOperand::CreateImm(imm)); 2227 return S; 2228 } 2229 2230 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2231 uint64_t Address, const void *Decoder) { 2232 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2233 return Success; 2234 } 2235 2236 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2237 uint64_t Address, const void *Decoder) { 2238 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2239 return Success; 2240 } 2241 2242 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2243 uint64_t Address, const void *Decoder) { 2244 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2245 return Success; 2246 } 2247 2248 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2249 uint64_t Address, const void *Decoder) { 2250 DecodeStatus S = Success; 2251 2252 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2253 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2254 2255 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2256 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); 2257 2258 return S; 2259 } 2260 2261 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2262 uint64_t Address, const void *Decoder) { 2263 DecodeStatus S = Success; 2264 2265 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2266 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2267 2268 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2269 Inst.addOperand(MCOperand::CreateImm(imm)); 2270 2271 return S; 2272 } 2273 2274 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2275 uint64_t Address, const void *Decoder) { 2276 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2277 2278 return Success; 2279 } 2280 2281 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2282 uint64_t Address, const void *Decoder) { 2283 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2284 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2285 2286 return Success; 2287 } 2288 2289 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2290 uint64_t Address, const void *Decoder) { 2291 DecodeStatus S = Success; 2292 2293 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2294 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2295 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2296 2297 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2298 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); 2299 Inst.addOperand(MCOperand::CreateImm(imm)); 2300 2301 return S; 2302 } 2303 2304 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2305 uint64_t Address, const void *Decoder) { 2306 DecodeStatus S = Success; 2307 2308 if (Inst.getOpcode() != ARM::t2PLDs) { 2309 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2310 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2311 } 2312 2313 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2314 if (Rn == 0xF) { 2315 switch (Inst.getOpcode()) { 2316 case ARM::t2LDRBs: 2317 Inst.setOpcode(ARM::t2LDRBpci); 2318 break; 2319 case ARM::t2LDRHs: 2320 Inst.setOpcode(ARM::t2LDRHpci); 2321 break; 2322 case ARM::t2LDRSHs: 2323 Inst.setOpcode(ARM::t2LDRSHpci); 2324 break; 2325 case ARM::t2LDRSBs: 2326 Inst.setOpcode(ARM::t2LDRSBpci); 2327 break; 2328 case ARM::t2PLDs: 2329 Inst.setOpcode(ARM::t2PLDi12); 2330 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2331 break; 2332 default: 2333 return Fail; 2334 } 2335 2336 int imm = fieldFromInstruction32(Insn, 0, 12); 2337 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2338 Inst.addOperand(MCOperand::CreateImm(imm)); 2339 2340 return S; 2341 } 2342 2343 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2344 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2345 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2346 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); 2347 2348 return S; 2349 } 2350 2351 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2352 uint64_t Address, const void *Decoder) { 2353 int imm = Val & 0xFF; 2354 if (!(Val & 0x100)) imm *= -1; 2355 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2356 2357 return Success; 2358 } 2359 2360 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2361 uint64_t Address, const void *Decoder) { 2362 DecodeStatus S = Success; 2363 2364 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2365 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2366 2367 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2368 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); 2369 2370 return S; 2371 } 2372 2373 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2374 uint64_t Address, const void *Decoder) { 2375 int imm = Val & 0xFF; 2376 if (!(Val & 0x100)) imm *= -1; 2377 Inst.addOperand(MCOperand::CreateImm(imm)); 2378 2379 return Success; 2380 } 2381 2382 2383 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2384 uint64_t Address, const void *Decoder) { 2385 DecodeStatus S = Success; 2386 2387 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2388 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2389 2390 // Some instructions always use an additive offset. 2391 switch (Inst.getOpcode()) { 2392 case ARM::t2LDRT: 2393 case ARM::t2LDRBT: 2394 case ARM::t2LDRHT: 2395 case ARM::t2LDRSBT: 2396 case ARM::t2LDRSHT: 2397 imm |= 0x100; 2398 break; 2399 default: 2400 break; 2401 } 2402 2403 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2404 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); 2405 2406 return S; 2407 } 2408 2409 2410 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2411 uint64_t Address, const void *Decoder) { 2412 DecodeStatus S = Success; 2413 2414 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2415 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2416 2417 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2418 Inst.addOperand(MCOperand::CreateImm(imm)); 2419 2420 return S; 2421 } 2422 2423 2424 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2425 uint64_t Address, const void *Decoder) { 2426 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2427 2428 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2429 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2430 Inst.addOperand(MCOperand::CreateImm(imm)); 2431 2432 return Success; 2433 } 2434 2435 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2436 uint64_t Address, const void *Decoder) { 2437 DecodeStatus S = Success; 2438 2439 if (Inst.getOpcode() == ARM::tADDrSP) { 2440 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2441 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2442 2443 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2444 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2445 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2446 } else if (Inst.getOpcode() == ARM::tADDspr) { 2447 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2448 2449 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2450 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2451 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2452 } 2453 2454 return S; 2455 } 2456 2457 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2458 uint64_t Address, const void *Decoder) { 2459 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2460 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2461 2462 Inst.addOperand(MCOperand::CreateImm(imod)); 2463 Inst.addOperand(MCOperand::CreateImm(flags)); 2464 2465 return Success; 2466 } 2467 2468 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2469 uint64_t Address, const void *Decoder) { 2470 DecodeStatus S = Success; 2471 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2472 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2473 2474 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; 2475 Inst.addOperand(MCOperand::CreateImm(add)); 2476 2477 return S; 2478 } 2479 2480 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2481 uint64_t Address, const void *Decoder) { 2482 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2483 return Success; 2484 } 2485 2486 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2487 uint64_t Address, const void *Decoder) { 2488 if (Val == 0xA || Val == 0xB) 2489 return Fail; 2490 2491 Inst.addOperand(MCOperand::CreateImm(Val)); 2492 return Success; 2493 } 2494 2495 static DecodeStatus 2496 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2497 uint64_t Address, const void *Decoder) { 2498 DecodeStatus S = Success; 2499 2500 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2501 if (pred == 0xE || pred == 0xF) { 2502 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2503 switch (opc) { 2504 default: 2505 return Fail; 2506 case 0: 2507 Inst.setOpcode(ARM::t2DSB); 2508 break; 2509 case 1: 2510 Inst.setOpcode(ARM::t2DMB); 2511 break; 2512 case 2: 2513 Inst.setOpcode(ARM::t2ISB); 2514 return Success; 2515 } 2516 2517 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2518 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2519 } 2520 2521 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2522 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2523 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2524 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2525 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2526 2527 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); 2528 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2529 2530 return S; 2531 } 2532 2533 // Decode a shifted immediate operand. These basically consist 2534 // of an 8-bit value, and a 4-bit directive that specifies either 2535 // a splat operation or a rotation. 2536 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2537 uint64_t Address, const void *Decoder) { 2538 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2539 if (ctrl == 0) { 2540 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2541 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2542 switch (byte) { 2543 case 0: 2544 Inst.addOperand(MCOperand::CreateImm(imm)); 2545 break; 2546 case 1: 2547 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2548 break; 2549 case 2: 2550 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2551 break; 2552 case 3: 2553 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2554 (imm << 8) | imm)); 2555 break; 2556 } 2557 } else { 2558 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2559 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2560 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2561 Inst.addOperand(MCOperand::CreateImm(imm)); 2562 } 2563 2564 return Success; 2565 } 2566 2567 static DecodeStatus 2568 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2569 uint64_t Address, const void *Decoder){ 2570 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2571 return Success; 2572 } 2573 2574 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2575 uint64_t Address, const void *Decoder){ 2576 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2577 return Success; 2578 } 2579 2580 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2581 uint64_t Address, const void *Decoder) { 2582 switch (Val) { 2583 default: 2584 return Fail; 2585 case 0xF: // SY 2586 case 0xE: // ST 2587 case 0xB: // ISH 2588 case 0xA: // ISHST 2589 case 0x7: // NSH 2590 case 0x6: // NSHST 2591 case 0x3: // OSH 2592 case 0x2: // OSHST 2593 break; 2594 } 2595 2596 Inst.addOperand(MCOperand::CreateImm(Val)); 2597 return Success; 2598 } 2599 2600 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2601 uint64_t Address, const void *Decoder) { 2602 if (!Val) return Fail; 2603 Inst.addOperand(MCOperand::CreateImm(Val)); 2604 return Success; 2605 } 2606 2607 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2608 uint64_t Address, const void *Decoder) { 2609 DecodeStatus S = Success; 2610 2611 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2612 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2613 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2614 2615 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2616 2617 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2618 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2619 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2620 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2621 2622 return S; 2623 } 2624 2625 2626 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2627 uint64_t Address, const void *Decoder){ 2628 DecodeStatus S = Success; 2629 2630 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2631 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2632 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2633 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2634 2635 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); 2636 2637 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2638 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; 2639 2640 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2641 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2642 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2643 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2644 2645 return S; 2646 } 2647 2648 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2649 uint64_t Address, const void *Decoder) { 2650 DecodeStatus S = Success; 2651 2652 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2653 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2654 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2655 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2656 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2657 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2658 2659 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2660 2661 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2662 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2663 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); 2664 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2665 2666 return S; 2667 } 2668 2669 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2670 uint64_t Address, const void *Decoder) { 2671 DecodeStatus S = Success; 2672 2673 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2674 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2675 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2676 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2677 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2678 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2679 2680 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable); 2681 2682 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2683 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2684 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); 2685 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2686 2687 return S; 2688 } 2689 2690 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2691 uint64_t Address, const void *Decoder) { 2692 DecodeStatus S = Success; 2693 2694 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2695 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2696 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2697 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2698 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2699 2700 unsigned align = 0; 2701 unsigned index = 0; 2702 switch (size) { 2703 default: 2704 return Fail; 2705 case 0: 2706 if (fieldFromInstruction32(Insn, 4, 1)) 2707 return Fail; // UNDEFINED 2708 index = fieldFromInstruction32(Insn, 5, 3); 2709 break; 2710 case 1: 2711 if (fieldFromInstruction32(Insn, 5, 1)) 2712 return Fail; // UNDEFINED 2713 index = fieldFromInstruction32(Insn, 6, 2); 2714 if (fieldFromInstruction32(Insn, 4, 1)) 2715 align = 2; 2716 break; 2717 case 2: 2718 if (fieldFromInstruction32(Insn, 6, 1)) 2719 return Fail; // UNDEFINED 2720 index = fieldFromInstruction32(Insn, 7, 1); 2721 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2722 align = 4; 2723 } 2724 2725 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2726 if (Rm != 0xF) { // Writeback 2727 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2728 } 2729 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2730 Inst.addOperand(MCOperand::CreateImm(align)); 2731 if (Rm != 0xF && Rm != 0xD) { 2732 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2733 } 2734 2735 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2736 Inst.addOperand(MCOperand::CreateImm(index)); 2737 2738 return S; 2739 } 2740 2741 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2742 uint64_t Address, const void *Decoder) { 2743 DecodeStatus S = Success; 2744 2745 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2746 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2747 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2748 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2749 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2750 2751 unsigned align = 0; 2752 unsigned index = 0; 2753 switch (size) { 2754 default: 2755 return Fail; 2756 case 0: 2757 if (fieldFromInstruction32(Insn, 4, 1)) 2758 return Fail; // UNDEFINED 2759 index = fieldFromInstruction32(Insn, 5, 3); 2760 break; 2761 case 1: 2762 if (fieldFromInstruction32(Insn, 5, 1)) 2763 return Fail; // UNDEFINED 2764 index = fieldFromInstruction32(Insn, 6, 2); 2765 if (fieldFromInstruction32(Insn, 4, 1)) 2766 align = 2; 2767 break; 2768 case 2: 2769 if (fieldFromInstruction32(Insn, 6, 1)) 2770 return Fail; // UNDEFINED 2771 index = fieldFromInstruction32(Insn, 7, 1); 2772 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2773 align = 4; 2774 } 2775 2776 if (Rm != 0xF) { // Writeback 2777 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2778 } 2779 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2780 Inst.addOperand(MCOperand::CreateImm(align)); 2781 if (Rm != 0xF && Rm != 0xD) { 2782 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2783 } 2784 2785 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2786 Inst.addOperand(MCOperand::CreateImm(index)); 2787 2788 return S; 2789 } 2790 2791 2792 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2793 uint64_t Address, const void *Decoder) { 2794 DecodeStatus S = Success; 2795 2796 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2797 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2798 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2799 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2800 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2801 2802 unsigned align = 0; 2803 unsigned index = 0; 2804 unsigned inc = 1; 2805 switch (size) { 2806 default: 2807 return Fail; 2808 case 0: 2809 index = fieldFromInstruction32(Insn, 5, 3); 2810 if (fieldFromInstruction32(Insn, 4, 1)) 2811 align = 2; 2812 break; 2813 case 1: 2814 index = fieldFromInstruction32(Insn, 6, 2); 2815 if (fieldFromInstruction32(Insn, 4, 1)) 2816 align = 4; 2817 if (fieldFromInstruction32(Insn, 5, 1)) 2818 inc = 2; 2819 break; 2820 case 2: 2821 if (fieldFromInstruction32(Insn, 5, 1)) 2822 return Fail; // UNDEFINED 2823 index = fieldFromInstruction32(Insn, 7, 1); 2824 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2825 align = 8; 2826 if (fieldFromInstruction32(Insn, 6, 1)) 2827 inc = 2; 2828 break; 2829 } 2830 2831 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2832 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2833 if (Rm != 0xF) { // Writeback 2834 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2835 } 2836 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2837 Inst.addOperand(MCOperand::CreateImm(align)); 2838 if (Rm != 0xF && Rm != 0xD) { 2839 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2840 } 2841 2842 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2843 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2844 Inst.addOperand(MCOperand::CreateImm(index)); 2845 2846 return S; 2847 } 2848 2849 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2850 uint64_t Address, const void *Decoder) { 2851 DecodeStatus S = Success; 2852 2853 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2854 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2855 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2856 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2857 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2858 2859 unsigned align = 0; 2860 unsigned index = 0; 2861 unsigned inc = 1; 2862 switch (size) { 2863 default: 2864 return Fail; 2865 case 0: 2866 index = fieldFromInstruction32(Insn, 5, 3); 2867 if (fieldFromInstruction32(Insn, 4, 1)) 2868 align = 2; 2869 break; 2870 case 1: 2871 index = fieldFromInstruction32(Insn, 6, 2); 2872 if (fieldFromInstruction32(Insn, 4, 1)) 2873 align = 4; 2874 if (fieldFromInstruction32(Insn, 5, 1)) 2875 inc = 2; 2876 break; 2877 case 2: 2878 if (fieldFromInstruction32(Insn, 5, 1)) 2879 return Fail; // UNDEFINED 2880 index = fieldFromInstruction32(Insn, 7, 1); 2881 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2882 align = 8; 2883 if (fieldFromInstruction32(Insn, 6, 1)) 2884 inc = 2; 2885 break; 2886 } 2887 2888 if (Rm != 0xF) { // Writeback 2889 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2890 } 2891 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2892 Inst.addOperand(MCOperand::CreateImm(align)); 2893 if (Rm != 0xF && Rm != 0xD) { 2894 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2895 } 2896 2897 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2898 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2899 Inst.addOperand(MCOperand::CreateImm(index)); 2900 2901 return S; 2902 } 2903 2904 2905 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 2906 uint64_t Address, const void *Decoder) { 2907 DecodeStatus S = Success; 2908 2909 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2910 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2911 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2912 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2913 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2914 2915 unsigned align = 0; 2916 unsigned index = 0; 2917 unsigned inc = 1; 2918 switch (size) { 2919 default: 2920 return Fail; 2921 case 0: 2922 if (fieldFromInstruction32(Insn, 4, 1)) 2923 return Fail; // UNDEFINED 2924 index = fieldFromInstruction32(Insn, 5, 3); 2925 break; 2926 case 1: 2927 if (fieldFromInstruction32(Insn, 4, 1)) 2928 return Fail; // UNDEFINED 2929 index = fieldFromInstruction32(Insn, 6, 2); 2930 if (fieldFromInstruction32(Insn, 5, 1)) 2931 inc = 2; 2932 break; 2933 case 2: 2934 if (fieldFromInstruction32(Insn, 4, 2)) 2935 return Fail; // UNDEFINED 2936 index = fieldFromInstruction32(Insn, 7, 1); 2937 if (fieldFromInstruction32(Insn, 6, 1)) 2938 inc = 2; 2939 break; 2940 } 2941 2942 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2943 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2944 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2945 2946 if (Rm != 0xF) { // Writeback 2947 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2948 } 2949 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2950 Inst.addOperand(MCOperand::CreateImm(align)); 2951 if (Rm != 0xF && Rm != 0xD) { 2952 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2953 } 2954 2955 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2956 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2957 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2958 Inst.addOperand(MCOperand::CreateImm(index)); 2959 2960 return S; 2961 } 2962 2963 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 2964 uint64_t Address, const void *Decoder) { 2965 DecodeStatus S = Success; 2966 2967 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2968 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2969 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2970 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2971 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2972 2973 unsigned align = 0; 2974 unsigned index = 0; 2975 unsigned inc = 1; 2976 switch (size) { 2977 default: 2978 return Fail; 2979 case 0: 2980 if (fieldFromInstruction32(Insn, 4, 1)) 2981 return Fail; // UNDEFINED 2982 index = fieldFromInstruction32(Insn, 5, 3); 2983 break; 2984 case 1: 2985 if (fieldFromInstruction32(Insn, 4, 1)) 2986 return Fail; // UNDEFINED 2987 index = fieldFromInstruction32(Insn, 6, 2); 2988 if (fieldFromInstruction32(Insn, 5, 1)) 2989 inc = 2; 2990 break; 2991 case 2: 2992 if (fieldFromInstruction32(Insn, 4, 2)) 2993 return Fail; // UNDEFINED 2994 index = fieldFromInstruction32(Insn, 7, 1); 2995 if (fieldFromInstruction32(Insn, 6, 1)) 2996 inc = 2; 2997 break; 2998 } 2999 3000 if (Rm != 0xF) { // Writeback 3001 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3002 } 3003 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3004 Inst.addOperand(MCOperand::CreateImm(align)); 3005 if (Rm != 0xF && Rm != 0xD) { 3006 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3007 } 3008 3009 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3010 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3011 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3012 Inst.addOperand(MCOperand::CreateImm(index)); 3013 3014 return S; 3015 } 3016 3017 3018 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3019 uint64_t Address, const void *Decoder) { 3020 DecodeStatus S = Success; 3021 3022 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3023 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3024 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3025 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3026 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3027 3028 unsigned align = 0; 3029 unsigned index = 0; 3030 unsigned inc = 1; 3031 switch (size) { 3032 default: 3033 return Fail; 3034 case 0: 3035 if (fieldFromInstruction32(Insn, 4, 1)) 3036 align = 4; 3037 index = fieldFromInstruction32(Insn, 5, 3); 3038 break; 3039 case 1: 3040 if (fieldFromInstruction32(Insn, 4, 1)) 3041 align = 8; 3042 index = fieldFromInstruction32(Insn, 6, 2); 3043 if (fieldFromInstruction32(Insn, 5, 1)) 3044 inc = 2; 3045 break; 3046 case 2: 3047 if (fieldFromInstruction32(Insn, 4, 2)) 3048 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3049 index = fieldFromInstruction32(Insn, 7, 1); 3050 if (fieldFromInstruction32(Insn, 6, 1)) 3051 inc = 2; 3052 break; 3053 } 3054 3055 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3056 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3057 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3058 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3059 3060 if (Rm != 0xF) { // Writeback 3061 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3062 } 3063 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3064 Inst.addOperand(MCOperand::CreateImm(align)); 3065 if (Rm != 0xF && Rm != 0xD) { 3066 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3067 } 3068 3069 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3070 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3071 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3072 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3073 Inst.addOperand(MCOperand::CreateImm(index)); 3074 3075 return S; 3076 } 3077 3078 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3079 uint64_t Address, const void *Decoder) { 3080 DecodeStatus S = Success; 3081 3082 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3083 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3084 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3085 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3086 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3087 3088 unsigned align = 0; 3089 unsigned index = 0; 3090 unsigned inc = 1; 3091 switch (size) { 3092 default: 3093 return Fail; 3094 case 0: 3095 if (fieldFromInstruction32(Insn, 4, 1)) 3096 align = 4; 3097 index = fieldFromInstruction32(Insn, 5, 3); 3098 break; 3099 case 1: 3100 if (fieldFromInstruction32(Insn, 4, 1)) 3101 align = 8; 3102 index = fieldFromInstruction32(Insn, 6, 2); 3103 if (fieldFromInstruction32(Insn, 5, 1)) 3104 inc = 2; 3105 break; 3106 case 2: 3107 if (fieldFromInstruction32(Insn, 4, 2)) 3108 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3109 index = fieldFromInstruction32(Insn, 7, 1); 3110 if (fieldFromInstruction32(Insn, 6, 1)) 3111 inc = 2; 3112 break; 3113 } 3114 3115 if (Rm != 0xF) { // Writeback 3116 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3117 } 3118 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3119 Inst.addOperand(MCOperand::CreateImm(align)); 3120 if (Rm != 0xF && Rm != 0xD) { 3121 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3122 } 3123 3124 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3125 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3126 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3127 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3128 Inst.addOperand(MCOperand::CreateImm(index)); 3129 3130 return S; 3131 } 3132 3133