1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 137 uint64_t Address, const void *Decoder); 138 static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 139 uint64_t Address, const void *Decoder); 140 static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 145 uint64_t Address, const void *Decoder); 146 147 148 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 149 uint64_t Address, const void *Decoder); 150 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 151 uint64_t Address, const void *Decoder); 152 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 153 uint64_t Address, const void *Decoder); 154 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 155 uint64_t Address, const void *Decoder); 156 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 157 uint64_t Address, const void *Decoder); 158 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 159 uint64_t Address, const void *Decoder); 160 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 161 uint64_t Address, const void *Decoder); 162 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 163 uint64_t Address, const void *Decoder); 164 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 167 uint64_t Address, const void *Decoder); 168 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 169 uint64_t Address, const void *Decoder); 170 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 171 uint64_t Address, const void *Decoder); 172 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 173 uint64_t Address, const void *Decoder); 174 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 177 uint64_t Address, const void *Decoder); 178 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 179 uint64_t Address, const void *Decoder); 180 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 181 uint64_t Address, const void *Decoder); 182 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 183 uint64_t Address, const void *Decoder); 184 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 197 #include "ARMGenDisassemblerTables.inc" 198 #include "ARMGenInstrInfo.inc" 199 #include "ARMGenEDInfo.inc" 200 201 using namespace llvm; 202 203 static MCDisassembler *createARMDisassembler(const Target &T) { 204 return new ARMDisassembler; 205 } 206 207 static MCDisassembler *createThumbDisassembler(const Target &T) { 208 return new ThumbDisassembler; 209 } 210 211 EDInstInfo *ARMDisassembler::getEDInfo() const { 212 return instInfoARM; 213 } 214 215 EDInstInfo *ThumbDisassembler::getEDInfo() const { 216 return instInfoARM; 217 } 218 219 220 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 221 const MemoryObject &Region, 222 uint64_t Address,raw_ostream &os) const { 223 uint8_t bytes[4]; 224 225 // We want to read exactly 4 bytes of data. 226 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 227 return false; 228 229 // Encoded as a small-endian 32-bit word in the stream. 230 uint32_t insn = (bytes[3] << 24) | 231 (bytes[2] << 16) | 232 (bytes[1] << 8) | 233 (bytes[0] << 0); 234 235 // Calling the auto-generated decoder function. 236 bool result = decodeARMInstruction32(MI, insn, Address, this); 237 if (result) { 238 Size = 4; 239 return true; 240 } 241 242 // Instructions that are shared between ARM and Thumb modes. 243 // FIXME: This shouldn't really exist. It's an artifact of the 244 // fact that we fail to encode a few instructions properly for Thumb. 245 MI.clear(); 246 result = decodeCommonInstruction32(MI, insn, Address, this); 247 if (result) { 248 Size = 4; 249 return true; 250 } 251 252 // VFP and NEON instructions, similarly, are shared between ARM 253 // and Thumb modes. 254 MI.clear(); 255 result = decodeVFPInstruction32(MI, insn, Address, this); 256 if (result) { 257 Size = 4; 258 return true; 259 } 260 261 MI.clear(); 262 result = decodeNEONDataInstruction32(MI, insn, Address, this); 263 if (result) { 264 Size = 4; 265 // Add a fake predicate operand, because we share these instruction 266 // definitions with Thumb2 where these instructions are predicable. 267 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 268 return true; 269 } 270 271 MI.clear(); 272 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 273 if (result) { 274 Size = 4; 275 // Add a fake predicate operand, because we share these instruction 276 // definitions with Thumb2 where these instructions are predicable. 277 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 278 return true; 279 } 280 281 MI.clear(); 282 result = decodeNEONDupInstruction32(MI, insn, Address, this); 283 if (result) { 284 Size = 4; 285 // Add a fake predicate operand, because we share these instruction 286 // definitions with Thumb2 where these instructions are predicable. 287 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 288 return true; 289 } 290 291 MI.clear(); 292 293 return false; 294 } 295 296 namespace llvm { 297 extern MCInstrDesc ARMInsts[]; 298 } 299 300 // Thumb1 instructions don't have explicit S bits. Rather, they 301 // implicitly set CPSR. Since it's not represented in the encoding, the 302 // auto-generated decoder won't inject the CPSR operand. We need to fix 303 // that as a post-pass. 304 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 305 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 306 MCInst::iterator I = MI.begin(); 307 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 308 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 309 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 310 return; 311 } 312 } 313 314 if (OpInfo[MI.size()].isOptionalDef() && 315 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 316 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 317 } 318 319 // Most Thumb instructions don't have explicit predicates in the 320 // encoding, but rather get their predicates from IT context. We need 321 // to fix up the predicate operands using this context information as a 322 // post-pass. 323 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 324 // A few instructions actually have predicates encoded in them. Don't 325 // try to overwrite it if we're seeing one of those. 326 switch (MI.getOpcode()) { 327 case ARM::tBcc: 328 case ARM::t2Bcc: 329 return; 330 default: 331 break; 332 } 333 334 // If we're in an IT block, base the predicate on that. Otherwise, 335 // assume a predicate of AL. 336 unsigned CC; 337 if (!ITBlock.empty()) { 338 CC = ITBlock.back(); 339 ITBlock.pop_back(); 340 } else 341 CC = ARMCC::AL; 342 343 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 344 MCInst::iterator I = MI.begin(); 345 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 346 if (OpInfo[i].isPredicate()) { 347 I = MI.insert(I, MCOperand::CreateImm(CC)); 348 ++I; 349 if (CC == ARMCC::AL) 350 MI.insert(I, MCOperand::CreateReg(0)); 351 else 352 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 353 return; 354 } 355 } 356 357 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 358 if (CC == ARMCC::AL) 359 MI.insert(MI.end(), MCOperand::CreateReg(0)); 360 else 361 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 362 } 363 364 // Thumb VFP instructions are a special case. Because we share their 365 // encodings between ARM and Thumb modes, and they are predicable in ARM 366 // mode, the auto-generated decoder will give them an (incorrect) 367 // predicate operand. We need to rewrite these operands based on the IT 368 // context as a post-pass. 369 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 370 unsigned CC; 371 if (!ITBlock.empty()) { 372 CC = ITBlock.back(); 373 ITBlock.pop_back(); 374 } else 375 CC = ARMCC::AL; 376 377 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 378 MCInst::iterator I = MI.begin(); 379 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 380 if (OpInfo[i].isPredicate() ) { 381 I->setImm(CC); 382 ++I; 383 if (CC == ARMCC::AL) 384 I->setReg(0); 385 else 386 I->setReg(ARM::CPSR); 387 return; 388 } 389 } 390 } 391 392 393 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 394 const MemoryObject &Region, 395 uint64_t Address,raw_ostream &os) const { 396 uint8_t bytes[4]; 397 398 // We want to read exactly 2 bytes of data. 399 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 400 return false; 401 402 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 403 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 404 if (result) { 405 Size = 2; 406 bool InITBlock = !ITBlock.empty(); 407 AddThumbPredicate(MI); 408 AddThumb1SBit(MI, InITBlock); 409 return true; 410 } 411 412 MI.clear(); 413 result = decodeThumb2Instruction16(MI, insn16, Address, this); 414 if (result) { 415 Size = 2; 416 AddThumbPredicate(MI); 417 418 // If we find an IT instruction, we need to parse its condition 419 // code and mask operands so that we can apply them correctly 420 // to the subsequent instructions. 421 if (MI.getOpcode() == ARM::t2IT) { 422 unsigned firstcond = MI.getOperand(0).getImm(); 423 uint32_t mask = MI.getOperand(1).getImm(); 424 unsigned zeros = CountTrailingZeros_32(mask); 425 mask >>= zeros+1; 426 427 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 428 if (firstcond ^ (mask & 1)) 429 ITBlock.push_back(firstcond ^ 1); 430 else 431 ITBlock.push_back(firstcond); 432 mask >>= 1; 433 } 434 ITBlock.push_back(firstcond); 435 } 436 437 return true; 438 } 439 440 // We want to read exactly 4 bytes of data. 441 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 442 return false; 443 444 uint32_t insn32 = (bytes[3] << 8) | 445 (bytes[2] << 0) | 446 (bytes[1] << 24) | 447 (bytes[0] << 16); 448 MI.clear(); 449 result = decodeThumbInstruction32(MI, insn32, Address, this); 450 if (result) { 451 Size = 4; 452 bool InITBlock = ITBlock.size(); 453 AddThumbPredicate(MI); 454 AddThumb1SBit(MI, InITBlock); 455 return true; 456 } 457 458 MI.clear(); 459 result = decodeThumb2Instruction32(MI, insn32, Address, this); 460 if (result) { 461 Size = 4; 462 AddThumbPredicate(MI); 463 return true; 464 } 465 466 MI.clear(); 467 result = decodeCommonInstruction32(MI, insn32, Address, this); 468 if (result) { 469 Size = 4; 470 AddThumbPredicate(MI); 471 return true; 472 } 473 474 MI.clear(); 475 result = decodeVFPInstruction32(MI, insn32, Address, this); 476 if (result) { 477 Size = 4; 478 UpdateThumbVFPPredicate(MI); 479 return true; 480 } 481 482 MI.clear(); 483 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 484 uint32_t NEONDataInsn = insn32; 485 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 486 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 487 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 488 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 489 if (result) { 490 Size = 4; 491 AddThumbPredicate(MI); 492 return true; 493 } 494 } 495 496 MI.clear(); 497 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); 498 if (result) { 499 Size = 4; 500 AddThumbPredicate(MI); 501 return true; 502 } 503 504 MI.clear(); 505 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 506 if (result) { 507 Size = 4; 508 AddThumbPredicate(MI); 509 return true; 510 } 511 512 return false; 513 } 514 515 516 extern "C" void LLVMInitializeARMDisassembler() { 517 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 518 createARMDisassembler); 519 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 520 createThumbDisassembler); 521 } 522 523 static const unsigned GPRDecoderTable[] = { 524 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 525 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 526 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 527 ARM::R12, ARM::SP, ARM::LR, ARM::PC 528 }; 529 530 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 531 uint64_t Address, const void *Decoder) { 532 if (RegNo > 15) 533 return false; 534 535 unsigned Register = GPRDecoderTable[RegNo]; 536 Inst.addOperand(MCOperand::CreateReg(Register)); 537 return true; 538 } 539 540 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 541 uint64_t Address, const void *Decoder) { 542 if (RegNo == 15) return false; 543 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 544 } 545 546 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 547 uint64_t Address, const void *Decoder) { 548 if (RegNo > 7) 549 return false; 550 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 551 } 552 553 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 554 uint64_t Address, const void *Decoder) { 555 unsigned Register = 0; 556 switch (RegNo) { 557 case 0: 558 Register = ARM::R0; 559 break; 560 case 1: 561 Register = ARM::R1; 562 break; 563 case 2: 564 Register = ARM::R2; 565 break; 566 case 3: 567 Register = ARM::R3; 568 break; 569 case 9: 570 Register = ARM::R9; 571 break; 572 case 12: 573 Register = ARM::R12; 574 break; 575 default: 576 return false; 577 } 578 579 Inst.addOperand(MCOperand::CreateReg(Register)); 580 return true; 581 } 582 583 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 584 uint64_t Address, const void *Decoder) { 585 if (RegNo == 13 || RegNo == 15) return false; 586 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 587 } 588 589 static const unsigned SPRDecoderTable[] = { 590 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 591 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 592 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 593 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 594 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 595 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 596 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 597 ARM::S28, ARM::S29, ARM::S30, ARM::S31 598 }; 599 600 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 601 uint64_t Address, const void *Decoder) { 602 if (RegNo > 31) 603 return false; 604 605 unsigned Register = SPRDecoderTable[RegNo]; 606 Inst.addOperand(MCOperand::CreateReg(Register)); 607 return true; 608 } 609 610 static const unsigned DPRDecoderTable[] = { 611 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 612 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 613 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 614 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 615 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 616 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 617 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 618 ARM::D28, ARM::D29, ARM::D30, ARM::D31 619 }; 620 621 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 622 uint64_t Address, const void *Decoder) { 623 if (RegNo > 31) 624 return false; 625 626 unsigned Register = DPRDecoderTable[RegNo]; 627 Inst.addOperand(MCOperand::CreateReg(Register)); 628 return true; 629 } 630 631 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 632 uint64_t Address, const void *Decoder) { 633 if (RegNo > 7) 634 return false; 635 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 636 } 637 638 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 639 uint64_t Address, const void *Decoder) { 640 if (RegNo > 15) 641 return false; 642 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 643 } 644 645 static const unsigned QPRDecoderTable[] = { 646 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 647 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 648 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 649 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 650 }; 651 652 653 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 654 uint64_t Address, const void *Decoder) { 655 if (RegNo > 31) 656 return false; 657 RegNo >>= 1; 658 659 unsigned Register = QPRDecoderTable[RegNo]; 660 Inst.addOperand(MCOperand::CreateReg(Register)); 661 return true; 662 } 663 664 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 665 uint64_t Address, const void *Decoder) { 666 if (Val == 0xF) return false; 667 // AL predicate is not allowed on Thumb1 branches. 668 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 669 return false; 670 Inst.addOperand(MCOperand::CreateImm(Val)); 671 if (Val == ARMCC::AL) { 672 Inst.addOperand(MCOperand::CreateReg(0)); 673 } else 674 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 675 return true; 676 } 677 678 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 679 uint64_t Address, const void *Decoder) { 680 if (Val) 681 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 682 else 683 Inst.addOperand(MCOperand::CreateReg(0)); 684 return true; 685 } 686 687 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 688 uint64_t Address, const void *Decoder) { 689 uint32_t imm = Val & 0xFF; 690 uint32_t rot = (Val & 0xF00) >> 7; 691 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 692 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 693 return true; 694 } 695 696 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 697 uint64_t Address, const void *Decoder) { 698 Val <<= 2; 699 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 700 return true; 701 } 702 703 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 704 uint64_t Address, const void *Decoder) { 705 706 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 707 unsigned type = fieldFromInstruction32(Val, 5, 2); 708 unsigned imm = fieldFromInstruction32(Val, 7, 5); 709 710 // Register-immediate 711 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 712 713 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 714 switch (type) { 715 case 0: 716 Shift = ARM_AM::lsl; 717 break; 718 case 1: 719 Shift = ARM_AM::lsr; 720 break; 721 case 2: 722 Shift = ARM_AM::asr; 723 break; 724 case 3: 725 Shift = ARM_AM::ror; 726 break; 727 } 728 729 if (Shift == ARM_AM::ror && imm == 0) 730 Shift = ARM_AM::rrx; 731 732 unsigned Op = Shift | (imm << 3); 733 Inst.addOperand(MCOperand::CreateImm(Op)); 734 735 return true; 736 } 737 738 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 739 uint64_t Address, const void *Decoder) { 740 741 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 742 unsigned type = fieldFromInstruction32(Val, 5, 2); 743 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 744 745 // Register-register 746 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 747 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 748 749 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 750 switch (type) { 751 case 0: 752 Shift = ARM_AM::lsl; 753 break; 754 case 1: 755 Shift = ARM_AM::lsr; 756 break; 757 case 2: 758 Shift = ARM_AM::asr; 759 break; 760 case 3: 761 Shift = ARM_AM::ror; 762 break; 763 } 764 765 Inst.addOperand(MCOperand::CreateImm(Shift)); 766 767 return true; 768 } 769 770 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 771 uint64_t Address, const void *Decoder) { 772 // Empty register lists are not allowed. 773 if (CountPopulation_32(Val) == 0) return false; 774 for (unsigned i = 0; i < 16; ++i) { 775 if (Val & (1 << i)) { 776 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 777 } 778 } 779 780 return true; 781 } 782 783 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 784 uint64_t Address, const void *Decoder) { 785 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 786 unsigned regs = Val & 0xFF; 787 788 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 789 for (unsigned i = 0; i < (regs - 1); ++i) { 790 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 791 } 792 793 return true; 794 } 795 796 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 797 uint64_t Address, const void *Decoder) { 798 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 799 unsigned regs = (Val & 0xFF) / 2; 800 801 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 802 for (unsigned i = 0; i < (regs - 1); ++i) { 803 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 804 } 805 806 return true; 807 } 808 809 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 810 uint64_t Address, const void *Decoder) { 811 // This operand encodes a mask of contiguous zeros between a specified MSB 812 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 813 // the mask of all bits LSB-and-lower, and then xor them to create 814 // the mask of that's all ones on [msb, lsb]. Finally we not it to 815 // create the final mask. 816 unsigned msb = fieldFromInstruction32(Val, 5, 5); 817 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 818 uint32_t msb_mask = (1 << (msb+1)) - 1; 819 uint32_t lsb_mask = (1 << lsb) - 1; 820 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 821 return true; 822 } 823 824 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 825 uint64_t Address, const void *Decoder) { 826 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 827 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 828 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 829 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 830 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 831 unsigned U = fieldFromInstruction32(Insn, 23, 1); 832 833 switch (Inst.getOpcode()) { 834 case ARM::LDC_OFFSET: 835 case ARM::LDC_PRE: 836 case ARM::LDC_POST: 837 case ARM::LDC_OPTION: 838 case ARM::LDCL_OFFSET: 839 case ARM::LDCL_PRE: 840 case ARM::LDCL_POST: 841 case ARM::LDCL_OPTION: 842 case ARM::STC_OFFSET: 843 case ARM::STC_PRE: 844 case ARM::STC_POST: 845 case ARM::STC_OPTION: 846 case ARM::STCL_OFFSET: 847 case ARM::STCL_PRE: 848 case ARM::STCL_POST: 849 case ARM::STCL_OPTION: 850 if (coproc == 0xA || coproc == 0xB) 851 return false; 852 break; 853 default: 854 break; 855 } 856 857 Inst.addOperand(MCOperand::CreateImm(coproc)); 858 Inst.addOperand(MCOperand::CreateImm(CRd)); 859 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 860 switch (Inst.getOpcode()) { 861 case ARM::LDC_OPTION: 862 case ARM::LDCL_OPTION: 863 case ARM::LDC2_OPTION: 864 case ARM::LDC2L_OPTION: 865 case ARM::STC_OPTION: 866 case ARM::STCL_OPTION: 867 case ARM::STC2_OPTION: 868 case ARM::STC2L_OPTION: 869 case ARM::LDCL_POST: 870 case ARM::STCL_POST: 871 break; 872 default: 873 Inst.addOperand(MCOperand::CreateReg(0)); 874 break; 875 } 876 877 unsigned P = fieldFromInstruction32(Insn, 24, 1); 878 unsigned W = fieldFromInstruction32(Insn, 21, 1); 879 880 bool writeback = (P == 0) || (W == 1); 881 unsigned idx_mode = 0; 882 if (P && writeback) 883 idx_mode = ARMII::IndexModePre; 884 else if (!P && writeback) 885 idx_mode = ARMII::IndexModePost; 886 887 switch (Inst.getOpcode()) { 888 case ARM::LDCL_POST: 889 case ARM::STCL_POST: 890 imm |= U << 8; 891 case ARM::LDC_OPTION: 892 case ARM::LDCL_OPTION: 893 case ARM::LDC2_OPTION: 894 case ARM::LDC2L_OPTION: 895 case ARM::STC_OPTION: 896 case ARM::STCL_OPTION: 897 case ARM::STC2_OPTION: 898 case ARM::STC2L_OPTION: 899 Inst.addOperand(MCOperand::CreateImm(imm)); 900 break; 901 default: 902 if (U) 903 Inst.addOperand(MCOperand::CreateImm( 904 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 905 else 906 Inst.addOperand(MCOperand::CreateImm( 907 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 908 break; 909 } 910 911 switch (Inst.getOpcode()) { 912 case ARM::LDC_OFFSET: 913 case ARM::LDC_PRE: 914 case ARM::LDC_POST: 915 case ARM::LDC_OPTION: 916 case ARM::LDCL_OFFSET: 917 case ARM::LDCL_PRE: 918 case ARM::LDCL_POST: 919 case ARM::LDCL_OPTION: 920 case ARM::STC_OFFSET: 921 case ARM::STC_PRE: 922 case ARM::STC_POST: 923 case ARM::STC_OPTION: 924 case ARM::STCL_OFFSET: 925 case ARM::STCL_PRE: 926 case ARM::STCL_POST: 927 case ARM::STCL_OPTION: 928 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 929 break; 930 default: 931 break; 932 } 933 934 return true; 935 } 936 937 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 938 uint64_t Address, const void *Decoder) { 939 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 940 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 941 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 942 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 943 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 944 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 945 unsigned P = fieldFromInstruction32(Insn, 24, 1); 946 unsigned W = fieldFromInstruction32(Insn, 21, 1); 947 948 // On stores, the writeback operand precedes Rt. 949 switch (Inst.getOpcode()) { 950 case ARM::STR_POST_IMM: 951 case ARM::STR_POST_REG: 952 case ARM::STRB_POST_IMM: 953 case ARM::STRB_POST_REG: 954 case ARM::STRT_POST_REG: 955 case ARM::STRT_POST_IMM: 956 case ARM::STRBT_POST_REG: 957 case ARM::STRBT_POST_IMM: 958 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 959 break; 960 default: 961 break; 962 } 963 964 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 965 966 // On loads, the writeback operand comes after Rt. 967 switch (Inst.getOpcode()) { 968 case ARM::LDR_POST_IMM: 969 case ARM::LDR_POST_REG: 970 case ARM::LDRB_POST_IMM: 971 case ARM::LDRB_POST_REG: 972 case ARM::LDR_PRE: 973 case ARM::LDRBT_POST_REG: 974 case ARM::LDRBT_POST_IMM: 975 case ARM::LDRT_POST_REG: 976 case ARM::LDRT_POST_IMM: 977 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 978 return false; 979 break; 980 default: 981 break; 982 } 983 984 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 985 986 ARM_AM::AddrOpc Op = ARM_AM::add; 987 if (!fieldFromInstruction32(Insn, 23, 1)) 988 Op = ARM_AM::sub; 989 990 bool writeback = (P == 0) || (W == 1); 991 unsigned idx_mode = 0; 992 if (P && writeback) 993 idx_mode = ARMII::IndexModePre; 994 else if (!P && writeback) 995 idx_mode = ARMII::IndexModePost; 996 997 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE 998 999 if (reg) { 1000 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 1001 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1002 switch( fieldFromInstruction32(Insn, 5, 2)) { 1003 case 0: 1004 Opc = ARM_AM::lsl; 1005 break; 1006 case 1: 1007 Opc = ARM_AM::lsr; 1008 break; 1009 case 2: 1010 Opc = ARM_AM::asr; 1011 break; 1012 case 3: 1013 Opc = ARM_AM::ror; 1014 break; 1015 default: 1016 return false; 1017 } 1018 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1019 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1020 1021 Inst.addOperand(MCOperand::CreateImm(imm)); 1022 } else { 1023 Inst.addOperand(MCOperand::CreateReg(0)); 1024 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1025 Inst.addOperand(MCOperand::CreateImm(tmp)); 1026 } 1027 1028 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1029 1030 return true; 1031 } 1032 1033 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1034 uint64_t Address, const void *Decoder) { 1035 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1036 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1037 unsigned type = fieldFromInstruction32(Val, 5, 2); 1038 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1039 unsigned U = fieldFromInstruction32(Val, 12, 1); 1040 1041 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1042 switch (type) { 1043 case 0: 1044 ShOp = ARM_AM::lsl; 1045 break; 1046 case 1: 1047 ShOp = ARM_AM::lsr; 1048 break; 1049 case 2: 1050 ShOp = ARM_AM::asr; 1051 break; 1052 case 3: 1053 ShOp = ARM_AM::ror; 1054 break; 1055 } 1056 1057 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1058 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1059 unsigned shift; 1060 if (U) 1061 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1062 else 1063 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1064 Inst.addOperand(MCOperand::CreateImm(shift)); 1065 1066 return true; 1067 } 1068 1069 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1070 uint64_t Address, const void *Decoder) { 1071 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1072 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1073 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1074 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1075 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1076 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1077 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1078 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1079 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1080 1081 bool writeback = (W == 1) | (P == 0); 1082 if (writeback) { // Writeback 1083 if (P) 1084 U |= ARMII::IndexModePre << 9; 1085 else 1086 U |= ARMII::IndexModePost << 9; 1087 1088 // On stores, the writeback operand precedes Rt. 1089 switch (Inst.getOpcode()) { 1090 case ARM::STRD: 1091 case ARM::STRD_PRE: 1092 case ARM::STRD_POST: 1093 case ARM::STRH: 1094 case ARM::STRH_PRE: 1095 case ARM::STRH_POST: 1096 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1097 return false; 1098 break; 1099 default: 1100 break; 1101 } 1102 } 1103 1104 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1105 return false; 1106 switch (Inst.getOpcode()) { 1107 case ARM::STRD: 1108 case ARM::STRD_PRE: 1109 case ARM::STRD_POST: 1110 case ARM::LDRD: 1111 case ARM::LDRD_PRE: 1112 case ARM::LDRD_POST: 1113 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1114 return false; 1115 break; 1116 default: 1117 break; 1118 } 1119 1120 if (writeback) { 1121 // On loads, the writeback operand comes after Rt. 1122 switch (Inst.getOpcode()) { 1123 case ARM::LDRD: 1124 case ARM::LDRD_PRE: 1125 case ARM::LDRD_POST: 1126 case ARM::LDRHTr: 1127 case ARM::LDRSBTr: 1128 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1129 return false; 1130 break; 1131 default: 1132 break; 1133 } 1134 } 1135 1136 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1137 return false; 1138 1139 if (type) { 1140 Inst.addOperand(MCOperand::CreateReg(0)); 1141 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1142 } else { 1143 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1144 return false; 1145 Inst.addOperand(MCOperand::CreateImm(U)); 1146 } 1147 1148 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1149 1150 return true; 1151 } 1152 1153 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1154 uint64_t Address, const void *Decoder) { 1155 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1156 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1157 1158 switch (mode) { 1159 case 0: 1160 mode = ARM_AM::da; 1161 break; 1162 case 1: 1163 mode = ARM_AM::ia; 1164 break; 1165 case 2: 1166 mode = ARM_AM::db; 1167 break; 1168 case 3: 1169 mode = ARM_AM::ib; 1170 break; 1171 } 1172 1173 Inst.addOperand(MCOperand::CreateImm(mode)); 1174 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1175 1176 return true; 1177 } 1178 1179 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1180 unsigned Insn, 1181 uint64_t Address, const void *Decoder) { 1182 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1183 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1184 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1185 1186 if (pred == 0xF) { 1187 switch (Inst.getOpcode()) { 1188 case ARM::STMDA: 1189 Inst.setOpcode(ARM::RFEDA); 1190 break; 1191 case ARM::STMDA_UPD: 1192 Inst.setOpcode(ARM::RFEDA_UPD); 1193 break; 1194 case ARM::STMDB: 1195 Inst.setOpcode(ARM::RFEDB); 1196 break; 1197 case ARM::STMDB_UPD: 1198 Inst.setOpcode(ARM::RFEDB_UPD); 1199 break; 1200 case ARM::STMIA: 1201 Inst.setOpcode(ARM::RFEIA); 1202 break; 1203 case ARM::STMIA_UPD: 1204 Inst.setOpcode(ARM::RFEIA_UPD); 1205 break; 1206 case ARM::STMIB: 1207 Inst.setOpcode(ARM::RFEIB); 1208 break; 1209 case ARM::STMIB_UPD: 1210 Inst.setOpcode(ARM::RFEIB_UPD); 1211 break; 1212 } 1213 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1214 } 1215 1216 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1217 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1218 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1219 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1220 return false; 1221 1222 return true; 1223 } 1224 1225 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1226 uint64_t Address, const void *Decoder) { 1227 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1228 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1229 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1230 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1231 1232 // imod == '01' --> UNPREDICTABLE 1233 if (imod == 1) return false; 1234 1235 if (M && mode && imod && iflags) { 1236 Inst.setOpcode(ARM::CPS3p); 1237 Inst.addOperand(MCOperand::CreateImm(imod)); 1238 Inst.addOperand(MCOperand::CreateImm(iflags)); 1239 Inst.addOperand(MCOperand::CreateImm(mode)); 1240 return true; 1241 } else if (!mode && !M) { 1242 Inst.setOpcode(ARM::CPS2p); 1243 Inst.addOperand(MCOperand::CreateImm(imod)); 1244 Inst.addOperand(MCOperand::CreateImm(iflags)); 1245 return true; 1246 } else if (!imod && !iflags && M) { 1247 Inst.setOpcode(ARM::CPS1p); 1248 Inst.addOperand(MCOperand::CreateImm(mode)); 1249 return true; 1250 } 1251 1252 return false; 1253 } 1254 1255 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1256 uint64_t Address, const void *Decoder) { 1257 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1258 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1259 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1260 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1261 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1262 1263 if (pred == 0xF) 1264 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1265 1266 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1267 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1268 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1269 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1270 return false; 1271 1272 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1273 1274 return true; 1275 } 1276 1277 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1278 uint64_t Address, const void *Decoder) { 1279 unsigned add = fieldFromInstruction32(Val, 12, 1); 1280 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1281 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1282 1283 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1284 return false; 1285 1286 if (!add) imm *= -1; 1287 if (imm == 0 && !add) imm = INT32_MIN; 1288 Inst.addOperand(MCOperand::CreateImm(imm)); 1289 1290 return true; 1291 } 1292 1293 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1294 uint64_t Address, const void *Decoder) { 1295 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1296 unsigned U = fieldFromInstruction32(Val, 8, 1); 1297 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1298 1299 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1300 return false; 1301 1302 if (U) 1303 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1304 else 1305 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1306 1307 return true; 1308 } 1309 1310 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1311 uint64_t Address, const void *Decoder) { 1312 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1313 } 1314 1315 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1316 uint64_t Address, const void *Decoder) { 1317 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1318 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1319 1320 if (pred == 0xF) { 1321 Inst.setOpcode(ARM::BLXi); 1322 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1323 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1324 return true; 1325 } 1326 1327 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1328 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1329 1330 return true; 1331 } 1332 1333 1334 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1335 uint64_t Address, const void *Decoder) { 1336 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1337 return true; 1338 } 1339 1340 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1341 uint64_t Address, const void *Decoder) { 1342 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1343 unsigned align = fieldFromInstruction32(Val, 4, 2); 1344 1345 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1346 return false; 1347 if (!align) 1348 Inst.addOperand(MCOperand::CreateImm(0)); 1349 else 1350 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1351 1352 return true; 1353 } 1354 1355 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1356 uint64_t Address, const void *Decoder) { 1357 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1358 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1359 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1360 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1361 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1362 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1363 1364 // First output register 1365 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1366 1367 // Second output register 1368 switch (Inst.getOpcode()) { 1369 case ARM::VLD1q8: 1370 case ARM::VLD1q16: 1371 case ARM::VLD1q32: 1372 case ARM::VLD1q64: 1373 case ARM::VLD1q8_UPD: 1374 case ARM::VLD1q16_UPD: 1375 case ARM::VLD1q32_UPD: 1376 case ARM::VLD1q64_UPD: 1377 case ARM::VLD1d8T: 1378 case ARM::VLD1d16T: 1379 case ARM::VLD1d32T: 1380 case ARM::VLD1d64T: 1381 case ARM::VLD1d8T_UPD: 1382 case ARM::VLD1d16T_UPD: 1383 case ARM::VLD1d32T_UPD: 1384 case ARM::VLD1d64T_UPD: 1385 case ARM::VLD1d8Q: 1386 case ARM::VLD1d16Q: 1387 case ARM::VLD1d32Q: 1388 case ARM::VLD1d64Q: 1389 case ARM::VLD1d8Q_UPD: 1390 case ARM::VLD1d16Q_UPD: 1391 case ARM::VLD1d32Q_UPD: 1392 case ARM::VLD1d64Q_UPD: 1393 case ARM::VLD2d8: 1394 case ARM::VLD2d16: 1395 case ARM::VLD2d32: 1396 case ARM::VLD2d8_UPD: 1397 case ARM::VLD2d16_UPD: 1398 case ARM::VLD2d32_UPD: 1399 case ARM::VLD2q8: 1400 case ARM::VLD2q16: 1401 case ARM::VLD2q32: 1402 case ARM::VLD2q8_UPD: 1403 case ARM::VLD2q16_UPD: 1404 case ARM::VLD2q32_UPD: 1405 case ARM::VLD3d8: 1406 case ARM::VLD3d16: 1407 case ARM::VLD3d32: 1408 case ARM::VLD3d8_UPD: 1409 case ARM::VLD3d16_UPD: 1410 case ARM::VLD3d32_UPD: 1411 case ARM::VLD4d8: 1412 case ARM::VLD4d16: 1413 case ARM::VLD4d32: 1414 case ARM::VLD4d8_UPD: 1415 case ARM::VLD4d16_UPD: 1416 case ARM::VLD4d32_UPD: 1417 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1418 break; 1419 case ARM::VLD2b8: 1420 case ARM::VLD2b16: 1421 case ARM::VLD2b32: 1422 case ARM::VLD2b8_UPD: 1423 case ARM::VLD2b16_UPD: 1424 case ARM::VLD2b32_UPD: 1425 case ARM::VLD3q8: 1426 case ARM::VLD3q16: 1427 case ARM::VLD3q32: 1428 case ARM::VLD3q8_UPD: 1429 case ARM::VLD3q16_UPD: 1430 case ARM::VLD3q32_UPD: 1431 case ARM::VLD4q8: 1432 case ARM::VLD4q16: 1433 case ARM::VLD4q32: 1434 case ARM::VLD4q8_UPD: 1435 case ARM::VLD4q16_UPD: 1436 case ARM::VLD4q32_UPD: 1437 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1438 default: 1439 break; 1440 } 1441 1442 // Third output register 1443 switch(Inst.getOpcode()) { 1444 case ARM::VLD1d8T: 1445 case ARM::VLD1d16T: 1446 case ARM::VLD1d32T: 1447 case ARM::VLD1d64T: 1448 case ARM::VLD1d8T_UPD: 1449 case ARM::VLD1d16T_UPD: 1450 case ARM::VLD1d32T_UPD: 1451 case ARM::VLD1d64T_UPD: 1452 case ARM::VLD1d8Q: 1453 case ARM::VLD1d16Q: 1454 case ARM::VLD1d32Q: 1455 case ARM::VLD1d64Q: 1456 case ARM::VLD1d8Q_UPD: 1457 case ARM::VLD1d16Q_UPD: 1458 case ARM::VLD1d32Q_UPD: 1459 case ARM::VLD1d64Q_UPD: 1460 case ARM::VLD2q8: 1461 case ARM::VLD2q16: 1462 case ARM::VLD2q32: 1463 case ARM::VLD2q8_UPD: 1464 case ARM::VLD2q16_UPD: 1465 case ARM::VLD2q32_UPD: 1466 case ARM::VLD3d8: 1467 case ARM::VLD3d16: 1468 case ARM::VLD3d32: 1469 case ARM::VLD3d8_UPD: 1470 case ARM::VLD3d16_UPD: 1471 case ARM::VLD3d32_UPD: 1472 case ARM::VLD4d8: 1473 case ARM::VLD4d16: 1474 case ARM::VLD4d32: 1475 case ARM::VLD4d8_UPD: 1476 case ARM::VLD4d16_UPD: 1477 case ARM::VLD4d32_UPD: 1478 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1479 break; 1480 case ARM::VLD3q8: 1481 case ARM::VLD3q16: 1482 case ARM::VLD3q32: 1483 case ARM::VLD3q8_UPD: 1484 case ARM::VLD3q16_UPD: 1485 case ARM::VLD3q32_UPD: 1486 case ARM::VLD4q8: 1487 case ARM::VLD4q16: 1488 case ARM::VLD4q32: 1489 case ARM::VLD4q8_UPD: 1490 case ARM::VLD4q16_UPD: 1491 case ARM::VLD4q32_UPD: 1492 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1493 break; 1494 default: 1495 break; 1496 } 1497 1498 // Fourth output register 1499 switch (Inst.getOpcode()) { 1500 case ARM::VLD1d8Q: 1501 case ARM::VLD1d16Q: 1502 case ARM::VLD1d32Q: 1503 case ARM::VLD1d64Q: 1504 case ARM::VLD1d8Q_UPD: 1505 case ARM::VLD1d16Q_UPD: 1506 case ARM::VLD1d32Q_UPD: 1507 case ARM::VLD1d64Q_UPD: 1508 case ARM::VLD2q8: 1509 case ARM::VLD2q16: 1510 case ARM::VLD2q32: 1511 case ARM::VLD2q8_UPD: 1512 case ARM::VLD2q16_UPD: 1513 case ARM::VLD2q32_UPD: 1514 case ARM::VLD4d8: 1515 case ARM::VLD4d16: 1516 case ARM::VLD4d32: 1517 case ARM::VLD4d8_UPD: 1518 case ARM::VLD4d16_UPD: 1519 case ARM::VLD4d32_UPD: 1520 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1521 break; 1522 case ARM::VLD4q8: 1523 case ARM::VLD4q16: 1524 case ARM::VLD4q32: 1525 case ARM::VLD4q8_UPD: 1526 case ARM::VLD4q16_UPD: 1527 case ARM::VLD4q32_UPD: 1528 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1529 break; 1530 default: 1531 break; 1532 } 1533 1534 // Writeback operand 1535 switch (Inst.getOpcode()) { 1536 case ARM::VLD1d8_UPD: 1537 case ARM::VLD1d16_UPD: 1538 case ARM::VLD1d32_UPD: 1539 case ARM::VLD1d64_UPD: 1540 case ARM::VLD1q8_UPD: 1541 case ARM::VLD1q16_UPD: 1542 case ARM::VLD1q32_UPD: 1543 case ARM::VLD1q64_UPD: 1544 case ARM::VLD1d8T_UPD: 1545 case ARM::VLD1d16T_UPD: 1546 case ARM::VLD1d32T_UPD: 1547 case ARM::VLD1d64T_UPD: 1548 case ARM::VLD1d8Q_UPD: 1549 case ARM::VLD1d16Q_UPD: 1550 case ARM::VLD1d32Q_UPD: 1551 case ARM::VLD1d64Q_UPD: 1552 case ARM::VLD2d8_UPD: 1553 case ARM::VLD2d16_UPD: 1554 case ARM::VLD2d32_UPD: 1555 case ARM::VLD2q8_UPD: 1556 case ARM::VLD2q16_UPD: 1557 case ARM::VLD2q32_UPD: 1558 case ARM::VLD2b8_UPD: 1559 case ARM::VLD2b16_UPD: 1560 case ARM::VLD2b32_UPD: 1561 case ARM::VLD3d8_UPD: 1562 case ARM::VLD3d16_UPD: 1563 case ARM::VLD3d32_UPD: 1564 case ARM::VLD3q8_UPD: 1565 case ARM::VLD3q16_UPD: 1566 case ARM::VLD3q32_UPD: 1567 case ARM::VLD4d8_UPD: 1568 case ARM::VLD4d16_UPD: 1569 case ARM::VLD4d32_UPD: 1570 case ARM::VLD4q8_UPD: 1571 case ARM::VLD4q16_UPD: 1572 case ARM::VLD4q32_UPD: 1573 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1574 break; 1575 default: 1576 break; 1577 } 1578 1579 // AddrMode6 Base (register+alignment) 1580 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1581 1582 // AddrMode6 Offset (register) 1583 if (Rm == 0xD) 1584 Inst.addOperand(MCOperand::CreateReg(0)); 1585 else if (Rm != 0xF) { 1586 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1587 return false; 1588 } 1589 1590 return true; 1591 } 1592 1593 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1594 uint64_t Address, const void *Decoder) { 1595 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1596 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1597 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1598 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1599 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1600 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1601 1602 // Writeback Operand 1603 switch (Inst.getOpcode()) { 1604 case ARM::VST1d8_UPD: 1605 case ARM::VST1d16_UPD: 1606 case ARM::VST1d32_UPD: 1607 case ARM::VST1d64_UPD: 1608 case ARM::VST1q8_UPD: 1609 case ARM::VST1q16_UPD: 1610 case ARM::VST1q32_UPD: 1611 case ARM::VST1q64_UPD: 1612 case ARM::VST1d8T_UPD: 1613 case ARM::VST1d16T_UPD: 1614 case ARM::VST1d32T_UPD: 1615 case ARM::VST1d64T_UPD: 1616 case ARM::VST1d8Q_UPD: 1617 case ARM::VST1d16Q_UPD: 1618 case ARM::VST1d32Q_UPD: 1619 case ARM::VST1d64Q_UPD: 1620 case ARM::VST2d8_UPD: 1621 case ARM::VST2d16_UPD: 1622 case ARM::VST2d32_UPD: 1623 case ARM::VST2q8_UPD: 1624 case ARM::VST2q16_UPD: 1625 case ARM::VST2q32_UPD: 1626 case ARM::VST2b8_UPD: 1627 case ARM::VST2b16_UPD: 1628 case ARM::VST2b32_UPD: 1629 case ARM::VST3d8_UPD: 1630 case ARM::VST3d16_UPD: 1631 case ARM::VST3d32_UPD: 1632 case ARM::VST3q8_UPD: 1633 case ARM::VST3q16_UPD: 1634 case ARM::VST3q32_UPD: 1635 case ARM::VST4d8_UPD: 1636 case ARM::VST4d16_UPD: 1637 case ARM::VST4d32_UPD: 1638 case ARM::VST4q8_UPD: 1639 case ARM::VST4q16_UPD: 1640 case ARM::VST4q32_UPD: 1641 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1642 return false; 1643 break; 1644 default: 1645 break; 1646 } 1647 1648 // AddrMode6 Base (register+alignment) 1649 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1650 1651 // AddrMode6 Offset (register) 1652 if (Rm == 0xD) 1653 Inst.addOperand(MCOperand::CreateReg(0)); 1654 else if (Rm != 0xF) { 1655 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1656 } 1657 1658 // First input register 1659 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1660 1661 // Second input register 1662 switch (Inst.getOpcode()) { 1663 case ARM::VST1q8: 1664 case ARM::VST1q16: 1665 case ARM::VST1q32: 1666 case ARM::VST1q64: 1667 case ARM::VST1q8_UPD: 1668 case ARM::VST1q16_UPD: 1669 case ARM::VST1q32_UPD: 1670 case ARM::VST1q64_UPD: 1671 case ARM::VST1d8T: 1672 case ARM::VST1d16T: 1673 case ARM::VST1d32T: 1674 case ARM::VST1d64T: 1675 case ARM::VST1d8T_UPD: 1676 case ARM::VST1d16T_UPD: 1677 case ARM::VST1d32T_UPD: 1678 case ARM::VST1d64T_UPD: 1679 case ARM::VST1d8Q: 1680 case ARM::VST1d16Q: 1681 case ARM::VST1d32Q: 1682 case ARM::VST1d64Q: 1683 case ARM::VST1d8Q_UPD: 1684 case ARM::VST1d16Q_UPD: 1685 case ARM::VST1d32Q_UPD: 1686 case ARM::VST1d64Q_UPD: 1687 case ARM::VST2d8: 1688 case ARM::VST2d16: 1689 case ARM::VST2d32: 1690 case ARM::VST2d8_UPD: 1691 case ARM::VST2d16_UPD: 1692 case ARM::VST2d32_UPD: 1693 case ARM::VST2q8: 1694 case ARM::VST2q16: 1695 case ARM::VST2q32: 1696 case ARM::VST2q8_UPD: 1697 case ARM::VST2q16_UPD: 1698 case ARM::VST2q32_UPD: 1699 case ARM::VST3d8: 1700 case ARM::VST3d16: 1701 case ARM::VST3d32: 1702 case ARM::VST3d8_UPD: 1703 case ARM::VST3d16_UPD: 1704 case ARM::VST3d32_UPD: 1705 case ARM::VST4d8: 1706 case ARM::VST4d16: 1707 case ARM::VST4d32: 1708 case ARM::VST4d8_UPD: 1709 case ARM::VST4d16_UPD: 1710 case ARM::VST4d32_UPD: 1711 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1712 break; 1713 case ARM::VST2b8: 1714 case ARM::VST2b16: 1715 case ARM::VST2b32: 1716 case ARM::VST2b8_UPD: 1717 case ARM::VST2b16_UPD: 1718 case ARM::VST2b32_UPD: 1719 case ARM::VST3q8: 1720 case ARM::VST3q16: 1721 case ARM::VST3q32: 1722 case ARM::VST3q8_UPD: 1723 case ARM::VST3q16_UPD: 1724 case ARM::VST3q32_UPD: 1725 case ARM::VST4q8: 1726 case ARM::VST4q16: 1727 case ARM::VST4q32: 1728 case ARM::VST4q8_UPD: 1729 case ARM::VST4q16_UPD: 1730 case ARM::VST4q32_UPD: 1731 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1732 break; 1733 default: 1734 break; 1735 } 1736 1737 // Third input register 1738 switch (Inst.getOpcode()) { 1739 case ARM::VST1d8T: 1740 case ARM::VST1d16T: 1741 case ARM::VST1d32T: 1742 case ARM::VST1d64T: 1743 case ARM::VST1d8T_UPD: 1744 case ARM::VST1d16T_UPD: 1745 case ARM::VST1d32T_UPD: 1746 case ARM::VST1d64T_UPD: 1747 case ARM::VST1d8Q: 1748 case ARM::VST1d16Q: 1749 case ARM::VST1d32Q: 1750 case ARM::VST1d64Q: 1751 case ARM::VST1d8Q_UPD: 1752 case ARM::VST1d16Q_UPD: 1753 case ARM::VST1d32Q_UPD: 1754 case ARM::VST1d64Q_UPD: 1755 case ARM::VST2q8: 1756 case ARM::VST2q16: 1757 case ARM::VST2q32: 1758 case ARM::VST2q8_UPD: 1759 case ARM::VST2q16_UPD: 1760 case ARM::VST2q32_UPD: 1761 case ARM::VST3d8: 1762 case ARM::VST3d16: 1763 case ARM::VST3d32: 1764 case ARM::VST3d8_UPD: 1765 case ARM::VST3d16_UPD: 1766 case ARM::VST3d32_UPD: 1767 case ARM::VST4d8: 1768 case ARM::VST4d16: 1769 case ARM::VST4d32: 1770 case ARM::VST4d8_UPD: 1771 case ARM::VST4d16_UPD: 1772 case ARM::VST4d32_UPD: 1773 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1774 break; 1775 case ARM::VST3q8: 1776 case ARM::VST3q16: 1777 case ARM::VST3q32: 1778 case ARM::VST3q8_UPD: 1779 case ARM::VST3q16_UPD: 1780 case ARM::VST3q32_UPD: 1781 case ARM::VST4q8: 1782 case ARM::VST4q16: 1783 case ARM::VST4q32: 1784 case ARM::VST4q8_UPD: 1785 case ARM::VST4q16_UPD: 1786 case ARM::VST4q32_UPD: 1787 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1788 break; 1789 default: 1790 break; 1791 } 1792 1793 // Fourth input register 1794 switch (Inst.getOpcode()) { 1795 case ARM::VST1d8Q: 1796 case ARM::VST1d16Q: 1797 case ARM::VST1d32Q: 1798 case ARM::VST1d64Q: 1799 case ARM::VST1d8Q_UPD: 1800 case ARM::VST1d16Q_UPD: 1801 case ARM::VST1d32Q_UPD: 1802 case ARM::VST1d64Q_UPD: 1803 case ARM::VST2q8: 1804 case ARM::VST2q16: 1805 case ARM::VST2q32: 1806 case ARM::VST2q8_UPD: 1807 case ARM::VST2q16_UPD: 1808 case ARM::VST2q32_UPD: 1809 case ARM::VST4d8: 1810 case ARM::VST4d16: 1811 case ARM::VST4d32: 1812 case ARM::VST4d8_UPD: 1813 case ARM::VST4d16_UPD: 1814 case ARM::VST4d32_UPD: 1815 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1816 break; 1817 case ARM::VST4q8: 1818 case ARM::VST4q16: 1819 case ARM::VST4q32: 1820 case ARM::VST4q8_UPD: 1821 case ARM::VST4q16_UPD: 1822 case ARM::VST4q32_UPD: 1823 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1824 break; 1825 default: 1826 break; 1827 } 1828 1829 return true; 1830 } 1831 1832 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1833 uint64_t Address, const void *Decoder) { 1834 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1835 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1836 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1837 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1838 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1839 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1840 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1841 1842 align *= (1 << size); 1843 1844 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1845 if (regs == 2) { 1846 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1847 } 1848 if (Rm == 0xD) { 1849 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1850 } 1851 1852 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1853 Inst.addOperand(MCOperand::CreateImm(align)); 1854 1855 if (Rm == 0xD) 1856 Inst.addOperand(MCOperand::CreateReg(0)); 1857 else if (Rm != 0xF) { 1858 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1859 } 1860 1861 return true; 1862 } 1863 1864 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1865 uint64_t Address, const void *Decoder) { 1866 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1867 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1868 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1869 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1870 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1871 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1872 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1873 align *= 2*size; 1874 1875 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1876 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1877 if (Rm == 0xD) { 1878 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1879 } 1880 1881 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1882 Inst.addOperand(MCOperand::CreateImm(align)); 1883 1884 if (Rm == 0xD) 1885 Inst.addOperand(MCOperand::CreateReg(0)); 1886 else if (Rm != 0xF) { 1887 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1888 } 1889 1890 return true; 1891 } 1892 1893 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1894 uint64_t Address, const void *Decoder) { 1895 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1896 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1897 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1898 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1899 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1900 1901 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1902 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1903 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1904 return false; 1905 if (Rm == 0xD) { 1906 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1907 } 1908 1909 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1910 Inst.addOperand(MCOperand::CreateImm(0)); 1911 1912 if (Rm == 0xD) 1913 Inst.addOperand(MCOperand::CreateReg(0)); 1914 else if (Rm != 0xF) { 1915 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1916 } 1917 1918 return true; 1919 } 1920 1921 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1922 uint64_t Address, const void *Decoder) { 1923 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1924 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1925 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1926 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1927 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1928 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1929 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1930 1931 if (size == 0x3) { 1932 size = 4; 1933 align = 16; 1934 } else { 1935 if (size == 2) { 1936 size = 1 << size; 1937 align *= 8; 1938 } else { 1939 size = 1 << size; 1940 align *= 4*size; 1941 } 1942 } 1943 1944 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1945 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1946 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1947 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 1948 return false; 1949 if (Rm == 0xD) { 1950 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1951 } 1952 1953 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1954 Inst.addOperand(MCOperand::CreateImm(align)); 1955 1956 if (Rm == 0xD) 1957 Inst.addOperand(MCOperand::CreateReg(0)); 1958 else if (Rm != 0xF) { 1959 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1960 } 1961 1962 return true; 1963 } 1964 1965 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1966 uint64_t Address, const void *Decoder) { 1967 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1968 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1969 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1970 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1971 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1972 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1973 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1974 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1975 1976 if (Q) { 1977 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1978 } else { 1979 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1980 } 1981 1982 Inst.addOperand(MCOperand::CreateImm(imm)); 1983 1984 switch (Inst.getOpcode()) { 1985 case ARM::VORRiv4i16: 1986 case ARM::VORRiv2i32: 1987 case ARM::VBICiv4i16: 1988 case ARM::VBICiv2i32: 1989 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1990 break; 1991 case ARM::VORRiv8i16: 1992 case ARM::VORRiv4i32: 1993 case ARM::VBICiv8i16: 1994 case ARM::VBICiv4i32: 1995 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1996 break; 1997 default: 1998 break; 1999 } 2000 2001 return true; 2002 } 2003 2004 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2005 uint64_t Address, const void *Decoder) { 2006 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2007 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2008 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2009 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2010 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2011 2012 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2013 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2014 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2015 2016 return true; 2017 } 2018 2019 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2020 uint64_t Address, const void *Decoder) { 2021 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2022 return true; 2023 } 2024 2025 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2026 uint64_t Address, const void *Decoder) { 2027 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2028 return true; 2029 } 2030 2031 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2032 uint64_t Address, const void *Decoder) { 2033 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2034 return true; 2035 } 2036 2037 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2038 uint64_t Address, const void *Decoder) { 2039 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2040 return true; 2041 } 2042 2043 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2044 uint64_t Address, const void *Decoder) { 2045 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2046 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2047 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2048 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2049 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2050 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2051 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2052 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2053 2054 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2055 if (op) { 2056 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2057 } 2058 2059 for (unsigned i = 0; i < length; ++i) { 2060 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2061 } 2062 2063 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2064 2065 return true; 2066 } 2067 2068 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2069 uint64_t Address, const void *Decoder) { 2070 // The immediate needs to be a fully instantiated float. However, the 2071 // auto-generated decoder is only able to fill in some of the bits 2072 // necessary. For instance, the 'b' bit is replicated multiple times, 2073 // and is even present in inverted form in one bit. We do a little 2074 // binary parsing here to fill in those missing bits, and then 2075 // reinterpret it all as a float. 2076 union { 2077 uint32_t integer; 2078 float fp; 2079 } fp_conv; 2080 2081 fp_conv.integer = Val; 2082 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2083 fp_conv.integer |= b << 26; 2084 fp_conv.integer |= b << 27; 2085 fp_conv.integer |= b << 28; 2086 fp_conv.integer |= b << 29; 2087 fp_conv.integer |= (~b & 0x1) << 30; 2088 2089 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2090 return true; 2091 } 2092 2093 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2094 uint64_t Address, const void *Decoder) { 2095 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2096 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2097 2098 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2099 2100 if (Inst.getOpcode() == ARM::tADR) 2101 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2102 else if (Inst.getOpcode() == ARM::tADDrSPi) 2103 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2104 else 2105 return false; 2106 2107 Inst.addOperand(MCOperand::CreateImm(imm)); 2108 return true; 2109 } 2110 2111 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2112 uint64_t Address, const void *Decoder) { 2113 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2114 return true; 2115 } 2116 2117 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2118 uint64_t Address, const void *Decoder) { 2119 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2120 return true; 2121 } 2122 2123 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2124 uint64_t Address, const void *Decoder) { 2125 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2126 return true; 2127 } 2128 2129 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2130 uint64_t Address, const void *Decoder) { 2131 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2132 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2133 2134 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2135 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2136 return false; 2137 2138 return true; 2139 } 2140 2141 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2142 uint64_t Address, const void *Decoder) { 2143 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2144 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2145 2146 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2147 Inst.addOperand(MCOperand::CreateImm(imm)); 2148 2149 return true; 2150 } 2151 2152 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2153 uint64_t Address, const void *Decoder) { 2154 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2155 2156 return true; 2157 } 2158 2159 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2160 uint64_t Address, const void *Decoder) { 2161 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2162 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2163 2164 return true; 2165 } 2166 2167 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2168 uint64_t Address, const void *Decoder) { 2169 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2170 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2171 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2172 2173 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2174 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2175 return false; 2176 Inst.addOperand(MCOperand::CreateImm(imm)); 2177 2178 return true; 2179 } 2180 2181 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2182 uint64_t Address, const void *Decoder) { 2183 if (Inst.getOpcode() != ARM::t2PLDs) { 2184 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2185 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2186 } 2187 2188 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2189 if (Rn == 0xF) { 2190 switch (Inst.getOpcode()) { 2191 case ARM::t2LDRBs: 2192 Inst.setOpcode(ARM::t2LDRBpci); 2193 break; 2194 case ARM::t2LDRHs: 2195 Inst.setOpcode(ARM::t2LDRHpci); 2196 break; 2197 case ARM::t2LDRSHs: 2198 Inst.setOpcode(ARM::t2LDRSHpci); 2199 break; 2200 case ARM::t2LDRSBs: 2201 Inst.setOpcode(ARM::t2LDRSBpci); 2202 break; 2203 case ARM::t2PLDs: 2204 Inst.setOpcode(ARM::t2PLDi12); 2205 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2206 break; 2207 default: 2208 return false; 2209 } 2210 2211 int imm = fieldFromInstruction32(Insn, 0, 12); 2212 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2213 Inst.addOperand(MCOperand::CreateImm(imm)); 2214 2215 return true; 2216 } 2217 2218 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2219 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2220 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2221 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2222 2223 return true; 2224 } 2225 2226 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2227 uint64_t Address, const void *Decoder) { 2228 int imm = Val & 0xFF; 2229 if (!(Val & 0x100)) imm *= -1; 2230 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2231 2232 return true; 2233 } 2234 2235 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2236 uint64_t Address, const void *Decoder) { 2237 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2238 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2239 2240 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2241 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2242 return false; 2243 2244 return true; 2245 } 2246 2247 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2248 uint64_t Address, const void *Decoder) { 2249 int imm = Val & 0xFF; 2250 if (!(Val & 0x100)) imm *= -1; 2251 Inst.addOperand(MCOperand::CreateImm(imm)); 2252 2253 return true; 2254 } 2255 2256 2257 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2258 uint64_t Address, const void *Decoder) { 2259 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2260 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2261 2262 // Some instructions always use an additive offset. 2263 switch (Inst.getOpcode()) { 2264 case ARM::t2LDRT: 2265 case ARM::t2LDRBT: 2266 case ARM::t2LDRHT: 2267 case ARM::t2LDRSBT: 2268 case ARM::t2LDRSHT: 2269 imm |= 0x100; 2270 break; 2271 default: 2272 break; 2273 } 2274 2275 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2276 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2277 return false; 2278 2279 return true; 2280 } 2281 2282 2283 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2284 uint64_t Address, const void *Decoder) { 2285 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2286 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2287 2288 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2289 Inst.addOperand(MCOperand::CreateImm(imm)); 2290 2291 return true; 2292 } 2293 2294 2295 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2296 uint64_t Address, const void *Decoder) { 2297 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2298 2299 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2300 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2301 Inst.addOperand(MCOperand::CreateImm(imm)); 2302 2303 return true; 2304 } 2305 2306 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2307 uint64_t Address, const void *Decoder) { 2308 if (Inst.getOpcode() == ARM::tADDrSP) { 2309 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2310 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2311 2312 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2313 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2314 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2315 } else if (Inst.getOpcode() == ARM::tADDspr) { 2316 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2317 2318 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2319 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2320 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2321 } 2322 2323 return true; 2324 } 2325 2326 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2327 uint64_t Address, const void *Decoder) { 2328 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2329 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2330 2331 Inst.addOperand(MCOperand::CreateImm(imod)); 2332 Inst.addOperand(MCOperand::CreateImm(flags)); 2333 2334 return true; 2335 } 2336 2337 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2338 uint64_t Address, const void *Decoder) { 2339 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2340 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2341 2342 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2343 Inst.addOperand(MCOperand::CreateImm(add)); 2344 2345 return true; 2346 } 2347 2348 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2349 uint64_t Address, const void *Decoder) { 2350 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2351 return true; 2352 } 2353 2354 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2355 uint64_t Address, const void *Decoder) { 2356 if (Val == 0xA || Val == 0xB) 2357 return false; 2358 2359 Inst.addOperand(MCOperand::CreateImm(Val)); 2360 return true; 2361 } 2362 2363 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2364 uint64_t Address, const void *Decoder) { 2365 if (Val == 0) 2366 Inst.addOperand(MCOperand::CreateImm(32)); 2367 else 2368 Inst.addOperand(MCOperand::CreateImm(Val)); 2369 return true; 2370 } 2371 2372 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2373 uint64_t Address, const void *Decoder) { 2374 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2375 if (pred == 0xE || pred == 0xF) { 2376 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2377 switch (opc) { 2378 default: 2379 return false; 2380 case 0: 2381 Inst.setOpcode(ARM::t2DSB); 2382 break; 2383 case 1: 2384 Inst.setOpcode(ARM::t2DMB); 2385 break; 2386 case 2: 2387 Inst.setOpcode(ARM::t2ISB); 2388 return true; 2389 } 2390 2391 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2392 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2393 } 2394 2395 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2396 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2397 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2398 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2399 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2400 2401 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2402 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2403 return false; 2404 2405 return true; 2406 } 2407 2408 // Decode a shifted immediate operand. These basically consist 2409 // of an 8-bit value, and a 4-bit directive that specifies either 2410 // a splat operation or a rotation. 2411 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2412 uint64_t Address, const void *Decoder) { 2413 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2414 if (ctrl == 0) { 2415 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2416 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2417 switch (byte) { 2418 case 0: 2419 Inst.addOperand(MCOperand::CreateImm(imm)); 2420 break; 2421 case 1: 2422 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2423 break; 2424 case 2: 2425 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2426 break; 2427 case 3: 2428 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2429 (imm << 8) | imm)); 2430 break; 2431 } 2432 } else { 2433 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2434 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2435 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2436 Inst.addOperand(MCOperand::CreateImm(imm)); 2437 } 2438 2439 return true; 2440 } 2441 2442 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2443 uint64_t Address, const void *Decoder){ 2444 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2445 return true; 2446 } 2447 2448 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2449 uint64_t Address, const void *Decoder){ 2450 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2451 return true; 2452 } 2453 2454 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, 2455 uint64_t Address, const void *Decoder) { 2456 bool isImm = fieldFromInstruction32(Val, 9, 1); 2457 bool isAdd = fieldFromInstruction32(Val, 8, 1); 2458 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2459 2460 if (!isImm) { 2461 if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false; 2462 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); 2463 } else { 2464 Inst.addOperand(MCOperand::CreateReg(0)); 2465 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); 2466 } 2467 2468 return true; 2469 } 2470 2471 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2472 uint64_t Address, const void *Decoder) { 2473 switch (Val) { 2474 default: 2475 return false; 2476 case 0xF: // SY 2477 case 0xE: // ST 2478 case 0xB: // ISH 2479 case 0xA: // ISHST 2480 case 0x7: // NSH 2481 case 0x6: // NSHST 2482 case 0x3: // OSH 2483 case 0x2: // OSHST 2484 break; 2485 } 2486 2487 Inst.addOperand(MCOperand::CreateImm(Val)); 2488 return true; 2489 } 2490 2491 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2492 uint64_t Address, const void *Decoder) { 2493 if (!Val) return false; 2494 Inst.addOperand(MCOperand::CreateImm(Val)); 2495 return true; 2496 } 2497 2498 static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2499 uint64_t Address, const void *Decoder) { 2500 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2501 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2502 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2503 2504 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2505 2506 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2507 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2508 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2509 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2510 2511 return true; 2512 } 2513 2514 2515 static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2516 uint64_t Address, const void *Decoder) { 2517 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2518 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2519 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2520 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2521 2522 if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2523 2524 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2525 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; 2526 2527 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2528 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2529 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2530 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2531 2532 return true; 2533 } 2534 2535 static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2536 uint64_t Address, const void *Decoder) { 2537 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2538 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2539 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2540 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2541 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2542 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2543 2544 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2545 2546 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2547 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2548 if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false; 2549 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2550 2551 return true; 2552 } 2553 2554 static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2555 uint64_t Address, const void *Decoder) { 2556 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2557 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2558 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2559 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2560 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2561 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2562 2563 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2564 2565 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2566 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2567 if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false; 2568 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2569 2570 return true; 2571 } 2572