1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARM.h" 13 #include "ARMSubtarget.h" 14 #include "MCTargetDesc/ARMAddressingModes.h" 15 #include "MCTargetDesc/ARMMCExpr.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCExpr.h" 21 #include "llvm/MC/MCContext.h" 22 #include "llvm/MC/MCDisassembler.h" 23 #include "llvm/Support/Debug.h" 24 #include "llvm/Support/MemoryObject.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 using namespace llvm; 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 /// ARMDisassembler - ARM disassembler for all ARM platforms. 35 class ARMDisassembler : public MCDisassembler { 36 public: 37 /// Constructor - Initializes the disassembler. 38 /// 39 ARMDisassembler(const MCSubtargetInfo &STI) : 40 MCDisassembler(STI) { 41 } 42 43 ~ARMDisassembler() { 44 } 45 46 /// getInstruction - See MCDisassembler. 47 DecodeStatus getInstruction(MCInst &instr, 48 uint64_t &size, 49 const MemoryObject ®ion, 50 uint64_t address, 51 raw_ostream &vStream, 52 raw_ostream &cStream) const; 53 54 /// getEDInfo - See MCDisassembler. 55 const EDInstInfo *getEDInfo() const; 56 private: 57 }; 58 59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 60 class ThumbDisassembler : public MCDisassembler { 61 public: 62 /// Constructor - Initializes the disassembler. 63 /// 64 ThumbDisassembler(const MCSubtargetInfo &STI) : 65 MCDisassembler(STI) { 66 } 67 68 ~ThumbDisassembler() { 69 } 70 71 /// getInstruction - See MCDisassembler. 72 DecodeStatus getInstruction(MCInst &instr, 73 uint64_t &size, 74 const MemoryObject ®ion, 75 uint64_t address, 76 raw_ostream &vStream, 77 raw_ostream &cStream) const; 78 79 /// getEDInfo - See MCDisassembler. 80 const EDInstInfo *getEDInfo() const; 81 private: 82 mutable std::vector<unsigned> ITBlock; 83 DecodeStatus AddThumbPredicate(MCInst&) const; 84 void UpdateThumbVFPPredicate(MCInst&) const; 85 }; 86 } 87 88 static bool Check(DecodeStatus &Out, DecodeStatus In) { 89 switch (In) { 90 case MCDisassembler::Success: 91 // Out stays the same. 92 return true; 93 case MCDisassembler::SoftFail: 94 Out = In; 95 return true; 96 case MCDisassembler::Fail: 97 Out = In; 98 return false; 99 } 100 llvm_unreachable("Invalid DecodeStatus!"); 101 } 102 103 104 // Forward declare these because the autogenerated code will reference them. 105 // Definitions are further down. 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 107 uint64_t Address, const void *Decoder); 108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, 109 unsigned RegNo, uint64_t Address, 110 const void *Decoder); 111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 112 uint64_t Address, const void *Decoder); 113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, 124 unsigned RegNo, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 128 uint64_t Address, const void *Decoder); 129 130 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 131 uint64_t Address, const void *Decoder); 132 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 133 uint64_t Address, const void *Decoder); 134 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 135 uint64_t Address, const void *Decoder); 136 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 137 uint64_t Address, const void *Decoder); 138 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 139 uint64_t Address, const void *Decoder); 140 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 141 uint64_t Address, const void *Decoder); 142 143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 146 uint64_t Address, const void *Decoder); 147 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, 148 unsigned Insn, 149 uint64_t Address, 150 const void *Decoder); 151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 160 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 161 unsigned Insn, 162 uint64_t Adddress, 163 const void *Decoder); 164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 173 uint64_t Address, const void *Decoder); 174 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 257 258 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 321 322 323 #include "ARMGenDisassemblerTables.inc" 324 #include "ARMGenInstrInfo.inc" 325 #include "ARMGenEDInfo.inc" 326 327 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) { 328 return new ARMDisassembler(STI); 329 } 330 331 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) { 332 return new ThumbDisassembler(STI); 333 } 334 335 const EDInstInfo *ARMDisassembler::getEDInfo() const { 336 return instInfoARM; 337 } 338 339 const EDInstInfo *ThumbDisassembler::getEDInfo() const { 340 return instInfoARM; 341 } 342 343 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 344 const MemoryObject &Region, 345 uint64_t Address, 346 raw_ostream &os, 347 raw_ostream &cs) const { 348 CommentStream = &cs; 349 350 uint8_t bytes[4]; 351 352 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 353 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 354 355 // We want to read exactly 4 bytes of data. 356 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 357 Size = 0; 358 return MCDisassembler::Fail; 359 } 360 361 // Encoded as a small-endian 32-bit word in the stream. 362 uint32_t insn = (bytes[3] << 24) | 363 (bytes[2] << 16) | 364 (bytes[1] << 8) | 365 (bytes[0] << 0); 366 367 // Calling the auto-generated decoder function. 368 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI); 369 if (result != MCDisassembler::Fail) { 370 Size = 4; 371 return result; 372 } 373 374 // VFP and NEON instructions, similarly, are shared between ARM 375 // and Thumb modes. 376 MI.clear(); 377 result = decodeVFPInstruction32(MI, insn, Address, this, STI); 378 if (result != MCDisassembler::Fail) { 379 Size = 4; 380 return result; 381 } 382 383 MI.clear(); 384 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI); 385 if (result != MCDisassembler::Fail) { 386 Size = 4; 387 // Add a fake predicate operand, because we share these instruction 388 // definitions with Thumb2 where these instructions are predicable. 389 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 390 return MCDisassembler::Fail; 391 return result; 392 } 393 394 MI.clear(); 395 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI); 396 if (result != MCDisassembler::Fail) { 397 Size = 4; 398 // Add a fake predicate operand, because we share these instruction 399 // definitions with Thumb2 where these instructions are predicable. 400 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 401 return MCDisassembler::Fail; 402 return result; 403 } 404 405 MI.clear(); 406 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI); 407 if (result != MCDisassembler::Fail) { 408 Size = 4; 409 // Add a fake predicate operand, because we share these instruction 410 // definitions with Thumb2 where these instructions are predicable. 411 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 412 return MCDisassembler::Fail; 413 return result; 414 } 415 416 MI.clear(); 417 418 Size = 0; 419 return MCDisassembler::Fail; 420 } 421 422 namespace llvm { 423 extern const MCInstrDesc ARMInsts[]; 424 } 425 426 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 427 /// immediate Value in the MCInst. The immediate Value has had any PC 428 /// adjustment made by the caller. If the instruction is a branch instruction 429 /// then isBranch is true, else false. If the getOpInfo() function was set as 430 /// part of the setupForSymbolicDisassembly() call then that function is called 431 /// to get any symbolic information at the Address for this instruction. If 432 /// that returns non-zero then the symbolic information it returns is used to 433 /// create an MCExpr and that is added as an operand to the MCInst. If 434 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 435 /// Value is done and if a symbol is found an MCExpr is created with that, else 436 /// an MCExpr with Value is created. This function returns true if it adds an 437 /// operand to the MCInst and false otherwise. 438 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 439 bool isBranch, uint64_t InstSize, 440 MCInst &MI, const void *Decoder) { 441 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 442 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback(); 443 struct LLVMOpInfo1 SymbolicOp; 444 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 445 SymbolicOp.Value = Value; 446 void *DisInfo = Dis->getDisInfoBlock(); 447 448 if (!getOpInfo || 449 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) { 450 // Clear SymbolicOp.Value from above and also all other fields. 451 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1)); 452 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 453 if (!SymbolLookUp) 454 return false; 455 uint64_t ReferenceType; 456 if (isBranch) 457 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch; 458 else 459 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None; 460 const char *ReferenceName; 461 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address, 462 &ReferenceName); 463 if (Name) { 464 SymbolicOp.AddSymbol.Name = Name; 465 SymbolicOp.AddSymbol.Present = true; 466 } 467 // For branches always create an MCExpr so it gets printed as hex address. 468 else if (isBranch) { 469 SymbolicOp.Value = Value; 470 } 471 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub) 472 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName; 473 if (!Name && !isBranch) 474 return false; 475 } 476 477 MCContext *Ctx = Dis->getMCContext(); 478 const MCExpr *Add = NULL; 479 if (SymbolicOp.AddSymbol.Present) { 480 if (SymbolicOp.AddSymbol.Name) { 481 StringRef Name(SymbolicOp.AddSymbol.Name); 482 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 483 Add = MCSymbolRefExpr::Create(Sym, *Ctx); 484 } else { 485 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx); 486 } 487 } 488 489 const MCExpr *Sub = NULL; 490 if (SymbolicOp.SubtractSymbol.Present) { 491 if (SymbolicOp.SubtractSymbol.Name) { 492 StringRef Name(SymbolicOp.SubtractSymbol.Name); 493 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name); 494 Sub = MCSymbolRefExpr::Create(Sym, *Ctx); 495 } else { 496 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx); 497 } 498 } 499 500 const MCExpr *Off = NULL; 501 if (SymbolicOp.Value != 0) 502 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx); 503 504 const MCExpr *Expr; 505 if (Sub) { 506 const MCExpr *LHS; 507 if (Add) 508 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx); 509 else 510 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx); 511 if (Off != 0) 512 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx); 513 else 514 Expr = LHS; 515 } else if (Add) { 516 if (Off != 0) 517 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx); 518 else 519 Expr = Add; 520 } else { 521 if (Off != 0) 522 Expr = Off; 523 else 524 Expr = MCConstantExpr::Create(0, *Ctx); 525 } 526 527 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16) 528 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 529 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16) 530 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 531 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None) 532 MI.addOperand(MCOperand::CreateExpr(Expr)); 533 else 534 llvm_unreachable("bad SymbolicOp.VariantKind"); 535 536 return true; 537 } 538 539 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 540 /// referenced by a load instruction with the base register that is the Pc. 541 /// These can often be values in a literal pool near the Address of the 542 /// instruction. The Address of the instruction and its immediate Value are 543 /// used as a possible literal pool entry. The SymbolLookUp call back will 544 /// return the name of a symbol referenced by the the literal pool's entry if 545 /// the referenced address is that of a symbol. Or it will return a pointer to 546 /// a literal 'C' string if the referenced address of the literal pool's entry 547 /// is an address into a section with 'C' string literals. 548 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 549 const void *Decoder) { 550 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 551 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback(); 552 if (SymbolLookUp) { 553 void *DisInfo = Dis->getDisInfoBlock(); 554 uint64_t ReferenceType; 555 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load; 556 const char *ReferenceName; 557 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName); 558 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr || 559 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr) 560 (*Dis->CommentStream) << "literal pool for: " << ReferenceName; 561 } 562 } 563 564 // Thumb1 instructions don't have explicit S bits. Rather, they 565 // implicitly set CPSR. Since it's not represented in the encoding, the 566 // auto-generated decoder won't inject the CPSR operand. We need to fix 567 // that as a post-pass. 568 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 569 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 570 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 571 MCInst::iterator I = MI.begin(); 572 for (unsigned i = 0; i < NumOps; ++i, ++I) { 573 if (I == MI.end()) break; 574 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 575 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 576 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 577 return; 578 } 579 } 580 581 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 582 } 583 584 // Most Thumb instructions don't have explicit predicates in the 585 // encoding, but rather get their predicates from IT context. We need 586 // to fix up the predicate operands using this context information as a 587 // post-pass. 588 MCDisassembler::DecodeStatus 589 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 590 MCDisassembler::DecodeStatus S = Success; 591 592 // A few instructions actually have predicates encoded in them. Don't 593 // try to overwrite it if we're seeing one of those. 594 switch (MI.getOpcode()) { 595 case ARM::tBcc: 596 case ARM::t2Bcc: 597 case ARM::tCBZ: 598 case ARM::tCBNZ: 599 case ARM::tCPS: 600 case ARM::t2CPS3p: 601 case ARM::t2CPS2p: 602 case ARM::t2CPS1p: 603 case ARM::tMOVSr: 604 case ARM::tSETEND: 605 // Some instructions (mostly conditional branches) are not 606 // allowed in IT blocks. 607 if (!ITBlock.empty()) 608 S = SoftFail; 609 else 610 return Success; 611 break; 612 case ARM::tB: 613 case ARM::t2B: 614 case ARM::t2TBB: 615 case ARM::t2TBH: 616 // Some instructions (mostly unconditional branches) can 617 // only appears at the end of, or outside of, an IT. 618 if (ITBlock.size() > 1) 619 S = SoftFail; 620 break; 621 default: 622 break; 623 } 624 625 // If we're in an IT block, base the predicate on that. Otherwise, 626 // assume a predicate of AL. 627 unsigned CC; 628 if (!ITBlock.empty()) { 629 CC = ITBlock.back(); 630 if (CC == 0xF) 631 CC = ARMCC::AL; 632 ITBlock.pop_back(); 633 } else 634 CC = ARMCC::AL; 635 636 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 637 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 638 MCInst::iterator I = MI.begin(); 639 for (unsigned i = 0; i < NumOps; ++i, ++I) { 640 if (I == MI.end()) break; 641 if (OpInfo[i].isPredicate()) { 642 I = MI.insert(I, MCOperand::CreateImm(CC)); 643 ++I; 644 if (CC == ARMCC::AL) 645 MI.insert(I, MCOperand::CreateReg(0)); 646 else 647 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 648 return S; 649 } 650 } 651 652 I = MI.insert(I, MCOperand::CreateImm(CC)); 653 ++I; 654 if (CC == ARMCC::AL) 655 MI.insert(I, MCOperand::CreateReg(0)); 656 else 657 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 658 659 return S; 660 } 661 662 // Thumb VFP instructions are a special case. Because we share their 663 // encodings between ARM and Thumb modes, and they are predicable in ARM 664 // mode, the auto-generated decoder will give them an (incorrect) 665 // predicate operand. We need to rewrite these operands based on the IT 666 // context as a post-pass. 667 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 668 unsigned CC; 669 if (!ITBlock.empty()) { 670 CC = ITBlock.back(); 671 ITBlock.pop_back(); 672 } else 673 CC = ARMCC::AL; 674 675 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 676 MCInst::iterator I = MI.begin(); 677 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 678 for (unsigned i = 0; i < NumOps; ++i, ++I) { 679 if (OpInfo[i].isPredicate() ) { 680 I->setImm(CC); 681 ++I; 682 if (CC == ARMCC::AL) 683 I->setReg(0); 684 else 685 I->setReg(ARM::CPSR); 686 return; 687 } 688 } 689 } 690 691 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 692 const MemoryObject &Region, 693 uint64_t Address, 694 raw_ostream &os, 695 raw_ostream &cs) const { 696 CommentStream = &cs; 697 698 uint8_t bytes[4]; 699 700 assert((STI.getFeatureBits() & ARM::ModeThumb) && 701 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 702 703 // We want to read exactly 2 bytes of data. 704 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) { 705 Size = 0; 706 return MCDisassembler::Fail; 707 } 708 709 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 710 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI); 711 if (result != MCDisassembler::Fail) { 712 Size = 2; 713 Check(result, AddThumbPredicate(MI)); 714 return result; 715 } 716 717 MI.clear(); 718 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI); 719 if (result) { 720 Size = 2; 721 bool InITBlock = !ITBlock.empty(); 722 Check(result, AddThumbPredicate(MI)); 723 AddThumb1SBit(MI, InITBlock); 724 return result; 725 } 726 727 MI.clear(); 728 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI); 729 if (result != MCDisassembler::Fail) { 730 Size = 2; 731 732 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 733 // the Thumb predicate. 734 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty()) 735 result = MCDisassembler::SoftFail; 736 737 Check(result, AddThumbPredicate(MI)); 738 739 // If we find an IT instruction, we need to parse its condition 740 // code and mask operands so that we can apply them correctly 741 // to the subsequent instructions. 742 if (MI.getOpcode() == ARM::t2IT) { 743 744 // (3 - the number of trailing zeros) is the number of then / else. 745 unsigned firstcond = MI.getOperand(0).getImm(); 746 unsigned Mask = MI.getOperand(1).getImm(); 747 unsigned CondBit0 = Mask >> 4 & 1; 748 unsigned NumTZ = CountTrailingZeros_32(Mask); 749 assert(NumTZ <= 3 && "Invalid IT mask!"); 750 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) { 751 bool T = ((Mask >> Pos) & 1) == CondBit0; 752 if (T) 753 ITBlock.insert(ITBlock.begin(), firstcond); 754 else 755 ITBlock.insert(ITBlock.begin(), firstcond ^ 1); 756 } 757 758 ITBlock.push_back(firstcond); 759 } 760 761 return result; 762 } 763 764 // We want to read exactly 4 bytes of data. 765 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) { 766 Size = 0; 767 return MCDisassembler::Fail; 768 } 769 770 uint32_t insn32 = (bytes[3] << 8) | 771 (bytes[2] << 0) | 772 (bytes[1] << 24) | 773 (bytes[0] << 16); 774 MI.clear(); 775 result = decodeThumbInstruction32(MI, insn32, Address, this, STI); 776 if (result != MCDisassembler::Fail) { 777 Size = 4; 778 bool InITBlock = ITBlock.size(); 779 Check(result, AddThumbPredicate(MI)); 780 AddThumb1SBit(MI, InITBlock); 781 return result; 782 } 783 784 MI.clear(); 785 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI); 786 if (result != MCDisassembler::Fail) { 787 Size = 4; 788 Check(result, AddThumbPredicate(MI)); 789 return result; 790 } 791 792 MI.clear(); 793 result = decodeVFPInstruction32(MI, insn32, Address, this, STI); 794 if (result != MCDisassembler::Fail) { 795 Size = 4; 796 UpdateThumbVFPPredicate(MI); 797 return result; 798 } 799 800 MI.clear(); 801 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI); 802 if (result != MCDisassembler::Fail) { 803 Size = 4; 804 Check(result, AddThumbPredicate(MI)); 805 return result; 806 } 807 808 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 809 MI.clear(); 810 uint32_t NEONLdStInsn = insn32; 811 NEONLdStInsn &= 0xF0FFFFFF; 812 NEONLdStInsn |= 0x04000000; 813 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI); 814 if (result != MCDisassembler::Fail) { 815 Size = 4; 816 Check(result, AddThumbPredicate(MI)); 817 return result; 818 } 819 } 820 821 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 822 MI.clear(); 823 uint32_t NEONDataInsn = insn32; 824 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 825 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 826 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 827 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI); 828 if (result != MCDisassembler::Fail) { 829 Size = 4; 830 Check(result, AddThumbPredicate(MI)); 831 return result; 832 } 833 } 834 835 Size = 0; 836 return MCDisassembler::Fail; 837 } 838 839 840 extern "C" void LLVMInitializeARMDisassembler() { 841 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 842 createARMDisassembler); 843 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 844 createThumbDisassembler); 845 } 846 847 static const unsigned GPRDecoderTable[] = { 848 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 849 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 850 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 851 ARM::R12, ARM::SP, ARM::LR, ARM::PC 852 }; 853 854 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 855 uint64_t Address, const void *Decoder) { 856 if (RegNo > 15) 857 return MCDisassembler::Fail; 858 859 unsigned Register = GPRDecoderTable[RegNo]; 860 Inst.addOperand(MCOperand::CreateReg(Register)); 861 return MCDisassembler::Success; 862 } 863 864 static DecodeStatus 865 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 866 uint64_t Address, const void *Decoder) { 867 if (RegNo == 15) return MCDisassembler::Fail; 868 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 869 } 870 871 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 872 uint64_t Address, const void *Decoder) { 873 if (RegNo > 7) 874 return MCDisassembler::Fail; 875 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 876 } 877 878 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 879 uint64_t Address, const void *Decoder) { 880 unsigned Register = 0; 881 switch (RegNo) { 882 case 0: 883 Register = ARM::R0; 884 break; 885 case 1: 886 Register = ARM::R1; 887 break; 888 case 2: 889 Register = ARM::R2; 890 break; 891 case 3: 892 Register = ARM::R3; 893 break; 894 case 9: 895 Register = ARM::R9; 896 break; 897 case 12: 898 Register = ARM::R12; 899 break; 900 default: 901 return MCDisassembler::Fail; 902 } 903 904 Inst.addOperand(MCOperand::CreateReg(Register)); 905 return MCDisassembler::Success; 906 } 907 908 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 909 uint64_t Address, const void *Decoder) { 910 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail; 911 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 912 } 913 914 static const unsigned SPRDecoderTable[] = { 915 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 916 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 917 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 918 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 919 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 920 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 921 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 922 ARM::S28, ARM::S29, ARM::S30, ARM::S31 923 }; 924 925 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 926 uint64_t Address, const void *Decoder) { 927 if (RegNo > 31) 928 return MCDisassembler::Fail; 929 930 unsigned Register = SPRDecoderTable[RegNo]; 931 Inst.addOperand(MCOperand::CreateReg(Register)); 932 return MCDisassembler::Success; 933 } 934 935 static const unsigned DPRDecoderTable[] = { 936 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 937 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 938 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 939 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 940 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 941 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 942 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 943 ARM::D28, ARM::D29, ARM::D30, ARM::D31 944 }; 945 946 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 947 uint64_t Address, const void *Decoder) { 948 if (RegNo > 31) 949 return MCDisassembler::Fail; 950 951 unsigned Register = DPRDecoderTable[RegNo]; 952 Inst.addOperand(MCOperand::CreateReg(Register)); 953 return MCDisassembler::Success; 954 } 955 956 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 957 uint64_t Address, const void *Decoder) { 958 if (RegNo > 7) 959 return MCDisassembler::Fail; 960 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 961 } 962 963 static DecodeStatus 964 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 965 uint64_t Address, const void *Decoder) { 966 if (RegNo > 15) 967 return MCDisassembler::Fail; 968 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 969 } 970 971 static const unsigned QPRDecoderTable[] = { 972 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 973 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 974 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 975 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 976 }; 977 978 979 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 980 uint64_t Address, const void *Decoder) { 981 if (RegNo > 31) 982 return MCDisassembler::Fail; 983 RegNo >>= 1; 984 985 unsigned Register = QPRDecoderTable[RegNo]; 986 Inst.addOperand(MCOperand::CreateReg(Register)); 987 return MCDisassembler::Success; 988 } 989 990 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 991 uint64_t Address, const void *Decoder) { 992 if (Val == 0xF) return MCDisassembler::Fail; 993 // AL predicate is not allowed on Thumb1 branches. 994 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 995 return MCDisassembler::Fail; 996 Inst.addOperand(MCOperand::CreateImm(Val)); 997 if (Val == ARMCC::AL) { 998 Inst.addOperand(MCOperand::CreateReg(0)); 999 } else 1000 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1001 return MCDisassembler::Success; 1002 } 1003 1004 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 1005 uint64_t Address, const void *Decoder) { 1006 if (Val) 1007 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1008 else 1009 Inst.addOperand(MCOperand::CreateReg(0)); 1010 return MCDisassembler::Success; 1011 } 1012 1013 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 1014 uint64_t Address, const void *Decoder) { 1015 uint32_t imm = Val & 0xFF; 1016 uint32_t rot = (Val & 0xF00) >> 7; 1017 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1018 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1019 return MCDisassembler::Success; 1020 } 1021 1022 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 1023 uint64_t Address, const void *Decoder) { 1024 DecodeStatus S = MCDisassembler::Success; 1025 1026 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1027 unsigned type = fieldFromInstruction32(Val, 5, 2); 1028 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1029 1030 // Register-immediate 1031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1032 return MCDisassembler::Fail; 1033 1034 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1035 switch (type) { 1036 case 0: 1037 Shift = ARM_AM::lsl; 1038 break; 1039 case 1: 1040 Shift = ARM_AM::lsr; 1041 break; 1042 case 2: 1043 Shift = ARM_AM::asr; 1044 break; 1045 case 3: 1046 Shift = ARM_AM::ror; 1047 break; 1048 } 1049 1050 if (Shift == ARM_AM::ror && imm == 0) 1051 Shift = ARM_AM::rrx; 1052 1053 unsigned Op = Shift | (imm << 3); 1054 Inst.addOperand(MCOperand::CreateImm(Op)); 1055 1056 return S; 1057 } 1058 1059 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 1060 uint64_t Address, const void *Decoder) { 1061 DecodeStatus S = MCDisassembler::Success; 1062 1063 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1064 unsigned type = fieldFromInstruction32(Val, 5, 2); 1065 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 1066 1067 // Register-register 1068 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1069 return MCDisassembler::Fail; 1070 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1071 return MCDisassembler::Fail; 1072 1073 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1074 switch (type) { 1075 case 0: 1076 Shift = ARM_AM::lsl; 1077 break; 1078 case 1: 1079 Shift = ARM_AM::lsr; 1080 break; 1081 case 2: 1082 Shift = ARM_AM::asr; 1083 break; 1084 case 3: 1085 Shift = ARM_AM::ror; 1086 break; 1087 } 1088 1089 Inst.addOperand(MCOperand::CreateImm(Shift)); 1090 1091 return S; 1092 } 1093 1094 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 1095 uint64_t Address, const void *Decoder) { 1096 DecodeStatus S = MCDisassembler::Success; 1097 1098 bool writebackLoad = false; 1099 unsigned writebackReg = 0; 1100 switch (Inst.getOpcode()) { 1101 default: 1102 break; 1103 case ARM::LDMIA_UPD: 1104 case ARM::LDMDB_UPD: 1105 case ARM::LDMIB_UPD: 1106 case ARM::LDMDA_UPD: 1107 case ARM::t2LDMIA_UPD: 1108 case ARM::t2LDMDB_UPD: 1109 writebackLoad = true; 1110 writebackReg = Inst.getOperand(0).getReg(); 1111 break; 1112 } 1113 1114 // Empty register lists are not allowed. 1115 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail; 1116 for (unsigned i = 0; i < 16; ++i) { 1117 if (Val & (1 << i)) { 1118 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1119 return MCDisassembler::Fail; 1120 // Writeback not allowed if Rn is in the target list. 1121 if (writebackLoad && writebackReg == Inst.end()[-1].getReg()) 1122 Check(S, MCDisassembler::SoftFail); 1123 } 1124 } 1125 1126 return S; 1127 } 1128 1129 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1130 uint64_t Address, const void *Decoder) { 1131 DecodeStatus S = MCDisassembler::Success; 1132 1133 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1134 unsigned regs = Val & 0xFF; 1135 1136 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1137 return MCDisassembler::Fail; 1138 for (unsigned i = 0; i < (regs - 1); ++i) { 1139 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1140 return MCDisassembler::Fail; 1141 } 1142 1143 return S; 1144 } 1145 1146 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 1147 uint64_t Address, const void *Decoder) { 1148 DecodeStatus S = MCDisassembler::Success; 1149 1150 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 1151 unsigned regs = (Val & 0xFF) / 2; 1152 1153 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1154 return MCDisassembler::Fail; 1155 for (unsigned i = 0; i < (regs - 1); ++i) { 1156 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1157 return MCDisassembler::Fail; 1158 } 1159 1160 return S; 1161 } 1162 1163 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 1164 uint64_t Address, const void *Decoder) { 1165 // This operand encodes a mask of contiguous zeros between a specified MSB 1166 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1167 // the mask of all bits LSB-and-lower, and then xor them to create 1168 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1169 // create the final mask. 1170 unsigned msb = fieldFromInstruction32(Val, 5, 5); 1171 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 1172 1173 DecodeStatus S = MCDisassembler::Success; 1174 if (lsb > msb) Check(S, MCDisassembler::SoftFail); 1175 1176 uint32_t msb_mask = 0xFFFFFFFF; 1177 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1178 uint32_t lsb_mask = (1U << lsb) - 1; 1179 1180 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1181 return S; 1182 } 1183 1184 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 1185 uint64_t Address, const void *Decoder) { 1186 DecodeStatus S = MCDisassembler::Success; 1187 1188 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1189 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 1190 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 1191 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 1192 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1193 unsigned U = fieldFromInstruction32(Insn, 23, 1); 1194 1195 switch (Inst.getOpcode()) { 1196 case ARM::LDC_OFFSET: 1197 case ARM::LDC_PRE: 1198 case ARM::LDC_POST: 1199 case ARM::LDC_OPTION: 1200 case ARM::LDCL_OFFSET: 1201 case ARM::LDCL_PRE: 1202 case ARM::LDCL_POST: 1203 case ARM::LDCL_OPTION: 1204 case ARM::STC_OFFSET: 1205 case ARM::STC_PRE: 1206 case ARM::STC_POST: 1207 case ARM::STC_OPTION: 1208 case ARM::STCL_OFFSET: 1209 case ARM::STCL_PRE: 1210 case ARM::STCL_POST: 1211 case ARM::STCL_OPTION: 1212 case ARM::t2LDC_OFFSET: 1213 case ARM::t2LDC_PRE: 1214 case ARM::t2LDC_POST: 1215 case ARM::t2LDC_OPTION: 1216 case ARM::t2LDCL_OFFSET: 1217 case ARM::t2LDCL_PRE: 1218 case ARM::t2LDCL_POST: 1219 case ARM::t2LDCL_OPTION: 1220 case ARM::t2STC_OFFSET: 1221 case ARM::t2STC_PRE: 1222 case ARM::t2STC_POST: 1223 case ARM::t2STC_OPTION: 1224 case ARM::t2STCL_OFFSET: 1225 case ARM::t2STCL_PRE: 1226 case ARM::t2STCL_POST: 1227 case ARM::t2STCL_OPTION: 1228 if (coproc == 0xA || coproc == 0xB) 1229 return MCDisassembler::Fail; 1230 break; 1231 default: 1232 break; 1233 } 1234 1235 Inst.addOperand(MCOperand::CreateImm(coproc)); 1236 Inst.addOperand(MCOperand::CreateImm(CRd)); 1237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1238 return MCDisassembler::Fail; 1239 1240 switch (Inst.getOpcode()) { 1241 case ARM::t2LDC2_OFFSET: 1242 case ARM::t2LDC2L_OFFSET: 1243 case ARM::t2LDC2_PRE: 1244 case ARM::t2LDC2L_PRE: 1245 case ARM::t2STC2_OFFSET: 1246 case ARM::t2STC2L_OFFSET: 1247 case ARM::t2STC2_PRE: 1248 case ARM::t2STC2L_PRE: 1249 case ARM::LDC2_OFFSET: 1250 case ARM::LDC2L_OFFSET: 1251 case ARM::LDC2_PRE: 1252 case ARM::LDC2L_PRE: 1253 case ARM::STC2_OFFSET: 1254 case ARM::STC2L_OFFSET: 1255 case ARM::STC2_PRE: 1256 case ARM::STC2L_PRE: 1257 case ARM::t2LDC_OFFSET: 1258 case ARM::t2LDCL_OFFSET: 1259 case ARM::t2LDC_PRE: 1260 case ARM::t2LDCL_PRE: 1261 case ARM::t2STC_OFFSET: 1262 case ARM::t2STCL_OFFSET: 1263 case ARM::t2STC_PRE: 1264 case ARM::t2STCL_PRE: 1265 case ARM::LDC_OFFSET: 1266 case ARM::LDCL_OFFSET: 1267 case ARM::LDC_PRE: 1268 case ARM::LDCL_PRE: 1269 case ARM::STC_OFFSET: 1270 case ARM::STCL_OFFSET: 1271 case ARM::STC_PRE: 1272 case ARM::STCL_PRE: 1273 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1274 Inst.addOperand(MCOperand::CreateImm(imm)); 1275 break; 1276 case ARM::t2LDC2_POST: 1277 case ARM::t2LDC2L_POST: 1278 case ARM::t2STC2_POST: 1279 case ARM::t2STC2L_POST: 1280 case ARM::LDC2_POST: 1281 case ARM::LDC2L_POST: 1282 case ARM::STC2_POST: 1283 case ARM::STC2L_POST: 1284 case ARM::t2LDC_POST: 1285 case ARM::t2LDCL_POST: 1286 case ARM::t2STC_POST: 1287 case ARM::t2STCL_POST: 1288 case ARM::LDC_POST: 1289 case ARM::LDCL_POST: 1290 case ARM::STC_POST: 1291 case ARM::STCL_POST: 1292 imm |= U << 8; 1293 // fall through. 1294 default: 1295 // The 'option' variant doesn't encode 'U' in the immediate since 1296 // the immediate is unsigned [0,255]. 1297 Inst.addOperand(MCOperand::CreateImm(imm)); 1298 break; 1299 } 1300 1301 switch (Inst.getOpcode()) { 1302 case ARM::LDC_OFFSET: 1303 case ARM::LDC_PRE: 1304 case ARM::LDC_POST: 1305 case ARM::LDC_OPTION: 1306 case ARM::LDCL_OFFSET: 1307 case ARM::LDCL_PRE: 1308 case ARM::LDCL_POST: 1309 case ARM::LDCL_OPTION: 1310 case ARM::STC_OFFSET: 1311 case ARM::STC_PRE: 1312 case ARM::STC_POST: 1313 case ARM::STC_OPTION: 1314 case ARM::STCL_OFFSET: 1315 case ARM::STCL_PRE: 1316 case ARM::STCL_POST: 1317 case ARM::STCL_OPTION: 1318 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1319 return MCDisassembler::Fail; 1320 break; 1321 default: 1322 break; 1323 } 1324 1325 return S; 1326 } 1327 1328 static DecodeStatus 1329 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 1330 uint64_t Address, const void *Decoder) { 1331 DecodeStatus S = MCDisassembler::Success; 1332 1333 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1334 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1335 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1336 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 1337 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1338 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 1339 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1340 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1341 1342 // On stores, the writeback operand precedes Rt. 1343 switch (Inst.getOpcode()) { 1344 case ARM::STR_POST_IMM: 1345 case ARM::STR_POST_REG: 1346 case ARM::STRB_POST_IMM: 1347 case ARM::STRB_POST_REG: 1348 case ARM::STRT_POST_REG: 1349 case ARM::STRT_POST_IMM: 1350 case ARM::STRBT_POST_REG: 1351 case ARM::STRBT_POST_IMM: 1352 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1353 return MCDisassembler::Fail; 1354 break; 1355 default: 1356 break; 1357 } 1358 1359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1360 return MCDisassembler::Fail; 1361 1362 // On loads, the writeback operand comes after Rt. 1363 switch (Inst.getOpcode()) { 1364 case ARM::LDR_POST_IMM: 1365 case ARM::LDR_POST_REG: 1366 case ARM::LDRB_POST_IMM: 1367 case ARM::LDRB_POST_REG: 1368 case ARM::LDRBT_POST_REG: 1369 case ARM::LDRBT_POST_IMM: 1370 case ARM::LDRT_POST_REG: 1371 case ARM::LDRT_POST_IMM: 1372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1373 return MCDisassembler::Fail; 1374 break; 1375 default: 1376 break; 1377 } 1378 1379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1380 return MCDisassembler::Fail; 1381 1382 ARM_AM::AddrOpc Op = ARM_AM::add; 1383 if (!fieldFromInstruction32(Insn, 23, 1)) 1384 Op = ARM_AM::sub; 1385 1386 bool writeback = (P == 0) || (W == 1); 1387 unsigned idx_mode = 0; 1388 if (P && writeback) 1389 idx_mode = ARMII::IndexModePre; 1390 else if (!P && writeback) 1391 idx_mode = ARMII::IndexModePost; 1392 1393 if (writeback && (Rn == 15 || Rn == Rt)) 1394 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1395 1396 if (reg) { 1397 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1398 return MCDisassembler::Fail; 1399 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1400 switch( fieldFromInstruction32(Insn, 5, 2)) { 1401 case 0: 1402 Opc = ARM_AM::lsl; 1403 break; 1404 case 1: 1405 Opc = ARM_AM::lsr; 1406 break; 1407 case 2: 1408 Opc = ARM_AM::asr; 1409 break; 1410 case 3: 1411 Opc = ARM_AM::ror; 1412 break; 1413 default: 1414 return MCDisassembler::Fail; 1415 } 1416 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1417 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1418 1419 Inst.addOperand(MCOperand::CreateImm(imm)); 1420 } else { 1421 Inst.addOperand(MCOperand::CreateReg(0)); 1422 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1423 Inst.addOperand(MCOperand::CreateImm(tmp)); 1424 } 1425 1426 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1427 return MCDisassembler::Fail; 1428 1429 return S; 1430 } 1431 1432 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1433 uint64_t Address, const void *Decoder) { 1434 DecodeStatus S = MCDisassembler::Success; 1435 1436 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1437 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1438 unsigned type = fieldFromInstruction32(Val, 5, 2); 1439 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1440 unsigned U = fieldFromInstruction32(Val, 12, 1); 1441 1442 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1443 switch (type) { 1444 case 0: 1445 ShOp = ARM_AM::lsl; 1446 break; 1447 case 1: 1448 ShOp = ARM_AM::lsr; 1449 break; 1450 case 2: 1451 ShOp = ARM_AM::asr; 1452 break; 1453 case 3: 1454 ShOp = ARM_AM::ror; 1455 break; 1456 } 1457 1458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1459 return MCDisassembler::Fail; 1460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1461 return MCDisassembler::Fail; 1462 unsigned shift; 1463 if (U) 1464 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1465 else 1466 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1467 Inst.addOperand(MCOperand::CreateImm(shift)); 1468 1469 return S; 1470 } 1471 1472 static DecodeStatus 1473 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1474 uint64_t Address, const void *Decoder) { 1475 DecodeStatus S = MCDisassembler::Success; 1476 1477 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1478 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1479 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1480 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1481 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1482 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1483 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1484 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1485 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1486 1487 bool writeback = (W == 1) | (P == 0); 1488 1489 // For {LD,ST}RD, Rt must be even, else undefined. 1490 switch (Inst.getOpcode()) { 1491 case ARM::STRD: 1492 case ARM::STRD_PRE: 1493 case ARM::STRD_POST: 1494 case ARM::LDRD: 1495 case ARM::LDRD_PRE: 1496 case ARM::LDRD_POST: 1497 if (Rt & 0x1) return MCDisassembler::Fail; 1498 break; 1499 default: 1500 break; 1501 } 1502 1503 if (writeback) { // Writeback 1504 if (P) 1505 U |= ARMII::IndexModePre << 9; 1506 else 1507 U |= ARMII::IndexModePost << 9; 1508 1509 // On stores, the writeback operand precedes Rt. 1510 switch (Inst.getOpcode()) { 1511 case ARM::STRD: 1512 case ARM::STRD_PRE: 1513 case ARM::STRD_POST: 1514 case ARM::STRH: 1515 case ARM::STRH_PRE: 1516 case ARM::STRH_POST: 1517 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1518 return MCDisassembler::Fail; 1519 break; 1520 default: 1521 break; 1522 } 1523 } 1524 1525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1526 return MCDisassembler::Fail; 1527 switch (Inst.getOpcode()) { 1528 case ARM::STRD: 1529 case ARM::STRD_PRE: 1530 case ARM::STRD_POST: 1531 case ARM::LDRD: 1532 case ARM::LDRD_PRE: 1533 case ARM::LDRD_POST: 1534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1535 return MCDisassembler::Fail; 1536 break; 1537 default: 1538 break; 1539 } 1540 1541 if (writeback) { 1542 // On loads, the writeback operand comes after Rt. 1543 switch (Inst.getOpcode()) { 1544 case ARM::LDRD: 1545 case ARM::LDRD_PRE: 1546 case ARM::LDRD_POST: 1547 case ARM::LDRH: 1548 case ARM::LDRH_PRE: 1549 case ARM::LDRH_POST: 1550 case ARM::LDRSH: 1551 case ARM::LDRSH_PRE: 1552 case ARM::LDRSH_POST: 1553 case ARM::LDRSB: 1554 case ARM::LDRSB_PRE: 1555 case ARM::LDRSB_POST: 1556 case ARM::LDRHTr: 1557 case ARM::LDRSBTr: 1558 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1559 return MCDisassembler::Fail; 1560 break; 1561 default: 1562 break; 1563 } 1564 } 1565 1566 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1567 return MCDisassembler::Fail; 1568 1569 if (type) { 1570 Inst.addOperand(MCOperand::CreateReg(0)); 1571 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1572 } else { 1573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1574 return MCDisassembler::Fail; 1575 Inst.addOperand(MCOperand::CreateImm(U)); 1576 } 1577 1578 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1579 return MCDisassembler::Fail; 1580 1581 return S; 1582 } 1583 1584 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1585 uint64_t Address, const void *Decoder) { 1586 DecodeStatus S = MCDisassembler::Success; 1587 1588 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1589 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1590 1591 switch (mode) { 1592 case 0: 1593 mode = ARM_AM::da; 1594 break; 1595 case 1: 1596 mode = ARM_AM::ia; 1597 break; 1598 case 2: 1599 mode = ARM_AM::db; 1600 break; 1601 case 3: 1602 mode = ARM_AM::ib; 1603 break; 1604 } 1605 1606 Inst.addOperand(MCOperand::CreateImm(mode)); 1607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1608 return MCDisassembler::Fail; 1609 1610 return S; 1611 } 1612 1613 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1614 unsigned Insn, 1615 uint64_t Address, const void *Decoder) { 1616 DecodeStatus S = MCDisassembler::Success; 1617 1618 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1619 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1620 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1621 1622 if (pred == 0xF) { 1623 switch (Inst.getOpcode()) { 1624 case ARM::LDMDA: 1625 Inst.setOpcode(ARM::RFEDA); 1626 break; 1627 case ARM::LDMDA_UPD: 1628 Inst.setOpcode(ARM::RFEDA_UPD); 1629 break; 1630 case ARM::LDMDB: 1631 Inst.setOpcode(ARM::RFEDB); 1632 break; 1633 case ARM::LDMDB_UPD: 1634 Inst.setOpcode(ARM::RFEDB_UPD); 1635 break; 1636 case ARM::LDMIA: 1637 Inst.setOpcode(ARM::RFEIA); 1638 break; 1639 case ARM::LDMIA_UPD: 1640 Inst.setOpcode(ARM::RFEIA_UPD); 1641 break; 1642 case ARM::LDMIB: 1643 Inst.setOpcode(ARM::RFEIB); 1644 break; 1645 case ARM::LDMIB_UPD: 1646 Inst.setOpcode(ARM::RFEIB_UPD); 1647 break; 1648 case ARM::STMDA: 1649 Inst.setOpcode(ARM::SRSDA); 1650 break; 1651 case ARM::STMDA_UPD: 1652 Inst.setOpcode(ARM::SRSDA_UPD); 1653 break; 1654 case ARM::STMDB: 1655 Inst.setOpcode(ARM::SRSDB); 1656 break; 1657 case ARM::STMDB_UPD: 1658 Inst.setOpcode(ARM::SRSDB_UPD); 1659 break; 1660 case ARM::STMIA: 1661 Inst.setOpcode(ARM::SRSIA); 1662 break; 1663 case ARM::STMIA_UPD: 1664 Inst.setOpcode(ARM::SRSIA_UPD); 1665 break; 1666 case ARM::STMIB: 1667 Inst.setOpcode(ARM::SRSIB); 1668 break; 1669 case ARM::STMIB_UPD: 1670 Inst.setOpcode(ARM::SRSIB_UPD); 1671 break; 1672 default: 1673 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail; 1674 } 1675 1676 // For stores (which become SRS's, the only operand is the mode. 1677 if (fieldFromInstruction32(Insn, 20, 1) == 0) { 1678 Inst.addOperand( 1679 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4))); 1680 return S; 1681 } 1682 1683 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1684 } 1685 1686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1687 return MCDisassembler::Fail; 1688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1689 return MCDisassembler::Fail; // Tied 1690 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1691 return MCDisassembler::Fail; 1692 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1693 return MCDisassembler::Fail; 1694 1695 return S; 1696 } 1697 1698 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1699 uint64_t Address, const void *Decoder) { 1700 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1701 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1702 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1703 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1704 1705 DecodeStatus S = MCDisassembler::Success; 1706 1707 // imod == '01' --> UNPREDICTABLE 1708 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1709 // return failure here. The '01' imod value is unprintable, so there's 1710 // nothing useful we could do even if we returned UNPREDICTABLE. 1711 1712 if (imod == 1) return MCDisassembler::Fail; 1713 1714 if (imod && M) { 1715 Inst.setOpcode(ARM::CPS3p); 1716 Inst.addOperand(MCOperand::CreateImm(imod)); 1717 Inst.addOperand(MCOperand::CreateImm(iflags)); 1718 Inst.addOperand(MCOperand::CreateImm(mode)); 1719 } else if (imod && !M) { 1720 Inst.setOpcode(ARM::CPS2p); 1721 Inst.addOperand(MCOperand::CreateImm(imod)); 1722 Inst.addOperand(MCOperand::CreateImm(iflags)); 1723 if (mode) S = MCDisassembler::SoftFail; 1724 } else if (!imod && M) { 1725 Inst.setOpcode(ARM::CPS1p); 1726 Inst.addOperand(MCOperand::CreateImm(mode)); 1727 if (iflags) S = MCDisassembler::SoftFail; 1728 } else { 1729 // imod == '00' && M == '0' --> UNPREDICTABLE 1730 Inst.setOpcode(ARM::CPS1p); 1731 Inst.addOperand(MCOperand::CreateImm(mode)); 1732 S = MCDisassembler::SoftFail; 1733 } 1734 1735 return S; 1736 } 1737 1738 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1739 uint64_t Address, const void *Decoder) { 1740 unsigned imod = fieldFromInstruction32(Insn, 9, 2); 1741 unsigned M = fieldFromInstruction32(Insn, 8, 1); 1742 unsigned iflags = fieldFromInstruction32(Insn, 5, 3); 1743 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1744 1745 DecodeStatus S = MCDisassembler::Success; 1746 1747 // imod == '01' --> UNPREDICTABLE 1748 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1749 // return failure here. The '01' imod value is unprintable, so there's 1750 // nothing useful we could do even if we returned UNPREDICTABLE. 1751 1752 if (imod == 1) return MCDisassembler::Fail; 1753 1754 if (imod && M) { 1755 Inst.setOpcode(ARM::t2CPS3p); 1756 Inst.addOperand(MCOperand::CreateImm(imod)); 1757 Inst.addOperand(MCOperand::CreateImm(iflags)); 1758 Inst.addOperand(MCOperand::CreateImm(mode)); 1759 } else if (imod && !M) { 1760 Inst.setOpcode(ARM::t2CPS2p); 1761 Inst.addOperand(MCOperand::CreateImm(imod)); 1762 Inst.addOperand(MCOperand::CreateImm(iflags)); 1763 if (mode) S = MCDisassembler::SoftFail; 1764 } else if (!imod && M) { 1765 Inst.setOpcode(ARM::t2CPS1p); 1766 Inst.addOperand(MCOperand::CreateImm(mode)); 1767 if (iflags) S = MCDisassembler::SoftFail; 1768 } else { 1769 // imod == '00' && M == '0' --> UNPREDICTABLE 1770 Inst.setOpcode(ARM::t2CPS1p); 1771 Inst.addOperand(MCOperand::CreateImm(mode)); 1772 S = MCDisassembler::SoftFail; 1773 } 1774 1775 return S; 1776 } 1777 1778 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1779 uint64_t Address, const void *Decoder) { 1780 DecodeStatus S = MCDisassembler::Success; 1781 1782 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); 1783 unsigned imm = 0; 1784 1785 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0); 1786 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8); 1787 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1788 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11); 1789 1790 if (Inst.getOpcode() == ARM::t2MOVTi16) 1791 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1792 return MCDisassembler::Fail; 1793 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 1796 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1797 Inst.addOperand(MCOperand::CreateImm(imm)); 1798 1799 return S; 1800 } 1801 1802 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1803 uint64_t Address, const void *Decoder) { 1804 DecodeStatus S = MCDisassembler::Success; 1805 1806 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1807 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1808 unsigned imm = 0; 1809 1810 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0); 1811 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12); 1812 1813 if (Inst.getOpcode() == ARM::MOVTi16) 1814 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1815 return MCDisassembler::Fail; 1816 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1817 return MCDisassembler::Fail; 1818 1819 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 1820 Inst.addOperand(MCOperand::CreateImm(imm)); 1821 1822 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1823 return MCDisassembler::Fail; 1824 1825 return S; 1826 } 1827 1828 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1829 uint64_t Address, const void *Decoder) { 1830 DecodeStatus S = MCDisassembler::Success; 1831 1832 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1833 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1834 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1835 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1836 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1837 1838 if (pred == 0xF) 1839 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1840 1841 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1842 return MCDisassembler::Fail; 1843 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1844 return MCDisassembler::Fail; 1845 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1846 return MCDisassembler::Fail; 1847 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 1848 return MCDisassembler::Fail; 1849 1850 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1851 return MCDisassembler::Fail; 1852 1853 return S; 1854 } 1855 1856 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1857 uint64_t Address, const void *Decoder) { 1858 DecodeStatus S = MCDisassembler::Success; 1859 1860 unsigned add = fieldFromInstruction32(Val, 12, 1); 1861 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1862 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1863 1864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1865 return MCDisassembler::Fail; 1866 1867 if (!add) imm *= -1; 1868 if (imm == 0 && !add) imm = INT32_MIN; 1869 Inst.addOperand(MCOperand::CreateImm(imm)); 1870 if (Rn == 15) 1871 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 1872 1873 return S; 1874 } 1875 1876 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1877 uint64_t Address, const void *Decoder) { 1878 DecodeStatus S = MCDisassembler::Success; 1879 1880 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1881 unsigned U = fieldFromInstruction32(Val, 8, 1); 1882 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1883 1884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1885 return MCDisassembler::Fail; 1886 1887 if (U) 1888 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1889 else 1890 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1891 1892 return S; 1893 } 1894 1895 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1896 uint64_t Address, const void *Decoder) { 1897 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1898 } 1899 1900 static DecodeStatus 1901 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1902 uint64_t Address, const void *Decoder) { 1903 DecodeStatus S = MCDisassembler::Success; 1904 1905 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1906 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1907 1908 if (pred == 0xF) { 1909 Inst.setOpcode(ARM::BLXi); 1910 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1911 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 1912 true, 4, Inst, Decoder)) 1913 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1914 return S; 1915 } 1916 1917 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 1918 true, 4, Inst, Decoder)) 1919 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1920 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1921 return MCDisassembler::Fail; 1922 1923 return S; 1924 } 1925 1926 1927 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1928 uint64_t Address, const void *Decoder) { 1929 DecodeStatus S = MCDisassembler::Success; 1930 1931 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1932 unsigned align = fieldFromInstruction32(Val, 4, 2); 1933 1934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1935 return MCDisassembler::Fail; 1936 if (!align) 1937 Inst.addOperand(MCOperand::CreateImm(0)); 1938 else 1939 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1940 1941 return S; 1942 } 1943 1944 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1945 uint64_t Address, const void *Decoder) { 1946 DecodeStatus S = MCDisassembler::Success; 1947 1948 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1949 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1950 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1951 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1952 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1953 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1954 1955 // First output register 1956 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 1957 return MCDisassembler::Fail; 1958 1959 // Second output register 1960 switch (Inst.getOpcode()) { 1961 case ARM::VLD3d8: 1962 case ARM::VLD3d16: 1963 case ARM::VLD3d32: 1964 case ARM::VLD3d8_UPD: 1965 case ARM::VLD3d16_UPD: 1966 case ARM::VLD3d32_UPD: 1967 case ARM::VLD4d8: 1968 case ARM::VLD4d16: 1969 case ARM::VLD4d32: 1970 case ARM::VLD4d8_UPD: 1971 case ARM::VLD4d16_UPD: 1972 case ARM::VLD4d32_UPD: 1973 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 1974 return MCDisassembler::Fail; 1975 break; 1976 case ARM::VLD3q8: 1977 case ARM::VLD3q16: 1978 case ARM::VLD3q32: 1979 case ARM::VLD3q8_UPD: 1980 case ARM::VLD3q16_UPD: 1981 case ARM::VLD3q32_UPD: 1982 case ARM::VLD4q8: 1983 case ARM::VLD4q16: 1984 case ARM::VLD4q32: 1985 case ARM::VLD4q8_UPD: 1986 case ARM::VLD4q16_UPD: 1987 case ARM::VLD4q32_UPD: 1988 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 1989 return MCDisassembler::Fail; 1990 default: 1991 break; 1992 } 1993 1994 // Third output register 1995 switch(Inst.getOpcode()) { 1996 case ARM::VLD3d8: 1997 case ARM::VLD3d16: 1998 case ARM::VLD3d32: 1999 case ARM::VLD3d8_UPD: 2000 case ARM::VLD3d16_UPD: 2001 case ARM::VLD3d32_UPD: 2002 case ARM::VLD4d8: 2003 case ARM::VLD4d16: 2004 case ARM::VLD4d32: 2005 case ARM::VLD4d8_UPD: 2006 case ARM::VLD4d16_UPD: 2007 case ARM::VLD4d32_UPD: 2008 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2009 return MCDisassembler::Fail; 2010 break; 2011 case ARM::VLD3q8: 2012 case ARM::VLD3q16: 2013 case ARM::VLD3q32: 2014 case ARM::VLD3q8_UPD: 2015 case ARM::VLD3q16_UPD: 2016 case ARM::VLD3q32_UPD: 2017 case ARM::VLD4q8: 2018 case ARM::VLD4q16: 2019 case ARM::VLD4q32: 2020 case ARM::VLD4q8_UPD: 2021 case ARM::VLD4q16_UPD: 2022 case ARM::VLD4q32_UPD: 2023 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2024 return MCDisassembler::Fail; 2025 break; 2026 default: 2027 break; 2028 } 2029 2030 // Fourth output register 2031 switch (Inst.getOpcode()) { 2032 case ARM::VLD4d8: 2033 case ARM::VLD4d16: 2034 case ARM::VLD4d32: 2035 case ARM::VLD4d8_UPD: 2036 case ARM::VLD4d16_UPD: 2037 case ARM::VLD4d32_UPD: 2038 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2039 return MCDisassembler::Fail; 2040 break; 2041 case ARM::VLD4q8: 2042 case ARM::VLD4q16: 2043 case ARM::VLD4q32: 2044 case ARM::VLD4q8_UPD: 2045 case ARM::VLD4q16_UPD: 2046 case ARM::VLD4q32_UPD: 2047 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2048 return MCDisassembler::Fail; 2049 break; 2050 default: 2051 break; 2052 } 2053 2054 // Writeback operand 2055 switch (Inst.getOpcode()) { 2056 case ARM::VLD1d8wb_fixed: 2057 case ARM::VLD1d16wb_fixed: 2058 case ARM::VLD1d32wb_fixed: 2059 case ARM::VLD1d64wb_fixed: 2060 case ARM::VLD1d8wb_register: 2061 case ARM::VLD1d16wb_register: 2062 case ARM::VLD1d32wb_register: 2063 case ARM::VLD1d64wb_register: 2064 case ARM::VLD1q8wb_fixed: 2065 case ARM::VLD1q16wb_fixed: 2066 case ARM::VLD1q32wb_fixed: 2067 case ARM::VLD1q64wb_fixed: 2068 case ARM::VLD1q8wb_register: 2069 case ARM::VLD1q16wb_register: 2070 case ARM::VLD1q32wb_register: 2071 case ARM::VLD1q64wb_register: 2072 case ARM::VLD1d8Twb_fixed: 2073 case ARM::VLD1d8Twb_register: 2074 case ARM::VLD1d16Twb_fixed: 2075 case ARM::VLD1d16Twb_register: 2076 case ARM::VLD1d32Twb_fixed: 2077 case ARM::VLD1d32Twb_register: 2078 case ARM::VLD1d64Twb_fixed: 2079 case ARM::VLD1d64Twb_register: 2080 case ARM::VLD1d8Qwb_fixed: 2081 case ARM::VLD1d8Qwb_register: 2082 case ARM::VLD1d16Qwb_fixed: 2083 case ARM::VLD1d16Qwb_register: 2084 case ARM::VLD1d32Qwb_fixed: 2085 case ARM::VLD1d32Qwb_register: 2086 case ARM::VLD1d64Qwb_fixed: 2087 case ARM::VLD1d64Qwb_register: 2088 case ARM::VLD2d8wb_fixed: 2089 case ARM::VLD2d16wb_fixed: 2090 case ARM::VLD2d32wb_fixed: 2091 case ARM::VLD2q8wb_fixed: 2092 case ARM::VLD2q16wb_fixed: 2093 case ARM::VLD2q32wb_fixed: 2094 case ARM::VLD2d8wb_register: 2095 case ARM::VLD2d16wb_register: 2096 case ARM::VLD2d32wb_register: 2097 case ARM::VLD2q8wb_register: 2098 case ARM::VLD2q16wb_register: 2099 case ARM::VLD2q32wb_register: 2100 case ARM::VLD2b8wb_fixed: 2101 case ARM::VLD2b16wb_fixed: 2102 case ARM::VLD2b32wb_fixed: 2103 case ARM::VLD2b8wb_register: 2104 case ARM::VLD2b16wb_register: 2105 case ARM::VLD2b32wb_register: 2106 case ARM::VLD3d8_UPD: 2107 case ARM::VLD3d16_UPD: 2108 case ARM::VLD3d32_UPD: 2109 case ARM::VLD3q8_UPD: 2110 case ARM::VLD3q16_UPD: 2111 case ARM::VLD3q32_UPD: 2112 case ARM::VLD4d8_UPD: 2113 case ARM::VLD4d16_UPD: 2114 case ARM::VLD4d32_UPD: 2115 case ARM::VLD4q8_UPD: 2116 case ARM::VLD4q16_UPD: 2117 case ARM::VLD4q32_UPD: 2118 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2119 return MCDisassembler::Fail; 2120 break; 2121 default: 2122 break; 2123 } 2124 2125 // AddrMode6 Base (register+alignment) 2126 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2127 return MCDisassembler::Fail; 2128 2129 // AddrMode6 Offset (register) 2130 switch (Inst.getOpcode()) { 2131 default: 2132 // The below have been updated to have explicit am6offset split 2133 // between fixed and register offset. For those instructions not 2134 // yet updated, we need to add an additional reg0 operand for the 2135 // fixed variant. 2136 // 2137 // The fixed offset encodes as Rm == 0xd, so we check for that. 2138 if (Rm == 0xd) { 2139 Inst.addOperand(MCOperand::CreateReg(0)); 2140 break; 2141 } 2142 // Fall through to handle the register offset variant. 2143 case ARM::VLD1d8wb_fixed: 2144 case ARM::VLD1d16wb_fixed: 2145 case ARM::VLD1d32wb_fixed: 2146 case ARM::VLD1d64wb_fixed: 2147 case ARM::VLD1d8Twb_fixed: 2148 case ARM::VLD1d16Twb_fixed: 2149 case ARM::VLD1d32Twb_fixed: 2150 case ARM::VLD1d64Twb_fixed: 2151 case ARM::VLD1d8Qwb_fixed: 2152 case ARM::VLD1d16Qwb_fixed: 2153 case ARM::VLD1d32Qwb_fixed: 2154 case ARM::VLD1d64Qwb_fixed: 2155 case ARM::VLD1d8wb_register: 2156 case ARM::VLD1d16wb_register: 2157 case ARM::VLD1d32wb_register: 2158 case ARM::VLD1d64wb_register: 2159 case ARM::VLD1q8wb_fixed: 2160 case ARM::VLD1q16wb_fixed: 2161 case ARM::VLD1q32wb_fixed: 2162 case ARM::VLD1q64wb_fixed: 2163 case ARM::VLD1q8wb_register: 2164 case ARM::VLD1q16wb_register: 2165 case ARM::VLD1q32wb_register: 2166 case ARM::VLD1q64wb_register: 2167 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2168 // variant encodes Rm == 0xf. Anything else is a register offset post- 2169 // increment and we need to add the register operand to the instruction. 2170 if (Rm != 0xD && Rm != 0xF && 2171 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2172 return MCDisassembler::Fail; 2173 break; 2174 } 2175 2176 return S; 2177 } 2178 2179 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 2180 uint64_t Address, const void *Decoder) { 2181 DecodeStatus S = MCDisassembler::Success; 2182 2183 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2184 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2185 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 2186 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2187 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 2188 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2189 2190 // Writeback Operand 2191 switch (Inst.getOpcode()) { 2192 case ARM::VST1d8wb_fixed: 2193 case ARM::VST1d16wb_fixed: 2194 case ARM::VST1d32wb_fixed: 2195 case ARM::VST1d64wb_fixed: 2196 case ARM::VST1d8wb_register: 2197 case ARM::VST1d16wb_register: 2198 case ARM::VST1d32wb_register: 2199 case ARM::VST1d64wb_register: 2200 case ARM::VST1q8wb_fixed: 2201 case ARM::VST1q16wb_fixed: 2202 case ARM::VST1q32wb_fixed: 2203 case ARM::VST1q64wb_fixed: 2204 case ARM::VST1q8wb_register: 2205 case ARM::VST1q16wb_register: 2206 case ARM::VST1q32wb_register: 2207 case ARM::VST1q64wb_register: 2208 case ARM::VST1d8Twb_fixed: 2209 case ARM::VST1d16Twb_fixed: 2210 case ARM::VST1d32Twb_fixed: 2211 case ARM::VST1d64Twb_fixed: 2212 case ARM::VST1d8Twb_register: 2213 case ARM::VST1d16Twb_register: 2214 case ARM::VST1d32Twb_register: 2215 case ARM::VST1d64Twb_register: 2216 case ARM::VST1d8Qwb_fixed: 2217 case ARM::VST1d16Qwb_fixed: 2218 case ARM::VST1d32Qwb_fixed: 2219 case ARM::VST1d64Qwb_fixed: 2220 case ARM::VST1d8Qwb_register: 2221 case ARM::VST1d16Qwb_register: 2222 case ARM::VST1d32Qwb_register: 2223 case ARM::VST1d64Qwb_register: 2224 case ARM::VST2d8wb_fixed: 2225 case ARM::VST2d16wb_fixed: 2226 case ARM::VST2d32wb_fixed: 2227 case ARM::VST2d8wb_register: 2228 case ARM::VST2d16wb_register: 2229 case ARM::VST2d32wb_register: 2230 case ARM::VST2q8wb_fixed: 2231 case ARM::VST2q16wb_fixed: 2232 case ARM::VST2q32wb_fixed: 2233 case ARM::VST2q8wb_register: 2234 case ARM::VST2q16wb_register: 2235 case ARM::VST2q32wb_register: 2236 case ARM::VST2b8wb_fixed: 2237 case ARM::VST2b16wb_fixed: 2238 case ARM::VST2b32wb_fixed: 2239 case ARM::VST2b8wb_register: 2240 case ARM::VST2b16wb_register: 2241 case ARM::VST2b32wb_register: 2242 case ARM::VST3d8_UPD: 2243 case ARM::VST3d16_UPD: 2244 case ARM::VST3d32_UPD: 2245 case ARM::VST3q8_UPD: 2246 case ARM::VST3q16_UPD: 2247 case ARM::VST3q32_UPD: 2248 case ARM::VST4d8_UPD: 2249 case ARM::VST4d16_UPD: 2250 case ARM::VST4d32_UPD: 2251 case ARM::VST4q8_UPD: 2252 case ARM::VST4q16_UPD: 2253 case ARM::VST4q32_UPD: 2254 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2255 return MCDisassembler::Fail; 2256 break; 2257 default: 2258 break; 2259 } 2260 2261 // AddrMode6 Base (register+alignment) 2262 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2263 return MCDisassembler::Fail; 2264 2265 // AddrMode6 Offset (register) 2266 switch (Inst.getOpcode()) { 2267 default: 2268 if (Rm == 0xD) 2269 Inst.addOperand(MCOperand::CreateReg(0)); 2270 else if (Rm != 0xF) { 2271 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2272 return MCDisassembler::Fail; 2273 } 2274 break; 2275 case ARM::VST1d8wb_fixed: 2276 case ARM::VST1d16wb_fixed: 2277 case ARM::VST1d32wb_fixed: 2278 case ARM::VST1d64wb_fixed: 2279 case ARM::VST1q8wb_fixed: 2280 case ARM::VST1q16wb_fixed: 2281 case ARM::VST1q32wb_fixed: 2282 case ARM::VST1q64wb_fixed: 2283 break; 2284 } 2285 2286 2287 // First input register 2288 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2289 return MCDisassembler::Fail; 2290 2291 // Second input register 2292 switch (Inst.getOpcode()) { 2293 case ARM::VST3d8: 2294 case ARM::VST3d16: 2295 case ARM::VST3d32: 2296 case ARM::VST3d8_UPD: 2297 case ARM::VST3d16_UPD: 2298 case ARM::VST3d32_UPD: 2299 case ARM::VST4d8: 2300 case ARM::VST4d16: 2301 case ARM::VST4d32: 2302 case ARM::VST4d8_UPD: 2303 case ARM::VST4d16_UPD: 2304 case ARM::VST4d32_UPD: 2305 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2306 return MCDisassembler::Fail; 2307 break; 2308 case ARM::VST3q8: 2309 case ARM::VST3q16: 2310 case ARM::VST3q32: 2311 case ARM::VST3q8_UPD: 2312 case ARM::VST3q16_UPD: 2313 case ARM::VST3q32_UPD: 2314 case ARM::VST4q8: 2315 case ARM::VST4q16: 2316 case ARM::VST4q32: 2317 case ARM::VST4q8_UPD: 2318 case ARM::VST4q16_UPD: 2319 case ARM::VST4q32_UPD: 2320 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2321 return MCDisassembler::Fail; 2322 break; 2323 default: 2324 break; 2325 } 2326 2327 // Third input register 2328 switch (Inst.getOpcode()) { 2329 case ARM::VST3d8: 2330 case ARM::VST3d16: 2331 case ARM::VST3d32: 2332 case ARM::VST3d8_UPD: 2333 case ARM::VST3d16_UPD: 2334 case ARM::VST3d32_UPD: 2335 case ARM::VST4d8: 2336 case ARM::VST4d16: 2337 case ARM::VST4d32: 2338 case ARM::VST4d8_UPD: 2339 case ARM::VST4d16_UPD: 2340 case ARM::VST4d32_UPD: 2341 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2342 return MCDisassembler::Fail; 2343 break; 2344 case ARM::VST3q8: 2345 case ARM::VST3q16: 2346 case ARM::VST3q32: 2347 case ARM::VST3q8_UPD: 2348 case ARM::VST3q16_UPD: 2349 case ARM::VST3q32_UPD: 2350 case ARM::VST4q8: 2351 case ARM::VST4q16: 2352 case ARM::VST4q32: 2353 case ARM::VST4q8_UPD: 2354 case ARM::VST4q16_UPD: 2355 case ARM::VST4q32_UPD: 2356 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2357 return MCDisassembler::Fail; 2358 break; 2359 default: 2360 break; 2361 } 2362 2363 // Fourth input register 2364 switch (Inst.getOpcode()) { 2365 case ARM::VST4d8: 2366 case ARM::VST4d16: 2367 case ARM::VST4d32: 2368 case ARM::VST4d8_UPD: 2369 case ARM::VST4d16_UPD: 2370 case ARM::VST4d32_UPD: 2371 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2372 return MCDisassembler::Fail; 2373 break; 2374 case ARM::VST4q8: 2375 case ARM::VST4q16: 2376 case ARM::VST4q32: 2377 case ARM::VST4q8_UPD: 2378 case ARM::VST4q16_UPD: 2379 case ARM::VST4q32_UPD: 2380 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2381 return MCDisassembler::Fail; 2382 break; 2383 default: 2384 break; 2385 } 2386 2387 return S; 2388 } 2389 2390 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2391 uint64_t Address, const void *Decoder) { 2392 DecodeStatus S = MCDisassembler::Success; 2393 2394 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2395 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2396 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2397 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2398 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2399 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2400 2401 align *= (1 << size); 2402 2403 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2404 return MCDisassembler::Fail; 2405 if (Rm != 0xF) { 2406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2407 return MCDisassembler::Fail; 2408 } 2409 2410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2411 return MCDisassembler::Fail; 2412 Inst.addOperand(MCOperand::CreateImm(align)); 2413 2414 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2415 // variant encodes Rm == 0xf. Anything else is a register offset post- 2416 // increment and we need to add the register operand to the instruction. 2417 if (Rm != 0xD && Rm != 0xF && 2418 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2419 return MCDisassembler::Fail; 2420 2421 return S; 2422 } 2423 2424 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2425 uint64_t Address, const void *Decoder) { 2426 DecodeStatus S = MCDisassembler::Success; 2427 2428 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2429 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2430 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2431 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2432 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2433 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 2434 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2435 align *= 2*size; 2436 2437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2438 return MCDisassembler::Fail; 2439 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2440 return MCDisassembler::Fail; 2441 if (Rm != 0xF) { 2442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2443 return MCDisassembler::Fail; 2444 } 2445 2446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2447 return MCDisassembler::Fail; 2448 Inst.addOperand(MCOperand::CreateImm(align)); 2449 2450 if (Rm == 0xD) 2451 Inst.addOperand(MCOperand::CreateReg(0)); 2452 else if (Rm != 0xF) { 2453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2454 return MCDisassembler::Fail; 2455 } 2456 2457 return S; 2458 } 2459 2460 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2461 uint64_t Address, const void *Decoder) { 2462 DecodeStatus S = MCDisassembler::Success; 2463 2464 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2465 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2466 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2467 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2468 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2469 2470 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2471 return MCDisassembler::Fail; 2472 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2473 return MCDisassembler::Fail; 2474 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2475 return MCDisassembler::Fail; 2476 if (Rm != 0xF) { 2477 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2478 return MCDisassembler::Fail; 2479 } 2480 2481 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2482 return MCDisassembler::Fail; 2483 Inst.addOperand(MCOperand::CreateImm(0)); 2484 2485 if (Rm == 0xD) 2486 Inst.addOperand(MCOperand::CreateReg(0)); 2487 else if (Rm != 0xF) { 2488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2489 return MCDisassembler::Fail; 2490 } 2491 2492 return S; 2493 } 2494 2495 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2496 uint64_t Address, const void *Decoder) { 2497 DecodeStatus S = MCDisassembler::Success; 2498 2499 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2500 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2501 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2502 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2503 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2504 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2505 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2506 2507 if (size == 0x3) { 2508 size = 4; 2509 align = 16; 2510 } else { 2511 if (size == 2) { 2512 size = 1 << size; 2513 align *= 8; 2514 } else { 2515 size = 1 << size; 2516 align *= 4*size; 2517 } 2518 } 2519 2520 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2521 return MCDisassembler::Fail; 2522 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2523 return MCDisassembler::Fail; 2524 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2525 return MCDisassembler::Fail; 2526 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2527 return MCDisassembler::Fail; 2528 if (Rm != 0xF) { 2529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2530 return MCDisassembler::Fail; 2531 } 2532 2533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 Inst.addOperand(MCOperand::CreateImm(align)); 2536 2537 if (Rm == 0xD) 2538 Inst.addOperand(MCOperand::CreateReg(0)); 2539 else if (Rm != 0xF) { 2540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2541 return MCDisassembler::Fail; 2542 } 2543 2544 return S; 2545 } 2546 2547 static DecodeStatus 2548 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2549 uint64_t Address, const void *Decoder) { 2550 DecodeStatus S = MCDisassembler::Success; 2551 2552 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2553 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2554 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2555 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2556 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2557 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2558 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2559 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2560 2561 if (Q) { 2562 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2563 return MCDisassembler::Fail; 2564 } else { 2565 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2566 return MCDisassembler::Fail; 2567 } 2568 2569 Inst.addOperand(MCOperand::CreateImm(imm)); 2570 2571 switch (Inst.getOpcode()) { 2572 case ARM::VORRiv4i16: 2573 case ARM::VORRiv2i32: 2574 case ARM::VBICiv4i16: 2575 case ARM::VBICiv2i32: 2576 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2577 return MCDisassembler::Fail; 2578 break; 2579 case ARM::VORRiv8i16: 2580 case ARM::VORRiv4i32: 2581 case ARM::VBICiv8i16: 2582 case ARM::VBICiv4i32: 2583 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2584 return MCDisassembler::Fail; 2585 break; 2586 default: 2587 break; 2588 } 2589 2590 return S; 2591 } 2592 2593 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2594 uint64_t Address, const void *Decoder) { 2595 DecodeStatus S = MCDisassembler::Success; 2596 2597 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2598 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2599 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2600 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2601 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2602 2603 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 2604 return MCDisassembler::Fail; 2605 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2606 return MCDisassembler::Fail; 2607 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2608 2609 return S; 2610 } 2611 2612 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2613 uint64_t Address, const void *Decoder) { 2614 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2615 return MCDisassembler::Success; 2616 } 2617 2618 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2619 uint64_t Address, const void *Decoder) { 2620 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2621 return MCDisassembler::Success; 2622 } 2623 2624 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2625 uint64_t Address, const void *Decoder) { 2626 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2627 return MCDisassembler::Success; 2628 } 2629 2630 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2631 uint64_t Address, const void *Decoder) { 2632 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2633 return MCDisassembler::Success; 2634 } 2635 2636 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2637 uint64_t Address, const void *Decoder) { 2638 DecodeStatus S = MCDisassembler::Success; 2639 2640 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2641 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2642 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2643 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2644 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2645 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2646 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2647 2648 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2649 return MCDisassembler::Fail; 2650 if (op) { 2651 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2652 return MCDisassembler::Fail; // Writeback 2653 } 2654 2655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 2656 return MCDisassembler::Fail; 2657 2658 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 2659 return MCDisassembler::Fail; 2660 2661 return S; 2662 } 2663 2664 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2665 uint64_t Address, const void *Decoder) { 2666 DecodeStatus S = MCDisassembler::Success; 2667 2668 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2669 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2670 2671 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 2672 return MCDisassembler::Fail; 2673 2674 switch(Inst.getOpcode()) { 2675 default: 2676 return MCDisassembler::Fail; 2677 case ARM::tADR: 2678 break; // tADR does not explicitly represent the PC as an operand. 2679 case ARM::tADDrSPi: 2680 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2681 break; 2682 } 2683 2684 Inst.addOperand(MCOperand::CreateImm(imm)); 2685 return S; 2686 } 2687 2688 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2689 uint64_t Address, const void *Decoder) { 2690 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2691 return MCDisassembler::Success; 2692 } 2693 2694 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2695 uint64_t Address, const void *Decoder) { 2696 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2697 return MCDisassembler::Success; 2698 } 2699 2700 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2701 uint64_t Address, const void *Decoder) { 2702 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2703 return MCDisassembler::Success; 2704 } 2705 2706 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2707 uint64_t Address, const void *Decoder) { 2708 DecodeStatus S = MCDisassembler::Success; 2709 2710 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2711 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2712 2713 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2714 return MCDisassembler::Fail; 2715 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 2716 return MCDisassembler::Fail; 2717 2718 return S; 2719 } 2720 2721 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2722 uint64_t Address, const void *Decoder) { 2723 DecodeStatus S = MCDisassembler::Success; 2724 2725 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2726 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2727 2728 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 2729 return MCDisassembler::Fail; 2730 Inst.addOperand(MCOperand::CreateImm(imm)); 2731 2732 return S; 2733 } 2734 2735 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2736 uint64_t Address, const void *Decoder) { 2737 unsigned imm = Val << 2; 2738 2739 Inst.addOperand(MCOperand::CreateImm(imm)); 2740 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 2741 2742 return MCDisassembler::Success; 2743 } 2744 2745 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2746 uint64_t Address, const void *Decoder) { 2747 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2748 Inst.addOperand(MCOperand::CreateImm(Val)); 2749 2750 return MCDisassembler::Success; 2751 } 2752 2753 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2754 uint64_t Address, const void *Decoder) { 2755 DecodeStatus S = MCDisassembler::Success; 2756 2757 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2758 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2759 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2760 2761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2762 return MCDisassembler::Fail; 2763 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 2764 return MCDisassembler::Fail; 2765 Inst.addOperand(MCOperand::CreateImm(imm)); 2766 2767 return S; 2768 } 2769 2770 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2771 uint64_t Address, const void *Decoder) { 2772 DecodeStatus S = MCDisassembler::Success; 2773 2774 switch (Inst.getOpcode()) { 2775 case ARM::t2PLDs: 2776 case ARM::t2PLDWs: 2777 case ARM::t2PLIs: 2778 break; 2779 default: { 2780 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2781 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2782 return MCDisassembler::Fail; 2783 } 2784 } 2785 2786 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2787 if (Rn == 0xF) { 2788 switch (Inst.getOpcode()) { 2789 case ARM::t2LDRBs: 2790 Inst.setOpcode(ARM::t2LDRBpci); 2791 break; 2792 case ARM::t2LDRHs: 2793 Inst.setOpcode(ARM::t2LDRHpci); 2794 break; 2795 case ARM::t2LDRSHs: 2796 Inst.setOpcode(ARM::t2LDRSHpci); 2797 break; 2798 case ARM::t2LDRSBs: 2799 Inst.setOpcode(ARM::t2LDRSBpci); 2800 break; 2801 case ARM::t2PLDs: 2802 Inst.setOpcode(ARM::t2PLDi12); 2803 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2804 break; 2805 default: 2806 return MCDisassembler::Fail; 2807 } 2808 2809 int imm = fieldFromInstruction32(Insn, 0, 12); 2810 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2811 Inst.addOperand(MCOperand::CreateImm(imm)); 2812 2813 return S; 2814 } 2815 2816 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2817 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2818 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2819 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 2820 return MCDisassembler::Fail; 2821 2822 return S; 2823 } 2824 2825 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2826 uint64_t Address, const void *Decoder) { 2827 int imm = Val & 0xFF; 2828 if (!(Val & 0x100)) imm *= -1; 2829 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2830 2831 return MCDisassembler::Success; 2832 } 2833 2834 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2835 uint64_t Address, const void *Decoder) { 2836 DecodeStatus S = MCDisassembler::Success; 2837 2838 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2839 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2840 2841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2842 return MCDisassembler::Fail; 2843 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 2844 return MCDisassembler::Fail; 2845 2846 return S; 2847 } 2848 2849 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val, 2850 uint64_t Address, const void *Decoder) { 2851 DecodeStatus S = MCDisassembler::Success; 2852 2853 unsigned Rn = fieldFromInstruction32(Val, 8, 4); 2854 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2855 2856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2857 return MCDisassembler::Fail; 2858 2859 Inst.addOperand(MCOperand::CreateImm(imm)); 2860 2861 return S; 2862 } 2863 2864 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2865 uint64_t Address, const void *Decoder) { 2866 int imm = Val & 0xFF; 2867 if (Val == 0) 2868 imm = INT32_MIN; 2869 else if (!(Val & 0x100)) 2870 imm *= -1; 2871 Inst.addOperand(MCOperand::CreateImm(imm)); 2872 2873 return MCDisassembler::Success; 2874 } 2875 2876 2877 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2878 uint64_t Address, const void *Decoder) { 2879 DecodeStatus S = MCDisassembler::Success; 2880 2881 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2882 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2883 2884 // Some instructions always use an additive offset. 2885 switch (Inst.getOpcode()) { 2886 case ARM::t2LDRT: 2887 case ARM::t2LDRBT: 2888 case ARM::t2LDRHT: 2889 case ARM::t2LDRSBT: 2890 case ARM::t2LDRSHT: 2891 case ARM::t2STRT: 2892 case ARM::t2STRBT: 2893 case ARM::t2STRHT: 2894 imm |= 0x100; 2895 break; 2896 default: 2897 break; 2898 } 2899 2900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2901 return MCDisassembler::Fail; 2902 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 2903 return MCDisassembler::Fail; 2904 2905 return S; 2906 } 2907 2908 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, 2909 uint64_t Address, const void *Decoder) { 2910 DecodeStatus S = MCDisassembler::Success; 2911 2912 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2913 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2914 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 2915 addr |= fieldFromInstruction32(Insn, 9, 1) << 8; 2916 addr |= Rn << 9; 2917 unsigned load = fieldFromInstruction32(Insn, 20, 1); 2918 2919 if (!load) { 2920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2921 return MCDisassembler::Fail; 2922 } 2923 2924 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 2925 return MCDisassembler::Fail; 2926 2927 if (load) { 2928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2929 return MCDisassembler::Fail; 2930 } 2931 2932 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 2933 return MCDisassembler::Fail; 2934 2935 return S; 2936 } 2937 2938 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2939 uint64_t Address, const void *Decoder) { 2940 DecodeStatus S = MCDisassembler::Success; 2941 2942 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2943 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2944 2945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2946 return MCDisassembler::Fail; 2947 Inst.addOperand(MCOperand::CreateImm(imm)); 2948 2949 return S; 2950 } 2951 2952 2953 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2954 uint64_t Address, const void *Decoder) { 2955 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2956 2957 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2958 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2959 Inst.addOperand(MCOperand::CreateImm(imm)); 2960 2961 return MCDisassembler::Success; 2962 } 2963 2964 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2965 uint64_t Address, const void *Decoder) { 2966 DecodeStatus S = MCDisassembler::Success; 2967 2968 if (Inst.getOpcode() == ARM::tADDrSP) { 2969 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2970 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2971 2972 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2973 return MCDisassembler::Fail; 2974 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 2975 return MCDisassembler::Fail; 2976 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2977 } else if (Inst.getOpcode() == ARM::tADDspr) { 2978 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2979 2980 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2981 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2982 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2983 return MCDisassembler::Fail; 2984 } 2985 2986 return S; 2987 } 2988 2989 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2990 uint64_t Address, const void *Decoder) { 2991 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2992 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2993 2994 Inst.addOperand(MCOperand::CreateImm(imod)); 2995 Inst.addOperand(MCOperand::CreateImm(flags)); 2996 2997 return MCDisassembler::Success; 2998 } 2999 3000 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 3001 uint64_t Address, const void *Decoder) { 3002 DecodeStatus S = MCDisassembler::Success; 3003 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3004 unsigned add = fieldFromInstruction32(Insn, 4, 1); 3005 3006 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3007 return MCDisassembler::Fail; 3008 Inst.addOperand(MCOperand::CreateImm(add)); 3009 3010 return S; 3011 } 3012 3013 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 3014 uint64_t Address, const void *Decoder) { 3015 if (!tryAddingSymbolicOperand(Address, 3016 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4, 3017 true, 4, Inst, Decoder)) 3018 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3019 return MCDisassembler::Success; 3020 } 3021 3022 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 3023 uint64_t Address, const void *Decoder) { 3024 if (Val == 0xA || Val == 0xB) 3025 return MCDisassembler::Fail; 3026 3027 Inst.addOperand(MCOperand::CreateImm(Val)); 3028 return MCDisassembler::Success; 3029 } 3030 3031 static DecodeStatus 3032 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, 3033 uint64_t Address, const void *Decoder) { 3034 DecodeStatus S = MCDisassembler::Success; 3035 3036 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3037 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3038 3039 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3041 return MCDisassembler::Fail; 3042 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3043 return MCDisassembler::Fail; 3044 return S; 3045 } 3046 3047 static DecodeStatus 3048 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 3049 uint64_t Address, const void *Decoder) { 3050 DecodeStatus S = MCDisassembler::Success; 3051 3052 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 3053 if (pred == 0xE || pred == 0xF) { 3054 unsigned opc = fieldFromInstruction32(Insn, 4, 28); 3055 switch (opc) { 3056 default: 3057 return MCDisassembler::Fail; 3058 case 0xf3bf8f4: 3059 Inst.setOpcode(ARM::t2DSB); 3060 break; 3061 case 0xf3bf8f5: 3062 Inst.setOpcode(ARM::t2DMB); 3063 break; 3064 case 0xf3bf8f6: 3065 Inst.setOpcode(ARM::t2ISB); 3066 break; 3067 } 3068 3069 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 3070 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3071 } 3072 3073 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 3074 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 3075 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 3076 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 3077 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 3078 3079 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3080 return MCDisassembler::Fail; 3081 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3082 return MCDisassembler::Fail; 3083 3084 return S; 3085 } 3086 3087 // Decode a shifted immediate operand. These basically consist 3088 // of an 8-bit value, and a 4-bit directive that specifies either 3089 // a splat operation or a rotation. 3090 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 3091 uint64_t Address, const void *Decoder) { 3092 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 3093 if (ctrl == 0) { 3094 unsigned byte = fieldFromInstruction32(Val, 8, 2); 3095 unsigned imm = fieldFromInstruction32(Val, 0, 8); 3096 switch (byte) { 3097 case 0: 3098 Inst.addOperand(MCOperand::CreateImm(imm)); 3099 break; 3100 case 1: 3101 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3102 break; 3103 case 2: 3104 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3105 break; 3106 case 3: 3107 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3108 (imm << 8) | imm)); 3109 break; 3110 } 3111 } else { 3112 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 3113 unsigned rot = fieldFromInstruction32(Val, 7, 5); 3114 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3115 Inst.addOperand(MCOperand::CreateImm(imm)); 3116 } 3117 3118 return MCDisassembler::Success; 3119 } 3120 3121 static DecodeStatus 3122 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 3123 uint64_t Address, const void *Decoder){ 3124 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3125 return MCDisassembler::Success; 3126 } 3127 3128 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 3129 uint64_t Address, const void *Decoder){ 3130 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<22>(Val<<1) + 4, 3131 true, 4, Inst, Decoder)) 3132 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 3133 return MCDisassembler::Success; 3134 } 3135 3136 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 3137 uint64_t Address, const void *Decoder) { 3138 switch (Val) { 3139 default: 3140 return MCDisassembler::Fail; 3141 case 0xF: // SY 3142 case 0xE: // ST 3143 case 0xB: // ISH 3144 case 0xA: // ISHST 3145 case 0x7: // NSH 3146 case 0x6: // NSHST 3147 case 0x3: // OSH 3148 case 0x2: // OSHST 3149 break; 3150 } 3151 3152 Inst.addOperand(MCOperand::CreateImm(Val)); 3153 return MCDisassembler::Success; 3154 } 3155 3156 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 3157 uint64_t Address, const void *Decoder) { 3158 if (!Val) return MCDisassembler::Fail; 3159 Inst.addOperand(MCOperand::CreateImm(Val)); 3160 return MCDisassembler::Success; 3161 } 3162 3163 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 3164 uint64_t Address, const void *Decoder) { 3165 DecodeStatus S = MCDisassembler::Success; 3166 3167 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3168 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3169 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3170 3171 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3172 3173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3174 return MCDisassembler::Fail; 3175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3176 return MCDisassembler::Fail; 3177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3178 return MCDisassembler::Fail; 3179 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3180 return MCDisassembler::Fail; 3181 3182 return S; 3183 } 3184 3185 3186 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 3187 uint64_t Address, const void *Decoder){ 3188 DecodeStatus S = MCDisassembler::Success; 3189 3190 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3191 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 3192 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3193 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3194 3195 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 3196 return MCDisassembler::Fail; 3197 3198 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail; 3199 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail; 3200 3201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3202 return MCDisassembler::Fail; 3203 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 3204 return MCDisassembler::Fail; 3205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3206 return MCDisassembler::Fail; 3207 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3208 return MCDisassembler::Fail; 3209 3210 return S; 3211 } 3212 3213 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, 3214 uint64_t Address, const void *Decoder) { 3215 DecodeStatus S = MCDisassembler::Success; 3216 3217 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3218 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3219 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3220 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3221 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3222 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3223 3224 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3225 3226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3227 return MCDisassembler::Fail; 3228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3229 return MCDisassembler::Fail; 3230 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3231 return MCDisassembler::Fail; 3232 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3233 return MCDisassembler::Fail; 3234 3235 return S; 3236 } 3237 3238 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, 3239 uint64_t Address, const void *Decoder) { 3240 DecodeStatus S = MCDisassembler::Success; 3241 3242 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3243 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3244 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3245 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3246 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3247 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3248 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3249 3250 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3251 if (Rm == 0xF) S = MCDisassembler::SoftFail; 3252 3253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3254 return MCDisassembler::Fail; 3255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3256 return MCDisassembler::Fail; 3257 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3258 return MCDisassembler::Fail; 3259 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3260 return MCDisassembler::Fail; 3261 3262 return S; 3263 } 3264 3265 3266 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 3267 uint64_t Address, const void *Decoder) { 3268 DecodeStatus S = MCDisassembler::Success; 3269 3270 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3271 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3272 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3273 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3274 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3275 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3276 3277 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3278 3279 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3280 return MCDisassembler::Fail; 3281 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3282 return MCDisassembler::Fail; 3283 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 3284 return MCDisassembler::Fail; 3285 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3286 return MCDisassembler::Fail; 3287 3288 return S; 3289 } 3290 3291 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 3292 uint64_t Address, const void *Decoder) { 3293 DecodeStatus S = MCDisassembler::Success; 3294 3295 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3296 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3297 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 3298 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 3299 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 3300 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3301 3302 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 3303 3304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3305 return MCDisassembler::Fail; 3306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3307 return MCDisassembler::Fail; 3308 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 3309 return MCDisassembler::Fail; 3310 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3311 return MCDisassembler::Fail; 3312 3313 return S; 3314 } 3315 3316 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 3317 uint64_t Address, const void *Decoder) { 3318 DecodeStatus S = MCDisassembler::Success; 3319 3320 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3321 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3322 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3323 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3324 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3325 3326 unsigned align = 0; 3327 unsigned index = 0; 3328 switch (size) { 3329 default: 3330 return MCDisassembler::Fail; 3331 case 0: 3332 if (fieldFromInstruction32(Insn, 4, 1)) 3333 return MCDisassembler::Fail; // UNDEFINED 3334 index = fieldFromInstruction32(Insn, 5, 3); 3335 break; 3336 case 1: 3337 if (fieldFromInstruction32(Insn, 5, 1)) 3338 return MCDisassembler::Fail; // UNDEFINED 3339 index = fieldFromInstruction32(Insn, 6, 2); 3340 if (fieldFromInstruction32(Insn, 4, 1)) 3341 align = 2; 3342 break; 3343 case 2: 3344 if (fieldFromInstruction32(Insn, 6, 1)) 3345 return MCDisassembler::Fail; // UNDEFINED 3346 index = fieldFromInstruction32(Insn, 7, 1); 3347 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3348 align = 4; 3349 } 3350 3351 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3352 return MCDisassembler::Fail; 3353 if (Rm != 0xF) { // Writeback 3354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3355 return MCDisassembler::Fail; 3356 } 3357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3358 return MCDisassembler::Fail; 3359 Inst.addOperand(MCOperand::CreateImm(align)); 3360 if (Rm != 0xF) { 3361 if (Rm != 0xD) { 3362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3363 return MCDisassembler::Fail; 3364 } else 3365 Inst.addOperand(MCOperand::CreateReg(0)); 3366 } 3367 3368 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3369 return MCDisassembler::Fail; 3370 Inst.addOperand(MCOperand::CreateImm(index)); 3371 3372 return S; 3373 } 3374 3375 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 3376 uint64_t Address, const void *Decoder) { 3377 DecodeStatus S = MCDisassembler::Success; 3378 3379 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3380 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3381 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3382 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3383 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3384 3385 unsigned align = 0; 3386 unsigned index = 0; 3387 switch (size) { 3388 default: 3389 return MCDisassembler::Fail; 3390 case 0: 3391 if (fieldFromInstruction32(Insn, 4, 1)) 3392 return MCDisassembler::Fail; // UNDEFINED 3393 index = fieldFromInstruction32(Insn, 5, 3); 3394 break; 3395 case 1: 3396 if (fieldFromInstruction32(Insn, 5, 1)) 3397 return MCDisassembler::Fail; // UNDEFINED 3398 index = fieldFromInstruction32(Insn, 6, 2); 3399 if (fieldFromInstruction32(Insn, 4, 1)) 3400 align = 2; 3401 break; 3402 case 2: 3403 if (fieldFromInstruction32(Insn, 6, 1)) 3404 return MCDisassembler::Fail; // UNDEFINED 3405 index = fieldFromInstruction32(Insn, 7, 1); 3406 if (fieldFromInstruction32(Insn, 4, 2) != 0) 3407 align = 4; 3408 } 3409 3410 if (Rm != 0xF) { // Writeback 3411 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3412 return MCDisassembler::Fail; 3413 } 3414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3415 return MCDisassembler::Fail; 3416 Inst.addOperand(MCOperand::CreateImm(align)); 3417 if (Rm != 0xF) { 3418 if (Rm != 0xD) { 3419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3420 return MCDisassembler::Fail; 3421 } else 3422 Inst.addOperand(MCOperand::CreateReg(0)); 3423 } 3424 3425 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3426 return MCDisassembler::Fail; 3427 Inst.addOperand(MCOperand::CreateImm(index)); 3428 3429 return S; 3430 } 3431 3432 3433 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 3434 uint64_t Address, const void *Decoder) { 3435 DecodeStatus S = MCDisassembler::Success; 3436 3437 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3438 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3439 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3440 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3441 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3442 3443 unsigned align = 0; 3444 unsigned index = 0; 3445 unsigned inc = 1; 3446 switch (size) { 3447 default: 3448 return MCDisassembler::Fail; 3449 case 0: 3450 index = fieldFromInstruction32(Insn, 5, 3); 3451 if (fieldFromInstruction32(Insn, 4, 1)) 3452 align = 2; 3453 break; 3454 case 1: 3455 index = fieldFromInstruction32(Insn, 6, 2); 3456 if (fieldFromInstruction32(Insn, 4, 1)) 3457 align = 4; 3458 if (fieldFromInstruction32(Insn, 5, 1)) 3459 inc = 2; 3460 break; 3461 case 2: 3462 if (fieldFromInstruction32(Insn, 5, 1)) 3463 return MCDisassembler::Fail; // UNDEFINED 3464 index = fieldFromInstruction32(Insn, 7, 1); 3465 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3466 align = 8; 3467 if (fieldFromInstruction32(Insn, 6, 1)) 3468 inc = 2; 3469 break; 3470 } 3471 3472 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3473 return MCDisassembler::Fail; 3474 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3475 return MCDisassembler::Fail; 3476 if (Rm != 0xF) { // Writeback 3477 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3478 return MCDisassembler::Fail; 3479 } 3480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3481 return MCDisassembler::Fail; 3482 Inst.addOperand(MCOperand::CreateImm(align)); 3483 if (Rm != 0xF) { 3484 if (Rm != 0xD) { 3485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3486 return MCDisassembler::Fail; 3487 } else 3488 Inst.addOperand(MCOperand::CreateReg(0)); 3489 } 3490 3491 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3492 return MCDisassembler::Fail; 3493 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3494 return MCDisassembler::Fail; 3495 Inst.addOperand(MCOperand::CreateImm(index)); 3496 3497 return S; 3498 } 3499 3500 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 3501 uint64_t Address, const void *Decoder) { 3502 DecodeStatus S = MCDisassembler::Success; 3503 3504 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3505 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3506 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3507 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3508 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3509 3510 unsigned align = 0; 3511 unsigned index = 0; 3512 unsigned inc = 1; 3513 switch (size) { 3514 default: 3515 return MCDisassembler::Fail; 3516 case 0: 3517 index = fieldFromInstruction32(Insn, 5, 3); 3518 if (fieldFromInstruction32(Insn, 4, 1)) 3519 align = 2; 3520 break; 3521 case 1: 3522 index = fieldFromInstruction32(Insn, 6, 2); 3523 if (fieldFromInstruction32(Insn, 4, 1)) 3524 align = 4; 3525 if (fieldFromInstruction32(Insn, 5, 1)) 3526 inc = 2; 3527 break; 3528 case 2: 3529 if (fieldFromInstruction32(Insn, 5, 1)) 3530 return MCDisassembler::Fail; // UNDEFINED 3531 index = fieldFromInstruction32(Insn, 7, 1); 3532 if (fieldFromInstruction32(Insn, 4, 1) != 0) 3533 align = 8; 3534 if (fieldFromInstruction32(Insn, 6, 1)) 3535 inc = 2; 3536 break; 3537 } 3538 3539 if (Rm != 0xF) { // Writeback 3540 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3541 return MCDisassembler::Fail; 3542 } 3543 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3544 return MCDisassembler::Fail; 3545 Inst.addOperand(MCOperand::CreateImm(align)); 3546 if (Rm != 0xF) { 3547 if (Rm != 0xD) { 3548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3549 return MCDisassembler::Fail; 3550 } else 3551 Inst.addOperand(MCOperand::CreateReg(0)); 3552 } 3553 3554 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3555 return MCDisassembler::Fail; 3556 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3557 return MCDisassembler::Fail; 3558 Inst.addOperand(MCOperand::CreateImm(index)); 3559 3560 return S; 3561 } 3562 3563 3564 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 3565 uint64_t Address, const void *Decoder) { 3566 DecodeStatus S = MCDisassembler::Success; 3567 3568 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3569 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3570 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3571 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3572 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3573 3574 unsigned align = 0; 3575 unsigned index = 0; 3576 unsigned inc = 1; 3577 switch (size) { 3578 default: 3579 return MCDisassembler::Fail; 3580 case 0: 3581 if (fieldFromInstruction32(Insn, 4, 1)) 3582 return MCDisassembler::Fail; // UNDEFINED 3583 index = fieldFromInstruction32(Insn, 5, 3); 3584 break; 3585 case 1: 3586 if (fieldFromInstruction32(Insn, 4, 1)) 3587 return MCDisassembler::Fail; // UNDEFINED 3588 index = fieldFromInstruction32(Insn, 6, 2); 3589 if (fieldFromInstruction32(Insn, 5, 1)) 3590 inc = 2; 3591 break; 3592 case 2: 3593 if (fieldFromInstruction32(Insn, 4, 2)) 3594 return MCDisassembler::Fail; // UNDEFINED 3595 index = fieldFromInstruction32(Insn, 7, 1); 3596 if (fieldFromInstruction32(Insn, 6, 1)) 3597 inc = 2; 3598 break; 3599 } 3600 3601 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3602 return MCDisassembler::Fail; 3603 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3604 return MCDisassembler::Fail; 3605 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3606 return MCDisassembler::Fail; 3607 3608 if (Rm != 0xF) { // Writeback 3609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3610 return MCDisassembler::Fail; 3611 } 3612 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3613 return MCDisassembler::Fail; 3614 Inst.addOperand(MCOperand::CreateImm(align)); 3615 if (Rm != 0xF) { 3616 if (Rm != 0xD) { 3617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3618 return MCDisassembler::Fail; 3619 } else 3620 Inst.addOperand(MCOperand::CreateReg(0)); 3621 } 3622 3623 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3624 return MCDisassembler::Fail; 3625 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3626 return MCDisassembler::Fail; 3627 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3628 return MCDisassembler::Fail; 3629 Inst.addOperand(MCOperand::CreateImm(index)); 3630 3631 return S; 3632 } 3633 3634 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 3635 uint64_t Address, const void *Decoder) { 3636 DecodeStatus S = MCDisassembler::Success; 3637 3638 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3639 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3640 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3641 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3642 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3643 3644 unsigned align = 0; 3645 unsigned index = 0; 3646 unsigned inc = 1; 3647 switch (size) { 3648 default: 3649 return MCDisassembler::Fail; 3650 case 0: 3651 if (fieldFromInstruction32(Insn, 4, 1)) 3652 return MCDisassembler::Fail; // UNDEFINED 3653 index = fieldFromInstruction32(Insn, 5, 3); 3654 break; 3655 case 1: 3656 if (fieldFromInstruction32(Insn, 4, 1)) 3657 return MCDisassembler::Fail; // UNDEFINED 3658 index = fieldFromInstruction32(Insn, 6, 2); 3659 if (fieldFromInstruction32(Insn, 5, 1)) 3660 inc = 2; 3661 break; 3662 case 2: 3663 if (fieldFromInstruction32(Insn, 4, 2)) 3664 return MCDisassembler::Fail; // UNDEFINED 3665 index = fieldFromInstruction32(Insn, 7, 1); 3666 if (fieldFromInstruction32(Insn, 6, 1)) 3667 inc = 2; 3668 break; 3669 } 3670 3671 if (Rm != 0xF) { // Writeback 3672 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3673 return MCDisassembler::Fail; 3674 } 3675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3676 return MCDisassembler::Fail; 3677 Inst.addOperand(MCOperand::CreateImm(align)); 3678 if (Rm != 0xF) { 3679 if (Rm != 0xD) { 3680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3681 return MCDisassembler::Fail; 3682 } else 3683 Inst.addOperand(MCOperand::CreateReg(0)); 3684 } 3685 3686 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3689 return MCDisassembler::Fail; 3690 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3691 return MCDisassembler::Fail; 3692 Inst.addOperand(MCOperand::CreateImm(index)); 3693 3694 return S; 3695 } 3696 3697 3698 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 3699 uint64_t Address, const void *Decoder) { 3700 DecodeStatus S = MCDisassembler::Success; 3701 3702 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3703 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3704 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3705 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3706 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3707 3708 unsigned align = 0; 3709 unsigned index = 0; 3710 unsigned inc = 1; 3711 switch (size) { 3712 default: 3713 return MCDisassembler::Fail; 3714 case 0: 3715 if (fieldFromInstruction32(Insn, 4, 1)) 3716 align = 4; 3717 index = fieldFromInstruction32(Insn, 5, 3); 3718 break; 3719 case 1: 3720 if (fieldFromInstruction32(Insn, 4, 1)) 3721 align = 8; 3722 index = fieldFromInstruction32(Insn, 6, 2); 3723 if (fieldFromInstruction32(Insn, 5, 1)) 3724 inc = 2; 3725 break; 3726 case 2: 3727 if (fieldFromInstruction32(Insn, 4, 2)) 3728 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3729 index = fieldFromInstruction32(Insn, 7, 1); 3730 if (fieldFromInstruction32(Insn, 6, 1)) 3731 inc = 2; 3732 break; 3733 } 3734 3735 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3736 return MCDisassembler::Fail; 3737 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3738 return MCDisassembler::Fail; 3739 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3740 return MCDisassembler::Fail; 3741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3742 return MCDisassembler::Fail; 3743 3744 if (Rm != 0xF) { // Writeback 3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3746 return MCDisassembler::Fail; 3747 } 3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3749 return MCDisassembler::Fail; 3750 Inst.addOperand(MCOperand::CreateImm(align)); 3751 if (Rm != 0xF) { 3752 if (Rm != 0xD) { 3753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3754 return MCDisassembler::Fail; 3755 } else 3756 Inst.addOperand(MCOperand::CreateReg(0)); 3757 } 3758 3759 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3760 return MCDisassembler::Fail; 3761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3762 return MCDisassembler::Fail; 3763 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3764 return MCDisassembler::Fail; 3765 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3766 return MCDisassembler::Fail; 3767 Inst.addOperand(MCOperand::CreateImm(index)); 3768 3769 return S; 3770 } 3771 3772 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3773 uint64_t Address, const void *Decoder) { 3774 DecodeStatus S = MCDisassembler::Success; 3775 3776 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3777 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3778 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3779 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3780 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3781 3782 unsigned align = 0; 3783 unsigned index = 0; 3784 unsigned inc = 1; 3785 switch (size) { 3786 default: 3787 return MCDisassembler::Fail; 3788 case 0: 3789 if (fieldFromInstruction32(Insn, 4, 1)) 3790 align = 4; 3791 index = fieldFromInstruction32(Insn, 5, 3); 3792 break; 3793 case 1: 3794 if (fieldFromInstruction32(Insn, 4, 1)) 3795 align = 8; 3796 index = fieldFromInstruction32(Insn, 6, 2); 3797 if (fieldFromInstruction32(Insn, 5, 1)) 3798 inc = 2; 3799 break; 3800 case 2: 3801 if (fieldFromInstruction32(Insn, 4, 2)) 3802 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3803 index = fieldFromInstruction32(Insn, 7, 1); 3804 if (fieldFromInstruction32(Insn, 6, 1)) 3805 inc = 2; 3806 break; 3807 } 3808 3809 if (Rm != 0xF) { // Writeback 3810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3811 return MCDisassembler::Fail; 3812 } 3813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3814 return MCDisassembler::Fail; 3815 Inst.addOperand(MCOperand::CreateImm(align)); 3816 if (Rm != 0xF) { 3817 if (Rm != 0xD) { 3818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3819 return MCDisassembler::Fail; 3820 } else 3821 Inst.addOperand(MCOperand::CreateReg(0)); 3822 } 3823 3824 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3825 return MCDisassembler::Fail; 3826 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 3827 return MCDisassembler::Fail; 3828 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 3829 return MCDisassembler::Fail; 3830 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 3831 return MCDisassembler::Fail; 3832 Inst.addOperand(MCOperand::CreateImm(index)); 3833 3834 return S; 3835 } 3836 3837 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, 3838 uint64_t Address, const void *Decoder) { 3839 DecodeStatus S = MCDisassembler::Success; 3840 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3841 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3842 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3843 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3844 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3845 3846 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3847 S = MCDisassembler::SoftFail; 3848 3849 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3850 return MCDisassembler::Fail; 3851 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3852 return MCDisassembler::Fail; 3853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3854 return MCDisassembler::Fail; 3855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3856 return MCDisassembler::Fail; 3857 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3858 return MCDisassembler::Fail; 3859 3860 return S; 3861 } 3862 3863 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, 3864 uint64_t Address, const void *Decoder) { 3865 DecodeStatus S = MCDisassembler::Success; 3866 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3867 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); 3868 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3869 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 3870 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 3871 3872 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 3873 S = MCDisassembler::SoftFail; 3874 3875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 3876 return MCDisassembler::Fail; 3877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 3878 return MCDisassembler::Fail; 3879 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 3880 return MCDisassembler::Fail; 3881 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 3882 return MCDisassembler::Fail; 3883 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3884 return MCDisassembler::Fail; 3885 3886 return S; 3887 } 3888 3889 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn, 3890 uint64_t Address, const void *Decoder) { 3891 DecodeStatus S = MCDisassembler::Success; 3892 unsigned pred = fieldFromInstruction16(Insn, 4, 4); 3893 // The InstPrinter needs to have the low bit of the predicate in 3894 // the mask operand to be able to print it properly. 3895 unsigned mask = fieldFromInstruction16(Insn, 0, 5); 3896 3897 if (pred == 0xF) { 3898 pred = 0xE; 3899 S = MCDisassembler::SoftFail; 3900 } 3901 3902 if ((mask & 0xF) == 0) { 3903 // Preserve the high bit of the mask, which is the low bit of 3904 // the predicate. 3905 mask &= 0x10; 3906 mask |= 0x8; 3907 S = MCDisassembler::SoftFail; 3908 } 3909 3910 Inst.addOperand(MCOperand::CreateImm(pred)); 3911 Inst.addOperand(MCOperand::CreateImm(mask)); 3912 return S; 3913 } 3914 3915 static DecodeStatus 3916 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3917 uint64_t Address, const void *Decoder) { 3918 DecodeStatus S = MCDisassembler::Success; 3919 3920 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3921 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3922 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3923 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3924 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3925 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3926 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3927 bool writeback = (W == 1) | (P == 0); 3928 3929 addr |= (U << 8) | (Rn << 9); 3930 3931 if (writeback && (Rn == Rt || Rn == Rt2)) 3932 Check(S, MCDisassembler::SoftFail); 3933 if (Rt == Rt2) 3934 Check(S, MCDisassembler::SoftFail); 3935 3936 // Rt 3937 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3938 return MCDisassembler::Fail; 3939 // Rt2 3940 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3941 return MCDisassembler::Fail; 3942 // Writeback operand 3943 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3944 return MCDisassembler::Fail; 3945 // addr 3946 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3947 return MCDisassembler::Fail; 3948 3949 return S; 3950 } 3951 3952 static DecodeStatus 3953 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, 3954 uint64_t Address, const void *Decoder) { 3955 DecodeStatus S = MCDisassembler::Success; 3956 3957 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 3958 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4); 3959 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3960 unsigned addr = fieldFromInstruction32(Insn, 0, 8); 3961 unsigned W = fieldFromInstruction32(Insn, 21, 1); 3962 unsigned U = fieldFromInstruction32(Insn, 23, 1); 3963 unsigned P = fieldFromInstruction32(Insn, 24, 1); 3964 bool writeback = (W == 1) | (P == 0); 3965 3966 addr |= (U << 8) | (Rn << 9); 3967 3968 if (writeback && (Rn == Rt || Rn == Rt2)) 3969 Check(S, MCDisassembler::SoftFail); 3970 3971 // Writeback operand 3972 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 3973 return MCDisassembler::Fail; 3974 // Rt 3975 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3976 return MCDisassembler::Fail; 3977 // Rt2 3978 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 3979 return MCDisassembler::Fail; 3980 // addr 3981 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 3982 return MCDisassembler::Fail; 3983 3984 return S; 3985 } 3986 3987 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, 3988 uint64_t Address, const void *Decoder) { 3989 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1); 3990 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1); 3991 if (sign1 != sign2) return MCDisassembler::Fail; 3992 3993 unsigned Val = fieldFromInstruction32(Insn, 0, 8); 3994 Val |= fieldFromInstruction32(Insn, 12, 3) << 8; 3995 Val |= fieldFromInstruction32(Insn, 26, 1) << 11; 3996 Val |= sign1 << 12; 3997 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 3998 3999 return MCDisassembler::Success; 4000 } 4001 4002 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val, 4003 uint64_t Address, 4004 const void *Decoder) { 4005 DecodeStatus S = MCDisassembler::Success; 4006 4007 // Shift of "asr #32" is not allowed in Thumb2 mode. 4008 if (Val == 0x20) S = MCDisassembler::SoftFail; 4009 Inst.addOperand(MCOperand::CreateImm(Val)); 4010 return S; 4011 } 4012 4013 static DecodeStatus DecodeSwap(llvm::MCInst &Inst, unsigned Insn, 4014 uint64_t Address, const void *Decoder) { 4015 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 4016 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4); 4017 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 4018 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 4019 4020 if (pred == 0xF) 4021 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4022 4023 DecodeStatus S = MCDisassembler::Success; 4024 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4025 return MCDisassembler::Fail; 4026 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4031 return MCDisassembler::Fail; 4032 4033 return S; 4034 } 4035 4036 static DecodeStatus DecodeVCVTD(llvm::MCInst &Inst, unsigned Insn, 4037 uint64_t Address, const void *Decoder) { 4038 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4039 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4040 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4041 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4042 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4043 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4044 4045 DecodeStatus S = MCDisassembler::Success; 4046 4047 // VMOVv2f32 is ambiguous with these decodings. 4048 if (!(imm & 0x38) && cmode == 0xF) { 4049 Inst.setOpcode(ARM::VMOVv2f32); 4050 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4051 } 4052 4053 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4054 4055 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 4056 return MCDisassembler::Fail; 4057 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 4058 return MCDisassembler::Fail; 4059 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4060 4061 return S; 4062 } 4063 4064 static DecodeStatus DecodeVCVTQ(llvm::MCInst &Inst, unsigned Insn, 4065 uint64_t Address, const void *Decoder) { 4066 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0); 4067 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4); 4068 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0); 4069 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4); 4070 unsigned imm = fieldFromInstruction32(Insn, 16, 6); 4071 unsigned cmode = fieldFromInstruction32(Insn, 8, 4); 4072 4073 DecodeStatus S = MCDisassembler::Success; 4074 4075 // VMOVv4f32 is ambiguous with these decodings. 4076 if (!(imm & 0x38) && cmode == 0xF) { 4077 Inst.setOpcode(ARM::VMOVv4f32); 4078 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 4079 } 4080 4081 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail); 4082 4083 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 4084 return MCDisassembler::Fail; 4085 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 4086 return MCDisassembler::Fail; 4087 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 4088 4089 return S; 4090 } 4091