1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/MC/TargetRegistry.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142 private: 143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 144 ArrayRef<uint8_t> Bytes, uint64_t Address, 145 raw_ostream &CStream) const; 146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 148 ArrayRef<uint8_t> Bytes, uint64_t Address, 149 raw_ostream &CStream) const; 150 151 mutable ITStatus ITBlock; 152 mutable VPTStatus VPTBlock; 153 154 DecodeStatus AddThumbPredicate(MCInst&) const; 155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 156 }; 157 158 } // end anonymous namespace 159 160 static bool Check(DecodeStatus &Out, DecodeStatus In) { 161 switch (In) { 162 case MCDisassembler::Success: 163 // Out stays the same. 164 return true; 165 case MCDisassembler::SoftFail: 166 Out = In; 167 return true; 168 case MCDisassembler::Fail: 169 Out = In; 170 return false; 171 } 172 llvm_unreachable("Invalid DecodeStatus!"); 173 } 174 175 // Forward declare these because the autogenerated code will reference them. 176 // Definitions are further down. 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, 179 const MCDisassembler *Decoder); 180 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, 182 const MCDisassembler *Decoder); 183 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, 185 const MCDisassembler *Decoder); 186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, 188 const MCDisassembler *Decoder); 189 static DecodeStatus 190 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 191 uint64_t Address, 192 const MCDisassembler *Decoder); 193 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 194 uint64_t Address, 195 const MCDisassembler *Decoder); 196 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 197 uint64_t Address, 198 const MCDisassembler *Decoder); 199 static DecodeStatus 200 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 201 const MCDisassembler *Decoder); 202 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 203 uint64_t Address, 204 const MCDisassembler *Decoder); 205 static DecodeStatus 206 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 207 const MCDisassembler *Decoder); 208 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 209 uint64_t Address, 210 const MCDisassembler *Decoder); 211 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, 213 const MCDisassembler *Decoder); 214 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 215 uint64_t Address, 216 const MCDisassembler *Decoder); 217 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 218 uint64_t Address, 219 const MCDisassembler *Decoder); 220 static DecodeStatus 221 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 222 const MCDisassembler *Decoder); 223 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, 225 const MCDisassembler *Decoder); 226 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, 228 const MCDisassembler *Decoder); 229 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 230 uint64_t Address, 231 const MCDisassembler *Decoder); 232 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 233 uint64_t Address, 234 const MCDisassembler *Decoder); 235 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 236 uint64_t Address, 237 const MCDisassembler *Decoder); 238 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 239 uint64_t Address, 240 const MCDisassembler *Decoder); 241 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 242 uint64_t Address, 243 const MCDisassembler *Decoder); 244 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 245 uint64_t Address, 246 const MCDisassembler *Decoder); 247 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 248 uint64_t Address, 249 const MCDisassembler *Decoder); 250 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 251 uint64_t Address, 252 const MCDisassembler *Decoder); 253 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 254 uint64_t Address, 255 const MCDisassembler *Decoder); 256 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 257 uint64_t Address, 258 const MCDisassembler *Decoder); 259 static DecodeStatus 260 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 261 const MCDisassembler *Decoder); 262 263 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 264 uint64_t Address, 265 const MCDisassembler *Decoder); 266 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 267 uint64_t Address, 268 const MCDisassembler *Decoder); 269 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 270 uint64_t Address, 271 const MCDisassembler *Decoder); 272 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 273 uint64_t Address, 274 const MCDisassembler *Decoder); 275 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 276 uint64_t Address, 277 const MCDisassembler *Decoder); 278 279 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 280 uint64_t Address, 281 const MCDisassembler *Decoder); 282 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 283 uint64_t Address, 284 const MCDisassembler *Decoder); 285 static DecodeStatus 286 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 287 const MCDisassembler *Decoder); 288 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 289 uint64_t Address, 290 const MCDisassembler *Decoder); 291 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 292 uint64_t Address, 293 const MCDisassembler *Decoder); 294 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 295 uint64_t Address, 296 const MCDisassembler *Decoder); 297 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 298 uint64_t Address, 299 const MCDisassembler *Decoder); 300 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 301 uint64_t Address, 302 const MCDisassembler *Decoder); 303 304 static DecodeStatus 305 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 306 uint64_t Adddress, 307 const MCDisassembler *Decoder); 308 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 309 uint64_t Address, 310 const MCDisassembler *Decoder); 311 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 312 uint64_t Address, 313 const MCDisassembler *Decoder); 314 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 315 uint64_t Address, 316 const MCDisassembler *Decoder); 317 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 318 uint64_t Address, 319 const MCDisassembler *Decoder); 320 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 321 uint64_t Address, 322 const MCDisassembler *Decoder); 323 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 324 uint64_t Address, 325 const MCDisassembler *Decoder); 326 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 327 uint64_t Address, 328 const MCDisassembler *Decoder); 329 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 330 uint64_t Address, 331 const MCDisassembler *Decoder); 332 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, 333 uint64_t Address, 334 const MCDisassembler *Decoder); 335 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 336 uint64_t Address, 337 const MCDisassembler *Decoder); 338 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 339 uint64_t Address, 340 const MCDisassembler *Decoder); 341 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 342 uint64_t Address, 343 const MCDisassembler *Decoder); 344 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 345 uint64_t Address, 346 const MCDisassembler *Decoder); 347 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 348 uint64_t Address, 349 const MCDisassembler *Decoder); 350 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 351 uint64_t Address, 352 const MCDisassembler *Decoder); 353 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 354 uint64_t Address, 355 const MCDisassembler *Decoder); 356 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 357 uint64_t Address, 358 const MCDisassembler *Decoder); 359 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 360 uint64_t Address, 361 const MCDisassembler *Decoder); 362 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 363 uint64_t Address, 364 const MCDisassembler *Decoder); 365 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 366 uint64_t Address, 367 const MCDisassembler *Decoder); 368 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 369 uint64_t Address, 370 const MCDisassembler *Decoder); 371 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 372 uint64_t Address, 373 const MCDisassembler *Decoder); 374 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 375 uint64_t Address, 376 const MCDisassembler *Decoder); 377 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 378 uint64_t Address, 379 const MCDisassembler *Decoder); 380 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 381 uint64_t Address, 382 const MCDisassembler *Decoder); 383 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 384 uint64_t Address, 385 const MCDisassembler *Decoder); 386 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val, 387 uint64_t Address, 388 const MCDisassembler *Decoder); 389 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val, 390 uint64_t Address, 391 const MCDisassembler *Decoder); 392 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 393 uint64_t Address, 394 const MCDisassembler *Decoder); 395 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 396 uint64_t Address, 397 const MCDisassembler *Decoder); 398 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 399 uint64_t Address, 400 const MCDisassembler *Decoder); 401 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 402 uint64_t Address, 403 const MCDisassembler *Decoder); 404 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 405 uint64_t Address, 406 const MCDisassembler *Decoder); 407 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 408 uint64_t Address, 409 const MCDisassembler *Decoder); 410 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 411 uint64_t Address, 412 const MCDisassembler *Decoder); 413 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 414 uint64_t Address, 415 const MCDisassembler *Decoder); 416 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 417 uint64_t Address, 418 const MCDisassembler *Decoder); 419 template <int shift> 420 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 421 uint64_t Address, 422 const MCDisassembler *Decoder); 423 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 424 uint64_t Address, 425 const MCDisassembler *Decoder); 426 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 427 uint64_t Address, 428 const MCDisassembler *Decoder); 429 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 430 uint64_t Address, 431 const MCDisassembler *Decoder); 432 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, 433 const MCDisassembler *Decoder); 434 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 435 uint64_t Address, 436 const MCDisassembler *Decoder); 437 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 438 uint64_t Address, 439 const MCDisassembler *Decoder); 440 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 441 uint64_t Address, 442 const MCDisassembler *Decoder); 443 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 444 uint64_t Address, 445 const MCDisassembler *Decoder); 446 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 447 uint64_t Address, 448 const MCDisassembler *Decoder); 449 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 450 uint64_t Address, 451 const MCDisassembler *Decoder); 452 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 453 uint64_t Address, 454 const MCDisassembler *Decoder); 455 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 456 const MCDisassembler *Decoder); 457 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 458 const MCDisassembler *Decoder); 459 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 460 const MCDisassembler *Decoder); 461 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 462 const MCDisassembler *Decoder); 463 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 464 const MCDisassembler *Decoder); 465 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 466 const MCDisassembler *Decoder); 467 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 468 const MCDisassembler *Decoder); 469 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 470 const MCDisassembler *Decoder); 471 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 472 const MCDisassembler *Decoder); 473 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 474 const MCDisassembler *Decoder); 475 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 476 const MCDisassembler *Decoder); 477 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 478 const MCDisassembler *Decoder); 479 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 480 const MCDisassembler *Decoder); 481 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 482 uint64_t Address, 483 const MCDisassembler *Decoder); 484 static DecodeStatus 485 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, 486 const MCDisassembler *Decoder); 487 488 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 489 uint64_t Address, 490 const MCDisassembler *Decoder); 491 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 492 uint64_t Address, 493 const MCDisassembler *Decoder); 494 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 495 uint64_t Address, 496 const MCDisassembler *Decoder); 497 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 498 uint64_t Address, 499 const MCDisassembler *Decoder); 500 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 501 uint64_t Address, 502 const MCDisassembler *Decoder); 503 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 504 uint64_t Address, 505 const MCDisassembler *Decoder); 506 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 507 uint64_t Address, 508 const MCDisassembler *Decoder); 509 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 510 uint64_t Address, 511 const MCDisassembler *Decoder); 512 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 513 uint64_t Address, 514 const MCDisassembler *Decoder); 515 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 516 uint64_t Address, 517 const MCDisassembler *Decoder); 518 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 519 uint64_t Address, 520 const MCDisassembler *Decoder); 521 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 522 uint64_t Address, 523 const MCDisassembler *Decoder); 524 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 525 const MCDisassembler *Decoder); 526 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 527 uint64_t Address, 528 const MCDisassembler *Decoder); 529 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 530 const MCDisassembler *Decoder); 531 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 532 const MCDisassembler *Decoder); 533 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 534 uint64_t Address, 535 const MCDisassembler *Decoder); 536 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 537 uint64_t Address, 538 const MCDisassembler *Decoder); 539 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 540 uint64_t Address, 541 const MCDisassembler *Decoder); 542 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 543 const MCDisassembler *Decoder); 544 template <int shift> 545 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 546 const MCDisassembler *Decoder); 547 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 548 uint64_t Address, 549 const MCDisassembler *Decoder); 550 template <int shift> 551 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 552 uint64_t Address, 553 const MCDisassembler *Decoder); 554 template <int shift, int WriteBack> 555 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 556 uint64_t Address, 557 const MCDisassembler *Decoder); 558 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 559 uint64_t Address, 560 const MCDisassembler *Decoder); 561 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 562 uint64_t Address, 563 const MCDisassembler *Decoder); 564 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 565 uint64_t Address, 566 const MCDisassembler *Decoder); 567 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 568 uint64_t Address, 569 const MCDisassembler *Decoder); 570 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 571 uint64_t Address, 572 const MCDisassembler *Decoder); 573 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 574 uint64_t Address, 575 const MCDisassembler *Decoder); 576 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 577 uint64_t Address, 578 const MCDisassembler *Decoder); 579 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 580 uint64_t Address, 581 const MCDisassembler *Decoder); 582 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 583 const MCDisassembler *Decoder); 584 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 585 uint64_t Address, 586 const MCDisassembler *Decoder); 587 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 588 uint64_t Address, 589 const MCDisassembler *Decoder); 590 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, 591 const MCDisassembler *Decoder); 592 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 593 uint64_t Address, 594 const MCDisassembler *Decoder); 595 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 596 uint64_t Address, 597 const MCDisassembler *Decoder); 598 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, 599 const MCDisassembler *Decoder); 600 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 601 uint64_t Address, 602 const MCDisassembler *Decoder); 603 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 604 uint64_t Address, 605 const MCDisassembler *Decoder); 606 607 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 608 const MCDisassembler *Decoder); 609 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 610 uint64_t Address, 611 const MCDisassembler *Decoder); 612 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 613 uint64_t Address, 614 const MCDisassembler *Decoder); 615 616 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 617 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 618 uint64_t Address, 619 const MCDisassembler *Decoder); 620 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 621 uint64_t Address, 622 const MCDisassembler *Decoder); 623 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 624 uint64_t Address, 625 const MCDisassembler *Decoder); 626 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 627 const MCDisassembler *Decoder); 628 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 629 uint64_t Address, 630 const MCDisassembler *Decoder); 631 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 632 const MCDisassembler *Decoder); 633 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 634 uint64_t Address, 635 const MCDisassembler *Decoder); 636 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 637 uint64_t Address, 638 const MCDisassembler *Decoder); 639 static DecodeStatus 640 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 641 const MCDisassembler *Decoder); 642 static DecodeStatus 643 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 644 const MCDisassembler *Decoder); 645 static DecodeStatus 646 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 647 const MCDisassembler *Decoder); 648 static DecodeStatus 649 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 650 const MCDisassembler *Decoder); 651 template <bool Writeback> 652 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 653 uint64_t Address, 654 const MCDisassembler *Decoder); 655 template <int shift> 656 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 657 uint64_t Address, 658 const MCDisassembler *Decoder); 659 template <int shift> 660 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 661 uint64_t Address, 662 const MCDisassembler *Decoder); 663 template <int shift> 664 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 665 uint64_t Address, 666 const MCDisassembler *Decoder); 667 template <unsigned MinLog, unsigned MaxLog> 668 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 669 uint64_t Address, 670 const MCDisassembler *Decoder); 671 template <unsigned start> 672 static DecodeStatus 673 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 674 const MCDisassembler *Decoder); 675 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 676 uint64_t Address, 677 const MCDisassembler *Decoder); 678 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 679 uint64_t Address, 680 const MCDisassembler *Decoder); 681 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 682 uint64_t Address, 683 const MCDisassembler *Decoder); 684 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 685 uint64_t Address, 686 const MCDisassembler *Decoder); 687 template <bool scalar, OperandDecoder predicate_decoder> 688 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 689 const MCDisassembler *Decoder); 690 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 691 const MCDisassembler *Decoder); 692 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 693 uint64_t Address, 694 const MCDisassembler *Decoder); 695 static DecodeStatus 696 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 697 const MCDisassembler *Decoder); 698 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 699 uint64_t Address, 700 const MCDisassembler *Decoder); 701 702 #include "ARMGenDisassemblerTables.inc" 703 704 static MCDisassembler *createARMDisassembler(const Target &T, 705 const MCSubtargetInfo &STI, 706 MCContext &Ctx) { 707 return new ARMDisassembler(STI, Ctx); 708 } 709 710 // Post-decoding checks 711 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 712 uint64_t Address, raw_ostream &CS, 713 uint32_t Insn, 714 DecodeStatus Result) { 715 switch (MI.getOpcode()) { 716 case ARM::HVC: { 717 // HVC is undefined if condition = 0xf otherwise upredictable 718 // if condition != 0xe 719 uint32_t Cond = (Insn >> 28) & 0xF; 720 if (Cond == 0xF) 721 return MCDisassembler::Fail; 722 if (Cond != 0xE) 723 return MCDisassembler::SoftFail; 724 return Result; 725 } 726 case ARM::t2ADDri: 727 case ARM::t2ADDri12: 728 case ARM::t2ADDrr: 729 case ARM::t2ADDrs: 730 case ARM::t2SUBri: 731 case ARM::t2SUBri12: 732 case ARM::t2SUBrr: 733 case ARM::t2SUBrs: 734 if (MI.getOperand(0).getReg() == ARM::SP && 735 MI.getOperand(1).getReg() != ARM::SP) 736 return MCDisassembler::SoftFail; 737 return Result; 738 default: return Result; 739 } 740 } 741 742 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 743 ArrayRef<uint8_t> Bytes, 744 uint64_t Address, 745 raw_ostream &CS) const { 746 if (STI.getFeatureBits()[ARM::ModeThumb]) 747 return getThumbInstruction(MI, Size, Bytes, Address, CS); 748 return getARMInstruction(MI, Size, Bytes, Address, CS); 749 } 750 751 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 752 ArrayRef<uint8_t> Bytes, 753 uint64_t Address, 754 raw_ostream &CS) const { 755 CommentStream = &CS; 756 757 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 758 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 759 "mode!"); 760 761 // We want to read exactly 4 bytes of data. 762 if (Bytes.size() < 4) { 763 Size = 0; 764 return MCDisassembler::Fail; 765 } 766 767 // Encoded as a small-endian 32-bit word in the stream. 768 uint32_t Insn = 769 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 770 771 // Calling the auto-generated decoder function. 772 DecodeStatus Result = 773 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 774 if (Result != MCDisassembler::Fail) { 775 Size = 4; 776 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 777 } 778 779 struct DecodeTable { 780 const uint8_t *P; 781 bool DecodePred; 782 }; 783 784 const DecodeTable Tables[] = { 785 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 786 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 787 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 788 {DecoderTablev8Crypto32, false}, 789 }; 790 791 for (auto Table : Tables) { 792 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 793 if (Result != MCDisassembler::Fail) { 794 Size = 4; 795 // Add a fake predicate operand, because we share these instruction 796 // definitions with Thumb2 where these instructions are predicable. 797 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 798 return MCDisassembler::Fail; 799 return Result; 800 } 801 } 802 803 Result = 804 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 805 if (Result != MCDisassembler::Fail) { 806 Size = 4; 807 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 808 } 809 810 Size = 4; 811 return MCDisassembler::Fail; 812 } 813 814 namespace llvm { 815 816 extern const MCInstrDesc ARMInsts[]; 817 818 } // end namespace llvm 819 820 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 821 /// immediate Value in the MCInst. The immediate Value has had any PC 822 /// adjustment made by the caller. If the instruction is a branch instruction 823 /// then isBranch is true, else false. If the getOpInfo() function was set as 824 /// part of the setupForSymbolicDisassembly() call then that function is called 825 /// to get any symbolic information at the Address for this instruction. If 826 /// that returns non-zero then the symbolic information it returns is used to 827 /// create an MCExpr and that is added as an operand to the MCInst. If 828 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 829 /// Value is done and if a symbol is found an MCExpr is created with that, else 830 /// an MCExpr with Value is created. This function returns true if it adds an 831 /// operand to the MCInst and false otherwise. 832 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 833 bool isBranch, uint64_t InstSize, 834 MCInst &MI, 835 const MCDisassembler *Decoder) { 836 // FIXME: Does it make sense for value to be negative? 837 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, 838 isBranch, /* Offset */ 0, InstSize); 839 } 840 841 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 842 /// referenced by a load instruction with the base register that is the Pc. 843 /// These can often be values in a literal pool near the Address of the 844 /// instruction. The Address of the instruction and its immediate Value are 845 /// used as a possible literal pool entry. The SymbolLookUp call back will 846 /// return the name of a symbol referenced by the literal pool's entry if 847 /// the referenced address is that of a symbol. Or it will return a pointer to 848 /// a literal 'C' string if the referenced address of the literal pool's entry 849 /// is an address into a section with 'C' string literals. 850 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 851 const MCDisassembler *Decoder) { 852 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 853 Dis->tryAddingPcLoadReferenceComment(Value, Address); 854 } 855 856 // Thumb1 instructions don't have explicit S bits. Rather, they 857 // implicitly set CPSR. Since it's not represented in the encoding, the 858 // auto-generated decoder won't inject the CPSR operand. We need to fix 859 // that as a post-pass. 860 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 861 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 862 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 863 MCInst::iterator I = MI.begin(); 864 for (unsigned i = 0; i < NumOps; ++i, ++I) { 865 if (I == MI.end()) break; 866 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 867 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 868 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 869 return; 870 } 871 } 872 873 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 874 } 875 876 static bool isVectorPredicable(unsigned Opcode) { 877 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 878 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 879 for (unsigned i = 0; i < NumOps; ++i) { 880 if (ARM::isVpred(OpInfo[i].OperandType)) 881 return true; 882 } 883 return false; 884 } 885 886 // Most Thumb instructions don't have explicit predicates in the 887 // encoding, but rather get their predicates from IT context. We need 888 // to fix up the predicate operands using this context information as a 889 // post-pass. 890 MCDisassembler::DecodeStatus 891 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 892 MCDisassembler::DecodeStatus S = Success; 893 894 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 895 896 // A few instructions actually have predicates encoded in them. Don't 897 // try to overwrite it if we're seeing one of those. 898 switch (MI.getOpcode()) { 899 case ARM::tBcc: 900 case ARM::t2Bcc: 901 case ARM::tCBZ: 902 case ARM::tCBNZ: 903 case ARM::tCPS: 904 case ARM::t2CPS3p: 905 case ARM::t2CPS2p: 906 case ARM::t2CPS1p: 907 case ARM::t2CSEL: 908 case ARM::t2CSINC: 909 case ARM::t2CSINV: 910 case ARM::t2CSNEG: 911 case ARM::tMOVSr: 912 case ARM::tSETEND: 913 // Some instructions (mostly conditional branches) are not 914 // allowed in IT blocks. 915 if (ITBlock.instrInITBlock()) 916 S = SoftFail; 917 else 918 return Success; 919 break; 920 case ARM::t2HINT: 921 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 922 S = SoftFail; 923 break; 924 case ARM::tB: 925 case ARM::t2B: 926 case ARM::t2TBB: 927 case ARM::t2TBH: 928 // Some instructions (mostly unconditional branches) can 929 // only appears at the end of, or outside of, an IT. 930 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 931 S = SoftFail; 932 break; 933 default: 934 break; 935 } 936 937 // Warn on non-VPT predicable instruction in a VPT block and a VPT 938 // predicable instruction in an IT block 939 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 940 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 941 S = SoftFail; 942 943 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 944 // assume a predicate of AL. 945 unsigned CC = ARMCC::AL; 946 unsigned VCC = ARMVCC::None; 947 if (ITBlock.instrInITBlock()) { 948 CC = ITBlock.getITCC(); 949 ITBlock.advanceITState(); 950 } else if (VPTBlock.instrInVPTBlock()) { 951 VCC = VPTBlock.getVPTPred(); 952 VPTBlock.advanceVPTState(); 953 } 954 955 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 956 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 957 958 MCInst::iterator CCI = MI.begin(); 959 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 960 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 961 } 962 963 if (ARMInsts[MI.getOpcode()].isPredicable()) { 964 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 965 ++CCI; 966 if (CC == ARMCC::AL) 967 MI.insert(CCI, MCOperand::createReg(0)); 968 else 969 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 970 } else if (CC != ARMCC::AL) { 971 Check(S, SoftFail); 972 } 973 974 MCInst::iterator VCCI = MI.begin(); 975 unsigned VCCPos; 976 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 977 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 978 } 979 980 if (isVectorPredicable(MI.getOpcode())) { 981 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 982 ++VCCI; 983 if (VCC == ARMVCC::None) 984 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 985 else 986 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 987 ++VCCI; 988 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 989 ++VCCI; 990 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 991 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 992 VCCPos + 3, MCOI::TIED_TO); 993 assert(TiedOp >= 0 && 994 "Inactive register in vpred_r is not tied to an output!"); 995 // Copy the operand to ensure it's not invalidated when MI grows. 996 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 997 } 998 } else if (VCC != ARMVCC::None) { 999 Check(S, SoftFail); 1000 } 1001 1002 return S; 1003 } 1004 1005 // Thumb VFP instructions are a special case. Because we share their 1006 // encodings between ARM and Thumb modes, and they are predicable in ARM 1007 // mode, the auto-generated decoder will give them an (incorrect) 1008 // predicate operand. We need to rewrite these operands based on the IT 1009 // context as a post-pass. 1010 void ARMDisassembler::UpdateThumbVFPPredicate( 1011 DecodeStatus &S, MCInst &MI) const { 1012 unsigned CC; 1013 CC = ITBlock.getITCC(); 1014 if (CC == 0xF) 1015 CC = ARMCC::AL; 1016 if (ITBlock.instrInITBlock()) 1017 ITBlock.advanceITState(); 1018 else if (VPTBlock.instrInVPTBlock()) { 1019 CC = VPTBlock.getVPTPred(); 1020 VPTBlock.advanceVPTState(); 1021 } 1022 1023 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 1024 MCInst::iterator I = MI.begin(); 1025 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 1026 for (unsigned i = 0; i < NumOps; ++i, ++I) { 1027 if (OpInfo[i].isPredicate() ) { 1028 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 1029 Check(S, SoftFail); 1030 I->setImm(CC); 1031 ++I; 1032 if (CC == ARMCC::AL) 1033 I->setReg(0); 1034 else 1035 I->setReg(ARM::CPSR); 1036 return; 1037 } 1038 } 1039 } 1040 1041 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 1042 ArrayRef<uint8_t> Bytes, 1043 uint64_t Address, 1044 raw_ostream &CS) const { 1045 CommentStream = &CS; 1046 1047 assert(STI.getFeatureBits()[ARM::ModeThumb] && 1048 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 1049 1050 // We want to read exactly 2 bytes of data. 1051 if (Bytes.size() < 2) { 1052 Size = 0; 1053 return MCDisassembler::Fail; 1054 } 1055 1056 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 1057 DecodeStatus Result = 1058 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 1059 if (Result != MCDisassembler::Fail) { 1060 Size = 2; 1061 Check(Result, AddThumbPredicate(MI)); 1062 return Result; 1063 } 1064 1065 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 1066 STI); 1067 if (Result) { 1068 Size = 2; 1069 bool InITBlock = ITBlock.instrInITBlock(); 1070 Check(Result, AddThumbPredicate(MI)); 1071 AddThumb1SBit(MI, InITBlock); 1072 return Result; 1073 } 1074 1075 Result = 1076 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 1077 if (Result != MCDisassembler::Fail) { 1078 Size = 2; 1079 1080 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 1081 // the Thumb predicate. 1082 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 1083 Result = MCDisassembler::SoftFail; 1084 1085 Check(Result, AddThumbPredicate(MI)); 1086 1087 // If we find an IT instruction, we need to parse its condition 1088 // code and mask operands so that we can apply them correctly 1089 // to the subsequent instructions. 1090 if (MI.getOpcode() == ARM::t2IT) { 1091 unsigned Firstcond = MI.getOperand(0).getImm(); 1092 unsigned Mask = MI.getOperand(1).getImm(); 1093 ITBlock.setITState(Firstcond, Mask); 1094 1095 // An IT instruction that would give a 'NV' predicate is unpredictable. 1096 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 1097 CS << "unpredictable IT predicate sequence"; 1098 } 1099 1100 return Result; 1101 } 1102 1103 // We want to read exactly 4 bytes of data. 1104 if (Bytes.size() < 4) { 1105 Size = 0; 1106 return MCDisassembler::Fail; 1107 } 1108 1109 uint32_t Insn32 = 1110 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 1111 1112 Result = 1113 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 1114 if (Result != MCDisassembler::Fail) { 1115 Size = 4; 1116 1117 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 1118 // the VPT predicate. 1119 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 1120 Result = MCDisassembler::SoftFail; 1121 1122 Check(Result, AddThumbPredicate(MI)); 1123 1124 if (isVPTOpcode(MI.getOpcode())) { 1125 unsigned Mask = MI.getOperand(0).getImm(); 1126 VPTBlock.setVPTState(Mask); 1127 } 1128 1129 return Result; 1130 } 1131 1132 Result = 1133 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1134 if (Result != MCDisassembler::Fail) { 1135 Size = 4; 1136 bool InITBlock = ITBlock.instrInITBlock(); 1137 Check(Result, AddThumbPredicate(MI)); 1138 AddThumb1SBit(MI, InITBlock); 1139 return Result; 1140 } 1141 1142 Result = 1143 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1144 if (Result != MCDisassembler::Fail) { 1145 Size = 4; 1146 Check(Result, AddThumbPredicate(MI)); 1147 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1148 } 1149 1150 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1151 Result = 1152 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1153 if (Result != MCDisassembler::Fail) { 1154 Size = 4; 1155 UpdateThumbVFPPredicate(Result, MI); 1156 return Result; 1157 } 1158 } 1159 1160 Result = 1161 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1162 if (Result != MCDisassembler::Fail) { 1163 Size = 4; 1164 return Result; 1165 } 1166 1167 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1168 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1169 STI); 1170 if (Result != MCDisassembler::Fail) { 1171 Size = 4; 1172 Check(Result, AddThumbPredicate(MI)); 1173 return Result; 1174 } 1175 } 1176 1177 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1178 uint32_t NEONLdStInsn = Insn32; 1179 NEONLdStInsn &= 0xF0FFFFFF; 1180 NEONLdStInsn |= 0x04000000; 1181 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1182 Address, this, STI); 1183 if (Result != MCDisassembler::Fail) { 1184 Size = 4; 1185 Check(Result, AddThumbPredicate(MI)); 1186 return Result; 1187 } 1188 } 1189 1190 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1191 uint32_t NEONDataInsn = Insn32; 1192 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1193 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1194 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1195 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1196 Address, this, STI); 1197 if (Result != MCDisassembler::Fail) { 1198 Size = 4; 1199 Check(Result, AddThumbPredicate(MI)); 1200 return Result; 1201 } 1202 1203 uint32_t NEONCryptoInsn = Insn32; 1204 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1205 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1206 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1207 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1208 Address, this, STI); 1209 if (Result != MCDisassembler::Fail) { 1210 Size = 4; 1211 return Result; 1212 } 1213 1214 uint32_t NEONv8Insn = Insn32; 1215 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1216 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1217 this, STI); 1218 if (Result != MCDisassembler::Fail) { 1219 Size = 4; 1220 return Result; 1221 } 1222 } 1223 1224 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1225 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1226 ? DecoderTableThumb2CDE32 1227 : DecoderTableThumb2CoProc32; 1228 Result = 1229 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1230 if (Result != MCDisassembler::Fail) { 1231 Size = 4; 1232 Check(Result, AddThumbPredicate(MI)); 1233 return Result; 1234 } 1235 1236 Size = 0; 1237 return MCDisassembler::Fail; 1238 } 1239 1240 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1241 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1242 createARMDisassembler); 1243 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1244 createARMDisassembler); 1245 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1246 createARMDisassembler); 1247 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1248 createARMDisassembler); 1249 } 1250 1251 static const uint16_t GPRDecoderTable[] = { 1252 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1253 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1254 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1255 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1256 }; 1257 1258 static const uint16_t CLRMGPRDecoderTable[] = { 1259 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1260 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1261 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1262 ARM::R12, 0, ARM::LR, ARM::APSR 1263 }; 1264 1265 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1266 uint64_t Address, 1267 const MCDisassembler *Decoder) { 1268 if (RegNo > 15) 1269 return MCDisassembler::Fail; 1270 1271 unsigned Register = GPRDecoderTable[RegNo]; 1272 Inst.addOperand(MCOperand::createReg(Register)); 1273 return MCDisassembler::Success; 1274 } 1275 1276 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1277 uint64_t Address, 1278 const MCDisassembler *Decoder) { 1279 if (RegNo > 15) 1280 return MCDisassembler::Fail; 1281 1282 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1283 if (Register == 0) 1284 return MCDisassembler::Fail; 1285 1286 Inst.addOperand(MCOperand::createReg(Register)); 1287 return MCDisassembler::Success; 1288 } 1289 1290 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1291 uint64_t Address, 1292 const MCDisassembler *Decoder) { 1293 DecodeStatus S = MCDisassembler::Success; 1294 1295 if (RegNo == 15) 1296 S = MCDisassembler::SoftFail; 1297 1298 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1299 1300 return S; 1301 } 1302 1303 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1304 uint64_t Address, 1305 const MCDisassembler *Decoder) { 1306 DecodeStatus S = MCDisassembler::Success; 1307 1308 if (RegNo == 13) 1309 S = MCDisassembler::SoftFail; 1310 1311 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1312 1313 return S; 1314 } 1315 1316 static DecodeStatus 1317 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1318 const MCDisassembler *Decoder) { 1319 DecodeStatus S = MCDisassembler::Success; 1320 1321 if (RegNo == 15) 1322 { 1323 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1324 return MCDisassembler::Success; 1325 } 1326 1327 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1328 return S; 1329 } 1330 1331 static DecodeStatus 1332 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1333 const MCDisassembler *Decoder) { 1334 DecodeStatus S = MCDisassembler::Success; 1335 1336 if (RegNo == 15) 1337 { 1338 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1339 return MCDisassembler::Success; 1340 } 1341 1342 if (RegNo == 13) 1343 Check(S, MCDisassembler::SoftFail); 1344 1345 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1346 return S; 1347 } 1348 1349 static DecodeStatus 1350 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1351 const MCDisassembler *Decoder) { 1352 DecodeStatus S = MCDisassembler::Success; 1353 if (RegNo == 13) 1354 return MCDisassembler::Fail; 1355 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1356 return S; 1357 } 1358 1359 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1360 uint64_t Address, 1361 const MCDisassembler *Decoder) { 1362 if (RegNo > 7) 1363 return MCDisassembler::Fail; 1364 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1365 } 1366 1367 static const uint16_t GPRPairDecoderTable[] = { 1368 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1369 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1370 }; 1371 1372 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1373 uint64_t Address, 1374 const MCDisassembler *Decoder) { 1375 DecodeStatus S = MCDisassembler::Success; 1376 1377 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1378 // rather than SoftFail as there is no GPRPair table entry for index 7. 1379 if (RegNo > 13) 1380 return MCDisassembler::Fail; 1381 1382 if (RegNo & 1) 1383 S = MCDisassembler::SoftFail; 1384 1385 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1386 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1387 return S; 1388 } 1389 1390 static DecodeStatus 1391 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1392 const MCDisassembler *Decoder) { 1393 if (RegNo > 13) 1394 return MCDisassembler::Fail; 1395 1396 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1397 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1398 1399 if ((RegNo & 1) || RegNo > 10) 1400 return MCDisassembler::SoftFail; 1401 return MCDisassembler::Success; 1402 } 1403 1404 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1405 uint64_t Address, 1406 const MCDisassembler *Decoder) { 1407 if (RegNo != 13) 1408 return MCDisassembler::Fail; 1409 1410 unsigned Register = GPRDecoderTable[RegNo]; 1411 Inst.addOperand(MCOperand::createReg(Register)); 1412 return MCDisassembler::Success; 1413 } 1414 1415 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1416 uint64_t Address, 1417 const MCDisassembler *Decoder) { 1418 unsigned Register = 0; 1419 switch (RegNo) { 1420 case 0: 1421 Register = ARM::R0; 1422 break; 1423 case 1: 1424 Register = ARM::R1; 1425 break; 1426 case 2: 1427 Register = ARM::R2; 1428 break; 1429 case 3: 1430 Register = ARM::R3; 1431 break; 1432 case 9: 1433 Register = ARM::R9; 1434 break; 1435 case 12: 1436 Register = ARM::R12; 1437 break; 1438 default: 1439 return MCDisassembler::Fail; 1440 } 1441 1442 Inst.addOperand(MCOperand::createReg(Register)); 1443 return MCDisassembler::Success; 1444 } 1445 1446 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1447 uint64_t Address, 1448 const MCDisassembler *Decoder) { 1449 DecodeStatus S = MCDisassembler::Success; 1450 1451 const FeatureBitset &featureBits = 1452 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1453 1454 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1455 S = MCDisassembler::SoftFail; 1456 1457 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1458 return S; 1459 } 1460 1461 static const uint16_t SPRDecoderTable[] = { 1462 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1463 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1464 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1465 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1466 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1467 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1468 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1469 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1470 }; 1471 1472 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1473 uint64_t Address, 1474 const MCDisassembler *Decoder) { 1475 if (RegNo > 31) 1476 return MCDisassembler::Fail; 1477 1478 unsigned Register = SPRDecoderTable[RegNo]; 1479 Inst.addOperand(MCOperand::createReg(Register)); 1480 return MCDisassembler::Success; 1481 } 1482 1483 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1484 uint64_t Address, 1485 const MCDisassembler *Decoder) { 1486 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1487 } 1488 1489 static const uint16_t DPRDecoderTable[] = { 1490 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1491 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1492 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1493 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1494 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1495 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1496 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1497 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1498 }; 1499 1500 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1501 uint64_t Address, 1502 const MCDisassembler *Decoder) { 1503 const FeatureBitset &featureBits = 1504 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1505 1506 bool hasD32 = featureBits[ARM::FeatureD32]; 1507 1508 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1509 return MCDisassembler::Fail; 1510 1511 unsigned Register = DPRDecoderTable[RegNo]; 1512 Inst.addOperand(MCOperand::createReg(Register)); 1513 return MCDisassembler::Success; 1514 } 1515 1516 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1517 uint64_t Address, 1518 const MCDisassembler *Decoder) { 1519 if (RegNo > 7) 1520 return MCDisassembler::Fail; 1521 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1522 } 1523 1524 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1525 uint64_t Address, 1526 const MCDisassembler *Decoder) { 1527 if (RegNo > 15) 1528 return MCDisassembler::Fail; 1529 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1530 } 1531 1532 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1533 uint64_t Address, 1534 const MCDisassembler *Decoder) { 1535 if (RegNo > 15) 1536 return MCDisassembler::Fail; 1537 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1538 } 1539 1540 static const uint16_t QPRDecoderTable[] = { 1541 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1542 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1543 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1544 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1545 }; 1546 1547 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1548 uint64_t Address, 1549 const MCDisassembler *Decoder) { 1550 if (RegNo > 31 || (RegNo & 1) != 0) 1551 return MCDisassembler::Fail; 1552 RegNo >>= 1; 1553 1554 unsigned Register = QPRDecoderTable[RegNo]; 1555 Inst.addOperand(MCOperand::createReg(Register)); 1556 return MCDisassembler::Success; 1557 } 1558 1559 static const uint16_t DPairDecoderTable[] = { 1560 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1561 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1562 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1563 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1564 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1565 ARM::Q15 1566 }; 1567 1568 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1569 uint64_t Address, 1570 const MCDisassembler *Decoder) { 1571 if (RegNo > 30) 1572 return MCDisassembler::Fail; 1573 1574 unsigned Register = DPairDecoderTable[RegNo]; 1575 Inst.addOperand(MCOperand::createReg(Register)); 1576 return MCDisassembler::Success; 1577 } 1578 1579 static const uint16_t DPairSpacedDecoderTable[] = { 1580 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1581 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1582 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1583 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1584 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1585 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1586 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1587 ARM::D28_D30, ARM::D29_D31 1588 }; 1589 1590 static DecodeStatus 1591 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1592 const MCDisassembler *Decoder) { 1593 if (RegNo > 29) 1594 return MCDisassembler::Fail; 1595 1596 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1597 Inst.addOperand(MCOperand::createReg(Register)); 1598 return MCDisassembler::Success; 1599 } 1600 1601 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1602 uint64_t Address, 1603 const MCDisassembler *Decoder) { 1604 DecodeStatus S = MCDisassembler::Success; 1605 if (Val == 0xF) return MCDisassembler::Fail; 1606 // AL predicate is not allowed on Thumb1 branches. 1607 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1608 return MCDisassembler::Fail; 1609 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1610 Check(S, MCDisassembler::SoftFail); 1611 Inst.addOperand(MCOperand::createImm(Val)); 1612 if (Val == ARMCC::AL) { 1613 Inst.addOperand(MCOperand::createReg(0)); 1614 } else 1615 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1616 return S; 1617 } 1618 1619 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1620 uint64_t Address, 1621 const MCDisassembler *Decoder) { 1622 if (Val) 1623 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1624 else 1625 Inst.addOperand(MCOperand::createReg(0)); 1626 return MCDisassembler::Success; 1627 } 1628 1629 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1630 uint64_t Address, 1631 const MCDisassembler *Decoder) { 1632 DecodeStatus S = MCDisassembler::Success; 1633 1634 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1635 unsigned type = fieldFromInstruction(Val, 5, 2); 1636 unsigned imm = fieldFromInstruction(Val, 7, 5); 1637 1638 // Register-immediate 1639 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1640 return MCDisassembler::Fail; 1641 1642 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1643 switch (type) { 1644 case 0: 1645 Shift = ARM_AM::lsl; 1646 break; 1647 case 1: 1648 Shift = ARM_AM::lsr; 1649 break; 1650 case 2: 1651 Shift = ARM_AM::asr; 1652 break; 1653 case 3: 1654 Shift = ARM_AM::ror; 1655 break; 1656 } 1657 1658 if (Shift == ARM_AM::ror && imm == 0) 1659 Shift = ARM_AM::rrx; 1660 1661 unsigned Op = Shift | (imm << 3); 1662 Inst.addOperand(MCOperand::createImm(Op)); 1663 1664 return S; 1665 } 1666 1667 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1668 uint64_t Address, 1669 const MCDisassembler *Decoder) { 1670 DecodeStatus S = MCDisassembler::Success; 1671 1672 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1673 unsigned type = fieldFromInstruction(Val, 5, 2); 1674 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1675 1676 // Register-register 1677 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1678 return MCDisassembler::Fail; 1679 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1680 return MCDisassembler::Fail; 1681 1682 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1683 switch (type) { 1684 case 0: 1685 Shift = ARM_AM::lsl; 1686 break; 1687 case 1: 1688 Shift = ARM_AM::lsr; 1689 break; 1690 case 2: 1691 Shift = ARM_AM::asr; 1692 break; 1693 case 3: 1694 Shift = ARM_AM::ror; 1695 break; 1696 } 1697 1698 Inst.addOperand(MCOperand::createImm(Shift)); 1699 1700 return S; 1701 } 1702 1703 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1704 uint64_t Address, 1705 const MCDisassembler *Decoder) { 1706 DecodeStatus S = MCDisassembler::Success; 1707 1708 bool NeedDisjointWriteback = false; 1709 unsigned WritebackReg = 0; 1710 bool CLRM = false; 1711 switch (Inst.getOpcode()) { 1712 default: 1713 break; 1714 case ARM::LDMIA_UPD: 1715 case ARM::LDMDB_UPD: 1716 case ARM::LDMIB_UPD: 1717 case ARM::LDMDA_UPD: 1718 case ARM::t2LDMIA_UPD: 1719 case ARM::t2LDMDB_UPD: 1720 case ARM::t2STMIA_UPD: 1721 case ARM::t2STMDB_UPD: 1722 NeedDisjointWriteback = true; 1723 WritebackReg = Inst.getOperand(0).getReg(); 1724 break; 1725 case ARM::t2CLRM: 1726 CLRM = true; 1727 break; 1728 } 1729 1730 // Empty register lists are not allowed. 1731 if (Val == 0) return MCDisassembler::Fail; 1732 for (unsigned i = 0; i < 16; ++i) { 1733 if (Val & (1 << i)) { 1734 if (CLRM) { 1735 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1736 return MCDisassembler::Fail; 1737 } 1738 } else { 1739 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1740 return MCDisassembler::Fail; 1741 // Writeback not allowed if Rn is in the target list. 1742 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1743 Check(S, MCDisassembler::SoftFail); 1744 } 1745 } 1746 } 1747 1748 return S; 1749 } 1750 1751 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1752 uint64_t Address, 1753 const MCDisassembler *Decoder) { 1754 DecodeStatus S = MCDisassembler::Success; 1755 1756 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1757 unsigned regs = fieldFromInstruction(Val, 0, 8); 1758 1759 // In case of unpredictable encoding, tweak the operands. 1760 if (regs == 0 || (Vd + regs) > 32) { 1761 regs = Vd + regs > 32 ? 32 - Vd : regs; 1762 regs = std::max( 1u, regs); 1763 S = MCDisassembler::SoftFail; 1764 } 1765 1766 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1767 return MCDisassembler::Fail; 1768 for (unsigned i = 0; i < (regs - 1); ++i) { 1769 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1770 return MCDisassembler::Fail; 1771 } 1772 1773 return S; 1774 } 1775 1776 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1777 uint64_t Address, 1778 const MCDisassembler *Decoder) { 1779 DecodeStatus S = MCDisassembler::Success; 1780 1781 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1782 unsigned regs = fieldFromInstruction(Val, 1, 7); 1783 1784 // In case of unpredictable encoding, tweak the operands. 1785 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1786 regs = Vd + regs > 32 ? 32 - Vd : regs; 1787 regs = std::max( 1u, regs); 1788 regs = std::min(16u, regs); 1789 S = MCDisassembler::SoftFail; 1790 } 1791 1792 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1793 return MCDisassembler::Fail; 1794 for (unsigned i = 0; i < (regs - 1); ++i) { 1795 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1796 return MCDisassembler::Fail; 1797 } 1798 1799 return S; 1800 } 1801 1802 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1803 uint64_t Address, 1804 const MCDisassembler *Decoder) { 1805 // This operand encodes a mask of contiguous zeros between a specified MSB 1806 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1807 // the mask of all bits LSB-and-lower, and then xor them to create 1808 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1809 // create the final mask. 1810 unsigned msb = fieldFromInstruction(Val, 5, 5); 1811 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1812 1813 DecodeStatus S = MCDisassembler::Success; 1814 if (lsb > msb) { 1815 Check(S, MCDisassembler::SoftFail); 1816 // The check above will cause the warning for the "potentially undefined 1817 // instruction encoding" but we can't build a bad MCOperand value here 1818 // with a lsb > msb or else printing the MCInst will cause a crash. 1819 lsb = msb; 1820 } 1821 1822 uint32_t msb_mask = 0xFFFFFFFF; 1823 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1824 uint32_t lsb_mask = (1U << lsb) - 1; 1825 1826 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1827 return S; 1828 } 1829 1830 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1831 uint64_t Address, 1832 const MCDisassembler *Decoder) { 1833 DecodeStatus S = MCDisassembler::Success; 1834 1835 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1836 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1837 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1838 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1839 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1840 unsigned U = fieldFromInstruction(Insn, 23, 1); 1841 const FeatureBitset &featureBits = 1842 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1843 1844 switch (Inst.getOpcode()) { 1845 case ARM::LDC_OFFSET: 1846 case ARM::LDC_PRE: 1847 case ARM::LDC_POST: 1848 case ARM::LDC_OPTION: 1849 case ARM::LDCL_OFFSET: 1850 case ARM::LDCL_PRE: 1851 case ARM::LDCL_POST: 1852 case ARM::LDCL_OPTION: 1853 case ARM::STC_OFFSET: 1854 case ARM::STC_PRE: 1855 case ARM::STC_POST: 1856 case ARM::STC_OPTION: 1857 case ARM::STCL_OFFSET: 1858 case ARM::STCL_PRE: 1859 case ARM::STCL_POST: 1860 case ARM::STCL_OPTION: 1861 case ARM::t2LDC_OFFSET: 1862 case ARM::t2LDC_PRE: 1863 case ARM::t2LDC_POST: 1864 case ARM::t2LDC_OPTION: 1865 case ARM::t2LDCL_OFFSET: 1866 case ARM::t2LDCL_PRE: 1867 case ARM::t2LDCL_POST: 1868 case ARM::t2LDCL_OPTION: 1869 case ARM::t2STC_OFFSET: 1870 case ARM::t2STC_PRE: 1871 case ARM::t2STC_POST: 1872 case ARM::t2STC_OPTION: 1873 case ARM::t2STCL_OFFSET: 1874 case ARM::t2STCL_PRE: 1875 case ARM::t2STCL_POST: 1876 case ARM::t2STCL_OPTION: 1877 case ARM::t2LDC2_OFFSET: 1878 case ARM::t2LDC2L_OFFSET: 1879 case ARM::t2LDC2_PRE: 1880 case ARM::t2LDC2L_PRE: 1881 case ARM::t2STC2_OFFSET: 1882 case ARM::t2STC2L_OFFSET: 1883 case ARM::t2STC2_PRE: 1884 case ARM::t2STC2L_PRE: 1885 case ARM::LDC2_OFFSET: 1886 case ARM::LDC2L_OFFSET: 1887 case ARM::LDC2_PRE: 1888 case ARM::LDC2L_PRE: 1889 case ARM::STC2_OFFSET: 1890 case ARM::STC2L_OFFSET: 1891 case ARM::STC2_PRE: 1892 case ARM::STC2L_PRE: 1893 case ARM::t2LDC2_OPTION: 1894 case ARM::t2STC2_OPTION: 1895 case ARM::t2LDC2_POST: 1896 case ARM::t2LDC2L_POST: 1897 case ARM::t2STC2_POST: 1898 case ARM::t2STC2L_POST: 1899 case ARM::LDC2_POST: 1900 case ARM::LDC2L_POST: 1901 case ARM::STC2_POST: 1902 case ARM::STC2L_POST: 1903 if (coproc == 0xA || coproc == 0xB || 1904 (featureBits[ARM::HasV8_1MMainlineOps] && 1905 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1906 coproc == 0xE || coproc == 0xF))) 1907 return MCDisassembler::Fail; 1908 break; 1909 default: 1910 break; 1911 } 1912 1913 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1914 return MCDisassembler::Fail; 1915 1916 Inst.addOperand(MCOperand::createImm(coproc)); 1917 Inst.addOperand(MCOperand::createImm(CRd)); 1918 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1919 return MCDisassembler::Fail; 1920 1921 switch (Inst.getOpcode()) { 1922 case ARM::t2LDC2_OFFSET: 1923 case ARM::t2LDC2L_OFFSET: 1924 case ARM::t2LDC2_PRE: 1925 case ARM::t2LDC2L_PRE: 1926 case ARM::t2STC2_OFFSET: 1927 case ARM::t2STC2L_OFFSET: 1928 case ARM::t2STC2_PRE: 1929 case ARM::t2STC2L_PRE: 1930 case ARM::LDC2_OFFSET: 1931 case ARM::LDC2L_OFFSET: 1932 case ARM::LDC2_PRE: 1933 case ARM::LDC2L_PRE: 1934 case ARM::STC2_OFFSET: 1935 case ARM::STC2L_OFFSET: 1936 case ARM::STC2_PRE: 1937 case ARM::STC2L_PRE: 1938 case ARM::t2LDC_OFFSET: 1939 case ARM::t2LDCL_OFFSET: 1940 case ARM::t2LDC_PRE: 1941 case ARM::t2LDCL_PRE: 1942 case ARM::t2STC_OFFSET: 1943 case ARM::t2STCL_OFFSET: 1944 case ARM::t2STC_PRE: 1945 case ARM::t2STCL_PRE: 1946 case ARM::LDC_OFFSET: 1947 case ARM::LDCL_OFFSET: 1948 case ARM::LDC_PRE: 1949 case ARM::LDCL_PRE: 1950 case ARM::STC_OFFSET: 1951 case ARM::STCL_OFFSET: 1952 case ARM::STC_PRE: 1953 case ARM::STCL_PRE: 1954 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1955 Inst.addOperand(MCOperand::createImm(imm)); 1956 break; 1957 case ARM::t2LDC2_POST: 1958 case ARM::t2LDC2L_POST: 1959 case ARM::t2STC2_POST: 1960 case ARM::t2STC2L_POST: 1961 case ARM::LDC2_POST: 1962 case ARM::LDC2L_POST: 1963 case ARM::STC2_POST: 1964 case ARM::STC2L_POST: 1965 case ARM::t2LDC_POST: 1966 case ARM::t2LDCL_POST: 1967 case ARM::t2STC_POST: 1968 case ARM::t2STCL_POST: 1969 case ARM::LDC_POST: 1970 case ARM::LDCL_POST: 1971 case ARM::STC_POST: 1972 case ARM::STCL_POST: 1973 imm |= U << 8; 1974 LLVM_FALLTHROUGH; 1975 default: 1976 // The 'option' variant doesn't encode 'U' in the immediate since 1977 // the immediate is unsigned [0,255]. 1978 Inst.addOperand(MCOperand::createImm(imm)); 1979 break; 1980 } 1981 1982 switch (Inst.getOpcode()) { 1983 case ARM::LDC_OFFSET: 1984 case ARM::LDC_PRE: 1985 case ARM::LDC_POST: 1986 case ARM::LDC_OPTION: 1987 case ARM::LDCL_OFFSET: 1988 case ARM::LDCL_PRE: 1989 case ARM::LDCL_POST: 1990 case ARM::LDCL_OPTION: 1991 case ARM::STC_OFFSET: 1992 case ARM::STC_PRE: 1993 case ARM::STC_POST: 1994 case ARM::STC_OPTION: 1995 case ARM::STCL_OFFSET: 1996 case ARM::STCL_PRE: 1997 case ARM::STCL_POST: 1998 case ARM::STCL_OPTION: 1999 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2000 return MCDisassembler::Fail; 2001 break; 2002 default: 2003 break; 2004 } 2005 2006 return S; 2007 } 2008 2009 static DecodeStatus 2010 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2011 const MCDisassembler *Decoder) { 2012 DecodeStatus S = MCDisassembler::Success; 2013 2014 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2015 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2016 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2017 unsigned imm = fieldFromInstruction(Insn, 0, 12); 2018 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2019 unsigned reg = fieldFromInstruction(Insn, 25, 1); 2020 unsigned P = fieldFromInstruction(Insn, 24, 1); 2021 unsigned W = fieldFromInstruction(Insn, 21, 1); 2022 2023 // On stores, the writeback operand precedes Rt. 2024 switch (Inst.getOpcode()) { 2025 case ARM::STR_POST_IMM: 2026 case ARM::STR_POST_REG: 2027 case ARM::STRB_POST_IMM: 2028 case ARM::STRB_POST_REG: 2029 case ARM::STRT_POST_REG: 2030 case ARM::STRT_POST_IMM: 2031 case ARM::STRBT_POST_REG: 2032 case ARM::STRBT_POST_IMM: 2033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2034 return MCDisassembler::Fail; 2035 break; 2036 default: 2037 break; 2038 } 2039 2040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2041 return MCDisassembler::Fail; 2042 2043 // On loads, the writeback operand comes after Rt. 2044 switch (Inst.getOpcode()) { 2045 case ARM::LDR_POST_IMM: 2046 case ARM::LDR_POST_REG: 2047 case ARM::LDRB_POST_IMM: 2048 case ARM::LDRB_POST_REG: 2049 case ARM::LDRBT_POST_REG: 2050 case ARM::LDRBT_POST_IMM: 2051 case ARM::LDRT_POST_REG: 2052 case ARM::LDRT_POST_IMM: 2053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2054 return MCDisassembler::Fail; 2055 break; 2056 default: 2057 break; 2058 } 2059 2060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2061 return MCDisassembler::Fail; 2062 2063 ARM_AM::AddrOpc Op = ARM_AM::add; 2064 if (!fieldFromInstruction(Insn, 23, 1)) 2065 Op = ARM_AM::sub; 2066 2067 bool writeback = (P == 0) || (W == 1); 2068 unsigned idx_mode = 0; 2069 if (P && writeback) 2070 idx_mode = ARMII::IndexModePre; 2071 else if (!P && writeback) 2072 idx_mode = ARMII::IndexModePost; 2073 2074 if (writeback && (Rn == 15 || Rn == Rt)) 2075 S = MCDisassembler::SoftFail; // UNPREDICTABLE 2076 2077 if (reg) { 2078 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2079 return MCDisassembler::Fail; 2080 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 2081 switch( fieldFromInstruction(Insn, 5, 2)) { 2082 case 0: 2083 Opc = ARM_AM::lsl; 2084 break; 2085 case 1: 2086 Opc = ARM_AM::lsr; 2087 break; 2088 case 2: 2089 Opc = ARM_AM::asr; 2090 break; 2091 case 3: 2092 Opc = ARM_AM::ror; 2093 break; 2094 default: 2095 return MCDisassembler::Fail; 2096 } 2097 unsigned amt = fieldFromInstruction(Insn, 7, 5); 2098 if (Opc == ARM_AM::ror && amt == 0) 2099 Opc = ARM_AM::rrx; 2100 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 2101 2102 Inst.addOperand(MCOperand::createImm(imm)); 2103 } else { 2104 Inst.addOperand(MCOperand::createReg(0)); 2105 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 2106 Inst.addOperand(MCOperand::createImm(tmp)); 2107 } 2108 2109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 2112 return S; 2113 } 2114 2115 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 2116 uint64_t Address, 2117 const MCDisassembler *Decoder) { 2118 DecodeStatus S = MCDisassembler::Success; 2119 2120 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2121 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2122 unsigned type = fieldFromInstruction(Val, 5, 2); 2123 unsigned imm = fieldFromInstruction(Val, 7, 5); 2124 unsigned U = fieldFromInstruction(Val, 12, 1); 2125 2126 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 2127 switch (type) { 2128 case 0: 2129 ShOp = ARM_AM::lsl; 2130 break; 2131 case 1: 2132 ShOp = ARM_AM::lsr; 2133 break; 2134 case 2: 2135 ShOp = ARM_AM::asr; 2136 break; 2137 case 3: 2138 ShOp = ARM_AM::ror; 2139 break; 2140 } 2141 2142 if (ShOp == ARM_AM::ror && imm == 0) 2143 ShOp = ARM_AM::rrx; 2144 2145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2146 return MCDisassembler::Fail; 2147 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2148 return MCDisassembler::Fail; 2149 unsigned shift; 2150 if (U) 2151 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 2152 else 2153 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 2154 Inst.addOperand(MCOperand::createImm(shift)); 2155 2156 return S; 2157 } 2158 2159 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 2160 uint64_t Address, 2161 const MCDisassembler *Decoder) { 2162 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) 2163 return MCDisassembler::Fail; 2164 2165 // The "csync" operand is not encoded into the "tsb" instruction (as this is 2166 // the only available operand), but LLVM expects the instruction to have one 2167 // operand, so we need to add the csync when decoding. 2168 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC)); 2169 return MCDisassembler::Success; 2170 } 2171 2172 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 2173 uint64_t Address, 2174 const MCDisassembler *Decoder) { 2175 DecodeStatus S = MCDisassembler::Success; 2176 2177 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2178 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2179 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2180 unsigned type = fieldFromInstruction(Insn, 22, 1); 2181 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2182 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2183 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2184 unsigned W = fieldFromInstruction(Insn, 21, 1); 2185 unsigned P = fieldFromInstruction(Insn, 24, 1); 2186 unsigned Rt2 = Rt + 1; 2187 2188 bool writeback = (W == 1) | (P == 0); 2189 2190 // For {LD,ST}RD, Rt must be even, else undefined. 2191 switch (Inst.getOpcode()) { 2192 case ARM::STRD: 2193 case ARM::STRD_PRE: 2194 case ARM::STRD_POST: 2195 case ARM::LDRD: 2196 case ARM::LDRD_PRE: 2197 case ARM::LDRD_POST: 2198 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2199 break; 2200 default: 2201 break; 2202 } 2203 switch (Inst.getOpcode()) { 2204 case ARM::STRD: 2205 case ARM::STRD_PRE: 2206 case ARM::STRD_POST: 2207 if (P == 0 && W == 1) 2208 S = MCDisassembler::SoftFail; 2209 2210 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2211 S = MCDisassembler::SoftFail; 2212 if (type && Rm == 15) 2213 S = MCDisassembler::SoftFail; 2214 if (Rt2 == 15) 2215 S = MCDisassembler::SoftFail; 2216 if (!type && fieldFromInstruction(Insn, 8, 4)) 2217 S = MCDisassembler::SoftFail; 2218 break; 2219 case ARM::STRH: 2220 case ARM::STRH_PRE: 2221 case ARM::STRH_POST: 2222 if (Rt == 15) 2223 S = MCDisassembler::SoftFail; 2224 if (writeback && (Rn == 15 || Rn == Rt)) 2225 S = MCDisassembler::SoftFail; 2226 if (!type && Rm == 15) 2227 S = MCDisassembler::SoftFail; 2228 break; 2229 case ARM::LDRD: 2230 case ARM::LDRD_PRE: 2231 case ARM::LDRD_POST: 2232 if (type && Rn == 15) { 2233 if (Rt2 == 15) 2234 S = MCDisassembler::SoftFail; 2235 break; 2236 } 2237 if (P == 0 && W == 1) 2238 S = MCDisassembler::SoftFail; 2239 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2240 S = MCDisassembler::SoftFail; 2241 if (!type && writeback && Rn == 15) 2242 S = MCDisassembler::SoftFail; 2243 if (writeback && (Rn == Rt || Rn == Rt2)) 2244 S = MCDisassembler::SoftFail; 2245 break; 2246 case ARM::LDRH: 2247 case ARM::LDRH_PRE: 2248 case ARM::LDRH_POST: 2249 if (type && Rn == 15) { 2250 if (Rt == 15) 2251 S = MCDisassembler::SoftFail; 2252 break; 2253 } 2254 if (Rt == 15) 2255 S = MCDisassembler::SoftFail; 2256 if (!type && Rm == 15) 2257 S = MCDisassembler::SoftFail; 2258 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2259 S = MCDisassembler::SoftFail; 2260 break; 2261 case ARM::LDRSH: 2262 case ARM::LDRSH_PRE: 2263 case ARM::LDRSH_POST: 2264 case ARM::LDRSB: 2265 case ARM::LDRSB_PRE: 2266 case ARM::LDRSB_POST: 2267 if (type && Rn == 15) { 2268 if (Rt == 15) 2269 S = MCDisassembler::SoftFail; 2270 break; 2271 } 2272 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2273 S = MCDisassembler::SoftFail; 2274 if (!type && (Rt == 15 || Rm == 15)) 2275 S = MCDisassembler::SoftFail; 2276 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2277 S = MCDisassembler::SoftFail; 2278 break; 2279 default: 2280 break; 2281 } 2282 2283 if (writeback) { // Writeback 2284 if (P) 2285 U |= ARMII::IndexModePre << 9; 2286 else 2287 U |= ARMII::IndexModePost << 9; 2288 2289 // On stores, the writeback operand precedes Rt. 2290 switch (Inst.getOpcode()) { 2291 case ARM::STRD: 2292 case ARM::STRD_PRE: 2293 case ARM::STRD_POST: 2294 case ARM::STRH: 2295 case ARM::STRH_PRE: 2296 case ARM::STRH_POST: 2297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2298 return MCDisassembler::Fail; 2299 break; 2300 default: 2301 break; 2302 } 2303 } 2304 2305 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2306 return MCDisassembler::Fail; 2307 switch (Inst.getOpcode()) { 2308 case ARM::STRD: 2309 case ARM::STRD_PRE: 2310 case ARM::STRD_POST: 2311 case ARM::LDRD: 2312 case ARM::LDRD_PRE: 2313 case ARM::LDRD_POST: 2314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2315 return MCDisassembler::Fail; 2316 break; 2317 default: 2318 break; 2319 } 2320 2321 if (writeback) { 2322 // On loads, the writeback operand comes after Rt. 2323 switch (Inst.getOpcode()) { 2324 case ARM::LDRD: 2325 case ARM::LDRD_PRE: 2326 case ARM::LDRD_POST: 2327 case ARM::LDRH: 2328 case ARM::LDRH_PRE: 2329 case ARM::LDRH_POST: 2330 case ARM::LDRSH: 2331 case ARM::LDRSH_PRE: 2332 case ARM::LDRSH_POST: 2333 case ARM::LDRSB: 2334 case ARM::LDRSB_PRE: 2335 case ARM::LDRSB_POST: 2336 case ARM::LDRHTr: 2337 case ARM::LDRSBTr: 2338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2339 return MCDisassembler::Fail; 2340 break; 2341 default: 2342 break; 2343 } 2344 } 2345 2346 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2347 return MCDisassembler::Fail; 2348 2349 if (type) { 2350 Inst.addOperand(MCOperand::createReg(0)); 2351 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2352 } else { 2353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2354 return MCDisassembler::Fail; 2355 Inst.addOperand(MCOperand::createImm(U)); 2356 } 2357 2358 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2359 return MCDisassembler::Fail; 2360 2361 return S; 2362 } 2363 2364 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2365 uint64_t Address, 2366 const MCDisassembler *Decoder) { 2367 DecodeStatus S = MCDisassembler::Success; 2368 2369 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2370 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2371 2372 switch (mode) { 2373 case 0: 2374 mode = ARM_AM::da; 2375 break; 2376 case 1: 2377 mode = ARM_AM::ia; 2378 break; 2379 case 2: 2380 mode = ARM_AM::db; 2381 break; 2382 case 3: 2383 mode = ARM_AM::ib; 2384 break; 2385 } 2386 2387 Inst.addOperand(MCOperand::createImm(mode)); 2388 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2389 return MCDisassembler::Fail; 2390 2391 return S; 2392 } 2393 2394 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2395 uint64_t Address, 2396 const MCDisassembler *Decoder) { 2397 DecodeStatus S = MCDisassembler::Success; 2398 2399 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2400 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2401 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2402 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2403 2404 if (pred == 0xF) 2405 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2406 2407 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2408 return MCDisassembler::Fail; 2409 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2410 return MCDisassembler::Fail; 2411 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2412 return MCDisassembler::Fail; 2413 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2414 return MCDisassembler::Fail; 2415 return S; 2416 } 2417 2418 static DecodeStatus 2419 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 2420 uint64_t Address, 2421 const MCDisassembler *Decoder) { 2422 DecodeStatus S = MCDisassembler::Success; 2423 2424 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2425 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2426 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2427 2428 if (pred == 0xF) { 2429 // Ambiguous with RFE and SRS 2430 switch (Inst.getOpcode()) { 2431 case ARM::LDMDA: 2432 Inst.setOpcode(ARM::RFEDA); 2433 break; 2434 case ARM::LDMDA_UPD: 2435 Inst.setOpcode(ARM::RFEDA_UPD); 2436 break; 2437 case ARM::LDMDB: 2438 Inst.setOpcode(ARM::RFEDB); 2439 break; 2440 case ARM::LDMDB_UPD: 2441 Inst.setOpcode(ARM::RFEDB_UPD); 2442 break; 2443 case ARM::LDMIA: 2444 Inst.setOpcode(ARM::RFEIA); 2445 break; 2446 case ARM::LDMIA_UPD: 2447 Inst.setOpcode(ARM::RFEIA_UPD); 2448 break; 2449 case ARM::LDMIB: 2450 Inst.setOpcode(ARM::RFEIB); 2451 break; 2452 case ARM::LDMIB_UPD: 2453 Inst.setOpcode(ARM::RFEIB_UPD); 2454 break; 2455 case ARM::STMDA: 2456 Inst.setOpcode(ARM::SRSDA); 2457 break; 2458 case ARM::STMDA_UPD: 2459 Inst.setOpcode(ARM::SRSDA_UPD); 2460 break; 2461 case ARM::STMDB: 2462 Inst.setOpcode(ARM::SRSDB); 2463 break; 2464 case ARM::STMDB_UPD: 2465 Inst.setOpcode(ARM::SRSDB_UPD); 2466 break; 2467 case ARM::STMIA: 2468 Inst.setOpcode(ARM::SRSIA); 2469 break; 2470 case ARM::STMIA_UPD: 2471 Inst.setOpcode(ARM::SRSIA_UPD); 2472 break; 2473 case ARM::STMIB: 2474 Inst.setOpcode(ARM::SRSIB); 2475 break; 2476 case ARM::STMIB_UPD: 2477 Inst.setOpcode(ARM::SRSIB_UPD); 2478 break; 2479 default: 2480 return MCDisassembler::Fail; 2481 } 2482 2483 // For stores (which become SRS's, the only operand is the mode. 2484 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2485 // Check SRS encoding constraints 2486 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2487 fieldFromInstruction(Insn, 20, 1) == 0)) 2488 return MCDisassembler::Fail; 2489 2490 Inst.addOperand( 2491 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2492 return S; 2493 } 2494 2495 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2496 } 2497 2498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2499 return MCDisassembler::Fail; 2500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2501 return MCDisassembler::Fail; // Tied 2502 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2503 return MCDisassembler::Fail; 2504 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2505 return MCDisassembler::Fail; 2506 2507 return S; 2508 } 2509 2510 // Check for UNPREDICTABLE predicated ESB instruction 2511 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2512 uint64_t Address, 2513 const MCDisassembler *Decoder) { 2514 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2515 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2516 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2517 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2518 2519 DecodeStatus S = MCDisassembler::Success; 2520 2521 Inst.addOperand(MCOperand::createImm(imm8)); 2522 2523 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2524 return MCDisassembler::Fail; 2525 2526 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2527 // so all predicates should be allowed. 2528 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2529 S = MCDisassembler::SoftFail; 2530 2531 return S; 2532 } 2533 2534 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2535 uint64_t Address, 2536 const MCDisassembler *Decoder) { 2537 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2538 unsigned M = fieldFromInstruction(Insn, 17, 1); 2539 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2540 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2541 2542 DecodeStatus S = MCDisassembler::Success; 2543 2544 // This decoder is called from multiple location that do not check 2545 // the full encoding is valid before they do. 2546 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2547 fieldFromInstruction(Insn, 16, 1) != 0 || 2548 fieldFromInstruction(Insn, 20, 8) != 0x10) 2549 return MCDisassembler::Fail; 2550 2551 // imod == '01' --> UNPREDICTABLE 2552 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2553 // return failure here. The '01' imod value is unprintable, so there's 2554 // nothing useful we could do even if we returned UNPREDICTABLE. 2555 2556 if (imod == 1) return MCDisassembler::Fail; 2557 2558 if (imod && M) { 2559 Inst.setOpcode(ARM::CPS3p); 2560 Inst.addOperand(MCOperand::createImm(imod)); 2561 Inst.addOperand(MCOperand::createImm(iflags)); 2562 Inst.addOperand(MCOperand::createImm(mode)); 2563 } else if (imod && !M) { 2564 Inst.setOpcode(ARM::CPS2p); 2565 Inst.addOperand(MCOperand::createImm(imod)); 2566 Inst.addOperand(MCOperand::createImm(iflags)); 2567 if (mode) S = MCDisassembler::SoftFail; 2568 } else if (!imod && M) { 2569 Inst.setOpcode(ARM::CPS1p); 2570 Inst.addOperand(MCOperand::createImm(mode)); 2571 if (iflags) S = MCDisassembler::SoftFail; 2572 } else { 2573 // imod == '00' && M == '0' --> UNPREDICTABLE 2574 Inst.setOpcode(ARM::CPS1p); 2575 Inst.addOperand(MCOperand::createImm(mode)); 2576 S = MCDisassembler::SoftFail; 2577 } 2578 2579 return S; 2580 } 2581 2582 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2583 uint64_t Address, 2584 const MCDisassembler *Decoder) { 2585 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2586 unsigned M = fieldFromInstruction(Insn, 8, 1); 2587 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2588 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2589 2590 DecodeStatus S = MCDisassembler::Success; 2591 2592 // imod == '01' --> UNPREDICTABLE 2593 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2594 // return failure here. The '01' imod value is unprintable, so there's 2595 // nothing useful we could do even if we returned UNPREDICTABLE. 2596 2597 if (imod == 1) return MCDisassembler::Fail; 2598 2599 if (imod && M) { 2600 Inst.setOpcode(ARM::t2CPS3p); 2601 Inst.addOperand(MCOperand::createImm(imod)); 2602 Inst.addOperand(MCOperand::createImm(iflags)); 2603 Inst.addOperand(MCOperand::createImm(mode)); 2604 } else if (imod && !M) { 2605 Inst.setOpcode(ARM::t2CPS2p); 2606 Inst.addOperand(MCOperand::createImm(imod)); 2607 Inst.addOperand(MCOperand::createImm(iflags)); 2608 if (mode) S = MCDisassembler::SoftFail; 2609 } else if (!imod && M) { 2610 Inst.setOpcode(ARM::t2CPS1p); 2611 Inst.addOperand(MCOperand::createImm(mode)); 2612 if (iflags) S = MCDisassembler::SoftFail; 2613 } else { 2614 // imod == '00' && M == '0' --> this is a HINT instruction 2615 int imm = fieldFromInstruction(Insn, 0, 8); 2616 // HINT are defined only for immediate in [0..4] 2617 if(imm > 4) return MCDisassembler::Fail; 2618 Inst.setOpcode(ARM::t2HINT); 2619 Inst.addOperand(MCOperand::createImm(imm)); 2620 } 2621 2622 return S; 2623 } 2624 2625 static DecodeStatus 2626 DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2627 const MCDisassembler *Decoder) { 2628 unsigned imm = fieldFromInstruction(Insn, 0, 8); 2629 2630 unsigned Opcode = ARM::t2HINT; 2631 2632 if (imm == 0x0D) { 2633 Opcode = ARM::t2PACBTI; 2634 } else if (imm == 0x1D) { 2635 Opcode = ARM::t2PAC; 2636 } else if (imm == 0x2D) { 2637 Opcode = ARM::t2AUT; 2638 } else if (imm == 0x0F) { 2639 Opcode = ARM::t2BTI; 2640 } 2641 2642 Inst.setOpcode(Opcode); 2643 if (Opcode == ARM::t2HINT) { 2644 Inst.addOperand(MCOperand::createImm(imm)); 2645 } 2646 2647 return MCDisassembler::Success; 2648 } 2649 2650 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2651 uint64_t Address, 2652 const MCDisassembler *Decoder) { 2653 DecodeStatus S = MCDisassembler::Success; 2654 2655 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2656 unsigned imm = 0; 2657 2658 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2659 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2660 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2661 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2662 2663 if (Inst.getOpcode() == ARM::t2MOVTi16) 2664 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2665 return MCDisassembler::Fail; 2666 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2667 return MCDisassembler::Fail; 2668 2669 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2670 Inst.addOperand(MCOperand::createImm(imm)); 2671 2672 return S; 2673 } 2674 2675 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2676 uint64_t Address, 2677 const MCDisassembler *Decoder) { 2678 DecodeStatus S = MCDisassembler::Success; 2679 2680 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2681 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2682 unsigned imm = 0; 2683 2684 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2685 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2686 2687 if (Inst.getOpcode() == ARM::MOVTi16) 2688 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2689 return MCDisassembler::Fail; 2690 2691 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2692 return MCDisassembler::Fail; 2693 2694 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2695 Inst.addOperand(MCOperand::createImm(imm)); 2696 2697 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2698 return MCDisassembler::Fail; 2699 2700 return S; 2701 } 2702 2703 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2704 uint64_t Address, 2705 const MCDisassembler *Decoder) { 2706 DecodeStatus S = MCDisassembler::Success; 2707 2708 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2709 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2710 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2711 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2712 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2713 2714 if (pred == 0xF) 2715 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2716 2717 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2718 return MCDisassembler::Fail; 2719 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2720 return MCDisassembler::Fail; 2721 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2724 return MCDisassembler::Fail; 2725 2726 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2727 return MCDisassembler::Fail; 2728 2729 return S; 2730 } 2731 2732 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2733 uint64_t Address, 2734 const MCDisassembler *Decoder) { 2735 DecodeStatus S = MCDisassembler::Success; 2736 2737 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2738 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2739 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2740 2741 if (Pred == 0xF) 2742 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2743 2744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2745 return MCDisassembler::Fail; 2746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2747 return MCDisassembler::Fail; 2748 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 2751 return S; 2752 } 2753 2754 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2755 uint64_t Address, 2756 const MCDisassembler *Decoder) { 2757 DecodeStatus S = MCDisassembler::Success; 2758 2759 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2760 2761 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2762 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2763 2764 if (!FeatureBits[ARM::HasV8_1aOps] || 2765 !FeatureBits[ARM::HasV8Ops]) 2766 return MCDisassembler::Fail; 2767 2768 // Decoder can be called from DecodeTST, which does not check the full 2769 // encoding is valid. 2770 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2771 fieldFromInstruction(Insn, 4,4) != 0) 2772 return MCDisassembler::Fail; 2773 if (fieldFromInstruction(Insn, 10,10) != 0 || 2774 fieldFromInstruction(Insn, 0,4) != 0) 2775 S = MCDisassembler::SoftFail; 2776 2777 Inst.setOpcode(ARM::SETPAN); 2778 Inst.addOperand(MCOperand::createImm(Imm)); 2779 2780 return S; 2781 } 2782 2783 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2784 uint64_t Address, 2785 const MCDisassembler *Decoder) { 2786 DecodeStatus S = MCDisassembler::Success; 2787 2788 unsigned add = fieldFromInstruction(Val, 12, 1); 2789 unsigned imm = fieldFromInstruction(Val, 0, 12); 2790 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2791 2792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 2795 if (!add) imm *= -1; 2796 if (imm == 0 && !add) imm = INT32_MIN; 2797 Inst.addOperand(MCOperand::createImm(imm)); 2798 if (Rn == 15) 2799 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2800 2801 return S; 2802 } 2803 2804 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2805 uint64_t Address, 2806 const MCDisassembler *Decoder) { 2807 DecodeStatus S = MCDisassembler::Success; 2808 2809 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2810 // U == 1 to add imm, 0 to subtract it. 2811 unsigned U = fieldFromInstruction(Val, 8, 1); 2812 unsigned imm = fieldFromInstruction(Val, 0, 8); 2813 2814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2815 return MCDisassembler::Fail; 2816 2817 if (U) 2818 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2819 else 2820 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2821 2822 return S; 2823 } 2824 2825 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2826 uint64_t Address, 2827 const MCDisassembler *Decoder) { 2828 DecodeStatus S = MCDisassembler::Success; 2829 2830 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2831 // U == 1 to add imm, 0 to subtract it. 2832 unsigned U = fieldFromInstruction(Val, 8, 1); 2833 unsigned imm = fieldFromInstruction(Val, 0, 8); 2834 2835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2836 return MCDisassembler::Fail; 2837 2838 if (U) 2839 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2840 else 2841 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2842 2843 return S; 2844 } 2845 2846 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2847 uint64_t Address, 2848 const MCDisassembler *Decoder) { 2849 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2850 } 2851 2852 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2853 uint64_t Address, 2854 const MCDisassembler *Decoder) { 2855 DecodeStatus Status = MCDisassembler::Success; 2856 2857 // Note the J1 and J2 values are from the encoded instruction. So here 2858 // change them to I1 and I2 values via as documented: 2859 // I1 = NOT(J1 EOR S); 2860 // I2 = NOT(J2 EOR S); 2861 // and build the imm32 with one trailing zero as documented: 2862 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2863 unsigned S = fieldFromInstruction(Insn, 26, 1); 2864 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2865 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2866 unsigned I1 = !(J1 ^ S); 2867 unsigned I2 = !(J2 ^ S); 2868 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2869 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2870 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2871 int imm32 = SignExtend32<25>(tmp << 1); 2872 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2873 true, 4, Inst, Decoder)) 2874 Inst.addOperand(MCOperand::createImm(imm32)); 2875 2876 return Status; 2877 } 2878 2879 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2880 uint64_t Address, 2881 const MCDisassembler *Decoder) { 2882 DecodeStatus S = MCDisassembler::Success; 2883 2884 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2885 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2886 2887 if (pred == 0xF) { 2888 Inst.setOpcode(ARM::BLXi); 2889 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2890 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2891 true, 4, Inst, Decoder)) 2892 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2893 return S; 2894 } 2895 2896 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2897 true, 4, Inst, Decoder)) 2898 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2899 2900 // We already have BL_pred for BL w/ predicate, no need to add addition 2901 // predicate opreands for BL 2902 if (Inst.getOpcode() != ARM::BL) 2903 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2904 return MCDisassembler::Fail; 2905 2906 return S; 2907 } 2908 2909 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2910 uint64_t Address, 2911 const MCDisassembler *Decoder) { 2912 DecodeStatus S = MCDisassembler::Success; 2913 2914 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2915 unsigned align = fieldFromInstruction(Val, 4, 2); 2916 2917 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2918 return MCDisassembler::Fail; 2919 if (!align) 2920 Inst.addOperand(MCOperand::createImm(0)); 2921 else 2922 Inst.addOperand(MCOperand::createImm(4 << align)); 2923 2924 return S; 2925 } 2926 2927 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2928 uint64_t Address, 2929 const MCDisassembler *Decoder) { 2930 DecodeStatus S = MCDisassembler::Success; 2931 2932 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2933 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2934 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2935 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2936 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2937 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2938 2939 // First output register 2940 switch (Inst.getOpcode()) { 2941 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2942 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2943 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2944 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2945 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2946 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2947 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2948 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2949 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2950 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2951 return MCDisassembler::Fail; 2952 break; 2953 case ARM::VLD2b16: 2954 case ARM::VLD2b32: 2955 case ARM::VLD2b8: 2956 case ARM::VLD2b16wb_fixed: 2957 case ARM::VLD2b16wb_register: 2958 case ARM::VLD2b32wb_fixed: 2959 case ARM::VLD2b32wb_register: 2960 case ARM::VLD2b8wb_fixed: 2961 case ARM::VLD2b8wb_register: 2962 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2963 return MCDisassembler::Fail; 2964 break; 2965 default: 2966 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2967 return MCDisassembler::Fail; 2968 } 2969 2970 // Second output register 2971 switch (Inst.getOpcode()) { 2972 case ARM::VLD3d8: 2973 case ARM::VLD3d16: 2974 case ARM::VLD3d32: 2975 case ARM::VLD3d8_UPD: 2976 case ARM::VLD3d16_UPD: 2977 case ARM::VLD3d32_UPD: 2978 case ARM::VLD4d8: 2979 case ARM::VLD4d16: 2980 case ARM::VLD4d32: 2981 case ARM::VLD4d8_UPD: 2982 case ARM::VLD4d16_UPD: 2983 case ARM::VLD4d32_UPD: 2984 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2985 return MCDisassembler::Fail; 2986 break; 2987 case ARM::VLD3q8: 2988 case ARM::VLD3q16: 2989 case ARM::VLD3q32: 2990 case ARM::VLD3q8_UPD: 2991 case ARM::VLD3q16_UPD: 2992 case ARM::VLD3q32_UPD: 2993 case ARM::VLD4q8: 2994 case ARM::VLD4q16: 2995 case ARM::VLD4q32: 2996 case ARM::VLD4q8_UPD: 2997 case ARM::VLD4q16_UPD: 2998 case ARM::VLD4q32_UPD: 2999 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3000 return MCDisassembler::Fail; 3001 break; 3002 default: 3003 break; 3004 } 3005 3006 // Third output register 3007 switch(Inst.getOpcode()) { 3008 case ARM::VLD3d8: 3009 case ARM::VLD3d16: 3010 case ARM::VLD3d32: 3011 case ARM::VLD3d8_UPD: 3012 case ARM::VLD3d16_UPD: 3013 case ARM::VLD3d32_UPD: 3014 case ARM::VLD4d8: 3015 case ARM::VLD4d16: 3016 case ARM::VLD4d32: 3017 case ARM::VLD4d8_UPD: 3018 case ARM::VLD4d16_UPD: 3019 case ARM::VLD4d32_UPD: 3020 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3021 return MCDisassembler::Fail; 3022 break; 3023 case ARM::VLD3q8: 3024 case ARM::VLD3q16: 3025 case ARM::VLD3q32: 3026 case ARM::VLD3q8_UPD: 3027 case ARM::VLD3q16_UPD: 3028 case ARM::VLD3q32_UPD: 3029 case ARM::VLD4q8: 3030 case ARM::VLD4q16: 3031 case ARM::VLD4q32: 3032 case ARM::VLD4q8_UPD: 3033 case ARM::VLD4q16_UPD: 3034 case ARM::VLD4q32_UPD: 3035 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3036 return MCDisassembler::Fail; 3037 break; 3038 default: 3039 break; 3040 } 3041 3042 // Fourth output register 3043 switch (Inst.getOpcode()) { 3044 case ARM::VLD4d8: 3045 case ARM::VLD4d16: 3046 case ARM::VLD4d32: 3047 case ARM::VLD4d8_UPD: 3048 case ARM::VLD4d16_UPD: 3049 case ARM::VLD4d32_UPD: 3050 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 break; 3053 case ARM::VLD4q8: 3054 case ARM::VLD4q16: 3055 case ARM::VLD4q32: 3056 case ARM::VLD4q8_UPD: 3057 case ARM::VLD4q16_UPD: 3058 case ARM::VLD4q32_UPD: 3059 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3060 return MCDisassembler::Fail; 3061 break; 3062 default: 3063 break; 3064 } 3065 3066 // Writeback operand 3067 switch (Inst.getOpcode()) { 3068 case ARM::VLD1d8wb_fixed: 3069 case ARM::VLD1d16wb_fixed: 3070 case ARM::VLD1d32wb_fixed: 3071 case ARM::VLD1d64wb_fixed: 3072 case ARM::VLD1d8wb_register: 3073 case ARM::VLD1d16wb_register: 3074 case ARM::VLD1d32wb_register: 3075 case ARM::VLD1d64wb_register: 3076 case ARM::VLD1q8wb_fixed: 3077 case ARM::VLD1q16wb_fixed: 3078 case ARM::VLD1q32wb_fixed: 3079 case ARM::VLD1q64wb_fixed: 3080 case ARM::VLD1q8wb_register: 3081 case ARM::VLD1q16wb_register: 3082 case ARM::VLD1q32wb_register: 3083 case ARM::VLD1q64wb_register: 3084 case ARM::VLD1d8Twb_fixed: 3085 case ARM::VLD1d8Twb_register: 3086 case ARM::VLD1d16Twb_fixed: 3087 case ARM::VLD1d16Twb_register: 3088 case ARM::VLD1d32Twb_fixed: 3089 case ARM::VLD1d32Twb_register: 3090 case ARM::VLD1d64Twb_fixed: 3091 case ARM::VLD1d64Twb_register: 3092 case ARM::VLD1d8Qwb_fixed: 3093 case ARM::VLD1d8Qwb_register: 3094 case ARM::VLD1d16Qwb_fixed: 3095 case ARM::VLD1d16Qwb_register: 3096 case ARM::VLD1d32Qwb_fixed: 3097 case ARM::VLD1d32Qwb_register: 3098 case ARM::VLD1d64Qwb_fixed: 3099 case ARM::VLD1d64Qwb_register: 3100 case ARM::VLD2d8wb_fixed: 3101 case ARM::VLD2d16wb_fixed: 3102 case ARM::VLD2d32wb_fixed: 3103 case ARM::VLD2q8wb_fixed: 3104 case ARM::VLD2q16wb_fixed: 3105 case ARM::VLD2q32wb_fixed: 3106 case ARM::VLD2d8wb_register: 3107 case ARM::VLD2d16wb_register: 3108 case ARM::VLD2d32wb_register: 3109 case ARM::VLD2q8wb_register: 3110 case ARM::VLD2q16wb_register: 3111 case ARM::VLD2q32wb_register: 3112 case ARM::VLD2b8wb_fixed: 3113 case ARM::VLD2b16wb_fixed: 3114 case ARM::VLD2b32wb_fixed: 3115 case ARM::VLD2b8wb_register: 3116 case ARM::VLD2b16wb_register: 3117 case ARM::VLD2b32wb_register: 3118 Inst.addOperand(MCOperand::createImm(0)); 3119 break; 3120 case ARM::VLD3d8_UPD: 3121 case ARM::VLD3d16_UPD: 3122 case ARM::VLD3d32_UPD: 3123 case ARM::VLD3q8_UPD: 3124 case ARM::VLD3q16_UPD: 3125 case ARM::VLD3q32_UPD: 3126 case ARM::VLD4d8_UPD: 3127 case ARM::VLD4d16_UPD: 3128 case ARM::VLD4d32_UPD: 3129 case ARM::VLD4q8_UPD: 3130 case ARM::VLD4q16_UPD: 3131 case ARM::VLD4q32_UPD: 3132 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3133 return MCDisassembler::Fail; 3134 break; 3135 default: 3136 break; 3137 } 3138 3139 // AddrMode6 Base (register+alignment) 3140 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3141 return MCDisassembler::Fail; 3142 3143 // AddrMode6 Offset (register) 3144 switch (Inst.getOpcode()) { 3145 default: 3146 // The below have been updated to have explicit am6offset split 3147 // between fixed and register offset. For those instructions not 3148 // yet updated, we need to add an additional reg0 operand for the 3149 // fixed variant. 3150 // 3151 // The fixed offset encodes as Rm == 0xd, so we check for that. 3152 if (Rm == 0xd) { 3153 Inst.addOperand(MCOperand::createReg(0)); 3154 break; 3155 } 3156 // Fall through to handle the register offset variant. 3157 LLVM_FALLTHROUGH; 3158 case ARM::VLD1d8wb_fixed: 3159 case ARM::VLD1d16wb_fixed: 3160 case ARM::VLD1d32wb_fixed: 3161 case ARM::VLD1d64wb_fixed: 3162 case ARM::VLD1d8Twb_fixed: 3163 case ARM::VLD1d16Twb_fixed: 3164 case ARM::VLD1d32Twb_fixed: 3165 case ARM::VLD1d64Twb_fixed: 3166 case ARM::VLD1d8Qwb_fixed: 3167 case ARM::VLD1d16Qwb_fixed: 3168 case ARM::VLD1d32Qwb_fixed: 3169 case ARM::VLD1d64Qwb_fixed: 3170 case ARM::VLD1d8wb_register: 3171 case ARM::VLD1d16wb_register: 3172 case ARM::VLD1d32wb_register: 3173 case ARM::VLD1d64wb_register: 3174 case ARM::VLD1q8wb_fixed: 3175 case ARM::VLD1q16wb_fixed: 3176 case ARM::VLD1q32wb_fixed: 3177 case ARM::VLD1q64wb_fixed: 3178 case ARM::VLD1q8wb_register: 3179 case ARM::VLD1q16wb_register: 3180 case ARM::VLD1q32wb_register: 3181 case ARM::VLD1q64wb_register: 3182 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3183 // variant encodes Rm == 0xf. Anything else is a register offset post- 3184 // increment and we need to add the register operand to the instruction. 3185 if (Rm != 0xD && Rm != 0xF && 3186 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3187 return MCDisassembler::Fail; 3188 break; 3189 case ARM::VLD2d8wb_fixed: 3190 case ARM::VLD2d16wb_fixed: 3191 case ARM::VLD2d32wb_fixed: 3192 case ARM::VLD2b8wb_fixed: 3193 case ARM::VLD2b16wb_fixed: 3194 case ARM::VLD2b32wb_fixed: 3195 case ARM::VLD2q8wb_fixed: 3196 case ARM::VLD2q16wb_fixed: 3197 case ARM::VLD2q32wb_fixed: 3198 break; 3199 } 3200 3201 return S; 3202 } 3203 3204 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 3205 uint64_t Address, 3206 const MCDisassembler *Decoder) { 3207 unsigned type = fieldFromInstruction(Insn, 8, 4); 3208 unsigned align = fieldFromInstruction(Insn, 4, 2); 3209 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 3210 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 3211 if (type == 10 && align == 3) return MCDisassembler::Fail; 3212 3213 unsigned load = fieldFromInstruction(Insn, 21, 1); 3214 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3215 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3216 } 3217 3218 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 3219 uint64_t Address, 3220 const MCDisassembler *Decoder) { 3221 unsigned size = fieldFromInstruction(Insn, 6, 2); 3222 if (size == 3) return MCDisassembler::Fail; 3223 3224 unsigned type = fieldFromInstruction(Insn, 8, 4); 3225 unsigned align = fieldFromInstruction(Insn, 4, 2); 3226 if (type == 8 && align == 3) return MCDisassembler::Fail; 3227 if (type == 9 && align == 3) return MCDisassembler::Fail; 3228 3229 unsigned load = fieldFromInstruction(Insn, 21, 1); 3230 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3231 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3232 } 3233 3234 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3235 uint64_t Address, 3236 const MCDisassembler *Decoder) { 3237 unsigned size = fieldFromInstruction(Insn, 6, 2); 3238 if (size == 3) return MCDisassembler::Fail; 3239 3240 unsigned align = fieldFromInstruction(Insn, 4, 2); 3241 if (align & 2) return MCDisassembler::Fail; 3242 3243 unsigned load = fieldFromInstruction(Insn, 21, 1); 3244 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3245 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3246 } 3247 3248 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3249 uint64_t Address, 3250 const MCDisassembler *Decoder) { 3251 unsigned size = fieldFromInstruction(Insn, 6, 2); 3252 if (size == 3) return MCDisassembler::Fail; 3253 3254 unsigned load = fieldFromInstruction(Insn, 21, 1); 3255 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3256 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3257 } 3258 3259 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3260 uint64_t Address, 3261 const MCDisassembler *Decoder) { 3262 DecodeStatus S = MCDisassembler::Success; 3263 3264 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3265 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3266 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3267 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3268 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3269 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3270 3271 // Writeback Operand 3272 switch (Inst.getOpcode()) { 3273 case ARM::VST1d8wb_fixed: 3274 case ARM::VST1d16wb_fixed: 3275 case ARM::VST1d32wb_fixed: 3276 case ARM::VST1d64wb_fixed: 3277 case ARM::VST1d8wb_register: 3278 case ARM::VST1d16wb_register: 3279 case ARM::VST1d32wb_register: 3280 case ARM::VST1d64wb_register: 3281 case ARM::VST1q8wb_fixed: 3282 case ARM::VST1q16wb_fixed: 3283 case ARM::VST1q32wb_fixed: 3284 case ARM::VST1q64wb_fixed: 3285 case ARM::VST1q8wb_register: 3286 case ARM::VST1q16wb_register: 3287 case ARM::VST1q32wb_register: 3288 case ARM::VST1q64wb_register: 3289 case ARM::VST1d8Twb_fixed: 3290 case ARM::VST1d16Twb_fixed: 3291 case ARM::VST1d32Twb_fixed: 3292 case ARM::VST1d64Twb_fixed: 3293 case ARM::VST1d8Twb_register: 3294 case ARM::VST1d16Twb_register: 3295 case ARM::VST1d32Twb_register: 3296 case ARM::VST1d64Twb_register: 3297 case ARM::VST1d8Qwb_fixed: 3298 case ARM::VST1d16Qwb_fixed: 3299 case ARM::VST1d32Qwb_fixed: 3300 case ARM::VST1d64Qwb_fixed: 3301 case ARM::VST1d8Qwb_register: 3302 case ARM::VST1d16Qwb_register: 3303 case ARM::VST1d32Qwb_register: 3304 case ARM::VST1d64Qwb_register: 3305 case ARM::VST2d8wb_fixed: 3306 case ARM::VST2d16wb_fixed: 3307 case ARM::VST2d32wb_fixed: 3308 case ARM::VST2d8wb_register: 3309 case ARM::VST2d16wb_register: 3310 case ARM::VST2d32wb_register: 3311 case ARM::VST2q8wb_fixed: 3312 case ARM::VST2q16wb_fixed: 3313 case ARM::VST2q32wb_fixed: 3314 case ARM::VST2q8wb_register: 3315 case ARM::VST2q16wb_register: 3316 case ARM::VST2q32wb_register: 3317 case ARM::VST2b8wb_fixed: 3318 case ARM::VST2b16wb_fixed: 3319 case ARM::VST2b32wb_fixed: 3320 case ARM::VST2b8wb_register: 3321 case ARM::VST2b16wb_register: 3322 case ARM::VST2b32wb_register: 3323 if (Rm == 0xF) 3324 return MCDisassembler::Fail; 3325 Inst.addOperand(MCOperand::createImm(0)); 3326 break; 3327 case ARM::VST3d8_UPD: 3328 case ARM::VST3d16_UPD: 3329 case ARM::VST3d32_UPD: 3330 case ARM::VST3q8_UPD: 3331 case ARM::VST3q16_UPD: 3332 case ARM::VST3q32_UPD: 3333 case ARM::VST4d8_UPD: 3334 case ARM::VST4d16_UPD: 3335 case ARM::VST4d32_UPD: 3336 case ARM::VST4q8_UPD: 3337 case ARM::VST4q16_UPD: 3338 case ARM::VST4q32_UPD: 3339 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3340 return MCDisassembler::Fail; 3341 break; 3342 default: 3343 break; 3344 } 3345 3346 // AddrMode6 Base (register+alignment) 3347 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3348 return MCDisassembler::Fail; 3349 3350 // AddrMode6 Offset (register) 3351 switch (Inst.getOpcode()) { 3352 default: 3353 if (Rm == 0xD) 3354 Inst.addOperand(MCOperand::createReg(0)); 3355 else if (Rm != 0xF) { 3356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3357 return MCDisassembler::Fail; 3358 } 3359 break; 3360 case ARM::VST1d8wb_fixed: 3361 case ARM::VST1d16wb_fixed: 3362 case ARM::VST1d32wb_fixed: 3363 case ARM::VST1d64wb_fixed: 3364 case ARM::VST1q8wb_fixed: 3365 case ARM::VST1q16wb_fixed: 3366 case ARM::VST1q32wb_fixed: 3367 case ARM::VST1q64wb_fixed: 3368 case ARM::VST1d8Twb_fixed: 3369 case ARM::VST1d16Twb_fixed: 3370 case ARM::VST1d32Twb_fixed: 3371 case ARM::VST1d64Twb_fixed: 3372 case ARM::VST1d8Qwb_fixed: 3373 case ARM::VST1d16Qwb_fixed: 3374 case ARM::VST1d32Qwb_fixed: 3375 case ARM::VST1d64Qwb_fixed: 3376 case ARM::VST2d8wb_fixed: 3377 case ARM::VST2d16wb_fixed: 3378 case ARM::VST2d32wb_fixed: 3379 case ARM::VST2q8wb_fixed: 3380 case ARM::VST2q16wb_fixed: 3381 case ARM::VST2q32wb_fixed: 3382 case ARM::VST2b8wb_fixed: 3383 case ARM::VST2b16wb_fixed: 3384 case ARM::VST2b32wb_fixed: 3385 break; 3386 } 3387 3388 // First input register 3389 switch (Inst.getOpcode()) { 3390 case ARM::VST1q16: 3391 case ARM::VST1q32: 3392 case ARM::VST1q64: 3393 case ARM::VST1q8: 3394 case ARM::VST1q16wb_fixed: 3395 case ARM::VST1q16wb_register: 3396 case ARM::VST1q32wb_fixed: 3397 case ARM::VST1q32wb_register: 3398 case ARM::VST1q64wb_fixed: 3399 case ARM::VST1q64wb_register: 3400 case ARM::VST1q8wb_fixed: 3401 case ARM::VST1q8wb_register: 3402 case ARM::VST2d16: 3403 case ARM::VST2d32: 3404 case ARM::VST2d8: 3405 case ARM::VST2d16wb_fixed: 3406 case ARM::VST2d16wb_register: 3407 case ARM::VST2d32wb_fixed: 3408 case ARM::VST2d32wb_register: 3409 case ARM::VST2d8wb_fixed: 3410 case ARM::VST2d8wb_register: 3411 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3412 return MCDisassembler::Fail; 3413 break; 3414 case ARM::VST2b16: 3415 case ARM::VST2b32: 3416 case ARM::VST2b8: 3417 case ARM::VST2b16wb_fixed: 3418 case ARM::VST2b16wb_register: 3419 case ARM::VST2b32wb_fixed: 3420 case ARM::VST2b32wb_register: 3421 case ARM::VST2b8wb_fixed: 3422 case ARM::VST2b8wb_register: 3423 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3424 return MCDisassembler::Fail; 3425 break; 3426 default: 3427 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3428 return MCDisassembler::Fail; 3429 } 3430 3431 // Second input register 3432 switch (Inst.getOpcode()) { 3433 case ARM::VST3d8: 3434 case ARM::VST3d16: 3435 case ARM::VST3d32: 3436 case ARM::VST3d8_UPD: 3437 case ARM::VST3d16_UPD: 3438 case ARM::VST3d32_UPD: 3439 case ARM::VST4d8: 3440 case ARM::VST4d16: 3441 case ARM::VST4d32: 3442 case ARM::VST4d8_UPD: 3443 case ARM::VST4d16_UPD: 3444 case ARM::VST4d32_UPD: 3445 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3446 return MCDisassembler::Fail; 3447 break; 3448 case ARM::VST3q8: 3449 case ARM::VST3q16: 3450 case ARM::VST3q32: 3451 case ARM::VST3q8_UPD: 3452 case ARM::VST3q16_UPD: 3453 case ARM::VST3q32_UPD: 3454 case ARM::VST4q8: 3455 case ARM::VST4q16: 3456 case ARM::VST4q32: 3457 case ARM::VST4q8_UPD: 3458 case ARM::VST4q16_UPD: 3459 case ARM::VST4q32_UPD: 3460 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 break; 3463 default: 3464 break; 3465 } 3466 3467 // Third input register 3468 switch (Inst.getOpcode()) { 3469 case ARM::VST3d8: 3470 case ARM::VST3d16: 3471 case ARM::VST3d32: 3472 case ARM::VST3d8_UPD: 3473 case ARM::VST3d16_UPD: 3474 case ARM::VST3d32_UPD: 3475 case ARM::VST4d8: 3476 case ARM::VST4d16: 3477 case ARM::VST4d32: 3478 case ARM::VST4d8_UPD: 3479 case ARM::VST4d16_UPD: 3480 case ARM::VST4d32_UPD: 3481 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3482 return MCDisassembler::Fail; 3483 break; 3484 case ARM::VST3q8: 3485 case ARM::VST3q16: 3486 case ARM::VST3q32: 3487 case ARM::VST3q8_UPD: 3488 case ARM::VST3q16_UPD: 3489 case ARM::VST3q32_UPD: 3490 case ARM::VST4q8: 3491 case ARM::VST4q16: 3492 case ARM::VST4q32: 3493 case ARM::VST4q8_UPD: 3494 case ARM::VST4q16_UPD: 3495 case ARM::VST4q32_UPD: 3496 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3497 return MCDisassembler::Fail; 3498 break; 3499 default: 3500 break; 3501 } 3502 3503 // Fourth input register 3504 switch (Inst.getOpcode()) { 3505 case ARM::VST4d8: 3506 case ARM::VST4d16: 3507 case ARM::VST4d32: 3508 case ARM::VST4d8_UPD: 3509 case ARM::VST4d16_UPD: 3510 case ARM::VST4d32_UPD: 3511 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3512 return MCDisassembler::Fail; 3513 break; 3514 case ARM::VST4q8: 3515 case ARM::VST4q16: 3516 case ARM::VST4q32: 3517 case ARM::VST4q8_UPD: 3518 case ARM::VST4q16_UPD: 3519 case ARM::VST4q32_UPD: 3520 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3521 return MCDisassembler::Fail; 3522 break; 3523 default: 3524 break; 3525 } 3526 3527 return S; 3528 } 3529 3530 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3531 uint64_t Address, 3532 const MCDisassembler *Decoder) { 3533 DecodeStatus S = MCDisassembler::Success; 3534 3535 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3536 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3537 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3538 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3539 unsigned align = fieldFromInstruction(Insn, 4, 1); 3540 unsigned size = fieldFromInstruction(Insn, 6, 2); 3541 3542 if (size == 0 && align == 1) 3543 return MCDisassembler::Fail; 3544 align *= (1 << size); 3545 3546 switch (Inst.getOpcode()) { 3547 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3548 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3549 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3550 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3551 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3552 return MCDisassembler::Fail; 3553 break; 3554 default: 3555 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3556 return MCDisassembler::Fail; 3557 break; 3558 } 3559 if (Rm != 0xF) { 3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 } 3563 3564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3565 return MCDisassembler::Fail; 3566 Inst.addOperand(MCOperand::createImm(align)); 3567 3568 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3569 // variant encodes Rm == 0xf. Anything else is a register offset post- 3570 // increment and we need to add the register operand to the instruction. 3571 if (Rm != 0xD && Rm != 0xF && 3572 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 3575 return S; 3576 } 3577 3578 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3579 uint64_t Address, 3580 const MCDisassembler *Decoder) { 3581 DecodeStatus S = MCDisassembler::Success; 3582 3583 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3584 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3585 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3586 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3587 unsigned align = fieldFromInstruction(Insn, 4, 1); 3588 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3589 align *= 2*size; 3590 3591 switch (Inst.getOpcode()) { 3592 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3593 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3594 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3595 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3596 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3597 return MCDisassembler::Fail; 3598 break; 3599 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3600 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3601 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3602 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3603 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3604 return MCDisassembler::Fail; 3605 break; 3606 default: 3607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3608 return MCDisassembler::Fail; 3609 break; 3610 } 3611 3612 if (Rm != 0xF) 3613 Inst.addOperand(MCOperand::createImm(0)); 3614 3615 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3616 return MCDisassembler::Fail; 3617 Inst.addOperand(MCOperand::createImm(align)); 3618 3619 if (Rm != 0xD && Rm != 0xF) { 3620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3621 return MCDisassembler::Fail; 3622 } 3623 3624 return S; 3625 } 3626 3627 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3628 uint64_t Address, 3629 const MCDisassembler *Decoder) { 3630 DecodeStatus S = MCDisassembler::Success; 3631 3632 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3633 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3634 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3635 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3636 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3637 3638 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3639 return MCDisassembler::Fail; 3640 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3641 return MCDisassembler::Fail; 3642 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 if (Rm != 0xF) { 3645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3646 return MCDisassembler::Fail; 3647 } 3648 3649 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3650 return MCDisassembler::Fail; 3651 Inst.addOperand(MCOperand::createImm(0)); 3652 3653 if (Rm == 0xD) 3654 Inst.addOperand(MCOperand::createReg(0)); 3655 else if (Rm != 0xF) { 3656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3657 return MCDisassembler::Fail; 3658 } 3659 3660 return S; 3661 } 3662 3663 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3664 uint64_t Address, 3665 const MCDisassembler *Decoder) { 3666 DecodeStatus S = MCDisassembler::Success; 3667 3668 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3669 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3670 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3671 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3672 unsigned size = fieldFromInstruction(Insn, 6, 2); 3673 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3674 unsigned align = fieldFromInstruction(Insn, 4, 1); 3675 3676 if (size == 0x3) { 3677 if (align == 0) 3678 return MCDisassembler::Fail; 3679 align = 16; 3680 } else { 3681 if (size == 2) { 3682 align *= 8; 3683 } else { 3684 size = 1 << size; 3685 align *= 4*size; 3686 } 3687 } 3688 3689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3692 return MCDisassembler::Fail; 3693 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3694 return MCDisassembler::Fail; 3695 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3696 return MCDisassembler::Fail; 3697 if (Rm != 0xF) { 3698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3699 return MCDisassembler::Fail; 3700 } 3701 3702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3703 return MCDisassembler::Fail; 3704 Inst.addOperand(MCOperand::createImm(align)); 3705 3706 if (Rm == 0xD) 3707 Inst.addOperand(MCOperand::createReg(0)); 3708 else if (Rm != 0xF) { 3709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3710 return MCDisassembler::Fail; 3711 } 3712 3713 return S; 3714 } 3715 3716 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3717 uint64_t Address, 3718 const MCDisassembler *Decoder) { 3719 DecodeStatus S = MCDisassembler::Success; 3720 3721 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3722 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3723 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3724 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3725 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3726 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3727 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3728 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3729 3730 if (Q) { 3731 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3732 return MCDisassembler::Fail; 3733 } else { 3734 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3735 return MCDisassembler::Fail; 3736 } 3737 3738 Inst.addOperand(MCOperand::createImm(imm)); 3739 3740 switch (Inst.getOpcode()) { 3741 case ARM::VORRiv4i16: 3742 case ARM::VORRiv2i32: 3743 case ARM::VBICiv4i16: 3744 case ARM::VBICiv2i32: 3745 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3746 return MCDisassembler::Fail; 3747 break; 3748 case ARM::VORRiv8i16: 3749 case ARM::VORRiv4i32: 3750 case ARM::VBICiv8i16: 3751 case ARM::VBICiv4i32: 3752 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3753 return MCDisassembler::Fail; 3754 break; 3755 default: 3756 break; 3757 } 3758 3759 return S; 3760 } 3761 3762 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3763 uint64_t Address, 3764 const MCDisassembler *Decoder) { 3765 DecodeStatus S = MCDisassembler::Success; 3766 3767 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3768 fieldFromInstruction(Insn, 13, 3)); 3769 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3770 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3771 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3772 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3773 imm |= cmode << 8; 3774 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3775 3776 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3777 return MCDisassembler::Fail; 3778 3779 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3780 return MCDisassembler::Fail; 3781 3782 Inst.addOperand(MCOperand::createImm(imm)); 3783 3784 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3785 Inst.addOperand(MCOperand::createReg(0)); 3786 Inst.addOperand(MCOperand::createImm(0)); 3787 3788 return S; 3789 } 3790 3791 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3792 uint64_t Address, 3793 const MCDisassembler *Decoder) { 3794 DecodeStatus S = MCDisassembler::Success; 3795 3796 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3797 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3798 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3799 return MCDisassembler::Fail; 3800 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3801 3802 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3803 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3804 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3805 return MCDisassembler::Fail; 3806 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3807 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3808 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3809 return MCDisassembler::Fail; 3810 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3811 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3812 Inst.addOperand(MCOperand::createImm(Qd)); 3813 3814 return S; 3815 } 3816 3817 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3818 uint64_t Address, 3819 const MCDisassembler *Decoder) { 3820 DecodeStatus S = MCDisassembler::Success; 3821 3822 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3823 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3824 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3825 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3826 unsigned size = fieldFromInstruction(Insn, 18, 2); 3827 3828 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3829 return MCDisassembler::Fail; 3830 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3831 return MCDisassembler::Fail; 3832 Inst.addOperand(MCOperand::createImm(8 << size)); 3833 3834 return S; 3835 } 3836 3837 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3838 uint64_t Address, 3839 const MCDisassembler *Decoder) { 3840 Inst.addOperand(MCOperand::createImm(8 - Val)); 3841 return MCDisassembler::Success; 3842 } 3843 3844 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3845 uint64_t Address, 3846 const MCDisassembler *Decoder) { 3847 Inst.addOperand(MCOperand::createImm(16 - Val)); 3848 return MCDisassembler::Success; 3849 } 3850 3851 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3852 uint64_t Address, 3853 const MCDisassembler *Decoder) { 3854 Inst.addOperand(MCOperand::createImm(32 - Val)); 3855 return MCDisassembler::Success; 3856 } 3857 3858 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3859 uint64_t Address, 3860 const MCDisassembler *Decoder) { 3861 Inst.addOperand(MCOperand::createImm(64 - Val)); 3862 return MCDisassembler::Success; 3863 } 3864 3865 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3866 uint64_t Address, 3867 const MCDisassembler *Decoder) { 3868 DecodeStatus S = MCDisassembler::Success; 3869 3870 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3871 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3872 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3873 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3874 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3875 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3876 unsigned op = fieldFromInstruction(Insn, 6, 1); 3877 3878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3879 return MCDisassembler::Fail; 3880 if (op) { 3881 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3882 return MCDisassembler::Fail; // Writeback 3883 } 3884 3885 switch (Inst.getOpcode()) { 3886 case ARM::VTBL2: 3887 case ARM::VTBX2: 3888 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3889 return MCDisassembler::Fail; 3890 break; 3891 default: 3892 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3893 return MCDisassembler::Fail; 3894 } 3895 3896 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3897 return MCDisassembler::Fail; 3898 3899 return S; 3900 } 3901 3902 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3903 uint64_t Address, 3904 const MCDisassembler *Decoder) { 3905 DecodeStatus S = MCDisassembler::Success; 3906 3907 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3908 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3909 3910 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3911 return MCDisassembler::Fail; 3912 3913 switch(Inst.getOpcode()) { 3914 default: 3915 return MCDisassembler::Fail; 3916 case ARM::tADR: 3917 break; // tADR does not explicitly represent the PC as an operand. 3918 case ARM::tADDrSPi: 3919 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3920 break; 3921 } 3922 3923 Inst.addOperand(MCOperand::createImm(imm)); 3924 return S; 3925 } 3926 3927 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3928 uint64_t Address, 3929 const MCDisassembler *Decoder) { 3930 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3931 true, 2, Inst, Decoder)) 3932 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3933 return MCDisassembler::Success; 3934 } 3935 3936 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3937 uint64_t Address, 3938 const MCDisassembler *Decoder) { 3939 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3940 true, 4, Inst, Decoder)) 3941 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3942 return MCDisassembler::Success; 3943 } 3944 3945 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3946 uint64_t Address, 3947 const MCDisassembler *Decoder) { 3948 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3949 true, 2, Inst, Decoder)) 3950 Inst.addOperand(MCOperand::createImm(Val << 1)); 3951 return MCDisassembler::Success; 3952 } 3953 3954 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3955 uint64_t Address, 3956 const MCDisassembler *Decoder) { 3957 DecodeStatus S = MCDisassembler::Success; 3958 3959 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3960 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3961 3962 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3963 return MCDisassembler::Fail; 3964 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3965 return MCDisassembler::Fail; 3966 3967 return S; 3968 } 3969 3970 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3971 uint64_t Address, 3972 const MCDisassembler *Decoder) { 3973 DecodeStatus S = MCDisassembler::Success; 3974 3975 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3976 unsigned imm = fieldFromInstruction(Val, 3, 5); 3977 3978 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3979 return MCDisassembler::Fail; 3980 Inst.addOperand(MCOperand::createImm(imm)); 3981 3982 return S; 3983 } 3984 3985 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3986 uint64_t Address, 3987 const MCDisassembler *Decoder) { 3988 unsigned imm = Val << 2; 3989 3990 Inst.addOperand(MCOperand::createImm(imm)); 3991 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3992 3993 return MCDisassembler::Success; 3994 } 3995 3996 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3997 uint64_t Address, 3998 const MCDisassembler *Decoder) { 3999 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4000 Inst.addOperand(MCOperand::createImm(Val)); 4001 4002 return MCDisassembler::Success; 4003 } 4004 4005 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 4006 uint64_t Address, 4007 const MCDisassembler *Decoder) { 4008 DecodeStatus S = MCDisassembler::Success; 4009 4010 unsigned Rn = fieldFromInstruction(Val, 6, 4); 4011 unsigned Rm = fieldFromInstruction(Val, 2, 4); 4012 unsigned imm = fieldFromInstruction(Val, 0, 2); 4013 4014 // Thumb stores cannot use PC as dest register. 4015 switch (Inst.getOpcode()) { 4016 case ARM::t2STRHs: 4017 case ARM::t2STRBs: 4018 case ARM::t2STRs: 4019 if (Rn == 15) 4020 return MCDisassembler::Fail; 4021 break; 4022 default: 4023 break; 4024 } 4025 4026 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4029 return MCDisassembler::Fail; 4030 Inst.addOperand(MCOperand::createImm(imm)); 4031 4032 return S; 4033 } 4034 4035 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 4036 uint64_t Address, 4037 const MCDisassembler *Decoder) { 4038 DecodeStatus S = MCDisassembler::Success; 4039 4040 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4041 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4042 4043 const FeatureBitset &featureBits = 4044 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4045 4046 bool hasMP = featureBits[ARM::FeatureMP]; 4047 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4048 4049 if (Rn == 15) { 4050 switch (Inst.getOpcode()) { 4051 case ARM::t2LDRBs: 4052 Inst.setOpcode(ARM::t2LDRBpci); 4053 break; 4054 case ARM::t2LDRHs: 4055 Inst.setOpcode(ARM::t2LDRHpci); 4056 break; 4057 case ARM::t2LDRSHs: 4058 Inst.setOpcode(ARM::t2LDRSHpci); 4059 break; 4060 case ARM::t2LDRSBs: 4061 Inst.setOpcode(ARM::t2LDRSBpci); 4062 break; 4063 case ARM::t2LDRs: 4064 Inst.setOpcode(ARM::t2LDRpci); 4065 break; 4066 case ARM::t2PLDs: 4067 Inst.setOpcode(ARM::t2PLDpci); 4068 break; 4069 case ARM::t2PLIs: 4070 Inst.setOpcode(ARM::t2PLIpci); 4071 break; 4072 default: 4073 return MCDisassembler::Fail; 4074 } 4075 4076 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4077 } 4078 4079 if (Rt == 15) { 4080 switch (Inst.getOpcode()) { 4081 case ARM::t2LDRSHs: 4082 return MCDisassembler::Fail; 4083 case ARM::t2LDRHs: 4084 Inst.setOpcode(ARM::t2PLDWs); 4085 break; 4086 case ARM::t2LDRSBs: 4087 Inst.setOpcode(ARM::t2PLIs); 4088 break; 4089 default: 4090 break; 4091 } 4092 } 4093 4094 switch (Inst.getOpcode()) { 4095 case ARM::t2PLDs: 4096 break; 4097 case ARM::t2PLIs: 4098 if (!hasV7Ops) 4099 return MCDisassembler::Fail; 4100 break; 4101 case ARM::t2PLDWs: 4102 if (!hasV7Ops || !hasMP) 4103 return MCDisassembler::Fail; 4104 break; 4105 default: 4106 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4107 return MCDisassembler::Fail; 4108 } 4109 4110 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 4111 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 4112 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 4113 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 4114 return MCDisassembler::Fail; 4115 4116 return S; 4117 } 4118 4119 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 4120 uint64_t Address, 4121 const MCDisassembler *Decoder) { 4122 DecodeStatus S = MCDisassembler::Success; 4123 4124 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4125 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4126 unsigned U = fieldFromInstruction(Insn, 9, 1); 4127 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4128 imm |= (U << 8); 4129 imm |= (Rn << 9); 4130 unsigned add = fieldFromInstruction(Insn, 9, 1); 4131 4132 const FeatureBitset &featureBits = 4133 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4134 4135 bool hasMP = featureBits[ARM::FeatureMP]; 4136 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4137 4138 if (Rn == 15) { 4139 switch (Inst.getOpcode()) { 4140 case ARM::t2LDRi8: 4141 Inst.setOpcode(ARM::t2LDRpci); 4142 break; 4143 case ARM::t2LDRBi8: 4144 Inst.setOpcode(ARM::t2LDRBpci); 4145 break; 4146 case ARM::t2LDRSBi8: 4147 Inst.setOpcode(ARM::t2LDRSBpci); 4148 break; 4149 case ARM::t2LDRHi8: 4150 Inst.setOpcode(ARM::t2LDRHpci); 4151 break; 4152 case ARM::t2LDRSHi8: 4153 Inst.setOpcode(ARM::t2LDRSHpci); 4154 break; 4155 case ARM::t2PLDi8: 4156 Inst.setOpcode(ARM::t2PLDpci); 4157 break; 4158 case ARM::t2PLIi8: 4159 Inst.setOpcode(ARM::t2PLIpci); 4160 break; 4161 default: 4162 return MCDisassembler::Fail; 4163 } 4164 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4165 } 4166 4167 if (Rt == 15) { 4168 switch (Inst.getOpcode()) { 4169 case ARM::t2LDRSHi8: 4170 return MCDisassembler::Fail; 4171 case ARM::t2LDRHi8: 4172 if (!add) 4173 Inst.setOpcode(ARM::t2PLDWi8); 4174 break; 4175 case ARM::t2LDRSBi8: 4176 Inst.setOpcode(ARM::t2PLIi8); 4177 break; 4178 default: 4179 break; 4180 } 4181 } 4182 4183 switch (Inst.getOpcode()) { 4184 case ARM::t2PLDi8: 4185 break; 4186 case ARM::t2PLIi8: 4187 if (!hasV7Ops) 4188 return MCDisassembler::Fail; 4189 break; 4190 case ARM::t2PLDWi8: 4191 if (!hasV7Ops || !hasMP) 4192 return MCDisassembler::Fail; 4193 break; 4194 default: 4195 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4196 return MCDisassembler::Fail; 4197 } 4198 4199 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4200 return MCDisassembler::Fail; 4201 return S; 4202 } 4203 4204 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 4205 uint64_t Address, 4206 const MCDisassembler *Decoder) { 4207 DecodeStatus S = MCDisassembler::Success; 4208 4209 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4210 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4211 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4212 imm |= (Rn << 13); 4213 4214 const FeatureBitset &featureBits = 4215 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4216 4217 bool hasMP = featureBits[ARM::FeatureMP]; 4218 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4219 4220 if (Rn == 15) { 4221 switch (Inst.getOpcode()) { 4222 case ARM::t2LDRi12: 4223 Inst.setOpcode(ARM::t2LDRpci); 4224 break; 4225 case ARM::t2LDRHi12: 4226 Inst.setOpcode(ARM::t2LDRHpci); 4227 break; 4228 case ARM::t2LDRSHi12: 4229 Inst.setOpcode(ARM::t2LDRSHpci); 4230 break; 4231 case ARM::t2LDRBi12: 4232 Inst.setOpcode(ARM::t2LDRBpci); 4233 break; 4234 case ARM::t2LDRSBi12: 4235 Inst.setOpcode(ARM::t2LDRSBpci); 4236 break; 4237 case ARM::t2PLDi12: 4238 Inst.setOpcode(ARM::t2PLDpci); 4239 break; 4240 case ARM::t2PLIi12: 4241 Inst.setOpcode(ARM::t2PLIpci); 4242 break; 4243 default: 4244 return MCDisassembler::Fail; 4245 } 4246 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4247 } 4248 4249 if (Rt == 15) { 4250 switch (Inst.getOpcode()) { 4251 case ARM::t2LDRSHi12: 4252 return MCDisassembler::Fail; 4253 case ARM::t2LDRHi12: 4254 Inst.setOpcode(ARM::t2PLDWi12); 4255 break; 4256 case ARM::t2LDRSBi12: 4257 Inst.setOpcode(ARM::t2PLIi12); 4258 break; 4259 default: 4260 break; 4261 } 4262 } 4263 4264 switch (Inst.getOpcode()) { 4265 case ARM::t2PLDi12: 4266 break; 4267 case ARM::t2PLIi12: 4268 if (!hasV7Ops) 4269 return MCDisassembler::Fail; 4270 break; 4271 case ARM::t2PLDWi12: 4272 if (!hasV7Ops || !hasMP) 4273 return MCDisassembler::Fail; 4274 break; 4275 default: 4276 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4277 return MCDisassembler::Fail; 4278 } 4279 4280 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4281 return MCDisassembler::Fail; 4282 return S; 4283 } 4284 4285 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 4286 const MCDisassembler *Decoder) { 4287 DecodeStatus S = MCDisassembler::Success; 4288 4289 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4290 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4291 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4292 imm |= (Rn << 9); 4293 4294 if (Rn == 15) { 4295 switch (Inst.getOpcode()) { 4296 case ARM::t2LDRT: 4297 Inst.setOpcode(ARM::t2LDRpci); 4298 break; 4299 case ARM::t2LDRBT: 4300 Inst.setOpcode(ARM::t2LDRBpci); 4301 break; 4302 case ARM::t2LDRHT: 4303 Inst.setOpcode(ARM::t2LDRHpci); 4304 break; 4305 case ARM::t2LDRSBT: 4306 Inst.setOpcode(ARM::t2LDRSBpci); 4307 break; 4308 case ARM::t2LDRSHT: 4309 Inst.setOpcode(ARM::t2LDRSHpci); 4310 break; 4311 default: 4312 return MCDisassembler::Fail; 4313 } 4314 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4315 } 4316 4317 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4318 return MCDisassembler::Fail; 4319 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4320 return MCDisassembler::Fail; 4321 return S; 4322 } 4323 4324 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4325 uint64_t Address, 4326 const MCDisassembler *Decoder) { 4327 DecodeStatus S = MCDisassembler::Success; 4328 4329 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4330 unsigned U = fieldFromInstruction(Insn, 23, 1); 4331 int imm = fieldFromInstruction(Insn, 0, 12); 4332 4333 const FeatureBitset &featureBits = 4334 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4335 4336 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4337 4338 if (Rt == 15) { 4339 switch (Inst.getOpcode()) { 4340 case ARM::t2LDRBpci: 4341 case ARM::t2LDRHpci: 4342 Inst.setOpcode(ARM::t2PLDpci); 4343 break; 4344 case ARM::t2LDRSBpci: 4345 Inst.setOpcode(ARM::t2PLIpci); 4346 break; 4347 case ARM::t2LDRSHpci: 4348 return MCDisassembler::Fail; 4349 default: 4350 break; 4351 } 4352 } 4353 4354 switch(Inst.getOpcode()) { 4355 case ARM::t2PLDpci: 4356 break; 4357 case ARM::t2PLIpci: 4358 if (!hasV7Ops) 4359 return MCDisassembler::Fail; 4360 break; 4361 default: 4362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 } 4365 4366 if (!U) { 4367 // Special case for #-0. 4368 if (imm == 0) 4369 imm = INT32_MIN; 4370 else 4371 imm = -imm; 4372 } 4373 Inst.addOperand(MCOperand::createImm(imm)); 4374 4375 return S; 4376 } 4377 4378 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 4379 const MCDisassembler *Decoder) { 4380 if (Val == 0) 4381 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4382 else { 4383 int imm = Val & 0xFF; 4384 4385 if (!(Val & 0x100)) imm *= -1; 4386 Inst.addOperand(MCOperand::createImm(imm * 4)); 4387 } 4388 4389 return MCDisassembler::Success; 4390 } 4391 4392 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4393 const MCDisassembler *Decoder) { 4394 if (Val == 0) 4395 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4396 else { 4397 int imm = Val & 0x7F; 4398 4399 if (!(Val & 0x80)) 4400 imm *= -1; 4401 Inst.addOperand(MCOperand::createImm(imm * 4)); 4402 } 4403 4404 return MCDisassembler::Success; 4405 } 4406 4407 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4408 uint64_t Address, 4409 const MCDisassembler *Decoder) { 4410 DecodeStatus S = MCDisassembler::Success; 4411 4412 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4413 unsigned imm = fieldFromInstruction(Val, 0, 9); 4414 4415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4416 return MCDisassembler::Fail; 4417 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4418 return MCDisassembler::Fail; 4419 4420 return S; 4421 } 4422 4423 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4424 uint64_t Address, 4425 const MCDisassembler *Decoder) { 4426 DecodeStatus S = MCDisassembler::Success; 4427 4428 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4429 unsigned imm = fieldFromInstruction(Val, 0, 8); 4430 4431 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4432 return MCDisassembler::Fail; 4433 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4434 return MCDisassembler::Fail; 4435 4436 return S; 4437 } 4438 4439 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 4440 uint64_t Address, 4441 const MCDisassembler *Decoder) { 4442 DecodeStatus S = MCDisassembler::Success; 4443 4444 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4445 unsigned imm = fieldFromInstruction(Val, 0, 8); 4446 4447 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4448 return MCDisassembler::Fail; 4449 4450 Inst.addOperand(MCOperand::createImm(imm)); 4451 4452 return S; 4453 } 4454 4455 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 4456 const MCDisassembler *Decoder) { 4457 int imm = Val & 0xFF; 4458 if (Val == 0) 4459 imm = INT32_MIN; 4460 else if (!(Val & 0x100)) 4461 imm *= -1; 4462 Inst.addOperand(MCOperand::createImm(imm)); 4463 4464 return MCDisassembler::Success; 4465 } 4466 4467 template <int shift> 4468 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 4469 const MCDisassembler *Decoder) { 4470 int imm = Val & 0x7F; 4471 if (Val == 0) 4472 imm = INT32_MIN; 4473 else if (!(Val & 0x80)) 4474 imm *= -1; 4475 if (imm != INT32_MIN) 4476 imm *= (1U << shift); 4477 Inst.addOperand(MCOperand::createImm(imm)); 4478 4479 return MCDisassembler::Success; 4480 } 4481 4482 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4483 uint64_t Address, 4484 const MCDisassembler *Decoder) { 4485 DecodeStatus S = MCDisassembler::Success; 4486 4487 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4488 unsigned imm = fieldFromInstruction(Val, 0, 9); 4489 4490 // Thumb stores cannot use PC as dest register. 4491 switch (Inst.getOpcode()) { 4492 case ARM::t2STRT: 4493 case ARM::t2STRBT: 4494 case ARM::t2STRHT: 4495 case ARM::t2STRi8: 4496 case ARM::t2STRHi8: 4497 case ARM::t2STRBi8: 4498 if (Rn == 15) 4499 return MCDisassembler::Fail; 4500 break; 4501 default: 4502 break; 4503 } 4504 4505 // Some instructions always use an additive offset. 4506 switch (Inst.getOpcode()) { 4507 case ARM::t2LDRT: 4508 case ARM::t2LDRBT: 4509 case ARM::t2LDRHT: 4510 case ARM::t2LDRSBT: 4511 case ARM::t2LDRSHT: 4512 case ARM::t2STRT: 4513 case ARM::t2STRBT: 4514 case ARM::t2STRHT: 4515 imm |= 0x100; 4516 break; 4517 default: 4518 break; 4519 } 4520 4521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4522 return MCDisassembler::Fail; 4523 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4524 return MCDisassembler::Fail; 4525 4526 return S; 4527 } 4528 4529 template <int shift> 4530 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4531 uint64_t Address, 4532 const MCDisassembler *Decoder) { 4533 DecodeStatus S = MCDisassembler::Success; 4534 4535 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4536 unsigned imm = fieldFromInstruction(Val, 0, 8); 4537 4538 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4539 return MCDisassembler::Fail; 4540 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4541 return MCDisassembler::Fail; 4542 4543 return S; 4544 } 4545 4546 template <int shift, int WriteBack> 4547 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4548 uint64_t Address, 4549 const MCDisassembler *Decoder) { 4550 DecodeStatus S = MCDisassembler::Success; 4551 4552 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4553 unsigned imm = fieldFromInstruction(Val, 0, 8); 4554 if (WriteBack) { 4555 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4556 return MCDisassembler::Fail; 4557 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4558 return MCDisassembler::Fail; 4559 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4560 return MCDisassembler::Fail; 4561 4562 return S; 4563 } 4564 4565 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4566 uint64_t Address, 4567 const MCDisassembler *Decoder) { 4568 DecodeStatus S = MCDisassembler::Success; 4569 4570 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4571 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4572 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4573 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4574 addr |= Rn << 9; 4575 unsigned load = fieldFromInstruction(Insn, 20, 1); 4576 4577 if (Rn == 15) { 4578 switch (Inst.getOpcode()) { 4579 case ARM::t2LDR_PRE: 4580 case ARM::t2LDR_POST: 4581 Inst.setOpcode(ARM::t2LDRpci); 4582 break; 4583 case ARM::t2LDRB_PRE: 4584 case ARM::t2LDRB_POST: 4585 Inst.setOpcode(ARM::t2LDRBpci); 4586 break; 4587 case ARM::t2LDRH_PRE: 4588 case ARM::t2LDRH_POST: 4589 Inst.setOpcode(ARM::t2LDRHpci); 4590 break; 4591 case ARM::t2LDRSB_PRE: 4592 case ARM::t2LDRSB_POST: 4593 if (Rt == 15) 4594 Inst.setOpcode(ARM::t2PLIpci); 4595 else 4596 Inst.setOpcode(ARM::t2LDRSBpci); 4597 break; 4598 case ARM::t2LDRSH_PRE: 4599 case ARM::t2LDRSH_POST: 4600 Inst.setOpcode(ARM::t2LDRSHpci); 4601 break; 4602 default: 4603 return MCDisassembler::Fail; 4604 } 4605 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4606 } 4607 4608 if (!load) { 4609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4610 return MCDisassembler::Fail; 4611 } 4612 4613 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4614 return MCDisassembler::Fail; 4615 4616 if (load) { 4617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4618 return MCDisassembler::Fail; 4619 } 4620 4621 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4622 return MCDisassembler::Fail; 4623 4624 return S; 4625 } 4626 4627 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4628 uint64_t Address, 4629 const MCDisassembler *Decoder) { 4630 DecodeStatus S = MCDisassembler::Success; 4631 4632 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4633 unsigned imm = fieldFromInstruction(Val, 0, 12); 4634 4635 // Thumb stores cannot use PC as dest register. 4636 switch (Inst.getOpcode()) { 4637 case ARM::t2STRi12: 4638 case ARM::t2STRBi12: 4639 case ARM::t2STRHi12: 4640 if (Rn == 15) 4641 return MCDisassembler::Fail; 4642 break; 4643 default: 4644 break; 4645 } 4646 4647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4648 return MCDisassembler::Fail; 4649 Inst.addOperand(MCOperand::createImm(imm)); 4650 4651 return S; 4652 } 4653 4654 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4655 uint64_t Address, 4656 const MCDisassembler *Decoder) { 4657 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4658 4659 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4660 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4661 Inst.addOperand(MCOperand::createImm(imm)); 4662 4663 return MCDisassembler::Success; 4664 } 4665 4666 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4667 uint64_t Address, 4668 const MCDisassembler *Decoder) { 4669 DecodeStatus S = MCDisassembler::Success; 4670 4671 if (Inst.getOpcode() == ARM::tADDrSP) { 4672 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4673 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4674 4675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4676 return MCDisassembler::Fail; 4677 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 } else if (Inst.getOpcode() == ARM::tADDspr) { 4681 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4682 4683 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4684 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4686 return MCDisassembler::Fail; 4687 } 4688 4689 return S; 4690 } 4691 4692 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4693 uint64_t Address, 4694 const MCDisassembler *Decoder) { 4695 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4696 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4697 4698 Inst.addOperand(MCOperand::createImm(imod)); 4699 Inst.addOperand(MCOperand::createImm(flags)); 4700 4701 return MCDisassembler::Success; 4702 } 4703 4704 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4705 uint64_t Address, 4706 const MCDisassembler *Decoder) { 4707 DecodeStatus S = MCDisassembler::Success; 4708 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4709 unsigned add = fieldFromInstruction(Insn, 4, 1); 4710 4711 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4712 return MCDisassembler::Fail; 4713 Inst.addOperand(MCOperand::createImm(add)); 4714 4715 return S; 4716 } 4717 4718 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4719 uint64_t Address, 4720 const MCDisassembler *Decoder) { 4721 DecodeStatus S = MCDisassembler::Success; 4722 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4723 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4724 4725 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4726 return MCDisassembler::Fail; 4727 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4728 return MCDisassembler::Fail; 4729 4730 return S; 4731 } 4732 4733 template <int shift> 4734 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4735 uint64_t Address, 4736 const MCDisassembler *Decoder) { 4737 DecodeStatus S = MCDisassembler::Success; 4738 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4739 int imm = fieldFromInstruction(Insn, 0, 7); 4740 4741 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4742 return MCDisassembler::Fail; 4743 4744 if(!fieldFromInstruction(Insn, 7, 1)) { 4745 if (imm == 0) 4746 imm = INT32_MIN; // indicate -0 4747 else 4748 imm *= -1; 4749 } 4750 if (imm != INT32_MIN) 4751 imm *= (1U << shift); 4752 Inst.addOperand(MCOperand::createImm(imm)); 4753 4754 return S; 4755 } 4756 4757 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4758 uint64_t Address, 4759 const MCDisassembler *Decoder) { 4760 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4761 // Note only one trailing zero not two. Also the J1 and J2 values are from 4762 // the encoded instruction. So here change to I1 and I2 values via: 4763 // I1 = NOT(J1 EOR S); 4764 // I2 = NOT(J2 EOR S); 4765 // and build the imm32 with two trailing zeros as documented: 4766 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4767 unsigned S = (Val >> 23) & 1; 4768 unsigned J1 = (Val >> 22) & 1; 4769 unsigned J2 = (Val >> 21) & 1; 4770 unsigned I1 = !(J1 ^ S); 4771 unsigned I2 = !(J2 ^ S); 4772 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4773 int imm32 = SignExtend32<25>(tmp << 1); 4774 4775 if (!tryAddingSymbolicOperand(Address, 4776 (Address & ~2u) + imm32 + 4, 4777 true, 4, Inst, Decoder)) 4778 Inst.addOperand(MCOperand::createImm(imm32)); 4779 return MCDisassembler::Success; 4780 } 4781 4782 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4783 uint64_t Address, 4784 const MCDisassembler *Decoder) { 4785 if (Val == 0xA || Val == 0xB) 4786 return MCDisassembler::Fail; 4787 4788 const FeatureBitset &featureBits = 4789 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4790 4791 if (!isValidCoprocessorNumber(Val, featureBits)) 4792 return MCDisassembler::Fail; 4793 4794 Inst.addOperand(MCOperand::createImm(Val)); 4795 return MCDisassembler::Success; 4796 } 4797 4798 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4799 uint64_t Address, 4800 const MCDisassembler *Decoder) { 4801 const FeatureBitset &FeatureBits = 4802 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4803 DecodeStatus S = MCDisassembler::Success; 4804 4805 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4806 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4807 4808 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4810 return MCDisassembler::Fail; 4811 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4812 return MCDisassembler::Fail; 4813 return S; 4814 } 4815 4816 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4817 uint64_t Address, 4818 const MCDisassembler *Decoder) { 4819 DecodeStatus S = MCDisassembler::Success; 4820 4821 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4822 if (pred == 0xE || pred == 0xF) { 4823 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4824 switch (opc) { 4825 default: 4826 return MCDisassembler::Fail; 4827 case 0xf3bf8f4: 4828 Inst.setOpcode(ARM::t2DSB); 4829 break; 4830 case 0xf3bf8f5: 4831 Inst.setOpcode(ARM::t2DMB); 4832 break; 4833 case 0xf3bf8f6: 4834 Inst.setOpcode(ARM::t2ISB); 4835 break; 4836 } 4837 4838 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4839 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4840 } 4841 4842 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4843 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4844 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4845 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4846 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4847 4848 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4849 return MCDisassembler::Fail; 4850 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4851 return MCDisassembler::Fail; 4852 4853 return S; 4854 } 4855 4856 // Decode a shifted immediate operand. These basically consist 4857 // of an 8-bit value, and a 4-bit directive that specifies either 4858 // a splat operation or a rotation. 4859 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 4860 const MCDisassembler *Decoder) { 4861 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4862 if (ctrl == 0) { 4863 unsigned byte = fieldFromInstruction(Val, 8, 2); 4864 unsigned imm = fieldFromInstruction(Val, 0, 8); 4865 switch (byte) { 4866 case 0: 4867 Inst.addOperand(MCOperand::createImm(imm)); 4868 break; 4869 case 1: 4870 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4871 break; 4872 case 2: 4873 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4874 break; 4875 case 3: 4876 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4877 (imm << 8) | imm)); 4878 break; 4879 } 4880 } else { 4881 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4882 unsigned rot = fieldFromInstruction(Val, 7, 5); 4883 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4884 Inst.addOperand(MCOperand::createImm(imm)); 4885 } 4886 4887 return MCDisassembler::Success; 4888 } 4889 4890 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4891 uint64_t Address, 4892 const MCDisassembler *Decoder) { 4893 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4894 true, 2, Inst, Decoder)) 4895 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4896 return MCDisassembler::Success; 4897 } 4898 4899 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4900 uint64_t Address, 4901 const MCDisassembler *Decoder) { 4902 // Val is passed in as S:J1:J2:imm10:imm11 4903 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4904 // the encoded instruction. So here change to I1 and I2 values via: 4905 // I1 = NOT(J1 EOR S); 4906 // I2 = NOT(J2 EOR S); 4907 // and build the imm32 with one trailing zero as documented: 4908 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4909 unsigned S = (Val >> 23) & 1; 4910 unsigned J1 = (Val >> 22) & 1; 4911 unsigned J2 = (Val >> 21) & 1; 4912 unsigned I1 = !(J1 ^ S); 4913 unsigned I2 = !(J2 ^ S); 4914 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4915 int imm32 = SignExtend32<25>(tmp << 1); 4916 4917 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4918 true, 4, Inst, Decoder)) 4919 Inst.addOperand(MCOperand::createImm(imm32)); 4920 return MCDisassembler::Success; 4921 } 4922 4923 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4924 uint64_t Address, 4925 const MCDisassembler *Decoder) { 4926 if (Val & ~0xf) 4927 return MCDisassembler::Fail; 4928 4929 Inst.addOperand(MCOperand::createImm(Val)); 4930 return MCDisassembler::Success; 4931 } 4932 4933 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4934 uint64_t Address, 4935 const MCDisassembler *Decoder) { 4936 if (Val & ~0xf) 4937 return MCDisassembler::Fail; 4938 4939 Inst.addOperand(MCOperand::createImm(Val)); 4940 return MCDisassembler::Success; 4941 } 4942 4943 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, 4944 const MCDisassembler *Decoder) { 4945 DecodeStatus S = MCDisassembler::Success; 4946 const FeatureBitset &FeatureBits = 4947 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4948 4949 if (FeatureBits[ARM::FeatureMClass]) { 4950 unsigned ValLow = Val & 0xff; 4951 4952 // Validate the SYSm value first. 4953 switch (ValLow) { 4954 case 0: // apsr 4955 case 1: // iapsr 4956 case 2: // eapsr 4957 case 3: // xpsr 4958 case 5: // ipsr 4959 case 6: // epsr 4960 case 7: // iepsr 4961 case 8: // msp 4962 case 9: // psp 4963 case 16: // primask 4964 case 20: // control 4965 break; 4966 case 17: // basepri 4967 case 18: // basepri_max 4968 case 19: // faultmask 4969 if (!(FeatureBits[ARM::HasV7Ops])) 4970 // Values basepri, basepri_max and faultmask are only valid for v7m. 4971 return MCDisassembler::Fail; 4972 break; 4973 case 0x8a: // msplim_ns 4974 case 0x8b: // psplim_ns 4975 case 0x91: // basepri_ns 4976 case 0x93: // faultmask_ns 4977 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4978 return MCDisassembler::Fail; 4979 LLVM_FALLTHROUGH; 4980 case 10: // msplim 4981 case 11: // psplim 4982 case 0x88: // msp_ns 4983 case 0x89: // psp_ns 4984 case 0x90: // primask_ns 4985 case 0x94: // control_ns 4986 case 0x98: // sp_ns 4987 if (!(FeatureBits[ARM::Feature8MSecExt])) 4988 return MCDisassembler::Fail; 4989 break; 4990 case 0x20: // pac_key_p_0 4991 case 0x21: // pac_key_p_1 4992 case 0x22: // pac_key_p_2 4993 case 0x23: // pac_key_p_3 4994 case 0x24: // pac_key_u_0 4995 case 0x25: // pac_key_u_1 4996 case 0x26: // pac_key_u_2 4997 case 0x27: // pac_key_u_3 4998 case 0xa0: // pac_key_p_0_ns 4999 case 0xa1: // pac_key_p_1_ns 5000 case 0xa2: // pac_key_p_2_ns 5001 case 0xa3: // pac_key_p_3_ns 5002 case 0xa4: // pac_key_u_0_ns 5003 case 0xa5: // pac_key_u_1_ns 5004 case 0xa6: // pac_key_u_2_ns 5005 case 0xa7: // pac_key_u_3_ns 5006 if (!(FeatureBits[ARM::FeaturePACBTI])) 5007 return MCDisassembler::Fail; 5008 break; 5009 default: 5010 // Architecturally defined as unpredictable 5011 S = MCDisassembler::SoftFail; 5012 break; 5013 } 5014 5015 if (Inst.getOpcode() == ARM::t2MSR_M) { 5016 unsigned Mask = fieldFromInstruction(Val, 10, 2); 5017 if (!(FeatureBits[ARM::HasV7Ops])) { 5018 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 5019 // unpredictable. 5020 if (Mask != 2) 5021 S = MCDisassembler::SoftFail; 5022 } 5023 else { 5024 // The ARMv7-M architecture stores an additional 2-bit mask value in 5025 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 5026 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 5027 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 5028 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 5029 // only if the processor includes the DSP extension. 5030 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 5031 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 5032 S = MCDisassembler::SoftFail; 5033 } 5034 } 5035 } else { 5036 // A/R class 5037 if (Val == 0) 5038 return MCDisassembler::Fail; 5039 } 5040 Inst.addOperand(MCOperand::createImm(Val)); 5041 return S; 5042 } 5043 5044 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 5045 uint64_t Address, 5046 const MCDisassembler *Decoder) { 5047 unsigned R = fieldFromInstruction(Val, 5, 1); 5048 unsigned SysM = fieldFromInstruction(Val, 0, 5); 5049 5050 // The table of encodings for these banked registers comes from B9.2.3 of the 5051 // ARM ARM. There are patterns, but nothing regular enough to make this logic 5052 // neater. So by fiat, these values are UNPREDICTABLE: 5053 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 5054 return MCDisassembler::Fail; 5055 5056 Inst.addOperand(MCOperand::createImm(Val)); 5057 return MCDisassembler::Success; 5058 } 5059 5060 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 5061 uint64_t Address, 5062 const MCDisassembler *Decoder) { 5063 DecodeStatus S = MCDisassembler::Success; 5064 5065 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5066 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5067 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5068 5069 if (Rn == 0xF) 5070 S = MCDisassembler::SoftFail; 5071 5072 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5073 return MCDisassembler::Fail; 5074 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5075 return MCDisassembler::Fail; 5076 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5077 return MCDisassembler::Fail; 5078 5079 return S; 5080 } 5081 5082 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 5083 uint64_t Address, 5084 const MCDisassembler *Decoder) { 5085 DecodeStatus S = MCDisassembler::Success; 5086 5087 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5088 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 5089 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5090 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5091 5092 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 5093 return MCDisassembler::Fail; 5094 5095 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 5096 S = MCDisassembler::SoftFail; 5097 5098 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5099 return MCDisassembler::Fail; 5100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5101 return MCDisassembler::Fail; 5102 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5103 return MCDisassembler::Fail; 5104 5105 return S; 5106 } 5107 5108 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 5109 uint64_t Address, 5110 const MCDisassembler *Decoder) { 5111 DecodeStatus S = MCDisassembler::Success; 5112 5113 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5114 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5115 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5116 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5117 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5118 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5119 5120 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5121 5122 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5123 return MCDisassembler::Fail; 5124 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5125 return MCDisassembler::Fail; 5126 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5127 return MCDisassembler::Fail; 5128 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5129 return MCDisassembler::Fail; 5130 5131 return S; 5132 } 5133 5134 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 5135 uint64_t Address, 5136 const MCDisassembler *Decoder) { 5137 DecodeStatus S = MCDisassembler::Success; 5138 5139 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5140 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5141 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5142 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5143 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5144 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5145 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5146 5147 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5148 if (Rm == 0xF) S = MCDisassembler::SoftFail; 5149 5150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5151 return MCDisassembler::Fail; 5152 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5153 return MCDisassembler::Fail; 5154 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5155 return MCDisassembler::Fail; 5156 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5157 return MCDisassembler::Fail; 5158 5159 return S; 5160 } 5161 5162 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 5163 uint64_t Address, 5164 const MCDisassembler *Decoder) { 5165 DecodeStatus S = MCDisassembler::Success; 5166 5167 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5168 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5169 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5170 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5171 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5172 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5173 5174 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5175 5176 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5177 return MCDisassembler::Fail; 5178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5179 return MCDisassembler::Fail; 5180 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5181 return MCDisassembler::Fail; 5182 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5183 return MCDisassembler::Fail; 5184 5185 return S; 5186 } 5187 5188 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 5189 uint64_t Address, 5190 const MCDisassembler *Decoder) { 5191 DecodeStatus S = MCDisassembler::Success; 5192 5193 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5194 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5195 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5196 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5197 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5198 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5199 5200 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5201 5202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5203 return MCDisassembler::Fail; 5204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5205 return MCDisassembler::Fail; 5206 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5207 return MCDisassembler::Fail; 5208 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5209 return MCDisassembler::Fail; 5210 5211 return S; 5212 } 5213 5214 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5215 const MCDisassembler *Decoder) { 5216 DecodeStatus S = MCDisassembler::Success; 5217 5218 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5219 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5220 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5221 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5222 unsigned size = fieldFromInstruction(Insn, 10, 2); 5223 5224 unsigned align = 0; 5225 unsigned index = 0; 5226 switch (size) { 5227 default: 5228 return MCDisassembler::Fail; 5229 case 0: 5230 if (fieldFromInstruction(Insn, 4, 1)) 5231 return MCDisassembler::Fail; // UNDEFINED 5232 index = fieldFromInstruction(Insn, 5, 3); 5233 break; 5234 case 1: 5235 if (fieldFromInstruction(Insn, 5, 1)) 5236 return MCDisassembler::Fail; // UNDEFINED 5237 index = fieldFromInstruction(Insn, 6, 2); 5238 if (fieldFromInstruction(Insn, 4, 1)) 5239 align = 2; 5240 break; 5241 case 2: 5242 if (fieldFromInstruction(Insn, 6, 1)) 5243 return MCDisassembler::Fail; // UNDEFINED 5244 index = fieldFromInstruction(Insn, 7, 1); 5245 5246 switch (fieldFromInstruction(Insn, 4, 2)) { 5247 case 0 : 5248 align = 0; break; 5249 case 3: 5250 align = 4; break; 5251 default: 5252 return MCDisassembler::Fail; 5253 } 5254 break; 5255 } 5256 5257 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5258 return MCDisassembler::Fail; 5259 if (Rm != 0xF) { // Writeback 5260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5261 return MCDisassembler::Fail; 5262 } 5263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5264 return MCDisassembler::Fail; 5265 Inst.addOperand(MCOperand::createImm(align)); 5266 if (Rm != 0xF) { 5267 if (Rm != 0xD) { 5268 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5269 return MCDisassembler::Fail; 5270 } else 5271 Inst.addOperand(MCOperand::createReg(0)); 5272 } 5273 5274 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5275 return MCDisassembler::Fail; 5276 Inst.addOperand(MCOperand::createImm(index)); 5277 5278 return S; 5279 } 5280 5281 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5282 const MCDisassembler *Decoder) { 5283 DecodeStatus S = MCDisassembler::Success; 5284 5285 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5286 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5287 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5288 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5289 unsigned size = fieldFromInstruction(Insn, 10, 2); 5290 5291 unsigned align = 0; 5292 unsigned index = 0; 5293 switch (size) { 5294 default: 5295 return MCDisassembler::Fail; 5296 case 0: 5297 if (fieldFromInstruction(Insn, 4, 1)) 5298 return MCDisassembler::Fail; // UNDEFINED 5299 index = fieldFromInstruction(Insn, 5, 3); 5300 break; 5301 case 1: 5302 if (fieldFromInstruction(Insn, 5, 1)) 5303 return MCDisassembler::Fail; // UNDEFINED 5304 index = fieldFromInstruction(Insn, 6, 2); 5305 if (fieldFromInstruction(Insn, 4, 1)) 5306 align = 2; 5307 break; 5308 case 2: 5309 if (fieldFromInstruction(Insn, 6, 1)) 5310 return MCDisassembler::Fail; // UNDEFINED 5311 index = fieldFromInstruction(Insn, 7, 1); 5312 5313 switch (fieldFromInstruction(Insn, 4, 2)) { 5314 case 0: 5315 align = 0; break; 5316 case 3: 5317 align = 4; break; 5318 default: 5319 return MCDisassembler::Fail; 5320 } 5321 break; 5322 } 5323 5324 if (Rm != 0xF) { // Writeback 5325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5326 return MCDisassembler::Fail; 5327 } 5328 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5329 return MCDisassembler::Fail; 5330 Inst.addOperand(MCOperand::createImm(align)); 5331 if (Rm != 0xF) { 5332 if (Rm != 0xD) { 5333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5334 return MCDisassembler::Fail; 5335 } else 5336 Inst.addOperand(MCOperand::createReg(0)); 5337 } 5338 5339 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5340 return MCDisassembler::Fail; 5341 Inst.addOperand(MCOperand::createImm(index)); 5342 5343 return S; 5344 } 5345 5346 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5347 const MCDisassembler *Decoder) { 5348 DecodeStatus S = MCDisassembler::Success; 5349 5350 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5351 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5352 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5353 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5354 unsigned size = fieldFromInstruction(Insn, 10, 2); 5355 5356 unsigned align = 0; 5357 unsigned index = 0; 5358 unsigned inc = 1; 5359 switch (size) { 5360 default: 5361 return MCDisassembler::Fail; 5362 case 0: 5363 index = fieldFromInstruction(Insn, 5, 3); 5364 if (fieldFromInstruction(Insn, 4, 1)) 5365 align = 2; 5366 break; 5367 case 1: 5368 index = fieldFromInstruction(Insn, 6, 2); 5369 if (fieldFromInstruction(Insn, 4, 1)) 5370 align = 4; 5371 if (fieldFromInstruction(Insn, 5, 1)) 5372 inc = 2; 5373 break; 5374 case 2: 5375 if (fieldFromInstruction(Insn, 5, 1)) 5376 return MCDisassembler::Fail; // UNDEFINED 5377 index = fieldFromInstruction(Insn, 7, 1); 5378 if (fieldFromInstruction(Insn, 4, 1) != 0) 5379 align = 8; 5380 if (fieldFromInstruction(Insn, 6, 1)) 5381 inc = 2; 5382 break; 5383 } 5384 5385 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5386 return MCDisassembler::Fail; 5387 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5388 return MCDisassembler::Fail; 5389 if (Rm != 0xF) { // Writeback 5390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5391 return MCDisassembler::Fail; 5392 } 5393 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5394 return MCDisassembler::Fail; 5395 Inst.addOperand(MCOperand::createImm(align)); 5396 if (Rm != 0xF) { 5397 if (Rm != 0xD) { 5398 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5399 return MCDisassembler::Fail; 5400 } else 5401 Inst.addOperand(MCOperand::createReg(0)); 5402 } 5403 5404 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5405 return MCDisassembler::Fail; 5406 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5407 return MCDisassembler::Fail; 5408 Inst.addOperand(MCOperand::createImm(index)); 5409 5410 return S; 5411 } 5412 5413 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5414 const MCDisassembler *Decoder) { 5415 DecodeStatus S = MCDisassembler::Success; 5416 5417 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5418 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5419 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5420 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5421 unsigned size = fieldFromInstruction(Insn, 10, 2); 5422 5423 unsigned align = 0; 5424 unsigned index = 0; 5425 unsigned inc = 1; 5426 switch (size) { 5427 default: 5428 return MCDisassembler::Fail; 5429 case 0: 5430 index = fieldFromInstruction(Insn, 5, 3); 5431 if (fieldFromInstruction(Insn, 4, 1)) 5432 align = 2; 5433 break; 5434 case 1: 5435 index = fieldFromInstruction(Insn, 6, 2); 5436 if (fieldFromInstruction(Insn, 4, 1)) 5437 align = 4; 5438 if (fieldFromInstruction(Insn, 5, 1)) 5439 inc = 2; 5440 break; 5441 case 2: 5442 if (fieldFromInstruction(Insn, 5, 1)) 5443 return MCDisassembler::Fail; // UNDEFINED 5444 index = fieldFromInstruction(Insn, 7, 1); 5445 if (fieldFromInstruction(Insn, 4, 1) != 0) 5446 align = 8; 5447 if (fieldFromInstruction(Insn, 6, 1)) 5448 inc = 2; 5449 break; 5450 } 5451 5452 if (Rm != 0xF) { // Writeback 5453 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5454 return MCDisassembler::Fail; 5455 } 5456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5457 return MCDisassembler::Fail; 5458 Inst.addOperand(MCOperand::createImm(align)); 5459 if (Rm != 0xF) { 5460 if (Rm != 0xD) { 5461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5462 return MCDisassembler::Fail; 5463 } else 5464 Inst.addOperand(MCOperand::createReg(0)); 5465 } 5466 5467 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5468 return MCDisassembler::Fail; 5469 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5470 return MCDisassembler::Fail; 5471 Inst.addOperand(MCOperand::createImm(index)); 5472 5473 return S; 5474 } 5475 5476 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5477 const MCDisassembler *Decoder) { 5478 DecodeStatus S = MCDisassembler::Success; 5479 5480 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5481 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5482 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5483 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5484 unsigned size = fieldFromInstruction(Insn, 10, 2); 5485 5486 unsigned align = 0; 5487 unsigned index = 0; 5488 unsigned inc = 1; 5489 switch (size) { 5490 default: 5491 return MCDisassembler::Fail; 5492 case 0: 5493 if (fieldFromInstruction(Insn, 4, 1)) 5494 return MCDisassembler::Fail; // UNDEFINED 5495 index = fieldFromInstruction(Insn, 5, 3); 5496 break; 5497 case 1: 5498 if (fieldFromInstruction(Insn, 4, 1)) 5499 return MCDisassembler::Fail; // UNDEFINED 5500 index = fieldFromInstruction(Insn, 6, 2); 5501 if (fieldFromInstruction(Insn, 5, 1)) 5502 inc = 2; 5503 break; 5504 case 2: 5505 if (fieldFromInstruction(Insn, 4, 2)) 5506 return MCDisassembler::Fail; // UNDEFINED 5507 index = fieldFromInstruction(Insn, 7, 1); 5508 if (fieldFromInstruction(Insn, 6, 1)) 5509 inc = 2; 5510 break; 5511 } 5512 5513 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5514 return MCDisassembler::Fail; 5515 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5516 return MCDisassembler::Fail; 5517 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5518 return MCDisassembler::Fail; 5519 5520 if (Rm != 0xF) { // Writeback 5521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5522 return MCDisassembler::Fail; 5523 } 5524 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5525 return MCDisassembler::Fail; 5526 Inst.addOperand(MCOperand::createImm(align)); 5527 if (Rm != 0xF) { 5528 if (Rm != 0xD) { 5529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5530 return MCDisassembler::Fail; 5531 } else 5532 Inst.addOperand(MCOperand::createReg(0)); 5533 } 5534 5535 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5536 return MCDisassembler::Fail; 5537 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5538 return MCDisassembler::Fail; 5539 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5540 return MCDisassembler::Fail; 5541 Inst.addOperand(MCOperand::createImm(index)); 5542 5543 return S; 5544 } 5545 5546 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5547 const MCDisassembler *Decoder) { 5548 DecodeStatus S = MCDisassembler::Success; 5549 5550 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5551 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5552 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5553 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5554 unsigned size = fieldFromInstruction(Insn, 10, 2); 5555 5556 unsigned align = 0; 5557 unsigned index = 0; 5558 unsigned inc = 1; 5559 switch (size) { 5560 default: 5561 return MCDisassembler::Fail; 5562 case 0: 5563 if (fieldFromInstruction(Insn, 4, 1)) 5564 return MCDisassembler::Fail; // UNDEFINED 5565 index = fieldFromInstruction(Insn, 5, 3); 5566 break; 5567 case 1: 5568 if (fieldFromInstruction(Insn, 4, 1)) 5569 return MCDisassembler::Fail; // UNDEFINED 5570 index = fieldFromInstruction(Insn, 6, 2); 5571 if (fieldFromInstruction(Insn, 5, 1)) 5572 inc = 2; 5573 break; 5574 case 2: 5575 if (fieldFromInstruction(Insn, 4, 2)) 5576 return MCDisassembler::Fail; // UNDEFINED 5577 index = fieldFromInstruction(Insn, 7, 1); 5578 if (fieldFromInstruction(Insn, 6, 1)) 5579 inc = 2; 5580 break; 5581 } 5582 5583 if (Rm != 0xF) { // Writeback 5584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5585 return MCDisassembler::Fail; 5586 } 5587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5588 return MCDisassembler::Fail; 5589 Inst.addOperand(MCOperand::createImm(align)); 5590 if (Rm != 0xF) { 5591 if (Rm != 0xD) { 5592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5593 return MCDisassembler::Fail; 5594 } else 5595 Inst.addOperand(MCOperand::createReg(0)); 5596 } 5597 5598 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5599 return MCDisassembler::Fail; 5600 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5601 return MCDisassembler::Fail; 5602 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5603 return MCDisassembler::Fail; 5604 Inst.addOperand(MCOperand::createImm(index)); 5605 5606 return S; 5607 } 5608 5609 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5610 const MCDisassembler *Decoder) { 5611 DecodeStatus S = MCDisassembler::Success; 5612 5613 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5614 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5615 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5616 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5617 unsigned size = fieldFromInstruction(Insn, 10, 2); 5618 5619 unsigned align = 0; 5620 unsigned index = 0; 5621 unsigned inc = 1; 5622 switch (size) { 5623 default: 5624 return MCDisassembler::Fail; 5625 case 0: 5626 if (fieldFromInstruction(Insn, 4, 1)) 5627 align = 4; 5628 index = fieldFromInstruction(Insn, 5, 3); 5629 break; 5630 case 1: 5631 if (fieldFromInstruction(Insn, 4, 1)) 5632 align = 8; 5633 index = fieldFromInstruction(Insn, 6, 2); 5634 if (fieldFromInstruction(Insn, 5, 1)) 5635 inc = 2; 5636 break; 5637 case 2: 5638 switch (fieldFromInstruction(Insn, 4, 2)) { 5639 case 0: 5640 align = 0; break; 5641 case 3: 5642 return MCDisassembler::Fail; 5643 default: 5644 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5645 } 5646 5647 index = fieldFromInstruction(Insn, 7, 1); 5648 if (fieldFromInstruction(Insn, 6, 1)) 5649 inc = 2; 5650 break; 5651 } 5652 5653 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5654 return MCDisassembler::Fail; 5655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5656 return MCDisassembler::Fail; 5657 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5658 return MCDisassembler::Fail; 5659 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5660 return MCDisassembler::Fail; 5661 5662 if (Rm != 0xF) { // Writeback 5663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5664 return MCDisassembler::Fail; 5665 } 5666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5667 return MCDisassembler::Fail; 5668 Inst.addOperand(MCOperand::createImm(align)); 5669 if (Rm != 0xF) { 5670 if (Rm != 0xD) { 5671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5672 return MCDisassembler::Fail; 5673 } else 5674 Inst.addOperand(MCOperand::createReg(0)); 5675 } 5676 5677 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5678 return MCDisassembler::Fail; 5679 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5680 return MCDisassembler::Fail; 5681 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5682 return MCDisassembler::Fail; 5683 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5684 return MCDisassembler::Fail; 5685 Inst.addOperand(MCOperand::createImm(index)); 5686 5687 return S; 5688 } 5689 5690 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5691 const MCDisassembler *Decoder) { 5692 DecodeStatus S = MCDisassembler::Success; 5693 5694 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5695 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5696 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5697 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5698 unsigned size = fieldFromInstruction(Insn, 10, 2); 5699 5700 unsigned align = 0; 5701 unsigned index = 0; 5702 unsigned inc = 1; 5703 switch (size) { 5704 default: 5705 return MCDisassembler::Fail; 5706 case 0: 5707 if (fieldFromInstruction(Insn, 4, 1)) 5708 align = 4; 5709 index = fieldFromInstruction(Insn, 5, 3); 5710 break; 5711 case 1: 5712 if (fieldFromInstruction(Insn, 4, 1)) 5713 align = 8; 5714 index = fieldFromInstruction(Insn, 6, 2); 5715 if (fieldFromInstruction(Insn, 5, 1)) 5716 inc = 2; 5717 break; 5718 case 2: 5719 switch (fieldFromInstruction(Insn, 4, 2)) { 5720 case 0: 5721 align = 0; break; 5722 case 3: 5723 return MCDisassembler::Fail; 5724 default: 5725 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5726 } 5727 5728 index = fieldFromInstruction(Insn, 7, 1); 5729 if (fieldFromInstruction(Insn, 6, 1)) 5730 inc = 2; 5731 break; 5732 } 5733 5734 if (Rm != 0xF) { // Writeback 5735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5736 return MCDisassembler::Fail; 5737 } 5738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5739 return MCDisassembler::Fail; 5740 Inst.addOperand(MCOperand::createImm(align)); 5741 if (Rm != 0xF) { 5742 if (Rm != 0xD) { 5743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5744 return MCDisassembler::Fail; 5745 } else 5746 Inst.addOperand(MCOperand::createReg(0)); 5747 } 5748 5749 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5750 return MCDisassembler::Fail; 5751 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5752 return MCDisassembler::Fail; 5753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5754 return MCDisassembler::Fail; 5755 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5756 return MCDisassembler::Fail; 5757 Inst.addOperand(MCOperand::createImm(index)); 5758 5759 return S; 5760 } 5761 5762 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 5763 const MCDisassembler *Decoder) { 5764 DecodeStatus S = MCDisassembler::Success; 5765 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5766 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5767 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5768 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5769 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5770 5771 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5772 S = MCDisassembler::SoftFail; 5773 5774 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5775 return MCDisassembler::Fail; 5776 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5777 return MCDisassembler::Fail; 5778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5779 return MCDisassembler::Fail; 5780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5781 return MCDisassembler::Fail; 5782 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5783 return MCDisassembler::Fail; 5784 5785 return S; 5786 } 5787 5788 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 5789 const MCDisassembler *Decoder) { 5790 DecodeStatus S = MCDisassembler::Success; 5791 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5792 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5793 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5794 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5795 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5796 5797 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5798 S = MCDisassembler::SoftFail; 5799 5800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5801 return MCDisassembler::Fail; 5802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5803 return MCDisassembler::Fail; 5804 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5805 return MCDisassembler::Fail; 5806 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5807 return MCDisassembler::Fail; 5808 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5809 return MCDisassembler::Fail; 5810 5811 return S; 5812 } 5813 5814 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, 5815 const MCDisassembler *Decoder) { 5816 DecodeStatus S = MCDisassembler::Success; 5817 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5818 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5819 5820 if (pred == 0xF) { 5821 pred = 0xE; 5822 S = MCDisassembler::SoftFail; 5823 } 5824 5825 if (mask == 0x0) 5826 return MCDisassembler::Fail; 5827 5828 // IT masks are encoded as a sequence of replacement low-order bits 5829 // for the condition code. So if the low bit of the starting 5830 // condition code is 1, then we have to flip all the bits above the 5831 // terminating bit (which is the lowest 1 bit). 5832 if (pred & 1) { 5833 unsigned LowBit = mask & -mask; 5834 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5835 mask ^= BitsAboveLowBit; 5836 } 5837 5838 Inst.addOperand(MCOperand::createImm(pred)); 5839 Inst.addOperand(MCOperand::createImm(mask)); 5840 return S; 5841 } 5842 5843 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5844 uint64_t Address, 5845 const MCDisassembler *Decoder) { 5846 DecodeStatus S = MCDisassembler::Success; 5847 5848 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5849 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5850 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5851 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5852 unsigned W = fieldFromInstruction(Insn, 21, 1); 5853 unsigned U = fieldFromInstruction(Insn, 23, 1); 5854 unsigned P = fieldFromInstruction(Insn, 24, 1); 5855 bool writeback = (W == 1) | (P == 0); 5856 5857 addr |= (U << 8) | (Rn << 9); 5858 5859 if (writeback && (Rn == Rt || Rn == Rt2)) 5860 Check(S, MCDisassembler::SoftFail); 5861 if (Rt == Rt2) 5862 Check(S, MCDisassembler::SoftFail); 5863 5864 // Rt 5865 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5866 return MCDisassembler::Fail; 5867 // Rt2 5868 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5869 return MCDisassembler::Fail; 5870 // Writeback operand 5871 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5872 return MCDisassembler::Fail; 5873 // addr 5874 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5875 return MCDisassembler::Fail; 5876 5877 return S; 5878 } 5879 5880 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5881 uint64_t Address, 5882 const MCDisassembler *Decoder) { 5883 DecodeStatus S = MCDisassembler::Success; 5884 5885 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5886 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5887 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5888 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5889 unsigned W = fieldFromInstruction(Insn, 21, 1); 5890 unsigned U = fieldFromInstruction(Insn, 23, 1); 5891 unsigned P = fieldFromInstruction(Insn, 24, 1); 5892 bool writeback = (W == 1) | (P == 0); 5893 5894 addr |= (U << 8) | (Rn << 9); 5895 5896 if (writeback && (Rn == Rt || Rn == Rt2)) 5897 Check(S, MCDisassembler::SoftFail); 5898 5899 // Writeback operand 5900 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5901 return MCDisassembler::Fail; 5902 // Rt 5903 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5904 return MCDisassembler::Fail; 5905 // Rt2 5906 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5907 return MCDisassembler::Fail; 5908 // addr 5909 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5910 return MCDisassembler::Fail; 5911 5912 return S; 5913 } 5914 5915 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, 5916 const MCDisassembler *Decoder) { 5917 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5918 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5919 if (sign1 != sign2) return MCDisassembler::Fail; 5920 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5921 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5922 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5923 5924 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5925 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5926 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5927 // If sign, then it is decreasing the address. 5928 if (sign1) { 5929 // Following ARMv7 Architecture Manual, when the offset 5930 // is zero, it is decoded as a subw, not as a adr.w 5931 if (!Val) { 5932 Inst.setOpcode(ARM::t2SUBri12); 5933 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5934 } else 5935 Val = -Val; 5936 } 5937 Inst.addOperand(MCOperand::createImm(Val)); 5938 return S; 5939 } 5940 5941 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5942 uint64_t Address, 5943 const MCDisassembler *Decoder) { 5944 DecodeStatus S = MCDisassembler::Success; 5945 5946 // Shift of "asr #32" is not allowed in Thumb2 mode. 5947 if (Val == 0x20) S = MCDisassembler::Fail; 5948 Inst.addOperand(MCOperand::createImm(Val)); 5949 return S; 5950 } 5951 5952 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 5953 const MCDisassembler *Decoder) { 5954 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5955 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5956 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5957 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5958 5959 if (pred == 0xF) 5960 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5961 5962 DecodeStatus S = MCDisassembler::Success; 5963 5964 if (Rt == Rn || Rn == Rt2) 5965 S = MCDisassembler::SoftFail; 5966 5967 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5968 return MCDisassembler::Fail; 5969 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5970 return MCDisassembler::Fail; 5971 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5972 return MCDisassembler::Fail; 5973 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5974 return MCDisassembler::Fail; 5975 5976 return S; 5977 } 5978 5979 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 5980 const MCDisassembler *Decoder) { 5981 const FeatureBitset &featureBits = 5982 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5983 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5984 5985 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5986 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5987 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5988 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5989 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5990 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5991 unsigned op = fieldFromInstruction(Insn, 5, 1); 5992 5993 DecodeStatus S = MCDisassembler::Success; 5994 5995 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5996 if (!(imm & 0x38)) { 5997 if (cmode == 0xF) { 5998 if (op == 1) return MCDisassembler::Fail; 5999 Inst.setOpcode(ARM::VMOVv2f32); 6000 } 6001 if (hasFullFP16) { 6002 if (cmode == 0xE) { 6003 if (op == 1) { 6004 Inst.setOpcode(ARM::VMOVv1i64); 6005 } else { 6006 Inst.setOpcode(ARM::VMOVv8i8); 6007 } 6008 } 6009 if (cmode == 0xD) { 6010 if (op == 1) { 6011 Inst.setOpcode(ARM::VMVNv2i32); 6012 } else { 6013 Inst.setOpcode(ARM::VMOVv2i32); 6014 } 6015 } 6016 if (cmode == 0xC) { 6017 if (op == 1) { 6018 Inst.setOpcode(ARM::VMVNv2i32); 6019 } else { 6020 Inst.setOpcode(ARM::VMOVv2i32); 6021 } 6022 } 6023 } 6024 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6025 } 6026 6027 if (!(imm & 0x20)) return MCDisassembler::Fail; 6028 6029 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 6030 return MCDisassembler::Fail; 6031 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6032 return MCDisassembler::Fail; 6033 Inst.addOperand(MCOperand::createImm(64 - imm)); 6034 6035 return S; 6036 } 6037 6038 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 6039 const MCDisassembler *Decoder) { 6040 const FeatureBitset &featureBits = 6041 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6042 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6043 6044 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6045 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6046 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6047 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6048 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6049 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6050 unsigned op = fieldFromInstruction(Insn, 5, 1); 6051 6052 DecodeStatus S = MCDisassembler::Success; 6053 6054 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6055 if (!(imm & 0x38)) { 6056 if (cmode == 0xF) { 6057 if (op == 1) return MCDisassembler::Fail; 6058 Inst.setOpcode(ARM::VMOVv4f32); 6059 } 6060 if (hasFullFP16) { 6061 if (cmode == 0xE) { 6062 if (op == 1) { 6063 Inst.setOpcode(ARM::VMOVv2i64); 6064 } else { 6065 Inst.setOpcode(ARM::VMOVv16i8); 6066 } 6067 } 6068 if (cmode == 0xD) { 6069 if (op == 1) { 6070 Inst.setOpcode(ARM::VMVNv4i32); 6071 } else { 6072 Inst.setOpcode(ARM::VMOVv4i32); 6073 } 6074 } 6075 if (cmode == 0xC) { 6076 if (op == 1) { 6077 Inst.setOpcode(ARM::VMVNv4i32); 6078 } else { 6079 Inst.setOpcode(ARM::VMOVv4i32); 6080 } 6081 } 6082 } 6083 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6084 } 6085 6086 if (!(imm & 0x20)) return MCDisassembler::Fail; 6087 6088 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 6089 return MCDisassembler::Fail; 6090 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 6091 return MCDisassembler::Fail; 6092 Inst.addOperand(MCOperand::createImm(64 - imm)); 6093 6094 return S; 6095 } 6096 6097 static DecodeStatus 6098 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, 6099 uint64_t Address, 6100 const MCDisassembler *Decoder) { 6101 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6102 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6103 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 6104 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 6105 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6106 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6107 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 6108 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 6109 6110 DecodeStatus S = MCDisassembler::Success; 6111 6112 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 6113 6114 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6115 return MCDisassembler::Fail; 6116 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6117 return MCDisassembler::Fail; 6118 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 6119 return MCDisassembler::Fail; 6120 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6121 return MCDisassembler::Fail; 6122 // The lane index does not have any bits in the encoding, because it can only 6123 // be 0. 6124 Inst.addOperand(MCOperand::createImm(0)); 6125 Inst.addOperand(MCOperand::createImm(rotate)); 6126 6127 return S; 6128 } 6129 6130 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 6131 const MCDisassembler *Decoder) { 6132 DecodeStatus S = MCDisassembler::Success; 6133 6134 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6135 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6136 unsigned Rm = fieldFromInstruction(Val, 0, 4); 6137 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 6138 unsigned Cond = fieldFromInstruction(Val, 28, 4); 6139 6140 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 6141 S = MCDisassembler::SoftFail; 6142 6143 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6144 return MCDisassembler::Fail; 6145 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6146 return MCDisassembler::Fail; 6147 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 6148 return MCDisassembler::Fail; 6149 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 6150 return MCDisassembler::Fail; 6151 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 6152 return MCDisassembler::Fail; 6153 6154 return S; 6155 } 6156 6157 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 6158 uint64_t Address, 6159 const MCDisassembler *Decoder) { 6160 DecodeStatus S = MCDisassembler::Success; 6161 6162 unsigned CRm = fieldFromInstruction(Val, 0, 4); 6163 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 6164 unsigned cop = fieldFromInstruction(Val, 8, 4); 6165 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6166 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 6167 6168 if ((cop & ~0x1) == 0xa) 6169 return MCDisassembler::Fail; 6170 6171 if (Rt == Rt2) 6172 S = MCDisassembler::SoftFail; 6173 6174 // We have to check if the instruction is MRRC2 6175 // or MCRR2 when constructing the operands for 6176 // Inst. Reason is because MRRC2 stores to two 6177 // registers so it's tablegen desc has has two 6178 // outputs whereas MCRR doesn't store to any 6179 // registers so all of it's operands are listed 6180 // as inputs, therefore the operand order for 6181 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 6182 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 6183 6184 if (Inst.getOpcode() == ARM::MRRC2) { 6185 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6186 return MCDisassembler::Fail; 6187 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6188 return MCDisassembler::Fail; 6189 } 6190 Inst.addOperand(MCOperand::createImm(cop)); 6191 Inst.addOperand(MCOperand::createImm(opc1)); 6192 if (Inst.getOpcode() == ARM::MCRR2) { 6193 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6194 return MCDisassembler::Fail; 6195 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6196 return MCDisassembler::Fail; 6197 } 6198 Inst.addOperand(MCOperand::createImm(CRm)); 6199 6200 return S; 6201 } 6202 6203 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 6204 uint64_t Address, 6205 const MCDisassembler *Decoder) { 6206 const FeatureBitset &featureBits = 6207 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6208 DecodeStatus S = MCDisassembler::Success; 6209 6210 // Add explicit operand for the destination sysreg, for cases where 6211 // we have to model it for code generation purposes. 6212 switch (Inst.getOpcode()) { 6213 case ARM::VMSR_FPSCR_NZCVQC: 6214 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6215 break; 6216 case ARM::VMSR_P0: 6217 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6218 break; 6219 } 6220 6221 if (Inst.getOpcode() != ARM::FMSTAT) { 6222 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6223 6224 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 6225 if (Rt == 13 || Rt == 15) 6226 S = MCDisassembler::SoftFail; 6227 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 6228 } else 6229 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 6230 } 6231 6232 // Add explicit operand for the source sysreg, similarly to above. 6233 switch (Inst.getOpcode()) { 6234 case ARM::VMRS_FPSCR_NZCVQC: 6235 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6236 break; 6237 case ARM::VMRS_P0: 6238 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6239 break; 6240 } 6241 6242 if (featureBits[ARM::ModeThumb]) { 6243 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6244 Inst.addOperand(MCOperand::createReg(0)); 6245 } else { 6246 unsigned pred = fieldFromInstruction(Val, 28, 4); 6247 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6248 return MCDisassembler::Fail; 6249 } 6250 6251 return S; 6252 } 6253 6254 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 6255 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 6256 uint64_t Address, 6257 const MCDisassembler *Decoder) { 6258 DecodeStatus S = MCDisassembler::Success; 6259 if (Val == 0 && !zeroPermitted) 6260 S = MCDisassembler::Fail; 6261 6262 uint64_t DecVal; 6263 if (isSigned) 6264 DecVal = SignExtend32<size + 1>(Val << 1); 6265 else 6266 DecVal = (Val << 1); 6267 6268 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 6269 Decoder)) 6270 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 6271 return S; 6272 } 6273 6274 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 6275 uint64_t Address, 6276 const MCDisassembler *Decoder) { 6277 6278 uint64_t LocImm = Inst.getOperand(0).getImm(); 6279 Val = LocImm + (2 << Val); 6280 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 6281 Decoder)) 6282 Inst.addOperand(MCOperand::createImm(Val)); 6283 return MCDisassembler::Success; 6284 } 6285 6286 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 6287 uint64_t Address, 6288 const MCDisassembler *Decoder) { 6289 if (Val >= ARMCC::AL) // also exclude the non-condition NV 6290 return MCDisassembler::Fail; 6291 Inst.addOperand(MCOperand::createImm(Val)); 6292 return MCDisassembler::Success; 6293 } 6294 6295 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6296 const MCDisassembler *Decoder) { 6297 DecodeStatus S = MCDisassembler::Success; 6298 6299 if (Inst.getOpcode() == ARM::MVE_LCTP) 6300 return S; 6301 6302 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6303 fieldFromInstruction(Insn, 1, 10) << 1; 6304 switch (Inst.getOpcode()) { 6305 case ARM::t2LEUpdate: 6306 case ARM::MVE_LETP: 6307 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6308 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6309 LLVM_FALLTHROUGH; 6310 case ARM::t2LE: 6311 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6312 Inst, Imm, Address, Decoder))) 6313 return MCDisassembler::Fail; 6314 break; 6315 case ARM::t2WLS: 6316 case ARM::MVE_WLSTP_8: 6317 case ARM::MVE_WLSTP_16: 6318 case ARM::MVE_WLSTP_32: 6319 case ARM::MVE_WLSTP_64: 6320 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6321 if (!Check(S, 6322 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6323 Address, Decoder)) || 6324 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6325 Inst, Imm, Address, Decoder))) 6326 return MCDisassembler::Fail; 6327 break; 6328 case ARM::t2DLS: 6329 case ARM::MVE_DLSTP_8: 6330 case ARM::MVE_DLSTP_16: 6331 case ARM::MVE_DLSTP_32: 6332 case ARM::MVE_DLSTP_64: 6333 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6334 if (Rn == 0xF) { 6335 // Enforce all the rest of the instruction bits in LCTP, which 6336 // won't have been reliably checked based on LCTP's own tablegen 6337 // record, because we came to this decode by a roundabout route. 6338 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6339 if ((Insn & ~SBZMask) != CanonicalLCTP) 6340 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6341 if (Insn != CanonicalLCTP) 6342 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6343 6344 Inst.setOpcode(ARM::MVE_LCTP); 6345 } else { 6346 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6347 if (!Check(S, DecoderGPRRegisterClass(Inst, 6348 fieldFromInstruction(Insn, 16, 4), 6349 Address, Decoder))) 6350 return MCDisassembler::Fail; 6351 } 6352 break; 6353 } 6354 return S; 6355 } 6356 6357 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6358 uint64_t Address, 6359 const MCDisassembler *Decoder) { 6360 DecodeStatus S = MCDisassembler::Success; 6361 6362 if (Val == 0) 6363 Val = 32; 6364 6365 Inst.addOperand(MCOperand::createImm(Val)); 6366 6367 return S; 6368 } 6369 6370 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6371 uint64_t Address, 6372 const MCDisassembler *Decoder) { 6373 if ((RegNo) + 1 > 11) 6374 return MCDisassembler::Fail; 6375 6376 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6377 Inst.addOperand(MCOperand::createReg(Register)); 6378 return MCDisassembler::Success; 6379 } 6380 6381 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6382 uint64_t Address, 6383 const MCDisassembler *Decoder) { 6384 if ((RegNo) > 14) 6385 return MCDisassembler::Fail; 6386 6387 unsigned Register = GPRDecoderTable[(RegNo)]; 6388 Inst.addOperand(MCOperand::createReg(Register)); 6389 return MCDisassembler::Success; 6390 } 6391 6392 static DecodeStatus 6393 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6394 uint64_t Address, 6395 const MCDisassembler *Decoder) { 6396 if (RegNo == 15) { 6397 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6398 return MCDisassembler::Success; 6399 } 6400 6401 unsigned Register = GPRDecoderTable[RegNo]; 6402 Inst.addOperand(MCOperand::createReg(Register)); 6403 6404 if (RegNo == 13) 6405 return MCDisassembler::SoftFail; 6406 6407 return MCDisassembler::Success; 6408 } 6409 6410 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6411 const MCDisassembler *Decoder) { 6412 DecodeStatus S = MCDisassembler::Success; 6413 6414 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6415 Inst.addOperand(MCOperand::createReg(0)); 6416 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6417 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6418 (fieldFromInstruction(Insn, 12, 4) << 8) | 6419 (fieldFromInstruction(Insn, 22, 1) << 12); 6420 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6421 return MCDisassembler::Fail; 6422 } 6423 } else { 6424 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6425 (fieldFromInstruction(Insn, 22, 1) << 8) | 6426 (fieldFromInstruction(Insn, 12, 4) << 9); 6427 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6428 return MCDisassembler::Fail; 6429 } 6430 } 6431 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6432 6433 return S; 6434 } 6435 6436 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6437 uint64_t Address, 6438 const MCDisassembler *Decoder) { 6439 if (RegNo > 7) 6440 return MCDisassembler::Fail; 6441 6442 unsigned Register = QPRDecoderTable[RegNo]; 6443 Inst.addOperand(MCOperand::createReg(Register)); 6444 return MCDisassembler::Success; 6445 } 6446 6447 static const uint16_t QQPRDecoderTable[] = { 6448 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6449 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6450 }; 6451 6452 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6453 uint64_t Address, 6454 const MCDisassembler *Decoder) { 6455 if (RegNo > 6) 6456 return MCDisassembler::Fail; 6457 6458 unsigned Register = QQPRDecoderTable[RegNo]; 6459 Inst.addOperand(MCOperand::createReg(Register)); 6460 return MCDisassembler::Success; 6461 } 6462 6463 static const uint16_t QQQQPRDecoderTable[] = { 6464 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6465 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6466 }; 6467 6468 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6469 uint64_t Address, 6470 const MCDisassembler *Decoder) { 6471 if (RegNo > 4) 6472 return MCDisassembler::Fail; 6473 6474 unsigned Register = QQQQPRDecoderTable[RegNo]; 6475 Inst.addOperand(MCOperand::createReg(Register)); 6476 return MCDisassembler::Success; 6477 } 6478 6479 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6480 uint64_t Address, 6481 const MCDisassembler *Decoder) { 6482 DecodeStatus S = MCDisassembler::Success; 6483 6484 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6485 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6486 // 't' as 0 and finish with a 1. 6487 unsigned Imm = 0; 6488 // We always start with a 't'. 6489 unsigned CurBit = 0; 6490 for (int i = 3; i >= 0; --i) { 6491 // If the bit we are looking at is not the same as last one, invert the 6492 // CurBit, if it is the same leave it as is. 6493 CurBit ^= (Val >> i) & 1U; 6494 6495 // Encode the CurBit at the right place in the immediate. 6496 Imm |= (CurBit << i); 6497 6498 // If we are done, finish the encoding with a 1. 6499 if ((Val & ~(~0U << i)) == 0) { 6500 Imm |= 1U << i; 6501 break; 6502 } 6503 } 6504 6505 Inst.addOperand(MCOperand::createImm(Imm)); 6506 6507 return S; 6508 } 6509 6510 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6511 uint64_t Address, 6512 const MCDisassembler *Decoder) { 6513 // The vpred_r operand type includes an MQPR register field derived 6514 // from the encoding. But we don't actually want to add an operand 6515 // to the MCInst at this stage, because AddThumbPredicate will do it 6516 // later, and will infer the register number from the TIED_TO 6517 // constraint. So this is a deliberately empty decoder method that 6518 // will inhibit the auto-generated disassembly code from adding an 6519 // operand at all. 6520 return MCDisassembler::Success; 6521 } 6522 6523 static DecodeStatus 6524 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6525 const MCDisassembler *Decoder) { 6526 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6527 return MCDisassembler::Success; 6528 } 6529 6530 static DecodeStatus 6531 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6532 const MCDisassembler *Decoder) { 6533 unsigned Code; 6534 switch (Val & 0x3) { 6535 case 0: 6536 Code = ARMCC::GE; 6537 break; 6538 case 1: 6539 Code = ARMCC::LT; 6540 break; 6541 case 2: 6542 Code = ARMCC::GT; 6543 break; 6544 case 3: 6545 Code = ARMCC::LE; 6546 break; 6547 } 6548 Inst.addOperand(MCOperand::createImm(Code)); 6549 return MCDisassembler::Success; 6550 } 6551 6552 static DecodeStatus 6553 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6554 const MCDisassembler *Decoder) { 6555 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6556 return MCDisassembler::Success; 6557 } 6558 6559 static DecodeStatus 6560 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6561 const MCDisassembler *Decoder) { 6562 unsigned Code; 6563 switch (Val) { 6564 default: 6565 return MCDisassembler::Fail; 6566 case 0: 6567 Code = ARMCC::EQ; 6568 break; 6569 case 1: 6570 Code = ARMCC::NE; 6571 break; 6572 case 4: 6573 Code = ARMCC::GE; 6574 break; 6575 case 5: 6576 Code = ARMCC::LT; 6577 break; 6578 case 6: 6579 Code = ARMCC::GT; 6580 break; 6581 case 7: 6582 Code = ARMCC::LE; 6583 break; 6584 } 6585 6586 Inst.addOperand(MCOperand::createImm(Code)); 6587 return MCDisassembler::Success; 6588 } 6589 6590 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6591 uint64_t Address, 6592 const MCDisassembler *Decoder) { 6593 DecodeStatus S = MCDisassembler::Success; 6594 6595 unsigned DecodedVal = 64 - Val; 6596 6597 switch (Inst.getOpcode()) { 6598 case ARM::MVE_VCVTf16s16_fix: 6599 case ARM::MVE_VCVTs16f16_fix: 6600 case ARM::MVE_VCVTf16u16_fix: 6601 case ARM::MVE_VCVTu16f16_fix: 6602 if (DecodedVal > 16) 6603 return MCDisassembler::Fail; 6604 break; 6605 case ARM::MVE_VCVTf32s32_fix: 6606 case ARM::MVE_VCVTs32f32_fix: 6607 case ARM::MVE_VCVTf32u32_fix: 6608 case ARM::MVE_VCVTu32f32_fix: 6609 if (DecodedVal > 32) 6610 return MCDisassembler::Fail; 6611 break; 6612 } 6613 6614 Inst.addOperand(MCOperand::createImm(64 - Val)); 6615 6616 return S; 6617 } 6618 6619 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6620 switch (Opcode) { 6621 case ARM::VSTR_P0_off: 6622 case ARM::VSTR_P0_pre: 6623 case ARM::VSTR_P0_post: 6624 case ARM::VLDR_P0_off: 6625 case ARM::VLDR_P0_pre: 6626 case ARM::VLDR_P0_post: 6627 return ARM::P0; 6628 default: 6629 return 0; 6630 } 6631 } 6632 6633 template <bool Writeback> 6634 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6635 uint64_t Address, 6636 const MCDisassembler *Decoder) { 6637 switch (Inst.getOpcode()) { 6638 case ARM::VSTR_FPSCR_pre: 6639 case ARM::VSTR_FPSCR_NZCVQC_pre: 6640 case ARM::VLDR_FPSCR_pre: 6641 case ARM::VLDR_FPSCR_NZCVQC_pre: 6642 case ARM::VSTR_FPSCR_off: 6643 case ARM::VSTR_FPSCR_NZCVQC_off: 6644 case ARM::VLDR_FPSCR_off: 6645 case ARM::VLDR_FPSCR_NZCVQC_off: 6646 case ARM::VSTR_FPSCR_post: 6647 case ARM::VSTR_FPSCR_NZCVQC_post: 6648 case ARM::VLDR_FPSCR_post: 6649 case ARM::VLDR_FPSCR_NZCVQC_post: 6650 const FeatureBitset &featureBits = 6651 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6652 6653 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6654 return MCDisassembler::Fail; 6655 } 6656 6657 DecodeStatus S = MCDisassembler::Success; 6658 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6659 Inst.addOperand(MCOperand::createReg(Sysreg)); 6660 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6661 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6662 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6663 6664 if (Writeback) { 6665 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6666 return MCDisassembler::Fail; 6667 } 6668 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6669 return MCDisassembler::Fail; 6670 6671 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6672 Inst.addOperand(MCOperand::createReg(0)); 6673 6674 return S; 6675 } 6676 6677 static inline DecodeStatus 6678 DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, 6679 const MCDisassembler *Decoder, unsigned Rn, 6680 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6681 DecodeStatus S = MCDisassembler::Success; 6682 6683 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6684 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6685 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6686 6687 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6688 return MCDisassembler::Fail; 6689 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6690 return MCDisassembler::Fail; 6691 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6692 return MCDisassembler::Fail; 6693 6694 return S; 6695 } 6696 6697 template <int shift> 6698 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6699 uint64_t Address, 6700 const MCDisassembler *Decoder) { 6701 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6702 fieldFromInstruction(Val, 16, 3), 6703 DecodetGPRRegisterClass, 6704 DecodeTAddrModeImm7<shift>); 6705 } 6706 6707 template <int shift> 6708 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6709 uint64_t Address, 6710 const MCDisassembler *Decoder) { 6711 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6712 fieldFromInstruction(Val, 16, 4), 6713 DecoderGPRRegisterClass, 6714 DecodeT2AddrModeImm7<shift,1>); 6715 } 6716 6717 template <int shift> 6718 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6719 uint64_t Address, 6720 const MCDisassembler *Decoder) { 6721 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6722 fieldFromInstruction(Val, 17, 3), 6723 DecodeMQPRRegisterClass, 6724 DecodeMveAddrModeQ<shift>); 6725 } 6726 6727 template <unsigned MinLog, unsigned MaxLog> 6728 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6729 uint64_t Address, 6730 const MCDisassembler *Decoder) { 6731 DecodeStatus S = MCDisassembler::Success; 6732 6733 if (Val < MinLog || Val > MaxLog) 6734 return MCDisassembler::Fail; 6735 6736 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6737 return S; 6738 } 6739 6740 template <unsigned start> 6741 static DecodeStatus 6742 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6743 const MCDisassembler *Decoder) { 6744 DecodeStatus S = MCDisassembler::Success; 6745 6746 Inst.addOperand(MCOperand::createImm(start + Val)); 6747 6748 return S; 6749 } 6750 6751 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6752 uint64_t Address, 6753 const MCDisassembler *Decoder) { 6754 DecodeStatus S = MCDisassembler::Success; 6755 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6756 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6757 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6758 fieldFromInstruction(Insn, 13, 3)); 6759 unsigned index = fieldFromInstruction(Insn, 4, 1); 6760 6761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6762 return MCDisassembler::Fail; 6763 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6764 return MCDisassembler::Fail; 6765 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6766 return MCDisassembler::Fail; 6767 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6768 return MCDisassembler::Fail; 6769 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6770 return MCDisassembler::Fail; 6771 6772 return S; 6773 } 6774 6775 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6776 uint64_t Address, 6777 const MCDisassembler *Decoder) { 6778 DecodeStatus S = MCDisassembler::Success; 6779 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6780 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6781 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6782 fieldFromInstruction(Insn, 13, 3)); 6783 unsigned index = fieldFromInstruction(Insn, 4, 1); 6784 6785 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6786 return MCDisassembler::Fail; 6787 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6788 return MCDisassembler::Fail; 6789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6790 return MCDisassembler::Fail; 6791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6792 return MCDisassembler::Fail; 6793 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6794 return MCDisassembler::Fail; 6795 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6796 return MCDisassembler::Fail; 6797 6798 return S; 6799 } 6800 6801 static DecodeStatus 6802 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 6803 const MCDisassembler *Decoder) { 6804 DecodeStatus S = MCDisassembler::Success; 6805 6806 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6807 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6808 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6809 6810 if (RdaHi == 14) { 6811 // This value of RdaHi (really indicating pc, because RdaHi has to 6812 // be an odd-numbered register, so the low bit will be set by the 6813 // decode function below) indicates that we must decode as SQRSHR 6814 // or UQRSHL, which both have a single Rda register field with all 6815 // four bits. 6816 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6817 6818 switch (Inst.getOpcode()) { 6819 case ARM::MVE_ASRLr: 6820 case ARM::MVE_SQRSHRL: 6821 Inst.setOpcode(ARM::MVE_SQRSHR); 6822 break; 6823 case ARM::MVE_LSLLr: 6824 case ARM::MVE_UQRSHLL: 6825 Inst.setOpcode(ARM::MVE_UQRSHL); 6826 break; 6827 default: 6828 llvm_unreachable("Unexpected starting opcode!"); 6829 } 6830 6831 // Rda as output parameter 6832 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6833 return MCDisassembler::Fail; 6834 6835 // Rda again as input parameter 6836 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6837 return MCDisassembler::Fail; 6838 6839 // Rm, the amount to shift by 6840 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6841 return MCDisassembler::Fail; 6842 6843 if (fieldFromInstruction (Insn, 6, 3) != 4) 6844 return MCDisassembler::SoftFail; 6845 6846 if (Rda == Rm) 6847 return MCDisassembler::SoftFail; 6848 6849 return S; 6850 } 6851 6852 // Otherwise, we decode as whichever opcode our caller has already 6853 // put into Inst. Those all look the same: 6854 6855 // RdaLo,RdaHi as output parameters 6856 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6857 return MCDisassembler::Fail; 6858 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6859 return MCDisassembler::Fail; 6860 6861 // RdaLo,RdaHi again as input parameters 6862 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6863 return MCDisassembler::Fail; 6864 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6865 return MCDisassembler::Fail; 6866 6867 // Rm, the amount to shift by 6868 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6869 return MCDisassembler::Fail; 6870 6871 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6872 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6873 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6874 // Saturate, the bit position for saturation 6875 Inst.addOperand(MCOperand::createImm(Saturate)); 6876 } 6877 6878 return S; 6879 } 6880 6881 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 6882 uint64_t Address, 6883 const MCDisassembler *Decoder) { 6884 DecodeStatus S = MCDisassembler::Success; 6885 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6886 fieldFromInstruction(Insn, 13, 3)); 6887 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6888 fieldFromInstruction(Insn, 1, 3)); 6889 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6890 6891 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6892 return MCDisassembler::Fail; 6893 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6894 return MCDisassembler::Fail; 6895 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6896 return MCDisassembler::Fail; 6897 6898 return S; 6899 } 6900 6901 template <bool scalar, OperandDecoder predicate_decoder> 6902 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6903 const MCDisassembler *Decoder) { 6904 DecodeStatus S = MCDisassembler::Success; 6905 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6906 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6907 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6908 return MCDisassembler::Fail; 6909 6910 unsigned fc; 6911 6912 if (scalar) { 6913 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6914 fieldFromInstruction(Insn, 7, 1) | 6915 fieldFromInstruction(Insn, 5, 1) << 1; 6916 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6917 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6918 return MCDisassembler::Fail; 6919 } else { 6920 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6921 fieldFromInstruction(Insn, 7, 1) | 6922 fieldFromInstruction(Insn, 0, 1) << 1; 6923 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6924 fieldFromInstruction(Insn, 1, 3); 6925 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6926 return MCDisassembler::Fail; 6927 } 6928 6929 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6930 return MCDisassembler::Fail; 6931 6932 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6933 Inst.addOperand(MCOperand::createReg(0)); 6934 Inst.addOperand(MCOperand::createImm(0)); 6935 6936 return S; 6937 } 6938 6939 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6940 const MCDisassembler *Decoder) { 6941 DecodeStatus S = MCDisassembler::Success; 6942 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6943 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6944 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6945 return MCDisassembler::Fail; 6946 return S; 6947 } 6948 6949 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 6950 uint64_t Address, 6951 const MCDisassembler *Decoder) { 6952 DecodeStatus S = MCDisassembler::Success; 6953 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6954 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6955 return S; 6956 } 6957 6958 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6959 uint64_t Address, 6960 const MCDisassembler *Decoder) { 6961 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6962 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6963 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6964 fieldFromInstruction(Insn, 12, 3) << 8 | 6965 fieldFromInstruction(Insn, 0, 8); 6966 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6967 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6968 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 6969 unsigned S = fieldFromInstruction(Insn, 20, 1); 6970 if (sign1 != sign2) 6971 return MCDisassembler::Fail; 6972 6973 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 6974 DecodeStatus DS = MCDisassembler::Success; 6975 if ((!Check(DS, 6976 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 6977 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 6978 return MCDisassembler::Fail; 6979 if (TypeT3) { 6980 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 6981 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 6982 } else { 6983 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 6984 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 6985 return MCDisassembler::Fail; 6986 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 6987 return MCDisassembler::Fail; 6988 } 6989 6990 return DS; 6991 } 6992