1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Pull DecodeStatus and its enum values into the global namespace. 28 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 29 #define Success llvm::MCDisassembler::Success 30 #define Unpredictable llvm::MCDisassembler::SoftFail 31 #define Fail llvm::MCDisassembler::Fail 32 33 // Helper macro to perform setwise reduction of the current running status 34 // and another status, and return if the new status is Fail. 35 #define CHECK(S,X) do { \ 36 S = (DecodeStatus) ((int)S & (X)); \ 37 if (S == Fail) return Fail; \ 38 } while(0) 39 40 // Forward declare these because the autogenerated code will reference them. 41 // Definitions are further down. 42 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 43 uint64_t Address, const void *Decoder); 44 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 45 uint64_t Address, const void *Decoder); 46 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 47 uint64_t Address, const void *Decoder); 48 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 49 uint64_t Address, const void *Decoder); 50 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 51 uint64_t Address, const void *Decoder); 52 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 53 uint64_t Address, const void *Decoder); 54 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 55 uint64_t Address, const void *Decoder); 56 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 57 uint64_t Address, const void *Decoder); 58 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 59 uint64_t Address, const void *Decoder); 60 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 61 uint64_t Address, const void *Decoder); 62 63 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 64 uint64_t Address, const void *Decoder); 65 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 66 uint64_t Address, const void *Decoder); 67 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 68 uint64_t Address, const void *Decoder); 69 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 70 uint64_t Address, const void *Decoder); 71 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 72 uint64_t Address, const void *Decoder); 73 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 74 uint64_t Address, const void *Decoder); 75 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 76 uint64_t Address, const void *Decoder); 77 78 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 79 uint64_t Address, const void *Decoder); 80 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 81 uint64_t Address, const void *Decoder); 82 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 83 uint64_t Address, const void *Decoder); 84 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 89 uint64_t Address, const void *Decoder); 90 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 91 uint64_t Address, const void *Decoder); 92 93 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 94 unsigned Insn, 95 uint64_t Adddress, 96 const void *Decoder); 97 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 98 uint64_t Address, const void *Decoder); 99 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 100 uint64_t Address, const void *Decoder); 101 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 102 uint64_t Address, const void *Decoder); 103 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 104 uint64_t Address, const void *Decoder); 105 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 106 uint64_t Address, const void *Decoder); 107 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 108 uint64_t Address, const void *Decoder); 109 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 110 uint64_t Address, const void *Decoder); 111 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 112 uint64_t Address, const void *Decoder); 113 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 116 uint64_t Address, const void *Decoder); 117 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 118 uint64_t Address, const void *Decoder); 119 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 120 uint64_t Address, const void *Decoder); 121 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 122 uint64_t Address, const void *Decoder); 123 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 124 uint64_t Address, const void *Decoder); 125 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 126 uint64_t Address, const void *Decoder); 127 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 128 uint64_t Address, const void *Decoder); 129 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 130 uint64_t Address, const void *Decoder); 131 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 132 uint64_t Address, const void *Decoder); 133 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 134 uint64_t Address, const void *Decoder); 135 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 136 uint64_t Address, const void *Decoder); 137 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 138 uint64_t Address, const void *Decoder); 139 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 140 uint64_t Address, const void *Decoder); 141 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 142 uint64_t Address, const void *Decoder); 143 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 144 uint64_t Address, const void *Decoder); 145 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 146 uint64_t Address, const void *Decoder); 147 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 148 uint64_t Address, const void *Decoder); 149 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 150 uint64_t Address, const void *Decoder); 151 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 164 uint64_t Address, const void *Decoder); 165 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 166 uint64_t Address, const void *Decoder); 167 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 172 uint64_t Address, const void *Decoder); 173 174 175 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 194 uint64_t Address, const void *Decoder); 195 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 196 uint64_t Address, const void *Decoder); 197 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 220 uint64_t Address, const void *Decoder); 221 222 #include "ARMGenDisassemblerTables.inc" 223 #include "ARMGenInstrInfo.inc" 224 #include "ARMGenEDInfo.inc" 225 226 using namespace llvm; 227 228 static MCDisassembler *createARMDisassembler(const Target &T) { 229 return new ARMDisassembler; 230 } 231 232 static MCDisassembler *createThumbDisassembler(const Target &T) { 233 return new ThumbDisassembler; 234 } 235 236 EDInstInfo *ARMDisassembler::getEDInfo() const { 237 return instInfoARM; 238 } 239 240 EDInstInfo *ThumbDisassembler::getEDInfo() const { 241 return instInfoARM; 242 } 243 244 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 245 const MemoryObject &Region, 246 uint64_t Address,raw_ostream &os) const { 247 uint8_t bytes[4]; 248 249 // We want to read exactly 4 bytes of data. 250 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 251 return Fail; 252 253 // Encoded as a small-endian 32-bit word in the stream. 254 uint32_t insn = (bytes[3] << 24) | 255 (bytes[2] << 16) | 256 (bytes[1] << 8) | 257 (bytes[0] << 0); 258 259 // Calling the auto-generated decoder function. 260 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this); 261 if (result != Fail) { 262 Size = 4; 263 return result; 264 } 265 266 // Instructions that are shared between ARM and Thumb modes. 267 // FIXME: This shouldn't really exist. It's an artifact of the 268 // fact that we fail to encode a few instructions properly for Thumb. 269 MI.clear(); 270 result = decodeCommonInstruction32(MI, insn, Address, this); 271 if (result != Fail) { 272 Size = 4; 273 return result; 274 } 275 276 // VFP and NEON instructions, similarly, are shared between ARM 277 // and Thumb modes. 278 MI.clear(); 279 result = decodeVFPInstruction32(MI, insn, Address, this); 280 if (result != Fail) { 281 Size = 4; 282 return result; 283 } 284 285 MI.clear(); 286 result = decodeNEONDataInstruction32(MI, insn, Address, this); 287 if (result != Fail) { 288 Size = 4; 289 // Add a fake predicate operand, because we share these instruction 290 // definitions with Thumb2 where these instructions are predicable. 291 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 292 return result; 293 } 294 295 MI.clear(); 296 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 297 if (result != Fail) { 298 Size = 4; 299 // Add a fake predicate operand, because we share these instruction 300 // definitions with Thumb2 where these instructions are predicable. 301 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 302 return result; 303 } 304 305 MI.clear(); 306 result = decodeNEONDupInstruction32(MI, insn, Address, this); 307 if (result != Fail) { 308 Size = 4; 309 // Add a fake predicate operand, because we share these instruction 310 // definitions with Thumb2 where these instructions are predicable. 311 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail; 312 return result; 313 } 314 315 MI.clear(); 316 317 return Fail; 318 } 319 320 namespace llvm { 321 extern MCInstrDesc ARMInsts[]; 322 } 323 324 // Thumb1 instructions don't have explicit S bits. Rather, they 325 // implicitly set CPSR. Since it's not represented in the encoding, the 326 // auto-generated decoder won't inject the CPSR operand. We need to fix 327 // that as a post-pass. 328 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 329 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 330 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 331 MCInst::iterator I = MI.begin(); 332 for (unsigned i = 0; i < NumOps; ++i, ++I) { 333 if (I == MI.end()) break; 334 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 335 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 336 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 337 return; 338 } 339 } 340 341 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 342 } 343 344 // Most Thumb instructions don't have explicit predicates in the 345 // encoding, but rather get their predicates from IT context. We need 346 // to fix up the predicate operands using this context information as a 347 // post-pass. 348 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 349 // A few instructions actually have predicates encoded in them. Don't 350 // try to overwrite it if we're seeing one of those. 351 switch (MI.getOpcode()) { 352 case ARM::tBcc: 353 case ARM::t2Bcc: 354 return; 355 default: 356 break; 357 } 358 359 // If we're in an IT block, base the predicate on that. Otherwise, 360 // assume a predicate of AL. 361 unsigned CC; 362 if (!ITBlock.empty()) { 363 CC = ITBlock.back(); 364 ITBlock.pop_back(); 365 } else 366 CC = ARMCC::AL; 367 368 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 369 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 370 MCInst::iterator I = MI.begin(); 371 for (unsigned i = 0; i < NumOps; ++i, ++I) { 372 if (I == MI.end()) break; 373 if (OpInfo[i].isPredicate()) { 374 I = MI.insert(I, MCOperand::CreateImm(CC)); 375 ++I; 376 if (CC == ARMCC::AL) 377 MI.insert(I, MCOperand::CreateReg(0)); 378 else 379 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 380 return; 381 } 382 } 383 384 I = MI.insert(I, MCOperand::CreateImm(CC)); 385 ++I; 386 if (CC == ARMCC::AL) 387 MI.insert(I, MCOperand::CreateReg(0)); 388 else 389 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 390 } 391 392 // Thumb VFP instructions are a special case. Because we share their 393 // encodings between ARM and Thumb modes, and they are predicable in ARM 394 // mode, the auto-generated decoder will give them an (incorrect) 395 // predicate operand. We need to rewrite these operands based on the IT 396 // context as a post-pass. 397 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 398 unsigned CC; 399 if (!ITBlock.empty()) { 400 CC = ITBlock.back(); 401 ITBlock.pop_back(); 402 } else 403 CC = ARMCC::AL; 404 405 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 406 MCInst::iterator I = MI.begin(); 407 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 408 if (OpInfo[i].isPredicate() ) { 409 I->setImm(CC); 410 ++I; 411 if (CC == ARMCC::AL) 412 I->setReg(0); 413 else 414 I->setReg(ARM::CPSR); 415 return; 416 } 417 } 418 } 419 420 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 421 const MemoryObject &Region, 422 uint64_t Address,raw_ostream &os) const { 423 uint8_t bytes[4]; 424 425 // We want to read exactly 2 bytes of data. 426 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 427 return Fail; 428 429 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 430 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this); 431 if (result != Fail) { 432 Size = 2; 433 AddThumbPredicate(MI); 434 return result; 435 } 436 437 MI.clear(); 438 result = decodeThumbSBitInstruction16(MI, insn16, Address, this); 439 if (result) { 440 Size = 2; 441 bool InITBlock = !ITBlock.empty(); 442 AddThumbPredicate(MI); 443 AddThumb1SBit(MI, InITBlock); 444 return result; 445 } 446 447 MI.clear(); 448 result = decodeThumb2Instruction16(MI, insn16, Address, this); 449 if (result != Fail) { 450 Size = 2; 451 AddThumbPredicate(MI); 452 453 // If we find an IT instruction, we need to parse its condition 454 // code and mask operands so that we can apply them correctly 455 // to the subsequent instructions. 456 if (MI.getOpcode() == ARM::t2IT) { 457 unsigned firstcond = MI.getOperand(0).getImm(); 458 uint32_t mask = MI.getOperand(1).getImm(); 459 unsigned zeros = CountTrailingZeros_32(mask); 460 mask >>= zeros+1; 461 462 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 463 if (firstcond ^ (mask & 1)) 464 ITBlock.push_back(firstcond ^ 1); 465 else 466 ITBlock.push_back(firstcond); 467 mask >>= 1; 468 } 469 ITBlock.push_back(firstcond); 470 } 471 472 return result; 473 } 474 475 // We want to read exactly 4 bytes of data. 476 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 477 return Fail; 478 479 uint32_t insn32 = (bytes[3] << 8) | 480 (bytes[2] << 0) | 481 (bytes[1] << 24) | 482 (bytes[0] << 16); 483 MI.clear(); 484 result = decodeThumbInstruction32(MI, insn32, Address, this); 485 if (result != Fail) { 486 Size = 4; 487 bool InITBlock = ITBlock.size(); 488 AddThumbPredicate(MI); 489 AddThumb1SBit(MI, InITBlock); 490 return result; 491 } 492 493 MI.clear(); 494 result = decodeThumb2Instruction32(MI, insn32, Address, this); 495 if (result != Fail) { 496 Size = 4; 497 AddThumbPredicate(MI); 498 return result; 499 } 500 501 MI.clear(); 502 result = decodeCommonInstruction32(MI, insn32, Address, this); 503 if (result != Fail) { 504 Size = 4; 505 AddThumbPredicate(MI); 506 return result; 507 } 508 509 MI.clear(); 510 result = decodeVFPInstruction32(MI, insn32, Address, this); 511 if (result != Fail) { 512 Size = 4; 513 UpdateThumbVFPPredicate(MI); 514 return result; 515 } 516 517 MI.clear(); 518 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 519 if (result != Fail) { 520 Size = 4; 521 AddThumbPredicate(MI); 522 return result; 523 } 524 525 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) { 526 MI.clear(); 527 uint32_t NEONLdStInsn = insn32; 528 NEONLdStInsn &= 0xF0FFFFFF; 529 NEONLdStInsn |= 0x04000000; 530 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this); 531 if (result != Fail) { 532 Size = 4; 533 AddThumbPredicate(MI); 534 return result; 535 } 536 } 537 538 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 539 MI.clear(); 540 uint32_t NEONDataInsn = insn32; 541 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 542 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 543 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 544 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 545 if (result != Fail) { 546 Size = 4; 547 AddThumbPredicate(MI); 548 return result; 549 } 550 } 551 552 return Fail; 553 } 554 555 556 extern "C" void LLVMInitializeARMDisassembler() { 557 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 558 createARMDisassembler); 559 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 560 createThumbDisassembler); 561 } 562 563 static const unsigned GPRDecoderTable[] = { 564 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 565 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 566 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 567 ARM::R12, ARM::SP, ARM::LR, ARM::PC 568 }; 569 570 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 571 uint64_t Address, const void *Decoder) { 572 if (RegNo > 15) 573 return Fail; 574 575 unsigned Register = GPRDecoderTable[RegNo]; 576 Inst.addOperand(MCOperand::CreateReg(Register)); 577 return Success; 578 } 579 580 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 581 uint64_t Address, const void *Decoder) { 582 if (RegNo == 15) return Fail; 583 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 584 } 585 586 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 587 uint64_t Address, const void *Decoder) { 588 if (RegNo > 7) 589 return Fail; 590 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 591 } 592 593 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 594 uint64_t Address, const void *Decoder) { 595 unsigned Register = 0; 596 switch (RegNo) { 597 case 0: 598 Register = ARM::R0; 599 break; 600 case 1: 601 Register = ARM::R1; 602 break; 603 case 2: 604 Register = ARM::R2; 605 break; 606 case 3: 607 Register = ARM::R3; 608 break; 609 case 9: 610 Register = ARM::R9; 611 break; 612 case 12: 613 Register = ARM::R12; 614 break; 615 default: 616 return Fail; 617 } 618 619 Inst.addOperand(MCOperand::CreateReg(Register)); 620 return Success; 621 } 622 623 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 624 uint64_t Address, const void *Decoder) { 625 if (RegNo == 13 || RegNo == 15) return Fail; 626 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 627 } 628 629 static const unsigned SPRDecoderTable[] = { 630 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 631 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 632 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 633 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 634 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 635 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 636 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 637 ARM::S28, ARM::S29, ARM::S30, ARM::S31 638 }; 639 640 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 641 uint64_t Address, const void *Decoder) { 642 if (RegNo > 31) 643 return Fail; 644 645 unsigned Register = SPRDecoderTable[RegNo]; 646 Inst.addOperand(MCOperand::CreateReg(Register)); 647 return Success; 648 } 649 650 static const unsigned DPRDecoderTable[] = { 651 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 652 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 653 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 654 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 655 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 656 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 657 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 658 ARM::D28, ARM::D29, ARM::D30, ARM::D31 659 }; 660 661 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 662 uint64_t Address, const void *Decoder) { 663 if (RegNo > 31) 664 return Fail; 665 666 unsigned Register = DPRDecoderTable[RegNo]; 667 Inst.addOperand(MCOperand::CreateReg(Register)); 668 return Success; 669 } 670 671 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 672 uint64_t Address, const void *Decoder) { 673 if (RegNo > 7) 674 return Fail; 675 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 676 } 677 678 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 679 uint64_t Address, const void *Decoder) { 680 if (RegNo > 15) 681 return Fail; 682 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 683 } 684 685 static const unsigned QPRDecoderTable[] = { 686 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 687 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 688 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 689 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 690 }; 691 692 693 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 694 uint64_t Address, const void *Decoder) { 695 if (RegNo > 31) 696 return Fail; 697 RegNo >>= 1; 698 699 unsigned Register = QPRDecoderTable[RegNo]; 700 Inst.addOperand(MCOperand::CreateReg(Register)); 701 return Success; 702 } 703 704 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 705 uint64_t Address, const void *Decoder) { 706 if (Val == 0xF) return Fail; 707 // AL predicate is not allowed on Thumb1 branches. 708 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 709 return Fail; 710 Inst.addOperand(MCOperand::CreateImm(Val)); 711 if (Val == ARMCC::AL) { 712 Inst.addOperand(MCOperand::CreateReg(0)); 713 } else 714 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 715 return Success; 716 } 717 718 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 719 uint64_t Address, const void *Decoder) { 720 if (Val) 721 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 722 else 723 Inst.addOperand(MCOperand::CreateReg(0)); 724 return Success; 725 } 726 727 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 728 uint64_t Address, const void *Decoder) { 729 uint32_t imm = Val & 0xFF; 730 uint32_t rot = (Val & 0xF00) >> 7; 731 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 732 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 733 return Success; 734 } 735 736 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 737 uint64_t Address, const void *Decoder) { 738 Val <<= 2; 739 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 740 return Success; 741 } 742 743 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 744 uint64_t Address, const void *Decoder) { 745 DecodeStatus S = Success; 746 747 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 748 unsigned type = fieldFromInstruction32(Val, 5, 2); 749 unsigned imm = fieldFromInstruction32(Val, 7, 5); 750 751 // Register-immediate 752 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 753 754 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 755 switch (type) { 756 case 0: 757 Shift = ARM_AM::lsl; 758 break; 759 case 1: 760 Shift = ARM_AM::lsr; 761 break; 762 case 2: 763 Shift = ARM_AM::asr; 764 break; 765 case 3: 766 Shift = ARM_AM::ror; 767 break; 768 } 769 770 if (Shift == ARM_AM::ror && imm == 0) 771 Shift = ARM_AM::rrx; 772 773 unsigned Op = Shift | (imm << 3); 774 Inst.addOperand(MCOperand::CreateImm(Op)); 775 776 return S; 777 } 778 779 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 780 uint64_t Address, const void *Decoder) { 781 DecodeStatus S = Success; 782 783 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 784 unsigned type = fieldFromInstruction32(Val, 5, 2); 785 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 786 787 // Register-register 788 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 789 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)); 790 791 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 792 switch (type) { 793 case 0: 794 Shift = ARM_AM::lsl; 795 break; 796 case 1: 797 Shift = ARM_AM::lsr; 798 break; 799 case 2: 800 Shift = ARM_AM::asr; 801 break; 802 case 3: 803 Shift = ARM_AM::ror; 804 break; 805 } 806 807 Inst.addOperand(MCOperand::CreateImm(Shift)); 808 809 return S; 810 } 811 812 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 813 uint64_t Address, const void *Decoder) { 814 DecodeStatus S = Success; 815 816 // Empty register lists are not allowed. 817 if (CountPopulation_32(Val) == 0) return Fail; 818 for (unsigned i = 0; i < 16; ++i) { 819 if (Val & (1 << i)) { 820 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)); 821 } 822 } 823 824 return S; 825 } 826 827 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 828 uint64_t Address, const void *Decoder) { 829 DecodeStatus S = Success; 830 831 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 832 unsigned regs = Val & 0xFF; 833 834 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)); 835 for (unsigned i = 0; i < (regs - 1); ++i) { 836 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)); 837 } 838 839 return S; 840 } 841 842 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 843 uint64_t Address, const void *Decoder) { 844 DecodeStatus S = Success; 845 846 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 847 unsigned regs = (Val & 0xFF) / 2; 848 849 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)); 850 for (unsigned i = 0; i < (regs - 1); ++i) { 851 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)); 852 } 853 854 return S; 855 } 856 857 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 858 uint64_t Address, const void *Decoder) { 859 // This operand encodes a mask of contiguous zeros between a specified MSB 860 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 861 // the mask of all bits LSB-and-lower, and then xor them to create 862 // the mask of that's all ones on [msb, lsb]. Finally we not it to 863 // create the final mask. 864 unsigned msb = fieldFromInstruction32(Val, 5, 5); 865 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 866 uint32_t msb_mask = (1 << (msb+1)) - 1; 867 uint32_t lsb_mask = (1 << lsb) - 1; 868 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 869 return Success; 870 } 871 872 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 873 uint64_t Address, const void *Decoder) { 874 DecodeStatus S = Success; 875 876 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 877 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 878 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 879 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 880 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 881 unsigned U = fieldFromInstruction32(Insn, 23, 1); 882 883 switch (Inst.getOpcode()) { 884 case ARM::LDC_OFFSET: 885 case ARM::LDC_PRE: 886 case ARM::LDC_POST: 887 case ARM::LDC_OPTION: 888 case ARM::LDCL_OFFSET: 889 case ARM::LDCL_PRE: 890 case ARM::LDCL_POST: 891 case ARM::LDCL_OPTION: 892 case ARM::STC_OFFSET: 893 case ARM::STC_PRE: 894 case ARM::STC_POST: 895 case ARM::STC_OPTION: 896 case ARM::STCL_OFFSET: 897 case ARM::STCL_PRE: 898 case ARM::STCL_POST: 899 case ARM::STCL_OPTION: 900 if (coproc == 0xA || coproc == 0xB) 901 return Fail; 902 break; 903 default: 904 break; 905 } 906 907 Inst.addOperand(MCOperand::CreateImm(coproc)); 908 Inst.addOperand(MCOperand::CreateImm(CRd)); 909 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 910 switch (Inst.getOpcode()) { 911 case ARM::LDC_OPTION: 912 case ARM::LDCL_OPTION: 913 case ARM::LDC2_OPTION: 914 case ARM::LDC2L_OPTION: 915 case ARM::STC_OPTION: 916 case ARM::STCL_OPTION: 917 case ARM::STC2_OPTION: 918 case ARM::STC2L_OPTION: 919 case ARM::LDCL_POST: 920 case ARM::STCL_POST: 921 break; 922 default: 923 Inst.addOperand(MCOperand::CreateReg(0)); 924 break; 925 } 926 927 unsigned P = fieldFromInstruction32(Insn, 24, 1); 928 unsigned W = fieldFromInstruction32(Insn, 21, 1); 929 930 bool writeback = (P == 0) || (W == 1); 931 unsigned idx_mode = 0; 932 if (P && writeback) 933 idx_mode = ARMII::IndexModePre; 934 else if (!P && writeback) 935 idx_mode = ARMII::IndexModePost; 936 937 switch (Inst.getOpcode()) { 938 case ARM::LDCL_POST: 939 case ARM::STCL_POST: 940 imm |= U << 8; 941 case ARM::LDC_OPTION: 942 case ARM::LDCL_OPTION: 943 case ARM::LDC2_OPTION: 944 case ARM::LDC2L_OPTION: 945 case ARM::STC_OPTION: 946 case ARM::STCL_OPTION: 947 case ARM::STC2_OPTION: 948 case ARM::STC2L_OPTION: 949 Inst.addOperand(MCOperand::CreateImm(imm)); 950 break; 951 default: 952 if (U) 953 Inst.addOperand(MCOperand::CreateImm( 954 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 955 else 956 Inst.addOperand(MCOperand::CreateImm( 957 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 958 break; 959 } 960 961 switch (Inst.getOpcode()) { 962 case ARM::LDC_OFFSET: 963 case ARM::LDC_PRE: 964 case ARM::LDC_POST: 965 case ARM::LDC_OPTION: 966 case ARM::LDCL_OFFSET: 967 case ARM::LDCL_PRE: 968 case ARM::LDCL_POST: 969 case ARM::LDCL_OPTION: 970 case ARM::STC_OFFSET: 971 case ARM::STC_PRE: 972 case ARM::STC_POST: 973 case ARM::STC_OPTION: 974 case ARM::STCL_OFFSET: 975 case ARM::STCL_PRE: 976 case ARM::STCL_POST: 977 case ARM::STCL_OPTION: 978 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 979 break; 980 default: 981 break; 982 } 983 984 return S; 985 } 986 987 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 988 uint64_t Address, const void *Decoder) { 989 DecodeStatus S = Success; 990 991 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 992 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 993 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 994 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 995 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 996 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 997 unsigned P = fieldFromInstruction32(Insn, 24, 1); 998 unsigned W = fieldFromInstruction32(Insn, 21, 1); 999 1000 // On stores, the writeback operand precedes Rt. 1001 switch (Inst.getOpcode()) { 1002 case ARM::STR_POST_IMM: 1003 case ARM::STR_POST_REG: 1004 case ARM::STRB_POST_IMM: 1005 case ARM::STRB_POST_REG: 1006 case ARM::STRT_POST_REG: 1007 case ARM::STRT_POST_IMM: 1008 case ARM::STRBT_POST_REG: 1009 case ARM::STRBT_POST_IMM: 1010 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1011 break; 1012 default: 1013 break; 1014 } 1015 1016 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1017 1018 // On loads, the writeback operand comes after Rt. 1019 switch (Inst.getOpcode()) { 1020 case ARM::LDR_POST_IMM: 1021 case ARM::LDR_POST_REG: 1022 case ARM::LDRB_POST_IMM: 1023 case ARM::LDRB_POST_REG: 1024 case ARM::LDR_PRE: 1025 case ARM::LDRB_PRE: 1026 case ARM::LDRBT_POST_REG: 1027 case ARM::LDRBT_POST_IMM: 1028 case ARM::LDRT_POST_REG: 1029 case ARM::LDRT_POST_IMM: 1030 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1031 break; 1032 default: 1033 break; 1034 } 1035 1036 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1037 1038 ARM_AM::AddrOpc Op = ARM_AM::add; 1039 if (!fieldFromInstruction32(Insn, 23, 1)) 1040 Op = ARM_AM::sub; 1041 1042 bool writeback = (P == 0) || (W == 1); 1043 unsigned idx_mode = 0; 1044 if (P && writeback) 1045 idx_mode = ARMII::IndexModePre; 1046 else if (!P && writeback) 1047 idx_mode = ARMII::IndexModePost; 1048 1049 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE 1050 1051 if (reg) { 1052 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1053 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1054 switch( fieldFromInstruction32(Insn, 5, 2)) { 1055 case 0: 1056 Opc = ARM_AM::lsl; 1057 break; 1058 case 1: 1059 Opc = ARM_AM::lsr; 1060 break; 1061 case 2: 1062 Opc = ARM_AM::asr; 1063 break; 1064 case 3: 1065 Opc = ARM_AM::ror; 1066 break; 1067 default: 1068 return Fail; 1069 } 1070 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1071 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1072 1073 Inst.addOperand(MCOperand::CreateImm(imm)); 1074 } else { 1075 Inst.addOperand(MCOperand::CreateReg(0)); 1076 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1077 Inst.addOperand(MCOperand::CreateImm(tmp)); 1078 } 1079 1080 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1081 1082 return S; 1083 } 1084 1085 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1086 uint64_t Address, const void *Decoder) { 1087 DecodeStatus S = Success; 1088 1089 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1090 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1091 unsigned type = fieldFromInstruction32(Val, 5, 2); 1092 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1093 unsigned U = fieldFromInstruction32(Val, 12, 1); 1094 1095 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1096 switch (type) { 1097 case 0: 1098 ShOp = ARM_AM::lsl; 1099 break; 1100 case 1: 1101 ShOp = ARM_AM::lsr; 1102 break; 1103 case 2: 1104 ShOp = ARM_AM::asr; 1105 break; 1106 case 3: 1107 ShOp = ARM_AM::ror; 1108 break; 1109 } 1110 1111 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1112 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1113 unsigned shift; 1114 if (U) 1115 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1116 else 1117 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1118 Inst.addOperand(MCOperand::CreateImm(shift)); 1119 1120 return S; 1121 } 1122 1123 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1124 uint64_t Address, const void *Decoder) { 1125 DecodeStatus S = Success; 1126 1127 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1128 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1129 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1130 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1131 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1132 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1133 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1134 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1135 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1136 1137 bool writeback = (W == 1) | (P == 0); 1138 1139 // For {LD,ST}RD, Rt must be even, else undefined. 1140 switch (Inst.getOpcode()) { 1141 case ARM::STRD: 1142 case ARM::STRD_PRE: 1143 case ARM::STRD_POST: 1144 case ARM::LDRD: 1145 case ARM::LDRD_PRE: 1146 case ARM::LDRD_POST: 1147 if (Rt & 0x1) return Fail; 1148 break; 1149 default: 1150 break; 1151 } 1152 1153 if (writeback) { // Writeback 1154 if (P) 1155 U |= ARMII::IndexModePre << 9; 1156 else 1157 U |= ARMII::IndexModePost << 9; 1158 1159 // On stores, the writeback operand precedes Rt. 1160 switch (Inst.getOpcode()) { 1161 case ARM::STRD: 1162 case ARM::STRD_PRE: 1163 case ARM::STRD_POST: 1164 case ARM::STRH: 1165 case ARM::STRH_PRE: 1166 case ARM::STRH_POST: 1167 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1168 break; 1169 default: 1170 break; 1171 } 1172 } 1173 1174 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 1175 switch (Inst.getOpcode()) { 1176 case ARM::STRD: 1177 case ARM::STRD_PRE: 1178 case ARM::STRD_POST: 1179 case ARM::LDRD: 1180 case ARM::LDRD_PRE: 1181 case ARM::LDRD_POST: 1182 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 1183 break; 1184 default: 1185 break; 1186 } 1187 1188 if (writeback) { 1189 // On loads, the writeback operand comes after Rt. 1190 switch (Inst.getOpcode()) { 1191 case ARM::LDRD: 1192 case ARM::LDRD_PRE: 1193 case ARM::LDRD_POST: 1194 case ARM::LDRH: 1195 case ARM::LDRH_PRE: 1196 case ARM::LDRH_POST: 1197 case ARM::LDRSH: 1198 case ARM::LDRSH_PRE: 1199 case ARM::LDRSH_POST: 1200 case ARM::LDRSB: 1201 case ARM::LDRSB_PRE: 1202 case ARM::LDRSB_POST: 1203 case ARM::LDRHTr: 1204 case ARM::LDRSBTr: 1205 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1206 break; 1207 default: 1208 break; 1209 } 1210 } 1211 1212 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1213 1214 if (type) { 1215 Inst.addOperand(MCOperand::CreateReg(0)); 1216 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1217 } else { 1218 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1219 Inst.addOperand(MCOperand::CreateImm(U)); 1220 } 1221 1222 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1223 1224 return S; 1225 } 1226 1227 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1228 uint64_t Address, const void *Decoder) { 1229 DecodeStatus S = Success; 1230 1231 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1232 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1233 1234 switch (mode) { 1235 case 0: 1236 mode = ARM_AM::da; 1237 break; 1238 case 1: 1239 mode = ARM_AM::ia; 1240 break; 1241 case 2: 1242 mode = ARM_AM::db; 1243 break; 1244 case 3: 1245 mode = ARM_AM::ib; 1246 break; 1247 } 1248 1249 Inst.addOperand(MCOperand::CreateImm(mode)); 1250 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1251 1252 return S; 1253 } 1254 1255 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1256 unsigned Insn, 1257 uint64_t Address, const void *Decoder) { 1258 DecodeStatus S = Success; 1259 1260 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1261 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1262 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1263 1264 if (pred == 0xF) { 1265 switch (Inst.getOpcode()) { 1266 case ARM::STMDA: 1267 Inst.setOpcode(ARM::RFEDA); 1268 break; 1269 case ARM::STMDA_UPD: 1270 Inst.setOpcode(ARM::RFEDA_UPD); 1271 break; 1272 case ARM::STMDB: 1273 Inst.setOpcode(ARM::RFEDB); 1274 break; 1275 case ARM::STMDB_UPD: 1276 Inst.setOpcode(ARM::RFEDB_UPD); 1277 break; 1278 case ARM::STMIA: 1279 Inst.setOpcode(ARM::RFEIA); 1280 break; 1281 case ARM::STMIA_UPD: 1282 Inst.setOpcode(ARM::RFEIA_UPD); 1283 break; 1284 case ARM::STMIB: 1285 Inst.setOpcode(ARM::RFEIB); 1286 break; 1287 case ARM::STMIB_UPD: 1288 Inst.setOpcode(ARM::RFEIB_UPD); 1289 break; 1290 } 1291 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1292 } 1293 1294 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1295 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied 1296 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1297 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)); 1298 1299 return S; 1300 } 1301 1302 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1303 uint64_t Address, const void *Decoder) { 1304 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1305 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1306 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1307 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1308 1309 // imod == '01' --> UNPREDICTABLE 1310 if (imod == 1) return Fail; 1311 1312 if (M && mode && imod && iflags) { 1313 Inst.setOpcode(ARM::CPS3p); 1314 Inst.addOperand(MCOperand::CreateImm(imod)); 1315 Inst.addOperand(MCOperand::CreateImm(iflags)); 1316 Inst.addOperand(MCOperand::CreateImm(mode)); 1317 return Success; 1318 } else if (!mode && !M) { 1319 Inst.setOpcode(ARM::CPS2p); 1320 Inst.addOperand(MCOperand::CreateImm(imod)); 1321 Inst.addOperand(MCOperand::CreateImm(iflags)); 1322 return Success; 1323 } else if (!imod && !iflags && M) { 1324 Inst.setOpcode(ARM::CPS1p); 1325 Inst.addOperand(MCOperand::CreateImm(mode)); 1326 return Success; 1327 } 1328 1329 return Fail; 1330 } 1331 1332 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1333 uint64_t Address, const void *Decoder) { 1334 DecodeStatus S = Success; 1335 1336 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1337 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1338 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1339 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1340 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1341 1342 if (pred == 0xF) 1343 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1344 1345 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)); 1346 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)); 1347 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)); 1348 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)); 1349 1350 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1351 1352 return S; 1353 } 1354 1355 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1356 uint64_t Address, const void *Decoder) { 1357 DecodeStatus S = Success; 1358 1359 unsigned add = fieldFromInstruction32(Val, 12, 1); 1360 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1361 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1362 1363 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1364 1365 if (!add) imm *= -1; 1366 if (imm == 0 && !add) imm = INT32_MIN; 1367 Inst.addOperand(MCOperand::CreateImm(imm)); 1368 1369 return S; 1370 } 1371 1372 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1373 uint64_t Address, const void *Decoder) { 1374 DecodeStatus S = Success; 1375 1376 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1377 unsigned U = fieldFromInstruction32(Val, 8, 1); 1378 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1379 1380 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1381 1382 if (U) 1383 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1384 else 1385 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1386 1387 return S; 1388 } 1389 1390 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1391 uint64_t Address, const void *Decoder) { 1392 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1393 } 1394 1395 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1396 uint64_t Address, const void *Decoder) { 1397 DecodeStatus S = Success; 1398 1399 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1400 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1401 1402 if (pred == 0xF) { 1403 Inst.setOpcode(ARM::BLXi); 1404 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1405 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1406 return S; 1407 } 1408 1409 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1410 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 1411 1412 return S; 1413 } 1414 1415 1416 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1417 uint64_t Address, const void *Decoder) { 1418 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1419 return Success; 1420 } 1421 1422 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1423 uint64_t Address, const void *Decoder) { 1424 DecodeStatus S = Success; 1425 1426 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1427 unsigned align = fieldFromInstruction32(Val, 4, 2); 1428 1429 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1430 if (!align) 1431 Inst.addOperand(MCOperand::CreateImm(0)); 1432 else 1433 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1434 1435 return S; 1436 } 1437 1438 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1439 uint64_t Address, const void *Decoder) { 1440 DecodeStatus S = Success; 1441 1442 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1443 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1444 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1445 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1446 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1447 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1448 1449 // First output register 1450 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1451 1452 // Second output register 1453 switch (Inst.getOpcode()) { 1454 case ARM::VLD1q8: 1455 case ARM::VLD1q16: 1456 case ARM::VLD1q32: 1457 case ARM::VLD1q64: 1458 case ARM::VLD1q8_UPD: 1459 case ARM::VLD1q16_UPD: 1460 case ARM::VLD1q32_UPD: 1461 case ARM::VLD1q64_UPD: 1462 case ARM::VLD1d8T: 1463 case ARM::VLD1d16T: 1464 case ARM::VLD1d32T: 1465 case ARM::VLD1d64T: 1466 case ARM::VLD1d8T_UPD: 1467 case ARM::VLD1d16T_UPD: 1468 case ARM::VLD1d32T_UPD: 1469 case ARM::VLD1d64T_UPD: 1470 case ARM::VLD1d8Q: 1471 case ARM::VLD1d16Q: 1472 case ARM::VLD1d32Q: 1473 case ARM::VLD1d64Q: 1474 case ARM::VLD1d8Q_UPD: 1475 case ARM::VLD1d16Q_UPD: 1476 case ARM::VLD1d32Q_UPD: 1477 case ARM::VLD1d64Q_UPD: 1478 case ARM::VLD2d8: 1479 case ARM::VLD2d16: 1480 case ARM::VLD2d32: 1481 case ARM::VLD2d8_UPD: 1482 case ARM::VLD2d16_UPD: 1483 case ARM::VLD2d32_UPD: 1484 case ARM::VLD2q8: 1485 case ARM::VLD2q16: 1486 case ARM::VLD2q32: 1487 case ARM::VLD2q8_UPD: 1488 case ARM::VLD2q16_UPD: 1489 case ARM::VLD2q32_UPD: 1490 case ARM::VLD3d8: 1491 case ARM::VLD3d16: 1492 case ARM::VLD3d32: 1493 case ARM::VLD3d8_UPD: 1494 case ARM::VLD3d16_UPD: 1495 case ARM::VLD3d32_UPD: 1496 case ARM::VLD4d8: 1497 case ARM::VLD4d16: 1498 case ARM::VLD4d32: 1499 case ARM::VLD4d8_UPD: 1500 case ARM::VLD4d16_UPD: 1501 case ARM::VLD4d32_UPD: 1502 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1503 break; 1504 case ARM::VLD2b8: 1505 case ARM::VLD2b16: 1506 case ARM::VLD2b32: 1507 case ARM::VLD2b8_UPD: 1508 case ARM::VLD2b16_UPD: 1509 case ARM::VLD2b32_UPD: 1510 case ARM::VLD3q8: 1511 case ARM::VLD3q16: 1512 case ARM::VLD3q32: 1513 case ARM::VLD3q8_UPD: 1514 case ARM::VLD3q16_UPD: 1515 case ARM::VLD3q32_UPD: 1516 case ARM::VLD4q8: 1517 case ARM::VLD4q16: 1518 case ARM::VLD4q32: 1519 case ARM::VLD4q8_UPD: 1520 case ARM::VLD4q16_UPD: 1521 case ARM::VLD4q32_UPD: 1522 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1523 default: 1524 break; 1525 } 1526 1527 // Third output register 1528 switch(Inst.getOpcode()) { 1529 case ARM::VLD1d8T: 1530 case ARM::VLD1d16T: 1531 case ARM::VLD1d32T: 1532 case ARM::VLD1d64T: 1533 case ARM::VLD1d8T_UPD: 1534 case ARM::VLD1d16T_UPD: 1535 case ARM::VLD1d32T_UPD: 1536 case ARM::VLD1d64T_UPD: 1537 case ARM::VLD1d8Q: 1538 case ARM::VLD1d16Q: 1539 case ARM::VLD1d32Q: 1540 case ARM::VLD1d64Q: 1541 case ARM::VLD1d8Q_UPD: 1542 case ARM::VLD1d16Q_UPD: 1543 case ARM::VLD1d32Q_UPD: 1544 case ARM::VLD1d64Q_UPD: 1545 case ARM::VLD2q8: 1546 case ARM::VLD2q16: 1547 case ARM::VLD2q32: 1548 case ARM::VLD2q8_UPD: 1549 case ARM::VLD2q16_UPD: 1550 case ARM::VLD2q32_UPD: 1551 case ARM::VLD3d8: 1552 case ARM::VLD3d16: 1553 case ARM::VLD3d32: 1554 case ARM::VLD3d8_UPD: 1555 case ARM::VLD3d16_UPD: 1556 case ARM::VLD3d32_UPD: 1557 case ARM::VLD4d8: 1558 case ARM::VLD4d16: 1559 case ARM::VLD4d32: 1560 case ARM::VLD4d8_UPD: 1561 case ARM::VLD4d16_UPD: 1562 case ARM::VLD4d32_UPD: 1563 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1564 break; 1565 case ARM::VLD3q8: 1566 case ARM::VLD3q16: 1567 case ARM::VLD3q32: 1568 case ARM::VLD3q8_UPD: 1569 case ARM::VLD3q16_UPD: 1570 case ARM::VLD3q32_UPD: 1571 case ARM::VLD4q8: 1572 case ARM::VLD4q16: 1573 case ARM::VLD4q32: 1574 case ARM::VLD4q8_UPD: 1575 case ARM::VLD4q16_UPD: 1576 case ARM::VLD4q32_UPD: 1577 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1578 break; 1579 default: 1580 break; 1581 } 1582 1583 // Fourth output register 1584 switch (Inst.getOpcode()) { 1585 case ARM::VLD1d8Q: 1586 case ARM::VLD1d16Q: 1587 case ARM::VLD1d32Q: 1588 case ARM::VLD1d64Q: 1589 case ARM::VLD1d8Q_UPD: 1590 case ARM::VLD1d16Q_UPD: 1591 case ARM::VLD1d32Q_UPD: 1592 case ARM::VLD1d64Q_UPD: 1593 case ARM::VLD2q8: 1594 case ARM::VLD2q16: 1595 case ARM::VLD2q32: 1596 case ARM::VLD2q8_UPD: 1597 case ARM::VLD2q16_UPD: 1598 case ARM::VLD2q32_UPD: 1599 case ARM::VLD4d8: 1600 case ARM::VLD4d16: 1601 case ARM::VLD4d32: 1602 case ARM::VLD4d8_UPD: 1603 case ARM::VLD4d16_UPD: 1604 case ARM::VLD4d32_UPD: 1605 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1606 break; 1607 case ARM::VLD4q8: 1608 case ARM::VLD4q16: 1609 case ARM::VLD4q32: 1610 case ARM::VLD4q8_UPD: 1611 case ARM::VLD4q16_UPD: 1612 case ARM::VLD4q32_UPD: 1613 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1614 break; 1615 default: 1616 break; 1617 } 1618 1619 // Writeback operand 1620 switch (Inst.getOpcode()) { 1621 case ARM::VLD1d8_UPD: 1622 case ARM::VLD1d16_UPD: 1623 case ARM::VLD1d32_UPD: 1624 case ARM::VLD1d64_UPD: 1625 case ARM::VLD1q8_UPD: 1626 case ARM::VLD1q16_UPD: 1627 case ARM::VLD1q32_UPD: 1628 case ARM::VLD1q64_UPD: 1629 case ARM::VLD1d8T_UPD: 1630 case ARM::VLD1d16T_UPD: 1631 case ARM::VLD1d32T_UPD: 1632 case ARM::VLD1d64T_UPD: 1633 case ARM::VLD1d8Q_UPD: 1634 case ARM::VLD1d16Q_UPD: 1635 case ARM::VLD1d32Q_UPD: 1636 case ARM::VLD1d64Q_UPD: 1637 case ARM::VLD2d8_UPD: 1638 case ARM::VLD2d16_UPD: 1639 case ARM::VLD2d32_UPD: 1640 case ARM::VLD2q8_UPD: 1641 case ARM::VLD2q16_UPD: 1642 case ARM::VLD2q32_UPD: 1643 case ARM::VLD2b8_UPD: 1644 case ARM::VLD2b16_UPD: 1645 case ARM::VLD2b32_UPD: 1646 case ARM::VLD3d8_UPD: 1647 case ARM::VLD3d16_UPD: 1648 case ARM::VLD3d32_UPD: 1649 case ARM::VLD3q8_UPD: 1650 case ARM::VLD3q16_UPD: 1651 case ARM::VLD3q32_UPD: 1652 case ARM::VLD4d8_UPD: 1653 case ARM::VLD4d16_UPD: 1654 case ARM::VLD4d32_UPD: 1655 case ARM::VLD4q8_UPD: 1656 case ARM::VLD4q16_UPD: 1657 case ARM::VLD4q32_UPD: 1658 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1659 break; 1660 default: 1661 break; 1662 } 1663 1664 // AddrMode6 Base (register+alignment) 1665 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1666 1667 // AddrMode6 Offset (register) 1668 if (Rm == 0xD) 1669 Inst.addOperand(MCOperand::CreateReg(0)); 1670 else if (Rm != 0xF) { 1671 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1672 } 1673 1674 return S; 1675 } 1676 1677 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1678 uint64_t Address, const void *Decoder) { 1679 DecodeStatus S = Success; 1680 1681 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1682 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1683 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1684 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1685 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1686 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1687 1688 // Writeback Operand 1689 switch (Inst.getOpcode()) { 1690 case ARM::VST1d8_UPD: 1691 case ARM::VST1d16_UPD: 1692 case ARM::VST1d32_UPD: 1693 case ARM::VST1d64_UPD: 1694 case ARM::VST1q8_UPD: 1695 case ARM::VST1q16_UPD: 1696 case ARM::VST1q32_UPD: 1697 case ARM::VST1q64_UPD: 1698 case ARM::VST1d8T_UPD: 1699 case ARM::VST1d16T_UPD: 1700 case ARM::VST1d32T_UPD: 1701 case ARM::VST1d64T_UPD: 1702 case ARM::VST1d8Q_UPD: 1703 case ARM::VST1d16Q_UPD: 1704 case ARM::VST1d32Q_UPD: 1705 case ARM::VST1d64Q_UPD: 1706 case ARM::VST2d8_UPD: 1707 case ARM::VST2d16_UPD: 1708 case ARM::VST2d32_UPD: 1709 case ARM::VST2q8_UPD: 1710 case ARM::VST2q16_UPD: 1711 case ARM::VST2q32_UPD: 1712 case ARM::VST2b8_UPD: 1713 case ARM::VST2b16_UPD: 1714 case ARM::VST2b32_UPD: 1715 case ARM::VST3d8_UPD: 1716 case ARM::VST3d16_UPD: 1717 case ARM::VST3d32_UPD: 1718 case ARM::VST3q8_UPD: 1719 case ARM::VST3q16_UPD: 1720 case ARM::VST3q32_UPD: 1721 case ARM::VST4d8_UPD: 1722 case ARM::VST4d16_UPD: 1723 case ARM::VST4d32_UPD: 1724 case ARM::VST4q8_UPD: 1725 case ARM::VST4q16_UPD: 1726 case ARM::VST4q32_UPD: 1727 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)); 1728 break; 1729 default: 1730 break; 1731 } 1732 1733 // AddrMode6 Base (register+alignment) 1734 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)); 1735 1736 // AddrMode6 Offset (register) 1737 if (Rm == 0xD) 1738 Inst.addOperand(MCOperand::CreateReg(0)); 1739 else if (Rm != 0xF) { 1740 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1741 } 1742 1743 // First input register 1744 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1745 1746 // Second input register 1747 switch (Inst.getOpcode()) { 1748 case ARM::VST1q8: 1749 case ARM::VST1q16: 1750 case ARM::VST1q32: 1751 case ARM::VST1q64: 1752 case ARM::VST1q8_UPD: 1753 case ARM::VST1q16_UPD: 1754 case ARM::VST1q32_UPD: 1755 case ARM::VST1q64_UPD: 1756 case ARM::VST1d8T: 1757 case ARM::VST1d16T: 1758 case ARM::VST1d32T: 1759 case ARM::VST1d64T: 1760 case ARM::VST1d8T_UPD: 1761 case ARM::VST1d16T_UPD: 1762 case ARM::VST1d32T_UPD: 1763 case ARM::VST1d64T_UPD: 1764 case ARM::VST1d8Q: 1765 case ARM::VST1d16Q: 1766 case ARM::VST1d32Q: 1767 case ARM::VST1d64Q: 1768 case ARM::VST1d8Q_UPD: 1769 case ARM::VST1d16Q_UPD: 1770 case ARM::VST1d32Q_UPD: 1771 case ARM::VST1d64Q_UPD: 1772 case ARM::VST2d8: 1773 case ARM::VST2d16: 1774 case ARM::VST2d32: 1775 case ARM::VST2d8_UPD: 1776 case ARM::VST2d16_UPD: 1777 case ARM::VST2d32_UPD: 1778 case ARM::VST2q8: 1779 case ARM::VST2q16: 1780 case ARM::VST2q32: 1781 case ARM::VST2q8_UPD: 1782 case ARM::VST2q16_UPD: 1783 case ARM::VST2q32_UPD: 1784 case ARM::VST3d8: 1785 case ARM::VST3d16: 1786 case ARM::VST3d32: 1787 case ARM::VST3d8_UPD: 1788 case ARM::VST3d16_UPD: 1789 case ARM::VST3d32_UPD: 1790 case ARM::VST4d8: 1791 case ARM::VST4d16: 1792 case ARM::VST4d32: 1793 case ARM::VST4d8_UPD: 1794 case ARM::VST4d16_UPD: 1795 case ARM::VST4d32_UPD: 1796 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1797 break; 1798 case ARM::VST2b8: 1799 case ARM::VST2b16: 1800 case ARM::VST2b32: 1801 case ARM::VST2b8_UPD: 1802 case ARM::VST2b16_UPD: 1803 case ARM::VST2b32_UPD: 1804 case ARM::VST3q8: 1805 case ARM::VST3q16: 1806 case ARM::VST3q32: 1807 case ARM::VST3q8_UPD: 1808 case ARM::VST3q16_UPD: 1809 case ARM::VST3q32_UPD: 1810 case ARM::VST4q8: 1811 case ARM::VST4q16: 1812 case ARM::VST4q32: 1813 case ARM::VST4q8_UPD: 1814 case ARM::VST4q16_UPD: 1815 case ARM::VST4q32_UPD: 1816 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1817 break; 1818 default: 1819 break; 1820 } 1821 1822 // Third input register 1823 switch (Inst.getOpcode()) { 1824 case ARM::VST1d8T: 1825 case ARM::VST1d16T: 1826 case ARM::VST1d32T: 1827 case ARM::VST1d64T: 1828 case ARM::VST1d8T_UPD: 1829 case ARM::VST1d16T_UPD: 1830 case ARM::VST1d32T_UPD: 1831 case ARM::VST1d64T_UPD: 1832 case ARM::VST1d8Q: 1833 case ARM::VST1d16Q: 1834 case ARM::VST1d32Q: 1835 case ARM::VST1d64Q: 1836 case ARM::VST1d8Q_UPD: 1837 case ARM::VST1d16Q_UPD: 1838 case ARM::VST1d32Q_UPD: 1839 case ARM::VST1d64Q_UPD: 1840 case ARM::VST2q8: 1841 case ARM::VST2q16: 1842 case ARM::VST2q32: 1843 case ARM::VST2q8_UPD: 1844 case ARM::VST2q16_UPD: 1845 case ARM::VST2q32_UPD: 1846 case ARM::VST3d8: 1847 case ARM::VST3d16: 1848 case ARM::VST3d32: 1849 case ARM::VST3d8_UPD: 1850 case ARM::VST3d16_UPD: 1851 case ARM::VST3d32_UPD: 1852 case ARM::VST4d8: 1853 case ARM::VST4d16: 1854 case ARM::VST4d32: 1855 case ARM::VST4d8_UPD: 1856 case ARM::VST4d16_UPD: 1857 case ARM::VST4d32_UPD: 1858 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)); 1859 break; 1860 case ARM::VST3q8: 1861 case ARM::VST3q16: 1862 case ARM::VST3q32: 1863 case ARM::VST3q8_UPD: 1864 case ARM::VST3q16_UPD: 1865 case ARM::VST3q32_UPD: 1866 case ARM::VST4q8: 1867 case ARM::VST4q16: 1868 case ARM::VST4q32: 1869 case ARM::VST4q8_UPD: 1870 case ARM::VST4q16_UPD: 1871 case ARM::VST4q32_UPD: 1872 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)); 1873 break; 1874 default: 1875 break; 1876 } 1877 1878 // Fourth input register 1879 switch (Inst.getOpcode()) { 1880 case ARM::VST1d8Q: 1881 case ARM::VST1d16Q: 1882 case ARM::VST1d32Q: 1883 case ARM::VST1d64Q: 1884 case ARM::VST1d8Q_UPD: 1885 case ARM::VST1d16Q_UPD: 1886 case ARM::VST1d32Q_UPD: 1887 case ARM::VST1d64Q_UPD: 1888 case ARM::VST2q8: 1889 case ARM::VST2q16: 1890 case ARM::VST2q32: 1891 case ARM::VST2q8_UPD: 1892 case ARM::VST2q16_UPD: 1893 case ARM::VST2q32_UPD: 1894 case ARM::VST4d8: 1895 case ARM::VST4d16: 1896 case ARM::VST4d32: 1897 case ARM::VST4d8_UPD: 1898 case ARM::VST4d16_UPD: 1899 case ARM::VST4d32_UPD: 1900 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)); 1901 break; 1902 case ARM::VST4q8: 1903 case ARM::VST4q16: 1904 case ARM::VST4q32: 1905 case ARM::VST4q8_UPD: 1906 case ARM::VST4q16_UPD: 1907 case ARM::VST4q32_UPD: 1908 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)); 1909 break; 1910 default: 1911 break; 1912 } 1913 1914 return S; 1915 } 1916 1917 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1918 uint64_t Address, const void *Decoder) { 1919 DecodeStatus S = Success; 1920 1921 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1922 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1923 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1924 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1925 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1926 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1927 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1928 1929 align *= (1 << size); 1930 1931 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1932 if (regs == 2) { 1933 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)); 1934 } 1935 if (Rm == 0xD) { 1936 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1937 } 1938 1939 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1940 Inst.addOperand(MCOperand::CreateImm(align)); 1941 1942 if (Rm == 0xD) 1943 Inst.addOperand(MCOperand::CreateReg(0)); 1944 else if (Rm != 0xF) { 1945 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1946 } 1947 1948 return S; 1949 } 1950 1951 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1952 uint64_t Address, const void *Decoder) { 1953 DecodeStatus S = Success; 1954 1955 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1956 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1957 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1958 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1959 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1960 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1961 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1962 align *= 2*size; 1963 1964 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1965 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 1966 if (Rm == 0xD) { 1967 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1968 } 1969 1970 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1971 Inst.addOperand(MCOperand::CreateImm(align)); 1972 1973 if (Rm == 0xD) 1974 Inst.addOperand(MCOperand::CreateReg(0)); 1975 else if (Rm != 0xF) { 1976 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 1977 } 1978 1979 return S; 1980 } 1981 1982 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1983 uint64_t Address, const void *Decoder) { 1984 DecodeStatus S = Success; 1985 1986 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1987 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1988 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1989 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1990 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1991 1992 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 1993 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 1994 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 1995 if (Rm == 0xD) { 1996 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 1997 } 1998 1999 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2000 Inst.addOperand(MCOperand::CreateImm(0)); 2001 2002 if (Rm == 0xD) 2003 Inst.addOperand(MCOperand::CreateReg(0)); 2004 else if (Rm != 0xF) { 2005 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2006 } 2007 2008 return S; 2009 } 2010 2011 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 2012 uint64_t Address, const void *Decoder) { 2013 DecodeStatus S = Success; 2014 2015 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2016 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2017 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2018 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2019 unsigned size = fieldFromInstruction32(Insn, 6, 2); 2020 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 2021 unsigned align = fieldFromInstruction32(Insn, 4, 1); 2022 2023 if (size == 0x3) { 2024 size = 4; 2025 align = 16; 2026 } else { 2027 if (size == 2) { 2028 size = 1 << size; 2029 align *= 8; 2030 } else { 2031 size = 1 << size; 2032 align *= 4*size; 2033 } 2034 } 2035 2036 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2037 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)); 2038 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)); 2039 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)); 2040 if (Rm == 0xD) { 2041 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2042 } 2043 2044 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2045 Inst.addOperand(MCOperand::CreateImm(align)); 2046 2047 if (Rm == 0xD) 2048 Inst.addOperand(MCOperand::CreateReg(0)); 2049 else if (Rm != 0xF) { 2050 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2051 } 2052 2053 return S; 2054 } 2055 2056 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2057 uint64_t Address, const void *Decoder) { 2058 DecodeStatus S = Success; 2059 2060 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2061 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2062 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2063 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2064 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2065 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2066 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2067 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2068 2069 if (Q) { 2070 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2071 } else { 2072 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2073 } 2074 2075 Inst.addOperand(MCOperand::CreateImm(imm)); 2076 2077 switch (Inst.getOpcode()) { 2078 case ARM::VORRiv4i16: 2079 case ARM::VORRiv2i32: 2080 case ARM::VBICiv4i16: 2081 case ARM::VBICiv2i32: 2082 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2083 break; 2084 case ARM::VORRiv8i16: 2085 case ARM::VORRiv4i32: 2086 case ARM::VBICiv8i16: 2087 case ARM::VBICiv4i32: 2088 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2089 break; 2090 default: 2091 break; 2092 } 2093 2094 return S; 2095 } 2096 2097 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2098 uint64_t Address, const void *Decoder) { 2099 DecodeStatus S = Success; 2100 2101 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2102 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2103 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2104 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2105 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2106 2107 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)); 2108 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2109 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2110 2111 return S; 2112 } 2113 2114 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2115 uint64_t Address, const void *Decoder) { 2116 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2117 return Success; 2118 } 2119 2120 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2121 uint64_t Address, const void *Decoder) { 2122 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2123 return Success; 2124 } 2125 2126 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2127 uint64_t Address, const void *Decoder) { 2128 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2129 return Success; 2130 } 2131 2132 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2133 uint64_t Address, const void *Decoder) { 2134 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2135 return Success; 2136 } 2137 2138 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2139 uint64_t Address, const void *Decoder) { 2140 DecodeStatus S = Success; 2141 2142 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2143 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2144 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2145 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2146 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2147 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2148 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2149 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2150 2151 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2152 if (op) { 2153 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback 2154 } 2155 2156 for (unsigned i = 0; i < length; ++i) { 2157 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)); 2158 } 2159 2160 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)); 2161 2162 return S; 2163 } 2164 2165 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2166 uint64_t Address, const void *Decoder) { 2167 // The immediate needs to be a fully instantiated float. However, the 2168 // auto-generated decoder is only able to fill in some of the bits 2169 // necessary. For instance, the 'b' bit is replicated multiple times, 2170 // and is even present in inverted form in one bit. We do a little 2171 // binary parsing here to fill in those missing bits, and then 2172 // reinterpret it all as a float. 2173 union { 2174 uint32_t integer; 2175 float fp; 2176 } fp_conv; 2177 2178 fp_conv.integer = Val; 2179 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2180 fp_conv.integer |= b << 26; 2181 fp_conv.integer |= b << 27; 2182 fp_conv.integer |= b << 28; 2183 fp_conv.integer |= b << 29; 2184 fp_conv.integer |= (~b & 0x1) << 30; 2185 2186 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2187 return Success; 2188 } 2189 2190 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2191 uint64_t Address, const void *Decoder) { 2192 DecodeStatus S = Success; 2193 2194 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2195 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2196 2197 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)); 2198 2199 if (Inst.getOpcode() == ARM::tADR) 2200 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2201 else if (Inst.getOpcode() == ARM::tADDrSPi) 2202 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2203 else 2204 return Fail; 2205 2206 Inst.addOperand(MCOperand::CreateImm(imm)); 2207 return S; 2208 } 2209 2210 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2211 uint64_t Address, const void *Decoder) { 2212 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2213 return Success; 2214 } 2215 2216 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2217 uint64_t Address, const void *Decoder) { 2218 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2219 return Success; 2220 } 2221 2222 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2223 uint64_t Address, const void *Decoder) { 2224 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2225 return Success; 2226 } 2227 2228 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2229 uint64_t Address, const void *Decoder) { 2230 DecodeStatus S = Success; 2231 2232 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2233 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2234 2235 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2236 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)); 2237 2238 return S; 2239 } 2240 2241 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2242 uint64_t Address, const void *Decoder) { 2243 DecodeStatus S = Success; 2244 2245 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2246 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2247 2248 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)); 2249 Inst.addOperand(MCOperand::CreateImm(imm)); 2250 2251 return S; 2252 } 2253 2254 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2255 uint64_t Address, const void *Decoder) { 2256 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2257 2258 return Success; 2259 } 2260 2261 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2262 uint64_t Address, const void *Decoder) { 2263 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2264 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2265 2266 return Success; 2267 } 2268 2269 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2270 uint64_t Address, const void *Decoder) { 2271 DecodeStatus S = Success; 2272 2273 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2274 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2275 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2276 2277 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2278 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)); 2279 Inst.addOperand(MCOperand::CreateImm(imm)); 2280 2281 return S; 2282 } 2283 2284 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2285 uint64_t Address, const void *Decoder) { 2286 DecodeStatus S = Success; 2287 2288 if (Inst.getOpcode() != ARM::t2PLDs) { 2289 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2290 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2291 } 2292 2293 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2294 if (Rn == 0xF) { 2295 switch (Inst.getOpcode()) { 2296 case ARM::t2LDRBs: 2297 Inst.setOpcode(ARM::t2LDRBpci); 2298 break; 2299 case ARM::t2LDRHs: 2300 Inst.setOpcode(ARM::t2LDRHpci); 2301 break; 2302 case ARM::t2LDRSHs: 2303 Inst.setOpcode(ARM::t2LDRSHpci); 2304 break; 2305 case ARM::t2LDRSBs: 2306 Inst.setOpcode(ARM::t2LDRSBpci); 2307 break; 2308 case ARM::t2PLDs: 2309 Inst.setOpcode(ARM::t2PLDi12); 2310 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2311 break; 2312 default: 2313 return Fail; 2314 } 2315 2316 int imm = fieldFromInstruction32(Insn, 0, 12); 2317 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2318 Inst.addOperand(MCOperand::CreateImm(imm)); 2319 2320 return S; 2321 } 2322 2323 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2324 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2325 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2326 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)); 2327 2328 return S; 2329 } 2330 2331 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2332 uint64_t Address, const void *Decoder) { 2333 int imm = Val & 0xFF; 2334 if (!(Val & 0x100)) imm *= -1; 2335 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2336 2337 return Success; 2338 } 2339 2340 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2341 uint64_t Address, const void *Decoder) { 2342 DecodeStatus S = Success; 2343 2344 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2345 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2346 2347 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2348 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)); 2349 2350 return S; 2351 } 2352 2353 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2354 uint64_t Address, const void *Decoder) { 2355 int imm = Val & 0xFF; 2356 if (!(Val & 0x100)) imm *= -1; 2357 Inst.addOperand(MCOperand::CreateImm(imm)); 2358 2359 return Success; 2360 } 2361 2362 2363 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2364 uint64_t Address, const void *Decoder) { 2365 DecodeStatus S = Success; 2366 2367 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2368 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2369 2370 // Some instructions always use an additive offset. 2371 switch (Inst.getOpcode()) { 2372 case ARM::t2LDRT: 2373 case ARM::t2LDRBT: 2374 case ARM::t2LDRHT: 2375 case ARM::t2LDRSBT: 2376 case ARM::t2LDRSHT: 2377 imm |= 0x100; 2378 break; 2379 default: 2380 break; 2381 } 2382 2383 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2384 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder)); 2385 2386 return S; 2387 } 2388 2389 2390 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2391 uint64_t Address, const void *Decoder) { 2392 DecodeStatus S = Success; 2393 2394 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2395 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2396 2397 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2398 Inst.addOperand(MCOperand::CreateImm(imm)); 2399 2400 return S; 2401 } 2402 2403 2404 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2405 uint64_t Address, const void *Decoder) { 2406 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2407 2408 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2409 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2410 Inst.addOperand(MCOperand::CreateImm(imm)); 2411 2412 return Success; 2413 } 2414 2415 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2416 uint64_t Address, const void *Decoder) { 2417 DecodeStatus S = Success; 2418 2419 if (Inst.getOpcode() == ARM::tADDrSP) { 2420 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2421 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2422 2423 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2424 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2425 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)); 2426 } else if (Inst.getOpcode() == ARM::tADDspr) { 2427 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2428 2429 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2430 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2431 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2432 } 2433 2434 return S; 2435 } 2436 2437 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2438 uint64_t Address, const void *Decoder) { 2439 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2440 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2441 2442 Inst.addOperand(MCOperand::CreateImm(imod)); 2443 Inst.addOperand(MCOperand::CreateImm(flags)); 2444 2445 return Success; 2446 } 2447 2448 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2449 uint64_t Address, const void *Decoder) { 2450 DecodeStatus S = Success; 2451 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2452 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2453 2454 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ; 2455 Inst.addOperand(MCOperand::CreateImm(add)); 2456 2457 return S; 2458 } 2459 2460 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2461 uint64_t Address, const void *Decoder) { 2462 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2463 return Success; 2464 } 2465 2466 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2467 uint64_t Address, const void *Decoder) { 2468 if (Val == 0xA || Val == 0xB) 2469 return Fail; 2470 2471 Inst.addOperand(MCOperand::CreateImm(Val)); 2472 return Success; 2473 } 2474 2475 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2476 uint64_t Address, const void *Decoder) { 2477 DecodeStatus S = Success; 2478 2479 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2480 if (pred == 0xE || pred == 0xF) { 2481 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2482 switch (opc) { 2483 default: 2484 return Fail; 2485 case 0: 2486 Inst.setOpcode(ARM::t2DSB); 2487 break; 2488 case 1: 2489 Inst.setOpcode(ARM::t2DMB); 2490 break; 2491 case 2: 2492 Inst.setOpcode(ARM::t2ISB); 2493 return Success; 2494 } 2495 2496 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2497 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2498 } 2499 2500 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2501 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2502 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2503 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2504 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2505 2506 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)); 2507 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2508 2509 return S; 2510 } 2511 2512 // Decode a shifted immediate operand. These basically consist 2513 // of an 8-bit value, and a 4-bit directive that specifies either 2514 // a splat operation or a rotation. 2515 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2516 uint64_t Address, const void *Decoder) { 2517 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2518 if (ctrl == 0) { 2519 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2520 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2521 switch (byte) { 2522 case 0: 2523 Inst.addOperand(MCOperand::CreateImm(imm)); 2524 break; 2525 case 1: 2526 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2527 break; 2528 case 2: 2529 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2530 break; 2531 case 3: 2532 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2533 (imm << 8) | imm)); 2534 break; 2535 } 2536 } else { 2537 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2538 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2539 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2540 Inst.addOperand(MCOperand::CreateImm(imm)); 2541 } 2542 2543 return Success; 2544 } 2545 2546 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2547 uint64_t Address, const void *Decoder){ 2548 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2549 return Success; 2550 } 2551 2552 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2553 uint64_t Address, const void *Decoder){ 2554 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2555 return Success; 2556 } 2557 2558 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2559 uint64_t Address, const void *Decoder) { 2560 switch (Val) { 2561 default: 2562 return Fail; 2563 case 0xF: // SY 2564 case 0xE: // ST 2565 case 0xB: // ISH 2566 case 0xA: // ISHST 2567 case 0x7: // NSH 2568 case 0x6: // NSHST 2569 case 0x3: // OSH 2570 case 0x2: // OSHST 2571 break; 2572 } 2573 2574 Inst.addOperand(MCOperand::CreateImm(Val)); 2575 return Success; 2576 } 2577 2578 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2579 uint64_t Address, const void *Decoder) { 2580 if (!Val) return Fail; 2581 Inst.addOperand(MCOperand::CreateImm(Val)); 2582 return Success; 2583 } 2584 2585 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2586 uint64_t Address, const void *Decoder) { 2587 DecodeStatus S = Success; 2588 2589 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2590 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2591 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2592 2593 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2594 2595 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2596 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2597 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2598 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2599 2600 return S; 2601 } 2602 2603 2604 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2605 uint64_t Address, const void *Decoder) { 2606 DecodeStatus S = Success; 2607 2608 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2609 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2610 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2611 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2612 2613 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)); 2614 2615 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail; 2616 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail; 2617 2618 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2619 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)); 2620 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2621 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2622 2623 return S; 2624 } 2625 2626 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2627 uint64_t Address, const void *Decoder) { 2628 DecodeStatus S = Success; 2629 2630 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2631 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2632 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2633 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2634 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2635 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2636 2637 if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE 2638 2639 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2640 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2641 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)); 2642 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2643 2644 return S; 2645 } 2646 2647 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2648 uint64_t Address, const void *Decoder) { 2649 DecodeStatus S = Success; 2650 2651 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2652 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2653 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2654 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2655 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2656 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2657 2658 if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE 2659 2660 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2661 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 2662 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)); 2663 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder)); 2664 2665 return S; 2666 } 2667 2668 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2669 uint64_t Address, const void *Decoder) { 2670 DecodeStatus S = Success; 2671 2672 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2673 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2674 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2675 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2676 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2677 2678 unsigned align = 0; 2679 unsigned index = 0; 2680 switch (size) { 2681 default: 2682 return Fail; 2683 case 0: 2684 if (fieldFromInstruction32(Insn, 4, 1)) 2685 return Fail; // UNDEFINED 2686 index = fieldFromInstruction32(Insn, 5, 3); 2687 break; 2688 case 1: 2689 if (fieldFromInstruction32(Insn, 5, 1)) 2690 return Fail; // UNDEFINED 2691 index = fieldFromInstruction32(Insn, 6, 2); 2692 if (fieldFromInstruction32(Insn, 4, 1)) 2693 align = 2; 2694 break; 2695 case 2: 2696 if (fieldFromInstruction32(Insn, 6, 1)) 2697 return Fail; // UNDEFINED 2698 index = fieldFromInstruction32(Insn, 7, 1); 2699 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2700 align = 4; 2701 } 2702 2703 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2704 if (Rm != 0xF) { // Writeback 2705 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2706 } 2707 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2708 Inst.addOperand(MCOperand::CreateImm(align)); 2709 if (Rm != 0xF && Rm != 0xD) { 2710 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2711 } 2712 2713 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2714 Inst.addOperand(MCOperand::CreateImm(index)); 2715 2716 return S; 2717 } 2718 2719 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2720 uint64_t Address, const void *Decoder) { 2721 DecodeStatus S = Success; 2722 2723 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2724 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2725 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2726 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2727 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2728 2729 unsigned align = 0; 2730 unsigned index = 0; 2731 switch (size) { 2732 default: 2733 return Fail; 2734 case 0: 2735 if (fieldFromInstruction32(Insn, 4, 1)) 2736 return Fail; // UNDEFINED 2737 index = fieldFromInstruction32(Insn, 5, 3); 2738 break; 2739 case 1: 2740 if (fieldFromInstruction32(Insn, 5, 1)) 2741 return Fail; // UNDEFINED 2742 index = fieldFromInstruction32(Insn, 6, 2); 2743 if (fieldFromInstruction32(Insn, 4, 1)) 2744 align = 2; 2745 break; 2746 case 2: 2747 if (fieldFromInstruction32(Insn, 6, 1)) 2748 return Fail; // UNDEFINED 2749 index = fieldFromInstruction32(Insn, 7, 1); 2750 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2751 align = 4; 2752 } 2753 2754 if (Rm != 0xF) { // Writeback 2755 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2756 } 2757 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2758 Inst.addOperand(MCOperand::CreateImm(align)); 2759 if (Rm != 0xF && Rm != 0xD) { 2760 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2761 } 2762 2763 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2764 Inst.addOperand(MCOperand::CreateImm(index)); 2765 2766 return S; 2767 } 2768 2769 2770 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2771 uint64_t Address, const void *Decoder) { 2772 DecodeStatus S = Success; 2773 2774 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2775 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2776 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2777 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2778 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2779 2780 unsigned align = 0; 2781 unsigned index = 0; 2782 unsigned inc = 1; 2783 switch (size) { 2784 default: 2785 return Fail; 2786 case 0: 2787 index = fieldFromInstruction32(Insn, 5, 3); 2788 if (fieldFromInstruction32(Insn, 4, 1)) 2789 align = 2; 2790 break; 2791 case 1: 2792 index = fieldFromInstruction32(Insn, 6, 2); 2793 if (fieldFromInstruction32(Insn, 4, 1)) 2794 align = 4; 2795 if (fieldFromInstruction32(Insn, 5, 1)) 2796 inc = 2; 2797 break; 2798 case 2: 2799 if (fieldFromInstruction32(Insn, 5, 1)) 2800 return Fail; // UNDEFINED 2801 index = fieldFromInstruction32(Insn, 7, 1); 2802 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2803 align = 8; 2804 if (fieldFromInstruction32(Insn, 6, 1)) 2805 inc = 2; 2806 break; 2807 } 2808 2809 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2810 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2811 if (Rm != 0xF) { // Writeback 2812 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2813 } 2814 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2815 Inst.addOperand(MCOperand::CreateImm(align)); 2816 if (Rm != 0xF && Rm != 0xD) { 2817 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2818 } 2819 2820 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2821 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2822 Inst.addOperand(MCOperand::CreateImm(index)); 2823 2824 return S; 2825 } 2826 2827 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2828 uint64_t Address, const void *Decoder) { 2829 DecodeStatus S = Success; 2830 2831 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2832 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2833 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2834 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2835 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2836 2837 unsigned align = 0; 2838 unsigned index = 0; 2839 unsigned inc = 1; 2840 switch (size) { 2841 default: 2842 return Fail; 2843 case 0: 2844 index = fieldFromInstruction32(Insn, 5, 3); 2845 if (fieldFromInstruction32(Insn, 4, 1)) 2846 align = 2; 2847 break; 2848 case 1: 2849 index = fieldFromInstruction32(Insn, 6, 2); 2850 if (fieldFromInstruction32(Insn, 4, 1)) 2851 align = 4; 2852 if (fieldFromInstruction32(Insn, 5, 1)) 2853 inc = 2; 2854 break; 2855 case 2: 2856 if (fieldFromInstruction32(Insn, 5, 1)) 2857 return Fail; // UNDEFINED 2858 index = fieldFromInstruction32(Insn, 7, 1); 2859 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2860 align = 8; 2861 if (fieldFromInstruction32(Insn, 6, 1)) 2862 inc = 2; 2863 break; 2864 } 2865 2866 if (Rm != 0xF) { // Writeback 2867 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2868 } 2869 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2870 Inst.addOperand(MCOperand::CreateImm(align)); 2871 if (Rm != 0xF && Rm != 0xD) { 2872 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2873 } 2874 2875 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2876 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2877 Inst.addOperand(MCOperand::CreateImm(index)); 2878 2879 return S; 2880 } 2881 2882 2883 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 2884 uint64_t Address, const void *Decoder) { 2885 DecodeStatus S = Success; 2886 2887 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2888 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2889 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2890 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2891 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2892 2893 unsigned align = 0; 2894 unsigned index = 0; 2895 unsigned inc = 1; 2896 switch (size) { 2897 default: 2898 return Fail; 2899 case 0: 2900 if (fieldFromInstruction32(Insn, 4, 1)) 2901 return Fail; // UNDEFINED 2902 index = fieldFromInstruction32(Insn, 5, 3); 2903 break; 2904 case 1: 2905 if (fieldFromInstruction32(Insn, 4, 1)) 2906 return Fail; // UNDEFINED 2907 index = fieldFromInstruction32(Insn, 6, 2); 2908 if (fieldFromInstruction32(Insn, 5, 1)) 2909 inc = 2; 2910 break; 2911 case 2: 2912 if (fieldFromInstruction32(Insn, 4, 2)) 2913 return Fail; // UNDEFINED 2914 index = fieldFromInstruction32(Insn, 7, 1); 2915 if (fieldFromInstruction32(Insn, 6, 1)) 2916 inc = 2; 2917 break; 2918 } 2919 2920 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2921 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2922 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2923 2924 if (Rm != 0xF) { // Writeback 2925 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2926 } 2927 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2928 Inst.addOperand(MCOperand::CreateImm(align)); 2929 if (Rm != 0xF && Rm != 0xD) { 2930 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2931 } 2932 2933 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2934 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2935 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2936 Inst.addOperand(MCOperand::CreateImm(index)); 2937 2938 return S; 2939 } 2940 2941 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 2942 uint64_t Address, const void *Decoder) { 2943 DecodeStatus S = Success; 2944 2945 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2946 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2947 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2948 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2949 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2950 2951 unsigned align = 0; 2952 unsigned index = 0; 2953 unsigned inc = 1; 2954 switch (size) { 2955 default: 2956 return Fail; 2957 case 0: 2958 if (fieldFromInstruction32(Insn, 4, 1)) 2959 return Fail; // UNDEFINED 2960 index = fieldFromInstruction32(Insn, 5, 3); 2961 break; 2962 case 1: 2963 if (fieldFromInstruction32(Insn, 4, 1)) 2964 return Fail; // UNDEFINED 2965 index = fieldFromInstruction32(Insn, 6, 2); 2966 if (fieldFromInstruction32(Insn, 5, 1)) 2967 inc = 2; 2968 break; 2969 case 2: 2970 if (fieldFromInstruction32(Insn, 4, 2)) 2971 return Fail; // UNDEFINED 2972 index = fieldFromInstruction32(Insn, 7, 1); 2973 if (fieldFromInstruction32(Insn, 6, 1)) 2974 inc = 2; 2975 break; 2976 } 2977 2978 if (Rm != 0xF) { // Writeback 2979 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2980 } 2981 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 2982 Inst.addOperand(MCOperand::CreateImm(align)); 2983 if (Rm != 0xF && Rm != 0xD) { 2984 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 2985 } 2986 2987 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 2988 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 2989 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 2990 Inst.addOperand(MCOperand::CreateImm(index)); 2991 2992 return S; 2993 } 2994 2995 2996 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 2997 uint64_t Address, const void *Decoder) { 2998 DecodeStatus S = Success; 2999 3000 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3001 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3002 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3003 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3004 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3005 3006 unsigned align = 0; 3007 unsigned index = 0; 3008 unsigned inc = 1; 3009 switch (size) { 3010 default: 3011 return Fail; 3012 case 0: 3013 if (fieldFromInstruction32(Insn, 4, 1)) 3014 align = 4; 3015 index = fieldFromInstruction32(Insn, 5, 3); 3016 break; 3017 case 1: 3018 if (fieldFromInstruction32(Insn, 4, 1)) 3019 align = 8; 3020 index = fieldFromInstruction32(Insn, 6, 2); 3021 if (fieldFromInstruction32(Insn, 5, 1)) 3022 inc = 2; 3023 break; 3024 case 2: 3025 if (fieldFromInstruction32(Insn, 4, 2)) 3026 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3027 index = fieldFromInstruction32(Insn, 7, 1); 3028 if (fieldFromInstruction32(Insn, 6, 1)) 3029 inc = 2; 3030 break; 3031 } 3032 3033 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3034 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3035 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3036 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3037 3038 if (Rm != 0xF) { // Writeback 3039 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3040 } 3041 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3042 Inst.addOperand(MCOperand::CreateImm(align)); 3043 if (Rm != 0xF && Rm != 0xD) { 3044 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3045 } 3046 3047 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3048 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3049 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3050 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3051 Inst.addOperand(MCOperand::CreateImm(index)); 3052 3053 return S; 3054 } 3055 3056 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 3057 uint64_t Address, const void *Decoder) { 3058 DecodeStatus S = Success; 3059 3060 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 3061 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 3062 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 3063 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 3064 unsigned size = fieldFromInstruction32(Insn, 10, 2); 3065 3066 unsigned align = 0; 3067 unsigned index = 0; 3068 unsigned inc = 1; 3069 switch (size) { 3070 default: 3071 return Fail; 3072 case 0: 3073 if (fieldFromInstruction32(Insn, 4, 1)) 3074 align = 4; 3075 index = fieldFromInstruction32(Insn, 5, 3); 3076 break; 3077 case 1: 3078 if (fieldFromInstruction32(Insn, 4, 1)) 3079 align = 8; 3080 index = fieldFromInstruction32(Insn, 6, 2); 3081 if (fieldFromInstruction32(Insn, 5, 1)) 3082 inc = 2; 3083 break; 3084 case 2: 3085 if (fieldFromInstruction32(Insn, 4, 2)) 3086 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3087 index = fieldFromInstruction32(Insn, 7, 1); 3088 if (fieldFromInstruction32(Insn, 6, 1)) 3089 inc = 2; 3090 break; 3091 } 3092 3093 if (Rm != 0xF) { // Writeback 3094 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3095 } 3096 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); 3097 Inst.addOperand(MCOperand::CreateImm(align)); 3098 if (Rm != 0xF && Rm != 0xD) { 3099 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)); 3100 } 3101 3102 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); 3103 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)); 3104 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)); 3105 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)); 3106 Inst.addOperand(MCOperand::CreateImm(index)); 3107 3108 return S; 3109 } 3110 3111