1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCDisassembler.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCFixedLenDisassembler.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/LEB128.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/TargetRegistry.h" 25 #include "llvm/Support/raw_ostream.h" 26 #include <vector> 27 28 using namespace llvm; 29 30 #define DEBUG_TYPE "arm-disassembler" 31 32 typedef MCDisassembler::DecodeStatus DecodeStatus; 33 34 namespace { 35 // Handles the condition code status of instructions in IT blocks 36 class ITStatus 37 { 38 public: 39 // Returns the condition code for instruction in IT block 40 unsigned getITCC() { 41 unsigned CC = ARMCC::AL; 42 if (instrInITBlock()) 43 CC = ITStates.back(); 44 return CC; 45 } 46 47 // Advances the IT block state to the next T or E 48 void advanceITState() { 49 ITStates.pop_back(); 50 } 51 52 // Returns true if the current instruction is in an IT block 53 bool instrInITBlock() { 54 return !ITStates.empty(); 55 } 56 57 // Returns true if current instruction is the last instruction in an IT block 58 bool instrLastInITBlock() { 59 return ITStates.size() == 1; 60 } 61 62 // Called when decoding an IT instruction. Sets the IT state for the following 63 // instructions that for the IT block. Firstcond and Mask correspond to the 64 // fields in the IT instruction encoding. 65 void setITState(char Firstcond, char Mask) { 66 // (3 - the number of trailing zeros) is the number of then / else. 67 unsigned CondBit0 = Firstcond & 1; 68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 70 assert(NumTZ <= 3 && "Invalid IT mask!"); 71 // push condition codes onto the stack the correct order for the pops 72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 73 bool T = ((Mask >> Pos) & 1) == CondBit0; 74 if (T) 75 ITStates.push_back(CCBits); 76 else 77 ITStates.push_back(CCBits ^ 1); 78 } 79 ITStates.push_back(CCBits); 80 } 81 82 private: 83 std::vector<unsigned char> ITStates; 84 }; 85 } 86 87 namespace { 88 /// ARMDisassembler - ARM disassembler for all ARM platforms. 89 class ARMDisassembler : public MCDisassembler { 90 public: 91 /// Constructor - Initializes the disassembler. 92 /// 93 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 94 MCDisassembler(STI, Ctx) { 95 } 96 97 ~ARMDisassembler() { 98 } 99 100 /// getInstruction - See MCDisassembler. 101 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 102 const MemoryObject ®ion, uint64_t address, 103 raw_ostream &vStream, 104 raw_ostream &cStream) const override; 105 }; 106 107 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms. 108 class ThumbDisassembler : public MCDisassembler { 109 public: 110 /// Constructor - Initializes the disassembler. 111 /// 112 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 113 MCDisassembler(STI, Ctx) { 114 } 115 116 ~ThumbDisassembler() { 117 } 118 119 /// getInstruction - See MCDisassembler. 120 DecodeStatus getInstruction(MCInst &instr, uint64_t &size, 121 const MemoryObject ®ion, uint64_t address, 122 raw_ostream &vStream, 123 raw_ostream &cStream) const override; 124 125 private: 126 mutable ITStatus ITBlock; 127 DecodeStatus AddThumbPredicate(MCInst&) const; 128 void UpdateThumbVFPPredicate(MCInst&) const; 129 }; 130 } 131 132 static bool Check(DecodeStatus &Out, DecodeStatus In) { 133 switch (In) { 134 case MCDisassembler::Success: 135 // Out stays the same. 136 return true; 137 case MCDisassembler::SoftFail: 138 Out = In; 139 return true; 140 case MCDisassembler::Fail: 141 Out = In; 142 return false; 143 } 144 llvm_unreachable("Invalid DecodeStatus!"); 145 } 146 147 148 // Forward declare these because the autogenerated code will reference them. 149 // Definitions are further down. 150 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 151 uint64_t Address, const void *Decoder); 152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 153 unsigned RegNo, uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 156 unsigned RegNo, uint64_t Address, 157 const void *Decoder); 158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 159 uint64_t Address, const void *Decoder); 160 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 161 uint64_t Address, const void *Decoder); 162 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 uint64_t Address, const void *Decoder); 164 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 165 uint64_t Address, const void *Decoder); 166 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 uint64_t Address, const void *Decoder); 168 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 uint64_t Address, const void *Decoder); 170 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, const void *Decoder); 172 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 173 unsigned RegNo, 174 uint64_t Address, 175 const void *Decoder); 176 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, const void *Decoder); 178 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 179 uint64_t Address, const void *Decoder); 180 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 181 unsigned RegNo, uint64_t Address, 182 const void *Decoder); 183 184 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 193 uint64_t Address, const void *Decoder); 194 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 195 uint64_t Address, const void *Decoder); 196 197 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 198 uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 202 unsigned Insn, 203 uint64_t Address, 204 const void *Decoder); 205 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 214 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 215 unsigned Insn, 216 uint64_t Adddress, 217 const void *Decoder); 218 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 223 uint64_t Address, const void *Decoder); 224 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 251 uint64_t Address, const void *Decoder); 252 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 253 uint64_t Address, const void *Decoder); 254 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 261 uint64_t Address, const void *Decoder); 262 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 263 uint64_t Address, const void *Decoder); 264 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 265 uint64_t Address, const void *Decoder); 266 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 323 uint64_t Address, const void *Decoder); 324 325 326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void* Decoder); 348 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void* Decoder); 350 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void* Decoder); 352 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void* Decoder); 354 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 395 uint64_t Address, const void *Decoder); 396 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 397 uint64_t Address, const void *Decoder); 398 399 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 #include "ARMGenDisassemblerTables.inc" 404 405 static MCDisassembler *createARMDisassembler(const Target &T, 406 const MCSubtargetInfo &STI, 407 MCContext &Ctx) { 408 return new ARMDisassembler(STI, Ctx); 409 } 410 411 static MCDisassembler *createThumbDisassembler(const Target &T, 412 const MCSubtargetInfo &STI, 413 MCContext &Ctx) { 414 return new ThumbDisassembler(STI, Ctx); 415 } 416 417 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 418 const MemoryObject &Region, 419 uint64_t Address, 420 raw_ostream &os, 421 raw_ostream &cs) const { 422 CommentStream = &cs; 423 424 uint8_t bytes[4]; 425 426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); 428 429 // We want to read exactly 4 bytes of data. 430 if (Region.readBytes(Address, 4, bytes) == -1) { 431 Size = 0; 432 return MCDisassembler::Fail; 433 } 434 435 // Encoded as a small-endian 32-bit word in the stream. 436 uint32_t insn = (bytes[3] << 24) | 437 (bytes[2] << 16) | 438 (bytes[1] << 8) | 439 (bytes[0] << 0); 440 441 // Calling the auto-generated decoder function. 442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, 443 Address, this, STI); 444 if (result != MCDisassembler::Fail) { 445 Size = 4; 446 return result; 447 } 448 449 // VFP and NEON instructions, similarly, are shared between ARM 450 // and Thumb modes. 451 MI.clear(); 452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); 453 if (result != MCDisassembler::Fail) { 454 Size = 4; 455 return result; 456 } 457 458 MI.clear(); 459 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI); 460 if (result != MCDisassembler::Fail) { 461 Size = 4; 462 return result; 463 } 464 465 MI.clear(); 466 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, 467 this, STI); 468 if (result != MCDisassembler::Fail) { 469 Size = 4; 470 // Add a fake predicate operand, because we share these instruction 471 // definitions with Thumb2 where these instructions are predicable. 472 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 473 return MCDisassembler::Fail; 474 return result; 475 } 476 477 MI.clear(); 478 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, 479 this, STI); 480 if (result != MCDisassembler::Fail) { 481 Size = 4; 482 // Add a fake predicate operand, because we share these instruction 483 // definitions with Thumb2 where these instructions are predicable. 484 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 485 return MCDisassembler::Fail; 486 return result; 487 } 488 489 MI.clear(); 490 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, 491 this, STI); 492 if (result != MCDisassembler::Fail) { 493 Size = 4; 494 // Add a fake predicate operand, because we share these instruction 495 // definitions with Thumb2 where these instructions are predicable. 496 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 497 return MCDisassembler::Fail; 498 return result; 499 } 500 501 MI.clear(); 502 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address, 503 this, STI); 504 if (result != MCDisassembler::Fail) { 505 Size = 4; 506 return result; 507 } 508 509 MI.clear(); 510 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address, 511 this, STI); 512 if (result != MCDisassembler::Fail) { 513 Size = 4; 514 return result; 515 } 516 517 MI.clear(); 518 Size = 0; 519 return MCDisassembler::Fail; 520 } 521 522 namespace llvm { 523 extern const MCInstrDesc ARMInsts[]; 524 } 525 526 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 527 /// immediate Value in the MCInst. The immediate Value has had any PC 528 /// adjustment made by the caller. If the instruction is a branch instruction 529 /// then isBranch is true, else false. If the getOpInfo() function was set as 530 /// part of the setupForSymbolicDisassembly() call then that function is called 531 /// to get any symbolic information at the Address for this instruction. If 532 /// that returns non-zero then the symbolic information it returns is used to 533 /// create an MCExpr and that is added as an operand to the MCInst. If 534 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 535 /// Value is done and if a symbol is found an MCExpr is created with that, else 536 /// an MCExpr with Value is created. This function returns true if it adds an 537 /// operand to the MCInst and false otherwise. 538 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 539 bool isBranch, uint64_t InstSize, 540 MCInst &MI, const void *Decoder) { 541 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 542 // FIXME: Does it make sense for value to be negative? 543 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 544 /* Offset */ 0, InstSize); 545 } 546 547 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 548 /// referenced by a load instruction with the base register that is the Pc. 549 /// These can often be values in a literal pool near the Address of the 550 /// instruction. The Address of the instruction and its immediate Value are 551 /// used as a possible literal pool entry. The SymbolLookUp call back will 552 /// return the name of a symbol referenced by the literal pool's entry if 553 /// the referenced address is that of a symbol. Or it will return a pointer to 554 /// a literal 'C' string if the referenced address of the literal pool's entry 555 /// is an address into a section with 'C' string literals. 556 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 557 const void *Decoder) { 558 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 559 Dis->tryAddingPcLoadReferenceComment(Value, Address); 560 } 561 562 // Thumb1 instructions don't have explicit S bits. Rather, they 563 // implicitly set CPSR. Since it's not represented in the encoding, the 564 // auto-generated decoder won't inject the CPSR operand. We need to fix 565 // that as a post-pass. 566 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 567 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 568 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 569 MCInst::iterator I = MI.begin(); 570 for (unsigned i = 0; i < NumOps; ++i, ++I) { 571 if (I == MI.end()) break; 572 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 573 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 574 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 575 return; 576 } 577 } 578 579 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 580 } 581 582 // Most Thumb instructions don't have explicit predicates in the 583 // encoding, but rather get their predicates from IT context. We need 584 // to fix up the predicate operands using this context information as a 585 // post-pass. 586 MCDisassembler::DecodeStatus 587 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 588 MCDisassembler::DecodeStatus S = Success; 589 590 // A few instructions actually have predicates encoded in them. Don't 591 // try to overwrite it if we're seeing one of those. 592 switch (MI.getOpcode()) { 593 case ARM::tBcc: 594 case ARM::t2Bcc: 595 case ARM::tCBZ: 596 case ARM::tCBNZ: 597 case ARM::tCPS: 598 case ARM::t2CPS3p: 599 case ARM::t2CPS2p: 600 case ARM::t2CPS1p: 601 case ARM::tMOVSr: 602 case ARM::tSETEND: 603 // Some instructions (mostly conditional branches) are not 604 // allowed in IT blocks. 605 if (ITBlock.instrInITBlock()) 606 S = SoftFail; 607 else 608 return Success; 609 break; 610 case ARM::tB: 611 case ARM::t2B: 612 case ARM::t2TBB: 613 case ARM::t2TBH: 614 // Some instructions (mostly unconditional branches) can 615 // only appears at the end of, or outside of, an IT. 616 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 617 S = SoftFail; 618 break; 619 default: 620 break; 621 } 622 623 // If we're in an IT block, base the predicate on that. Otherwise, 624 // assume a predicate of AL. 625 unsigned CC; 626 CC = ITBlock.getITCC(); 627 if (CC == 0xF) 628 CC = ARMCC::AL; 629 if (ITBlock.instrInITBlock()) 630 ITBlock.advanceITState(); 631 632 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 633 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 634 MCInst::iterator I = MI.begin(); 635 for (unsigned i = 0; i < NumOps; ++i, ++I) { 636 if (I == MI.end()) break; 637 if (OpInfo[i].isPredicate()) { 638 I = MI.insert(I, MCOperand::CreateImm(CC)); 639 ++I; 640 if (CC == ARMCC::AL) 641 MI.insert(I, MCOperand::CreateReg(0)); 642 else 643 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 644 return S; 645 } 646 } 647 648 I = MI.insert(I, MCOperand::CreateImm(CC)); 649 ++I; 650 if (CC == ARMCC::AL) 651 MI.insert(I, MCOperand::CreateReg(0)); 652 else 653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 654 655 return S; 656 } 657 658 // Thumb VFP instructions are a special case. Because we share their 659 // encodings between ARM and Thumb modes, and they are predicable in ARM 660 // mode, the auto-generated decoder will give them an (incorrect) 661 // predicate operand. We need to rewrite these operands based on the IT 662 // context as a post-pass. 663 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 664 unsigned CC; 665 CC = ITBlock.getITCC(); 666 if (ITBlock.instrInITBlock()) 667 ITBlock.advanceITState(); 668 669 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 670 MCInst::iterator I = MI.begin(); 671 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 672 for (unsigned i = 0; i < NumOps; ++i, ++I) { 673 if (OpInfo[i].isPredicate() ) { 674 I->setImm(CC); 675 ++I; 676 if (CC == ARMCC::AL) 677 I->setReg(0); 678 else 679 I->setReg(ARM::CPSR); 680 return; 681 } 682 } 683 } 684 685 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 686 const MemoryObject &Region, 687 uint64_t Address, 688 raw_ostream &os, 689 raw_ostream &cs) const { 690 CommentStream = &cs; 691 692 uint8_t bytes[4]; 693 694 assert((STI.getFeatureBits() & ARM::ModeThumb) && 695 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 696 697 // We want to read exactly 2 bytes of data. 698 if (Region.readBytes(Address, 2, bytes) == -1) { 699 Size = 0; 700 return MCDisassembler::Fail; 701 } 702 703 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 704 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, 705 Address, this, STI); 706 if (result != MCDisassembler::Fail) { 707 Size = 2; 708 Check(result, AddThumbPredicate(MI)); 709 return result; 710 } 711 712 MI.clear(); 713 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, 714 Address, this, STI); 715 if (result) { 716 Size = 2; 717 bool InITBlock = ITBlock.instrInITBlock(); 718 Check(result, AddThumbPredicate(MI)); 719 AddThumb1SBit(MI, InITBlock); 720 return result; 721 } 722 723 MI.clear(); 724 result = decodeInstruction(DecoderTableThumb216, MI, insn16, 725 Address, this, STI); 726 if (result != MCDisassembler::Fail) { 727 Size = 2; 728 729 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 730 // the Thumb predicate. 731 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 732 result = MCDisassembler::SoftFail; 733 734 Check(result, AddThumbPredicate(MI)); 735 736 // If we find an IT instruction, we need to parse its condition 737 // code and mask operands so that we can apply them correctly 738 // to the subsequent instructions. 739 if (MI.getOpcode() == ARM::t2IT) { 740 741 unsigned Firstcond = MI.getOperand(0).getImm(); 742 unsigned Mask = MI.getOperand(1).getImm(); 743 ITBlock.setITState(Firstcond, Mask); 744 } 745 746 return result; 747 } 748 749 // We want to read exactly 4 bytes of data. 750 if (Region.readBytes(Address, 4, bytes) == -1) { 751 Size = 0; 752 return MCDisassembler::Fail; 753 } 754 755 uint32_t insn32 = (bytes[3] << 8) | 756 (bytes[2] << 0) | 757 (bytes[1] << 24) | 758 (bytes[0] << 16); 759 MI.clear(); 760 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, 761 this, STI); 762 if (result != MCDisassembler::Fail) { 763 Size = 4; 764 bool InITBlock = ITBlock.instrInITBlock(); 765 Check(result, AddThumbPredicate(MI)); 766 AddThumb1SBit(MI, InITBlock); 767 return result; 768 } 769 770 MI.clear(); 771 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, 772 this, STI); 773 if (result != MCDisassembler::Fail) { 774 Size = 4; 775 Check(result, AddThumbPredicate(MI)); 776 return result; 777 } 778 779 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 780 MI.clear(); 781 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); 782 if (result != MCDisassembler::Fail) { 783 Size = 4; 784 UpdateThumbVFPPredicate(MI); 785 return result; 786 } 787 } 788 789 MI.clear(); 790 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI); 791 if (result != MCDisassembler::Fail) { 792 Size = 4; 793 return result; 794 } 795 796 if (fieldFromInstruction(insn32, 28, 4) == 0xE) { 797 MI.clear(); 798 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, 799 this, STI); 800 if (result != MCDisassembler::Fail) { 801 Size = 4; 802 Check(result, AddThumbPredicate(MI)); 803 return result; 804 } 805 } 806 807 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { 808 MI.clear(); 809 uint32_t NEONLdStInsn = insn32; 810 NEONLdStInsn &= 0xF0FFFFFF; 811 NEONLdStInsn |= 0x04000000; 812 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 813 Address, this, STI); 814 if (result != MCDisassembler::Fail) { 815 Size = 4; 816 Check(result, AddThumbPredicate(MI)); 817 return result; 818 } 819 } 820 821 if (fieldFromInstruction(insn32, 24, 4) == 0xF) { 822 MI.clear(); 823 uint32_t NEONDataInsn = insn32; 824 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 825 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 826 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 827 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 828 Address, this, STI); 829 if (result != MCDisassembler::Fail) { 830 Size = 4; 831 Check(result, AddThumbPredicate(MI)); 832 return result; 833 } 834 835 MI.clear(); 836 uint32_t NEONCryptoInsn = insn32; 837 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 838 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 839 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 840 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 841 Address, this, STI); 842 if (result != MCDisassembler::Fail) { 843 Size = 4; 844 return result; 845 } 846 847 MI.clear(); 848 uint32_t NEONv8Insn = insn32; 849 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 850 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 851 this, STI); 852 if (result != MCDisassembler::Fail) { 853 Size = 4; 854 return result; 855 } 856 } 857 858 MI.clear(); 859 Size = 0; 860 return MCDisassembler::Fail; 861 } 862 863 864 extern "C" void LLVMInitializeARMDisassembler() { 865 TargetRegistry::RegisterMCDisassembler(TheARMLETarget, 866 createARMDisassembler); 867 TargetRegistry::RegisterMCDisassembler(TheARMBETarget, 868 createARMDisassembler); 869 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget, 870 createThumbDisassembler); 871 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget, 872 createThumbDisassembler); 873 } 874 875 static const uint16_t GPRDecoderTable[] = { 876 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 877 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 878 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 879 ARM::R12, ARM::SP, ARM::LR, ARM::PC 880 }; 881 882 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 883 uint64_t Address, const void *Decoder) { 884 if (RegNo > 15) 885 return MCDisassembler::Fail; 886 887 unsigned Register = GPRDecoderTable[RegNo]; 888 Inst.addOperand(MCOperand::CreateReg(Register)); 889 return MCDisassembler::Success; 890 } 891 892 static DecodeStatus 893 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 894 uint64_t Address, const void *Decoder) { 895 DecodeStatus S = MCDisassembler::Success; 896 897 if (RegNo == 15) 898 S = MCDisassembler::SoftFail; 899 900 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 901 902 return S; 903 } 904 905 static DecodeStatus 906 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 907 uint64_t Address, const void *Decoder) { 908 DecodeStatus S = MCDisassembler::Success; 909 910 if (RegNo == 15) 911 { 912 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 913 return MCDisassembler::Success; 914 } 915 916 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 917 return S; 918 } 919 920 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 921 uint64_t Address, const void *Decoder) { 922 if (RegNo > 7) 923 return MCDisassembler::Fail; 924 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 925 } 926 927 static const uint16_t GPRPairDecoderTable[] = { 928 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 929 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 930 }; 931 932 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 933 uint64_t Address, const void *Decoder) { 934 DecodeStatus S = MCDisassembler::Success; 935 936 if (RegNo > 13) 937 return MCDisassembler::Fail; 938 939 if ((RegNo & 1) || RegNo == 0xe) 940 S = MCDisassembler::SoftFail; 941 942 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 943 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 944 return S; 945 } 946 947 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 948 uint64_t Address, const void *Decoder) { 949 unsigned Register = 0; 950 switch (RegNo) { 951 case 0: 952 Register = ARM::R0; 953 break; 954 case 1: 955 Register = ARM::R1; 956 break; 957 case 2: 958 Register = ARM::R2; 959 break; 960 case 3: 961 Register = ARM::R3; 962 break; 963 case 9: 964 Register = ARM::R9; 965 break; 966 case 12: 967 Register = ARM::R12; 968 break; 969 default: 970 return MCDisassembler::Fail; 971 } 972 973 Inst.addOperand(MCOperand::CreateReg(Register)); 974 return MCDisassembler::Success; 975 } 976 977 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 978 uint64_t Address, const void *Decoder) { 979 DecodeStatus S = MCDisassembler::Success; 980 if (RegNo == 13 || RegNo == 15) 981 S = MCDisassembler::SoftFail; 982 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 983 return S; 984 } 985 986 static const uint16_t SPRDecoderTable[] = { 987 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 988 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 989 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 990 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 991 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 992 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 993 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 994 ARM::S28, ARM::S29, ARM::S30, ARM::S31 995 }; 996 997 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 998 uint64_t Address, const void *Decoder) { 999 if (RegNo > 31) 1000 return MCDisassembler::Fail; 1001 1002 unsigned Register = SPRDecoderTable[RegNo]; 1003 Inst.addOperand(MCOperand::CreateReg(Register)); 1004 return MCDisassembler::Success; 1005 } 1006 1007 static const uint16_t DPRDecoderTable[] = { 1008 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1009 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1010 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1011 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1012 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1013 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1014 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1015 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1016 }; 1017 1018 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1019 uint64_t Address, const void *Decoder) { 1020 if (RegNo > 31) 1021 return MCDisassembler::Fail; 1022 1023 unsigned Register = DPRDecoderTable[RegNo]; 1024 Inst.addOperand(MCOperand::CreateReg(Register)); 1025 return MCDisassembler::Success; 1026 } 1027 1028 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1029 uint64_t Address, const void *Decoder) { 1030 if (RegNo > 7) 1031 return MCDisassembler::Fail; 1032 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1033 } 1034 1035 static DecodeStatus 1036 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1037 uint64_t Address, const void *Decoder) { 1038 if (RegNo > 15) 1039 return MCDisassembler::Fail; 1040 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1041 } 1042 1043 static const uint16_t QPRDecoderTable[] = { 1044 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1045 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1046 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1047 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1048 }; 1049 1050 1051 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1052 uint64_t Address, const void *Decoder) { 1053 if (RegNo > 31 || (RegNo & 1) != 0) 1054 return MCDisassembler::Fail; 1055 RegNo >>= 1; 1056 1057 unsigned Register = QPRDecoderTable[RegNo]; 1058 Inst.addOperand(MCOperand::CreateReg(Register)); 1059 return MCDisassembler::Success; 1060 } 1061 1062 static const uint16_t DPairDecoderTable[] = { 1063 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1064 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1065 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1066 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1067 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1068 ARM::Q15 1069 }; 1070 1071 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1072 uint64_t Address, const void *Decoder) { 1073 if (RegNo > 30) 1074 return MCDisassembler::Fail; 1075 1076 unsigned Register = DPairDecoderTable[RegNo]; 1077 Inst.addOperand(MCOperand::CreateReg(Register)); 1078 return MCDisassembler::Success; 1079 } 1080 1081 static const uint16_t DPairSpacedDecoderTable[] = { 1082 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1083 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1084 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1085 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1086 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1087 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1088 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1089 ARM::D28_D30, ARM::D29_D31 1090 }; 1091 1092 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1093 unsigned RegNo, 1094 uint64_t Address, 1095 const void *Decoder) { 1096 if (RegNo > 29) 1097 return MCDisassembler::Fail; 1098 1099 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1100 Inst.addOperand(MCOperand::CreateReg(Register)); 1101 return MCDisassembler::Success; 1102 } 1103 1104 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1105 uint64_t Address, const void *Decoder) { 1106 if (Val == 0xF) return MCDisassembler::Fail; 1107 // AL predicate is not allowed on Thumb1 branches. 1108 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1109 return MCDisassembler::Fail; 1110 Inst.addOperand(MCOperand::CreateImm(Val)); 1111 if (Val == ARMCC::AL) { 1112 Inst.addOperand(MCOperand::CreateReg(0)); 1113 } else 1114 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1115 return MCDisassembler::Success; 1116 } 1117 1118 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1119 uint64_t Address, const void *Decoder) { 1120 if (Val) 1121 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1122 else 1123 Inst.addOperand(MCOperand::CreateReg(0)); 1124 return MCDisassembler::Success; 1125 } 1126 1127 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1128 uint64_t Address, const void *Decoder) { 1129 uint32_t imm = Val & 0xFF; 1130 uint32_t rot = (Val & 0xF00) >> 7; 1131 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1132 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1133 return MCDisassembler::Success; 1134 } 1135 1136 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1137 uint64_t Address, const void *Decoder) { 1138 DecodeStatus S = MCDisassembler::Success; 1139 1140 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1141 unsigned type = fieldFromInstruction(Val, 5, 2); 1142 unsigned imm = fieldFromInstruction(Val, 7, 5); 1143 1144 // Register-immediate 1145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1146 return MCDisassembler::Fail; 1147 1148 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1149 switch (type) { 1150 case 0: 1151 Shift = ARM_AM::lsl; 1152 break; 1153 case 1: 1154 Shift = ARM_AM::lsr; 1155 break; 1156 case 2: 1157 Shift = ARM_AM::asr; 1158 break; 1159 case 3: 1160 Shift = ARM_AM::ror; 1161 break; 1162 } 1163 1164 if (Shift == ARM_AM::ror && imm == 0) 1165 Shift = ARM_AM::rrx; 1166 1167 unsigned Op = Shift | (imm << 3); 1168 Inst.addOperand(MCOperand::CreateImm(Op)); 1169 1170 return S; 1171 } 1172 1173 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1174 uint64_t Address, const void *Decoder) { 1175 DecodeStatus S = MCDisassembler::Success; 1176 1177 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1178 unsigned type = fieldFromInstruction(Val, 5, 2); 1179 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1180 1181 // Register-register 1182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1183 return MCDisassembler::Fail; 1184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1185 return MCDisassembler::Fail; 1186 1187 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1188 switch (type) { 1189 case 0: 1190 Shift = ARM_AM::lsl; 1191 break; 1192 case 1: 1193 Shift = ARM_AM::lsr; 1194 break; 1195 case 2: 1196 Shift = ARM_AM::asr; 1197 break; 1198 case 3: 1199 Shift = ARM_AM::ror; 1200 break; 1201 } 1202 1203 Inst.addOperand(MCOperand::CreateImm(Shift)); 1204 1205 return S; 1206 } 1207 1208 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1209 uint64_t Address, const void *Decoder) { 1210 DecodeStatus S = MCDisassembler::Success; 1211 1212 bool NeedDisjointWriteback = false; 1213 unsigned WritebackReg = 0; 1214 switch (Inst.getOpcode()) { 1215 default: 1216 break; 1217 case ARM::LDMIA_UPD: 1218 case ARM::LDMDB_UPD: 1219 case ARM::LDMIB_UPD: 1220 case ARM::LDMDA_UPD: 1221 case ARM::t2LDMIA_UPD: 1222 case ARM::t2LDMDB_UPD: 1223 case ARM::t2STMIA_UPD: 1224 case ARM::t2STMDB_UPD: 1225 NeedDisjointWriteback = true; 1226 WritebackReg = Inst.getOperand(0).getReg(); 1227 break; 1228 } 1229 1230 // Empty register lists are not allowed. 1231 if (Val == 0) return MCDisassembler::Fail; 1232 for (unsigned i = 0; i < 16; ++i) { 1233 if (Val & (1 << i)) { 1234 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1235 return MCDisassembler::Fail; 1236 // Writeback not allowed if Rn is in the target list. 1237 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1238 Check(S, MCDisassembler::SoftFail); 1239 } 1240 } 1241 1242 return S; 1243 } 1244 1245 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1246 uint64_t Address, const void *Decoder) { 1247 DecodeStatus S = MCDisassembler::Success; 1248 1249 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1250 unsigned regs = fieldFromInstruction(Val, 0, 8); 1251 1252 // In case of unpredictable encoding, tweak the operands. 1253 if (regs == 0 || (Vd + regs) > 32) { 1254 regs = Vd + regs > 32 ? 32 - Vd : regs; 1255 regs = std::max( 1u, regs); 1256 S = MCDisassembler::SoftFail; 1257 } 1258 1259 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1260 return MCDisassembler::Fail; 1261 for (unsigned i = 0; i < (regs - 1); ++i) { 1262 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1263 return MCDisassembler::Fail; 1264 } 1265 1266 return S; 1267 } 1268 1269 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1270 uint64_t Address, const void *Decoder) { 1271 DecodeStatus S = MCDisassembler::Success; 1272 1273 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1274 unsigned regs = fieldFromInstruction(Val, 1, 7); 1275 1276 // In case of unpredictable encoding, tweak the operands. 1277 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1278 regs = Vd + regs > 32 ? 32 - Vd : regs; 1279 regs = std::max( 1u, regs); 1280 regs = std::min(16u, regs); 1281 S = MCDisassembler::SoftFail; 1282 } 1283 1284 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1285 return MCDisassembler::Fail; 1286 for (unsigned i = 0; i < (regs - 1); ++i) { 1287 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1288 return MCDisassembler::Fail; 1289 } 1290 1291 return S; 1292 } 1293 1294 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1295 uint64_t Address, const void *Decoder) { 1296 // This operand encodes a mask of contiguous zeros between a specified MSB 1297 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1298 // the mask of all bits LSB-and-lower, and then xor them to create 1299 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1300 // create the final mask. 1301 unsigned msb = fieldFromInstruction(Val, 5, 5); 1302 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1303 1304 DecodeStatus S = MCDisassembler::Success; 1305 if (lsb > msb) { 1306 Check(S, MCDisassembler::SoftFail); 1307 // The check above will cause the warning for the "potentially undefined 1308 // instruction encoding" but we can't build a bad MCOperand value here 1309 // with a lsb > msb or else printing the MCInst will cause a crash. 1310 lsb = msb; 1311 } 1312 1313 uint32_t msb_mask = 0xFFFFFFFF; 1314 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1315 uint32_t lsb_mask = (1U << lsb) - 1; 1316 1317 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1318 return S; 1319 } 1320 1321 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1322 uint64_t Address, const void *Decoder) { 1323 DecodeStatus S = MCDisassembler::Success; 1324 1325 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1326 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1327 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1328 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1329 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1330 unsigned U = fieldFromInstruction(Insn, 23, 1); 1331 1332 switch (Inst.getOpcode()) { 1333 case ARM::LDC_OFFSET: 1334 case ARM::LDC_PRE: 1335 case ARM::LDC_POST: 1336 case ARM::LDC_OPTION: 1337 case ARM::LDCL_OFFSET: 1338 case ARM::LDCL_PRE: 1339 case ARM::LDCL_POST: 1340 case ARM::LDCL_OPTION: 1341 case ARM::STC_OFFSET: 1342 case ARM::STC_PRE: 1343 case ARM::STC_POST: 1344 case ARM::STC_OPTION: 1345 case ARM::STCL_OFFSET: 1346 case ARM::STCL_PRE: 1347 case ARM::STCL_POST: 1348 case ARM::STCL_OPTION: 1349 case ARM::t2LDC_OFFSET: 1350 case ARM::t2LDC_PRE: 1351 case ARM::t2LDC_POST: 1352 case ARM::t2LDC_OPTION: 1353 case ARM::t2LDCL_OFFSET: 1354 case ARM::t2LDCL_PRE: 1355 case ARM::t2LDCL_POST: 1356 case ARM::t2LDCL_OPTION: 1357 case ARM::t2STC_OFFSET: 1358 case ARM::t2STC_PRE: 1359 case ARM::t2STC_POST: 1360 case ARM::t2STC_OPTION: 1361 case ARM::t2STCL_OFFSET: 1362 case ARM::t2STCL_PRE: 1363 case ARM::t2STCL_POST: 1364 case ARM::t2STCL_OPTION: 1365 if (coproc == 0xA || coproc == 0xB) 1366 return MCDisassembler::Fail; 1367 break; 1368 default: 1369 break; 1370 } 1371 1372 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 1373 .getFeatureBits(); 1374 if ((featureBits & ARM::HasV8Ops) && (coproc != 14)) 1375 return MCDisassembler::Fail; 1376 1377 Inst.addOperand(MCOperand::CreateImm(coproc)); 1378 Inst.addOperand(MCOperand::CreateImm(CRd)); 1379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1380 return MCDisassembler::Fail; 1381 1382 switch (Inst.getOpcode()) { 1383 case ARM::t2LDC2_OFFSET: 1384 case ARM::t2LDC2L_OFFSET: 1385 case ARM::t2LDC2_PRE: 1386 case ARM::t2LDC2L_PRE: 1387 case ARM::t2STC2_OFFSET: 1388 case ARM::t2STC2L_OFFSET: 1389 case ARM::t2STC2_PRE: 1390 case ARM::t2STC2L_PRE: 1391 case ARM::LDC2_OFFSET: 1392 case ARM::LDC2L_OFFSET: 1393 case ARM::LDC2_PRE: 1394 case ARM::LDC2L_PRE: 1395 case ARM::STC2_OFFSET: 1396 case ARM::STC2L_OFFSET: 1397 case ARM::STC2_PRE: 1398 case ARM::STC2L_PRE: 1399 case ARM::t2LDC_OFFSET: 1400 case ARM::t2LDCL_OFFSET: 1401 case ARM::t2LDC_PRE: 1402 case ARM::t2LDCL_PRE: 1403 case ARM::t2STC_OFFSET: 1404 case ARM::t2STCL_OFFSET: 1405 case ARM::t2STC_PRE: 1406 case ARM::t2STCL_PRE: 1407 case ARM::LDC_OFFSET: 1408 case ARM::LDCL_OFFSET: 1409 case ARM::LDC_PRE: 1410 case ARM::LDCL_PRE: 1411 case ARM::STC_OFFSET: 1412 case ARM::STCL_OFFSET: 1413 case ARM::STC_PRE: 1414 case ARM::STCL_PRE: 1415 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1416 Inst.addOperand(MCOperand::CreateImm(imm)); 1417 break; 1418 case ARM::t2LDC2_POST: 1419 case ARM::t2LDC2L_POST: 1420 case ARM::t2STC2_POST: 1421 case ARM::t2STC2L_POST: 1422 case ARM::LDC2_POST: 1423 case ARM::LDC2L_POST: 1424 case ARM::STC2_POST: 1425 case ARM::STC2L_POST: 1426 case ARM::t2LDC_POST: 1427 case ARM::t2LDCL_POST: 1428 case ARM::t2STC_POST: 1429 case ARM::t2STCL_POST: 1430 case ARM::LDC_POST: 1431 case ARM::LDCL_POST: 1432 case ARM::STC_POST: 1433 case ARM::STCL_POST: 1434 imm |= U << 8; 1435 // fall through. 1436 default: 1437 // The 'option' variant doesn't encode 'U' in the immediate since 1438 // the immediate is unsigned [0,255]. 1439 Inst.addOperand(MCOperand::CreateImm(imm)); 1440 break; 1441 } 1442 1443 switch (Inst.getOpcode()) { 1444 case ARM::LDC_OFFSET: 1445 case ARM::LDC_PRE: 1446 case ARM::LDC_POST: 1447 case ARM::LDC_OPTION: 1448 case ARM::LDCL_OFFSET: 1449 case ARM::LDCL_PRE: 1450 case ARM::LDCL_POST: 1451 case ARM::LDCL_OPTION: 1452 case ARM::STC_OFFSET: 1453 case ARM::STC_PRE: 1454 case ARM::STC_POST: 1455 case ARM::STC_OPTION: 1456 case ARM::STCL_OFFSET: 1457 case ARM::STCL_PRE: 1458 case ARM::STCL_POST: 1459 case ARM::STCL_OPTION: 1460 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1461 return MCDisassembler::Fail; 1462 break; 1463 default: 1464 break; 1465 } 1466 1467 return S; 1468 } 1469 1470 static DecodeStatus 1471 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1472 uint64_t Address, const void *Decoder) { 1473 DecodeStatus S = MCDisassembler::Success; 1474 1475 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1476 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1477 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1478 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1479 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1480 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1481 unsigned P = fieldFromInstruction(Insn, 24, 1); 1482 unsigned W = fieldFromInstruction(Insn, 21, 1); 1483 1484 // On stores, the writeback operand precedes Rt. 1485 switch (Inst.getOpcode()) { 1486 case ARM::STR_POST_IMM: 1487 case ARM::STR_POST_REG: 1488 case ARM::STRB_POST_IMM: 1489 case ARM::STRB_POST_REG: 1490 case ARM::STRT_POST_REG: 1491 case ARM::STRT_POST_IMM: 1492 case ARM::STRBT_POST_REG: 1493 case ARM::STRBT_POST_IMM: 1494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1495 return MCDisassembler::Fail; 1496 break; 1497 default: 1498 break; 1499 } 1500 1501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1502 return MCDisassembler::Fail; 1503 1504 // On loads, the writeback operand comes after Rt. 1505 switch (Inst.getOpcode()) { 1506 case ARM::LDR_POST_IMM: 1507 case ARM::LDR_POST_REG: 1508 case ARM::LDRB_POST_IMM: 1509 case ARM::LDRB_POST_REG: 1510 case ARM::LDRBT_POST_REG: 1511 case ARM::LDRBT_POST_IMM: 1512 case ARM::LDRT_POST_REG: 1513 case ARM::LDRT_POST_IMM: 1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1515 return MCDisassembler::Fail; 1516 break; 1517 default: 1518 break; 1519 } 1520 1521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1522 return MCDisassembler::Fail; 1523 1524 ARM_AM::AddrOpc Op = ARM_AM::add; 1525 if (!fieldFromInstruction(Insn, 23, 1)) 1526 Op = ARM_AM::sub; 1527 1528 bool writeback = (P == 0) || (W == 1); 1529 unsigned idx_mode = 0; 1530 if (P && writeback) 1531 idx_mode = ARMII::IndexModePre; 1532 else if (!P && writeback) 1533 idx_mode = ARMII::IndexModePost; 1534 1535 if (writeback && (Rn == 15 || Rn == Rt)) 1536 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1537 1538 if (reg) { 1539 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1540 return MCDisassembler::Fail; 1541 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1542 switch( fieldFromInstruction(Insn, 5, 2)) { 1543 case 0: 1544 Opc = ARM_AM::lsl; 1545 break; 1546 case 1: 1547 Opc = ARM_AM::lsr; 1548 break; 1549 case 2: 1550 Opc = ARM_AM::asr; 1551 break; 1552 case 3: 1553 Opc = ARM_AM::ror; 1554 break; 1555 default: 1556 return MCDisassembler::Fail; 1557 } 1558 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1559 if (Opc == ARM_AM::ror && amt == 0) 1560 Opc = ARM_AM::rrx; 1561 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1562 1563 Inst.addOperand(MCOperand::CreateImm(imm)); 1564 } else { 1565 Inst.addOperand(MCOperand::CreateReg(0)); 1566 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1567 Inst.addOperand(MCOperand::CreateImm(tmp)); 1568 } 1569 1570 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1571 return MCDisassembler::Fail; 1572 1573 return S; 1574 } 1575 1576 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1577 uint64_t Address, const void *Decoder) { 1578 DecodeStatus S = MCDisassembler::Success; 1579 1580 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1581 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1582 unsigned type = fieldFromInstruction(Val, 5, 2); 1583 unsigned imm = fieldFromInstruction(Val, 7, 5); 1584 unsigned U = fieldFromInstruction(Val, 12, 1); 1585 1586 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1587 switch (type) { 1588 case 0: 1589 ShOp = ARM_AM::lsl; 1590 break; 1591 case 1: 1592 ShOp = ARM_AM::lsr; 1593 break; 1594 case 2: 1595 ShOp = ARM_AM::asr; 1596 break; 1597 case 3: 1598 ShOp = ARM_AM::ror; 1599 break; 1600 } 1601 1602 if (ShOp == ARM_AM::ror && imm == 0) 1603 ShOp = ARM_AM::rrx; 1604 1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1606 return MCDisassembler::Fail; 1607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1608 return MCDisassembler::Fail; 1609 unsigned shift; 1610 if (U) 1611 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1612 else 1613 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1614 Inst.addOperand(MCOperand::CreateImm(shift)); 1615 1616 return S; 1617 } 1618 1619 static DecodeStatus 1620 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1621 uint64_t Address, const void *Decoder) { 1622 DecodeStatus S = MCDisassembler::Success; 1623 1624 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1625 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1626 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1627 unsigned type = fieldFromInstruction(Insn, 22, 1); 1628 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1629 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1630 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1631 unsigned W = fieldFromInstruction(Insn, 21, 1); 1632 unsigned P = fieldFromInstruction(Insn, 24, 1); 1633 unsigned Rt2 = Rt + 1; 1634 1635 bool writeback = (W == 1) | (P == 0); 1636 1637 // For {LD,ST}RD, Rt must be even, else undefined. 1638 switch (Inst.getOpcode()) { 1639 case ARM::STRD: 1640 case ARM::STRD_PRE: 1641 case ARM::STRD_POST: 1642 case ARM::LDRD: 1643 case ARM::LDRD_PRE: 1644 case ARM::LDRD_POST: 1645 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1646 break; 1647 default: 1648 break; 1649 } 1650 switch (Inst.getOpcode()) { 1651 case ARM::STRD: 1652 case ARM::STRD_PRE: 1653 case ARM::STRD_POST: 1654 if (P == 0 && W == 1) 1655 S = MCDisassembler::SoftFail; 1656 1657 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1658 S = MCDisassembler::SoftFail; 1659 if (type && Rm == 15) 1660 S = MCDisassembler::SoftFail; 1661 if (Rt2 == 15) 1662 S = MCDisassembler::SoftFail; 1663 if (!type && fieldFromInstruction(Insn, 8, 4)) 1664 S = MCDisassembler::SoftFail; 1665 break; 1666 case ARM::STRH: 1667 case ARM::STRH_PRE: 1668 case ARM::STRH_POST: 1669 if (Rt == 15) 1670 S = MCDisassembler::SoftFail; 1671 if (writeback && (Rn == 15 || Rn == Rt)) 1672 S = MCDisassembler::SoftFail; 1673 if (!type && Rm == 15) 1674 S = MCDisassembler::SoftFail; 1675 break; 1676 case ARM::LDRD: 1677 case ARM::LDRD_PRE: 1678 case ARM::LDRD_POST: 1679 if (type && Rn == 15){ 1680 if (Rt2 == 15) 1681 S = MCDisassembler::SoftFail; 1682 break; 1683 } 1684 if (P == 0 && W == 1) 1685 S = MCDisassembler::SoftFail; 1686 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1687 S = MCDisassembler::SoftFail; 1688 if (!type && writeback && Rn == 15) 1689 S = MCDisassembler::SoftFail; 1690 if (writeback && (Rn == Rt || Rn == Rt2)) 1691 S = MCDisassembler::SoftFail; 1692 break; 1693 case ARM::LDRH: 1694 case ARM::LDRH_PRE: 1695 case ARM::LDRH_POST: 1696 if (type && Rn == 15){ 1697 if (Rt == 15) 1698 S = MCDisassembler::SoftFail; 1699 break; 1700 } 1701 if (Rt == 15) 1702 S = MCDisassembler::SoftFail; 1703 if (!type && Rm == 15) 1704 S = MCDisassembler::SoftFail; 1705 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1706 S = MCDisassembler::SoftFail; 1707 break; 1708 case ARM::LDRSH: 1709 case ARM::LDRSH_PRE: 1710 case ARM::LDRSH_POST: 1711 case ARM::LDRSB: 1712 case ARM::LDRSB_PRE: 1713 case ARM::LDRSB_POST: 1714 if (type && Rn == 15){ 1715 if (Rt == 15) 1716 S = MCDisassembler::SoftFail; 1717 break; 1718 } 1719 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1720 S = MCDisassembler::SoftFail; 1721 if (!type && (Rt == 15 || Rm == 15)) 1722 S = MCDisassembler::SoftFail; 1723 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1724 S = MCDisassembler::SoftFail; 1725 break; 1726 default: 1727 break; 1728 } 1729 1730 if (writeback) { // Writeback 1731 if (P) 1732 U |= ARMII::IndexModePre << 9; 1733 else 1734 U |= ARMII::IndexModePost << 9; 1735 1736 // On stores, the writeback operand precedes Rt. 1737 switch (Inst.getOpcode()) { 1738 case ARM::STRD: 1739 case ARM::STRD_PRE: 1740 case ARM::STRD_POST: 1741 case ARM::STRH: 1742 case ARM::STRH_PRE: 1743 case ARM::STRH_POST: 1744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1745 return MCDisassembler::Fail; 1746 break; 1747 default: 1748 break; 1749 } 1750 } 1751 1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1753 return MCDisassembler::Fail; 1754 switch (Inst.getOpcode()) { 1755 case ARM::STRD: 1756 case ARM::STRD_PRE: 1757 case ARM::STRD_POST: 1758 case ARM::LDRD: 1759 case ARM::LDRD_PRE: 1760 case ARM::LDRD_POST: 1761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1762 return MCDisassembler::Fail; 1763 break; 1764 default: 1765 break; 1766 } 1767 1768 if (writeback) { 1769 // On loads, the writeback operand comes after Rt. 1770 switch (Inst.getOpcode()) { 1771 case ARM::LDRD: 1772 case ARM::LDRD_PRE: 1773 case ARM::LDRD_POST: 1774 case ARM::LDRH: 1775 case ARM::LDRH_PRE: 1776 case ARM::LDRH_POST: 1777 case ARM::LDRSH: 1778 case ARM::LDRSH_PRE: 1779 case ARM::LDRSH_POST: 1780 case ARM::LDRSB: 1781 case ARM::LDRSB_PRE: 1782 case ARM::LDRSB_POST: 1783 case ARM::LDRHTr: 1784 case ARM::LDRSBTr: 1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1786 return MCDisassembler::Fail; 1787 break; 1788 default: 1789 break; 1790 } 1791 } 1792 1793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 1796 if (type) { 1797 Inst.addOperand(MCOperand::CreateReg(0)); 1798 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1799 } else { 1800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1801 return MCDisassembler::Fail; 1802 Inst.addOperand(MCOperand::CreateImm(U)); 1803 } 1804 1805 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1806 return MCDisassembler::Fail; 1807 1808 return S; 1809 } 1810 1811 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1812 uint64_t Address, const void *Decoder) { 1813 DecodeStatus S = MCDisassembler::Success; 1814 1815 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1816 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1817 1818 switch (mode) { 1819 case 0: 1820 mode = ARM_AM::da; 1821 break; 1822 case 1: 1823 mode = ARM_AM::ia; 1824 break; 1825 case 2: 1826 mode = ARM_AM::db; 1827 break; 1828 case 3: 1829 mode = ARM_AM::ib; 1830 break; 1831 } 1832 1833 Inst.addOperand(MCOperand::CreateImm(mode)); 1834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1835 return MCDisassembler::Fail; 1836 1837 return S; 1838 } 1839 1840 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1841 uint64_t Address, const void *Decoder) { 1842 DecodeStatus S = MCDisassembler::Success; 1843 1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1845 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1846 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1847 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1848 1849 if (pred == 0xF) 1850 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1851 1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1853 return MCDisassembler::Fail; 1854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1855 return MCDisassembler::Fail; 1856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1857 return MCDisassembler::Fail; 1858 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1859 return MCDisassembler::Fail; 1860 return S; 1861 } 1862 1863 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1864 unsigned Insn, 1865 uint64_t Address, const void *Decoder) { 1866 DecodeStatus S = MCDisassembler::Success; 1867 1868 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1869 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1870 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1871 1872 if (pred == 0xF) { 1873 // Ambiguous with RFE and SRS 1874 switch (Inst.getOpcode()) { 1875 case ARM::LDMDA: 1876 Inst.setOpcode(ARM::RFEDA); 1877 break; 1878 case ARM::LDMDA_UPD: 1879 Inst.setOpcode(ARM::RFEDA_UPD); 1880 break; 1881 case ARM::LDMDB: 1882 Inst.setOpcode(ARM::RFEDB); 1883 break; 1884 case ARM::LDMDB_UPD: 1885 Inst.setOpcode(ARM::RFEDB_UPD); 1886 break; 1887 case ARM::LDMIA: 1888 Inst.setOpcode(ARM::RFEIA); 1889 break; 1890 case ARM::LDMIA_UPD: 1891 Inst.setOpcode(ARM::RFEIA_UPD); 1892 break; 1893 case ARM::LDMIB: 1894 Inst.setOpcode(ARM::RFEIB); 1895 break; 1896 case ARM::LDMIB_UPD: 1897 Inst.setOpcode(ARM::RFEIB_UPD); 1898 break; 1899 case ARM::STMDA: 1900 Inst.setOpcode(ARM::SRSDA); 1901 break; 1902 case ARM::STMDA_UPD: 1903 Inst.setOpcode(ARM::SRSDA_UPD); 1904 break; 1905 case ARM::STMDB: 1906 Inst.setOpcode(ARM::SRSDB); 1907 break; 1908 case ARM::STMDB_UPD: 1909 Inst.setOpcode(ARM::SRSDB_UPD); 1910 break; 1911 case ARM::STMIA: 1912 Inst.setOpcode(ARM::SRSIA); 1913 break; 1914 case ARM::STMIA_UPD: 1915 Inst.setOpcode(ARM::SRSIA_UPD); 1916 break; 1917 case ARM::STMIB: 1918 Inst.setOpcode(ARM::SRSIB); 1919 break; 1920 case ARM::STMIB_UPD: 1921 Inst.setOpcode(ARM::SRSIB_UPD); 1922 break; 1923 default: 1924 return MCDisassembler::Fail; 1925 } 1926 1927 // For stores (which become SRS's, the only operand is the mode. 1928 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1929 // Check SRS encoding constraints 1930 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1931 fieldFromInstruction(Insn, 20, 1) == 0)) 1932 return MCDisassembler::Fail; 1933 1934 Inst.addOperand( 1935 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1936 return S; 1937 } 1938 1939 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1940 } 1941 1942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1943 return MCDisassembler::Fail; 1944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1945 return MCDisassembler::Fail; // Tied 1946 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1947 return MCDisassembler::Fail; 1948 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 1951 return S; 1952 } 1953 1954 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1955 uint64_t Address, const void *Decoder) { 1956 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1957 unsigned M = fieldFromInstruction(Insn, 17, 1); 1958 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1959 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1960 1961 DecodeStatus S = MCDisassembler::Success; 1962 1963 // This decoder is called from multiple location that do not check 1964 // the full encoding is valid before they do. 1965 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1966 fieldFromInstruction(Insn, 16, 1) != 0 || 1967 fieldFromInstruction(Insn, 20, 8) != 0x10) 1968 return MCDisassembler::Fail; 1969 1970 // imod == '01' --> UNPREDICTABLE 1971 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1972 // return failure here. The '01' imod value is unprintable, so there's 1973 // nothing useful we could do even if we returned UNPREDICTABLE. 1974 1975 if (imod == 1) return MCDisassembler::Fail; 1976 1977 if (imod && M) { 1978 Inst.setOpcode(ARM::CPS3p); 1979 Inst.addOperand(MCOperand::CreateImm(imod)); 1980 Inst.addOperand(MCOperand::CreateImm(iflags)); 1981 Inst.addOperand(MCOperand::CreateImm(mode)); 1982 } else if (imod && !M) { 1983 Inst.setOpcode(ARM::CPS2p); 1984 Inst.addOperand(MCOperand::CreateImm(imod)); 1985 Inst.addOperand(MCOperand::CreateImm(iflags)); 1986 if (mode) S = MCDisassembler::SoftFail; 1987 } else if (!imod && M) { 1988 Inst.setOpcode(ARM::CPS1p); 1989 Inst.addOperand(MCOperand::CreateImm(mode)); 1990 if (iflags) S = MCDisassembler::SoftFail; 1991 } else { 1992 // imod == '00' && M == '0' --> UNPREDICTABLE 1993 Inst.setOpcode(ARM::CPS1p); 1994 Inst.addOperand(MCOperand::CreateImm(mode)); 1995 S = MCDisassembler::SoftFail; 1996 } 1997 1998 return S; 1999 } 2000 2001 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2002 uint64_t Address, const void *Decoder) { 2003 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2004 unsigned M = fieldFromInstruction(Insn, 8, 1); 2005 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2006 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2007 2008 DecodeStatus S = MCDisassembler::Success; 2009 2010 // imod == '01' --> UNPREDICTABLE 2011 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2012 // return failure here. The '01' imod value is unprintable, so there's 2013 // nothing useful we could do even if we returned UNPREDICTABLE. 2014 2015 if (imod == 1) return MCDisassembler::Fail; 2016 2017 if (imod && M) { 2018 Inst.setOpcode(ARM::t2CPS3p); 2019 Inst.addOperand(MCOperand::CreateImm(imod)); 2020 Inst.addOperand(MCOperand::CreateImm(iflags)); 2021 Inst.addOperand(MCOperand::CreateImm(mode)); 2022 } else if (imod && !M) { 2023 Inst.setOpcode(ARM::t2CPS2p); 2024 Inst.addOperand(MCOperand::CreateImm(imod)); 2025 Inst.addOperand(MCOperand::CreateImm(iflags)); 2026 if (mode) S = MCDisassembler::SoftFail; 2027 } else if (!imod && M) { 2028 Inst.setOpcode(ARM::t2CPS1p); 2029 Inst.addOperand(MCOperand::CreateImm(mode)); 2030 if (iflags) S = MCDisassembler::SoftFail; 2031 } else { 2032 // imod == '00' && M == '0' --> this is a HINT instruction 2033 int imm = fieldFromInstruction(Insn, 0, 8); 2034 // HINT are defined only for immediate in [0..4] 2035 if(imm > 4) return MCDisassembler::Fail; 2036 Inst.setOpcode(ARM::t2HINT); 2037 Inst.addOperand(MCOperand::CreateImm(imm)); 2038 } 2039 2040 return S; 2041 } 2042 2043 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2044 uint64_t Address, const void *Decoder) { 2045 DecodeStatus S = MCDisassembler::Success; 2046 2047 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2048 unsigned imm = 0; 2049 2050 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2051 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2052 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2053 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2054 2055 if (Inst.getOpcode() == ARM::t2MOVTi16) 2056 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2057 return MCDisassembler::Fail; 2058 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2059 return MCDisassembler::Fail; 2060 2061 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2062 Inst.addOperand(MCOperand::CreateImm(imm)); 2063 2064 return S; 2065 } 2066 2067 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2068 uint64_t Address, const void *Decoder) { 2069 DecodeStatus S = MCDisassembler::Success; 2070 2071 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2072 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2073 unsigned imm = 0; 2074 2075 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2076 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2077 2078 if (Inst.getOpcode() == ARM::MOVTi16) 2079 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2080 return MCDisassembler::Fail; 2081 2082 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2083 return MCDisassembler::Fail; 2084 2085 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2086 Inst.addOperand(MCOperand::CreateImm(imm)); 2087 2088 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2089 return MCDisassembler::Fail; 2090 2091 return S; 2092 } 2093 2094 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2095 uint64_t Address, const void *Decoder) { 2096 DecodeStatus S = MCDisassembler::Success; 2097 2098 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2099 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2100 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2101 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2102 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2103 2104 if (pred == 0xF) 2105 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2106 2107 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2108 return MCDisassembler::Fail; 2109 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2114 return MCDisassembler::Fail; 2115 2116 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2117 return MCDisassembler::Fail; 2118 2119 return S; 2120 } 2121 2122 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2123 uint64_t Address, const void *Decoder) { 2124 DecodeStatus S = MCDisassembler::Success; 2125 2126 unsigned add = fieldFromInstruction(Val, 12, 1); 2127 unsigned imm = fieldFromInstruction(Val, 0, 12); 2128 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2129 2130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2131 return MCDisassembler::Fail; 2132 2133 if (!add) imm *= -1; 2134 if (imm == 0 && !add) imm = INT32_MIN; 2135 Inst.addOperand(MCOperand::CreateImm(imm)); 2136 if (Rn == 15) 2137 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2138 2139 return S; 2140 } 2141 2142 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2143 uint64_t Address, const void *Decoder) { 2144 DecodeStatus S = MCDisassembler::Success; 2145 2146 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2147 unsigned U = fieldFromInstruction(Val, 8, 1); 2148 unsigned imm = fieldFromInstruction(Val, 0, 8); 2149 2150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2151 return MCDisassembler::Fail; 2152 2153 if (U) 2154 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2155 else 2156 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2157 2158 return S; 2159 } 2160 2161 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2162 uint64_t Address, const void *Decoder) { 2163 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2164 } 2165 2166 static DecodeStatus 2167 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2168 uint64_t Address, const void *Decoder) { 2169 DecodeStatus Status = MCDisassembler::Success; 2170 2171 // Note the J1 and J2 values are from the encoded instruction. So here 2172 // change them to I1 and I2 values via as documented: 2173 // I1 = NOT(J1 EOR S); 2174 // I2 = NOT(J2 EOR S); 2175 // and build the imm32 with one trailing zero as documented: 2176 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2177 unsigned S = fieldFromInstruction(Insn, 26, 1); 2178 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2179 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2180 unsigned I1 = !(J1 ^ S); 2181 unsigned I2 = !(J2 ^ S); 2182 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2183 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2184 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2185 int imm32 = SignExtend32<25>(tmp << 1); 2186 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2187 true, 4, Inst, Decoder)) 2188 Inst.addOperand(MCOperand::CreateImm(imm32)); 2189 2190 return Status; 2191 } 2192 2193 static DecodeStatus 2194 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2195 uint64_t Address, const void *Decoder) { 2196 DecodeStatus S = MCDisassembler::Success; 2197 2198 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2199 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2200 2201 if (pred == 0xF) { 2202 Inst.setOpcode(ARM::BLXi); 2203 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2204 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2205 true, 4, Inst, Decoder)) 2206 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2207 return S; 2208 } 2209 2210 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2211 true, 4, Inst, Decoder)) 2212 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2213 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2214 return MCDisassembler::Fail; 2215 2216 return S; 2217 } 2218 2219 2220 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2221 uint64_t Address, const void *Decoder) { 2222 DecodeStatus S = MCDisassembler::Success; 2223 2224 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2225 unsigned align = fieldFromInstruction(Val, 4, 2); 2226 2227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2228 return MCDisassembler::Fail; 2229 if (!align) 2230 Inst.addOperand(MCOperand::CreateImm(0)); 2231 else 2232 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2233 2234 return S; 2235 } 2236 2237 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2238 uint64_t Address, const void *Decoder) { 2239 DecodeStatus S = MCDisassembler::Success; 2240 2241 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2242 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2243 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2244 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2245 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2246 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2247 2248 // First output register 2249 switch (Inst.getOpcode()) { 2250 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2251 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2252 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2253 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2254 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2255 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2256 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2257 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2258 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2259 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2260 return MCDisassembler::Fail; 2261 break; 2262 case ARM::VLD2b16: 2263 case ARM::VLD2b32: 2264 case ARM::VLD2b8: 2265 case ARM::VLD2b16wb_fixed: 2266 case ARM::VLD2b16wb_register: 2267 case ARM::VLD2b32wb_fixed: 2268 case ARM::VLD2b32wb_register: 2269 case ARM::VLD2b8wb_fixed: 2270 case ARM::VLD2b8wb_register: 2271 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2272 return MCDisassembler::Fail; 2273 break; 2274 default: 2275 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2276 return MCDisassembler::Fail; 2277 } 2278 2279 // Second output register 2280 switch (Inst.getOpcode()) { 2281 case ARM::VLD3d8: 2282 case ARM::VLD3d16: 2283 case ARM::VLD3d32: 2284 case ARM::VLD3d8_UPD: 2285 case ARM::VLD3d16_UPD: 2286 case ARM::VLD3d32_UPD: 2287 case ARM::VLD4d8: 2288 case ARM::VLD4d16: 2289 case ARM::VLD4d32: 2290 case ARM::VLD4d8_UPD: 2291 case ARM::VLD4d16_UPD: 2292 case ARM::VLD4d32_UPD: 2293 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2294 return MCDisassembler::Fail; 2295 break; 2296 case ARM::VLD3q8: 2297 case ARM::VLD3q16: 2298 case ARM::VLD3q32: 2299 case ARM::VLD3q8_UPD: 2300 case ARM::VLD3q16_UPD: 2301 case ARM::VLD3q32_UPD: 2302 case ARM::VLD4q8: 2303 case ARM::VLD4q16: 2304 case ARM::VLD4q32: 2305 case ARM::VLD4q8_UPD: 2306 case ARM::VLD4q16_UPD: 2307 case ARM::VLD4q32_UPD: 2308 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2309 return MCDisassembler::Fail; 2310 default: 2311 break; 2312 } 2313 2314 // Third output register 2315 switch(Inst.getOpcode()) { 2316 case ARM::VLD3d8: 2317 case ARM::VLD3d16: 2318 case ARM::VLD3d32: 2319 case ARM::VLD3d8_UPD: 2320 case ARM::VLD3d16_UPD: 2321 case ARM::VLD3d32_UPD: 2322 case ARM::VLD4d8: 2323 case ARM::VLD4d16: 2324 case ARM::VLD4d32: 2325 case ARM::VLD4d8_UPD: 2326 case ARM::VLD4d16_UPD: 2327 case ARM::VLD4d32_UPD: 2328 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2329 return MCDisassembler::Fail; 2330 break; 2331 case ARM::VLD3q8: 2332 case ARM::VLD3q16: 2333 case ARM::VLD3q32: 2334 case ARM::VLD3q8_UPD: 2335 case ARM::VLD3q16_UPD: 2336 case ARM::VLD3q32_UPD: 2337 case ARM::VLD4q8: 2338 case ARM::VLD4q16: 2339 case ARM::VLD4q32: 2340 case ARM::VLD4q8_UPD: 2341 case ARM::VLD4q16_UPD: 2342 case ARM::VLD4q32_UPD: 2343 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2344 return MCDisassembler::Fail; 2345 break; 2346 default: 2347 break; 2348 } 2349 2350 // Fourth output register 2351 switch (Inst.getOpcode()) { 2352 case ARM::VLD4d8: 2353 case ARM::VLD4d16: 2354 case ARM::VLD4d32: 2355 case ARM::VLD4d8_UPD: 2356 case ARM::VLD4d16_UPD: 2357 case ARM::VLD4d32_UPD: 2358 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2359 return MCDisassembler::Fail; 2360 break; 2361 case ARM::VLD4q8: 2362 case ARM::VLD4q16: 2363 case ARM::VLD4q32: 2364 case ARM::VLD4q8_UPD: 2365 case ARM::VLD4q16_UPD: 2366 case ARM::VLD4q32_UPD: 2367 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2368 return MCDisassembler::Fail; 2369 break; 2370 default: 2371 break; 2372 } 2373 2374 // Writeback operand 2375 switch (Inst.getOpcode()) { 2376 case ARM::VLD1d8wb_fixed: 2377 case ARM::VLD1d16wb_fixed: 2378 case ARM::VLD1d32wb_fixed: 2379 case ARM::VLD1d64wb_fixed: 2380 case ARM::VLD1d8wb_register: 2381 case ARM::VLD1d16wb_register: 2382 case ARM::VLD1d32wb_register: 2383 case ARM::VLD1d64wb_register: 2384 case ARM::VLD1q8wb_fixed: 2385 case ARM::VLD1q16wb_fixed: 2386 case ARM::VLD1q32wb_fixed: 2387 case ARM::VLD1q64wb_fixed: 2388 case ARM::VLD1q8wb_register: 2389 case ARM::VLD1q16wb_register: 2390 case ARM::VLD1q32wb_register: 2391 case ARM::VLD1q64wb_register: 2392 case ARM::VLD1d8Twb_fixed: 2393 case ARM::VLD1d8Twb_register: 2394 case ARM::VLD1d16Twb_fixed: 2395 case ARM::VLD1d16Twb_register: 2396 case ARM::VLD1d32Twb_fixed: 2397 case ARM::VLD1d32Twb_register: 2398 case ARM::VLD1d64Twb_fixed: 2399 case ARM::VLD1d64Twb_register: 2400 case ARM::VLD1d8Qwb_fixed: 2401 case ARM::VLD1d8Qwb_register: 2402 case ARM::VLD1d16Qwb_fixed: 2403 case ARM::VLD1d16Qwb_register: 2404 case ARM::VLD1d32Qwb_fixed: 2405 case ARM::VLD1d32Qwb_register: 2406 case ARM::VLD1d64Qwb_fixed: 2407 case ARM::VLD1d64Qwb_register: 2408 case ARM::VLD2d8wb_fixed: 2409 case ARM::VLD2d16wb_fixed: 2410 case ARM::VLD2d32wb_fixed: 2411 case ARM::VLD2q8wb_fixed: 2412 case ARM::VLD2q16wb_fixed: 2413 case ARM::VLD2q32wb_fixed: 2414 case ARM::VLD2d8wb_register: 2415 case ARM::VLD2d16wb_register: 2416 case ARM::VLD2d32wb_register: 2417 case ARM::VLD2q8wb_register: 2418 case ARM::VLD2q16wb_register: 2419 case ARM::VLD2q32wb_register: 2420 case ARM::VLD2b8wb_fixed: 2421 case ARM::VLD2b16wb_fixed: 2422 case ARM::VLD2b32wb_fixed: 2423 case ARM::VLD2b8wb_register: 2424 case ARM::VLD2b16wb_register: 2425 case ARM::VLD2b32wb_register: 2426 Inst.addOperand(MCOperand::CreateImm(0)); 2427 break; 2428 case ARM::VLD3d8_UPD: 2429 case ARM::VLD3d16_UPD: 2430 case ARM::VLD3d32_UPD: 2431 case ARM::VLD3q8_UPD: 2432 case ARM::VLD3q16_UPD: 2433 case ARM::VLD3q32_UPD: 2434 case ARM::VLD4d8_UPD: 2435 case ARM::VLD4d16_UPD: 2436 case ARM::VLD4d32_UPD: 2437 case ARM::VLD4q8_UPD: 2438 case ARM::VLD4q16_UPD: 2439 case ARM::VLD4q32_UPD: 2440 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2441 return MCDisassembler::Fail; 2442 break; 2443 default: 2444 break; 2445 } 2446 2447 // AddrMode6 Base (register+alignment) 2448 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2449 return MCDisassembler::Fail; 2450 2451 // AddrMode6 Offset (register) 2452 switch (Inst.getOpcode()) { 2453 default: 2454 // The below have been updated to have explicit am6offset split 2455 // between fixed and register offset. For those instructions not 2456 // yet updated, we need to add an additional reg0 operand for the 2457 // fixed variant. 2458 // 2459 // The fixed offset encodes as Rm == 0xd, so we check for that. 2460 if (Rm == 0xd) { 2461 Inst.addOperand(MCOperand::CreateReg(0)); 2462 break; 2463 } 2464 // Fall through to handle the register offset variant. 2465 case ARM::VLD1d8wb_fixed: 2466 case ARM::VLD1d16wb_fixed: 2467 case ARM::VLD1d32wb_fixed: 2468 case ARM::VLD1d64wb_fixed: 2469 case ARM::VLD1d8Twb_fixed: 2470 case ARM::VLD1d16Twb_fixed: 2471 case ARM::VLD1d32Twb_fixed: 2472 case ARM::VLD1d64Twb_fixed: 2473 case ARM::VLD1d8Qwb_fixed: 2474 case ARM::VLD1d16Qwb_fixed: 2475 case ARM::VLD1d32Qwb_fixed: 2476 case ARM::VLD1d64Qwb_fixed: 2477 case ARM::VLD1d8wb_register: 2478 case ARM::VLD1d16wb_register: 2479 case ARM::VLD1d32wb_register: 2480 case ARM::VLD1d64wb_register: 2481 case ARM::VLD1q8wb_fixed: 2482 case ARM::VLD1q16wb_fixed: 2483 case ARM::VLD1q32wb_fixed: 2484 case ARM::VLD1q64wb_fixed: 2485 case ARM::VLD1q8wb_register: 2486 case ARM::VLD1q16wb_register: 2487 case ARM::VLD1q32wb_register: 2488 case ARM::VLD1q64wb_register: 2489 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2490 // variant encodes Rm == 0xf. Anything else is a register offset post- 2491 // increment and we need to add the register operand to the instruction. 2492 if (Rm != 0xD && Rm != 0xF && 2493 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2494 return MCDisassembler::Fail; 2495 break; 2496 case ARM::VLD2d8wb_fixed: 2497 case ARM::VLD2d16wb_fixed: 2498 case ARM::VLD2d32wb_fixed: 2499 case ARM::VLD2b8wb_fixed: 2500 case ARM::VLD2b16wb_fixed: 2501 case ARM::VLD2b32wb_fixed: 2502 case ARM::VLD2q8wb_fixed: 2503 case ARM::VLD2q16wb_fixed: 2504 case ARM::VLD2q32wb_fixed: 2505 break; 2506 } 2507 2508 return S; 2509 } 2510 2511 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2512 uint64_t Address, const void *Decoder) { 2513 unsigned type = fieldFromInstruction(Insn, 8, 4); 2514 unsigned align = fieldFromInstruction(Insn, 4, 2); 2515 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2516 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2517 if (type == 10 && align == 3) return MCDisassembler::Fail; 2518 2519 unsigned load = fieldFromInstruction(Insn, 21, 1); 2520 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2521 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2522 } 2523 2524 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2525 uint64_t Address, const void *Decoder) { 2526 unsigned size = fieldFromInstruction(Insn, 6, 2); 2527 if (size == 3) return MCDisassembler::Fail; 2528 2529 unsigned type = fieldFromInstruction(Insn, 8, 4); 2530 unsigned align = fieldFromInstruction(Insn, 4, 2); 2531 if (type == 8 && align == 3) return MCDisassembler::Fail; 2532 if (type == 9 && align == 3) return MCDisassembler::Fail; 2533 2534 unsigned load = fieldFromInstruction(Insn, 21, 1); 2535 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2536 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2537 } 2538 2539 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2540 uint64_t Address, const void *Decoder) { 2541 unsigned size = fieldFromInstruction(Insn, 6, 2); 2542 if (size == 3) return MCDisassembler::Fail; 2543 2544 unsigned align = fieldFromInstruction(Insn, 4, 2); 2545 if (align & 2) return MCDisassembler::Fail; 2546 2547 unsigned load = fieldFromInstruction(Insn, 21, 1); 2548 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2549 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2550 } 2551 2552 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2553 uint64_t Address, const void *Decoder) { 2554 unsigned size = fieldFromInstruction(Insn, 6, 2); 2555 if (size == 3) return MCDisassembler::Fail; 2556 2557 unsigned load = fieldFromInstruction(Insn, 21, 1); 2558 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2559 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2560 } 2561 2562 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2563 uint64_t Address, const void *Decoder) { 2564 DecodeStatus S = MCDisassembler::Success; 2565 2566 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2567 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2568 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2569 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2570 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2571 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2572 2573 // Writeback Operand 2574 switch (Inst.getOpcode()) { 2575 case ARM::VST1d8wb_fixed: 2576 case ARM::VST1d16wb_fixed: 2577 case ARM::VST1d32wb_fixed: 2578 case ARM::VST1d64wb_fixed: 2579 case ARM::VST1d8wb_register: 2580 case ARM::VST1d16wb_register: 2581 case ARM::VST1d32wb_register: 2582 case ARM::VST1d64wb_register: 2583 case ARM::VST1q8wb_fixed: 2584 case ARM::VST1q16wb_fixed: 2585 case ARM::VST1q32wb_fixed: 2586 case ARM::VST1q64wb_fixed: 2587 case ARM::VST1q8wb_register: 2588 case ARM::VST1q16wb_register: 2589 case ARM::VST1q32wb_register: 2590 case ARM::VST1q64wb_register: 2591 case ARM::VST1d8Twb_fixed: 2592 case ARM::VST1d16Twb_fixed: 2593 case ARM::VST1d32Twb_fixed: 2594 case ARM::VST1d64Twb_fixed: 2595 case ARM::VST1d8Twb_register: 2596 case ARM::VST1d16Twb_register: 2597 case ARM::VST1d32Twb_register: 2598 case ARM::VST1d64Twb_register: 2599 case ARM::VST1d8Qwb_fixed: 2600 case ARM::VST1d16Qwb_fixed: 2601 case ARM::VST1d32Qwb_fixed: 2602 case ARM::VST1d64Qwb_fixed: 2603 case ARM::VST1d8Qwb_register: 2604 case ARM::VST1d16Qwb_register: 2605 case ARM::VST1d32Qwb_register: 2606 case ARM::VST1d64Qwb_register: 2607 case ARM::VST2d8wb_fixed: 2608 case ARM::VST2d16wb_fixed: 2609 case ARM::VST2d32wb_fixed: 2610 case ARM::VST2d8wb_register: 2611 case ARM::VST2d16wb_register: 2612 case ARM::VST2d32wb_register: 2613 case ARM::VST2q8wb_fixed: 2614 case ARM::VST2q16wb_fixed: 2615 case ARM::VST2q32wb_fixed: 2616 case ARM::VST2q8wb_register: 2617 case ARM::VST2q16wb_register: 2618 case ARM::VST2q32wb_register: 2619 case ARM::VST2b8wb_fixed: 2620 case ARM::VST2b16wb_fixed: 2621 case ARM::VST2b32wb_fixed: 2622 case ARM::VST2b8wb_register: 2623 case ARM::VST2b16wb_register: 2624 case ARM::VST2b32wb_register: 2625 if (Rm == 0xF) 2626 return MCDisassembler::Fail; 2627 Inst.addOperand(MCOperand::CreateImm(0)); 2628 break; 2629 case ARM::VST3d8_UPD: 2630 case ARM::VST3d16_UPD: 2631 case ARM::VST3d32_UPD: 2632 case ARM::VST3q8_UPD: 2633 case ARM::VST3q16_UPD: 2634 case ARM::VST3q32_UPD: 2635 case ARM::VST4d8_UPD: 2636 case ARM::VST4d16_UPD: 2637 case ARM::VST4d32_UPD: 2638 case ARM::VST4q8_UPD: 2639 case ARM::VST4q16_UPD: 2640 case ARM::VST4q32_UPD: 2641 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2642 return MCDisassembler::Fail; 2643 break; 2644 default: 2645 break; 2646 } 2647 2648 // AddrMode6 Base (register+alignment) 2649 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2650 return MCDisassembler::Fail; 2651 2652 // AddrMode6 Offset (register) 2653 switch (Inst.getOpcode()) { 2654 default: 2655 if (Rm == 0xD) 2656 Inst.addOperand(MCOperand::CreateReg(0)); 2657 else if (Rm != 0xF) { 2658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2659 return MCDisassembler::Fail; 2660 } 2661 break; 2662 case ARM::VST1d8wb_fixed: 2663 case ARM::VST1d16wb_fixed: 2664 case ARM::VST1d32wb_fixed: 2665 case ARM::VST1d64wb_fixed: 2666 case ARM::VST1q8wb_fixed: 2667 case ARM::VST1q16wb_fixed: 2668 case ARM::VST1q32wb_fixed: 2669 case ARM::VST1q64wb_fixed: 2670 case ARM::VST1d8Twb_fixed: 2671 case ARM::VST1d16Twb_fixed: 2672 case ARM::VST1d32Twb_fixed: 2673 case ARM::VST1d64Twb_fixed: 2674 case ARM::VST1d8Qwb_fixed: 2675 case ARM::VST1d16Qwb_fixed: 2676 case ARM::VST1d32Qwb_fixed: 2677 case ARM::VST1d64Qwb_fixed: 2678 case ARM::VST2d8wb_fixed: 2679 case ARM::VST2d16wb_fixed: 2680 case ARM::VST2d32wb_fixed: 2681 case ARM::VST2q8wb_fixed: 2682 case ARM::VST2q16wb_fixed: 2683 case ARM::VST2q32wb_fixed: 2684 case ARM::VST2b8wb_fixed: 2685 case ARM::VST2b16wb_fixed: 2686 case ARM::VST2b32wb_fixed: 2687 break; 2688 } 2689 2690 2691 // First input register 2692 switch (Inst.getOpcode()) { 2693 case ARM::VST1q16: 2694 case ARM::VST1q32: 2695 case ARM::VST1q64: 2696 case ARM::VST1q8: 2697 case ARM::VST1q16wb_fixed: 2698 case ARM::VST1q16wb_register: 2699 case ARM::VST1q32wb_fixed: 2700 case ARM::VST1q32wb_register: 2701 case ARM::VST1q64wb_fixed: 2702 case ARM::VST1q64wb_register: 2703 case ARM::VST1q8wb_fixed: 2704 case ARM::VST1q8wb_register: 2705 case ARM::VST2d16: 2706 case ARM::VST2d32: 2707 case ARM::VST2d8: 2708 case ARM::VST2d16wb_fixed: 2709 case ARM::VST2d16wb_register: 2710 case ARM::VST2d32wb_fixed: 2711 case ARM::VST2d32wb_register: 2712 case ARM::VST2d8wb_fixed: 2713 case ARM::VST2d8wb_register: 2714 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2715 return MCDisassembler::Fail; 2716 break; 2717 case ARM::VST2b16: 2718 case ARM::VST2b32: 2719 case ARM::VST2b8: 2720 case ARM::VST2b16wb_fixed: 2721 case ARM::VST2b16wb_register: 2722 case ARM::VST2b32wb_fixed: 2723 case ARM::VST2b32wb_register: 2724 case ARM::VST2b8wb_fixed: 2725 case ARM::VST2b8wb_register: 2726 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2727 return MCDisassembler::Fail; 2728 break; 2729 default: 2730 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2731 return MCDisassembler::Fail; 2732 } 2733 2734 // Second input register 2735 switch (Inst.getOpcode()) { 2736 case ARM::VST3d8: 2737 case ARM::VST3d16: 2738 case ARM::VST3d32: 2739 case ARM::VST3d8_UPD: 2740 case ARM::VST3d16_UPD: 2741 case ARM::VST3d32_UPD: 2742 case ARM::VST4d8: 2743 case ARM::VST4d16: 2744 case ARM::VST4d32: 2745 case ARM::VST4d8_UPD: 2746 case ARM::VST4d16_UPD: 2747 case ARM::VST4d32_UPD: 2748 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 break; 2751 case ARM::VST3q8: 2752 case ARM::VST3q16: 2753 case ARM::VST3q32: 2754 case ARM::VST3q8_UPD: 2755 case ARM::VST3q16_UPD: 2756 case ARM::VST3q32_UPD: 2757 case ARM::VST4q8: 2758 case ARM::VST4q16: 2759 case ARM::VST4q32: 2760 case ARM::VST4q8_UPD: 2761 case ARM::VST4q16_UPD: 2762 case ARM::VST4q32_UPD: 2763 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2764 return MCDisassembler::Fail; 2765 break; 2766 default: 2767 break; 2768 } 2769 2770 // Third input register 2771 switch (Inst.getOpcode()) { 2772 case ARM::VST3d8: 2773 case ARM::VST3d16: 2774 case ARM::VST3d32: 2775 case ARM::VST3d8_UPD: 2776 case ARM::VST3d16_UPD: 2777 case ARM::VST3d32_UPD: 2778 case ARM::VST4d8: 2779 case ARM::VST4d16: 2780 case ARM::VST4d32: 2781 case ARM::VST4d8_UPD: 2782 case ARM::VST4d16_UPD: 2783 case ARM::VST4d32_UPD: 2784 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2785 return MCDisassembler::Fail; 2786 break; 2787 case ARM::VST3q8: 2788 case ARM::VST3q16: 2789 case ARM::VST3q32: 2790 case ARM::VST3q8_UPD: 2791 case ARM::VST3q16_UPD: 2792 case ARM::VST3q32_UPD: 2793 case ARM::VST4q8: 2794 case ARM::VST4q16: 2795 case ARM::VST4q32: 2796 case ARM::VST4q8_UPD: 2797 case ARM::VST4q16_UPD: 2798 case ARM::VST4q32_UPD: 2799 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 break; 2802 default: 2803 break; 2804 } 2805 2806 // Fourth input register 2807 switch (Inst.getOpcode()) { 2808 case ARM::VST4d8: 2809 case ARM::VST4d16: 2810 case ARM::VST4d32: 2811 case ARM::VST4d8_UPD: 2812 case ARM::VST4d16_UPD: 2813 case ARM::VST4d32_UPD: 2814 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2815 return MCDisassembler::Fail; 2816 break; 2817 case ARM::VST4q8: 2818 case ARM::VST4q16: 2819 case ARM::VST4q32: 2820 case ARM::VST4q8_UPD: 2821 case ARM::VST4q16_UPD: 2822 case ARM::VST4q32_UPD: 2823 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2824 return MCDisassembler::Fail; 2825 break; 2826 default: 2827 break; 2828 } 2829 2830 return S; 2831 } 2832 2833 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2834 uint64_t Address, const void *Decoder) { 2835 DecodeStatus S = MCDisassembler::Success; 2836 2837 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2838 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2839 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2840 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2841 unsigned align = fieldFromInstruction(Insn, 4, 1); 2842 unsigned size = fieldFromInstruction(Insn, 6, 2); 2843 2844 if (size == 0 && align == 1) 2845 return MCDisassembler::Fail; 2846 align *= (1 << size); 2847 2848 switch (Inst.getOpcode()) { 2849 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2850 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2851 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2852 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2853 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2854 return MCDisassembler::Fail; 2855 break; 2856 default: 2857 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2858 return MCDisassembler::Fail; 2859 break; 2860 } 2861 if (Rm != 0xF) { 2862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2863 return MCDisassembler::Fail; 2864 } 2865 2866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2867 return MCDisassembler::Fail; 2868 Inst.addOperand(MCOperand::CreateImm(align)); 2869 2870 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2871 // variant encodes Rm == 0xf. Anything else is a register offset post- 2872 // increment and we need to add the register operand to the instruction. 2873 if (Rm != 0xD && Rm != 0xF && 2874 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 2877 return S; 2878 } 2879 2880 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2881 uint64_t Address, const void *Decoder) { 2882 DecodeStatus S = MCDisassembler::Success; 2883 2884 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2885 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2886 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2887 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2888 unsigned align = fieldFromInstruction(Insn, 4, 1); 2889 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2890 align *= 2*size; 2891 2892 switch (Inst.getOpcode()) { 2893 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2894 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2895 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2896 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2897 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2898 return MCDisassembler::Fail; 2899 break; 2900 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2901 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2902 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2903 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2904 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2905 return MCDisassembler::Fail; 2906 break; 2907 default: 2908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 break; 2911 } 2912 2913 if (Rm != 0xF) 2914 Inst.addOperand(MCOperand::CreateImm(0)); 2915 2916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2917 return MCDisassembler::Fail; 2918 Inst.addOperand(MCOperand::CreateImm(align)); 2919 2920 if (Rm != 0xD && Rm != 0xF) { 2921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2922 return MCDisassembler::Fail; 2923 } 2924 2925 return S; 2926 } 2927 2928 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2929 uint64_t Address, const void *Decoder) { 2930 DecodeStatus S = MCDisassembler::Success; 2931 2932 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2933 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2934 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2935 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2936 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2937 2938 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2939 return MCDisassembler::Fail; 2940 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2941 return MCDisassembler::Fail; 2942 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2943 return MCDisassembler::Fail; 2944 if (Rm != 0xF) { 2945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2946 return MCDisassembler::Fail; 2947 } 2948 2949 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2950 return MCDisassembler::Fail; 2951 Inst.addOperand(MCOperand::CreateImm(0)); 2952 2953 if (Rm == 0xD) 2954 Inst.addOperand(MCOperand::CreateReg(0)); 2955 else if (Rm != 0xF) { 2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 } 2959 2960 return S; 2961 } 2962 2963 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2964 uint64_t Address, const void *Decoder) { 2965 DecodeStatus S = MCDisassembler::Success; 2966 2967 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2968 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2969 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2970 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2971 unsigned size = fieldFromInstruction(Insn, 6, 2); 2972 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2973 unsigned align = fieldFromInstruction(Insn, 4, 1); 2974 2975 if (size == 0x3) { 2976 if (align == 0) 2977 return MCDisassembler::Fail; 2978 size = 4; 2979 align = 16; 2980 } else { 2981 if (size == 2) { 2982 size = 1 << size; 2983 align *= 8; 2984 } else { 2985 size = 1 << size; 2986 align *= 4*size; 2987 } 2988 } 2989 2990 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2991 return MCDisassembler::Fail; 2992 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2993 return MCDisassembler::Fail; 2994 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2995 return MCDisassembler::Fail; 2996 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2997 return MCDisassembler::Fail; 2998 if (Rm != 0xF) { 2999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3000 return MCDisassembler::Fail; 3001 } 3002 3003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3004 return MCDisassembler::Fail; 3005 Inst.addOperand(MCOperand::CreateImm(align)); 3006 3007 if (Rm == 0xD) 3008 Inst.addOperand(MCOperand::CreateReg(0)); 3009 else if (Rm != 0xF) { 3010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3011 return MCDisassembler::Fail; 3012 } 3013 3014 return S; 3015 } 3016 3017 static DecodeStatus 3018 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3019 uint64_t Address, const void *Decoder) { 3020 DecodeStatus S = MCDisassembler::Success; 3021 3022 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3023 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3024 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3025 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3026 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3027 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3028 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3029 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3030 3031 if (Q) { 3032 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3033 return MCDisassembler::Fail; 3034 } else { 3035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3036 return MCDisassembler::Fail; 3037 } 3038 3039 Inst.addOperand(MCOperand::CreateImm(imm)); 3040 3041 switch (Inst.getOpcode()) { 3042 case ARM::VORRiv4i16: 3043 case ARM::VORRiv2i32: 3044 case ARM::VBICiv4i16: 3045 case ARM::VBICiv2i32: 3046 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3047 return MCDisassembler::Fail; 3048 break; 3049 case ARM::VORRiv8i16: 3050 case ARM::VORRiv4i32: 3051 case ARM::VBICiv8i16: 3052 case ARM::VBICiv4i32: 3053 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3054 return MCDisassembler::Fail; 3055 break; 3056 default: 3057 break; 3058 } 3059 3060 return S; 3061 } 3062 3063 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3064 uint64_t Address, const void *Decoder) { 3065 DecodeStatus S = MCDisassembler::Success; 3066 3067 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3068 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3069 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3070 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3071 unsigned size = fieldFromInstruction(Insn, 18, 2); 3072 3073 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3074 return MCDisassembler::Fail; 3075 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3076 return MCDisassembler::Fail; 3077 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3078 3079 return S; 3080 } 3081 3082 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3083 uint64_t Address, const void *Decoder) { 3084 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3085 return MCDisassembler::Success; 3086 } 3087 3088 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3089 uint64_t Address, const void *Decoder) { 3090 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3091 return MCDisassembler::Success; 3092 } 3093 3094 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3095 uint64_t Address, const void *Decoder) { 3096 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3097 return MCDisassembler::Success; 3098 } 3099 3100 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3101 uint64_t Address, const void *Decoder) { 3102 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3103 return MCDisassembler::Success; 3104 } 3105 3106 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3107 uint64_t Address, const void *Decoder) { 3108 DecodeStatus S = MCDisassembler::Success; 3109 3110 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3111 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3112 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3113 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3114 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3115 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3116 unsigned op = fieldFromInstruction(Insn, 6, 1); 3117 3118 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3119 return MCDisassembler::Fail; 3120 if (op) { 3121 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3122 return MCDisassembler::Fail; // Writeback 3123 } 3124 3125 switch (Inst.getOpcode()) { 3126 case ARM::VTBL2: 3127 case ARM::VTBX2: 3128 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3129 return MCDisassembler::Fail; 3130 break; 3131 default: 3132 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3133 return MCDisassembler::Fail; 3134 } 3135 3136 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3137 return MCDisassembler::Fail; 3138 3139 return S; 3140 } 3141 3142 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3143 uint64_t Address, const void *Decoder) { 3144 DecodeStatus S = MCDisassembler::Success; 3145 3146 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3147 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3148 3149 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3150 return MCDisassembler::Fail; 3151 3152 switch(Inst.getOpcode()) { 3153 default: 3154 return MCDisassembler::Fail; 3155 case ARM::tADR: 3156 break; // tADR does not explicitly represent the PC as an operand. 3157 case ARM::tADDrSPi: 3158 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3159 break; 3160 } 3161 3162 Inst.addOperand(MCOperand::CreateImm(imm)); 3163 return S; 3164 } 3165 3166 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3167 uint64_t Address, const void *Decoder) { 3168 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3169 true, 2, Inst, Decoder)) 3170 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3171 return MCDisassembler::Success; 3172 } 3173 3174 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3175 uint64_t Address, const void *Decoder) { 3176 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3177 true, 4, Inst, Decoder)) 3178 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3179 return MCDisassembler::Success; 3180 } 3181 3182 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3183 uint64_t Address, const void *Decoder) { 3184 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3185 true, 2, Inst, Decoder)) 3186 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3187 return MCDisassembler::Success; 3188 } 3189 3190 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3191 uint64_t Address, const void *Decoder) { 3192 DecodeStatus S = MCDisassembler::Success; 3193 3194 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3195 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3196 3197 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3198 return MCDisassembler::Fail; 3199 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3200 return MCDisassembler::Fail; 3201 3202 return S; 3203 } 3204 3205 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3206 uint64_t Address, const void *Decoder) { 3207 DecodeStatus S = MCDisassembler::Success; 3208 3209 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3210 unsigned imm = fieldFromInstruction(Val, 3, 5); 3211 3212 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3213 return MCDisassembler::Fail; 3214 Inst.addOperand(MCOperand::CreateImm(imm)); 3215 3216 return S; 3217 } 3218 3219 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3220 uint64_t Address, const void *Decoder) { 3221 unsigned imm = Val << 2; 3222 3223 Inst.addOperand(MCOperand::CreateImm(imm)); 3224 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3225 3226 return MCDisassembler::Success; 3227 } 3228 3229 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3230 uint64_t Address, const void *Decoder) { 3231 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3232 Inst.addOperand(MCOperand::CreateImm(Val)); 3233 3234 return MCDisassembler::Success; 3235 } 3236 3237 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3238 uint64_t Address, const void *Decoder) { 3239 DecodeStatus S = MCDisassembler::Success; 3240 3241 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3242 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3243 unsigned imm = fieldFromInstruction(Val, 0, 2); 3244 3245 // Thumb stores cannot use PC as dest register. 3246 switch (Inst.getOpcode()) { 3247 case ARM::t2STRHs: 3248 case ARM::t2STRBs: 3249 case ARM::t2STRs: 3250 if (Rn == 15) 3251 return MCDisassembler::Fail; 3252 default: 3253 break; 3254 } 3255 3256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3257 return MCDisassembler::Fail; 3258 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3259 return MCDisassembler::Fail; 3260 Inst.addOperand(MCOperand::CreateImm(imm)); 3261 3262 return S; 3263 } 3264 3265 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3266 uint64_t Address, const void *Decoder) { 3267 DecodeStatus S = MCDisassembler::Success; 3268 3269 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3270 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3271 3272 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3273 .getFeatureBits(); 3274 bool hasMP = featureBits & ARM::FeatureMP; 3275 bool hasV7Ops = featureBits & ARM::HasV7Ops; 3276 3277 if (Rn == 15) { 3278 switch (Inst.getOpcode()) { 3279 case ARM::t2LDRBs: 3280 Inst.setOpcode(ARM::t2LDRBpci); 3281 break; 3282 case ARM::t2LDRHs: 3283 Inst.setOpcode(ARM::t2LDRHpci); 3284 break; 3285 case ARM::t2LDRSHs: 3286 Inst.setOpcode(ARM::t2LDRSHpci); 3287 break; 3288 case ARM::t2LDRSBs: 3289 Inst.setOpcode(ARM::t2LDRSBpci); 3290 break; 3291 case ARM::t2LDRs: 3292 Inst.setOpcode(ARM::t2LDRpci); 3293 break; 3294 case ARM::t2PLDs: 3295 Inst.setOpcode(ARM::t2PLDpci); 3296 break; 3297 case ARM::t2PLIs: 3298 Inst.setOpcode(ARM::t2PLIpci); 3299 break; 3300 default: 3301 return MCDisassembler::Fail; 3302 } 3303 3304 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3305 } 3306 3307 if (Rt == 15) { 3308 switch (Inst.getOpcode()) { 3309 case ARM::t2LDRSHs: 3310 return MCDisassembler::Fail; 3311 case ARM::t2LDRHs: 3312 Inst.setOpcode(ARM::t2PLDWs); 3313 break; 3314 case ARM::t2LDRSBs: 3315 Inst.setOpcode(ARM::t2PLIs); 3316 default: 3317 break; 3318 } 3319 } 3320 3321 switch (Inst.getOpcode()) { 3322 case ARM::t2PLDs: 3323 break; 3324 case ARM::t2PLIs: 3325 if (!hasV7Ops) 3326 return MCDisassembler::Fail; 3327 break; 3328 case ARM::t2PLDWs: 3329 if (!hasV7Ops || !hasMP) 3330 return MCDisassembler::Fail; 3331 break; 3332 default: 3333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3334 return MCDisassembler::Fail; 3335 } 3336 3337 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3338 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3339 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3340 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3341 return MCDisassembler::Fail; 3342 3343 return S; 3344 } 3345 3346 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3347 uint64_t Address, const void* Decoder) { 3348 DecodeStatus S = MCDisassembler::Success; 3349 3350 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3351 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3352 unsigned U = fieldFromInstruction(Insn, 9, 1); 3353 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3354 imm |= (U << 8); 3355 imm |= (Rn << 9); 3356 unsigned add = fieldFromInstruction(Insn, 9, 1); 3357 3358 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3359 .getFeatureBits(); 3360 bool hasMP = featureBits & ARM::FeatureMP; 3361 bool hasV7Ops = featureBits & ARM::HasV7Ops; 3362 3363 if (Rn == 15) { 3364 switch (Inst.getOpcode()) { 3365 case ARM::t2LDRi8: 3366 Inst.setOpcode(ARM::t2LDRpci); 3367 break; 3368 case ARM::t2LDRBi8: 3369 Inst.setOpcode(ARM::t2LDRBpci); 3370 break; 3371 case ARM::t2LDRSBi8: 3372 Inst.setOpcode(ARM::t2LDRSBpci); 3373 break; 3374 case ARM::t2LDRHi8: 3375 Inst.setOpcode(ARM::t2LDRHpci); 3376 break; 3377 case ARM::t2LDRSHi8: 3378 Inst.setOpcode(ARM::t2LDRSHpci); 3379 break; 3380 case ARM::t2PLDi8: 3381 Inst.setOpcode(ARM::t2PLDpci); 3382 break; 3383 case ARM::t2PLIi8: 3384 Inst.setOpcode(ARM::t2PLIpci); 3385 break; 3386 default: 3387 return MCDisassembler::Fail; 3388 } 3389 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3390 } 3391 3392 if (Rt == 15) { 3393 switch (Inst.getOpcode()) { 3394 case ARM::t2LDRSHi8: 3395 return MCDisassembler::Fail; 3396 case ARM::t2LDRHi8: 3397 if (!add) 3398 Inst.setOpcode(ARM::t2PLDWi8); 3399 break; 3400 case ARM::t2LDRSBi8: 3401 Inst.setOpcode(ARM::t2PLIi8); 3402 break; 3403 default: 3404 break; 3405 } 3406 } 3407 3408 switch (Inst.getOpcode()) { 3409 case ARM::t2PLDi8: 3410 break; 3411 case ARM::t2PLIi8: 3412 if (!hasV7Ops) 3413 return MCDisassembler::Fail; 3414 break; 3415 case ARM::t2PLDWi8: 3416 if (!hasV7Ops || !hasMP) 3417 return MCDisassembler::Fail; 3418 break; 3419 default: 3420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3421 return MCDisassembler::Fail; 3422 } 3423 3424 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3425 return MCDisassembler::Fail; 3426 return S; 3427 } 3428 3429 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3430 uint64_t Address, const void* Decoder) { 3431 DecodeStatus S = MCDisassembler::Success; 3432 3433 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3434 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3435 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3436 imm |= (Rn << 13); 3437 3438 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3439 .getFeatureBits(); 3440 bool hasMP = (featureBits & ARM::FeatureMP); 3441 bool hasV7Ops = (featureBits & ARM::HasV7Ops); 3442 3443 if (Rn == 15) { 3444 switch (Inst.getOpcode()) { 3445 case ARM::t2LDRi12: 3446 Inst.setOpcode(ARM::t2LDRpci); 3447 break; 3448 case ARM::t2LDRHi12: 3449 Inst.setOpcode(ARM::t2LDRHpci); 3450 break; 3451 case ARM::t2LDRSHi12: 3452 Inst.setOpcode(ARM::t2LDRSHpci); 3453 break; 3454 case ARM::t2LDRBi12: 3455 Inst.setOpcode(ARM::t2LDRBpci); 3456 break; 3457 case ARM::t2LDRSBi12: 3458 Inst.setOpcode(ARM::t2LDRSBpci); 3459 break; 3460 case ARM::t2PLDi12: 3461 Inst.setOpcode(ARM::t2PLDpci); 3462 break; 3463 case ARM::t2PLIi12: 3464 Inst.setOpcode(ARM::t2PLIpci); 3465 break; 3466 default: 3467 return MCDisassembler::Fail; 3468 } 3469 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3470 } 3471 3472 if (Rt == 15) { 3473 switch (Inst.getOpcode()) { 3474 case ARM::t2LDRSHi12: 3475 return MCDisassembler::Fail; 3476 case ARM::t2LDRHi12: 3477 Inst.setOpcode(ARM::t2PLDWi12); 3478 break; 3479 case ARM::t2LDRSBi12: 3480 Inst.setOpcode(ARM::t2PLIi12); 3481 break; 3482 default: 3483 break; 3484 } 3485 } 3486 3487 switch (Inst.getOpcode()) { 3488 case ARM::t2PLDi12: 3489 break; 3490 case ARM::t2PLIi12: 3491 if (!hasV7Ops) 3492 return MCDisassembler::Fail; 3493 break; 3494 case ARM::t2PLDWi12: 3495 if (!hasV7Ops || !hasMP) 3496 return MCDisassembler::Fail; 3497 break; 3498 default: 3499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 } 3502 3503 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3504 return MCDisassembler::Fail; 3505 return S; 3506 } 3507 3508 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3509 uint64_t Address, const void* Decoder) { 3510 DecodeStatus S = MCDisassembler::Success; 3511 3512 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3513 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3514 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3515 imm |= (Rn << 9); 3516 3517 if (Rn == 15) { 3518 switch (Inst.getOpcode()) { 3519 case ARM::t2LDRT: 3520 Inst.setOpcode(ARM::t2LDRpci); 3521 break; 3522 case ARM::t2LDRBT: 3523 Inst.setOpcode(ARM::t2LDRBpci); 3524 break; 3525 case ARM::t2LDRHT: 3526 Inst.setOpcode(ARM::t2LDRHpci); 3527 break; 3528 case ARM::t2LDRSBT: 3529 Inst.setOpcode(ARM::t2LDRSBpci); 3530 break; 3531 case ARM::t2LDRSHT: 3532 Inst.setOpcode(ARM::t2LDRSHpci); 3533 break; 3534 default: 3535 return MCDisassembler::Fail; 3536 } 3537 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3538 } 3539 3540 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3541 return MCDisassembler::Fail; 3542 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3543 return MCDisassembler::Fail; 3544 return S; 3545 } 3546 3547 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3548 uint64_t Address, const void* Decoder) { 3549 DecodeStatus S = MCDisassembler::Success; 3550 3551 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3552 unsigned U = fieldFromInstruction(Insn, 23, 1); 3553 int imm = fieldFromInstruction(Insn, 0, 12); 3554 3555 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3556 .getFeatureBits(); 3557 bool hasV7Ops = (featureBits & ARM::HasV7Ops); 3558 3559 if (Rt == 15) { 3560 switch (Inst.getOpcode()) { 3561 case ARM::t2LDRBpci: 3562 case ARM::t2LDRHpci: 3563 Inst.setOpcode(ARM::t2PLDpci); 3564 break; 3565 case ARM::t2LDRSBpci: 3566 Inst.setOpcode(ARM::t2PLIpci); 3567 break; 3568 case ARM::t2LDRSHpci: 3569 return MCDisassembler::Fail; 3570 default: 3571 break; 3572 } 3573 } 3574 3575 switch(Inst.getOpcode()) { 3576 case ARM::t2PLDpci: 3577 break; 3578 case ARM::t2PLIpci: 3579 if (!hasV7Ops) 3580 return MCDisassembler::Fail; 3581 break; 3582 default: 3583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3584 return MCDisassembler::Fail; 3585 } 3586 3587 if (!U) { 3588 // Special case for #-0. 3589 if (imm == 0) 3590 imm = INT32_MIN; 3591 else 3592 imm = -imm; 3593 } 3594 Inst.addOperand(MCOperand::CreateImm(imm)); 3595 3596 return S; 3597 } 3598 3599 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3600 uint64_t Address, const void *Decoder) { 3601 if (Val == 0) 3602 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3603 else { 3604 int imm = Val & 0xFF; 3605 3606 if (!(Val & 0x100)) imm *= -1; 3607 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3608 } 3609 3610 return MCDisassembler::Success; 3611 } 3612 3613 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3614 uint64_t Address, const void *Decoder) { 3615 DecodeStatus S = MCDisassembler::Success; 3616 3617 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3618 unsigned imm = fieldFromInstruction(Val, 0, 9); 3619 3620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3621 return MCDisassembler::Fail; 3622 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3623 return MCDisassembler::Fail; 3624 3625 return S; 3626 } 3627 3628 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3629 uint64_t Address, const void *Decoder) { 3630 DecodeStatus S = MCDisassembler::Success; 3631 3632 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3633 unsigned imm = fieldFromInstruction(Val, 0, 8); 3634 3635 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 3638 Inst.addOperand(MCOperand::CreateImm(imm)); 3639 3640 return S; 3641 } 3642 3643 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3644 uint64_t Address, const void *Decoder) { 3645 int imm = Val & 0xFF; 3646 if (Val == 0) 3647 imm = INT32_MIN; 3648 else if (!(Val & 0x100)) 3649 imm *= -1; 3650 Inst.addOperand(MCOperand::CreateImm(imm)); 3651 3652 return MCDisassembler::Success; 3653 } 3654 3655 3656 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3657 uint64_t Address, const void *Decoder) { 3658 DecodeStatus S = MCDisassembler::Success; 3659 3660 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3661 unsigned imm = fieldFromInstruction(Val, 0, 9); 3662 3663 // Thumb stores cannot use PC as dest register. 3664 switch (Inst.getOpcode()) { 3665 case ARM::t2STRT: 3666 case ARM::t2STRBT: 3667 case ARM::t2STRHT: 3668 case ARM::t2STRi8: 3669 case ARM::t2STRHi8: 3670 case ARM::t2STRBi8: 3671 if (Rn == 15) 3672 return MCDisassembler::Fail; 3673 break; 3674 default: 3675 break; 3676 } 3677 3678 // Some instructions always use an additive offset. 3679 switch (Inst.getOpcode()) { 3680 case ARM::t2LDRT: 3681 case ARM::t2LDRBT: 3682 case ARM::t2LDRHT: 3683 case ARM::t2LDRSBT: 3684 case ARM::t2LDRSHT: 3685 case ARM::t2STRT: 3686 case ARM::t2STRBT: 3687 case ARM::t2STRHT: 3688 imm |= 0x100; 3689 break; 3690 default: 3691 break; 3692 } 3693 3694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3695 return MCDisassembler::Fail; 3696 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3697 return MCDisassembler::Fail; 3698 3699 return S; 3700 } 3701 3702 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3703 uint64_t Address, const void *Decoder) { 3704 DecodeStatus S = MCDisassembler::Success; 3705 3706 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3707 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3708 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3709 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3710 addr |= Rn << 9; 3711 unsigned load = fieldFromInstruction(Insn, 20, 1); 3712 3713 if (Rn == 15) { 3714 switch (Inst.getOpcode()) { 3715 case ARM::t2LDR_PRE: 3716 case ARM::t2LDR_POST: 3717 Inst.setOpcode(ARM::t2LDRpci); 3718 break; 3719 case ARM::t2LDRB_PRE: 3720 case ARM::t2LDRB_POST: 3721 Inst.setOpcode(ARM::t2LDRBpci); 3722 break; 3723 case ARM::t2LDRH_PRE: 3724 case ARM::t2LDRH_POST: 3725 Inst.setOpcode(ARM::t2LDRHpci); 3726 break; 3727 case ARM::t2LDRSB_PRE: 3728 case ARM::t2LDRSB_POST: 3729 if (Rt == 15) 3730 Inst.setOpcode(ARM::t2PLIpci); 3731 else 3732 Inst.setOpcode(ARM::t2LDRSBpci); 3733 break; 3734 case ARM::t2LDRSH_PRE: 3735 case ARM::t2LDRSH_POST: 3736 Inst.setOpcode(ARM::t2LDRSHpci); 3737 break; 3738 default: 3739 return MCDisassembler::Fail; 3740 } 3741 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3742 } 3743 3744 if (!load) { 3745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3746 return MCDisassembler::Fail; 3747 } 3748 3749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3750 return MCDisassembler::Fail; 3751 3752 if (load) { 3753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3754 return MCDisassembler::Fail; 3755 } 3756 3757 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3758 return MCDisassembler::Fail; 3759 3760 return S; 3761 } 3762 3763 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3764 uint64_t Address, const void *Decoder) { 3765 DecodeStatus S = MCDisassembler::Success; 3766 3767 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3768 unsigned imm = fieldFromInstruction(Val, 0, 12); 3769 3770 // Thumb stores cannot use PC as dest register. 3771 switch (Inst.getOpcode()) { 3772 case ARM::t2STRi12: 3773 case ARM::t2STRBi12: 3774 case ARM::t2STRHi12: 3775 if (Rn == 15) 3776 return MCDisassembler::Fail; 3777 default: 3778 break; 3779 } 3780 3781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3782 return MCDisassembler::Fail; 3783 Inst.addOperand(MCOperand::CreateImm(imm)); 3784 3785 return S; 3786 } 3787 3788 3789 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3790 uint64_t Address, const void *Decoder) { 3791 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3792 3793 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3794 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3795 Inst.addOperand(MCOperand::CreateImm(imm)); 3796 3797 return MCDisassembler::Success; 3798 } 3799 3800 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3801 uint64_t Address, const void *Decoder) { 3802 DecodeStatus S = MCDisassembler::Success; 3803 3804 if (Inst.getOpcode() == ARM::tADDrSP) { 3805 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3806 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3807 3808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3809 return MCDisassembler::Fail; 3810 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3812 return MCDisassembler::Fail; 3813 } else if (Inst.getOpcode() == ARM::tADDspr) { 3814 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3815 3816 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3817 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3818 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3819 return MCDisassembler::Fail; 3820 } 3821 3822 return S; 3823 } 3824 3825 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3826 uint64_t Address, const void *Decoder) { 3827 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3828 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3829 3830 Inst.addOperand(MCOperand::CreateImm(imod)); 3831 Inst.addOperand(MCOperand::CreateImm(flags)); 3832 3833 return MCDisassembler::Success; 3834 } 3835 3836 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3837 uint64_t Address, const void *Decoder) { 3838 DecodeStatus S = MCDisassembler::Success; 3839 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3840 unsigned add = fieldFromInstruction(Insn, 4, 1); 3841 3842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3843 return MCDisassembler::Fail; 3844 Inst.addOperand(MCOperand::CreateImm(add)); 3845 3846 return S; 3847 } 3848 3849 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3850 uint64_t Address, const void *Decoder) { 3851 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3852 // Note only one trailing zero not two. Also the J1 and J2 values are from 3853 // the encoded instruction. So here change to I1 and I2 values via: 3854 // I1 = NOT(J1 EOR S); 3855 // I2 = NOT(J2 EOR S); 3856 // and build the imm32 with two trailing zeros as documented: 3857 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3858 unsigned S = (Val >> 23) & 1; 3859 unsigned J1 = (Val >> 22) & 1; 3860 unsigned J2 = (Val >> 21) & 1; 3861 unsigned I1 = !(J1 ^ S); 3862 unsigned I2 = !(J2 ^ S); 3863 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3864 int imm32 = SignExtend32<25>(tmp << 1); 3865 3866 if (!tryAddingSymbolicOperand(Address, 3867 (Address & ~2u) + imm32 + 4, 3868 true, 4, Inst, Decoder)) 3869 Inst.addOperand(MCOperand::CreateImm(imm32)); 3870 return MCDisassembler::Success; 3871 } 3872 3873 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3874 uint64_t Address, const void *Decoder) { 3875 if (Val == 0xA || Val == 0xB) 3876 return MCDisassembler::Fail; 3877 3878 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3879 .getFeatureBits(); 3880 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15)) 3881 return MCDisassembler::Fail; 3882 3883 Inst.addOperand(MCOperand::CreateImm(Val)); 3884 return MCDisassembler::Success; 3885 } 3886 3887 static DecodeStatus 3888 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3889 uint64_t Address, const void *Decoder) { 3890 DecodeStatus S = MCDisassembler::Success; 3891 3892 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3893 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3894 3895 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3897 return MCDisassembler::Fail; 3898 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3899 return MCDisassembler::Fail; 3900 return S; 3901 } 3902 3903 static DecodeStatus 3904 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3905 uint64_t Address, const void *Decoder) { 3906 DecodeStatus S = MCDisassembler::Success; 3907 3908 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3909 if (pred == 0xE || pred == 0xF) { 3910 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3911 switch (opc) { 3912 default: 3913 return MCDisassembler::Fail; 3914 case 0xf3bf8f4: 3915 Inst.setOpcode(ARM::t2DSB); 3916 break; 3917 case 0xf3bf8f5: 3918 Inst.setOpcode(ARM::t2DMB); 3919 break; 3920 case 0xf3bf8f6: 3921 Inst.setOpcode(ARM::t2ISB); 3922 break; 3923 } 3924 3925 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3926 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3927 } 3928 3929 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3930 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3931 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3932 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3933 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3934 3935 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3936 return MCDisassembler::Fail; 3937 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3938 return MCDisassembler::Fail; 3939 3940 return S; 3941 } 3942 3943 // Decode a shifted immediate operand. These basically consist 3944 // of an 8-bit value, and a 4-bit directive that specifies either 3945 // a splat operation or a rotation. 3946 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3947 uint64_t Address, const void *Decoder) { 3948 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3949 if (ctrl == 0) { 3950 unsigned byte = fieldFromInstruction(Val, 8, 2); 3951 unsigned imm = fieldFromInstruction(Val, 0, 8); 3952 switch (byte) { 3953 case 0: 3954 Inst.addOperand(MCOperand::CreateImm(imm)); 3955 break; 3956 case 1: 3957 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3958 break; 3959 case 2: 3960 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3961 break; 3962 case 3: 3963 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3964 (imm << 8) | imm)); 3965 break; 3966 } 3967 } else { 3968 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3969 unsigned rot = fieldFromInstruction(Val, 7, 5); 3970 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3971 Inst.addOperand(MCOperand::CreateImm(imm)); 3972 } 3973 3974 return MCDisassembler::Success; 3975 } 3976 3977 static DecodeStatus 3978 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3979 uint64_t Address, const void *Decoder){ 3980 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3981 true, 2, Inst, Decoder)) 3982 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3983 return MCDisassembler::Success; 3984 } 3985 3986 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3987 uint64_t Address, const void *Decoder){ 3988 // Val is passed in as S:J1:J2:imm10:imm11 3989 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3990 // the encoded instruction. So here change to I1 and I2 values via: 3991 // I1 = NOT(J1 EOR S); 3992 // I2 = NOT(J2 EOR S); 3993 // and build the imm32 with one trailing zero as documented: 3994 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3995 unsigned S = (Val >> 23) & 1; 3996 unsigned J1 = (Val >> 22) & 1; 3997 unsigned J2 = (Val >> 21) & 1; 3998 unsigned I1 = !(J1 ^ S); 3999 unsigned I2 = !(J2 ^ S); 4000 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4001 int imm32 = SignExtend32<25>(tmp << 1); 4002 4003 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4004 true, 4, Inst, Decoder)) 4005 Inst.addOperand(MCOperand::CreateImm(imm32)); 4006 return MCDisassembler::Success; 4007 } 4008 4009 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4010 uint64_t Address, const void *Decoder) { 4011 if (Val & ~0xf) 4012 return MCDisassembler::Fail; 4013 4014 Inst.addOperand(MCOperand::CreateImm(Val)); 4015 return MCDisassembler::Success; 4016 } 4017 4018 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4019 uint64_t Address, const void *Decoder) { 4020 if (Val & ~0xf) 4021 return MCDisassembler::Fail; 4022 4023 Inst.addOperand(MCOperand::CreateImm(Val)); 4024 return MCDisassembler::Success; 4025 } 4026 4027 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4028 uint64_t Address, const void *Decoder) { 4029 DecodeStatus S = MCDisassembler::Success; 4030 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 4031 .getFeatureBits(); 4032 if (FeatureBits & ARM::FeatureMClass) { 4033 unsigned ValLow = Val & 0xff; 4034 4035 // Validate the SYSm value first. 4036 switch (ValLow) { 4037 case 0: // apsr 4038 case 1: // iapsr 4039 case 2: // eapsr 4040 case 3: // xpsr 4041 case 5: // ipsr 4042 case 6: // epsr 4043 case 7: // iepsr 4044 case 8: // msp 4045 case 9: // psp 4046 case 16: // primask 4047 case 20: // control 4048 break; 4049 case 17: // basepri 4050 case 18: // basepri_max 4051 case 19: // faultmask 4052 if (!(FeatureBits & ARM::HasV7Ops)) 4053 // Values basepri, basepri_max and faultmask are only valid for v7m. 4054 return MCDisassembler::Fail; 4055 break; 4056 default: 4057 return MCDisassembler::Fail; 4058 } 4059 4060 if (Inst.getOpcode() == ARM::t2MSR_M) { 4061 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4062 if (!(FeatureBits & ARM::HasV7Ops)) { 4063 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4064 // unpredictable. 4065 if (Mask != 2) 4066 S = MCDisassembler::SoftFail; 4067 } 4068 else { 4069 // The ARMv7-M architecture stores an additional 2-bit mask value in 4070 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4071 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4072 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4073 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4074 // only if the processor includes the DSP extension. 4075 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4076 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1))) 4077 S = MCDisassembler::SoftFail; 4078 } 4079 } 4080 } else { 4081 // A/R class 4082 if (Val == 0) 4083 return MCDisassembler::Fail; 4084 } 4085 Inst.addOperand(MCOperand::CreateImm(Val)); 4086 return S; 4087 } 4088 4089 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4090 uint64_t Address, const void *Decoder) { 4091 4092 unsigned R = fieldFromInstruction(Val, 5, 1); 4093 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4094 4095 // The table of encodings for these banked registers comes from B9.2.3 of the 4096 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4097 // neater. So by fiat, these values are UNPREDICTABLE: 4098 if (!R) { 4099 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || 4100 SysM == 0x1a || SysM == 0x1b) 4101 return MCDisassembler::SoftFail; 4102 } else { 4103 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && 4104 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) 4105 return MCDisassembler::SoftFail; 4106 } 4107 4108 Inst.addOperand(MCOperand::CreateImm(Val)); 4109 return MCDisassembler::Success; 4110 } 4111 4112 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4113 uint64_t Address, const void *Decoder) { 4114 DecodeStatus S = MCDisassembler::Success; 4115 4116 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4117 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4118 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4119 4120 if (Rn == 0xF) 4121 S = MCDisassembler::SoftFail; 4122 4123 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4124 return MCDisassembler::Fail; 4125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4126 return MCDisassembler::Fail; 4127 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4128 return MCDisassembler::Fail; 4129 4130 return S; 4131 } 4132 4133 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4134 uint64_t Address, const void *Decoder){ 4135 DecodeStatus S = MCDisassembler::Success; 4136 4137 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4138 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4139 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4140 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4141 4142 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4143 return MCDisassembler::Fail; 4144 4145 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4146 S = MCDisassembler::SoftFail; 4147 4148 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4149 return MCDisassembler::Fail; 4150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4151 return MCDisassembler::Fail; 4152 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4153 return MCDisassembler::Fail; 4154 4155 return S; 4156 } 4157 4158 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4159 uint64_t Address, const void *Decoder) { 4160 DecodeStatus S = MCDisassembler::Success; 4161 4162 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4163 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4164 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4165 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4166 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4167 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4168 4169 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4170 4171 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4172 return MCDisassembler::Fail; 4173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4174 return MCDisassembler::Fail; 4175 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4176 return MCDisassembler::Fail; 4177 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4178 return MCDisassembler::Fail; 4179 4180 return S; 4181 } 4182 4183 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4184 uint64_t Address, const void *Decoder) { 4185 DecodeStatus S = MCDisassembler::Success; 4186 4187 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4188 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4189 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4190 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4191 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4192 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4193 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4194 4195 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4196 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4197 4198 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4199 return MCDisassembler::Fail; 4200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4201 return MCDisassembler::Fail; 4202 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4203 return MCDisassembler::Fail; 4204 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4205 return MCDisassembler::Fail; 4206 4207 return S; 4208 } 4209 4210 4211 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4212 uint64_t Address, const void *Decoder) { 4213 DecodeStatus S = MCDisassembler::Success; 4214 4215 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4216 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4217 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4218 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4219 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4220 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4221 4222 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4223 4224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4225 return MCDisassembler::Fail; 4226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4227 return MCDisassembler::Fail; 4228 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4229 return MCDisassembler::Fail; 4230 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4231 return MCDisassembler::Fail; 4232 4233 return S; 4234 } 4235 4236 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4237 uint64_t Address, const void *Decoder) { 4238 DecodeStatus S = MCDisassembler::Success; 4239 4240 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4241 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4242 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4243 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4244 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4245 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4246 4247 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4248 4249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4250 return MCDisassembler::Fail; 4251 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4252 return MCDisassembler::Fail; 4253 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4254 return MCDisassembler::Fail; 4255 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4256 return MCDisassembler::Fail; 4257 4258 return S; 4259 } 4260 4261 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4262 uint64_t Address, const void *Decoder) { 4263 DecodeStatus S = MCDisassembler::Success; 4264 4265 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4266 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4267 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4268 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4269 unsigned size = fieldFromInstruction(Insn, 10, 2); 4270 4271 unsigned align = 0; 4272 unsigned index = 0; 4273 switch (size) { 4274 default: 4275 return MCDisassembler::Fail; 4276 case 0: 4277 if (fieldFromInstruction(Insn, 4, 1)) 4278 return MCDisassembler::Fail; // UNDEFINED 4279 index = fieldFromInstruction(Insn, 5, 3); 4280 break; 4281 case 1: 4282 if (fieldFromInstruction(Insn, 5, 1)) 4283 return MCDisassembler::Fail; // UNDEFINED 4284 index = fieldFromInstruction(Insn, 6, 2); 4285 if (fieldFromInstruction(Insn, 4, 1)) 4286 align = 2; 4287 break; 4288 case 2: 4289 if (fieldFromInstruction(Insn, 6, 1)) 4290 return MCDisassembler::Fail; // UNDEFINED 4291 index = fieldFromInstruction(Insn, 7, 1); 4292 4293 switch (fieldFromInstruction(Insn, 4, 2)) { 4294 case 0 : 4295 align = 0; break; 4296 case 3: 4297 align = 4; break; 4298 default: 4299 return MCDisassembler::Fail; 4300 } 4301 break; 4302 } 4303 4304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4305 return MCDisassembler::Fail; 4306 if (Rm != 0xF) { // Writeback 4307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4308 return MCDisassembler::Fail; 4309 } 4310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 Inst.addOperand(MCOperand::CreateImm(align)); 4313 if (Rm != 0xF) { 4314 if (Rm != 0xD) { 4315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4316 return MCDisassembler::Fail; 4317 } else 4318 Inst.addOperand(MCOperand::CreateReg(0)); 4319 } 4320 4321 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4322 return MCDisassembler::Fail; 4323 Inst.addOperand(MCOperand::CreateImm(index)); 4324 4325 return S; 4326 } 4327 4328 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4329 uint64_t Address, const void *Decoder) { 4330 DecodeStatus S = MCDisassembler::Success; 4331 4332 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4333 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4334 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4335 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4336 unsigned size = fieldFromInstruction(Insn, 10, 2); 4337 4338 unsigned align = 0; 4339 unsigned index = 0; 4340 switch (size) { 4341 default: 4342 return MCDisassembler::Fail; 4343 case 0: 4344 if (fieldFromInstruction(Insn, 4, 1)) 4345 return MCDisassembler::Fail; // UNDEFINED 4346 index = fieldFromInstruction(Insn, 5, 3); 4347 break; 4348 case 1: 4349 if (fieldFromInstruction(Insn, 5, 1)) 4350 return MCDisassembler::Fail; // UNDEFINED 4351 index = fieldFromInstruction(Insn, 6, 2); 4352 if (fieldFromInstruction(Insn, 4, 1)) 4353 align = 2; 4354 break; 4355 case 2: 4356 if (fieldFromInstruction(Insn, 6, 1)) 4357 return MCDisassembler::Fail; // UNDEFINED 4358 index = fieldFromInstruction(Insn, 7, 1); 4359 4360 switch (fieldFromInstruction(Insn, 4, 2)) { 4361 case 0: 4362 align = 0; break; 4363 case 3: 4364 align = 4; break; 4365 default: 4366 return MCDisassembler::Fail; 4367 } 4368 break; 4369 } 4370 4371 if (Rm != 0xF) { // Writeback 4372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4373 return MCDisassembler::Fail; 4374 } 4375 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4376 return MCDisassembler::Fail; 4377 Inst.addOperand(MCOperand::CreateImm(align)); 4378 if (Rm != 0xF) { 4379 if (Rm != 0xD) { 4380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4381 return MCDisassembler::Fail; 4382 } else 4383 Inst.addOperand(MCOperand::CreateReg(0)); 4384 } 4385 4386 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4387 return MCDisassembler::Fail; 4388 Inst.addOperand(MCOperand::CreateImm(index)); 4389 4390 return S; 4391 } 4392 4393 4394 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4395 uint64_t Address, const void *Decoder) { 4396 DecodeStatus S = MCDisassembler::Success; 4397 4398 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4399 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4400 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4401 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4402 unsigned size = fieldFromInstruction(Insn, 10, 2); 4403 4404 unsigned align = 0; 4405 unsigned index = 0; 4406 unsigned inc = 1; 4407 switch (size) { 4408 default: 4409 return MCDisassembler::Fail; 4410 case 0: 4411 index = fieldFromInstruction(Insn, 5, 3); 4412 if (fieldFromInstruction(Insn, 4, 1)) 4413 align = 2; 4414 break; 4415 case 1: 4416 index = fieldFromInstruction(Insn, 6, 2); 4417 if (fieldFromInstruction(Insn, 4, 1)) 4418 align = 4; 4419 if (fieldFromInstruction(Insn, 5, 1)) 4420 inc = 2; 4421 break; 4422 case 2: 4423 if (fieldFromInstruction(Insn, 5, 1)) 4424 return MCDisassembler::Fail; // UNDEFINED 4425 index = fieldFromInstruction(Insn, 7, 1); 4426 if (fieldFromInstruction(Insn, 4, 1) != 0) 4427 align = 8; 4428 if (fieldFromInstruction(Insn, 6, 1)) 4429 inc = 2; 4430 break; 4431 } 4432 4433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4434 return MCDisassembler::Fail; 4435 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4436 return MCDisassembler::Fail; 4437 if (Rm != 0xF) { // Writeback 4438 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4439 return MCDisassembler::Fail; 4440 } 4441 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4442 return MCDisassembler::Fail; 4443 Inst.addOperand(MCOperand::CreateImm(align)); 4444 if (Rm != 0xF) { 4445 if (Rm != 0xD) { 4446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4447 return MCDisassembler::Fail; 4448 } else 4449 Inst.addOperand(MCOperand::CreateReg(0)); 4450 } 4451 4452 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4453 return MCDisassembler::Fail; 4454 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4455 return MCDisassembler::Fail; 4456 Inst.addOperand(MCOperand::CreateImm(index)); 4457 4458 return S; 4459 } 4460 4461 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4462 uint64_t Address, const void *Decoder) { 4463 DecodeStatus S = MCDisassembler::Success; 4464 4465 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4466 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4467 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4468 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4469 unsigned size = fieldFromInstruction(Insn, 10, 2); 4470 4471 unsigned align = 0; 4472 unsigned index = 0; 4473 unsigned inc = 1; 4474 switch (size) { 4475 default: 4476 return MCDisassembler::Fail; 4477 case 0: 4478 index = fieldFromInstruction(Insn, 5, 3); 4479 if (fieldFromInstruction(Insn, 4, 1)) 4480 align = 2; 4481 break; 4482 case 1: 4483 index = fieldFromInstruction(Insn, 6, 2); 4484 if (fieldFromInstruction(Insn, 4, 1)) 4485 align = 4; 4486 if (fieldFromInstruction(Insn, 5, 1)) 4487 inc = 2; 4488 break; 4489 case 2: 4490 if (fieldFromInstruction(Insn, 5, 1)) 4491 return MCDisassembler::Fail; // UNDEFINED 4492 index = fieldFromInstruction(Insn, 7, 1); 4493 if (fieldFromInstruction(Insn, 4, 1) != 0) 4494 align = 8; 4495 if (fieldFromInstruction(Insn, 6, 1)) 4496 inc = 2; 4497 break; 4498 } 4499 4500 if (Rm != 0xF) { // Writeback 4501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4502 return MCDisassembler::Fail; 4503 } 4504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4505 return MCDisassembler::Fail; 4506 Inst.addOperand(MCOperand::CreateImm(align)); 4507 if (Rm != 0xF) { 4508 if (Rm != 0xD) { 4509 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4510 return MCDisassembler::Fail; 4511 } else 4512 Inst.addOperand(MCOperand::CreateReg(0)); 4513 } 4514 4515 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4516 return MCDisassembler::Fail; 4517 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4518 return MCDisassembler::Fail; 4519 Inst.addOperand(MCOperand::CreateImm(index)); 4520 4521 return S; 4522 } 4523 4524 4525 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4526 uint64_t Address, const void *Decoder) { 4527 DecodeStatus S = MCDisassembler::Success; 4528 4529 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4530 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4531 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4532 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4533 unsigned size = fieldFromInstruction(Insn, 10, 2); 4534 4535 unsigned align = 0; 4536 unsigned index = 0; 4537 unsigned inc = 1; 4538 switch (size) { 4539 default: 4540 return MCDisassembler::Fail; 4541 case 0: 4542 if (fieldFromInstruction(Insn, 4, 1)) 4543 return MCDisassembler::Fail; // UNDEFINED 4544 index = fieldFromInstruction(Insn, 5, 3); 4545 break; 4546 case 1: 4547 if (fieldFromInstruction(Insn, 4, 1)) 4548 return MCDisassembler::Fail; // UNDEFINED 4549 index = fieldFromInstruction(Insn, 6, 2); 4550 if (fieldFromInstruction(Insn, 5, 1)) 4551 inc = 2; 4552 break; 4553 case 2: 4554 if (fieldFromInstruction(Insn, 4, 2)) 4555 return MCDisassembler::Fail; // UNDEFINED 4556 index = fieldFromInstruction(Insn, 7, 1); 4557 if (fieldFromInstruction(Insn, 6, 1)) 4558 inc = 2; 4559 break; 4560 } 4561 4562 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4563 return MCDisassembler::Fail; 4564 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4565 return MCDisassembler::Fail; 4566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4567 return MCDisassembler::Fail; 4568 4569 if (Rm != 0xF) { // Writeback 4570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4571 return MCDisassembler::Fail; 4572 } 4573 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4574 return MCDisassembler::Fail; 4575 Inst.addOperand(MCOperand::CreateImm(align)); 4576 if (Rm != 0xF) { 4577 if (Rm != 0xD) { 4578 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4579 return MCDisassembler::Fail; 4580 } else 4581 Inst.addOperand(MCOperand::CreateReg(0)); 4582 } 4583 4584 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4585 return MCDisassembler::Fail; 4586 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4587 return MCDisassembler::Fail; 4588 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4589 return MCDisassembler::Fail; 4590 Inst.addOperand(MCOperand::CreateImm(index)); 4591 4592 return S; 4593 } 4594 4595 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4596 uint64_t Address, const void *Decoder) { 4597 DecodeStatus S = MCDisassembler::Success; 4598 4599 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4600 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4601 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4602 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4603 unsigned size = fieldFromInstruction(Insn, 10, 2); 4604 4605 unsigned align = 0; 4606 unsigned index = 0; 4607 unsigned inc = 1; 4608 switch (size) { 4609 default: 4610 return MCDisassembler::Fail; 4611 case 0: 4612 if (fieldFromInstruction(Insn, 4, 1)) 4613 return MCDisassembler::Fail; // UNDEFINED 4614 index = fieldFromInstruction(Insn, 5, 3); 4615 break; 4616 case 1: 4617 if (fieldFromInstruction(Insn, 4, 1)) 4618 return MCDisassembler::Fail; // UNDEFINED 4619 index = fieldFromInstruction(Insn, 6, 2); 4620 if (fieldFromInstruction(Insn, 5, 1)) 4621 inc = 2; 4622 break; 4623 case 2: 4624 if (fieldFromInstruction(Insn, 4, 2)) 4625 return MCDisassembler::Fail; // UNDEFINED 4626 index = fieldFromInstruction(Insn, 7, 1); 4627 if (fieldFromInstruction(Insn, 6, 1)) 4628 inc = 2; 4629 break; 4630 } 4631 4632 if (Rm != 0xF) { // Writeback 4633 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4634 return MCDisassembler::Fail; 4635 } 4636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4637 return MCDisassembler::Fail; 4638 Inst.addOperand(MCOperand::CreateImm(align)); 4639 if (Rm != 0xF) { 4640 if (Rm != 0xD) { 4641 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4642 return MCDisassembler::Fail; 4643 } else 4644 Inst.addOperand(MCOperand::CreateReg(0)); 4645 } 4646 4647 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4648 return MCDisassembler::Fail; 4649 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4650 return MCDisassembler::Fail; 4651 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4652 return MCDisassembler::Fail; 4653 Inst.addOperand(MCOperand::CreateImm(index)); 4654 4655 return S; 4656 } 4657 4658 4659 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4660 uint64_t Address, const void *Decoder) { 4661 DecodeStatus S = MCDisassembler::Success; 4662 4663 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4664 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4665 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4666 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4667 unsigned size = fieldFromInstruction(Insn, 10, 2); 4668 4669 unsigned align = 0; 4670 unsigned index = 0; 4671 unsigned inc = 1; 4672 switch (size) { 4673 default: 4674 return MCDisassembler::Fail; 4675 case 0: 4676 if (fieldFromInstruction(Insn, 4, 1)) 4677 align = 4; 4678 index = fieldFromInstruction(Insn, 5, 3); 4679 break; 4680 case 1: 4681 if (fieldFromInstruction(Insn, 4, 1)) 4682 align = 8; 4683 index = fieldFromInstruction(Insn, 6, 2); 4684 if (fieldFromInstruction(Insn, 5, 1)) 4685 inc = 2; 4686 break; 4687 case 2: 4688 switch (fieldFromInstruction(Insn, 4, 2)) { 4689 case 0: 4690 align = 0; break; 4691 case 3: 4692 return MCDisassembler::Fail; 4693 default: 4694 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4695 } 4696 4697 index = fieldFromInstruction(Insn, 7, 1); 4698 if (fieldFromInstruction(Insn, 6, 1)) 4699 inc = 2; 4700 break; 4701 } 4702 4703 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4704 return MCDisassembler::Fail; 4705 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4706 return MCDisassembler::Fail; 4707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4708 return MCDisassembler::Fail; 4709 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4710 return MCDisassembler::Fail; 4711 4712 if (Rm != 0xF) { // Writeback 4713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4714 return MCDisassembler::Fail; 4715 } 4716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4717 return MCDisassembler::Fail; 4718 Inst.addOperand(MCOperand::CreateImm(align)); 4719 if (Rm != 0xF) { 4720 if (Rm != 0xD) { 4721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4722 return MCDisassembler::Fail; 4723 } else 4724 Inst.addOperand(MCOperand::CreateReg(0)); 4725 } 4726 4727 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4728 return MCDisassembler::Fail; 4729 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4730 return MCDisassembler::Fail; 4731 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4732 return MCDisassembler::Fail; 4733 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4734 return MCDisassembler::Fail; 4735 Inst.addOperand(MCOperand::CreateImm(index)); 4736 4737 return S; 4738 } 4739 4740 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4741 uint64_t Address, const void *Decoder) { 4742 DecodeStatus S = MCDisassembler::Success; 4743 4744 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4745 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4746 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4747 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4748 unsigned size = fieldFromInstruction(Insn, 10, 2); 4749 4750 unsigned align = 0; 4751 unsigned index = 0; 4752 unsigned inc = 1; 4753 switch (size) { 4754 default: 4755 return MCDisassembler::Fail; 4756 case 0: 4757 if (fieldFromInstruction(Insn, 4, 1)) 4758 align = 4; 4759 index = fieldFromInstruction(Insn, 5, 3); 4760 break; 4761 case 1: 4762 if (fieldFromInstruction(Insn, 4, 1)) 4763 align = 8; 4764 index = fieldFromInstruction(Insn, 6, 2); 4765 if (fieldFromInstruction(Insn, 5, 1)) 4766 inc = 2; 4767 break; 4768 case 2: 4769 switch (fieldFromInstruction(Insn, 4, 2)) { 4770 case 0: 4771 align = 0; break; 4772 case 3: 4773 return MCDisassembler::Fail; 4774 default: 4775 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4776 } 4777 4778 index = fieldFromInstruction(Insn, 7, 1); 4779 if (fieldFromInstruction(Insn, 6, 1)) 4780 inc = 2; 4781 break; 4782 } 4783 4784 if (Rm != 0xF) { // Writeback 4785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4786 return MCDisassembler::Fail; 4787 } 4788 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4789 return MCDisassembler::Fail; 4790 Inst.addOperand(MCOperand::CreateImm(align)); 4791 if (Rm != 0xF) { 4792 if (Rm != 0xD) { 4793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4794 return MCDisassembler::Fail; 4795 } else 4796 Inst.addOperand(MCOperand::CreateReg(0)); 4797 } 4798 4799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4800 return MCDisassembler::Fail; 4801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4802 return MCDisassembler::Fail; 4803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4804 return MCDisassembler::Fail; 4805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4806 return MCDisassembler::Fail; 4807 Inst.addOperand(MCOperand::CreateImm(index)); 4808 4809 return S; 4810 } 4811 4812 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4813 uint64_t Address, const void *Decoder) { 4814 DecodeStatus S = MCDisassembler::Success; 4815 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4816 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4817 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4818 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4819 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4820 4821 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4822 S = MCDisassembler::SoftFail; 4823 4824 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4825 return MCDisassembler::Fail; 4826 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4827 return MCDisassembler::Fail; 4828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4829 return MCDisassembler::Fail; 4830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4831 return MCDisassembler::Fail; 4832 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4833 return MCDisassembler::Fail; 4834 4835 return S; 4836 } 4837 4838 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4839 uint64_t Address, const void *Decoder) { 4840 DecodeStatus S = MCDisassembler::Success; 4841 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4842 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4843 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4844 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4845 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4846 4847 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4848 S = MCDisassembler::SoftFail; 4849 4850 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4851 return MCDisassembler::Fail; 4852 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4853 return MCDisassembler::Fail; 4854 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4855 return MCDisassembler::Fail; 4856 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4857 return MCDisassembler::Fail; 4858 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4859 return MCDisassembler::Fail; 4860 4861 return S; 4862 } 4863 4864 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4865 uint64_t Address, const void *Decoder) { 4866 DecodeStatus S = MCDisassembler::Success; 4867 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4868 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4869 4870 if (pred == 0xF) { 4871 pred = 0xE; 4872 S = MCDisassembler::SoftFail; 4873 } 4874 4875 if (mask == 0x0) 4876 return MCDisassembler::Fail; 4877 4878 Inst.addOperand(MCOperand::CreateImm(pred)); 4879 Inst.addOperand(MCOperand::CreateImm(mask)); 4880 return S; 4881 } 4882 4883 static DecodeStatus 4884 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4885 uint64_t Address, const void *Decoder) { 4886 DecodeStatus S = MCDisassembler::Success; 4887 4888 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4889 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4890 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4891 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4892 unsigned W = fieldFromInstruction(Insn, 21, 1); 4893 unsigned U = fieldFromInstruction(Insn, 23, 1); 4894 unsigned P = fieldFromInstruction(Insn, 24, 1); 4895 bool writeback = (W == 1) | (P == 0); 4896 4897 addr |= (U << 8) | (Rn << 9); 4898 4899 if (writeback && (Rn == Rt || Rn == Rt2)) 4900 Check(S, MCDisassembler::SoftFail); 4901 if (Rt == Rt2) 4902 Check(S, MCDisassembler::SoftFail); 4903 4904 // Rt 4905 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4906 return MCDisassembler::Fail; 4907 // Rt2 4908 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4909 return MCDisassembler::Fail; 4910 // Writeback operand 4911 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4912 return MCDisassembler::Fail; 4913 // addr 4914 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4915 return MCDisassembler::Fail; 4916 4917 return S; 4918 } 4919 4920 static DecodeStatus 4921 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4922 uint64_t Address, const void *Decoder) { 4923 DecodeStatus S = MCDisassembler::Success; 4924 4925 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4926 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4927 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4928 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4929 unsigned W = fieldFromInstruction(Insn, 21, 1); 4930 unsigned U = fieldFromInstruction(Insn, 23, 1); 4931 unsigned P = fieldFromInstruction(Insn, 24, 1); 4932 bool writeback = (W == 1) | (P == 0); 4933 4934 addr |= (U << 8) | (Rn << 9); 4935 4936 if (writeback && (Rn == Rt || Rn == Rt2)) 4937 Check(S, MCDisassembler::SoftFail); 4938 4939 // Writeback operand 4940 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4941 return MCDisassembler::Fail; 4942 // Rt 4943 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4944 return MCDisassembler::Fail; 4945 // Rt2 4946 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4947 return MCDisassembler::Fail; 4948 // addr 4949 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4950 return MCDisassembler::Fail; 4951 4952 return S; 4953 } 4954 4955 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4956 uint64_t Address, const void *Decoder) { 4957 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4958 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4959 if (sign1 != sign2) return MCDisassembler::Fail; 4960 4961 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4962 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4963 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4964 Val |= sign1 << 12; 4965 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4966 4967 return MCDisassembler::Success; 4968 } 4969 4970 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4971 uint64_t Address, 4972 const void *Decoder) { 4973 DecodeStatus S = MCDisassembler::Success; 4974 4975 // Shift of "asr #32" is not allowed in Thumb2 mode. 4976 if (Val == 0x20) S = MCDisassembler::SoftFail; 4977 Inst.addOperand(MCOperand::CreateImm(Val)); 4978 return S; 4979 } 4980 4981 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4982 uint64_t Address, const void *Decoder) { 4983 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4984 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4985 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4986 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4987 4988 if (pred == 0xF) 4989 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4990 4991 DecodeStatus S = MCDisassembler::Success; 4992 4993 if (Rt == Rn || Rn == Rt2) 4994 S = MCDisassembler::SoftFail; 4995 4996 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4997 return MCDisassembler::Fail; 4998 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4999 return MCDisassembler::Fail; 5000 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5001 return MCDisassembler::Fail; 5002 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5003 return MCDisassembler::Fail; 5004 5005 return S; 5006 } 5007 5008 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5009 uint64_t Address, const void *Decoder) { 5010 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5011 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5012 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5013 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5014 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5015 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5016 unsigned op = fieldFromInstruction(Insn, 5, 1); 5017 5018 DecodeStatus S = MCDisassembler::Success; 5019 5020 // VMOVv2f32 is ambiguous with these decodings. 5021 if (!(imm & 0x38) && cmode == 0xF) { 5022 if (op == 1) return MCDisassembler::Fail; 5023 Inst.setOpcode(ARM::VMOVv2f32); 5024 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5025 } 5026 5027 if (!(imm & 0x20)) return MCDisassembler::Fail; 5028 5029 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5030 return MCDisassembler::Fail; 5031 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5032 return MCDisassembler::Fail; 5033 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 5034 5035 return S; 5036 } 5037 5038 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5039 uint64_t Address, const void *Decoder) { 5040 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5041 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5042 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5043 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5044 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5045 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5046 unsigned op = fieldFromInstruction(Insn, 5, 1); 5047 5048 DecodeStatus S = MCDisassembler::Success; 5049 5050 // VMOVv4f32 is ambiguous with these decodings. 5051 if (!(imm & 0x38) && cmode == 0xF) { 5052 if (op == 1) return MCDisassembler::Fail; 5053 Inst.setOpcode(ARM::VMOVv4f32); 5054 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5055 } 5056 5057 if (!(imm & 0x20)) return MCDisassembler::Fail; 5058 5059 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5060 return MCDisassembler::Fail; 5061 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5062 return MCDisassembler::Fail; 5063 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 5064 5065 return S; 5066 } 5067 5068 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5069 uint64_t Address, const void *Decoder) { 5070 DecodeStatus S = MCDisassembler::Success; 5071 5072 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5073 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5074 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5075 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5076 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5077 5078 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5079 S = MCDisassembler::SoftFail; 5080 5081 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5082 return MCDisassembler::Fail; 5083 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5084 return MCDisassembler::Fail; 5085 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5086 return MCDisassembler::Fail; 5087 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5088 return MCDisassembler::Fail; 5089 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5090 return MCDisassembler::Fail; 5091 5092 return S; 5093 } 5094 5095 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 5096 uint64_t Address, const void *Decoder) { 5097 5098 DecodeStatus S = MCDisassembler::Success; 5099 5100 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5101 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5102 unsigned cop = fieldFromInstruction(Val, 8, 4); 5103 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5104 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5105 5106 if ((cop & ~0x1) == 0xa) 5107 return MCDisassembler::Fail; 5108 5109 if (Rt == Rt2) 5110 S = MCDisassembler::SoftFail; 5111 5112 Inst.addOperand(MCOperand::CreateImm(cop)); 5113 Inst.addOperand(MCOperand::CreateImm(opc1)); 5114 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5115 return MCDisassembler::Fail; 5116 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5117 return MCDisassembler::Fail; 5118 Inst.addOperand(MCOperand::CreateImm(CRm)); 5119 5120 return S; 5121 } 5122 5123