1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDecoderOps.h" 17 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/MC/TargetRegistry.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 InstructionEndianness = STI.getFeatureBits()[ARM::ModeBigEndianInstructions] 135 ? llvm::support::big 136 : llvm::support::little; 137 } 138 139 ~ARMDisassembler() override = default; 140 141 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 142 ArrayRef<uint8_t> Bytes, uint64_t Address, 143 raw_ostream &CStream) const override; 144 145 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 146 uint64_t Address) const override; 147 148 private: 149 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 150 ArrayRef<uint8_t> Bytes, uint64_t Address, 151 raw_ostream &CStream) const; 152 153 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 154 ArrayRef<uint8_t> Bytes, uint64_t Address, 155 raw_ostream &CStream) const; 156 157 mutable ITStatus ITBlock; 158 mutable VPTStatus VPTBlock; 159 160 DecodeStatus AddThumbPredicate(MCInst&) const; 161 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 162 163 llvm::support::endianness InstructionEndianness; 164 }; 165 166 } // end anonymous namespace 167 168 // Forward declare these because the autogenerated code will reference them. 169 // Definitions are further down. 170 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 171 uint64_t Address, 172 const MCDisassembler *Decoder); 173 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 174 uint64_t Address, 175 const MCDisassembler *Decoder); 176 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, 178 const MCDisassembler *Decoder); 179 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, 181 const MCDisassembler *Decoder); 182 static DecodeStatus 183 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, 185 const MCDisassembler *Decoder); 186 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, 188 const MCDisassembler *Decoder); 189 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 190 uint64_t Address, 191 const MCDisassembler *Decoder); 192 static DecodeStatus 193 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 194 const MCDisassembler *Decoder); 195 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 196 uint64_t Address, 197 const MCDisassembler *Decoder); 198 static DecodeStatus 199 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 200 const MCDisassembler *Decoder); 201 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, 203 const MCDisassembler *Decoder); 204 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 205 uint64_t Address, 206 const MCDisassembler *Decoder); 207 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, 209 const MCDisassembler *Decoder); 210 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 211 uint64_t Address, 212 const MCDisassembler *Decoder); 213 static DecodeStatus 214 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 215 const MCDisassembler *Decoder); 216 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, 218 const MCDisassembler *Decoder); 219 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 220 uint64_t Address, 221 const MCDisassembler *Decoder); 222 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 223 uint64_t Address, 224 const MCDisassembler *Decoder); 225 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 226 uint64_t Address, 227 const MCDisassembler *Decoder); 228 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, 230 const MCDisassembler *Decoder); 231 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 232 uint64_t Address, 233 const MCDisassembler *Decoder); 234 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 235 uint64_t Address, 236 const MCDisassembler *Decoder); 237 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 238 uint64_t Address, 239 const MCDisassembler *Decoder); 240 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 241 uint64_t Address, 242 const MCDisassembler *Decoder); 243 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 244 uint64_t Address, 245 const MCDisassembler *Decoder); 246 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 247 uint64_t Address, 248 const MCDisassembler *Decoder); 249 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 250 uint64_t Address, 251 const MCDisassembler *Decoder); 252 static DecodeStatus 253 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 254 const MCDisassembler *Decoder); 255 256 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 257 uint64_t Address, 258 const MCDisassembler *Decoder); 259 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 260 uint64_t Address, 261 const MCDisassembler *Decoder); 262 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 263 uint64_t Address, 264 const MCDisassembler *Decoder); 265 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 266 uint64_t Address, 267 const MCDisassembler *Decoder); 268 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 269 uint64_t Address, 270 const MCDisassembler *Decoder); 271 272 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 273 uint64_t Address, 274 const MCDisassembler *Decoder); 275 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, 277 const MCDisassembler *Decoder); 278 static DecodeStatus 279 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 280 const MCDisassembler *Decoder); 281 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 282 uint64_t Address, 283 const MCDisassembler *Decoder); 284 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 285 uint64_t Address, 286 const MCDisassembler *Decoder); 287 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 288 uint64_t Address, 289 const MCDisassembler *Decoder); 290 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 291 uint64_t Address, 292 const MCDisassembler *Decoder); 293 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 294 uint64_t Address, 295 const MCDisassembler *Decoder); 296 297 static DecodeStatus 298 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 299 uint64_t Adddress, 300 const MCDisassembler *Decoder); 301 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 302 uint64_t Address, 303 const MCDisassembler *Decoder); 304 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 305 uint64_t Address, 306 const MCDisassembler *Decoder); 307 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 308 uint64_t Address, 309 const MCDisassembler *Decoder); 310 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 311 uint64_t Address, 312 const MCDisassembler *Decoder); 313 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 314 uint64_t Address, 315 const MCDisassembler *Decoder); 316 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 317 uint64_t Address, 318 const MCDisassembler *Decoder); 319 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 320 uint64_t Address, 321 const MCDisassembler *Decoder); 322 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 323 uint64_t Address, 324 const MCDisassembler *Decoder); 325 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, 326 uint64_t Address, 327 const MCDisassembler *Decoder); 328 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 329 uint64_t Address, 330 const MCDisassembler *Decoder); 331 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 332 uint64_t Address, 333 const MCDisassembler *Decoder); 334 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 335 uint64_t Address, 336 const MCDisassembler *Decoder); 337 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 338 uint64_t Address, 339 const MCDisassembler *Decoder); 340 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 341 uint64_t Address, 342 const MCDisassembler *Decoder); 343 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 344 uint64_t Address, 345 const MCDisassembler *Decoder); 346 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 347 uint64_t Address, 348 const MCDisassembler *Decoder); 349 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 350 uint64_t Address, 351 const MCDisassembler *Decoder); 352 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 353 uint64_t Address, 354 const MCDisassembler *Decoder); 355 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 356 uint64_t Address, 357 const MCDisassembler *Decoder); 358 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 359 uint64_t Address, 360 const MCDisassembler *Decoder); 361 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 362 uint64_t Address, 363 const MCDisassembler *Decoder); 364 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 365 uint64_t Address, 366 const MCDisassembler *Decoder); 367 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 368 uint64_t Address, 369 const MCDisassembler *Decoder); 370 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 371 uint64_t Address, 372 const MCDisassembler *Decoder); 373 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 374 uint64_t Address, 375 const MCDisassembler *Decoder); 376 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 377 uint64_t Address, 378 const MCDisassembler *Decoder); 379 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val, 380 uint64_t Address, 381 const MCDisassembler *Decoder); 382 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val, 383 uint64_t Address, 384 const MCDisassembler *Decoder); 385 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 386 uint64_t Address, 387 const MCDisassembler *Decoder); 388 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 389 uint64_t Address, 390 const MCDisassembler *Decoder); 391 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 392 uint64_t Address, 393 const MCDisassembler *Decoder); 394 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 395 uint64_t Address, 396 const MCDisassembler *Decoder); 397 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 398 uint64_t Address, 399 const MCDisassembler *Decoder); 400 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 401 uint64_t Address, 402 const MCDisassembler *Decoder); 403 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 404 uint64_t Address, 405 const MCDisassembler *Decoder); 406 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 407 uint64_t Address, 408 const MCDisassembler *Decoder); 409 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 410 uint64_t Address, 411 const MCDisassembler *Decoder); 412 template <int shift> 413 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 414 uint64_t Address, 415 const MCDisassembler *Decoder); 416 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 417 uint64_t Address, 418 const MCDisassembler *Decoder); 419 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 420 uint64_t Address, 421 const MCDisassembler *Decoder); 422 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 423 uint64_t Address, 424 const MCDisassembler *Decoder); 425 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, 426 const MCDisassembler *Decoder); 427 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 428 uint64_t Address, 429 const MCDisassembler *Decoder); 430 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 431 uint64_t Address, 432 const MCDisassembler *Decoder); 433 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 434 uint64_t Address, 435 const MCDisassembler *Decoder); 436 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 437 uint64_t Address, 438 const MCDisassembler *Decoder); 439 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 440 uint64_t Address, 441 const MCDisassembler *Decoder); 442 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 443 uint64_t Address, 444 const MCDisassembler *Decoder); 445 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 446 uint64_t Address, 447 const MCDisassembler *Decoder); 448 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 449 const MCDisassembler *Decoder); 450 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 451 const MCDisassembler *Decoder); 452 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 453 const MCDisassembler *Decoder); 454 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 455 const MCDisassembler *Decoder); 456 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 457 const MCDisassembler *Decoder); 458 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 459 const MCDisassembler *Decoder); 460 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 461 const MCDisassembler *Decoder); 462 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 463 const MCDisassembler *Decoder); 464 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 465 const MCDisassembler *Decoder); 466 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 467 const MCDisassembler *Decoder); 468 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 469 const MCDisassembler *Decoder); 470 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 471 const MCDisassembler *Decoder); 472 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 473 const MCDisassembler *Decoder); 474 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 475 uint64_t Address, 476 const MCDisassembler *Decoder); 477 static DecodeStatus 478 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, 479 const MCDisassembler *Decoder); 480 481 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 482 uint64_t Address, 483 const MCDisassembler *Decoder); 484 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 485 uint64_t Address, 486 const MCDisassembler *Decoder); 487 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 488 uint64_t Address, 489 const MCDisassembler *Decoder); 490 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 491 uint64_t Address, 492 const MCDisassembler *Decoder); 493 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 494 uint64_t Address, 495 const MCDisassembler *Decoder); 496 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 497 uint64_t Address, 498 const MCDisassembler *Decoder); 499 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 500 uint64_t Address, 501 const MCDisassembler *Decoder); 502 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const MCDisassembler *Decoder); 505 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 506 uint64_t Address, 507 const MCDisassembler *Decoder); 508 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 509 uint64_t Address, 510 const MCDisassembler *Decoder); 511 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 512 uint64_t Address, 513 const MCDisassembler *Decoder); 514 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 515 uint64_t Address, 516 const MCDisassembler *Decoder); 517 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 518 const MCDisassembler *Decoder); 519 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 520 uint64_t Address, 521 const MCDisassembler *Decoder); 522 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 523 const MCDisassembler *Decoder); 524 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 525 const MCDisassembler *Decoder); 526 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 527 uint64_t Address, 528 const MCDisassembler *Decoder); 529 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 530 uint64_t Address, 531 const MCDisassembler *Decoder); 532 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 533 uint64_t Address, 534 const MCDisassembler *Decoder); 535 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 536 const MCDisassembler *Decoder); 537 template <int shift> 538 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 539 const MCDisassembler *Decoder); 540 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 541 uint64_t Address, 542 const MCDisassembler *Decoder); 543 template <int shift> 544 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 545 uint64_t Address, 546 const MCDisassembler *Decoder); 547 template <int shift, int WriteBack> 548 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 549 uint64_t Address, 550 const MCDisassembler *Decoder); 551 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 552 uint64_t Address, 553 const MCDisassembler *Decoder); 554 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 555 uint64_t Address, 556 const MCDisassembler *Decoder); 557 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 558 uint64_t Address, 559 const MCDisassembler *Decoder); 560 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 561 uint64_t Address, 562 const MCDisassembler *Decoder); 563 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 564 uint64_t Address, 565 const MCDisassembler *Decoder); 566 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 567 uint64_t Address, 568 const MCDisassembler *Decoder); 569 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 570 uint64_t Address, 571 const MCDisassembler *Decoder); 572 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 573 uint64_t Address, 574 const MCDisassembler *Decoder); 575 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 576 const MCDisassembler *Decoder); 577 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 578 uint64_t Address, 579 const MCDisassembler *Decoder); 580 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 581 uint64_t Address, 582 const MCDisassembler *Decoder); 583 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, 584 const MCDisassembler *Decoder); 585 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 586 uint64_t Address, 587 const MCDisassembler *Decoder); 588 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 589 uint64_t Address, 590 const MCDisassembler *Decoder); 591 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, 592 const MCDisassembler *Decoder); 593 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 594 uint64_t Address, 595 const MCDisassembler *Decoder); 596 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 597 uint64_t Address, 598 const MCDisassembler *Decoder); 599 600 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 601 const MCDisassembler *Decoder); 602 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 603 uint64_t Address, 604 const MCDisassembler *Decoder); 605 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 606 uint64_t Address, 607 const MCDisassembler *Decoder); 608 609 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 610 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 611 uint64_t Address, 612 const MCDisassembler *Decoder); 613 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 614 uint64_t Address, 615 const MCDisassembler *Decoder); 616 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 617 uint64_t Address, 618 const MCDisassembler *Decoder); 619 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 620 const MCDisassembler *Decoder); 621 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 622 uint64_t Address, 623 const MCDisassembler *Decoder); 624 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 625 const MCDisassembler *Decoder); 626 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 627 uint64_t Address, 628 const MCDisassembler *Decoder); 629 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 630 uint64_t Address, 631 const MCDisassembler *Decoder); 632 static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val, 633 uint64_t Address, 634 const MCDisassembler *Decoder); 635 static DecodeStatus 636 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 637 const MCDisassembler *Decoder); 638 static DecodeStatus 639 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 640 const MCDisassembler *Decoder); 641 static DecodeStatus 642 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 643 const MCDisassembler *Decoder); 644 static DecodeStatus 645 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 646 const MCDisassembler *Decoder); 647 template <bool Writeback> 648 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 649 uint64_t Address, 650 const MCDisassembler *Decoder); 651 template <int shift> 652 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 653 uint64_t Address, 654 const MCDisassembler *Decoder); 655 template <int shift> 656 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 657 uint64_t Address, 658 const MCDisassembler *Decoder); 659 template <int shift> 660 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 661 uint64_t Address, 662 const MCDisassembler *Decoder); 663 template <unsigned MinLog, unsigned MaxLog> 664 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 665 uint64_t Address, 666 const MCDisassembler *Decoder); 667 template <unsigned start> 668 static DecodeStatus 669 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 670 const MCDisassembler *Decoder); 671 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 672 uint64_t Address, 673 const MCDisassembler *Decoder); 674 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 675 uint64_t Address, 676 const MCDisassembler *Decoder); 677 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 678 uint64_t Address, 679 const MCDisassembler *Decoder); 680 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 681 uint64_t Address, 682 const MCDisassembler *Decoder); 683 template <bool scalar, OperandDecoder predicate_decoder> 684 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 685 const MCDisassembler *Decoder); 686 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 687 const MCDisassembler *Decoder); 688 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 689 uint64_t Address, 690 const MCDisassembler *Decoder); 691 static DecodeStatus 692 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 693 const MCDisassembler *Decoder); 694 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 695 uint64_t Address, 696 const MCDisassembler *Decoder); 697 698 #include "ARMGenDisassemblerTables.inc" 699 700 static MCDisassembler *createARMDisassembler(const Target &T, 701 const MCSubtargetInfo &STI, 702 MCContext &Ctx) { 703 return new ARMDisassembler(STI, Ctx); 704 } 705 706 // Post-decoding checks 707 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 708 uint64_t Address, raw_ostream &CS, 709 uint32_t Insn, 710 DecodeStatus Result) { 711 switch (MI.getOpcode()) { 712 case ARM::HVC: { 713 // HVC is undefined if condition = 0xf otherwise upredictable 714 // if condition != 0xe 715 uint32_t Cond = (Insn >> 28) & 0xF; 716 if (Cond == 0xF) 717 return MCDisassembler::Fail; 718 if (Cond != 0xE) 719 return MCDisassembler::SoftFail; 720 return Result; 721 } 722 case ARM::t2ADDri: 723 case ARM::t2ADDri12: 724 case ARM::t2ADDrr: 725 case ARM::t2ADDrs: 726 case ARM::t2SUBri: 727 case ARM::t2SUBri12: 728 case ARM::t2SUBrr: 729 case ARM::t2SUBrs: 730 if (MI.getOperand(0).getReg() == ARM::SP && 731 MI.getOperand(1).getReg() != ARM::SP) 732 return MCDisassembler::SoftFail; 733 return Result; 734 default: return Result; 735 } 736 } 737 738 uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 739 uint64_t Address) const { 740 // In Arm state, instructions are always 4 bytes wide, so there's no 741 // point in skipping any smaller number of bytes if an instruction 742 // can't be decoded. 743 if (!STI.getFeatureBits()[ARM::ModeThumb]) 744 return 4; 745 746 // In a Thumb instruction stream, a halfword is a standalone 2-byte 747 // instruction if and only if its value is less than 0xE800. 748 // Otherwise, it's the first halfword of a 4-byte instruction. 749 // 750 // So, if we can see the upcoming halfword, we can judge on that 751 // basis, and maybe skip a whole 4-byte instruction that we don't 752 // know how to decode, without accidentally trying to interpret its 753 // second half as something else. 754 // 755 // If we don't have the instruction data available, we just have to 756 // recommend skipping the minimum sensible distance, which is 2 757 // bytes. 758 if (Bytes.size() < 2) 759 return 2; 760 761 uint16_t Insn16 = llvm::support::endian::read<uint16_t>( 762 Bytes.data(), InstructionEndianness); 763 return Insn16 < 0xE800 ? 2 : 4; 764 } 765 766 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 767 ArrayRef<uint8_t> Bytes, 768 uint64_t Address, 769 raw_ostream &CS) const { 770 if (STI.getFeatureBits()[ARM::ModeThumb]) 771 return getThumbInstruction(MI, Size, Bytes, Address, CS); 772 return getARMInstruction(MI, Size, Bytes, Address, CS); 773 } 774 775 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 776 ArrayRef<uint8_t> Bytes, 777 uint64_t Address, 778 raw_ostream &CS) const { 779 CommentStream = &CS; 780 781 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 782 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 783 "mode!"); 784 785 // We want to read exactly 4 bytes of data. 786 if (Bytes.size() < 4) { 787 Size = 0; 788 return MCDisassembler::Fail; 789 } 790 791 // Encoded as a 32-bit word in the stream. 792 uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(), 793 InstructionEndianness); 794 795 // Calling the auto-generated decoder function. 796 DecodeStatus Result = 797 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 798 if (Result != MCDisassembler::Fail) { 799 Size = 4; 800 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 801 } 802 803 struct DecodeTable { 804 const uint8_t *P; 805 bool DecodePred; 806 }; 807 808 const DecodeTable Tables[] = { 809 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 810 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 811 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 812 {DecoderTablev8Crypto32, false}, 813 }; 814 815 for (auto Table : Tables) { 816 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 817 if (Result != MCDisassembler::Fail) { 818 Size = 4; 819 // Add a fake predicate operand, because we share these instruction 820 // definitions with Thumb2 where these instructions are predicable. 821 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 822 return MCDisassembler::Fail; 823 return Result; 824 } 825 } 826 827 Result = 828 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 829 if (Result != MCDisassembler::Fail) { 830 Size = 4; 831 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 832 } 833 834 Size = 4; 835 return MCDisassembler::Fail; 836 } 837 838 namespace llvm { 839 840 extern const MCInstrDesc ARMInsts[]; 841 842 } // end namespace llvm 843 844 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 845 /// immediate Value in the MCInst. The immediate Value has had any PC 846 /// adjustment made by the caller. If the instruction is a branch instruction 847 /// then isBranch is true, else false. If the getOpInfo() function was set as 848 /// part of the setupForSymbolicDisassembly() call then that function is called 849 /// to get any symbolic information at the Address for this instruction. If 850 /// that returns non-zero then the symbolic information it returns is used to 851 /// create an MCExpr and that is added as an operand to the MCInst. If 852 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 853 /// Value is done and if a symbol is found an MCExpr is created with that, else 854 /// an MCExpr with Value is created. This function returns true if it adds an 855 /// operand to the MCInst and false otherwise. 856 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 857 bool isBranch, uint64_t InstSize, 858 MCInst &MI, 859 const MCDisassembler *Decoder) { 860 // FIXME: Does it make sense for value to be negative? 861 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, 862 isBranch, /*Offset=*/0, /*OpSize=*/0, 863 InstSize); 864 } 865 866 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 867 /// referenced by a load instruction with the base register that is the Pc. 868 /// These can often be values in a literal pool near the Address of the 869 /// instruction. The Address of the instruction and its immediate Value are 870 /// used as a possible literal pool entry. The SymbolLookUp call back will 871 /// return the name of a symbol referenced by the literal pool's entry if 872 /// the referenced address is that of a symbol. Or it will return a pointer to 873 /// a literal 'C' string if the referenced address of the literal pool's entry 874 /// is an address into a section with 'C' string literals. 875 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 876 const MCDisassembler *Decoder) { 877 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 878 Dis->tryAddingPcLoadReferenceComment(Value, Address); 879 } 880 881 // Thumb1 instructions don't have explicit S bits. Rather, they 882 // implicitly set CPSR. Since it's not represented in the encoding, the 883 // auto-generated decoder won't inject the CPSR operand. We need to fix 884 // that as a post-pass. 885 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 886 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 887 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 888 MCInst::iterator I = MI.begin(); 889 for (unsigned i = 0; i < NumOps; ++i, ++I) { 890 if (I == MI.end()) break; 891 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 892 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 893 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 894 return; 895 } 896 } 897 898 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 899 } 900 901 static bool isVectorPredicable(unsigned Opcode) { 902 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 903 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 904 for (unsigned i = 0; i < NumOps; ++i) { 905 if (ARM::isVpred(OpInfo[i].OperandType)) 906 return true; 907 } 908 return false; 909 } 910 911 // Most Thumb instructions don't have explicit predicates in the 912 // encoding, but rather get their predicates from IT context. We need 913 // to fix up the predicate operands using this context information as a 914 // post-pass. 915 MCDisassembler::DecodeStatus 916 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 917 MCDisassembler::DecodeStatus S = Success; 918 919 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 920 921 // A few instructions actually have predicates encoded in them. Don't 922 // try to overwrite it if we're seeing one of those. 923 switch (MI.getOpcode()) { 924 case ARM::tBcc: 925 case ARM::t2Bcc: 926 case ARM::tCBZ: 927 case ARM::tCBNZ: 928 case ARM::tCPS: 929 case ARM::t2CPS3p: 930 case ARM::t2CPS2p: 931 case ARM::t2CPS1p: 932 case ARM::t2CSEL: 933 case ARM::t2CSINC: 934 case ARM::t2CSINV: 935 case ARM::t2CSNEG: 936 case ARM::tMOVSr: 937 case ARM::tSETEND: 938 // Some instructions (mostly conditional branches) are not 939 // allowed in IT blocks. 940 if (ITBlock.instrInITBlock()) 941 S = SoftFail; 942 else 943 return Success; 944 break; 945 case ARM::t2HINT: 946 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 947 S = SoftFail; 948 break; 949 case ARM::tB: 950 case ARM::t2B: 951 case ARM::t2TBB: 952 case ARM::t2TBH: 953 // Some instructions (mostly unconditional branches) can 954 // only appears at the end of, or outside of, an IT. 955 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 956 S = SoftFail; 957 break; 958 default: 959 break; 960 } 961 962 // Warn on non-VPT predicable instruction in a VPT block and a VPT 963 // predicable instruction in an IT block 964 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 965 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 966 S = SoftFail; 967 968 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 969 // assume a predicate of AL. 970 unsigned CC = ARMCC::AL; 971 unsigned VCC = ARMVCC::None; 972 if (ITBlock.instrInITBlock()) { 973 CC = ITBlock.getITCC(); 974 ITBlock.advanceITState(); 975 } else if (VPTBlock.instrInVPTBlock()) { 976 VCC = VPTBlock.getVPTPred(); 977 VPTBlock.advanceVPTState(); 978 } 979 980 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 981 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 982 983 MCInst::iterator CCI = MI.begin(); 984 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 985 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 986 } 987 988 if (ARMInsts[MI.getOpcode()].isPredicable()) { 989 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 990 ++CCI; 991 if (CC == ARMCC::AL) 992 MI.insert(CCI, MCOperand::createReg(0)); 993 else 994 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 995 } else if (CC != ARMCC::AL) { 996 Check(S, SoftFail); 997 } 998 999 MCInst::iterator VCCI = MI.begin(); 1000 unsigned VCCPos; 1001 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 1002 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 1003 } 1004 1005 if (isVectorPredicable(MI.getOpcode())) { 1006 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 1007 ++VCCI; 1008 if (VCC == ARMVCC::None) 1009 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1010 else 1011 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 1012 ++VCCI; 1013 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1014 ++VCCI; 1015 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 1016 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 1017 VCCPos + 3, MCOI::TIED_TO); 1018 assert(TiedOp >= 0 && 1019 "Inactive register in vpred_r is not tied to an output!"); 1020 // Copy the operand to ensure it's not invalidated when MI grows. 1021 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 1022 } 1023 } else if (VCC != ARMVCC::None) { 1024 Check(S, SoftFail); 1025 } 1026 1027 return S; 1028 } 1029 1030 // Thumb VFP instructions are a special case. Because we share their 1031 // encodings between ARM and Thumb modes, and they are predicable in ARM 1032 // mode, the auto-generated decoder will give them an (incorrect) 1033 // predicate operand. We need to rewrite these operands based on the IT 1034 // context as a post-pass. 1035 void ARMDisassembler::UpdateThumbVFPPredicate( 1036 DecodeStatus &S, MCInst &MI) const { 1037 unsigned CC; 1038 CC = ITBlock.getITCC(); 1039 if (CC == 0xF) 1040 CC = ARMCC::AL; 1041 if (ITBlock.instrInITBlock()) 1042 ITBlock.advanceITState(); 1043 else if (VPTBlock.instrInVPTBlock()) { 1044 CC = VPTBlock.getVPTPred(); 1045 VPTBlock.advanceVPTState(); 1046 } 1047 1048 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 1049 MCInst::iterator I = MI.begin(); 1050 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 1051 for (unsigned i = 0; i < NumOps; ++i, ++I) { 1052 if (OpInfo[i].isPredicate() ) { 1053 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 1054 Check(S, SoftFail); 1055 I->setImm(CC); 1056 ++I; 1057 if (CC == ARMCC::AL) 1058 I->setReg(0); 1059 else 1060 I->setReg(ARM::CPSR); 1061 return; 1062 } 1063 } 1064 } 1065 1066 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 1067 ArrayRef<uint8_t> Bytes, 1068 uint64_t Address, 1069 raw_ostream &CS) const { 1070 CommentStream = &CS; 1071 1072 assert(STI.getFeatureBits()[ARM::ModeThumb] && 1073 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 1074 1075 // We want to read exactly 2 bytes of data. 1076 if (Bytes.size() < 2) { 1077 Size = 0; 1078 return MCDisassembler::Fail; 1079 } 1080 1081 uint16_t Insn16 = llvm::support::endian::read<uint16_t>( 1082 Bytes.data(), InstructionEndianness); 1083 DecodeStatus Result = 1084 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 1085 if (Result != MCDisassembler::Fail) { 1086 Size = 2; 1087 Check(Result, AddThumbPredicate(MI)); 1088 return Result; 1089 } 1090 1091 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 1092 STI); 1093 if (Result) { 1094 Size = 2; 1095 bool InITBlock = ITBlock.instrInITBlock(); 1096 Check(Result, AddThumbPredicate(MI)); 1097 AddThumb1SBit(MI, InITBlock); 1098 return Result; 1099 } 1100 1101 Result = 1102 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 1103 if (Result != MCDisassembler::Fail) { 1104 Size = 2; 1105 1106 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 1107 // the Thumb predicate. 1108 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 1109 Result = MCDisassembler::SoftFail; 1110 1111 Check(Result, AddThumbPredicate(MI)); 1112 1113 // If we find an IT instruction, we need to parse its condition 1114 // code and mask operands so that we can apply them correctly 1115 // to the subsequent instructions. 1116 if (MI.getOpcode() == ARM::t2IT) { 1117 unsigned Firstcond = MI.getOperand(0).getImm(); 1118 unsigned Mask = MI.getOperand(1).getImm(); 1119 ITBlock.setITState(Firstcond, Mask); 1120 1121 // An IT instruction that would give a 'NV' predicate is unpredictable. 1122 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 1123 CS << "unpredictable IT predicate sequence"; 1124 } 1125 1126 return Result; 1127 } 1128 1129 // We want to read exactly 4 bytes of data. 1130 if (Bytes.size() < 4) { 1131 Size = 0; 1132 return MCDisassembler::Fail; 1133 } 1134 1135 uint32_t Insn32 = 1136 (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>( 1137 Bytes.data() + 2, InstructionEndianness); 1138 1139 Result = 1140 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 1141 if (Result != MCDisassembler::Fail) { 1142 Size = 4; 1143 1144 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 1145 // the VPT predicate. 1146 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 1147 Result = MCDisassembler::SoftFail; 1148 1149 Check(Result, AddThumbPredicate(MI)); 1150 1151 if (isVPTOpcode(MI.getOpcode())) { 1152 unsigned Mask = MI.getOperand(0).getImm(); 1153 VPTBlock.setVPTState(Mask); 1154 } 1155 1156 return Result; 1157 } 1158 1159 Result = 1160 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1161 if (Result != MCDisassembler::Fail) { 1162 Size = 4; 1163 bool InITBlock = ITBlock.instrInITBlock(); 1164 Check(Result, AddThumbPredicate(MI)); 1165 AddThumb1SBit(MI, InITBlock); 1166 return Result; 1167 } 1168 1169 Result = 1170 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1171 if (Result != MCDisassembler::Fail) { 1172 Size = 4; 1173 Check(Result, AddThumbPredicate(MI)); 1174 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1175 } 1176 1177 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1178 Result = 1179 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1180 if (Result != MCDisassembler::Fail) { 1181 Size = 4; 1182 UpdateThumbVFPPredicate(Result, MI); 1183 return Result; 1184 } 1185 } 1186 1187 Result = 1188 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1189 if (Result != MCDisassembler::Fail) { 1190 Size = 4; 1191 return Result; 1192 } 1193 1194 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1195 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1196 STI); 1197 if (Result != MCDisassembler::Fail) { 1198 Size = 4; 1199 Check(Result, AddThumbPredicate(MI)); 1200 return Result; 1201 } 1202 } 1203 1204 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1205 uint32_t NEONLdStInsn = Insn32; 1206 NEONLdStInsn &= 0xF0FFFFFF; 1207 NEONLdStInsn |= 0x04000000; 1208 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1209 Address, this, STI); 1210 if (Result != MCDisassembler::Fail) { 1211 Size = 4; 1212 Check(Result, AddThumbPredicate(MI)); 1213 return Result; 1214 } 1215 } 1216 1217 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1218 uint32_t NEONDataInsn = Insn32; 1219 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1220 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1221 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1222 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1223 Address, this, STI); 1224 if (Result != MCDisassembler::Fail) { 1225 Size = 4; 1226 Check(Result, AddThumbPredicate(MI)); 1227 return Result; 1228 } 1229 1230 uint32_t NEONCryptoInsn = Insn32; 1231 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1232 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1233 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1234 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1235 Address, this, STI); 1236 if (Result != MCDisassembler::Fail) { 1237 Size = 4; 1238 return Result; 1239 } 1240 1241 uint32_t NEONv8Insn = Insn32; 1242 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1243 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1244 this, STI); 1245 if (Result != MCDisassembler::Fail) { 1246 Size = 4; 1247 return Result; 1248 } 1249 } 1250 1251 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1252 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1253 ? DecoderTableThumb2CDE32 1254 : DecoderTableThumb2CoProc32; 1255 Result = 1256 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1257 if (Result != MCDisassembler::Fail) { 1258 Size = 4; 1259 Check(Result, AddThumbPredicate(MI)); 1260 return Result; 1261 } 1262 1263 Size = 0; 1264 return MCDisassembler::Fail; 1265 } 1266 1267 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1268 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1269 createARMDisassembler); 1270 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1271 createARMDisassembler); 1272 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1273 createARMDisassembler); 1274 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1275 createARMDisassembler); 1276 } 1277 1278 static const uint16_t GPRDecoderTable[] = { 1279 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1280 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1281 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1282 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1283 }; 1284 1285 static const uint16_t CLRMGPRDecoderTable[] = { 1286 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1287 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1288 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1289 ARM::R12, 0, ARM::LR, ARM::APSR 1290 }; 1291 1292 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1293 uint64_t Address, 1294 const MCDisassembler *Decoder) { 1295 if (RegNo > 15) 1296 return MCDisassembler::Fail; 1297 1298 unsigned Register = GPRDecoderTable[RegNo]; 1299 Inst.addOperand(MCOperand::createReg(Register)); 1300 return MCDisassembler::Success; 1301 } 1302 1303 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1304 uint64_t Address, 1305 const MCDisassembler *Decoder) { 1306 if (RegNo > 15) 1307 return MCDisassembler::Fail; 1308 1309 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1310 if (Register == 0) 1311 return MCDisassembler::Fail; 1312 1313 Inst.addOperand(MCOperand::createReg(Register)); 1314 return MCDisassembler::Success; 1315 } 1316 1317 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1318 uint64_t Address, 1319 const MCDisassembler *Decoder) { 1320 DecodeStatus S = MCDisassembler::Success; 1321 1322 if (RegNo == 15) 1323 S = MCDisassembler::SoftFail; 1324 1325 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1326 1327 return S; 1328 } 1329 1330 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1331 uint64_t Address, 1332 const MCDisassembler *Decoder) { 1333 DecodeStatus S = MCDisassembler::Success; 1334 1335 if (RegNo == 13) 1336 S = MCDisassembler::SoftFail; 1337 1338 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1339 1340 return S; 1341 } 1342 1343 static DecodeStatus 1344 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1345 const MCDisassembler *Decoder) { 1346 DecodeStatus S = MCDisassembler::Success; 1347 1348 if (RegNo == 15) 1349 { 1350 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1351 return MCDisassembler::Success; 1352 } 1353 1354 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1355 return S; 1356 } 1357 1358 static DecodeStatus 1359 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1360 const MCDisassembler *Decoder) { 1361 DecodeStatus S = MCDisassembler::Success; 1362 1363 if (RegNo == 15) 1364 { 1365 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1366 return MCDisassembler::Success; 1367 } 1368 1369 if (RegNo == 13) 1370 Check(S, MCDisassembler::SoftFail); 1371 1372 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1373 return S; 1374 } 1375 1376 static DecodeStatus 1377 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1378 const MCDisassembler *Decoder) { 1379 DecodeStatus S = MCDisassembler::Success; 1380 if (RegNo == 13) 1381 return MCDisassembler::Fail; 1382 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1383 return S; 1384 } 1385 1386 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1387 uint64_t Address, 1388 const MCDisassembler *Decoder) { 1389 if (RegNo > 7) 1390 return MCDisassembler::Fail; 1391 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1392 } 1393 1394 static const uint16_t GPRPairDecoderTable[] = { 1395 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1396 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1397 }; 1398 1399 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1400 uint64_t Address, 1401 const MCDisassembler *Decoder) { 1402 DecodeStatus S = MCDisassembler::Success; 1403 1404 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1405 // rather than SoftFail as there is no GPRPair table entry for index 7. 1406 if (RegNo > 13) 1407 return MCDisassembler::Fail; 1408 1409 if (RegNo & 1) 1410 S = MCDisassembler::SoftFail; 1411 1412 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1413 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1414 return S; 1415 } 1416 1417 static DecodeStatus 1418 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1419 const MCDisassembler *Decoder) { 1420 if (RegNo > 13) 1421 return MCDisassembler::Fail; 1422 1423 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1424 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1425 1426 if ((RegNo & 1) || RegNo > 10) 1427 return MCDisassembler::SoftFail; 1428 return MCDisassembler::Success; 1429 } 1430 1431 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1432 uint64_t Address, 1433 const MCDisassembler *Decoder) { 1434 if (RegNo != 13) 1435 return MCDisassembler::Fail; 1436 1437 unsigned Register = GPRDecoderTable[RegNo]; 1438 Inst.addOperand(MCOperand::createReg(Register)); 1439 return MCDisassembler::Success; 1440 } 1441 1442 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1443 uint64_t Address, 1444 const MCDisassembler *Decoder) { 1445 unsigned Register = 0; 1446 switch (RegNo) { 1447 case 0: 1448 Register = ARM::R0; 1449 break; 1450 case 1: 1451 Register = ARM::R1; 1452 break; 1453 case 2: 1454 Register = ARM::R2; 1455 break; 1456 case 3: 1457 Register = ARM::R3; 1458 break; 1459 case 9: 1460 Register = ARM::R9; 1461 break; 1462 case 12: 1463 Register = ARM::R12; 1464 break; 1465 default: 1466 return MCDisassembler::Fail; 1467 } 1468 1469 Inst.addOperand(MCOperand::createReg(Register)); 1470 return MCDisassembler::Success; 1471 } 1472 1473 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1474 uint64_t Address, 1475 const MCDisassembler *Decoder) { 1476 DecodeStatus S = MCDisassembler::Success; 1477 1478 const FeatureBitset &featureBits = 1479 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1480 1481 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1482 S = MCDisassembler::SoftFail; 1483 1484 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1485 return S; 1486 } 1487 1488 static const uint16_t SPRDecoderTable[] = { 1489 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1490 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1491 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1492 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1493 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1494 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1495 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1496 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1497 }; 1498 1499 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1500 uint64_t Address, 1501 const MCDisassembler *Decoder) { 1502 if (RegNo > 31) 1503 return MCDisassembler::Fail; 1504 1505 unsigned Register = SPRDecoderTable[RegNo]; 1506 Inst.addOperand(MCOperand::createReg(Register)); 1507 return MCDisassembler::Success; 1508 } 1509 1510 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1511 uint64_t Address, 1512 const MCDisassembler *Decoder) { 1513 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1514 } 1515 1516 static const uint16_t DPRDecoderTable[] = { 1517 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1518 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1519 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1520 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1521 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1522 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1523 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1524 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1525 }; 1526 1527 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1528 uint64_t Address, 1529 const MCDisassembler *Decoder) { 1530 const FeatureBitset &featureBits = 1531 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1532 1533 bool hasD32 = featureBits[ARM::FeatureD32]; 1534 1535 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1536 return MCDisassembler::Fail; 1537 1538 unsigned Register = DPRDecoderTable[RegNo]; 1539 Inst.addOperand(MCOperand::createReg(Register)); 1540 return MCDisassembler::Success; 1541 } 1542 1543 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1544 uint64_t Address, 1545 const MCDisassembler *Decoder) { 1546 if (RegNo > 7) 1547 return MCDisassembler::Fail; 1548 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1549 } 1550 1551 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1552 uint64_t Address, 1553 const MCDisassembler *Decoder) { 1554 if (RegNo > 15) 1555 return MCDisassembler::Fail; 1556 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1557 } 1558 1559 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1560 uint64_t Address, 1561 const MCDisassembler *Decoder) { 1562 if (RegNo > 15) 1563 return MCDisassembler::Fail; 1564 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1565 } 1566 1567 static const uint16_t QPRDecoderTable[] = { 1568 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1569 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1570 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1571 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1572 }; 1573 1574 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1575 uint64_t Address, 1576 const MCDisassembler *Decoder) { 1577 if (RegNo > 31 || (RegNo & 1) != 0) 1578 return MCDisassembler::Fail; 1579 RegNo >>= 1; 1580 1581 unsigned Register = QPRDecoderTable[RegNo]; 1582 Inst.addOperand(MCOperand::createReg(Register)); 1583 return MCDisassembler::Success; 1584 } 1585 1586 static const uint16_t DPairDecoderTable[] = { 1587 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1588 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1589 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1590 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1591 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1592 ARM::Q15 1593 }; 1594 1595 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1596 uint64_t Address, 1597 const MCDisassembler *Decoder) { 1598 if (RegNo > 30) 1599 return MCDisassembler::Fail; 1600 1601 unsigned Register = DPairDecoderTable[RegNo]; 1602 Inst.addOperand(MCOperand::createReg(Register)); 1603 return MCDisassembler::Success; 1604 } 1605 1606 static const uint16_t DPairSpacedDecoderTable[] = { 1607 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1608 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1609 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1610 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1611 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1612 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1613 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1614 ARM::D28_D30, ARM::D29_D31 1615 }; 1616 1617 static DecodeStatus 1618 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1619 const MCDisassembler *Decoder) { 1620 if (RegNo > 29) 1621 return MCDisassembler::Fail; 1622 1623 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1624 Inst.addOperand(MCOperand::createReg(Register)); 1625 return MCDisassembler::Success; 1626 } 1627 1628 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1629 uint64_t Address, 1630 const MCDisassembler *Decoder) { 1631 DecodeStatus S = MCDisassembler::Success; 1632 if (Val == 0xF) return MCDisassembler::Fail; 1633 // AL predicate is not allowed on Thumb1 branches. 1634 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1635 return MCDisassembler::Fail; 1636 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1637 Check(S, MCDisassembler::SoftFail); 1638 Inst.addOperand(MCOperand::createImm(Val)); 1639 if (Val == ARMCC::AL) { 1640 Inst.addOperand(MCOperand::createReg(0)); 1641 } else 1642 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1643 return S; 1644 } 1645 1646 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1647 uint64_t Address, 1648 const MCDisassembler *Decoder) { 1649 if (Val) 1650 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1651 else 1652 Inst.addOperand(MCOperand::createReg(0)); 1653 return MCDisassembler::Success; 1654 } 1655 1656 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1657 uint64_t Address, 1658 const MCDisassembler *Decoder) { 1659 DecodeStatus S = MCDisassembler::Success; 1660 1661 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1662 unsigned type = fieldFromInstruction(Val, 5, 2); 1663 unsigned imm = fieldFromInstruction(Val, 7, 5); 1664 1665 // Register-immediate 1666 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1667 return MCDisassembler::Fail; 1668 1669 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1670 switch (type) { 1671 case 0: 1672 Shift = ARM_AM::lsl; 1673 break; 1674 case 1: 1675 Shift = ARM_AM::lsr; 1676 break; 1677 case 2: 1678 Shift = ARM_AM::asr; 1679 break; 1680 case 3: 1681 Shift = ARM_AM::ror; 1682 break; 1683 } 1684 1685 if (Shift == ARM_AM::ror && imm == 0) 1686 Shift = ARM_AM::rrx; 1687 1688 unsigned Op = Shift | (imm << 3); 1689 Inst.addOperand(MCOperand::createImm(Op)); 1690 1691 return S; 1692 } 1693 1694 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1695 uint64_t Address, 1696 const MCDisassembler *Decoder) { 1697 DecodeStatus S = MCDisassembler::Success; 1698 1699 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1700 unsigned type = fieldFromInstruction(Val, 5, 2); 1701 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1702 1703 // Register-register 1704 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1705 return MCDisassembler::Fail; 1706 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1707 return MCDisassembler::Fail; 1708 1709 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1710 switch (type) { 1711 case 0: 1712 Shift = ARM_AM::lsl; 1713 break; 1714 case 1: 1715 Shift = ARM_AM::lsr; 1716 break; 1717 case 2: 1718 Shift = ARM_AM::asr; 1719 break; 1720 case 3: 1721 Shift = ARM_AM::ror; 1722 break; 1723 } 1724 1725 Inst.addOperand(MCOperand::createImm(Shift)); 1726 1727 return S; 1728 } 1729 1730 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1731 uint64_t Address, 1732 const MCDisassembler *Decoder) { 1733 DecodeStatus S = MCDisassembler::Success; 1734 1735 bool NeedDisjointWriteback = false; 1736 unsigned WritebackReg = 0; 1737 bool CLRM = false; 1738 switch (Inst.getOpcode()) { 1739 default: 1740 break; 1741 case ARM::LDMIA_UPD: 1742 case ARM::LDMDB_UPD: 1743 case ARM::LDMIB_UPD: 1744 case ARM::LDMDA_UPD: 1745 case ARM::t2LDMIA_UPD: 1746 case ARM::t2LDMDB_UPD: 1747 case ARM::t2STMIA_UPD: 1748 case ARM::t2STMDB_UPD: 1749 NeedDisjointWriteback = true; 1750 WritebackReg = Inst.getOperand(0).getReg(); 1751 break; 1752 case ARM::t2CLRM: 1753 CLRM = true; 1754 break; 1755 } 1756 1757 // Empty register lists are not allowed. 1758 if (Val == 0) return MCDisassembler::Fail; 1759 for (unsigned i = 0; i < 16; ++i) { 1760 if (Val & (1 << i)) { 1761 if (CLRM) { 1762 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1763 return MCDisassembler::Fail; 1764 } 1765 } else { 1766 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1767 return MCDisassembler::Fail; 1768 // Writeback not allowed if Rn is in the target list. 1769 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1770 Check(S, MCDisassembler::SoftFail); 1771 } 1772 } 1773 } 1774 1775 return S; 1776 } 1777 1778 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1779 uint64_t Address, 1780 const MCDisassembler *Decoder) { 1781 DecodeStatus S = MCDisassembler::Success; 1782 1783 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1784 unsigned regs = fieldFromInstruction(Val, 0, 8); 1785 1786 // In case of unpredictable encoding, tweak the operands. 1787 if (regs == 0 || (Vd + regs) > 32) { 1788 regs = Vd + regs > 32 ? 32 - Vd : regs; 1789 regs = std::max( 1u, regs); 1790 S = MCDisassembler::SoftFail; 1791 } 1792 1793 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 for (unsigned i = 0; i < (regs - 1); ++i) { 1796 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1797 return MCDisassembler::Fail; 1798 } 1799 1800 return S; 1801 } 1802 1803 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1804 uint64_t Address, 1805 const MCDisassembler *Decoder) { 1806 DecodeStatus S = MCDisassembler::Success; 1807 1808 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1809 unsigned regs = fieldFromInstruction(Val, 1, 7); 1810 1811 // In case of unpredictable encoding, tweak the operands. 1812 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1813 regs = Vd + regs > 32 ? 32 - Vd : regs; 1814 regs = std::max( 1u, regs); 1815 regs = std::min(16u, regs); 1816 S = MCDisassembler::SoftFail; 1817 } 1818 1819 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1820 return MCDisassembler::Fail; 1821 for (unsigned i = 0; i < (regs - 1); ++i) { 1822 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1823 return MCDisassembler::Fail; 1824 } 1825 1826 return S; 1827 } 1828 1829 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1830 uint64_t Address, 1831 const MCDisassembler *Decoder) { 1832 // This operand encodes a mask of contiguous zeros between a specified MSB 1833 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1834 // the mask of all bits LSB-and-lower, and then xor them to create 1835 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1836 // create the final mask. 1837 unsigned msb = fieldFromInstruction(Val, 5, 5); 1838 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1839 1840 DecodeStatus S = MCDisassembler::Success; 1841 if (lsb > msb) { 1842 Check(S, MCDisassembler::SoftFail); 1843 // The check above will cause the warning for the "potentially undefined 1844 // instruction encoding" but we can't build a bad MCOperand value here 1845 // with a lsb > msb or else printing the MCInst will cause a crash. 1846 lsb = msb; 1847 } 1848 1849 uint32_t msb_mask = 0xFFFFFFFF; 1850 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1851 uint32_t lsb_mask = (1U << lsb) - 1; 1852 1853 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1854 return S; 1855 } 1856 1857 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1858 uint64_t Address, 1859 const MCDisassembler *Decoder) { 1860 DecodeStatus S = MCDisassembler::Success; 1861 1862 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1863 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1864 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1865 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1866 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1867 unsigned U = fieldFromInstruction(Insn, 23, 1); 1868 const FeatureBitset &featureBits = 1869 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1870 1871 switch (Inst.getOpcode()) { 1872 case ARM::LDC_OFFSET: 1873 case ARM::LDC_PRE: 1874 case ARM::LDC_POST: 1875 case ARM::LDC_OPTION: 1876 case ARM::LDCL_OFFSET: 1877 case ARM::LDCL_PRE: 1878 case ARM::LDCL_POST: 1879 case ARM::LDCL_OPTION: 1880 case ARM::STC_OFFSET: 1881 case ARM::STC_PRE: 1882 case ARM::STC_POST: 1883 case ARM::STC_OPTION: 1884 case ARM::STCL_OFFSET: 1885 case ARM::STCL_PRE: 1886 case ARM::STCL_POST: 1887 case ARM::STCL_OPTION: 1888 case ARM::t2LDC_OFFSET: 1889 case ARM::t2LDC_PRE: 1890 case ARM::t2LDC_POST: 1891 case ARM::t2LDC_OPTION: 1892 case ARM::t2LDCL_OFFSET: 1893 case ARM::t2LDCL_PRE: 1894 case ARM::t2LDCL_POST: 1895 case ARM::t2LDCL_OPTION: 1896 case ARM::t2STC_OFFSET: 1897 case ARM::t2STC_PRE: 1898 case ARM::t2STC_POST: 1899 case ARM::t2STC_OPTION: 1900 case ARM::t2STCL_OFFSET: 1901 case ARM::t2STCL_PRE: 1902 case ARM::t2STCL_POST: 1903 case ARM::t2STCL_OPTION: 1904 case ARM::t2LDC2_OFFSET: 1905 case ARM::t2LDC2L_OFFSET: 1906 case ARM::t2LDC2_PRE: 1907 case ARM::t2LDC2L_PRE: 1908 case ARM::t2STC2_OFFSET: 1909 case ARM::t2STC2L_OFFSET: 1910 case ARM::t2STC2_PRE: 1911 case ARM::t2STC2L_PRE: 1912 case ARM::LDC2_OFFSET: 1913 case ARM::LDC2L_OFFSET: 1914 case ARM::LDC2_PRE: 1915 case ARM::LDC2L_PRE: 1916 case ARM::STC2_OFFSET: 1917 case ARM::STC2L_OFFSET: 1918 case ARM::STC2_PRE: 1919 case ARM::STC2L_PRE: 1920 case ARM::t2LDC2_OPTION: 1921 case ARM::t2STC2_OPTION: 1922 case ARM::t2LDC2_POST: 1923 case ARM::t2LDC2L_POST: 1924 case ARM::t2STC2_POST: 1925 case ARM::t2STC2L_POST: 1926 case ARM::LDC2_POST: 1927 case ARM::LDC2L_POST: 1928 case ARM::STC2_POST: 1929 case ARM::STC2L_POST: 1930 if (coproc == 0xA || coproc == 0xB || 1931 (featureBits[ARM::HasV8_1MMainlineOps] && 1932 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1933 coproc == 0xE || coproc == 0xF))) 1934 return MCDisassembler::Fail; 1935 break; 1936 default: 1937 break; 1938 } 1939 1940 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1941 return MCDisassembler::Fail; 1942 1943 Inst.addOperand(MCOperand::createImm(coproc)); 1944 Inst.addOperand(MCOperand::createImm(CRd)); 1945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1946 return MCDisassembler::Fail; 1947 1948 switch (Inst.getOpcode()) { 1949 case ARM::t2LDC2_OFFSET: 1950 case ARM::t2LDC2L_OFFSET: 1951 case ARM::t2LDC2_PRE: 1952 case ARM::t2LDC2L_PRE: 1953 case ARM::t2STC2_OFFSET: 1954 case ARM::t2STC2L_OFFSET: 1955 case ARM::t2STC2_PRE: 1956 case ARM::t2STC2L_PRE: 1957 case ARM::LDC2_OFFSET: 1958 case ARM::LDC2L_OFFSET: 1959 case ARM::LDC2_PRE: 1960 case ARM::LDC2L_PRE: 1961 case ARM::STC2_OFFSET: 1962 case ARM::STC2L_OFFSET: 1963 case ARM::STC2_PRE: 1964 case ARM::STC2L_PRE: 1965 case ARM::t2LDC_OFFSET: 1966 case ARM::t2LDCL_OFFSET: 1967 case ARM::t2LDC_PRE: 1968 case ARM::t2LDCL_PRE: 1969 case ARM::t2STC_OFFSET: 1970 case ARM::t2STCL_OFFSET: 1971 case ARM::t2STC_PRE: 1972 case ARM::t2STCL_PRE: 1973 case ARM::LDC_OFFSET: 1974 case ARM::LDCL_OFFSET: 1975 case ARM::LDC_PRE: 1976 case ARM::LDCL_PRE: 1977 case ARM::STC_OFFSET: 1978 case ARM::STCL_OFFSET: 1979 case ARM::STC_PRE: 1980 case ARM::STCL_PRE: 1981 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1982 Inst.addOperand(MCOperand::createImm(imm)); 1983 break; 1984 case ARM::t2LDC2_POST: 1985 case ARM::t2LDC2L_POST: 1986 case ARM::t2STC2_POST: 1987 case ARM::t2STC2L_POST: 1988 case ARM::LDC2_POST: 1989 case ARM::LDC2L_POST: 1990 case ARM::STC2_POST: 1991 case ARM::STC2L_POST: 1992 case ARM::t2LDC_POST: 1993 case ARM::t2LDCL_POST: 1994 case ARM::t2STC_POST: 1995 case ARM::t2STCL_POST: 1996 case ARM::LDC_POST: 1997 case ARM::LDCL_POST: 1998 case ARM::STC_POST: 1999 case ARM::STCL_POST: 2000 imm |= U << 8; 2001 [[fallthrough]]; 2002 default: 2003 // The 'option' variant doesn't encode 'U' in the immediate since 2004 // the immediate is unsigned [0,255]. 2005 Inst.addOperand(MCOperand::createImm(imm)); 2006 break; 2007 } 2008 2009 switch (Inst.getOpcode()) { 2010 case ARM::LDC_OFFSET: 2011 case ARM::LDC_PRE: 2012 case ARM::LDC_POST: 2013 case ARM::LDC_OPTION: 2014 case ARM::LDCL_OFFSET: 2015 case ARM::LDCL_PRE: 2016 case ARM::LDCL_POST: 2017 case ARM::LDCL_OPTION: 2018 case ARM::STC_OFFSET: 2019 case ARM::STC_PRE: 2020 case ARM::STC_POST: 2021 case ARM::STC_OPTION: 2022 case ARM::STCL_OFFSET: 2023 case ARM::STCL_PRE: 2024 case ARM::STCL_POST: 2025 case ARM::STCL_OPTION: 2026 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2027 return MCDisassembler::Fail; 2028 break; 2029 default: 2030 break; 2031 } 2032 2033 return S; 2034 } 2035 2036 static DecodeStatus 2037 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2038 const MCDisassembler *Decoder) { 2039 DecodeStatus S = MCDisassembler::Success; 2040 2041 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2042 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2043 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2044 unsigned imm = fieldFromInstruction(Insn, 0, 12); 2045 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2046 unsigned reg = fieldFromInstruction(Insn, 25, 1); 2047 unsigned P = fieldFromInstruction(Insn, 24, 1); 2048 unsigned W = fieldFromInstruction(Insn, 21, 1); 2049 2050 // On stores, the writeback operand precedes Rt. 2051 switch (Inst.getOpcode()) { 2052 case ARM::STR_POST_IMM: 2053 case ARM::STR_POST_REG: 2054 case ARM::STRB_POST_IMM: 2055 case ARM::STRB_POST_REG: 2056 case ARM::STRT_POST_REG: 2057 case ARM::STRT_POST_IMM: 2058 case ARM::STRBT_POST_REG: 2059 case ARM::STRBT_POST_IMM: 2060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2061 return MCDisassembler::Fail; 2062 break; 2063 default: 2064 break; 2065 } 2066 2067 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2068 return MCDisassembler::Fail; 2069 2070 // On loads, the writeback operand comes after Rt. 2071 switch (Inst.getOpcode()) { 2072 case ARM::LDR_POST_IMM: 2073 case ARM::LDR_POST_REG: 2074 case ARM::LDRB_POST_IMM: 2075 case ARM::LDRB_POST_REG: 2076 case ARM::LDRBT_POST_REG: 2077 case ARM::LDRBT_POST_IMM: 2078 case ARM::LDRT_POST_REG: 2079 case ARM::LDRT_POST_IMM: 2080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2081 return MCDisassembler::Fail; 2082 break; 2083 default: 2084 break; 2085 } 2086 2087 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2088 return MCDisassembler::Fail; 2089 2090 ARM_AM::AddrOpc Op = ARM_AM::add; 2091 if (!fieldFromInstruction(Insn, 23, 1)) 2092 Op = ARM_AM::sub; 2093 2094 bool writeback = (P == 0) || (W == 1); 2095 unsigned idx_mode = 0; 2096 if (P && writeback) 2097 idx_mode = ARMII::IndexModePre; 2098 else if (!P && writeback) 2099 idx_mode = ARMII::IndexModePost; 2100 2101 if (writeback && (Rn == 15 || Rn == Rt)) 2102 S = MCDisassembler::SoftFail; // UNPREDICTABLE 2103 2104 if (reg) { 2105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2106 return MCDisassembler::Fail; 2107 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 2108 switch( fieldFromInstruction(Insn, 5, 2)) { 2109 case 0: 2110 Opc = ARM_AM::lsl; 2111 break; 2112 case 1: 2113 Opc = ARM_AM::lsr; 2114 break; 2115 case 2: 2116 Opc = ARM_AM::asr; 2117 break; 2118 case 3: 2119 Opc = ARM_AM::ror; 2120 break; 2121 default: 2122 return MCDisassembler::Fail; 2123 } 2124 unsigned amt = fieldFromInstruction(Insn, 7, 5); 2125 if (Opc == ARM_AM::ror && amt == 0) 2126 Opc = ARM_AM::rrx; 2127 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 2128 2129 Inst.addOperand(MCOperand::createImm(imm)); 2130 } else { 2131 Inst.addOperand(MCOperand::createReg(0)); 2132 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 2133 Inst.addOperand(MCOperand::createImm(tmp)); 2134 } 2135 2136 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2137 return MCDisassembler::Fail; 2138 2139 return S; 2140 } 2141 2142 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 2143 uint64_t Address, 2144 const MCDisassembler *Decoder) { 2145 DecodeStatus S = MCDisassembler::Success; 2146 2147 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2148 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2149 unsigned type = fieldFromInstruction(Val, 5, 2); 2150 unsigned imm = fieldFromInstruction(Val, 7, 5); 2151 unsigned U = fieldFromInstruction(Val, 12, 1); 2152 2153 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 2154 switch (type) { 2155 case 0: 2156 ShOp = ARM_AM::lsl; 2157 break; 2158 case 1: 2159 ShOp = ARM_AM::lsr; 2160 break; 2161 case 2: 2162 ShOp = ARM_AM::asr; 2163 break; 2164 case 3: 2165 ShOp = ARM_AM::ror; 2166 break; 2167 } 2168 2169 if (ShOp == ARM_AM::ror && imm == 0) 2170 ShOp = ARM_AM::rrx; 2171 2172 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2173 return MCDisassembler::Fail; 2174 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2175 return MCDisassembler::Fail; 2176 unsigned shift; 2177 if (U) 2178 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 2179 else 2180 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 2181 Inst.addOperand(MCOperand::createImm(shift)); 2182 2183 return S; 2184 } 2185 2186 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 2187 uint64_t Address, 2188 const MCDisassembler *Decoder) { 2189 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) 2190 return MCDisassembler::Fail; 2191 2192 // The "csync" operand is not encoded into the "tsb" instruction (as this is 2193 // the only available operand), but LLVM expects the instruction to have one 2194 // operand, so we need to add the csync when decoding. 2195 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC)); 2196 return MCDisassembler::Success; 2197 } 2198 2199 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 2200 uint64_t Address, 2201 const MCDisassembler *Decoder) { 2202 DecodeStatus S = MCDisassembler::Success; 2203 2204 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2205 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2206 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2207 unsigned type = fieldFromInstruction(Insn, 22, 1); 2208 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2209 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2210 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2211 unsigned W = fieldFromInstruction(Insn, 21, 1); 2212 unsigned P = fieldFromInstruction(Insn, 24, 1); 2213 unsigned Rt2 = Rt + 1; 2214 2215 bool writeback = (W == 1) | (P == 0); 2216 2217 // For {LD,ST}RD, Rt must be even, else undefined. 2218 switch (Inst.getOpcode()) { 2219 case ARM::STRD: 2220 case ARM::STRD_PRE: 2221 case ARM::STRD_POST: 2222 case ARM::LDRD: 2223 case ARM::LDRD_PRE: 2224 case ARM::LDRD_POST: 2225 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2226 break; 2227 default: 2228 break; 2229 } 2230 switch (Inst.getOpcode()) { 2231 case ARM::STRD: 2232 case ARM::STRD_PRE: 2233 case ARM::STRD_POST: 2234 if (P == 0 && W == 1) 2235 S = MCDisassembler::SoftFail; 2236 2237 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2238 S = MCDisassembler::SoftFail; 2239 if (type && Rm == 15) 2240 S = MCDisassembler::SoftFail; 2241 if (Rt2 == 15) 2242 S = MCDisassembler::SoftFail; 2243 if (!type && fieldFromInstruction(Insn, 8, 4)) 2244 S = MCDisassembler::SoftFail; 2245 break; 2246 case ARM::STRH: 2247 case ARM::STRH_PRE: 2248 case ARM::STRH_POST: 2249 if (Rt == 15) 2250 S = MCDisassembler::SoftFail; 2251 if (writeback && (Rn == 15 || Rn == Rt)) 2252 S = MCDisassembler::SoftFail; 2253 if (!type && Rm == 15) 2254 S = MCDisassembler::SoftFail; 2255 break; 2256 case ARM::LDRD: 2257 case ARM::LDRD_PRE: 2258 case ARM::LDRD_POST: 2259 if (type && Rn == 15) { 2260 if (Rt2 == 15) 2261 S = MCDisassembler::SoftFail; 2262 break; 2263 } 2264 if (P == 0 && W == 1) 2265 S = MCDisassembler::SoftFail; 2266 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2267 S = MCDisassembler::SoftFail; 2268 if (!type && writeback && Rn == 15) 2269 S = MCDisassembler::SoftFail; 2270 if (writeback && (Rn == Rt || Rn == Rt2)) 2271 S = MCDisassembler::SoftFail; 2272 break; 2273 case ARM::LDRH: 2274 case ARM::LDRH_PRE: 2275 case ARM::LDRH_POST: 2276 if (type && Rn == 15) { 2277 if (Rt == 15) 2278 S = MCDisassembler::SoftFail; 2279 break; 2280 } 2281 if (Rt == 15) 2282 S = MCDisassembler::SoftFail; 2283 if (!type && Rm == 15) 2284 S = MCDisassembler::SoftFail; 2285 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2286 S = MCDisassembler::SoftFail; 2287 break; 2288 case ARM::LDRSH: 2289 case ARM::LDRSH_PRE: 2290 case ARM::LDRSH_POST: 2291 case ARM::LDRSB: 2292 case ARM::LDRSB_PRE: 2293 case ARM::LDRSB_POST: 2294 if (type && Rn == 15) { 2295 if (Rt == 15) 2296 S = MCDisassembler::SoftFail; 2297 break; 2298 } 2299 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2300 S = MCDisassembler::SoftFail; 2301 if (!type && (Rt == 15 || Rm == 15)) 2302 S = MCDisassembler::SoftFail; 2303 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2304 S = MCDisassembler::SoftFail; 2305 break; 2306 default: 2307 break; 2308 } 2309 2310 if (writeback) { // Writeback 2311 if (P) 2312 U |= ARMII::IndexModePre << 9; 2313 else 2314 U |= ARMII::IndexModePost << 9; 2315 2316 // On stores, the writeback operand precedes Rt. 2317 switch (Inst.getOpcode()) { 2318 case ARM::STRD: 2319 case ARM::STRD_PRE: 2320 case ARM::STRD_POST: 2321 case ARM::STRH: 2322 case ARM::STRH_PRE: 2323 case ARM::STRH_POST: 2324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2325 return MCDisassembler::Fail; 2326 break; 2327 default: 2328 break; 2329 } 2330 } 2331 2332 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2333 return MCDisassembler::Fail; 2334 switch (Inst.getOpcode()) { 2335 case ARM::STRD: 2336 case ARM::STRD_PRE: 2337 case ARM::STRD_POST: 2338 case ARM::LDRD: 2339 case ARM::LDRD_PRE: 2340 case ARM::LDRD_POST: 2341 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2342 return MCDisassembler::Fail; 2343 break; 2344 default: 2345 break; 2346 } 2347 2348 if (writeback) { 2349 // On loads, the writeback operand comes after Rt. 2350 switch (Inst.getOpcode()) { 2351 case ARM::LDRD: 2352 case ARM::LDRD_PRE: 2353 case ARM::LDRD_POST: 2354 case ARM::LDRH: 2355 case ARM::LDRH_PRE: 2356 case ARM::LDRH_POST: 2357 case ARM::LDRSH: 2358 case ARM::LDRSH_PRE: 2359 case ARM::LDRSH_POST: 2360 case ARM::LDRSB: 2361 case ARM::LDRSB_PRE: 2362 case ARM::LDRSB_POST: 2363 case ARM::LDRHTr: 2364 case ARM::LDRSBTr: 2365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2366 return MCDisassembler::Fail; 2367 break; 2368 default: 2369 break; 2370 } 2371 } 2372 2373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2374 return MCDisassembler::Fail; 2375 2376 if (type) { 2377 Inst.addOperand(MCOperand::createReg(0)); 2378 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2379 } else { 2380 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2381 return MCDisassembler::Fail; 2382 Inst.addOperand(MCOperand::createImm(U)); 2383 } 2384 2385 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2386 return MCDisassembler::Fail; 2387 2388 return S; 2389 } 2390 2391 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2392 uint64_t Address, 2393 const MCDisassembler *Decoder) { 2394 DecodeStatus S = MCDisassembler::Success; 2395 2396 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2397 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2398 2399 switch (mode) { 2400 case 0: 2401 mode = ARM_AM::da; 2402 break; 2403 case 1: 2404 mode = ARM_AM::ia; 2405 break; 2406 case 2: 2407 mode = ARM_AM::db; 2408 break; 2409 case 3: 2410 mode = ARM_AM::ib; 2411 break; 2412 } 2413 2414 Inst.addOperand(MCOperand::createImm(mode)); 2415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2416 return MCDisassembler::Fail; 2417 2418 return S; 2419 } 2420 2421 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2422 uint64_t Address, 2423 const MCDisassembler *Decoder) { 2424 DecodeStatus S = MCDisassembler::Success; 2425 2426 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2427 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2428 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2429 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2430 2431 if (pred == 0xF) 2432 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2433 2434 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2435 return MCDisassembler::Fail; 2436 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2437 return MCDisassembler::Fail; 2438 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2439 return MCDisassembler::Fail; 2440 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2441 return MCDisassembler::Fail; 2442 return S; 2443 } 2444 2445 static DecodeStatus 2446 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 2447 uint64_t Address, 2448 const MCDisassembler *Decoder) { 2449 DecodeStatus S = MCDisassembler::Success; 2450 2451 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2452 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2453 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2454 2455 if (pred == 0xF) { 2456 // Ambiguous with RFE and SRS 2457 switch (Inst.getOpcode()) { 2458 case ARM::LDMDA: 2459 Inst.setOpcode(ARM::RFEDA); 2460 break; 2461 case ARM::LDMDA_UPD: 2462 Inst.setOpcode(ARM::RFEDA_UPD); 2463 break; 2464 case ARM::LDMDB: 2465 Inst.setOpcode(ARM::RFEDB); 2466 break; 2467 case ARM::LDMDB_UPD: 2468 Inst.setOpcode(ARM::RFEDB_UPD); 2469 break; 2470 case ARM::LDMIA: 2471 Inst.setOpcode(ARM::RFEIA); 2472 break; 2473 case ARM::LDMIA_UPD: 2474 Inst.setOpcode(ARM::RFEIA_UPD); 2475 break; 2476 case ARM::LDMIB: 2477 Inst.setOpcode(ARM::RFEIB); 2478 break; 2479 case ARM::LDMIB_UPD: 2480 Inst.setOpcode(ARM::RFEIB_UPD); 2481 break; 2482 case ARM::STMDA: 2483 Inst.setOpcode(ARM::SRSDA); 2484 break; 2485 case ARM::STMDA_UPD: 2486 Inst.setOpcode(ARM::SRSDA_UPD); 2487 break; 2488 case ARM::STMDB: 2489 Inst.setOpcode(ARM::SRSDB); 2490 break; 2491 case ARM::STMDB_UPD: 2492 Inst.setOpcode(ARM::SRSDB_UPD); 2493 break; 2494 case ARM::STMIA: 2495 Inst.setOpcode(ARM::SRSIA); 2496 break; 2497 case ARM::STMIA_UPD: 2498 Inst.setOpcode(ARM::SRSIA_UPD); 2499 break; 2500 case ARM::STMIB: 2501 Inst.setOpcode(ARM::SRSIB); 2502 break; 2503 case ARM::STMIB_UPD: 2504 Inst.setOpcode(ARM::SRSIB_UPD); 2505 break; 2506 default: 2507 return MCDisassembler::Fail; 2508 } 2509 2510 // For stores (which become SRS's, the only operand is the mode. 2511 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2512 // Check SRS encoding constraints 2513 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2514 fieldFromInstruction(Insn, 20, 1) == 0)) 2515 return MCDisassembler::Fail; 2516 2517 Inst.addOperand( 2518 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2519 return S; 2520 } 2521 2522 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2523 } 2524 2525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2526 return MCDisassembler::Fail; 2527 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2528 return MCDisassembler::Fail; // Tied 2529 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2530 return MCDisassembler::Fail; 2531 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 2534 return S; 2535 } 2536 2537 // Check for UNPREDICTABLE predicated ESB instruction 2538 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2539 uint64_t Address, 2540 const MCDisassembler *Decoder) { 2541 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2542 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2543 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2544 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2545 2546 DecodeStatus S = MCDisassembler::Success; 2547 2548 Inst.addOperand(MCOperand::createImm(imm8)); 2549 2550 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2551 return MCDisassembler::Fail; 2552 2553 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2554 // so all predicates should be allowed. 2555 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2556 S = MCDisassembler::SoftFail; 2557 2558 return S; 2559 } 2560 2561 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2562 uint64_t Address, 2563 const MCDisassembler *Decoder) { 2564 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2565 unsigned M = fieldFromInstruction(Insn, 17, 1); 2566 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2567 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2568 2569 DecodeStatus S = MCDisassembler::Success; 2570 2571 // This decoder is called from multiple location that do not check 2572 // the full encoding is valid before they do. 2573 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2574 fieldFromInstruction(Insn, 16, 1) != 0 || 2575 fieldFromInstruction(Insn, 20, 8) != 0x10) 2576 return MCDisassembler::Fail; 2577 2578 // imod == '01' --> UNPREDICTABLE 2579 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2580 // return failure here. The '01' imod value is unprintable, so there's 2581 // nothing useful we could do even if we returned UNPREDICTABLE. 2582 2583 if (imod == 1) return MCDisassembler::Fail; 2584 2585 if (imod && M) { 2586 Inst.setOpcode(ARM::CPS3p); 2587 Inst.addOperand(MCOperand::createImm(imod)); 2588 Inst.addOperand(MCOperand::createImm(iflags)); 2589 Inst.addOperand(MCOperand::createImm(mode)); 2590 } else if (imod && !M) { 2591 Inst.setOpcode(ARM::CPS2p); 2592 Inst.addOperand(MCOperand::createImm(imod)); 2593 Inst.addOperand(MCOperand::createImm(iflags)); 2594 if (mode) S = MCDisassembler::SoftFail; 2595 } else if (!imod && M) { 2596 Inst.setOpcode(ARM::CPS1p); 2597 Inst.addOperand(MCOperand::createImm(mode)); 2598 if (iflags) S = MCDisassembler::SoftFail; 2599 } else { 2600 // imod == '00' && M == '0' --> UNPREDICTABLE 2601 Inst.setOpcode(ARM::CPS1p); 2602 Inst.addOperand(MCOperand::createImm(mode)); 2603 S = MCDisassembler::SoftFail; 2604 } 2605 2606 return S; 2607 } 2608 2609 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2610 uint64_t Address, 2611 const MCDisassembler *Decoder) { 2612 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2613 unsigned M = fieldFromInstruction(Insn, 8, 1); 2614 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2615 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2616 2617 DecodeStatus S = MCDisassembler::Success; 2618 2619 // imod == '01' --> UNPREDICTABLE 2620 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2621 // return failure here. The '01' imod value is unprintable, so there's 2622 // nothing useful we could do even if we returned UNPREDICTABLE. 2623 2624 if (imod == 1) return MCDisassembler::Fail; 2625 2626 if (imod && M) { 2627 Inst.setOpcode(ARM::t2CPS3p); 2628 Inst.addOperand(MCOperand::createImm(imod)); 2629 Inst.addOperand(MCOperand::createImm(iflags)); 2630 Inst.addOperand(MCOperand::createImm(mode)); 2631 } else if (imod && !M) { 2632 Inst.setOpcode(ARM::t2CPS2p); 2633 Inst.addOperand(MCOperand::createImm(imod)); 2634 Inst.addOperand(MCOperand::createImm(iflags)); 2635 if (mode) S = MCDisassembler::SoftFail; 2636 } else if (!imod && M) { 2637 Inst.setOpcode(ARM::t2CPS1p); 2638 Inst.addOperand(MCOperand::createImm(mode)); 2639 if (iflags) S = MCDisassembler::SoftFail; 2640 } else { 2641 // imod == '00' && M == '0' --> this is a HINT instruction 2642 int imm = fieldFromInstruction(Insn, 0, 8); 2643 // HINT are defined only for immediate in [0..4] 2644 if(imm > 4) return MCDisassembler::Fail; 2645 Inst.setOpcode(ARM::t2HINT); 2646 Inst.addOperand(MCOperand::createImm(imm)); 2647 } 2648 2649 return S; 2650 } 2651 2652 static DecodeStatus 2653 DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2654 const MCDisassembler *Decoder) { 2655 unsigned imm = fieldFromInstruction(Insn, 0, 8); 2656 2657 unsigned Opcode = ARM::t2HINT; 2658 2659 if (imm == 0x0D) { 2660 Opcode = ARM::t2PACBTI; 2661 } else if (imm == 0x1D) { 2662 Opcode = ARM::t2PAC; 2663 } else if (imm == 0x2D) { 2664 Opcode = ARM::t2AUT; 2665 } else if (imm == 0x0F) { 2666 Opcode = ARM::t2BTI; 2667 } 2668 2669 Inst.setOpcode(Opcode); 2670 if (Opcode == ARM::t2HINT) { 2671 Inst.addOperand(MCOperand::createImm(imm)); 2672 } 2673 2674 return MCDisassembler::Success; 2675 } 2676 2677 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2678 uint64_t Address, 2679 const MCDisassembler *Decoder) { 2680 DecodeStatus S = MCDisassembler::Success; 2681 2682 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2683 unsigned imm = 0; 2684 2685 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2686 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2687 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2688 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2689 2690 if (Inst.getOpcode() == ARM::t2MOVTi16) 2691 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2692 return MCDisassembler::Fail; 2693 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2694 return MCDisassembler::Fail; 2695 2696 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2697 Inst.addOperand(MCOperand::createImm(imm)); 2698 2699 return S; 2700 } 2701 2702 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2703 uint64_t Address, 2704 const MCDisassembler *Decoder) { 2705 DecodeStatus S = MCDisassembler::Success; 2706 2707 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2708 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2709 unsigned imm = 0; 2710 2711 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2712 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2713 2714 if (Inst.getOpcode() == ARM::MOVTi16) 2715 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2716 return MCDisassembler::Fail; 2717 2718 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2719 return MCDisassembler::Fail; 2720 2721 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2722 Inst.addOperand(MCOperand::createImm(imm)); 2723 2724 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2725 return MCDisassembler::Fail; 2726 2727 return S; 2728 } 2729 2730 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2731 uint64_t Address, 2732 const MCDisassembler *Decoder) { 2733 DecodeStatus S = MCDisassembler::Success; 2734 2735 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2736 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2737 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2738 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2739 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2740 2741 if (pred == 0xF) 2742 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2743 2744 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2745 return MCDisassembler::Fail; 2746 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2747 return MCDisassembler::Fail; 2748 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2751 return MCDisassembler::Fail; 2752 2753 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2754 return MCDisassembler::Fail; 2755 2756 return S; 2757 } 2758 2759 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2760 uint64_t Address, 2761 const MCDisassembler *Decoder) { 2762 DecodeStatus S = MCDisassembler::Success; 2763 2764 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2765 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2766 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2767 2768 if (Pred == 0xF) 2769 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2770 2771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2772 return MCDisassembler::Fail; 2773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2774 return MCDisassembler::Fail; 2775 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2776 return MCDisassembler::Fail; 2777 2778 return S; 2779 } 2780 2781 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2782 uint64_t Address, 2783 const MCDisassembler *Decoder) { 2784 DecodeStatus S = MCDisassembler::Success; 2785 2786 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2787 2788 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2789 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2790 2791 if (!FeatureBits[ARM::HasV8_1aOps] || 2792 !FeatureBits[ARM::HasV8Ops]) 2793 return MCDisassembler::Fail; 2794 2795 // Decoder can be called from DecodeTST, which does not check the full 2796 // encoding is valid. 2797 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2798 fieldFromInstruction(Insn, 4,4) != 0) 2799 return MCDisassembler::Fail; 2800 if (fieldFromInstruction(Insn, 10,10) != 0 || 2801 fieldFromInstruction(Insn, 0,4) != 0) 2802 S = MCDisassembler::SoftFail; 2803 2804 Inst.setOpcode(ARM::SETPAN); 2805 Inst.addOperand(MCOperand::createImm(Imm)); 2806 2807 return S; 2808 } 2809 2810 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2811 uint64_t Address, 2812 const MCDisassembler *Decoder) { 2813 DecodeStatus S = MCDisassembler::Success; 2814 2815 unsigned add = fieldFromInstruction(Val, 12, 1); 2816 unsigned imm = fieldFromInstruction(Val, 0, 12); 2817 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2818 2819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2820 return MCDisassembler::Fail; 2821 2822 if (!add) imm *= -1; 2823 if (imm == 0 && !add) imm = INT32_MIN; 2824 Inst.addOperand(MCOperand::createImm(imm)); 2825 if (Rn == 15) 2826 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2827 2828 return S; 2829 } 2830 2831 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2832 uint64_t Address, 2833 const MCDisassembler *Decoder) { 2834 DecodeStatus S = MCDisassembler::Success; 2835 2836 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2837 // U == 1 to add imm, 0 to subtract it. 2838 unsigned U = fieldFromInstruction(Val, 8, 1); 2839 unsigned imm = fieldFromInstruction(Val, 0, 8); 2840 2841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2842 return MCDisassembler::Fail; 2843 2844 if (U) 2845 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2846 else 2847 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2848 2849 return S; 2850 } 2851 2852 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2853 uint64_t Address, 2854 const MCDisassembler *Decoder) { 2855 DecodeStatus S = MCDisassembler::Success; 2856 2857 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2858 // U == 1 to add imm, 0 to subtract it. 2859 unsigned U = fieldFromInstruction(Val, 8, 1); 2860 unsigned imm = fieldFromInstruction(Val, 0, 8); 2861 2862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2863 return MCDisassembler::Fail; 2864 2865 if (U) 2866 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2867 else 2868 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2869 2870 return S; 2871 } 2872 2873 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2874 uint64_t Address, 2875 const MCDisassembler *Decoder) { 2876 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2877 } 2878 2879 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2880 uint64_t Address, 2881 const MCDisassembler *Decoder) { 2882 DecodeStatus Status = MCDisassembler::Success; 2883 2884 // Note the J1 and J2 values are from the encoded instruction. So here 2885 // change them to I1 and I2 values via as documented: 2886 // I1 = NOT(J1 EOR S); 2887 // I2 = NOT(J2 EOR S); 2888 // and build the imm32 with one trailing zero as documented: 2889 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2890 unsigned S = fieldFromInstruction(Insn, 26, 1); 2891 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2892 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2893 unsigned I1 = !(J1 ^ S); 2894 unsigned I2 = !(J2 ^ S); 2895 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2896 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2897 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2898 int imm32 = SignExtend32<25>(tmp << 1); 2899 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2900 true, 4, Inst, Decoder)) 2901 Inst.addOperand(MCOperand::createImm(imm32)); 2902 2903 return Status; 2904 } 2905 2906 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2907 uint64_t Address, 2908 const MCDisassembler *Decoder) { 2909 DecodeStatus S = MCDisassembler::Success; 2910 2911 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2912 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2913 2914 if (pred == 0xF) { 2915 Inst.setOpcode(ARM::BLXi); 2916 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2917 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2918 true, 4, Inst, Decoder)) 2919 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2920 return S; 2921 } 2922 2923 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2924 true, 4, Inst, Decoder)) 2925 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2926 2927 // We already have BL_pred for BL w/ predicate, no need to add addition 2928 // predicate opreands for BL 2929 if (Inst.getOpcode() != ARM::BL) 2930 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2931 return MCDisassembler::Fail; 2932 2933 return S; 2934 } 2935 2936 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2937 uint64_t Address, 2938 const MCDisassembler *Decoder) { 2939 DecodeStatus S = MCDisassembler::Success; 2940 2941 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2942 unsigned align = fieldFromInstruction(Val, 4, 2); 2943 2944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2945 return MCDisassembler::Fail; 2946 if (!align) 2947 Inst.addOperand(MCOperand::createImm(0)); 2948 else 2949 Inst.addOperand(MCOperand::createImm(4 << align)); 2950 2951 return S; 2952 } 2953 2954 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2955 uint64_t Address, 2956 const MCDisassembler *Decoder) { 2957 DecodeStatus S = MCDisassembler::Success; 2958 2959 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2960 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2961 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2962 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2963 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2964 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2965 2966 // First output register 2967 switch (Inst.getOpcode()) { 2968 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2969 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2970 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2971 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2972 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2973 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2974 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2975 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2976 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2977 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2978 return MCDisassembler::Fail; 2979 break; 2980 case ARM::VLD2b16: 2981 case ARM::VLD2b32: 2982 case ARM::VLD2b8: 2983 case ARM::VLD2b16wb_fixed: 2984 case ARM::VLD2b16wb_register: 2985 case ARM::VLD2b32wb_fixed: 2986 case ARM::VLD2b32wb_register: 2987 case ARM::VLD2b8wb_fixed: 2988 case ARM::VLD2b8wb_register: 2989 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2990 return MCDisassembler::Fail; 2991 break; 2992 default: 2993 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2994 return MCDisassembler::Fail; 2995 } 2996 2997 // Second output register 2998 switch (Inst.getOpcode()) { 2999 case ARM::VLD3d8: 3000 case ARM::VLD3d16: 3001 case ARM::VLD3d32: 3002 case ARM::VLD3d8_UPD: 3003 case ARM::VLD3d16_UPD: 3004 case ARM::VLD3d32_UPD: 3005 case ARM::VLD4d8: 3006 case ARM::VLD4d16: 3007 case ARM::VLD4d32: 3008 case ARM::VLD4d8_UPD: 3009 case ARM::VLD4d16_UPD: 3010 case ARM::VLD4d32_UPD: 3011 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3012 return MCDisassembler::Fail; 3013 break; 3014 case ARM::VLD3q8: 3015 case ARM::VLD3q16: 3016 case ARM::VLD3q32: 3017 case ARM::VLD3q8_UPD: 3018 case ARM::VLD3q16_UPD: 3019 case ARM::VLD3q32_UPD: 3020 case ARM::VLD4q8: 3021 case ARM::VLD4q16: 3022 case ARM::VLD4q32: 3023 case ARM::VLD4q8_UPD: 3024 case ARM::VLD4q16_UPD: 3025 case ARM::VLD4q32_UPD: 3026 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3027 return MCDisassembler::Fail; 3028 break; 3029 default: 3030 break; 3031 } 3032 3033 // Third output register 3034 switch(Inst.getOpcode()) { 3035 case ARM::VLD3d8: 3036 case ARM::VLD3d16: 3037 case ARM::VLD3d32: 3038 case ARM::VLD3d8_UPD: 3039 case ARM::VLD3d16_UPD: 3040 case ARM::VLD3d32_UPD: 3041 case ARM::VLD4d8: 3042 case ARM::VLD4d16: 3043 case ARM::VLD4d32: 3044 case ARM::VLD4d8_UPD: 3045 case ARM::VLD4d16_UPD: 3046 case ARM::VLD4d32_UPD: 3047 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3048 return MCDisassembler::Fail; 3049 break; 3050 case ARM::VLD3q8: 3051 case ARM::VLD3q16: 3052 case ARM::VLD3q32: 3053 case ARM::VLD3q8_UPD: 3054 case ARM::VLD3q16_UPD: 3055 case ARM::VLD3q32_UPD: 3056 case ARM::VLD4q8: 3057 case ARM::VLD4q16: 3058 case ARM::VLD4q32: 3059 case ARM::VLD4q8_UPD: 3060 case ARM::VLD4q16_UPD: 3061 case ARM::VLD4q32_UPD: 3062 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3063 return MCDisassembler::Fail; 3064 break; 3065 default: 3066 break; 3067 } 3068 3069 // Fourth output register 3070 switch (Inst.getOpcode()) { 3071 case ARM::VLD4d8: 3072 case ARM::VLD4d16: 3073 case ARM::VLD4d32: 3074 case ARM::VLD4d8_UPD: 3075 case ARM::VLD4d16_UPD: 3076 case ARM::VLD4d32_UPD: 3077 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3078 return MCDisassembler::Fail; 3079 break; 3080 case ARM::VLD4q8: 3081 case ARM::VLD4q16: 3082 case ARM::VLD4q32: 3083 case ARM::VLD4q8_UPD: 3084 case ARM::VLD4q16_UPD: 3085 case ARM::VLD4q32_UPD: 3086 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3087 return MCDisassembler::Fail; 3088 break; 3089 default: 3090 break; 3091 } 3092 3093 // Writeback operand 3094 switch (Inst.getOpcode()) { 3095 case ARM::VLD1d8wb_fixed: 3096 case ARM::VLD1d16wb_fixed: 3097 case ARM::VLD1d32wb_fixed: 3098 case ARM::VLD1d64wb_fixed: 3099 case ARM::VLD1d8wb_register: 3100 case ARM::VLD1d16wb_register: 3101 case ARM::VLD1d32wb_register: 3102 case ARM::VLD1d64wb_register: 3103 case ARM::VLD1q8wb_fixed: 3104 case ARM::VLD1q16wb_fixed: 3105 case ARM::VLD1q32wb_fixed: 3106 case ARM::VLD1q64wb_fixed: 3107 case ARM::VLD1q8wb_register: 3108 case ARM::VLD1q16wb_register: 3109 case ARM::VLD1q32wb_register: 3110 case ARM::VLD1q64wb_register: 3111 case ARM::VLD1d8Twb_fixed: 3112 case ARM::VLD1d8Twb_register: 3113 case ARM::VLD1d16Twb_fixed: 3114 case ARM::VLD1d16Twb_register: 3115 case ARM::VLD1d32Twb_fixed: 3116 case ARM::VLD1d32Twb_register: 3117 case ARM::VLD1d64Twb_fixed: 3118 case ARM::VLD1d64Twb_register: 3119 case ARM::VLD1d8Qwb_fixed: 3120 case ARM::VLD1d8Qwb_register: 3121 case ARM::VLD1d16Qwb_fixed: 3122 case ARM::VLD1d16Qwb_register: 3123 case ARM::VLD1d32Qwb_fixed: 3124 case ARM::VLD1d32Qwb_register: 3125 case ARM::VLD1d64Qwb_fixed: 3126 case ARM::VLD1d64Qwb_register: 3127 case ARM::VLD2d8wb_fixed: 3128 case ARM::VLD2d16wb_fixed: 3129 case ARM::VLD2d32wb_fixed: 3130 case ARM::VLD2q8wb_fixed: 3131 case ARM::VLD2q16wb_fixed: 3132 case ARM::VLD2q32wb_fixed: 3133 case ARM::VLD2d8wb_register: 3134 case ARM::VLD2d16wb_register: 3135 case ARM::VLD2d32wb_register: 3136 case ARM::VLD2q8wb_register: 3137 case ARM::VLD2q16wb_register: 3138 case ARM::VLD2q32wb_register: 3139 case ARM::VLD2b8wb_fixed: 3140 case ARM::VLD2b16wb_fixed: 3141 case ARM::VLD2b32wb_fixed: 3142 case ARM::VLD2b8wb_register: 3143 case ARM::VLD2b16wb_register: 3144 case ARM::VLD2b32wb_register: 3145 Inst.addOperand(MCOperand::createImm(0)); 3146 break; 3147 case ARM::VLD3d8_UPD: 3148 case ARM::VLD3d16_UPD: 3149 case ARM::VLD3d32_UPD: 3150 case ARM::VLD3q8_UPD: 3151 case ARM::VLD3q16_UPD: 3152 case ARM::VLD3q32_UPD: 3153 case ARM::VLD4d8_UPD: 3154 case ARM::VLD4d16_UPD: 3155 case ARM::VLD4d32_UPD: 3156 case ARM::VLD4q8_UPD: 3157 case ARM::VLD4q16_UPD: 3158 case ARM::VLD4q32_UPD: 3159 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3160 return MCDisassembler::Fail; 3161 break; 3162 default: 3163 break; 3164 } 3165 3166 // AddrMode6 Base (register+alignment) 3167 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3168 return MCDisassembler::Fail; 3169 3170 // AddrMode6 Offset (register) 3171 switch (Inst.getOpcode()) { 3172 default: 3173 // The below have been updated to have explicit am6offset split 3174 // between fixed and register offset. For those instructions not 3175 // yet updated, we need to add an additional reg0 operand for the 3176 // fixed variant. 3177 // 3178 // The fixed offset encodes as Rm == 0xd, so we check for that. 3179 if (Rm == 0xd) { 3180 Inst.addOperand(MCOperand::createReg(0)); 3181 break; 3182 } 3183 // Fall through to handle the register offset variant. 3184 [[fallthrough]]; 3185 case ARM::VLD1d8wb_fixed: 3186 case ARM::VLD1d16wb_fixed: 3187 case ARM::VLD1d32wb_fixed: 3188 case ARM::VLD1d64wb_fixed: 3189 case ARM::VLD1d8Twb_fixed: 3190 case ARM::VLD1d16Twb_fixed: 3191 case ARM::VLD1d32Twb_fixed: 3192 case ARM::VLD1d64Twb_fixed: 3193 case ARM::VLD1d8Qwb_fixed: 3194 case ARM::VLD1d16Qwb_fixed: 3195 case ARM::VLD1d32Qwb_fixed: 3196 case ARM::VLD1d64Qwb_fixed: 3197 case ARM::VLD1d8wb_register: 3198 case ARM::VLD1d16wb_register: 3199 case ARM::VLD1d32wb_register: 3200 case ARM::VLD1d64wb_register: 3201 case ARM::VLD1q8wb_fixed: 3202 case ARM::VLD1q16wb_fixed: 3203 case ARM::VLD1q32wb_fixed: 3204 case ARM::VLD1q64wb_fixed: 3205 case ARM::VLD1q8wb_register: 3206 case ARM::VLD1q16wb_register: 3207 case ARM::VLD1q32wb_register: 3208 case ARM::VLD1q64wb_register: 3209 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3210 // variant encodes Rm == 0xf. Anything else is a register offset post- 3211 // increment and we need to add the register operand to the instruction. 3212 if (Rm != 0xD && Rm != 0xF && 3213 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3214 return MCDisassembler::Fail; 3215 break; 3216 case ARM::VLD2d8wb_fixed: 3217 case ARM::VLD2d16wb_fixed: 3218 case ARM::VLD2d32wb_fixed: 3219 case ARM::VLD2b8wb_fixed: 3220 case ARM::VLD2b16wb_fixed: 3221 case ARM::VLD2b32wb_fixed: 3222 case ARM::VLD2q8wb_fixed: 3223 case ARM::VLD2q16wb_fixed: 3224 case ARM::VLD2q32wb_fixed: 3225 break; 3226 } 3227 3228 return S; 3229 } 3230 3231 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 3232 uint64_t Address, 3233 const MCDisassembler *Decoder) { 3234 unsigned type = fieldFromInstruction(Insn, 8, 4); 3235 unsigned align = fieldFromInstruction(Insn, 4, 2); 3236 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 3237 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 3238 if (type == 10 && align == 3) return MCDisassembler::Fail; 3239 3240 unsigned load = fieldFromInstruction(Insn, 21, 1); 3241 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3242 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3243 } 3244 3245 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 3246 uint64_t Address, 3247 const MCDisassembler *Decoder) { 3248 unsigned size = fieldFromInstruction(Insn, 6, 2); 3249 if (size == 3) return MCDisassembler::Fail; 3250 3251 unsigned type = fieldFromInstruction(Insn, 8, 4); 3252 unsigned align = fieldFromInstruction(Insn, 4, 2); 3253 if (type == 8 && align == 3) return MCDisassembler::Fail; 3254 if (type == 9 && align == 3) return MCDisassembler::Fail; 3255 3256 unsigned load = fieldFromInstruction(Insn, 21, 1); 3257 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3258 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3259 } 3260 3261 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3262 uint64_t Address, 3263 const MCDisassembler *Decoder) { 3264 unsigned size = fieldFromInstruction(Insn, 6, 2); 3265 if (size == 3) return MCDisassembler::Fail; 3266 3267 unsigned align = fieldFromInstruction(Insn, 4, 2); 3268 if (align & 2) return MCDisassembler::Fail; 3269 3270 unsigned load = fieldFromInstruction(Insn, 21, 1); 3271 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3272 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3273 } 3274 3275 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3276 uint64_t Address, 3277 const MCDisassembler *Decoder) { 3278 unsigned size = fieldFromInstruction(Insn, 6, 2); 3279 if (size == 3) return MCDisassembler::Fail; 3280 3281 unsigned load = fieldFromInstruction(Insn, 21, 1); 3282 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3283 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3284 } 3285 3286 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3287 uint64_t Address, 3288 const MCDisassembler *Decoder) { 3289 DecodeStatus S = MCDisassembler::Success; 3290 3291 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3292 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3293 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3294 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3295 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3296 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3297 3298 // Writeback Operand 3299 switch (Inst.getOpcode()) { 3300 case ARM::VST1d8wb_fixed: 3301 case ARM::VST1d16wb_fixed: 3302 case ARM::VST1d32wb_fixed: 3303 case ARM::VST1d64wb_fixed: 3304 case ARM::VST1d8wb_register: 3305 case ARM::VST1d16wb_register: 3306 case ARM::VST1d32wb_register: 3307 case ARM::VST1d64wb_register: 3308 case ARM::VST1q8wb_fixed: 3309 case ARM::VST1q16wb_fixed: 3310 case ARM::VST1q32wb_fixed: 3311 case ARM::VST1q64wb_fixed: 3312 case ARM::VST1q8wb_register: 3313 case ARM::VST1q16wb_register: 3314 case ARM::VST1q32wb_register: 3315 case ARM::VST1q64wb_register: 3316 case ARM::VST1d8Twb_fixed: 3317 case ARM::VST1d16Twb_fixed: 3318 case ARM::VST1d32Twb_fixed: 3319 case ARM::VST1d64Twb_fixed: 3320 case ARM::VST1d8Twb_register: 3321 case ARM::VST1d16Twb_register: 3322 case ARM::VST1d32Twb_register: 3323 case ARM::VST1d64Twb_register: 3324 case ARM::VST1d8Qwb_fixed: 3325 case ARM::VST1d16Qwb_fixed: 3326 case ARM::VST1d32Qwb_fixed: 3327 case ARM::VST1d64Qwb_fixed: 3328 case ARM::VST1d8Qwb_register: 3329 case ARM::VST1d16Qwb_register: 3330 case ARM::VST1d32Qwb_register: 3331 case ARM::VST1d64Qwb_register: 3332 case ARM::VST2d8wb_fixed: 3333 case ARM::VST2d16wb_fixed: 3334 case ARM::VST2d32wb_fixed: 3335 case ARM::VST2d8wb_register: 3336 case ARM::VST2d16wb_register: 3337 case ARM::VST2d32wb_register: 3338 case ARM::VST2q8wb_fixed: 3339 case ARM::VST2q16wb_fixed: 3340 case ARM::VST2q32wb_fixed: 3341 case ARM::VST2q8wb_register: 3342 case ARM::VST2q16wb_register: 3343 case ARM::VST2q32wb_register: 3344 case ARM::VST2b8wb_fixed: 3345 case ARM::VST2b16wb_fixed: 3346 case ARM::VST2b32wb_fixed: 3347 case ARM::VST2b8wb_register: 3348 case ARM::VST2b16wb_register: 3349 case ARM::VST2b32wb_register: 3350 if (Rm == 0xF) 3351 return MCDisassembler::Fail; 3352 Inst.addOperand(MCOperand::createImm(0)); 3353 break; 3354 case ARM::VST3d8_UPD: 3355 case ARM::VST3d16_UPD: 3356 case ARM::VST3d32_UPD: 3357 case ARM::VST3q8_UPD: 3358 case ARM::VST3q16_UPD: 3359 case ARM::VST3q32_UPD: 3360 case ARM::VST4d8_UPD: 3361 case ARM::VST4d16_UPD: 3362 case ARM::VST4d32_UPD: 3363 case ARM::VST4q8_UPD: 3364 case ARM::VST4q16_UPD: 3365 case ARM::VST4q32_UPD: 3366 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3367 return MCDisassembler::Fail; 3368 break; 3369 default: 3370 break; 3371 } 3372 3373 // AddrMode6 Base (register+alignment) 3374 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3375 return MCDisassembler::Fail; 3376 3377 // AddrMode6 Offset (register) 3378 switch (Inst.getOpcode()) { 3379 default: 3380 if (Rm == 0xD) 3381 Inst.addOperand(MCOperand::createReg(0)); 3382 else if (Rm != 0xF) { 3383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3384 return MCDisassembler::Fail; 3385 } 3386 break; 3387 case ARM::VST1d8wb_fixed: 3388 case ARM::VST1d16wb_fixed: 3389 case ARM::VST1d32wb_fixed: 3390 case ARM::VST1d64wb_fixed: 3391 case ARM::VST1q8wb_fixed: 3392 case ARM::VST1q16wb_fixed: 3393 case ARM::VST1q32wb_fixed: 3394 case ARM::VST1q64wb_fixed: 3395 case ARM::VST1d8Twb_fixed: 3396 case ARM::VST1d16Twb_fixed: 3397 case ARM::VST1d32Twb_fixed: 3398 case ARM::VST1d64Twb_fixed: 3399 case ARM::VST1d8Qwb_fixed: 3400 case ARM::VST1d16Qwb_fixed: 3401 case ARM::VST1d32Qwb_fixed: 3402 case ARM::VST1d64Qwb_fixed: 3403 case ARM::VST2d8wb_fixed: 3404 case ARM::VST2d16wb_fixed: 3405 case ARM::VST2d32wb_fixed: 3406 case ARM::VST2q8wb_fixed: 3407 case ARM::VST2q16wb_fixed: 3408 case ARM::VST2q32wb_fixed: 3409 case ARM::VST2b8wb_fixed: 3410 case ARM::VST2b16wb_fixed: 3411 case ARM::VST2b32wb_fixed: 3412 break; 3413 } 3414 3415 // First input register 3416 switch (Inst.getOpcode()) { 3417 case ARM::VST1q16: 3418 case ARM::VST1q32: 3419 case ARM::VST1q64: 3420 case ARM::VST1q8: 3421 case ARM::VST1q16wb_fixed: 3422 case ARM::VST1q16wb_register: 3423 case ARM::VST1q32wb_fixed: 3424 case ARM::VST1q32wb_register: 3425 case ARM::VST1q64wb_fixed: 3426 case ARM::VST1q64wb_register: 3427 case ARM::VST1q8wb_fixed: 3428 case ARM::VST1q8wb_register: 3429 case ARM::VST2d16: 3430 case ARM::VST2d32: 3431 case ARM::VST2d8: 3432 case ARM::VST2d16wb_fixed: 3433 case ARM::VST2d16wb_register: 3434 case ARM::VST2d32wb_fixed: 3435 case ARM::VST2d32wb_register: 3436 case ARM::VST2d8wb_fixed: 3437 case ARM::VST2d8wb_register: 3438 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3439 return MCDisassembler::Fail; 3440 break; 3441 case ARM::VST2b16: 3442 case ARM::VST2b32: 3443 case ARM::VST2b8: 3444 case ARM::VST2b16wb_fixed: 3445 case ARM::VST2b16wb_register: 3446 case ARM::VST2b32wb_fixed: 3447 case ARM::VST2b32wb_register: 3448 case ARM::VST2b8wb_fixed: 3449 case ARM::VST2b8wb_register: 3450 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3451 return MCDisassembler::Fail; 3452 break; 3453 default: 3454 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3455 return MCDisassembler::Fail; 3456 } 3457 3458 // Second input register 3459 switch (Inst.getOpcode()) { 3460 case ARM::VST3d8: 3461 case ARM::VST3d16: 3462 case ARM::VST3d32: 3463 case ARM::VST3d8_UPD: 3464 case ARM::VST3d16_UPD: 3465 case ARM::VST3d32_UPD: 3466 case ARM::VST4d8: 3467 case ARM::VST4d16: 3468 case ARM::VST4d32: 3469 case ARM::VST4d8_UPD: 3470 case ARM::VST4d16_UPD: 3471 case ARM::VST4d32_UPD: 3472 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3473 return MCDisassembler::Fail; 3474 break; 3475 case ARM::VST3q8: 3476 case ARM::VST3q16: 3477 case ARM::VST3q32: 3478 case ARM::VST3q8_UPD: 3479 case ARM::VST3q16_UPD: 3480 case ARM::VST3q32_UPD: 3481 case ARM::VST4q8: 3482 case ARM::VST4q16: 3483 case ARM::VST4q32: 3484 case ARM::VST4q8_UPD: 3485 case ARM::VST4q16_UPD: 3486 case ARM::VST4q32_UPD: 3487 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3488 return MCDisassembler::Fail; 3489 break; 3490 default: 3491 break; 3492 } 3493 3494 // Third input register 3495 switch (Inst.getOpcode()) { 3496 case ARM::VST3d8: 3497 case ARM::VST3d16: 3498 case ARM::VST3d32: 3499 case ARM::VST3d8_UPD: 3500 case ARM::VST3d16_UPD: 3501 case ARM::VST3d32_UPD: 3502 case ARM::VST4d8: 3503 case ARM::VST4d16: 3504 case ARM::VST4d32: 3505 case ARM::VST4d8_UPD: 3506 case ARM::VST4d16_UPD: 3507 case ARM::VST4d32_UPD: 3508 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3509 return MCDisassembler::Fail; 3510 break; 3511 case ARM::VST3q8: 3512 case ARM::VST3q16: 3513 case ARM::VST3q32: 3514 case ARM::VST3q8_UPD: 3515 case ARM::VST3q16_UPD: 3516 case ARM::VST3q32_UPD: 3517 case ARM::VST4q8: 3518 case ARM::VST4q16: 3519 case ARM::VST4q32: 3520 case ARM::VST4q8_UPD: 3521 case ARM::VST4q16_UPD: 3522 case ARM::VST4q32_UPD: 3523 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3524 return MCDisassembler::Fail; 3525 break; 3526 default: 3527 break; 3528 } 3529 3530 // Fourth input register 3531 switch (Inst.getOpcode()) { 3532 case ARM::VST4d8: 3533 case ARM::VST4d16: 3534 case ARM::VST4d32: 3535 case ARM::VST4d8_UPD: 3536 case ARM::VST4d16_UPD: 3537 case ARM::VST4d32_UPD: 3538 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3539 return MCDisassembler::Fail; 3540 break; 3541 case ARM::VST4q8: 3542 case ARM::VST4q16: 3543 case ARM::VST4q32: 3544 case ARM::VST4q8_UPD: 3545 case ARM::VST4q16_UPD: 3546 case ARM::VST4q32_UPD: 3547 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3548 return MCDisassembler::Fail; 3549 break; 3550 default: 3551 break; 3552 } 3553 3554 return S; 3555 } 3556 3557 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3558 uint64_t Address, 3559 const MCDisassembler *Decoder) { 3560 DecodeStatus S = MCDisassembler::Success; 3561 3562 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3563 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3564 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3565 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3566 unsigned align = fieldFromInstruction(Insn, 4, 1); 3567 unsigned size = fieldFromInstruction(Insn, 6, 2); 3568 3569 if (size == 0 && align == 1) 3570 return MCDisassembler::Fail; 3571 align *= (1 << size); 3572 3573 switch (Inst.getOpcode()) { 3574 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3575 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3576 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3577 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3578 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3579 return MCDisassembler::Fail; 3580 break; 3581 default: 3582 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3583 return MCDisassembler::Fail; 3584 break; 3585 } 3586 if (Rm != 0xF) { 3587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3588 return MCDisassembler::Fail; 3589 } 3590 3591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3592 return MCDisassembler::Fail; 3593 Inst.addOperand(MCOperand::createImm(align)); 3594 3595 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3596 // variant encodes Rm == 0xf. Anything else is a register offset post- 3597 // increment and we need to add the register operand to the instruction. 3598 if (Rm != 0xD && Rm != 0xF && 3599 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3600 return MCDisassembler::Fail; 3601 3602 return S; 3603 } 3604 3605 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3606 uint64_t Address, 3607 const MCDisassembler *Decoder) { 3608 DecodeStatus S = MCDisassembler::Success; 3609 3610 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3611 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3612 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3613 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3614 unsigned align = fieldFromInstruction(Insn, 4, 1); 3615 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3616 align *= 2*size; 3617 3618 switch (Inst.getOpcode()) { 3619 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3620 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3621 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3622 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3623 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3624 return MCDisassembler::Fail; 3625 break; 3626 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3627 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3628 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3629 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3630 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3631 return MCDisassembler::Fail; 3632 break; 3633 default: 3634 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 break; 3637 } 3638 3639 if (Rm != 0xF) 3640 Inst.addOperand(MCOperand::createImm(0)); 3641 3642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3643 return MCDisassembler::Fail; 3644 Inst.addOperand(MCOperand::createImm(align)); 3645 3646 if (Rm != 0xD && Rm != 0xF) { 3647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3648 return MCDisassembler::Fail; 3649 } 3650 3651 return S; 3652 } 3653 3654 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3655 uint64_t Address, 3656 const MCDisassembler *Decoder) { 3657 DecodeStatus S = MCDisassembler::Success; 3658 3659 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3660 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3661 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3662 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3663 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3664 3665 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3666 return MCDisassembler::Fail; 3667 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3668 return MCDisassembler::Fail; 3669 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3670 return MCDisassembler::Fail; 3671 if (Rm != 0xF) { 3672 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3673 return MCDisassembler::Fail; 3674 } 3675 3676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3677 return MCDisassembler::Fail; 3678 Inst.addOperand(MCOperand::createImm(0)); 3679 3680 if (Rm == 0xD) 3681 Inst.addOperand(MCOperand::createReg(0)); 3682 else if (Rm != 0xF) { 3683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3684 return MCDisassembler::Fail; 3685 } 3686 3687 return S; 3688 } 3689 3690 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3691 uint64_t Address, 3692 const MCDisassembler *Decoder) { 3693 DecodeStatus S = MCDisassembler::Success; 3694 3695 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3696 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3697 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3698 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3699 unsigned size = fieldFromInstruction(Insn, 6, 2); 3700 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3701 unsigned align = fieldFromInstruction(Insn, 4, 1); 3702 3703 if (size == 0x3) { 3704 if (align == 0) 3705 return MCDisassembler::Fail; 3706 align = 16; 3707 } else { 3708 if (size == 2) { 3709 align *= 8; 3710 } else { 3711 size = 1 << size; 3712 align *= 4*size; 3713 } 3714 } 3715 3716 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3717 return MCDisassembler::Fail; 3718 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3719 return MCDisassembler::Fail; 3720 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3721 return MCDisassembler::Fail; 3722 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3723 return MCDisassembler::Fail; 3724 if (Rm != 0xF) { 3725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3726 return MCDisassembler::Fail; 3727 } 3728 3729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3730 return MCDisassembler::Fail; 3731 Inst.addOperand(MCOperand::createImm(align)); 3732 3733 if (Rm == 0xD) 3734 Inst.addOperand(MCOperand::createReg(0)); 3735 else if (Rm != 0xF) { 3736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3737 return MCDisassembler::Fail; 3738 } 3739 3740 return S; 3741 } 3742 3743 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3744 uint64_t Address, 3745 const MCDisassembler *Decoder) { 3746 DecodeStatus S = MCDisassembler::Success; 3747 3748 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3749 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3750 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3751 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3752 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3753 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3754 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3755 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3756 3757 if (Q) { 3758 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3759 return MCDisassembler::Fail; 3760 } else { 3761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3762 return MCDisassembler::Fail; 3763 } 3764 3765 Inst.addOperand(MCOperand::createImm(imm)); 3766 3767 switch (Inst.getOpcode()) { 3768 case ARM::VORRiv4i16: 3769 case ARM::VORRiv2i32: 3770 case ARM::VBICiv4i16: 3771 case ARM::VBICiv2i32: 3772 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3773 return MCDisassembler::Fail; 3774 break; 3775 case ARM::VORRiv8i16: 3776 case ARM::VORRiv4i32: 3777 case ARM::VBICiv8i16: 3778 case ARM::VBICiv4i32: 3779 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3780 return MCDisassembler::Fail; 3781 break; 3782 default: 3783 break; 3784 } 3785 3786 return S; 3787 } 3788 3789 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3790 uint64_t Address, 3791 const MCDisassembler *Decoder) { 3792 DecodeStatus S = MCDisassembler::Success; 3793 3794 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3795 fieldFromInstruction(Insn, 13, 3)); 3796 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3797 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3798 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3799 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3800 imm |= cmode << 8; 3801 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3802 3803 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3804 return MCDisassembler::Fail; 3805 3806 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3807 return MCDisassembler::Fail; 3808 3809 Inst.addOperand(MCOperand::createImm(imm)); 3810 3811 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3812 Inst.addOperand(MCOperand::createReg(0)); 3813 Inst.addOperand(MCOperand::createImm(0)); 3814 3815 return S; 3816 } 3817 3818 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3819 uint64_t Address, 3820 const MCDisassembler *Decoder) { 3821 DecodeStatus S = MCDisassembler::Success; 3822 3823 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3824 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3825 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3826 return MCDisassembler::Fail; 3827 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3828 3829 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3830 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3831 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3832 return MCDisassembler::Fail; 3833 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3834 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3835 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3836 return MCDisassembler::Fail; 3837 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3838 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3839 Inst.addOperand(MCOperand::createImm(Qd)); 3840 3841 return S; 3842 } 3843 3844 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3845 uint64_t Address, 3846 const MCDisassembler *Decoder) { 3847 DecodeStatus S = MCDisassembler::Success; 3848 3849 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3850 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3851 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3852 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3853 unsigned size = fieldFromInstruction(Insn, 18, 2); 3854 3855 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3856 return MCDisassembler::Fail; 3857 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3858 return MCDisassembler::Fail; 3859 Inst.addOperand(MCOperand::createImm(8 << size)); 3860 3861 return S; 3862 } 3863 3864 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3865 uint64_t Address, 3866 const MCDisassembler *Decoder) { 3867 Inst.addOperand(MCOperand::createImm(8 - Val)); 3868 return MCDisassembler::Success; 3869 } 3870 3871 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3872 uint64_t Address, 3873 const MCDisassembler *Decoder) { 3874 Inst.addOperand(MCOperand::createImm(16 - Val)); 3875 return MCDisassembler::Success; 3876 } 3877 3878 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3879 uint64_t Address, 3880 const MCDisassembler *Decoder) { 3881 Inst.addOperand(MCOperand::createImm(32 - Val)); 3882 return MCDisassembler::Success; 3883 } 3884 3885 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3886 uint64_t Address, 3887 const MCDisassembler *Decoder) { 3888 Inst.addOperand(MCOperand::createImm(64 - Val)); 3889 return MCDisassembler::Success; 3890 } 3891 3892 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3893 uint64_t Address, 3894 const MCDisassembler *Decoder) { 3895 DecodeStatus S = MCDisassembler::Success; 3896 3897 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3898 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3899 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3900 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3901 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3902 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3903 unsigned op = fieldFromInstruction(Insn, 6, 1); 3904 3905 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3906 return MCDisassembler::Fail; 3907 if (op) { 3908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3909 return MCDisassembler::Fail; // Writeback 3910 } 3911 3912 switch (Inst.getOpcode()) { 3913 case ARM::VTBL2: 3914 case ARM::VTBX2: 3915 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3916 return MCDisassembler::Fail; 3917 break; 3918 default: 3919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3920 return MCDisassembler::Fail; 3921 } 3922 3923 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3924 return MCDisassembler::Fail; 3925 3926 return S; 3927 } 3928 3929 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3930 uint64_t Address, 3931 const MCDisassembler *Decoder) { 3932 DecodeStatus S = MCDisassembler::Success; 3933 3934 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3935 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3936 3937 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3938 return MCDisassembler::Fail; 3939 3940 switch(Inst.getOpcode()) { 3941 default: 3942 return MCDisassembler::Fail; 3943 case ARM::tADR: 3944 break; // tADR does not explicitly represent the PC as an operand. 3945 case ARM::tADDrSPi: 3946 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3947 break; 3948 } 3949 3950 Inst.addOperand(MCOperand::createImm(imm)); 3951 return S; 3952 } 3953 3954 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3955 uint64_t Address, 3956 const MCDisassembler *Decoder) { 3957 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3958 true, 2, Inst, Decoder)) 3959 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3960 return MCDisassembler::Success; 3961 } 3962 3963 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3964 uint64_t Address, 3965 const MCDisassembler *Decoder) { 3966 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3967 true, 4, Inst, Decoder)) 3968 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3969 return MCDisassembler::Success; 3970 } 3971 3972 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3973 uint64_t Address, 3974 const MCDisassembler *Decoder) { 3975 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3976 true, 2, Inst, Decoder)) 3977 Inst.addOperand(MCOperand::createImm(Val << 1)); 3978 return MCDisassembler::Success; 3979 } 3980 3981 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3982 uint64_t Address, 3983 const MCDisassembler *Decoder) { 3984 DecodeStatus S = MCDisassembler::Success; 3985 3986 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3987 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3988 3989 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3990 return MCDisassembler::Fail; 3991 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3992 return MCDisassembler::Fail; 3993 3994 return S; 3995 } 3996 3997 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3998 uint64_t Address, 3999 const MCDisassembler *Decoder) { 4000 DecodeStatus S = MCDisassembler::Success; 4001 4002 unsigned Rn = fieldFromInstruction(Val, 0, 3); 4003 unsigned imm = fieldFromInstruction(Val, 3, 5); 4004 4005 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4006 return MCDisassembler::Fail; 4007 Inst.addOperand(MCOperand::createImm(imm)); 4008 4009 return S; 4010 } 4011 4012 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 4013 uint64_t Address, 4014 const MCDisassembler *Decoder) { 4015 unsigned imm = Val << 2; 4016 4017 Inst.addOperand(MCOperand::createImm(imm)); 4018 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 4019 4020 return MCDisassembler::Success; 4021 } 4022 4023 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 4024 uint64_t Address, 4025 const MCDisassembler *Decoder) { 4026 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4027 Inst.addOperand(MCOperand::createImm(Val)); 4028 4029 return MCDisassembler::Success; 4030 } 4031 4032 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 4033 uint64_t Address, 4034 const MCDisassembler *Decoder) { 4035 DecodeStatus S = MCDisassembler::Success; 4036 4037 unsigned Rn = fieldFromInstruction(Val, 6, 4); 4038 unsigned Rm = fieldFromInstruction(Val, 2, 4); 4039 unsigned imm = fieldFromInstruction(Val, 0, 2); 4040 4041 // Thumb stores cannot use PC as dest register. 4042 switch (Inst.getOpcode()) { 4043 case ARM::t2STRHs: 4044 case ARM::t2STRBs: 4045 case ARM::t2STRs: 4046 if (Rn == 15) 4047 return MCDisassembler::Fail; 4048 break; 4049 default: 4050 break; 4051 } 4052 4053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4054 return MCDisassembler::Fail; 4055 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4056 return MCDisassembler::Fail; 4057 Inst.addOperand(MCOperand::createImm(imm)); 4058 4059 return S; 4060 } 4061 4062 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 4063 uint64_t Address, 4064 const MCDisassembler *Decoder) { 4065 DecodeStatus S = MCDisassembler::Success; 4066 4067 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4068 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4069 4070 const FeatureBitset &featureBits = 4071 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4072 4073 bool hasMP = featureBits[ARM::FeatureMP]; 4074 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4075 4076 if (Rn == 15) { 4077 switch (Inst.getOpcode()) { 4078 case ARM::t2LDRBs: 4079 Inst.setOpcode(ARM::t2LDRBpci); 4080 break; 4081 case ARM::t2LDRHs: 4082 Inst.setOpcode(ARM::t2LDRHpci); 4083 break; 4084 case ARM::t2LDRSHs: 4085 Inst.setOpcode(ARM::t2LDRSHpci); 4086 break; 4087 case ARM::t2LDRSBs: 4088 Inst.setOpcode(ARM::t2LDRSBpci); 4089 break; 4090 case ARM::t2LDRs: 4091 Inst.setOpcode(ARM::t2LDRpci); 4092 break; 4093 case ARM::t2PLDs: 4094 Inst.setOpcode(ARM::t2PLDpci); 4095 break; 4096 case ARM::t2PLIs: 4097 Inst.setOpcode(ARM::t2PLIpci); 4098 break; 4099 default: 4100 return MCDisassembler::Fail; 4101 } 4102 4103 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4104 } 4105 4106 if (Rt == 15) { 4107 switch (Inst.getOpcode()) { 4108 case ARM::t2LDRSHs: 4109 return MCDisassembler::Fail; 4110 case ARM::t2LDRHs: 4111 Inst.setOpcode(ARM::t2PLDWs); 4112 break; 4113 case ARM::t2LDRSBs: 4114 Inst.setOpcode(ARM::t2PLIs); 4115 break; 4116 default: 4117 break; 4118 } 4119 } 4120 4121 switch (Inst.getOpcode()) { 4122 case ARM::t2PLDs: 4123 break; 4124 case ARM::t2PLIs: 4125 if (!hasV7Ops) 4126 return MCDisassembler::Fail; 4127 break; 4128 case ARM::t2PLDWs: 4129 if (!hasV7Ops || !hasMP) 4130 return MCDisassembler::Fail; 4131 break; 4132 default: 4133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4134 return MCDisassembler::Fail; 4135 } 4136 4137 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 4138 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 4139 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 4140 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 4141 return MCDisassembler::Fail; 4142 4143 return S; 4144 } 4145 4146 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 4147 uint64_t Address, 4148 const MCDisassembler *Decoder) { 4149 DecodeStatus S = MCDisassembler::Success; 4150 4151 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4152 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4153 unsigned U = fieldFromInstruction(Insn, 9, 1); 4154 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4155 imm |= (U << 8); 4156 imm |= (Rn << 9); 4157 unsigned add = fieldFromInstruction(Insn, 9, 1); 4158 4159 const FeatureBitset &featureBits = 4160 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4161 4162 bool hasMP = featureBits[ARM::FeatureMP]; 4163 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4164 4165 if (Rn == 15) { 4166 switch (Inst.getOpcode()) { 4167 case ARM::t2LDRi8: 4168 Inst.setOpcode(ARM::t2LDRpci); 4169 break; 4170 case ARM::t2LDRBi8: 4171 Inst.setOpcode(ARM::t2LDRBpci); 4172 break; 4173 case ARM::t2LDRSBi8: 4174 Inst.setOpcode(ARM::t2LDRSBpci); 4175 break; 4176 case ARM::t2LDRHi8: 4177 Inst.setOpcode(ARM::t2LDRHpci); 4178 break; 4179 case ARM::t2LDRSHi8: 4180 Inst.setOpcode(ARM::t2LDRSHpci); 4181 break; 4182 case ARM::t2PLDi8: 4183 Inst.setOpcode(ARM::t2PLDpci); 4184 break; 4185 case ARM::t2PLIi8: 4186 Inst.setOpcode(ARM::t2PLIpci); 4187 break; 4188 default: 4189 return MCDisassembler::Fail; 4190 } 4191 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4192 } 4193 4194 if (Rt == 15) { 4195 switch (Inst.getOpcode()) { 4196 case ARM::t2LDRSHi8: 4197 return MCDisassembler::Fail; 4198 case ARM::t2LDRHi8: 4199 if (!add) 4200 Inst.setOpcode(ARM::t2PLDWi8); 4201 break; 4202 case ARM::t2LDRSBi8: 4203 Inst.setOpcode(ARM::t2PLIi8); 4204 break; 4205 default: 4206 break; 4207 } 4208 } 4209 4210 switch (Inst.getOpcode()) { 4211 case ARM::t2PLDi8: 4212 break; 4213 case ARM::t2PLIi8: 4214 if (!hasV7Ops) 4215 return MCDisassembler::Fail; 4216 break; 4217 case ARM::t2PLDWi8: 4218 if (!hasV7Ops || !hasMP) 4219 return MCDisassembler::Fail; 4220 break; 4221 default: 4222 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4223 return MCDisassembler::Fail; 4224 } 4225 4226 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4227 return MCDisassembler::Fail; 4228 return S; 4229 } 4230 4231 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 4232 uint64_t Address, 4233 const MCDisassembler *Decoder) { 4234 DecodeStatus S = MCDisassembler::Success; 4235 4236 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4237 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4238 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4239 imm |= (Rn << 13); 4240 4241 const FeatureBitset &featureBits = 4242 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4243 4244 bool hasMP = featureBits[ARM::FeatureMP]; 4245 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4246 4247 if (Rn == 15) { 4248 switch (Inst.getOpcode()) { 4249 case ARM::t2LDRi12: 4250 Inst.setOpcode(ARM::t2LDRpci); 4251 break; 4252 case ARM::t2LDRHi12: 4253 Inst.setOpcode(ARM::t2LDRHpci); 4254 break; 4255 case ARM::t2LDRSHi12: 4256 Inst.setOpcode(ARM::t2LDRSHpci); 4257 break; 4258 case ARM::t2LDRBi12: 4259 Inst.setOpcode(ARM::t2LDRBpci); 4260 break; 4261 case ARM::t2LDRSBi12: 4262 Inst.setOpcode(ARM::t2LDRSBpci); 4263 break; 4264 case ARM::t2PLDi12: 4265 Inst.setOpcode(ARM::t2PLDpci); 4266 break; 4267 case ARM::t2PLIi12: 4268 Inst.setOpcode(ARM::t2PLIpci); 4269 break; 4270 default: 4271 return MCDisassembler::Fail; 4272 } 4273 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4274 } 4275 4276 if (Rt == 15) { 4277 switch (Inst.getOpcode()) { 4278 case ARM::t2LDRSHi12: 4279 return MCDisassembler::Fail; 4280 case ARM::t2LDRHi12: 4281 Inst.setOpcode(ARM::t2PLDWi12); 4282 break; 4283 case ARM::t2LDRSBi12: 4284 Inst.setOpcode(ARM::t2PLIi12); 4285 break; 4286 default: 4287 break; 4288 } 4289 } 4290 4291 switch (Inst.getOpcode()) { 4292 case ARM::t2PLDi12: 4293 break; 4294 case ARM::t2PLIi12: 4295 if (!hasV7Ops) 4296 return MCDisassembler::Fail; 4297 break; 4298 case ARM::t2PLDWi12: 4299 if (!hasV7Ops || !hasMP) 4300 return MCDisassembler::Fail; 4301 break; 4302 default: 4303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 } 4306 4307 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4308 return MCDisassembler::Fail; 4309 return S; 4310 } 4311 4312 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 4313 const MCDisassembler *Decoder) { 4314 DecodeStatus S = MCDisassembler::Success; 4315 4316 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4317 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4318 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4319 imm |= (Rn << 9); 4320 4321 if (Rn == 15) { 4322 switch (Inst.getOpcode()) { 4323 case ARM::t2LDRT: 4324 Inst.setOpcode(ARM::t2LDRpci); 4325 break; 4326 case ARM::t2LDRBT: 4327 Inst.setOpcode(ARM::t2LDRBpci); 4328 break; 4329 case ARM::t2LDRHT: 4330 Inst.setOpcode(ARM::t2LDRHpci); 4331 break; 4332 case ARM::t2LDRSBT: 4333 Inst.setOpcode(ARM::t2LDRSBpci); 4334 break; 4335 case ARM::t2LDRSHT: 4336 Inst.setOpcode(ARM::t2LDRSHpci); 4337 break; 4338 default: 4339 return MCDisassembler::Fail; 4340 } 4341 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4342 } 4343 4344 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4345 return MCDisassembler::Fail; 4346 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4347 return MCDisassembler::Fail; 4348 return S; 4349 } 4350 4351 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4352 uint64_t Address, 4353 const MCDisassembler *Decoder) { 4354 DecodeStatus S = MCDisassembler::Success; 4355 4356 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4357 unsigned U = fieldFromInstruction(Insn, 23, 1); 4358 int imm = fieldFromInstruction(Insn, 0, 12); 4359 4360 const FeatureBitset &featureBits = 4361 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4362 4363 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4364 4365 if (Rt == 15) { 4366 switch (Inst.getOpcode()) { 4367 case ARM::t2LDRBpci: 4368 case ARM::t2LDRHpci: 4369 Inst.setOpcode(ARM::t2PLDpci); 4370 break; 4371 case ARM::t2LDRSBpci: 4372 Inst.setOpcode(ARM::t2PLIpci); 4373 break; 4374 case ARM::t2LDRSHpci: 4375 return MCDisassembler::Fail; 4376 default: 4377 break; 4378 } 4379 } 4380 4381 switch(Inst.getOpcode()) { 4382 case ARM::t2PLDpci: 4383 break; 4384 case ARM::t2PLIpci: 4385 if (!hasV7Ops) 4386 return MCDisassembler::Fail; 4387 break; 4388 default: 4389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4390 return MCDisassembler::Fail; 4391 } 4392 4393 if (!U) { 4394 // Special case for #-0. 4395 if (imm == 0) 4396 imm = INT32_MIN; 4397 else 4398 imm = -imm; 4399 } 4400 Inst.addOperand(MCOperand::createImm(imm)); 4401 4402 return S; 4403 } 4404 4405 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 4406 const MCDisassembler *Decoder) { 4407 if (Val == 0) 4408 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4409 else { 4410 int imm = Val & 0xFF; 4411 4412 if (!(Val & 0x100)) imm *= -1; 4413 Inst.addOperand(MCOperand::createImm(imm * 4)); 4414 } 4415 4416 return MCDisassembler::Success; 4417 } 4418 4419 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4420 const MCDisassembler *Decoder) { 4421 if (Val == 0) 4422 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4423 else { 4424 int imm = Val & 0x7F; 4425 4426 if (!(Val & 0x80)) 4427 imm *= -1; 4428 Inst.addOperand(MCOperand::createImm(imm * 4)); 4429 } 4430 4431 return MCDisassembler::Success; 4432 } 4433 4434 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4435 uint64_t Address, 4436 const MCDisassembler *Decoder) { 4437 DecodeStatus S = MCDisassembler::Success; 4438 4439 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4440 unsigned imm = fieldFromInstruction(Val, 0, 9); 4441 4442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4443 return MCDisassembler::Fail; 4444 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4445 return MCDisassembler::Fail; 4446 4447 return S; 4448 } 4449 4450 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4451 uint64_t Address, 4452 const MCDisassembler *Decoder) { 4453 DecodeStatus S = MCDisassembler::Success; 4454 4455 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4456 unsigned imm = fieldFromInstruction(Val, 0, 8); 4457 4458 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4459 return MCDisassembler::Fail; 4460 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4461 return MCDisassembler::Fail; 4462 4463 return S; 4464 } 4465 4466 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 4467 uint64_t Address, 4468 const MCDisassembler *Decoder) { 4469 DecodeStatus S = MCDisassembler::Success; 4470 4471 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4472 unsigned imm = fieldFromInstruction(Val, 0, 8); 4473 4474 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4475 return MCDisassembler::Fail; 4476 4477 Inst.addOperand(MCOperand::createImm(imm)); 4478 4479 return S; 4480 } 4481 4482 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 4483 const MCDisassembler *Decoder) { 4484 int imm = Val & 0xFF; 4485 if (Val == 0) 4486 imm = INT32_MIN; 4487 else if (!(Val & 0x100)) 4488 imm *= -1; 4489 Inst.addOperand(MCOperand::createImm(imm)); 4490 4491 return MCDisassembler::Success; 4492 } 4493 4494 template <int shift> 4495 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 4496 const MCDisassembler *Decoder) { 4497 int imm = Val & 0x7F; 4498 if (Val == 0) 4499 imm = INT32_MIN; 4500 else if (!(Val & 0x80)) 4501 imm *= -1; 4502 if (imm != INT32_MIN) 4503 imm *= (1U << shift); 4504 Inst.addOperand(MCOperand::createImm(imm)); 4505 4506 return MCDisassembler::Success; 4507 } 4508 4509 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4510 uint64_t Address, 4511 const MCDisassembler *Decoder) { 4512 DecodeStatus S = MCDisassembler::Success; 4513 4514 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4515 unsigned imm = fieldFromInstruction(Val, 0, 9); 4516 4517 // Thumb stores cannot use PC as dest register. 4518 switch (Inst.getOpcode()) { 4519 case ARM::t2STRT: 4520 case ARM::t2STRBT: 4521 case ARM::t2STRHT: 4522 case ARM::t2STRi8: 4523 case ARM::t2STRHi8: 4524 case ARM::t2STRBi8: 4525 if (Rn == 15) 4526 return MCDisassembler::Fail; 4527 break; 4528 default: 4529 break; 4530 } 4531 4532 // Some instructions always use an additive offset. 4533 switch (Inst.getOpcode()) { 4534 case ARM::t2LDRT: 4535 case ARM::t2LDRBT: 4536 case ARM::t2LDRHT: 4537 case ARM::t2LDRSBT: 4538 case ARM::t2LDRSHT: 4539 case ARM::t2STRT: 4540 case ARM::t2STRBT: 4541 case ARM::t2STRHT: 4542 imm |= 0x100; 4543 break; 4544 default: 4545 break; 4546 } 4547 4548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4549 return MCDisassembler::Fail; 4550 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4551 return MCDisassembler::Fail; 4552 4553 return S; 4554 } 4555 4556 template <int shift> 4557 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4558 uint64_t Address, 4559 const MCDisassembler *Decoder) { 4560 DecodeStatus S = MCDisassembler::Success; 4561 4562 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4563 unsigned imm = fieldFromInstruction(Val, 0, 8); 4564 4565 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4566 return MCDisassembler::Fail; 4567 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4568 return MCDisassembler::Fail; 4569 4570 return S; 4571 } 4572 4573 template <int shift, int WriteBack> 4574 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4575 uint64_t Address, 4576 const MCDisassembler *Decoder) { 4577 DecodeStatus S = MCDisassembler::Success; 4578 4579 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4580 unsigned imm = fieldFromInstruction(Val, 0, 8); 4581 if (WriteBack) { 4582 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4583 return MCDisassembler::Fail; 4584 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4585 return MCDisassembler::Fail; 4586 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4587 return MCDisassembler::Fail; 4588 4589 return S; 4590 } 4591 4592 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4593 uint64_t Address, 4594 const MCDisassembler *Decoder) { 4595 DecodeStatus S = MCDisassembler::Success; 4596 4597 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4598 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4599 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4600 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4601 addr |= Rn << 9; 4602 unsigned load = fieldFromInstruction(Insn, 20, 1); 4603 4604 if (Rn == 15) { 4605 switch (Inst.getOpcode()) { 4606 case ARM::t2LDR_PRE: 4607 case ARM::t2LDR_POST: 4608 Inst.setOpcode(ARM::t2LDRpci); 4609 break; 4610 case ARM::t2LDRB_PRE: 4611 case ARM::t2LDRB_POST: 4612 Inst.setOpcode(ARM::t2LDRBpci); 4613 break; 4614 case ARM::t2LDRH_PRE: 4615 case ARM::t2LDRH_POST: 4616 Inst.setOpcode(ARM::t2LDRHpci); 4617 break; 4618 case ARM::t2LDRSB_PRE: 4619 case ARM::t2LDRSB_POST: 4620 if (Rt == 15) 4621 Inst.setOpcode(ARM::t2PLIpci); 4622 else 4623 Inst.setOpcode(ARM::t2LDRSBpci); 4624 break; 4625 case ARM::t2LDRSH_PRE: 4626 case ARM::t2LDRSH_POST: 4627 Inst.setOpcode(ARM::t2LDRSHpci); 4628 break; 4629 default: 4630 return MCDisassembler::Fail; 4631 } 4632 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4633 } 4634 4635 if (!load) { 4636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4637 return MCDisassembler::Fail; 4638 } 4639 4640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4641 return MCDisassembler::Fail; 4642 4643 if (load) { 4644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4645 return MCDisassembler::Fail; 4646 } 4647 4648 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4649 return MCDisassembler::Fail; 4650 4651 return S; 4652 } 4653 4654 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4655 uint64_t Address, 4656 const MCDisassembler *Decoder) { 4657 DecodeStatus S = MCDisassembler::Success; 4658 4659 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4660 unsigned imm = fieldFromInstruction(Val, 0, 12); 4661 4662 // Thumb stores cannot use PC as dest register. 4663 switch (Inst.getOpcode()) { 4664 case ARM::t2STRi12: 4665 case ARM::t2STRBi12: 4666 case ARM::t2STRHi12: 4667 if (Rn == 15) 4668 return MCDisassembler::Fail; 4669 break; 4670 default: 4671 break; 4672 } 4673 4674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4675 return MCDisassembler::Fail; 4676 Inst.addOperand(MCOperand::createImm(imm)); 4677 4678 return S; 4679 } 4680 4681 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4682 uint64_t Address, 4683 const MCDisassembler *Decoder) { 4684 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4685 4686 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4687 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4688 Inst.addOperand(MCOperand::createImm(imm)); 4689 4690 return MCDisassembler::Success; 4691 } 4692 4693 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4694 uint64_t Address, 4695 const MCDisassembler *Decoder) { 4696 DecodeStatus S = MCDisassembler::Success; 4697 4698 if (Inst.getOpcode() == ARM::tADDrSP) { 4699 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4700 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4701 4702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4703 return MCDisassembler::Fail; 4704 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4706 return MCDisassembler::Fail; 4707 } else if (Inst.getOpcode() == ARM::tADDspr) { 4708 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4709 4710 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4711 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4713 return MCDisassembler::Fail; 4714 } 4715 4716 return S; 4717 } 4718 4719 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4720 uint64_t Address, 4721 const MCDisassembler *Decoder) { 4722 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4723 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4724 4725 Inst.addOperand(MCOperand::createImm(imod)); 4726 Inst.addOperand(MCOperand::createImm(flags)); 4727 4728 return MCDisassembler::Success; 4729 } 4730 4731 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4732 uint64_t Address, 4733 const MCDisassembler *Decoder) { 4734 DecodeStatus S = MCDisassembler::Success; 4735 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4736 unsigned add = fieldFromInstruction(Insn, 4, 1); 4737 4738 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4739 return MCDisassembler::Fail; 4740 Inst.addOperand(MCOperand::createImm(add)); 4741 4742 return S; 4743 } 4744 4745 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4746 uint64_t Address, 4747 const MCDisassembler *Decoder) { 4748 DecodeStatus S = MCDisassembler::Success; 4749 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4750 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4751 4752 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4753 return MCDisassembler::Fail; 4754 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4755 return MCDisassembler::Fail; 4756 4757 return S; 4758 } 4759 4760 template <int shift> 4761 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4762 uint64_t Address, 4763 const MCDisassembler *Decoder) { 4764 DecodeStatus S = MCDisassembler::Success; 4765 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4766 int imm = fieldFromInstruction(Insn, 0, 7); 4767 4768 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4769 return MCDisassembler::Fail; 4770 4771 if(!fieldFromInstruction(Insn, 7, 1)) { 4772 if (imm == 0) 4773 imm = INT32_MIN; // indicate -0 4774 else 4775 imm *= -1; 4776 } 4777 if (imm != INT32_MIN) 4778 imm *= (1U << shift); 4779 Inst.addOperand(MCOperand::createImm(imm)); 4780 4781 return S; 4782 } 4783 4784 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4785 uint64_t Address, 4786 const MCDisassembler *Decoder) { 4787 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4788 // Note only one trailing zero not two. Also the J1 and J2 values are from 4789 // the encoded instruction. So here change to I1 and I2 values via: 4790 // I1 = NOT(J1 EOR S); 4791 // I2 = NOT(J2 EOR S); 4792 // and build the imm32 with two trailing zeros as documented: 4793 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4794 unsigned S = (Val >> 23) & 1; 4795 unsigned J1 = (Val >> 22) & 1; 4796 unsigned J2 = (Val >> 21) & 1; 4797 unsigned I1 = !(J1 ^ S); 4798 unsigned I2 = !(J2 ^ S); 4799 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4800 int imm32 = SignExtend32<25>(tmp << 1); 4801 4802 if (!tryAddingSymbolicOperand(Address, 4803 (Address & ~2u) + imm32 + 4, 4804 true, 4, Inst, Decoder)) 4805 Inst.addOperand(MCOperand::createImm(imm32)); 4806 return MCDisassembler::Success; 4807 } 4808 4809 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4810 uint64_t Address, 4811 const MCDisassembler *Decoder) { 4812 if (Val == 0xA || Val == 0xB) 4813 return MCDisassembler::Fail; 4814 4815 const FeatureBitset &featureBits = 4816 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4817 4818 if (!isValidCoprocessorNumber(Val, featureBits)) 4819 return MCDisassembler::Fail; 4820 4821 Inst.addOperand(MCOperand::createImm(Val)); 4822 return MCDisassembler::Success; 4823 } 4824 4825 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4826 uint64_t Address, 4827 const MCDisassembler *Decoder) { 4828 const FeatureBitset &FeatureBits = 4829 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4830 DecodeStatus S = MCDisassembler::Success; 4831 4832 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4833 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4834 4835 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4837 return MCDisassembler::Fail; 4838 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4839 return MCDisassembler::Fail; 4840 return S; 4841 } 4842 4843 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4844 uint64_t Address, 4845 const MCDisassembler *Decoder) { 4846 DecodeStatus S = MCDisassembler::Success; 4847 4848 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4849 if (pred == 0xE || pred == 0xF) { 4850 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4851 switch (opc) { 4852 default: 4853 return MCDisassembler::Fail; 4854 case 0xf3bf8f4: 4855 Inst.setOpcode(ARM::t2DSB); 4856 break; 4857 case 0xf3bf8f5: 4858 Inst.setOpcode(ARM::t2DMB); 4859 break; 4860 case 0xf3bf8f6: 4861 Inst.setOpcode(ARM::t2ISB); 4862 break; 4863 } 4864 4865 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4866 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4867 } 4868 4869 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4870 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4871 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4872 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4873 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4874 4875 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4876 return MCDisassembler::Fail; 4877 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4878 return MCDisassembler::Fail; 4879 4880 return S; 4881 } 4882 4883 // Decode a shifted immediate operand. These basically consist 4884 // of an 8-bit value, and a 4-bit directive that specifies either 4885 // a splat operation or a rotation. 4886 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 4887 const MCDisassembler *Decoder) { 4888 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4889 if (ctrl == 0) { 4890 unsigned byte = fieldFromInstruction(Val, 8, 2); 4891 unsigned imm = fieldFromInstruction(Val, 0, 8); 4892 switch (byte) { 4893 case 0: 4894 Inst.addOperand(MCOperand::createImm(imm)); 4895 break; 4896 case 1: 4897 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4898 break; 4899 case 2: 4900 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4901 break; 4902 case 3: 4903 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4904 (imm << 8) | imm)); 4905 break; 4906 } 4907 } else { 4908 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4909 unsigned rot = fieldFromInstruction(Val, 7, 5); 4910 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4911 Inst.addOperand(MCOperand::createImm(imm)); 4912 } 4913 4914 return MCDisassembler::Success; 4915 } 4916 4917 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4918 uint64_t Address, 4919 const MCDisassembler *Decoder) { 4920 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4921 true, 2, Inst, Decoder)) 4922 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4923 return MCDisassembler::Success; 4924 } 4925 4926 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4927 uint64_t Address, 4928 const MCDisassembler *Decoder) { 4929 // Val is passed in as S:J1:J2:imm10:imm11 4930 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4931 // the encoded instruction. So here change to I1 and I2 values via: 4932 // I1 = NOT(J1 EOR S); 4933 // I2 = NOT(J2 EOR S); 4934 // and build the imm32 with one trailing zero as documented: 4935 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4936 unsigned S = (Val >> 23) & 1; 4937 unsigned J1 = (Val >> 22) & 1; 4938 unsigned J2 = (Val >> 21) & 1; 4939 unsigned I1 = !(J1 ^ S); 4940 unsigned I2 = !(J2 ^ S); 4941 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4942 int imm32 = SignExtend32<25>(tmp << 1); 4943 4944 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4945 true, 4, Inst, Decoder)) 4946 Inst.addOperand(MCOperand::createImm(imm32)); 4947 return MCDisassembler::Success; 4948 } 4949 4950 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4951 uint64_t Address, 4952 const MCDisassembler *Decoder) { 4953 if (Val & ~0xf) 4954 return MCDisassembler::Fail; 4955 4956 Inst.addOperand(MCOperand::createImm(Val)); 4957 return MCDisassembler::Success; 4958 } 4959 4960 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4961 uint64_t Address, 4962 const MCDisassembler *Decoder) { 4963 if (Val & ~0xf) 4964 return MCDisassembler::Fail; 4965 4966 Inst.addOperand(MCOperand::createImm(Val)); 4967 return MCDisassembler::Success; 4968 } 4969 4970 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, 4971 const MCDisassembler *Decoder) { 4972 DecodeStatus S = MCDisassembler::Success; 4973 const FeatureBitset &FeatureBits = 4974 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4975 4976 if (FeatureBits[ARM::FeatureMClass]) { 4977 unsigned ValLow = Val & 0xff; 4978 4979 // Validate the SYSm value first. 4980 switch (ValLow) { 4981 case 0: // apsr 4982 case 1: // iapsr 4983 case 2: // eapsr 4984 case 3: // xpsr 4985 case 5: // ipsr 4986 case 6: // epsr 4987 case 7: // iepsr 4988 case 8: // msp 4989 case 9: // psp 4990 case 16: // primask 4991 case 20: // control 4992 break; 4993 case 17: // basepri 4994 case 18: // basepri_max 4995 case 19: // faultmask 4996 if (!(FeatureBits[ARM::HasV7Ops])) 4997 // Values basepri, basepri_max and faultmask are only valid for v7m. 4998 return MCDisassembler::Fail; 4999 break; 5000 case 0x8a: // msplim_ns 5001 case 0x8b: // psplim_ns 5002 case 0x91: // basepri_ns 5003 case 0x93: // faultmask_ns 5004 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 5005 return MCDisassembler::Fail; 5006 [[fallthrough]]; 5007 case 10: // msplim 5008 case 11: // psplim 5009 case 0x88: // msp_ns 5010 case 0x89: // psp_ns 5011 case 0x90: // primask_ns 5012 case 0x94: // control_ns 5013 case 0x98: // sp_ns 5014 if (!(FeatureBits[ARM::Feature8MSecExt])) 5015 return MCDisassembler::Fail; 5016 break; 5017 case 0x20: // pac_key_p_0 5018 case 0x21: // pac_key_p_1 5019 case 0x22: // pac_key_p_2 5020 case 0x23: // pac_key_p_3 5021 case 0x24: // pac_key_u_0 5022 case 0x25: // pac_key_u_1 5023 case 0x26: // pac_key_u_2 5024 case 0x27: // pac_key_u_3 5025 case 0xa0: // pac_key_p_0_ns 5026 case 0xa1: // pac_key_p_1_ns 5027 case 0xa2: // pac_key_p_2_ns 5028 case 0xa3: // pac_key_p_3_ns 5029 case 0xa4: // pac_key_u_0_ns 5030 case 0xa5: // pac_key_u_1_ns 5031 case 0xa6: // pac_key_u_2_ns 5032 case 0xa7: // pac_key_u_3_ns 5033 if (!(FeatureBits[ARM::FeaturePACBTI])) 5034 return MCDisassembler::Fail; 5035 break; 5036 default: 5037 // Architecturally defined as unpredictable 5038 S = MCDisassembler::SoftFail; 5039 break; 5040 } 5041 5042 if (Inst.getOpcode() == ARM::t2MSR_M) { 5043 unsigned Mask = fieldFromInstruction(Val, 10, 2); 5044 if (!(FeatureBits[ARM::HasV7Ops])) { 5045 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 5046 // unpredictable. 5047 if (Mask != 2) 5048 S = MCDisassembler::SoftFail; 5049 } 5050 else { 5051 // The ARMv7-M architecture stores an additional 2-bit mask value in 5052 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 5053 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 5054 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 5055 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 5056 // only if the processor includes the DSP extension. 5057 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 5058 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 5059 S = MCDisassembler::SoftFail; 5060 } 5061 } 5062 } else { 5063 // A/R class 5064 if (Val == 0) 5065 return MCDisassembler::Fail; 5066 } 5067 Inst.addOperand(MCOperand::createImm(Val)); 5068 return S; 5069 } 5070 5071 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 5072 uint64_t Address, 5073 const MCDisassembler *Decoder) { 5074 unsigned R = fieldFromInstruction(Val, 5, 1); 5075 unsigned SysM = fieldFromInstruction(Val, 0, 5); 5076 5077 // The table of encodings for these banked registers comes from B9.2.3 of the 5078 // ARM ARM. There are patterns, but nothing regular enough to make this logic 5079 // neater. So by fiat, these values are UNPREDICTABLE: 5080 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 5081 return MCDisassembler::Fail; 5082 5083 Inst.addOperand(MCOperand::createImm(Val)); 5084 return MCDisassembler::Success; 5085 } 5086 5087 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 5088 uint64_t Address, 5089 const MCDisassembler *Decoder) { 5090 DecodeStatus S = MCDisassembler::Success; 5091 5092 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5093 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5094 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5095 5096 if (Rn == 0xF) 5097 S = MCDisassembler::SoftFail; 5098 5099 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5100 return MCDisassembler::Fail; 5101 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5102 return MCDisassembler::Fail; 5103 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5104 return MCDisassembler::Fail; 5105 5106 return S; 5107 } 5108 5109 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 5110 uint64_t Address, 5111 const MCDisassembler *Decoder) { 5112 DecodeStatus S = MCDisassembler::Success; 5113 5114 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5115 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 5116 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5117 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5118 5119 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 5120 return MCDisassembler::Fail; 5121 5122 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 5123 S = MCDisassembler::SoftFail; 5124 5125 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5126 return MCDisassembler::Fail; 5127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5128 return MCDisassembler::Fail; 5129 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5130 return MCDisassembler::Fail; 5131 5132 return S; 5133 } 5134 5135 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 5136 uint64_t Address, 5137 const MCDisassembler *Decoder) { 5138 DecodeStatus S = MCDisassembler::Success; 5139 5140 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5141 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5142 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5143 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5144 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5145 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5146 5147 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5148 5149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5150 return MCDisassembler::Fail; 5151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5152 return MCDisassembler::Fail; 5153 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5154 return MCDisassembler::Fail; 5155 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5156 return MCDisassembler::Fail; 5157 5158 return S; 5159 } 5160 5161 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 5162 uint64_t Address, 5163 const MCDisassembler *Decoder) { 5164 DecodeStatus S = MCDisassembler::Success; 5165 5166 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5167 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5168 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5169 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5170 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5171 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5172 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5173 5174 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5175 if (Rm == 0xF) S = MCDisassembler::SoftFail; 5176 5177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5178 return MCDisassembler::Fail; 5179 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5180 return MCDisassembler::Fail; 5181 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5182 return MCDisassembler::Fail; 5183 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5184 return MCDisassembler::Fail; 5185 5186 return S; 5187 } 5188 5189 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 5190 uint64_t Address, 5191 const MCDisassembler *Decoder) { 5192 DecodeStatus S = MCDisassembler::Success; 5193 5194 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5195 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5196 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5197 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5198 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5199 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5200 5201 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5202 5203 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5204 return MCDisassembler::Fail; 5205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5206 return MCDisassembler::Fail; 5207 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5208 return MCDisassembler::Fail; 5209 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5210 return MCDisassembler::Fail; 5211 5212 return S; 5213 } 5214 5215 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 5216 uint64_t Address, 5217 const MCDisassembler *Decoder) { 5218 DecodeStatus S = MCDisassembler::Success; 5219 5220 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5221 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5222 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5223 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5224 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5225 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5226 5227 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5228 5229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5230 return MCDisassembler::Fail; 5231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5232 return MCDisassembler::Fail; 5233 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5234 return MCDisassembler::Fail; 5235 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5236 return MCDisassembler::Fail; 5237 5238 return S; 5239 } 5240 5241 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5242 const MCDisassembler *Decoder) { 5243 DecodeStatus S = MCDisassembler::Success; 5244 5245 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5246 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5247 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5248 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5249 unsigned size = fieldFromInstruction(Insn, 10, 2); 5250 5251 unsigned align = 0; 5252 unsigned index = 0; 5253 switch (size) { 5254 default: 5255 return MCDisassembler::Fail; 5256 case 0: 5257 if (fieldFromInstruction(Insn, 4, 1)) 5258 return MCDisassembler::Fail; // UNDEFINED 5259 index = fieldFromInstruction(Insn, 5, 3); 5260 break; 5261 case 1: 5262 if (fieldFromInstruction(Insn, 5, 1)) 5263 return MCDisassembler::Fail; // UNDEFINED 5264 index = fieldFromInstruction(Insn, 6, 2); 5265 if (fieldFromInstruction(Insn, 4, 1)) 5266 align = 2; 5267 break; 5268 case 2: 5269 if (fieldFromInstruction(Insn, 6, 1)) 5270 return MCDisassembler::Fail; // UNDEFINED 5271 index = fieldFromInstruction(Insn, 7, 1); 5272 5273 switch (fieldFromInstruction(Insn, 4, 2)) { 5274 case 0 : 5275 align = 0; break; 5276 case 3: 5277 align = 4; break; 5278 default: 5279 return MCDisassembler::Fail; 5280 } 5281 break; 5282 } 5283 5284 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5285 return MCDisassembler::Fail; 5286 if (Rm != 0xF) { // Writeback 5287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5288 return MCDisassembler::Fail; 5289 } 5290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5291 return MCDisassembler::Fail; 5292 Inst.addOperand(MCOperand::createImm(align)); 5293 if (Rm != 0xF) { 5294 if (Rm != 0xD) { 5295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5296 return MCDisassembler::Fail; 5297 } else 5298 Inst.addOperand(MCOperand::createReg(0)); 5299 } 5300 5301 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5302 return MCDisassembler::Fail; 5303 Inst.addOperand(MCOperand::createImm(index)); 5304 5305 return S; 5306 } 5307 5308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5309 const MCDisassembler *Decoder) { 5310 DecodeStatus S = MCDisassembler::Success; 5311 5312 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5313 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5314 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5315 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5316 unsigned size = fieldFromInstruction(Insn, 10, 2); 5317 5318 unsigned align = 0; 5319 unsigned index = 0; 5320 switch (size) { 5321 default: 5322 return MCDisassembler::Fail; 5323 case 0: 5324 if (fieldFromInstruction(Insn, 4, 1)) 5325 return MCDisassembler::Fail; // UNDEFINED 5326 index = fieldFromInstruction(Insn, 5, 3); 5327 break; 5328 case 1: 5329 if (fieldFromInstruction(Insn, 5, 1)) 5330 return MCDisassembler::Fail; // UNDEFINED 5331 index = fieldFromInstruction(Insn, 6, 2); 5332 if (fieldFromInstruction(Insn, 4, 1)) 5333 align = 2; 5334 break; 5335 case 2: 5336 if (fieldFromInstruction(Insn, 6, 1)) 5337 return MCDisassembler::Fail; // UNDEFINED 5338 index = fieldFromInstruction(Insn, 7, 1); 5339 5340 switch (fieldFromInstruction(Insn, 4, 2)) { 5341 case 0: 5342 align = 0; break; 5343 case 3: 5344 align = 4; break; 5345 default: 5346 return MCDisassembler::Fail; 5347 } 5348 break; 5349 } 5350 5351 if (Rm != 0xF) { // Writeback 5352 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5353 return MCDisassembler::Fail; 5354 } 5355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5356 return MCDisassembler::Fail; 5357 Inst.addOperand(MCOperand::createImm(align)); 5358 if (Rm != 0xF) { 5359 if (Rm != 0xD) { 5360 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5361 return MCDisassembler::Fail; 5362 } else 5363 Inst.addOperand(MCOperand::createReg(0)); 5364 } 5365 5366 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5367 return MCDisassembler::Fail; 5368 Inst.addOperand(MCOperand::createImm(index)); 5369 5370 return S; 5371 } 5372 5373 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5374 const MCDisassembler *Decoder) { 5375 DecodeStatus S = MCDisassembler::Success; 5376 5377 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5378 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5379 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5380 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5381 unsigned size = fieldFromInstruction(Insn, 10, 2); 5382 5383 unsigned align = 0; 5384 unsigned index = 0; 5385 unsigned inc = 1; 5386 switch (size) { 5387 default: 5388 return MCDisassembler::Fail; 5389 case 0: 5390 index = fieldFromInstruction(Insn, 5, 3); 5391 if (fieldFromInstruction(Insn, 4, 1)) 5392 align = 2; 5393 break; 5394 case 1: 5395 index = fieldFromInstruction(Insn, 6, 2); 5396 if (fieldFromInstruction(Insn, 4, 1)) 5397 align = 4; 5398 if (fieldFromInstruction(Insn, 5, 1)) 5399 inc = 2; 5400 break; 5401 case 2: 5402 if (fieldFromInstruction(Insn, 5, 1)) 5403 return MCDisassembler::Fail; // UNDEFINED 5404 index = fieldFromInstruction(Insn, 7, 1); 5405 if (fieldFromInstruction(Insn, 4, 1) != 0) 5406 align = 8; 5407 if (fieldFromInstruction(Insn, 6, 1)) 5408 inc = 2; 5409 break; 5410 } 5411 5412 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5413 return MCDisassembler::Fail; 5414 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5415 return MCDisassembler::Fail; 5416 if (Rm != 0xF) { // Writeback 5417 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5418 return MCDisassembler::Fail; 5419 } 5420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5421 return MCDisassembler::Fail; 5422 Inst.addOperand(MCOperand::createImm(align)); 5423 if (Rm != 0xF) { 5424 if (Rm != 0xD) { 5425 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5426 return MCDisassembler::Fail; 5427 } else 5428 Inst.addOperand(MCOperand::createReg(0)); 5429 } 5430 5431 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5432 return MCDisassembler::Fail; 5433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5434 return MCDisassembler::Fail; 5435 Inst.addOperand(MCOperand::createImm(index)); 5436 5437 return S; 5438 } 5439 5440 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5441 const MCDisassembler *Decoder) { 5442 DecodeStatus S = MCDisassembler::Success; 5443 5444 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5445 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5446 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5447 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5448 unsigned size = fieldFromInstruction(Insn, 10, 2); 5449 5450 unsigned align = 0; 5451 unsigned index = 0; 5452 unsigned inc = 1; 5453 switch (size) { 5454 default: 5455 return MCDisassembler::Fail; 5456 case 0: 5457 index = fieldFromInstruction(Insn, 5, 3); 5458 if (fieldFromInstruction(Insn, 4, 1)) 5459 align = 2; 5460 break; 5461 case 1: 5462 index = fieldFromInstruction(Insn, 6, 2); 5463 if (fieldFromInstruction(Insn, 4, 1)) 5464 align = 4; 5465 if (fieldFromInstruction(Insn, 5, 1)) 5466 inc = 2; 5467 break; 5468 case 2: 5469 if (fieldFromInstruction(Insn, 5, 1)) 5470 return MCDisassembler::Fail; // UNDEFINED 5471 index = fieldFromInstruction(Insn, 7, 1); 5472 if (fieldFromInstruction(Insn, 4, 1) != 0) 5473 align = 8; 5474 if (fieldFromInstruction(Insn, 6, 1)) 5475 inc = 2; 5476 break; 5477 } 5478 5479 if (Rm != 0xF) { // Writeback 5480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5481 return MCDisassembler::Fail; 5482 } 5483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5484 return MCDisassembler::Fail; 5485 Inst.addOperand(MCOperand::createImm(align)); 5486 if (Rm != 0xF) { 5487 if (Rm != 0xD) { 5488 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5489 return MCDisassembler::Fail; 5490 } else 5491 Inst.addOperand(MCOperand::createReg(0)); 5492 } 5493 5494 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5495 return MCDisassembler::Fail; 5496 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5497 return MCDisassembler::Fail; 5498 Inst.addOperand(MCOperand::createImm(index)); 5499 5500 return S; 5501 } 5502 5503 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5504 const MCDisassembler *Decoder) { 5505 DecodeStatus S = MCDisassembler::Success; 5506 5507 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5508 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5509 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5510 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5511 unsigned size = fieldFromInstruction(Insn, 10, 2); 5512 5513 unsigned align = 0; 5514 unsigned index = 0; 5515 unsigned inc = 1; 5516 switch (size) { 5517 default: 5518 return MCDisassembler::Fail; 5519 case 0: 5520 if (fieldFromInstruction(Insn, 4, 1)) 5521 return MCDisassembler::Fail; // UNDEFINED 5522 index = fieldFromInstruction(Insn, 5, 3); 5523 break; 5524 case 1: 5525 if (fieldFromInstruction(Insn, 4, 1)) 5526 return MCDisassembler::Fail; // UNDEFINED 5527 index = fieldFromInstruction(Insn, 6, 2); 5528 if (fieldFromInstruction(Insn, 5, 1)) 5529 inc = 2; 5530 break; 5531 case 2: 5532 if (fieldFromInstruction(Insn, 4, 2)) 5533 return MCDisassembler::Fail; // UNDEFINED 5534 index = fieldFromInstruction(Insn, 7, 1); 5535 if (fieldFromInstruction(Insn, 6, 1)) 5536 inc = 2; 5537 break; 5538 } 5539 5540 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5541 return MCDisassembler::Fail; 5542 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5543 return MCDisassembler::Fail; 5544 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5545 return MCDisassembler::Fail; 5546 5547 if (Rm != 0xF) { // Writeback 5548 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5549 return MCDisassembler::Fail; 5550 } 5551 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5552 return MCDisassembler::Fail; 5553 Inst.addOperand(MCOperand::createImm(align)); 5554 if (Rm != 0xF) { 5555 if (Rm != 0xD) { 5556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5557 return MCDisassembler::Fail; 5558 } else 5559 Inst.addOperand(MCOperand::createReg(0)); 5560 } 5561 5562 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5563 return MCDisassembler::Fail; 5564 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5565 return MCDisassembler::Fail; 5566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5567 return MCDisassembler::Fail; 5568 Inst.addOperand(MCOperand::createImm(index)); 5569 5570 return S; 5571 } 5572 5573 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5574 const MCDisassembler *Decoder) { 5575 DecodeStatus S = MCDisassembler::Success; 5576 5577 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5578 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5579 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5580 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5581 unsigned size = fieldFromInstruction(Insn, 10, 2); 5582 5583 unsigned align = 0; 5584 unsigned index = 0; 5585 unsigned inc = 1; 5586 switch (size) { 5587 default: 5588 return MCDisassembler::Fail; 5589 case 0: 5590 if (fieldFromInstruction(Insn, 4, 1)) 5591 return MCDisassembler::Fail; // UNDEFINED 5592 index = fieldFromInstruction(Insn, 5, 3); 5593 break; 5594 case 1: 5595 if (fieldFromInstruction(Insn, 4, 1)) 5596 return MCDisassembler::Fail; // UNDEFINED 5597 index = fieldFromInstruction(Insn, 6, 2); 5598 if (fieldFromInstruction(Insn, 5, 1)) 5599 inc = 2; 5600 break; 5601 case 2: 5602 if (fieldFromInstruction(Insn, 4, 2)) 5603 return MCDisassembler::Fail; // UNDEFINED 5604 index = fieldFromInstruction(Insn, 7, 1); 5605 if (fieldFromInstruction(Insn, 6, 1)) 5606 inc = 2; 5607 break; 5608 } 5609 5610 if (Rm != 0xF) { // Writeback 5611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5612 return MCDisassembler::Fail; 5613 } 5614 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5615 return MCDisassembler::Fail; 5616 Inst.addOperand(MCOperand::createImm(align)); 5617 if (Rm != 0xF) { 5618 if (Rm != 0xD) { 5619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5620 return MCDisassembler::Fail; 5621 } else 5622 Inst.addOperand(MCOperand::createReg(0)); 5623 } 5624 5625 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5626 return MCDisassembler::Fail; 5627 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5628 return MCDisassembler::Fail; 5629 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5630 return MCDisassembler::Fail; 5631 Inst.addOperand(MCOperand::createImm(index)); 5632 5633 return S; 5634 } 5635 5636 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5637 const MCDisassembler *Decoder) { 5638 DecodeStatus S = MCDisassembler::Success; 5639 5640 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5641 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5642 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5643 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5644 unsigned size = fieldFromInstruction(Insn, 10, 2); 5645 5646 unsigned align = 0; 5647 unsigned index = 0; 5648 unsigned inc = 1; 5649 switch (size) { 5650 default: 5651 return MCDisassembler::Fail; 5652 case 0: 5653 if (fieldFromInstruction(Insn, 4, 1)) 5654 align = 4; 5655 index = fieldFromInstruction(Insn, 5, 3); 5656 break; 5657 case 1: 5658 if (fieldFromInstruction(Insn, 4, 1)) 5659 align = 8; 5660 index = fieldFromInstruction(Insn, 6, 2); 5661 if (fieldFromInstruction(Insn, 5, 1)) 5662 inc = 2; 5663 break; 5664 case 2: 5665 switch (fieldFromInstruction(Insn, 4, 2)) { 5666 case 0: 5667 align = 0; break; 5668 case 3: 5669 return MCDisassembler::Fail; 5670 default: 5671 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5672 } 5673 5674 index = fieldFromInstruction(Insn, 7, 1); 5675 if (fieldFromInstruction(Insn, 6, 1)) 5676 inc = 2; 5677 break; 5678 } 5679 5680 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5681 return MCDisassembler::Fail; 5682 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5683 return MCDisassembler::Fail; 5684 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5685 return MCDisassembler::Fail; 5686 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5687 return MCDisassembler::Fail; 5688 5689 if (Rm != 0xF) { // Writeback 5690 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5691 return MCDisassembler::Fail; 5692 } 5693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5694 return MCDisassembler::Fail; 5695 Inst.addOperand(MCOperand::createImm(align)); 5696 if (Rm != 0xF) { 5697 if (Rm != 0xD) { 5698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5699 return MCDisassembler::Fail; 5700 } else 5701 Inst.addOperand(MCOperand::createReg(0)); 5702 } 5703 5704 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5705 return MCDisassembler::Fail; 5706 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5707 return MCDisassembler::Fail; 5708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5709 return MCDisassembler::Fail; 5710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5711 return MCDisassembler::Fail; 5712 Inst.addOperand(MCOperand::createImm(index)); 5713 5714 return S; 5715 } 5716 5717 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5718 const MCDisassembler *Decoder) { 5719 DecodeStatus S = MCDisassembler::Success; 5720 5721 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5722 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5723 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5724 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5725 unsigned size = fieldFromInstruction(Insn, 10, 2); 5726 5727 unsigned align = 0; 5728 unsigned index = 0; 5729 unsigned inc = 1; 5730 switch (size) { 5731 default: 5732 return MCDisassembler::Fail; 5733 case 0: 5734 if (fieldFromInstruction(Insn, 4, 1)) 5735 align = 4; 5736 index = fieldFromInstruction(Insn, 5, 3); 5737 break; 5738 case 1: 5739 if (fieldFromInstruction(Insn, 4, 1)) 5740 align = 8; 5741 index = fieldFromInstruction(Insn, 6, 2); 5742 if (fieldFromInstruction(Insn, 5, 1)) 5743 inc = 2; 5744 break; 5745 case 2: 5746 switch (fieldFromInstruction(Insn, 4, 2)) { 5747 case 0: 5748 align = 0; break; 5749 case 3: 5750 return MCDisassembler::Fail; 5751 default: 5752 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5753 } 5754 5755 index = fieldFromInstruction(Insn, 7, 1); 5756 if (fieldFromInstruction(Insn, 6, 1)) 5757 inc = 2; 5758 break; 5759 } 5760 5761 if (Rm != 0xF) { // Writeback 5762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5763 return MCDisassembler::Fail; 5764 } 5765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5766 return MCDisassembler::Fail; 5767 Inst.addOperand(MCOperand::createImm(align)); 5768 if (Rm != 0xF) { 5769 if (Rm != 0xD) { 5770 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5771 return MCDisassembler::Fail; 5772 } else 5773 Inst.addOperand(MCOperand::createReg(0)); 5774 } 5775 5776 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5777 return MCDisassembler::Fail; 5778 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5779 return MCDisassembler::Fail; 5780 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5781 return MCDisassembler::Fail; 5782 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5783 return MCDisassembler::Fail; 5784 Inst.addOperand(MCOperand::createImm(index)); 5785 5786 return S; 5787 } 5788 5789 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 5790 const MCDisassembler *Decoder) { 5791 DecodeStatus S = MCDisassembler::Success; 5792 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5793 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5794 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5795 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5796 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5797 5798 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5799 S = MCDisassembler::SoftFail; 5800 5801 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5802 return MCDisassembler::Fail; 5803 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5804 return MCDisassembler::Fail; 5805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5806 return MCDisassembler::Fail; 5807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5808 return MCDisassembler::Fail; 5809 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5810 return MCDisassembler::Fail; 5811 5812 return S; 5813 } 5814 5815 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 5816 const MCDisassembler *Decoder) { 5817 DecodeStatus S = MCDisassembler::Success; 5818 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5819 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5820 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5821 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5822 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5823 5824 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5825 S = MCDisassembler::SoftFail; 5826 5827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5828 return MCDisassembler::Fail; 5829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5830 return MCDisassembler::Fail; 5831 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5832 return MCDisassembler::Fail; 5833 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5834 return MCDisassembler::Fail; 5835 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5836 return MCDisassembler::Fail; 5837 5838 return S; 5839 } 5840 5841 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, 5842 const MCDisassembler *Decoder) { 5843 DecodeStatus S = MCDisassembler::Success; 5844 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5845 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5846 5847 if (pred == 0xF) { 5848 pred = 0xE; 5849 S = MCDisassembler::SoftFail; 5850 } 5851 5852 if (mask == 0x0) 5853 return MCDisassembler::Fail; 5854 5855 // IT masks are encoded as a sequence of replacement low-order bits 5856 // for the condition code. So if the low bit of the starting 5857 // condition code is 1, then we have to flip all the bits above the 5858 // terminating bit (which is the lowest 1 bit). 5859 if (pred & 1) { 5860 unsigned LowBit = mask & -mask; 5861 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5862 mask ^= BitsAboveLowBit; 5863 } 5864 5865 Inst.addOperand(MCOperand::createImm(pred)); 5866 Inst.addOperand(MCOperand::createImm(mask)); 5867 return S; 5868 } 5869 5870 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5871 uint64_t Address, 5872 const MCDisassembler *Decoder) { 5873 DecodeStatus S = MCDisassembler::Success; 5874 5875 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5876 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5877 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5878 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5879 unsigned W = fieldFromInstruction(Insn, 21, 1); 5880 unsigned U = fieldFromInstruction(Insn, 23, 1); 5881 unsigned P = fieldFromInstruction(Insn, 24, 1); 5882 bool writeback = (W == 1) | (P == 0); 5883 5884 addr |= (U << 8) | (Rn << 9); 5885 5886 if (writeback && (Rn == Rt || Rn == Rt2)) 5887 Check(S, MCDisassembler::SoftFail); 5888 if (Rt == Rt2) 5889 Check(S, MCDisassembler::SoftFail); 5890 5891 // Rt 5892 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5893 return MCDisassembler::Fail; 5894 // Rt2 5895 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5896 return MCDisassembler::Fail; 5897 // Writeback operand 5898 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5899 return MCDisassembler::Fail; 5900 // addr 5901 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5902 return MCDisassembler::Fail; 5903 5904 return S; 5905 } 5906 5907 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5908 uint64_t Address, 5909 const MCDisassembler *Decoder) { 5910 DecodeStatus S = MCDisassembler::Success; 5911 5912 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5913 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5914 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5915 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5916 unsigned W = fieldFromInstruction(Insn, 21, 1); 5917 unsigned U = fieldFromInstruction(Insn, 23, 1); 5918 unsigned P = fieldFromInstruction(Insn, 24, 1); 5919 bool writeback = (W == 1) | (P == 0); 5920 5921 addr |= (U << 8) | (Rn << 9); 5922 5923 if (writeback && (Rn == Rt || Rn == Rt2)) 5924 Check(S, MCDisassembler::SoftFail); 5925 5926 // Writeback operand 5927 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5928 return MCDisassembler::Fail; 5929 // Rt 5930 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5931 return MCDisassembler::Fail; 5932 // Rt2 5933 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5934 return MCDisassembler::Fail; 5935 // addr 5936 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5937 return MCDisassembler::Fail; 5938 5939 return S; 5940 } 5941 5942 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, 5943 const MCDisassembler *Decoder) { 5944 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5945 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5946 if (sign1 != sign2) return MCDisassembler::Fail; 5947 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5948 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5949 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5950 5951 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5952 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5953 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5954 // If sign, then it is decreasing the address. 5955 if (sign1) { 5956 // Following ARMv7 Architecture Manual, when the offset 5957 // is zero, it is decoded as a subw, not as a adr.w 5958 if (!Val) { 5959 Inst.setOpcode(ARM::t2SUBri12); 5960 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5961 } else 5962 Val = -Val; 5963 } 5964 Inst.addOperand(MCOperand::createImm(Val)); 5965 return S; 5966 } 5967 5968 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5969 uint64_t Address, 5970 const MCDisassembler *Decoder) { 5971 DecodeStatus S = MCDisassembler::Success; 5972 5973 // Shift of "asr #32" is not allowed in Thumb2 mode. 5974 if (Val == 0x20) S = MCDisassembler::Fail; 5975 Inst.addOperand(MCOperand::createImm(Val)); 5976 return S; 5977 } 5978 5979 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 5980 const MCDisassembler *Decoder) { 5981 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5982 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5983 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5984 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5985 5986 if (pred == 0xF) 5987 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5988 5989 DecodeStatus S = MCDisassembler::Success; 5990 5991 if (Rt == Rn || Rn == Rt2) 5992 S = MCDisassembler::SoftFail; 5993 5994 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5995 return MCDisassembler::Fail; 5996 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5997 return MCDisassembler::Fail; 5998 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5999 return MCDisassembler::Fail; 6000 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6001 return MCDisassembler::Fail; 6002 6003 return S; 6004 } 6005 6006 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 6007 const MCDisassembler *Decoder) { 6008 const FeatureBitset &featureBits = 6009 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6010 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6011 6012 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6013 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6014 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6015 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6016 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6017 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6018 unsigned op = fieldFromInstruction(Insn, 5, 1); 6019 6020 DecodeStatus S = MCDisassembler::Success; 6021 6022 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6023 if (!(imm & 0x38)) { 6024 if (cmode == 0xF) { 6025 if (op == 1) return MCDisassembler::Fail; 6026 Inst.setOpcode(ARM::VMOVv2f32); 6027 } 6028 if (hasFullFP16) { 6029 if (cmode == 0xE) { 6030 if (op == 1) { 6031 Inst.setOpcode(ARM::VMOVv1i64); 6032 } else { 6033 Inst.setOpcode(ARM::VMOVv8i8); 6034 } 6035 } 6036 if (cmode == 0xD) { 6037 if (op == 1) { 6038 Inst.setOpcode(ARM::VMVNv2i32); 6039 } else { 6040 Inst.setOpcode(ARM::VMOVv2i32); 6041 } 6042 } 6043 if (cmode == 0xC) { 6044 if (op == 1) { 6045 Inst.setOpcode(ARM::VMVNv2i32); 6046 } else { 6047 Inst.setOpcode(ARM::VMOVv2i32); 6048 } 6049 } 6050 } 6051 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6052 } 6053 6054 if (!(imm & 0x20)) return MCDisassembler::Fail; 6055 6056 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 6057 return MCDisassembler::Fail; 6058 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6059 return MCDisassembler::Fail; 6060 Inst.addOperand(MCOperand::createImm(64 - imm)); 6061 6062 return S; 6063 } 6064 6065 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 6066 const MCDisassembler *Decoder) { 6067 const FeatureBitset &featureBits = 6068 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6069 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6070 6071 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6072 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6073 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6074 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6075 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6076 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6077 unsigned op = fieldFromInstruction(Insn, 5, 1); 6078 6079 DecodeStatus S = MCDisassembler::Success; 6080 6081 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6082 if (!(imm & 0x38)) { 6083 if (cmode == 0xF) { 6084 if (op == 1) return MCDisassembler::Fail; 6085 Inst.setOpcode(ARM::VMOVv4f32); 6086 } 6087 if (hasFullFP16) { 6088 if (cmode == 0xE) { 6089 if (op == 1) { 6090 Inst.setOpcode(ARM::VMOVv2i64); 6091 } else { 6092 Inst.setOpcode(ARM::VMOVv16i8); 6093 } 6094 } 6095 if (cmode == 0xD) { 6096 if (op == 1) { 6097 Inst.setOpcode(ARM::VMVNv4i32); 6098 } else { 6099 Inst.setOpcode(ARM::VMOVv4i32); 6100 } 6101 } 6102 if (cmode == 0xC) { 6103 if (op == 1) { 6104 Inst.setOpcode(ARM::VMVNv4i32); 6105 } else { 6106 Inst.setOpcode(ARM::VMOVv4i32); 6107 } 6108 } 6109 } 6110 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6111 } 6112 6113 if (!(imm & 0x20)) return MCDisassembler::Fail; 6114 6115 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 6116 return MCDisassembler::Fail; 6117 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 6118 return MCDisassembler::Fail; 6119 Inst.addOperand(MCOperand::createImm(64 - imm)); 6120 6121 return S; 6122 } 6123 6124 static DecodeStatus 6125 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, 6126 uint64_t Address, 6127 const MCDisassembler *Decoder) { 6128 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6129 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6130 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 6131 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 6132 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6133 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6134 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 6135 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 6136 6137 DecodeStatus S = MCDisassembler::Success; 6138 6139 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 6140 6141 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6142 return MCDisassembler::Fail; 6143 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6144 return MCDisassembler::Fail; 6145 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 6146 return MCDisassembler::Fail; 6147 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6148 return MCDisassembler::Fail; 6149 // The lane index does not have any bits in the encoding, because it can only 6150 // be 0. 6151 Inst.addOperand(MCOperand::createImm(0)); 6152 Inst.addOperand(MCOperand::createImm(rotate)); 6153 6154 return S; 6155 } 6156 6157 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 6158 const MCDisassembler *Decoder) { 6159 DecodeStatus S = MCDisassembler::Success; 6160 6161 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6162 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6163 unsigned Rm = fieldFromInstruction(Val, 0, 4); 6164 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 6165 unsigned Cond = fieldFromInstruction(Val, 28, 4); 6166 6167 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 6168 S = MCDisassembler::SoftFail; 6169 6170 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6171 return MCDisassembler::Fail; 6172 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6173 return MCDisassembler::Fail; 6174 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 6175 return MCDisassembler::Fail; 6176 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 6177 return MCDisassembler::Fail; 6178 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 6179 return MCDisassembler::Fail; 6180 6181 return S; 6182 } 6183 6184 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 6185 uint64_t Address, 6186 const MCDisassembler *Decoder) { 6187 DecodeStatus S = MCDisassembler::Success; 6188 6189 unsigned CRm = fieldFromInstruction(Val, 0, 4); 6190 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 6191 unsigned cop = fieldFromInstruction(Val, 8, 4); 6192 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6193 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 6194 6195 if ((cop & ~0x1) == 0xa) 6196 return MCDisassembler::Fail; 6197 6198 if (Rt == Rt2) 6199 S = MCDisassembler::SoftFail; 6200 6201 // We have to check if the instruction is MRRC2 6202 // or MCRR2 when constructing the operands for 6203 // Inst. Reason is because MRRC2 stores to two 6204 // registers so it's tablegen desc has has two 6205 // outputs whereas MCRR doesn't store to any 6206 // registers so all of it's operands are listed 6207 // as inputs, therefore the operand order for 6208 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 6209 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 6210 6211 if (Inst.getOpcode() == ARM::MRRC2) { 6212 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6213 return MCDisassembler::Fail; 6214 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6215 return MCDisassembler::Fail; 6216 } 6217 Inst.addOperand(MCOperand::createImm(cop)); 6218 Inst.addOperand(MCOperand::createImm(opc1)); 6219 if (Inst.getOpcode() == ARM::MCRR2) { 6220 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6221 return MCDisassembler::Fail; 6222 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6223 return MCDisassembler::Fail; 6224 } 6225 Inst.addOperand(MCOperand::createImm(CRm)); 6226 6227 return S; 6228 } 6229 6230 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 6231 uint64_t Address, 6232 const MCDisassembler *Decoder) { 6233 const FeatureBitset &featureBits = 6234 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6235 DecodeStatus S = MCDisassembler::Success; 6236 6237 // Add explicit operand for the destination sysreg, for cases where 6238 // we have to model it for code generation purposes. 6239 switch (Inst.getOpcode()) { 6240 case ARM::VMSR_FPSCR_NZCVQC: 6241 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6242 break; 6243 case ARM::VMSR_P0: 6244 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6245 break; 6246 } 6247 6248 if (Inst.getOpcode() != ARM::FMSTAT) { 6249 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6250 6251 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 6252 if (Rt == 13 || Rt == 15) 6253 S = MCDisassembler::SoftFail; 6254 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 6255 } else 6256 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 6257 } 6258 6259 // Add explicit operand for the source sysreg, similarly to above. 6260 switch (Inst.getOpcode()) { 6261 case ARM::VMRS_FPSCR_NZCVQC: 6262 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6263 break; 6264 case ARM::VMRS_P0: 6265 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6266 break; 6267 } 6268 6269 if (featureBits[ARM::ModeThumb]) { 6270 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6271 Inst.addOperand(MCOperand::createReg(0)); 6272 } else { 6273 unsigned pred = fieldFromInstruction(Val, 28, 4); 6274 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6275 return MCDisassembler::Fail; 6276 } 6277 6278 return S; 6279 } 6280 6281 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 6282 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 6283 uint64_t Address, 6284 const MCDisassembler *Decoder) { 6285 DecodeStatus S = MCDisassembler::Success; 6286 if (Val == 0 && !zeroPermitted) 6287 S = MCDisassembler::Fail; 6288 6289 uint64_t DecVal; 6290 if (isSigned) 6291 DecVal = SignExtend32<size + 1>(Val << 1); 6292 else 6293 DecVal = (Val << 1); 6294 6295 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 6296 Decoder)) 6297 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 6298 return S; 6299 } 6300 6301 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 6302 uint64_t Address, 6303 const MCDisassembler *Decoder) { 6304 6305 uint64_t LocImm = Inst.getOperand(0).getImm(); 6306 Val = LocImm + (2 << Val); 6307 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 6308 Decoder)) 6309 Inst.addOperand(MCOperand::createImm(Val)); 6310 return MCDisassembler::Success; 6311 } 6312 6313 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 6314 uint64_t Address, 6315 const MCDisassembler *Decoder) { 6316 if (Val >= ARMCC::AL) // also exclude the non-condition NV 6317 return MCDisassembler::Fail; 6318 Inst.addOperand(MCOperand::createImm(Val)); 6319 return MCDisassembler::Success; 6320 } 6321 6322 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6323 const MCDisassembler *Decoder) { 6324 DecodeStatus S = MCDisassembler::Success; 6325 6326 if (Inst.getOpcode() == ARM::MVE_LCTP) 6327 return S; 6328 6329 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6330 fieldFromInstruction(Insn, 1, 10) << 1; 6331 switch (Inst.getOpcode()) { 6332 case ARM::t2LEUpdate: 6333 case ARM::MVE_LETP: 6334 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6335 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6336 [[fallthrough]]; 6337 case ARM::t2LE: 6338 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6339 Inst, Imm, Address, Decoder))) 6340 return MCDisassembler::Fail; 6341 break; 6342 case ARM::t2WLS: 6343 case ARM::MVE_WLSTP_8: 6344 case ARM::MVE_WLSTP_16: 6345 case ARM::MVE_WLSTP_32: 6346 case ARM::MVE_WLSTP_64: 6347 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6348 if (!Check(S, 6349 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6350 Address, Decoder)) || 6351 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6352 Inst, Imm, Address, Decoder))) 6353 return MCDisassembler::Fail; 6354 break; 6355 case ARM::t2DLS: 6356 case ARM::MVE_DLSTP_8: 6357 case ARM::MVE_DLSTP_16: 6358 case ARM::MVE_DLSTP_32: 6359 case ARM::MVE_DLSTP_64: 6360 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6361 if (Rn == 0xF) { 6362 // Enforce all the rest of the instruction bits in LCTP, which 6363 // won't have been reliably checked based on LCTP's own tablegen 6364 // record, because we came to this decode by a roundabout route. 6365 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6366 if ((Insn & ~SBZMask) != CanonicalLCTP) 6367 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6368 if (Insn != CanonicalLCTP) 6369 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6370 6371 Inst.setOpcode(ARM::MVE_LCTP); 6372 } else { 6373 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6374 if (!Check(S, DecoderGPRRegisterClass(Inst, 6375 fieldFromInstruction(Insn, 16, 4), 6376 Address, Decoder))) 6377 return MCDisassembler::Fail; 6378 } 6379 break; 6380 } 6381 return S; 6382 } 6383 6384 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6385 uint64_t Address, 6386 const MCDisassembler *Decoder) { 6387 DecodeStatus S = MCDisassembler::Success; 6388 6389 if (Val == 0) 6390 Val = 32; 6391 6392 Inst.addOperand(MCOperand::createImm(Val)); 6393 6394 return S; 6395 } 6396 6397 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6398 uint64_t Address, 6399 const MCDisassembler *Decoder) { 6400 if ((RegNo) + 1 > 11) 6401 return MCDisassembler::Fail; 6402 6403 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6404 Inst.addOperand(MCOperand::createReg(Register)); 6405 return MCDisassembler::Success; 6406 } 6407 6408 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6409 uint64_t Address, 6410 const MCDisassembler *Decoder) { 6411 if ((RegNo) > 14) 6412 return MCDisassembler::Fail; 6413 6414 unsigned Register = GPRDecoderTable[(RegNo)]; 6415 Inst.addOperand(MCOperand::createReg(Register)); 6416 return MCDisassembler::Success; 6417 } 6418 6419 static DecodeStatus 6420 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6421 uint64_t Address, 6422 const MCDisassembler *Decoder) { 6423 if (RegNo == 15) { 6424 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6425 return MCDisassembler::Success; 6426 } 6427 6428 unsigned Register = GPRDecoderTable[RegNo]; 6429 Inst.addOperand(MCOperand::createReg(Register)); 6430 6431 if (RegNo == 13) 6432 return MCDisassembler::SoftFail; 6433 6434 return MCDisassembler::Success; 6435 } 6436 6437 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6438 const MCDisassembler *Decoder) { 6439 DecodeStatus S = MCDisassembler::Success; 6440 6441 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6442 Inst.addOperand(MCOperand::createReg(0)); 6443 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6444 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6445 (fieldFromInstruction(Insn, 12, 4) << 8) | 6446 (fieldFromInstruction(Insn, 22, 1) << 12); 6447 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6448 return MCDisassembler::Fail; 6449 } 6450 } else { 6451 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6452 (fieldFromInstruction(Insn, 22, 1) << 8) | 6453 (fieldFromInstruction(Insn, 12, 4) << 9); 6454 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6455 return MCDisassembler::Fail; 6456 } 6457 } 6458 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6459 6460 return S; 6461 } 6462 6463 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6464 uint64_t Address, 6465 const MCDisassembler *Decoder) { 6466 if (RegNo > 7) 6467 return MCDisassembler::Fail; 6468 6469 unsigned Register = QPRDecoderTable[RegNo]; 6470 Inst.addOperand(MCOperand::createReg(Register)); 6471 return MCDisassembler::Success; 6472 } 6473 6474 static const uint16_t QQPRDecoderTable[] = { 6475 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6476 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6477 }; 6478 6479 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6480 uint64_t Address, 6481 const MCDisassembler *Decoder) { 6482 if (RegNo > 6) 6483 return MCDisassembler::Fail; 6484 6485 unsigned Register = QQPRDecoderTable[RegNo]; 6486 Inst.addOperand(MCOperand::createReg(Register)); 6487 return MCDisassembler::Success; 6488 } 6489 6490 static const uint16_t QQQQPRDecoderTable[] = { 6491 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6492 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6493 }; 6494 6495 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6496 uint64_t Address, 6497 const MCDisassembler *Decoder) { 6498 if (RegNo > 4) 6499 return MCDisassembler::Fail; 6500 6501 unsigned Register = QQQQPRDecoderTable[RegNo]; 6502 Inst.addOperand(MCOperand::createReg(Register)); 6503 return MCDisassembler::Success; 6504 } 6505 6506 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6507 uint64_t Address, 6508 const MCDisassembler *Decoder) { 6509 DecodeStatus S = MCDisassembler::Success; 6510 6511 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6512 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6513 // 't' as 0 and finish with a 1. 6514 unsigned Imm = 0; 6515 // We always start with a 't'. 6516 unsigned CurBit = 0; 6517 for (int i = 3; i >= 0; --i) { 6518 // If the bit we are looking at is not the same as last one, invert the 6519 // CurBit, if it is the same leave it as is. 6520 CurBit ^= (Val >> i) & 1U; 6521 6522 // Encode the CurBit at the right place in the immediate. 6523 Imm |= (CurBit << i); 6524 6525 // If we are done, finish the encoding with a 1. 6526 if ((Val & ~(~0U << i)) == 0) { 6527 Imm |= 1U << i; 6528 break; 6529 } 6530 } 6531 6532 Inst.addOperand(MCOperand::createImm(Imm)); 6533 6534 return S; 6535 } 6536 6537 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6538 uint64_t Address, 6539 const MCDisassembler *Decoder) { 6540 // The vpred_r operand type includes an MQPR register field derived 6541 // from the encoding. But we don't actually want to add an operand 6542 // to the MCInst at this stage, because AddThumbPredicate will do it 6543 // later, and will infer the register number from the TIED_TO 6544 // constraint. So this is a deliberately empty decoder method that 6545 // will inhibit the auto-generated disassembly code from adding an 6546 // operand at all. 6547 return MCDisassembler::Success; 6548 } 6549 6550 [[maybe_unused]] static DecodeStatus 6551 DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address, 6552 const MCDisassembler *Decoder) { 6553 // Similar to above, we want to ensure that no operands are added for the 6554 // vpred operands. (This is marked "maybe_unused" for the moment; because 6555 // DecoderEmitter currently (wrongly) omits operands with no instruction bits, 6556 // the decoder doesn't actually call it yet. That will be addressed in a 6557 // future change.) 6558 return MCDisassembler::Success; 6559 } 6560 6561 static DecodeStatus 6562 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6563 const MCDisassembler *Decoder) { 6564 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6565 return MCDisassembler::Success; 6566 } 6567 6568 static DecodeStatus 6569 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6570 const MCDisassembler *Decoder) { 6571 unsigned Code; 6572 switch (Val & 0x3) { 6573 case 0: 6574 Code = ARMCC::GE; 6575 break; 6576 case 1: 6577 Code = ARMCC::LT; 6578 break; 6579 case 2: 6580 Code = ARMCC::GT; 6581 break; 6582 case 3: 6583 Code = ARMCC::LE; 6584 break; 6585 } 6586 Inst.addOperand(MCOperand::createImm(Code)); 6587 return MCDisassembler::Success; 6588 } 6589 6590 static DecodeStatus 6591 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6592 const MCDisassembler *Decoder) { 6593 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6594 return MCDisassembler::Success; 6595 } 6596 6597 static DecodeStatus 6598 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6599 const MCDisassembler *Decoder) { 6600 unsigned Code; 6601 switch (Val) { 6602 default: 6603 return MCDisassembler::Fail; 6604 case 0: 6605 Code = ARMCC::EQ; 6606 break; 6607 case 1: 6608 Code = ARMCC::NE; 6609 break; 6610 case 4: 6611 Code = ARMCC::GE; 6612 break; 6613 case 5: 6614 Code = ARMCC::LT; 6615 break; 6616 case 6: 6617 Code = ARMCC::GT; 6618 break; 6619 case 7: 6620 Code = ARMCC::LE; 6621 break; 6622 } 6623 6624 Inst.addOperand(MCOperand::createImm(Code)); 6625 return MCDisassembler::Success; 6626 } 6627 6628 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6629 uint64_t Address, 6630 const MCDisassembler *Decoder) { 6631 DecodeStatus S = MCDisassembler::Success; 6632 6633 unsigned DecodedVal = 64 - Val; 6634 6635 switch (Inst.getOpcode()) { 6636 case ARM::MVE_VCVTf16s16_fix: 6637 case ARM::MVE_VCVTs16f16_fix: 6638 case ARM::MVE_VCVTf16u16_fix: 6639 case ARM::MVE_VCVTu16f16_fix: 6640 if (DecodedVal > 16) 6641 return MCDisassembler::Fail; 6642 break; 6643 case ARM::MVE_VCVTf32s32_fix: 6644 case ARM::MVE_VCVTs32f32_fix: 6645 case ARM::MVE_VCVTf32u32_fix: 6646 case ARM::MVE_VCVTu32f32_fix: 6647 if (DecodedVal > 32) 6648 return MCDisassembler::Fail; 6649 break; 6650 } 6651 6652 Inst.addOperand(MCOperand::createImm(64 - Val)); 6653 6654 return S; 6655 } 6656 6657 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6658 switch (Opcode) { 6659 case ARM::VSTR_P0_off: 6660 case ARM::VSTR_P0_pre: 6661 case ARM::VSTR_P0_post: 6662 case ARM::VLDR_P0_off: 6663 case ARM::VLDR_P0_pre: 6664 case ARM::VLDR_P0_post: 6665 return ARM::P0; 6666 default: 6667 return 0; 6668 } 6669 } 6670 6671 template <bool Writeback> 6672 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6673 uint64_t Address, 6674 const MCDisassembler *Decoder) { 6675 switch (Inst.getOpcode()) { 6676 case ARM::VSTR_FPSCR_pre: 6677 case ARM::VSTR_FPSCR_NZCVQC_pre: 6678 case ARM::VLDR_FPSCR_pre: 6679 case ARM::VLDR_FPSCR_NZCVQC_pre: 6680 case ARM::VSTR_FPSCR_off: 6681 case ARM::VSTR_FPSCR_NZCVQC_off: 6682 case ARM::VLDR_FPSCR_off: 6683 case ARM::VLDR_FPSCR_NZCVQC_off: 6684 case ARM::VSTR_FPSCR_post: 6685 case ARM::VSTR_FPSCR_NZCVQC_post: 6686 case ARM::VLDR_FPSCR_post: 6687 case ARM::VLDR_FPSCR_NZCVQC_post: 6688 const FeatureBitset &featureBits = 6689 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6690 6691 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6692 return MCDisassembler::Fail; 6693 } 6694 6695 DecodeStatus S = MCDisassembler::Success; 6696 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6697 Inst.addOperand(MCOperand::createReg(Sysreg)); 6698 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6699 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6700 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6701 6702 if (Writeback) { 6703 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6704 return MCDisassembler::Fail; 6705 } 6706 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6707 return MCDisassembler::Fail; 6708 6709 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6710 Inst.addOperand(MCOperand::createReg(0)); 6711 6712 return S; 6713 } 6714 6715 static inline DecodeStatus 6716 DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, 6717 const MCDisassembler *Decoder, unsigned Rn, 6718 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6719 DecodeStatus S = MCDisassembler::Success; 6720 6721 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6722 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6723 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6724 6725 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6726 return MCDisassembler::Fail; 6727 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6728 return MCDisassembler::Fail; 6729 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6730 return MCDisassembler::Fail; 6731 6732 return S; 6733 } 6734 6735 template <int shift> 6736 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6737 uint64_t Address, 6738 const MCDisassembler *Decoder) { 6739 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6740 fieldFromInstruction(Val, 16, 3), 6741 DecodetGPRRegisterClass, 6742 DecodeTAddrModeImm7<shift>); 6743 } 6744 6745 template <int shift> 6746 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6747 uint64_t Address, 6748 const MCDisassembler *Decoder) { 6749 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6750 fieldFromInstruction(Val, 16, 4), 6751 DecoderGPRRegisterClass, 6752 DecodeT2AddrModeImm7<shift,1>); 6753 } 6754 6755 template <int shift> 6756 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6757 uint64_t Address, 6758 const MCDisassembler *Decoder) { 6759 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6760 fieldFromInstruction(Val, 17, 3), 6761 DecodeMQPRRegisterClass, 6762 DecodeMveAddrModeQ<shift>); 6763 } 6764 6765 template <unsigned MinLog, unsigned MaxLog> 6766 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6767 uint64_t Address, 6768 const MCDisassembler *Decoder) { 6769 DecodeStatus S = MCDisassembler::Success; 6770 6771 if (Val < MinLog || Val > MaxLog) 6772 return MCDisassembler::Fail; 6773 6774 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6775 return S; 6776 } 6777 6778 template <unsigned start> 6779 static DecodeStatus 6780 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6781 const MCDisassembler *Decoder) { 6782 DecodeStatus S = MCDisassembler::Success; 6783 6784 Inst.addOperand(MCOperand::createImm(start + Val)); 6785 6786 return S; 6787 } 6788 6789 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6790 uint64_t Address, 6791 const MCDisassembler *Decoder) { 6792 DecodeStatus S = MCDisassembler::Success; 6793 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6794 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6795 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6796 fieldFromInstruction(Insn, 13, 3)); 6797 unsigned index = fieldFromInstruction(Insn, 4, 1); 6798 6799 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6800 return MCDisassembler::Fail; 6801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6802 return MCDisassembler::Fail; 6803 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6804 return MCDisassembler::Fail; 6805 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6806 return MCDisassembler::Fail; 6807 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6808 return MCDisassembler::Fail; 6809 6810 return S; 6811 } 6812 6813 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6814 uint64_t Address, 6815 const MCDisassembler *Decoder) { 6816 DecodeStatus S = MCDisassembler::Success; 6817 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6818 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6819 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6820 fieldFromInstruction(Insn, 13, 3)); 6821 unsigned index = fieldFromInstruction(Insn, 4, 1); 6822 6823 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6824 return MCDisassembler::Fail; 6825 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6826 return MCDisassembler::Fail; 6827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6828 return MCDisassembler::Fail; 6829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6830 return MCDisassembler::Fail; 6831 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6832 return MCDisassembler::Fail; 6833 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6834 return MCDisassembler::Fail; 6835 6836 return S; 6837 } 6838 6839 static DecodeStatus 6840 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 6841 const MCDisassembler *Decoder) { 6842 DecodeStatus S = MCDisassembler::Success; 6843 6844 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6845 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6846 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6847 6848 if (RdaHi == 14) { 6849 // This value of RdaHi (really indicating pc, because RdaHi has to 6850 // be an odd-numbered register, so the low bit will be set by the 6851 // decode function below) indicates that we must decode as SQRSHR 6852 // or UQRSHL, which both have a single Rda register field with all 6853 // four bits. 6854 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6855 6856 switch (Inst.getOpcode()) { 6857 case ARM::MVE_ASRLr: 6858 case ARM::MVE_SQRSHRL: 6859 Inst.setOpcode(ARM::MVE_SQRSHR); 6860 break; 6861 case ARM::MVE_LSLLr: 6862 case ARM::MVE_UQRSHLL: 6863 Inst.setOpcode(ARM::MVE_UQRSHL); 6864 break; 6865 default: 6866 llvm_unreachable("Unexpected starting opcode!"); 6867 } 6868 6869 // Rda as output parameter 6870 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6871 return MCDisassembler::Fail; 6872 6873 // Rda again as input parameter 6874 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6875 return MCDisassembler::Fail; 6876 6877 // Rm, the amount to shift by 6878 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6879 return MCDisassembler::Fail; 6880 6881 if (fieldFromInstruction (Insn, 6, 3) != 4) 6882 return MCDisassembler::SoftFail; 6883 6884 if (Rda == Rm) 6885 return MCDisassembler::SoftFail; 6886 6887 return S; 6888 } 6889 6890 // Otherwise, we decode as whichever opcode our caller has already 6891 // put into Inst. Those all look the same: 6892 6893 // RdaLo,RdaHi as output parameters 6894 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6895 return MCDisassembler::Fail; 6896 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6897 return MCDisassembler::Fail; 6898 6899 // RdaLo,RdaHi again as input parameters 6900 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6901 return MCDisassembler::Fail; 6902 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6903 return MCDisassembler::Fail; 6904 6905 // Rm, the amount to shift by 6906 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6907 return MCDisassembler::Fail; 6908 6909 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6910 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6911 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6912 // Saturate, the bit position for saturation 6913 Inst.addOperand(MCOperand::createImm(Saturate)); 6914 } 6915 6916 return S; 6917 } 6918 6919 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 6920 uint64_t Address, 6921 const MCDisassembler *Decoder) { 6922 DecodeStatus S = MCDisassembler::Success; 6923 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6924 fieldFromInstruction(Insn, 13, 3)); 6925 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6926 fieldFromInstruction(Insn, 1, 3)); 6927 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6928 6929 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6930 return MCDisassembler::Fail; 6931 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6932 return MCDisassembler::Fail; 6933 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6934 return MCDisassembler::Fail; 6935 6936 return S; 6937 } 6938 6939 template <bool scalar, OperandDecoder predicate_decoder> 6940 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6941 const MCDisassembler *Decoder) { 6942 DecodeStatus S = MCDisassembler::Success; 6943 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6944 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6945 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6946 return MCDisassembler::Fail; 6947 6948 unsigned fc; 6949 6950 if (scalar) { 6951 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6952 fieldFromInstruction(Insn, 7, 1) | 6953 fieldFromInstruction(Insn, 5, 1) << 1; 6954 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6955 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6956 return MCDisassembler::Fail; 6957 } else { 6958 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6959 fieldFromInstruction(Insn, 7, 1) | 6960 fieldFromInstruction(Insn, 0, 1) << 1; 6961 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6962 fieldFromInstruction(Insn, 1, 3); 6963 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6964 return MCDisassembler::Fail; 6965 } 6966 6967 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6968 return MCDisassembler::Fail; 6969 6970 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6971 Inst.addOperand(MCOperand::createReg(0)); 6972 Inst.addOperand(MCOperand::createImm(0)); 6973 6974 return S; 6975 } 6976 6977 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6978 const MCDisassembler *Decoder) { 6979 DecodeStatus S = MCDisassembler::Success; 6980 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6981 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6982 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6983 return MCDisassembler::Fail; 6984 return S; 6985 } 6986 6987 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 6988 uint64_t Address, 6989 const MCDisassembler *Decoder) { 6990 DecodeStatus S = MCDisassembler::Success; 6991 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6992 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6993 return S; 6994 } 6995 6996 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6997 uint64_t Address, 6998 const MCDisassembler *Decoder) { 6999 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 7000 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 7001 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 7002 fieldFromInstruction(Insn, 12, 3) << 8 | 7003 fieldFromInstruction(Insn, 0, 8); 7004 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 7005 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 7006 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 7007 unsigned S = fieldFromInstruction(Insn, 20, 1); 7008 if (sign1 != sign2) 7009 return MCDisassembler::Fail; 7010 7011 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 7012 DecodeStatus DS = MCDisassembler::Success; 7013 if ((!Check(DS, 7014 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 7015 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 7016 return MCDisassembler::Fail; 7017 if (TypeT3) { 7018 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 7019 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 7020 } else { 7021 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 7022 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 7023 return MCDisassembler::Fail; 7024 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 7025 return MCDisassembler::Fail; 7026 } 7027 7028 return DS; 7029 } 7030