1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCDisassembler.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCFixedLenDisassembler.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/LEB128.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <vector> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "arm-disassembler" 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 // Handles the condition code status of instructions in IT blocks 35 class ITStatus 36 { 37 public: 38 // Returns the condition code for instruction in IT block 39 unsigned getITCC() { 40 unsigned CC = ARMCC::AL; 41 if (instrInITBlock()) 42 CC = ITStates.back(); 43 return CC; 44 } 45 46 // Advances the IT block state to the next T or E 47 void advanceITState() { 48 ITStates.pop_back(); 49 } 50 51 // Returns true if the current instruction is in an IT block 52 bool instrInITBlock() { 53 return !ITStates.empty(); 54 } 55 56 // Returns true if current instruction is the last instruction in an IT block 57 bool instrLastInITBlock() { 58 return ITStates.size() == 1; 59 } 60 61 // Called when decoding an IT instruction. Sets the IT state for the following 62 // instructions that for the IT block. Firstcond and Mask correspond to the 63 // fields in the IT instruction encoding. 64 void setITState(char Firstcond, char Mask) { 65 // (3 - the number of trailing zeros) is the number of then / else. 66 unsigned CondBit0 = Firstcond & 1; 67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 69 assert(NumTZ <= 3 && "Invalid IT mask!"); 70 // push condition codes onto the stack the correct order for the pops 71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 72 bool T = ((Mask >> Pos) & 1) == CondBit0; 73 if (T) 74 ITStates.push_back(CCBits); 75 else 76 ITStates.push_back(CCBits ^ 1); 77 } 78 ITStates.push_back(CCBits); 79 } 80 81 private: 82 std::vector<unsigned char> ITStates; 83 }; 84 } 85 86 namespace { 87 /// ARM disassembler for all ARM platforms. 88 class ARMDisassembler : public MCDisassembler { 89 public: 90 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 91 MCDisassembler(STI, Ctx) { 92 } 93 94 ~ARMDisassembler() {} 95 96 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 97 ArrayRef<uint8_t> Bytes, uint64_t Address, 98 raw_ostream &VStream, 99 raw_ostream &CStream) const override; 100 }; 101 102 /// Thumb disassembler for all Thumb platforms. 103 class ThumbDisassembler : public MCDisassembler { 104 public: 105 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 106 MCDisassembler(STI, Ctx) { 107 } 108 109 ~ThumbDisassembler() {} 110 111 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 112 ArrayRef<uint8_t> Bytes, uint64_t Address, 113 raw_ostream &VStream, 114 raw_ostream &CStream) const override; 115 116 private: 117 mutable ITStatus ITBlock; 118 DecodeStatus AddThumbPredicate(MCInst&) const; 119 void UpdateThumbVFPPredicate(MCInst&) const; 120 }; 121 } 122 123 static bool Check(DecodeStatus &Out, DecodeStatus In) { 124 switch (In) { 125 case MCDisassembler::Success: 126 // Out stays the same. 127 return true; 128 case MCDisassembler::SoftFail: 129 Out = In; 130 return true; 131 case MCDisassembler::Fail: 132 Out = In; 133 return false; 134 } 135 llvm_unreachable("Invalid DecodeStatus!"); 136 } 137 138 139 // Forward declare these because the autogenerated code will reference them. 140 // Definitions are further down. 141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, const void *Decoder); 143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 144 unsigned RegNo, uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 147 unsigned RegNo, uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 150 uint64_t Address, const void *Decoder); 151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 164 unsigned RegNo, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 172 unsigned RegNo, uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 186 uint64_t Address, const void *Decoder); 187 188 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 191 uint64_t Address, const void *Decoder); 192 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 193 unsigned Insn, 194 uint64_t Address, 195 const void *Decoder); 196 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 201 uint64_t Address, const void *Decoder); 202 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 203 uint64_t Address, const void *Decoder); 204 205 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 206 unsigned Insn, 207 uint64_t Adddress, 208 const void *Decoder); 209 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 314 uint64_t Address, const void *Decoder); 315 316 317 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void* Decoder); 339 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 340 uint64_t Address, const void* Decoder); 341 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 342 uint64_t Address, const void* Decoder); 343 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 344 uint64_t Address, const void* Decoder); 345 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 388 uint64_t Address, const void *Decoder); 389 390 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 393 uint64_t Address, const void *Decoder); 394 #include "ARMGenDisassemblerTables.inc" 395 396 static MCDisassembler *createARMDisassembler(const Target &T, 397 const MCSubtargetInfo &STI, 398 MCContext &Ctx) { 399 return new ARMDisassembler(STI, Ctx); 400 } 401 402 static MCDisassembler *createThumbDisassembler(const Target &T, 403 const MCSubtargetInfo &STI, 404 MCContext &Ctx) { 405 return new ThumbDisassembler(STI, Ctx); 406 } 407 408 // Post-decoding checks 409 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 410 uint64_t Address, raw_ostream &OS, 411 raw_ostream &CS, 412 uint32_t Insn, 413 DecodeStatus Result) 414 { 415 switch (MI.getOpcode()) { 416 case ARM::HVC: { 417 // HVC is undefined if condition = 0xf otherwise upredictable 418 // if condition != 0xe 419 uint32_t Cond = (Insn >> 28) & 0xF; 420 if (Cond == 0xF) 421 return MCDisassembler::Fail; 422 if (Cond != 0xE) 423 return MCDisassembler::SoftFail; 424 return Result; 425 } 426 default: return Result; 427 } 428 } 429 430 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 431 ArrayRef<uint8_t> Bytes, 432 uint64_t Address, raw_ostream &OS, 433 raw_ostream &CS) const { 434 CommentStream = &CS; 435 436 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 437 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 438 "mode!"); 439 440 // We want to read exactly 4 bytes of data. 441 if (Bytes.size() < 4) { 442 Size = 0; 443 return MCDisassembler::Fail; 444 } 445 446 // Encoded as a small-endian 32-bit word in the stream. 447 uint32_t Insn = 448 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 449 450 // Calling the auto-generated decoder function. 451 DecodeStatus Result = 452 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 453 if (Result != MCDisassembler::Fail) { 454 Size = 4; 455 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 456 } 457 458 // VFP and NEON instructions, similarly, are shared between ARM 459 // and Thumb modes. 460 MI.clear(); 461 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI); 462 if (Result != MCDisassembler::Fail) { 463 Size = 4; 464 return Result; 465 } 466 467 MI.clear(); 468 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI); 469 if (Result != MCDisassembler::Fail) { 470 Size = 4; 471 return Result; 472 } 473 474 MI.clear(); 475 Result = 476 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI); 477 if (Result != MCDisassembler::Fail) { 478 Size = 4; 479 // Add a fake predicate operand, because we share these instruction 480 // definitions with Thumb2 where these instructions are predicable. 481 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 482 return MCDisassembler::Fail; 483 return Result; 484 } 485 486 MI.clear(); 487 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address, 488 this, STI); 489 if (Result != MCDisassembler::Fail) { 490 Size = 4; 491 // Add a fake predicate operand, because we share these instruction 492 // definitions with Thumb2 where these instructions are predicable. 493 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 494 return MCDisassembler::Fail; 495 return Result; 496 } 497 498 MI.clear(); 499 Result = 500 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI); 501 if (Result != MCDisassembler::Fail) { 502 Size = 4; 503 // Add a fake predicate operand, because we share these instruction 504 // definitions with Thumb2 where these instructions are predicable. 505 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 506 return MCDisassembler::Fail; 507 return Result; 508 } 509 510 MI.clear(); 511 Result = 512 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI); 513 if (Result != MCDisassembler::Fail) { 514 Size = 4; 515 return Result; 516 } 517 518 MI.clear(); 519 Result = 520 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI); 521 if (Result != MCDisassembler::Fail) { 522 Size = 4; 523 return Result; 524 } 525 526 MI.clear(); 527 Size = 0; 528 return MCDisassembler::Fail; 529 } 530 531 namespace llvm { 532 extern const MCInstrDesc ARMInsts[]; 533 } 534 535 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 536 /// immediate Value in the MCInst. The immediate Value has had any PC 537 /// adjustment made by the caller. If the instruction is a branch instruction 538 /// then isBranch is true, else false. If the getOpInfo() function was set as 539 /// part of the setupForSymbolicDisassembly() call then that function is called 540 /// to get any symbolic information at the Address for this instruction. If 541 /// that returns non-zero then the symbolic information it returns is used to 542 /// create an MCExpr and that is added as an operand to the MCInst. If 543 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 544 /// Value is done and if a symbol is found an MCExpr is created with that, else 545 /// an MCExpr with Value is created. This function returns true if it adds an 546 /// operand to the MCInst and false otherwise. 547 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 548 bool isBranch, uint64_t InstSize, 549 MCInst &MI, const void *Decoder) { 550 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 551 // FIXME: Does it make sense for value to be negative? 552 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 553 /* Offset */ 0, InstSize); 554 } 555 556 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 557 /// referenced by a load instruction with the base register that is the Pc. 558 /// These can often be values in a literal pool near the Address of the 559 /// instruction. The Address of the instruction and its immediate Value are 560 /// used as a possible literal pool entry. The SymbolLookUp call back will 561 /// return the name of a symbol referenced by the literal pool's entry if 562 /// the referenced address is that of a symbol. Or it will return a pointer to 563 /// a literal 'C' string if the referenced address of the literal pool's entry 564 /// is an address into a section with 'C' string literals. 565 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 566 const void *Decoder) { 567 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 568 Dis->tryAddingPcLoadReferenceComment(Value, Address); 569 } 570 571 // Thumb1 instructions don't have explicit S bits. Rather, they 572 // implicitly set CPSR. Since it's not represented in the encoding, the 573 // auto-generated decoder won't inject the CPSR operand. We need to fix 574 // that as a post-pass. 575 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 576 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 577 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 578 MCInst::iterator I = MI.begin(); 579 for (unsigned i = 0; i < NumOps; ++i, ++I) { 580 if (I == MI.end()) break; 581 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 582 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 583 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 584 return; 585 } 586 } 587 588 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 589 } 590 591 // Most Thumb instructions don't have explicit predicates in the 592 // encoding, but rather get their predicates from IT context. We need 593 // to fix up the predicate operands using this context information as a 594 // post-pass. 595 MCDisassembler::DecodeStatus 596 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 597 MCDisassembler::DecodeStatus S = Success; 598 599 // A few instructions actually have predicates encoded in them. Don't 600 // try to overwrite it if we're seeing one of those. 601 switch (MI.getOpcode()) { 602 case ARM::tBcc: 603 case ARM::t2Bcc: 604 case ARM::tCBZ: 605 case ARM::tCBNZ: 606 case ARM::tCPS: 607 case ARM::t2CPS3p: 608 case ARM::t2CPS2p: 609 case ARM::t2CPS1p: 610 case ARM::tMOVSr: 611 case ARM::tSETEND: 612 // Some instructions (mostly conditional branches) are not 613 // allowed in IT blocks. 614 if (ITBlock.instrInITBlock()) 615 S = SoftFail; 616 else 617 return Success; 618 break; 619 case ARM::tB: 620 case ARM::t2B: 621 case ARM::t2TBB: 622 case ARM::t2TBH: 623 // Some instructions (mostly unconditional branches) can 624 // only appears at the end of, or outside of, an IT. 625 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 626 S = SoftFail; 627 break; 628 default: 629 break; 630 } 631 632 // If we're in an IT block, base the predicate on that. Otherwise, 633 // assume a predicate of AL. 634 unsigned CC; 635 CC = ITBlock.getITCC(); 636 if (CC == 0xF) 637 CC = ARMCC::AL; 638 if (ITBlock.instrInITBlock()) 639 ITBlock.advanceITState(); 640 641 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 642 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 643 MCInst::iterator I = MI.begin(); 644 for (unsigned i = 0; i < NumOps; ++i, ++I) { 645 if (I == MI.end()) break; 646 if (OpInfo[i].isPredicate()) { 647 I = MI.insert(I, MCOperand::CreateImm(CC)); 648 ++I; 649 if (CC == ARMCC::AL) 650 MI.insert(I, MCOperand::CreateReg(0)); 651 else 652 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 653 return S; 654 } 655 } 656 657 I = MI.insert(I, MCOperand::CreateImm(CC)); 658 ++I; 659 if (CC == ARMCC::AL) 660 MI.insert(I, MCOperand::CreateReg(0)); 661 else 662 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 663 664 return S; 665 } 666 667 // Thumb VFP instructions are a special case. Because we share their 668 // encodings between ARM and Thumb modes, and they are predicable in ARM 669 // mode, the auto-generated decoder will give them an (incorrect) 670 // predicate operand. We need to rewrite these operands based on the IT 671 // context as a post-pass. 672 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 673 unsigned CC; 674 CC = ITBlock.getITCC(); 675 if (ITBlock.instrInITBlock()) 676 ITBlock.advanceITState(); 677 678 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 679 MCInst::iterator I = MI.begin(); 680 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 681 for (unsigned i = 0; i < NumOps; ++i, ++I) { 682 if (OpInfo[i].isPredicate() ) { 683 I->setImm(CC); 684 ++I; 685 if (CC == ARMCC::AL) 686 I->setReg(0); 687 else 688 I->setReg(ARM::CPSR); 689 return; 690 } 691 } 692 } 693 694 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 695 ArrayRef<uint8_t> Bytes, 696 uint64_t Address, 697 raw_ostream &OS, 698 raw_ostream &CS) const { 699 CommentStream = &CS; 700 701 assert((STI.getFeatureBits() & ARM::ModeThumb) && 702 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 703 704 // We want to read exactly 2 bytes of data. 705 if (Bytes.size() < 2) { 706 Size = 0; 707 return MCDisassembler::Fail; 708 } 709 710 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 711 DecodeStatus Result = 712 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 713 if (Result != MCDisassembler::Fail) { 714 Size = 2; 715 Check(Result, AddThumbPredicate(MI)); 716 return Result; 717 } 718 719 MI.clear(); 720 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 721 STI); 722 if (Result) { 723 Size = 2; 724 bool InITBlock = ITBlock.instrInITBlock(); 725 Check(Result, AddThumbPredicate(MI)); 726 AddThumb1SBit(MI, InITBlock); 727 return Result; 728 } 729 730 MI.clear(); 731 Result = 732 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 733 if (Result != MCDisassembler::Fail) { 734 Size = 2; 735 736 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 737 // the Thumb predicate. 738 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 739 Result = MCDisassembler::SoftFail; 740 741 Check(Result, AddThumbPredicate(MI)); 742 743 // If we find an IT instruction, we need to parse its condition 744 // code and mask operands so that we can apply them correctly 745 // to the subsequent instructions. 746 if (MI.getOpcode() == ARM::t2IT) { 747 748 unsigned Firstcond = MI.getOperand(0).getImm(); 749 unsigned Mask = MI.getOperand(1).getImm(); 750 ITBlock.setITState(Firstcond, Mask); 751 } 752 753 return Result; 754 } 755 756 // We want to read exactly 4 bytes of data. 757 if (Bytes.size() < 4) { 758 Size = 0; 759 return MCDisassembler::Fail; 760 } 761 762 uint32_t Insn32 = 763 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 764 MI.clear(); 765 Result = 766 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 767 if (Result != MCDisassembler::Fail) { 768 Size = 4; 769 bool InITBlock = ITBlock.instrInITBlock(); 770 Check(Result, AddThumbPredicate(MI)); 771 AddThumb1SBit(MI, InITBlock); 772 return Result; 773 } 774 775 MI.clear(); 776 Result = 777 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 778 if (Result != MCDisassembler::Fail) { 779 Size = 4; 780 Check(Result, AddThumbPredicate(MI)); 781 return Result; 782 } 783 784 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 785 MI.clear(); 786 Result = 787 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 788 if (Result != MCDisassembler::Fail) { 789 Size = 4; 790 UpdateThumbVFPPredicate(MI); 791 return Result; 792 } 793 } 794 795 MI.clear(); 796 Result = 797 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 798 if (Result != MCDisassembler::Fail) { 799 Size = 4; 800 return Result; 801 } 802 803 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 804 MI.clear(); 805 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 806 STI); 807 if (Result != MCDisassembler::Fail) { 808 Size = 4; 809 Check(Result, AddThumbPredicate(MI)); 810 return Result; 811 } 812 } 813 814 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 815 MI.clear(); 816 uint32_t NEONLdStInsn = Insn32; 817 NEONLdStInsn &= 0xF0FFFFFF; 818 NEONLdStInsn |= 0x04000000; 819 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 820 Address, this, STI); 821 if (Result != MCDisassembler::Fail) { 822 Size = 4; 823 Check(Result, AddThumbPredicate(MI)); 824 return Result; 825 } 826 } 827 828 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 829 MI.clear(); 830 uint32_t NEONDataInsn = Insn32; 831 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 832 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 833 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 834 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 835 Address, this, STI); 836 if (Result != MCDisassembler::Fail) { 837 Size = 4; 838 Check(Result, AddThumbPredicate(MI)); 839 return Result; 840 } 841 842 MI.clear(); 843 uint32_t NEONCryptoInsn = Insn32; 844 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 845 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 846 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 847 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 848 Address, this, STI); 849 if (Result != MCDisassembler::Fail) { 850 Size = 4; 851 return Result; 852 } 853 854 MI.clear(); 855 uint32_t NEONv8Insn = Insn32; 856 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 857 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 858 this, STI); 859 if (Result != MCDisassembler::Fail) { 860 Size = 4; 861 return Result; 862 } 863 } 864 865 MI.clear(); 866 Size = 0; 867 return MCDisassembler::Fail; 868 } 869 870 871 extern "C" void LLVMInitializeARMDisassembler() { 872 TargetRegistry::RegisterMCDisassembler(TheARMLETarget, 873 createARMDisassembler); 874 TargetRegistry::RegisterMCDisassembler(TheARMBETarget, 875 createARMDisassembler); 876 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget, 877 createThumbDisassembler); 878 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget, 879 createThumbDisassembler); 880 } 881 882 static const uint16_t GPRDecoderTable[] = { 883 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 884 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 885 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 886 ARM::R12, ARM::SP, ARM::LR, ARM::PC 887 }; 888 889 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 890 uint64_t Address, const void *Decoder) { 891 if (RegNo > 15) 892 return MCDisassembler::Fail; 893 894 unsigned Register = GPRDecoderTable[RegNo]; 895 Inst.addOperand(MCOperand::CreateReg(Register)); 896 return MCDisassembler::Success; 897 } 898 899 static DecodeStatus 900 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 901 uint64_t Address, const void *Decoder) { 902 DecodeStatus S = MCDisassembler::Success; 903 904 if (RegNo == 15) 905 S = MCDisassembler::SoftFail; 906 907 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 908 909 return S; 910 } 911 912 static DecodeStatus 913 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 914 uint64_t Address, const void *Decoder) { 915 DecodeStatus S = MCDisassembler::Success; 916 917 if (RegNo == 15) 918 { 919 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 920 return MCDisassembler::Success; 921 } 922 923 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 924 return S; 925 } 926 927 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 928 uint64_t Address, const void *Decoder) { 929 if (RegNo > 7) 930 return MCDisassembler::Fail; 931 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 932 } 933 934 static const uint16_t GPRPairDecoderTable[] = { 935 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 936 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 937 }; 938 939 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 940 uint64_t Address, const void *Decoder) { 941 DecodeStatus S = MCDisassembler::Success; 942 943 if (RegNo > 13) 944 return MCDisassembler::Fail; 945 946 if ((RegNo & 1) || RegNo == 0xe) 947 S = MCDisassembler::SoftFail; 948 949 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 950 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 951 return S; 952 } 953 954 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 955 uint64_t Address, const void *Decoder) { 956 unsigned Register = 0; 957 switch (RegNo) { 958 case 0: 959 Register = ARM::R0; 960 break; 961 case 1: 962 Register = ARM::R1; 963 break; 964 case 2: 965 Register = ARM::R2; 966 break; 967 case 3: 968 Register = ARM::R3; 969 break; 970 case 9: 971 Register = ARM::R9; 972 break; 973 case 12: 974 Register = ARM::R12; 975 break; 976 default: 977 return MCDisassembler::Fail; 978 } 979 980 Inst.addOperand(MCOperand::CreateReg(Register)); 981 return MCDisassembler::Success; 982 } 983 984 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 985 uint64_t Address, const void *Decoder) { 986 DecodeStatus S = MCDisassembler::Success; 987 if (RegNo == 13 || RegNo == 15) 988 S = MCDisassembler::SoftFail; 989 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 990 return S; 991 } 992 993 static const uint16_t SPRDecoderTable[] = { 994 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 995 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 996 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 997 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 998 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 999 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1000 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1001 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1002 }; 1003 1004 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1005 uint64_t Address, const void *Decoder) { 1006 if (RegNo > 31) 1007 return MCDisassembler::Fail; 1008 1009 unsigned Register = SPRDecoderTable[RegNo]; 1010 Inst.addOperand(MCOperand::CreateReg(Register)); 1011 return MCDisassembler::Success; 1012 } 1013 1014 static const uint16_t DPRDecoderTable[] = { 1015 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1016 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1017 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1018 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1019 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1020 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1021 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1022 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1023 }; 1024 1025 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1026 uint64_t Address, const void *Decoder) { 1027 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 1028 .getFeatureBits(); 1029 bool hasD16 = featureBits & ARM::FeatureD16; 1030 1031 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1032 return MCDisassembler::Fail; 1033 1034 unsigned Register = DPRDecoderTable[RegNo]; 1035 Inst.addOperand(MCOperand::CreateReg(Register)); 1036 return MCDisassembler::Success; 1037 } 1038 1039 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1040 uint64_t Address, const void *Decoder) { 1041 if (RegNo > 7) 1042 return MCDisassembler::Fail; 1043 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1044 } 1045 1046 static DecodeStatus 1047 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1048 uint64_t Address, const void *Decoder) { 1049 if (RegNo > 15) 1050 return MCDisassembler::Fail; 1051 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1052 } 1053 1054 static const uint16_t QPRDecoderTable[] = { 1055 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1056 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1057 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1058 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1059 }; 1060 1061 1062 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1063 uint64_t Address, const void *Decoder) { 1064 if (RegNo > 31 || (RegNo & 1) != 0) 1065 return MCDisassembler::Fail; 1066 RegNo >>= 1; 1067 1068 unsigned Register = QPRDecoderTable[RegNo]; 1069 Inst.addOperand(MCOperand::CreateReg(Register)); 1070 return MCDisassembler::Success; 1071 } 1072 1073 static const uint16_t DPairDecoderTable[] = { 1074 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1075 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1076 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1077 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1078 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1079 ARM::Q15 1080 }; 1081 1082 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1083 uint64_t Address, const void *Decoder) { 1084 if (RegNo > 30) 1085 return MCDisassembler::Fail; 1086 1087 unsigned Register = DPairDecoderTable[RegNo]; 1088 Inst.addOperand(MCOperand::CreateReg(Register)); 1089 return MCDisassembler::Success; 1090 } 1091 1092 static const uint16_t DPairSpacedDecoderTable[] = { 1093 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1094 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1095 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1096 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1097 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1098 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1099 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1100 ARM::D28_D30, ARM::D29_D31 1101 }; 1102 1103 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1104 unsigned RegNo, 1105 uint64_t Address, 1106 const void *Decoder) { 1107 if (RegNo > 29) 1108 return MCDisassembler::Fail; 1109 1110 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1111 Inst.addOperand(MCOperand::CreateReg(Register)); 1112 return MCDisassembler::Success; 1113 } 1114 1115 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1116 uint64_t Address, const void *Decoder) { 1117 if (Val == 0xF) return MCDisassembler::Fail; 1118 // AL predicate is not allowed on Thumb1 branches. 1119 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1120 return MCDisassembler::Fail; 1121 Inst.addOperand(MCOperand::CreateImm(Val)); 1122 if (Val == ARMCC::AL) { 1123 Inst.addOperand(MCOperand::CreateReg(0)); 1124 } else 1125 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1126 return MCDisassembler::Success; 1127 } 1128 1129 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1130 uint64_t Address, const void *Decoder) { 1131 if (Val) 1132 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1133 else 1134 Inst.addOperand(MCOperand::CreateReg(0)); 1135 return MCDisassembler::Success; 1136 } 1137 1138 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val, 1139 uint64_t Address, const void *Decoder) { 1140 uint32_t imm = Val & 0xFF; 1141 uint32_t rot = (Val & 0xF00) >> 7; 1142 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F)); 1143 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 1144 return MCDisassembler::Success; 1145 } 1146 1147 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1148 uint64_t Address, const void *Decoder) { 1149 DecodeStatus S = MCDisassembler::Success; 1150 1151 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1152 unsigned type = fieldFromInstruction(Val, 5, 2); 1153 unsigned imm = fieldFromInstruction(Val, 7, 5); 1154 1155 // Register-immediate 1156 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1157 return MCDisassembler::Fail; 1158 1159 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1160 switch (type) { 1161 case 0: 1162 Shift = ARM_AM::lsl; 1163 break; 1164 case 1: 1165 Shift = ARM_AM::lsr; 1166 break; 1167 case 2: 1168 Shift = ARM_AM::asr; 1169 break; 1170 case 3: 1171 Shift = ARM_AM::ror; 1172 break; 1173 } 1174 1175 if (Shift == ARM_AM::ror && imm == 0) 1176 Shift = ARM_AM::rrx; 1177 1178 unsigned Op = Shift | (imm << 3); 1179 Inst.addOperand(MCOperand::CreateImm(Op)); 1180 1181 return S; 1182 } 1183 1184 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1185 uint64_t Address, const void *Decoder) { 1186 DecodeStatus S = MCDisassembler::Success; 1187 1188 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1189 unsigned type = fieldFromInstruction(Val, 5, 2); 1190 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1191 1192 // Register-register 1193 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1194 return MCDisassembler::Fail; 1195 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1196 return MCDisassembler::Fail; 1197 1198 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1199 switch (type) { 1200 case 0: 1201 Shift = ARM_AM::lsl; 1202 break; 1203 case 1: 1204 Shift = ARM_AM::lsr; 1205 break; 1206 case 2: 1207 Shift = ARM_AM::asr; 1208 break; 1209 case 3: 1210 Shift = ARM_AM::ror; 1211 break; 1212 } 1213 1214 Inst.addOperand(MCOperand::CreateImm(Shift)); 1215 1216 return S; 1217 } 1218 1219 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1220 uint64_t Address, const void *Decoder) { 1221 DecodeStatus S = MCDisassembler::Success; 1222 1223 bool NeedDisjointWriteback = false; 1224 unsigned WritebackReg = 0; 1225 switch (Inst.getOpcode()) { 1226 default: 1227 break; 1228 case ARM::LDMIA_UPD: 1229 case ARM::LDMDB_UPD: 1230 case ARM::LDMIB_UPD: 1231 case ARM::LDMDA_UPD: 1232 case ARM::t2LDMIA_UPD: 1233 case ARM::t2LDMDB_UPD: 1234 case ARM::t2STMIA_UPD: 1235 case ARM::t2STMDB_UPD: 1236 NeedDisjointWriteback = true; 1237 WritebackReg = Inst.getOperand(0).getReg(); 1238 break; 1239 } 1240 1241 // Empty register lists are not allowed. 1242 if (Val == 0) return MCDisassembler::Fail; 1243 for (unsigned i = 0; i < 16; ++i) { 1244 if (Val & (1 << i)) { 1245 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1246 return MCDisassembler::Fail; 1247 // Writeback not allowed if Rn is in the target list. 1248 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1249 Check(S, MCDisassembler::SoftFail); 1250 } 1251 } 1252 1253 return S; 1254 } 1255 1256 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1257 uint64_t Address, const void *Decoder) { 1258 DecodeStatus S = MCDisassembler::Success; 1259 1260 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1261 unsigned regs = fieldFromInstruction(Val, 0, 8); 1262 1263 // In case of unpredictable encoding, tweak the operands. 1264 if (regs == 0 || (Vd + regs) > 32) { 1265 regs = Vd + regs > 32 ? 32 - Vd : regs; 1266 regs = std::max( 1u, regs); 1267 S = MCDisassembler::SoftFail; 1268 } 1269 1270 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1271 return MCDisassembler::Fail; 1272 for (unsigned i = 0; i < (regs - 1); ++i) { 1273 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1274 return MCDisassembler::Fail; 1275 } 1276 1277 return S; 1278 } 1279 1280 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1281 uint64_t Address, const void *Decoder) { 1282 DecodeStatus S = MCDisassembler::Success; 1283 1284 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1285 unsigned regs = fieldFromInstruction(Val, 1, 7); 1286 1287 // In case of unpredictable encoding, tweak the operands. 1288 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1289 regs = Vd + regs > 32 ? 32 - Vd : regs; 1290 regs = std::max( 1u, regs); 1291 regs = std::min(16u, regs); 1292 S = MCDisassembler::SoftFail; 1293 } 1294 1295 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1296 return MCDisassembler::Fail; 1297 for (unsigned i = 0; i < (regs - 1); ++i) { 1298 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1299 return MCDisassembler::Fail; 1300 } 1301 1302 return S; 1303 } 1304 1305 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1306 uint64_t Address, const void *Decoder) { 1307 // This operand encodes a mask of contiguous zeros between a specified MSB 1308 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1309 // the mask of all bits LSB-and-lower, and then xor them to create 1310 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1311 // create the final mask. 1312 unsigned msb = fieldFromInstruction(Val, 5, 5); 1313 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1314 1315 DecodeStatus S = MCDisassembler::Success; 1316 if (lsb > msb) { 1317 Check(S, MCDisassembler::SoftFail); 1318 // The check above will cause the warning for the "potentially undefined 1319 // instruction encoding" but we can't build a bad MCOperand value here 1320 // with a lsb > msb or else printing the MCInst will cause a crash. 1321 lsb = msb; 1322 } 1323 1324 uint32_t msb_mask = 0xFFFFFFFF; 1325 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1326 uint32_t lsb_mask = (1U << lsb) - 1; 1327 1328 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1329 return S; 1330 } 1331 1332 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1333 uint64_t Address, const void *Decoder) { 1334 DecodeStatus S = MCDisassembler::Success; 1335 1336 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1337 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1338 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1339 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1340 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1341 unsigned U = fieldFromInstruction(Insn, 23, 1); 1342 1343 switch (Inst.getOpcode()) { 1344 case ARM::LDC_OFFSET: 1345 case ARM::LDC_PRE: 1346 case ARM::LDC_POST: 1347 case ARM::LDC_OPTION: 1348 case ARM::LDCL_OFFSET: 1349 case ARM::LDCL_PRE: 1350 case ARM::LDCL_POST: 1351 case ARM::LDCL_OPTION: 1352 case ARM::STC_OFFSET: 1353 case ARM::STC_PRE: 1354 case ARM::STC_POST: 1355 case ARM::STC_OPTION: 1356 case ARM::STCL_OFFSET: 1357 case ARM::STCL_PRE: 1358 case ARM::STCL_POST: 1359 case ARM::STCL_OPTION: 1360 case ARM::t2LDC_OFFSET: 1361 case ARM::t2LDC_PRE: 1362 case ARM::t2LDC_POST: 1363 case ARM::t2LDC_OPTION: 1364 case ARM::t2LDCL_OFFSET: 1365 case ARM::t2LDCL_PRE: 1366 case ARM::t2LDCL_POST: 1367 case ARM::t2LDCL_OPTION: 1368 case ARM::t2STC_OFFSET: 1369 case ARM::t2STC_PRE: 1370 case ARM::t2STC_POST: 1371 case ARM::t2STC_OPTION: 1372 case ARM::t2STCL_OFFSET: 1373 case ARM::t2STCL_PRE: 1374 case ARM::t2STCL_POST: 1375 case ARM::t2STCL_OPTION: 1376 if (coproc == 0xA || coproc == 0xB) 1377 return MCDisassembler::Fail; 1378 break; 1379 default: 1380 break; 1381 } 1382 1383 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 1384 .getFeatureBits(); 1385 if ((featureBits & ARM::HasV8Ops) && (coproc != 14)) 1386 return MCDisassembler::Fail; 1387 1388 Inst.addOperand(MCOperand::CreateImm(coproc)); 1389 Inst.addOperand(MCOperand::CreateImm(CRd)); 1390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1391 return MCDisassembler::Fail; 1392 1393 switch (Inst.getOpcode()) { 1394 case ARM::t2LDC2_OFFSET: 1395 case ARM::t2LDC2L_OFFSET: 1396 case ARM::t2LDC2_PRE: 1397 case ARM::t2LDC2L_PRE: 1398 case ARM::t2STC2_OFFSET: 1399 case ARM::t2STC2L_OFFSET: 1400 case ARM::t2STC2_PRE: 1401 case ARM::t2STC2L_PRE: 1402 case ARM::LDC2_OFFSET: 1403 case ARM::LDC2L_OFFSET: 1404 case ARM::LDC2_PRE: 1405 case ARM::LDC2L_PRE: 1406 case ARM::STC2_OFFSET: 1407 case ARM::STC2L_OFFSET: 1408 case ARM::STC2_PRE: 1409 case ARM::STC2L_PRE: 1410 case ARM::t2LDC_OFFSET: 1411 case ARM::t2LDCL_OFFSET: 1412 case ARM::t2LDC_PRE: 1413 case ARM::t2LDCL_PRE: 1414 case ARM::t2STC_OFFSET: 1415 case ARM::t2STCL_OFFSET: 1416 case ARM::t2STC_PRE: 1417 case ARM::t2STCL_PRE: 1418 case ARM::LDC_OFFSET: 1419 case ARM::LDCL_OFFSET: 1420 case ARM::LDC_PRE: 1421 case ARM::LDCL_PRE: 1422 case ARM::STC_OFFSET: 1423 case ARM::STCL_OFFSET: 1424 case ARM::STC_PRE: 1425 case ARM::STCL_PRE: 1426 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1427 Inst.addOperand(MCOperand::CreateImm(imm)); 1428 break; 1429 case ARM::t2LDC2_POST: 1430 case ARM::t2LDC2L_POST: 1431 case ARM::t2STC2_POST: 1432 case ARM::t2STC2L_POST: 1433 case ARM::LDC2_POST: 1434 case ARM::LDC2L_POST: 1435 case ARM::STC2_POST: 1436 case ARM::STC2L_POST: 1437 case ARM::t2LDC_POST: 1438 case ARM::t2LDCL_POST: 1439 case ARM::t2STC_POST: 1440 case ARM::t2STCL_POST: 1441 case ARM::LDC_POST: 1442 case ARM::LDCL_POST: 1443 case ARM::STC_POST: 1444 case ARM::STCL_POST: 1445 imm |= U << 8; 1446 // fall through. 1447 default: 1448 // The 'option' variant doesn't encode 'U' in the immediate since 1449 // the immediate is unsigned [0,255]. 1450 Inst.addOperand(MCOperand::CreateImm(imm)); 1451 break; 1452 } 1453 1454 switch (Inst.getOpcode()) { 1455 case ARM::LDC_OFFSET: 1456 case ARM::LDC_PRE: 1457 case ARM::LDC_POST: 1458 case ARM::LDC_OPTION: 1459 case ARM::LDCL_OFFSET: 1460 case ARM::LDCL_PRE: 1461 case ARM::LDCL_POST: 1462 case ARM::LDCL_OPTION: 1463 case ARM::STC_OFFSET: 1464 case ARM::STC_PRE: 1465 case ARM::STC_POST: 1466 case ARM::STC_OPTION: 1467 case ARM::STCL_OFFSET: 1468 case ARM::STCL_PRE: 1469 case ARM::STCL_POST: 1470 case ARM::STCL_OPTION: 1471 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1472 return MCDisassembler::Fail; 1473 break; 1474 default: 1475 break; 1476 } 1477 1478 return S; 1479 } 1480 1481 static DecodeStatus 1482 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1483 uint64_t Address, const void *Decoder) { 1484 DecodeStatus S = MCDisassembler::Success; 1485 1486 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1487 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1488 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1489 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1490 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1491 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1492 unsigned P = fieldFromInstruction(Insn, 24, 1); 1493 unsigned W = fieldFromInstruction(Insn, 21, 1); 1494 1495 // On stores, the writeback operand precedes Rt. 1496 switch (Inst.getOpcode()) { 1497 case ARM::STR_POST_IMM: 1498 case ARM::STR_POST_REG: 1499 case ARM::STRB_POST_IMM: 1500 case ARM::STRB_POST_REG: 1501 case ARM::STRT_POST_REG: 1502 case ARM::STRT_POST_IMM: 1503 case ARM::STRBT_POST_REG: 1504 case ARM::STRBT_POST_IMM: 1505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1506 return MCDisassembler::Fail; 1507 break; 1508 default: 1509 break; 1510 } 1511 1512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1513 return MCDisassembler::Fail; 1514 1515 // On loads, the writeback operand comes after Rt. 1516 switch (Inst.getOpcode()) { 1517 case ARM::LDR_POST_IMM: 1518 case ARM::LDR_POST_REG: 1519 case ARM::LDRB_POST_IMM: 1520 case ARM::LDRB_POST_REG: 1521 case ARM::LDRBT_POST_REG: 1522 case ARM::LDRBT_POST_IMM: 1523 case ARM::LDRT_POST_REG: 1524 case ARM::LDRT_POST_IMM: 1525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1526 return MCDisassembler::Fail; 1527 break; 1528 default: 1529 break; 1530 } 1531 1532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1533 return MCDisassembler::Fail; 1534 1535 ARM_AM::AddrOpc Op = ARM_AM::add; 1536 if (!fieldFromInstruction(Insn, 23, 1)) 1537 Op = ARM_AM::sub; 1538 1539 bool writeback = (P == 0) || (W == 1); 1540 unsigned idx_mode = 0; 1541 if (P && writeback) 1542 idx_mode = ARMII::IndexModePre; 1543 else if (!P && writeback) 1544 idx_mode = ARMII::IndexModePost; 1545 1546 if (writeback && (Rn == 15 || Rn == Rt)) 1547 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1548 1549 if (reg) { 1550 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1551 return MCDisassembler::Fail; 1552 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1553 switch( fieldFromInstruction(Insn, 5, 2)) { 1554 case 0: 1555 Opc = ARM_AM::lsl; 1556 break; 1557 case 1: 1558 Opc = ARM_AM::lsr; 1559 break; 1560 case 2: 1561 Opc = ARM_AM::asr; 1562 break; 1563 case 3: 1564 Opc = ARM_AM::ror; 1565 break; 1566 default: 1567 return MCDisassembler::Fail; 1568 } 1569 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1570 if (Opc == ARM_AM::ror && amt == 0) 1571 Opc = ARM_AM::rrx; 1572 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1573 1574 Inst.addOperand(MCOperand::CreateImm(imm)); 1575 } else { 1576 Inst.addOperand(MCOperand::CreateReg(0)); 1577 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1578 Inst.addOperand(MCOperand::CreateImm(tmp)); 1579 } 1580 1581 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1582 return MCDisassembler::Fail; 1583 1584 return S; 1585 } 1586 1587 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1588 uint64_t Address, const void *Decoder) { 1589 DecodeStatus S = MCDisassembler::Success; 1590 1591 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1592 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1593 unsigned type = fieldFromInstruction(Val, 5, 2); 1594 unsigned imm = fieldFromInstruction(Val, 7, 5); 1595 unsigned U = fieldFromInstruction(Val, 12, 1); 1596 1597 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1598 switch (type) { 1599 case 0: 1600 ShOp = ARM_AM::lsl; 1601 break; 1602 case 1: 1603 ShOp = ARM_AM::lsr; 1604 break; 1605 case 2: 1606 ShOp = ARM_AM::asr; 1607 break; 1608 case 3: 1609 ShOp = ARM_AM::ror; 1610 break; 1611 } 1612 1613 if (ShOp == ARM_AM::ror && imm == 0) 1614 ShOp = ARM_AM::rrx; 1615 1616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1617 return MCDisassembler::Fail; 1618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1619 return MCDisassembler::Fail; 1620 unsigned shift; 1621 if (U) 1622 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1623 else 1624 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1625 Inst.addOperand(MCOperand::CreateImm(shift)); 1626 1627 return S; 1628 } 1629 1630 static DecodeStatus 1631 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1632 uint64_t Address, const void *Decoder) { 1633 DecodeStatus S = MCDisassembler::Success; 1634 1635 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1636 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1637 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1638 unsigned type = fieldFromInstruction(Insn, 22, 1); 1639 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1640 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1641 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1642 unsigned W = fieldFromInstruction(Insn, 21, 1); 1643 unsigned P = fieldFromInstruction(Insn, 24, 1); 1644 unsigned Rt2 = Rt + 1; 1645 1646 bool writeback = (W == 1) | (P == 0); 1647 1648 // For {LD,ST}RD, Rt must be even, else undefined. 1649 switch (Inst.getOpcode()) { 1650 case ARM::STRD: 1651 case ARM::STRD_PRE: 1652 case ARM::STRD_POST: 1653 case ARM::LDRD: 1654 case ARM::LDRD_PRE: 1655 case ARM::LDRD_POST: 1656 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1657 break; 1658 default: 1659 break; 1660 } 1661 switch (Inst.getOpcode()) { 1662 case ARM::STRD: 1663 case ARM::STRD_PRE: 1664 case ARM::STRD_POST: 1665 if (P == 0 && W == 1) 1666 S = MCDisassembler::SoftFail; 1667 1668 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1669 S = MCDisassembler::SoftFail; 1670 if (type && Rm == 15) 1671 S = MCDisassembler::SoftFail; 1672 if (Rt2 == 15) 1673 S = MCDisassembler::SoftFail; 1674 if (!type && fieldFromInstruction(Insn, 8, 4)) 1675 S = MCDisassembler::SoftFail; 1676 break; 1677 case ARM::STRH: 1678 case ARM::STRH_PRE: 1679 case ARM::STRH_POST: 1680 if (Rt == 15) 1681 S = MCDisassembler::SoftFail; 1682 if (writeback && (Rn == 15 || Rn == Rt)) 1683 S = MCDisassembler::SoftFail; 1684 if (!type && Rm == 15) 1685 S = MCDisassembler::SoftFail; 1686 break; 1687 case ARM::LDRD: 1688 case ARM::LDRD_PRE: 1689 case ARM::LDRD_POST: 1690 if (type && Rn == 15){ 1691 if (Rt2 == 15) 1692 S = MCDisassembler::SoftFail; 1693 break; 1694 } 1695 if (P == 0 && W == 1) 1696 S = MCDisassembler::SoftFail; 1697 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1698 S = MCDisassembler::SoftFail; 1699 if (!type && writeback && Rn == 15) 1700 S = MCDisassembler::SoftFail; 1701 if (writeback && (Rn == Rt || Rn == Rt2)) 1702 S = MCDisassembler::SoftFail; 1703 break; 1704 case ARM::LDRH: 1705 case ARM::LDRH_PRE: 1706 case ARM::LDRH_POST: 1707 if (type && Rn == 15){ 1708 if (Rt == 15) 1709 S = MCDisassembler::SoftFail; 1710 break; 1711 } 1712 if (Rt == 15) 1713 S = MCDisassembler::SoftFail; 1714 if (!type && Rm == 15) 1715 S = MCDisassembler::SoftFail; 1716 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1717 S = MCDisassembler::SoftFail; 1718 break; 1719 case ARM::LDRSH: 1720 case ARM::LDRSH_PRE: 1721 case ARM::LDRSH_POST: 1722 case ARM::LDRSB: 1723 case ARM::LDRSB_PRE: 1724 case ARM::LDRSB_POST: 1725 if (type && Rn == 15){ 1726 if (Rt == 15) 1727 S = MCDisassembler::SoftFail; 1728 break; 1729 } 1730 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1731 S = MCDisassembler::SoftFail; 1732 if (!type && (Rt == 15 || Rm == 15)) 1733 S = MCDisassembler::SoftFail; 1734 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1735 S = MCDisassembler::SoftFail; 1736 break; 1737 default: 1738 break; 1739 } 1740 1741 if (writeback) { // Writeback 1742 if (P) 1743 U |= ARMII::IndexModePre << 9; 1744 else 1745 U |= ARMII::IndexModePost << 9; 1746 1747 // On stores, the writeback operand precedes Rt. 1748 switch (Inst.getOpcode()) { 1749 case ARM::STRD: 1750 case ARM::STRD_PRE: 1751 case ARM::STRD_POST: 1752 case ARM::STRH: 1753 case ARM::STRH_PRE: 1754 case ARM::STRH_POST: 1755 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1756 return MCDisassembler::Fail; 1757 break; 1758 default: 1759 break; 1760 } 1761 } 1762 1763 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1764 return MCDisassembler::Fail; 1765 switch (Inst.getOpcode()) { 1766 case ARM::STRD: 1767 case ARM::STRD_PRE: 1768 case ARM::STRD_POST: 1769 case ARM::LDRD: 1770 case ARM::LDRD_PRE: 1771 case ARM::LDRD_POST: 1772 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1773 return MCDisassembler::Fail; 1774 break; 1775 default: 1776 break; 1777 } 1778 1779 if (writeback) { 1780 // On loads, the writeback operand comes after Rt. 1781 switch (Inst.getOpcode()) { 1782 case ARM::LDRD: 1783 case ARM::LDRD_PRE: 1784 case ARM::LDRD_POST: 1785 case ARM::LDRH: 1786 case ARM::LDRH_PRE: 1787 case ARM::LDRH_POST: 1788 case ARM::LDRSH: 1789 case ARM::LDRSH_PRE: 1790 case ARM::LDRSH_POST: 1791 case ARM::LDRSB: 1792 case ARM::LDRSB_PRE: 1793 case ARM::LDRSB_POST: 1794 case ARM::LDRHTr: 1795 case ARM::LDRSBTr: 1796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1797 return MCDisassembler::Fail; 1798 break; 1799 default: 1800 break; 1801 } 1802 } 1803 1804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1805 return MCDisassembler::Fail; 1806 1807 if (type) { 1808 Inst.addOperand(MCOperand::CreateReg(0)); 1809 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1810 } else { 1811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1812 return MCDisassembler::Fail; 1813 Inst.addOperand(MCOperand::CreateImm(U)); 1814 } 1815 1816 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1817 return MCDisassembler::Fail; 1818 1819 return S; 1820 } 1821 1822 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1823 uint64_t Address, const void *Decoder) { 1824 DecodeStatus S = MCDisassembler::Success; 1825 1826 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1827 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1828 1829 switch (mode) { 1830 case 0: 1831 mode = ARM_AM::da; 1832 break; 1833 case 1: 1834 mode = ARM_AM::ia; 1835 break; 1836 case 2: 1837 mode = ARM_AM::db; 1838 break; 1839 case 3: 1840 mode = ARM_AM::ib; 1841 break; 1842 } 1843 1844 Inst.addOperand(MCOperand::CreateImm(mode)); 1845 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1846 return MCDisassembler::Fail; 1847 1848 return S; 1849 } 1850 1851 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1852 uint64_t Address, const void *Decoder) { 1853 DecodeStatus S = MCDisassembler::Success; 1854 1855 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1856 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1857 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1858 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1859 1860 if (pred == 0xF) 1861 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1862 1863 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1864 return MCDisassembler::Fail; 1865 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1866 return MCDisassembler::Fail; 1867 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1868 return MCDisassembler::Fail; 1869 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1870 return MCDisassembler::Fail; 1871 return S; 1872 } 1873 1874 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1875 unsigned Insn, 1876 uint64_t Address, const void *Decoder) { 1877 DecodeStatus S = MCDisassembler::Success; 1878 1879 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1880 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1881 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1882 1883 if (pred == 0xF) { 1884 // Ambiguous with RFE and SRS 1885 switch (Inst.getOpcode()) { 1886 case ARM::LDMDA: 1887 Inst.setOpcode(ARM::RFEDA); 1888 break; 1889 case ARM::LDMDA_UPD: 1890 Inst.setOpcode(ARM::RFEDA_UPD); 1891 break; 1892 case ARM::LDMDB: 1893 Inst.setOpcode(ARM::RFEDB); 1894 break; 1895 case ARM::LDMDB_UPD: 1896 Inst.setOpcode(ARM::RFEDB_UPD); 1897 break; 1898 case ARM::LDMIA: 1899 Inst.setOpcode(ARM::RFEIA); 1900 break; 1901 case ARM::LDMIA_UPD: 1902 Inst.setOpcode(ARM::RFEIA_UPD); 1903 break; 1904 case ARM::LDMIB: 1905 Inst.setOpcode(ARM::RFEIB); 1906 break; 1907 case ARM::LDMIB_UPD: 1908 Inst.setOpcode(ARM::RFEIB_UPD); 1909 break; 1910 case ARM::STMDA: 1911 Inst.setOpcode(ARM::SRSDA); 1912 break; 1913 case ARM::STMDA_UPD: 1914 Inst.setOpcode(ARM::SRSDA_UPD); 1915 break; 1916 case ARM::STMDB: 1917 Inst.setOpcode(ARM::SRSDB); 1918 break; 1919 case ARM::STMDB_UPD: 1920 Inst.setOpcode(ARM::SRSDB_UPD); 1921 break; 1922 case ARM::STMIA: 1923 Inst.setOpcode(ARM::SRSIA); 1924 break; 1925 case ARM::STMIA_UPD: 1926 Inst.setOpcode(ARM::SRSIA_UPD); 1927 break; 1928 case ARM::STMIB: 1929 Inst.setOpcode(ARM::SRSIB); 1930 break; 1931 case ARM::STMIB_UPD: 1932 Inst.setOpcode(ARM::SRSIB_UPD); 1933 break; 1934 default: 1935 return MCDisassembler::Fail; 1936 } 1937 1938 // For stores (which become SRS's, the only operand is the mode. 1939 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1940 // Check SRS encoding constraints 1941 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1942 fieldFromInstruction(Insn, 20, 1) == 0)) 1943 return MCDisassembler::Fail; 1944 1945 Inst.addOperand( 1946 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1947 return S; 1948 } 1949 1950 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1951 } 1952 1953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1954 return MCDisassembler::Fail; 1955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1956 return MCDisassembler::Fail; // Tied 1957 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1958 return MCDisassembler::Fail; 1959 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1960 return MCDisassembler::Fail; 1961 1962 return S; 1963 } 1964 1965 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1966 uint64_t Address, const void *Decoder) { 1967 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1968 unsigned M = fieldFromInstruction(Insn, 17, 1); 1969 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1970 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1971 1972 DecodeStatus S = MCDisassembler::Success; 1973 1974 // This decoder is called from multiple location that do not check 1975 // the full encoding is valid before they do. 1976 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1977 fieldFromInstruction(Insn, 16, 1) != 0 || 1978 fieldFromInstruction(Insn, 20, 8) != 0x10) 1979 return MCDisassembler::Fail; 1980 1981 // imod == '01' --> UNPREDICTABLE 1982 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1983 // return failure here. The '01' imod value is unprintable, so there's 1984 // nothing useful we could do even if we returned UNPREDICTABLE. 1985 1986 if (imod == 1) return MCDisassembler::Fail; 1987 1988 if (imod && M) { 1989 Inst.setOpcode(ARM::CPS3p); 1990 Inst.addOperand(MCOperand::CreateImm(imod)); 1991 Inst.addOperand(MCOperand::CreateImm(iflags)); 1992 Inst.addOperand(MCOperand::CreateImm(mode)); 1993 } else if (imod && !M) { 1994 Inst.setOpcode(ARM::CPS2p); 1995 Inst.addOperand(MCOperand::CreateImm(imod)); 1996 Inst.addOperand(MCOperand::CreateImm(iflags)); 1997 if (mode) S = MCDisassembler::SoftFail; 1998 } else if (!imod && M) { 1999 Inst.setOpcode(ARM::CPS1p); 2000 Inst.addOperand(MCOperand::CreateImm(mode)); 2001 if (iflags) S = MCDisassembler::SoftFail; 2002 } else { 2003 // imod == '00' && M == '0' --> UNPREDICTABLE 2004 Inst.setOpcode(ARM::CPS1p); 2005 Inst.addOperand(MCOperand::CreateImm(mode)); 2006 S = MCDisassembler::SoftFail; 2007 } 2008 2009 return S; 2010 } 2011 2012 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2013 uint64_t Address, const void *Decoder) { 2014 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2015 unsigned M = fieldFromInstruction(Insn, 8, 1); 2016 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2017 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2018 2019 DecodeStatus S = MCDisassembler::Success; 2020 2021 // imod == '01' --> UNPREDICTABLE 2022 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2023 // return failure here. The '01' imod value is unprintable, so there's 2024 // nothing useful we could do even if we returned UNPREDICTABLE. 2025 2026 if (imod == 1) return MCDisassembler::Fail; 2027 2028 if (imod && M) { 2029 Inst.setOpcode(ARM::t2CPS3p); 2030 Inst.addOperand(MCOperand::CreateImm(imod)); 2031 Inst.addOperand(MCOperand::CreateImm(iflags)); 2032 Inst.addOperand(MCOperand::CreateImm(mode)); 2033 } else if (imod && !M) { 2034 Inst.setOpcode(ARM::t2CPS2p); 2035 Inst.addOperand(MCOperand::CreateImm(imod)); 2036 Inst.addOperand(MCOperand::CreateImm(iflags)); 2037 if (mode) S = MCDisassembler::SoftFail; 2038 } else if (!imod && M) { 2039 Inst.setOpcode(ARM::t2CPS1p); 2040 Inst.addOperand(MCOperand::CreateImm(mode)); 2041 if (iflags) S = MCDisassembler::SoftFail; 2042 } else { 2043 // imod == '00' && M == '0' --> this is a HINT instruction 2044 int imm = fieldFromInstruction(Insn, 0, 8); 2045 // HINT are defined only for immediate in [0..4] 2046 if(imm > 4) return MCDisassembler::Fail; 2047 Inst.setOpcode(ARM::t2HINT); 2048 Inst.addOperand(MCOperand::CreateImm(imm)); 2049 } 2050 2051 return S; 2052 } 2053 2054 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2055 uint64_t Address, const void *Decoder) { 2056 DecodeStatus S = MCDisassembler::Success; 2057 2058 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2059 unsigned imm = 0; 2060 2061 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2062 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2063 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2064 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2065 2066 if (Inst.getOpcode() == ARM::t2MOVTi16) 2067 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2068 return MCDisassembler::Fail; 2069 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2070 return MCDisassembler::Fail; 2071 2072 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2073 Inst.addOperand(MCOperand::CreateImm(imm)); 2074 2075 return S; 2076 } 2077 2078 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2079 uint64_t Address, const void *Decoder) { 2080 DecodeStatus S = MCDisassembler::Success; 2081 2082 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2083 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2084 unsigned imm = 0; 2085 2086 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2087 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2088 2089 if (Inst.getOpcode() == ARM::MOVTi16) 2090 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2091 return MCDisassembler::Fail; 2092 2093 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2094 return MCDisassembler::Fail; 2095 2096 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2097 Inst.addOperand(MCOperand::CreateImm(imm)); 2098 2099 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2100 return MCDisassembler::Fail; 2101 2102 return S; 2103 } 2104 2105 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2106 uint64_t Address, const void *Decoder) { 2107 DecodeStatus S = MCDisassembler::Success; 2108 2109 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2110 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2111 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2112 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2113 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2114 2115 if (pred == 0xF) 2116 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2117 2118 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2119 return MCDisassembler::Fail; 2120 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2121 return MCDisassembler::Fail; 2122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2123 return MCDisassembler::Fail; 2124 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2125 return MCDisassembler::Fail; 2126 2127 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2128 return MCDisassembler::Fail; 2129 2130 return S; 2131 } 2132 2133 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2134 uint64_t Address, const void *Decoder) { 2135 DecodeStatus S = MCDisassembler::Success; 2136 2137 unsigned add = fieldFromInstruction(Val, 12, 1); 2138 unsigned imm = fieldFromInstruction(Val, 0, 12); 2139 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2140 2141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2142 return MCDisassembler::Fail; 2143 2144 if (!add) imm *= -1; 2145 if (imm == 0 && !add) imm = INT32_MIN; 2146 Inst.addOperand(MCOperand::CreateImm(imm)); 2147 if (Rn == 15) 2148 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2149 2150 return S; 2151 } 2152 2153 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2154 uint64_t Address, const void *Decoder) { 2155 DecodeStatus S = MCDisassembler::Success; 2156 2157 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2158 unsigned U = fieldFromInstruction(Val, 8, 1); 2159 unsigned imm = fieldFromInstruction(Val, 0, 8); 2160 2161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2162 return MCDisassembler::Fail; 2163 2164 if (U) 2165 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2166 else 2167 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2168 2169 return S; 2170 } 2171 2172 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2173 uint64_t Address, const void *Decoder) { 2174 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2175 } 2176 2177 static DecodeStatus 2178 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2179 uint64_t Address, const void *Decoder) { 2180 DecodeStatus Status = MCDisassembler::Success; 2181 2182 // Note the J1 and J2 values are from the encoded instruction. So here 2183 // change them to I1 and I2 values via as documented: 2184 // I1 = NOT(J1 EOR S); 2185 // I2 = NOT(J2 EOR S); 2186 // and build the imm32 with one trailing zero as documented: 2187 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2188 unsigned S = fieldFromInstruction(Insn, 26, 1); 2189 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2190 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2191 unsigned I1 = !(J1 ^ S); 2192 unsigned I2 = !(J2 ^ S); 2193 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2194 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2195 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2196 int imm32 = SignExtend32<25>(tmp << 1); 2197 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2198 true, 4, Inst, Decoder)) 2199 Inst.addOperand(MCOperand::CreateImm(imm32)); 2200 2201 return Status; 2202 } 2203 2204 static DecodeStatus 2205 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2206 uint64_t Address, const void *Decoder) { 2207 DecodeStatus S = MCDisassembler::Success; 2208 2209 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2210 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2211 2212 if (pred == 0xF) { 2213 Inst.setOpcode(ARM::BLXi); 2214 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2215 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2216 true, 4, Inst, Decoder)) 2217 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2218 return S; 2219 } 2220 2221 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2222 true, 4, Inst, Decoder)) 2223 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2224 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2225 return MCDisassembler::Fail; 2226 2227 return S; 2228 } 2229 2230 2231 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2232 uint64_t Address, const void *Decoder) { 2233 DecodeStatus S = MCDisassembler::Success; 2234 2235 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2236 unsigned align = fieldFromInstruction(Val, 4, 2); 2237 2238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2239 return MCDisassembler::Fail; 2240 if (!align) 2241 Inst.addOperand(MCOperand::CreateImm(0)); 2242 else 2243 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2244 2245 return S; 2246 } 2247 2248 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2249 uint64_t Address, const void *Decoder) { 2250 DecodeStatus S = MCDisassembler::Success; 2251 2252 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2253 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2254 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2255 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2256 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2257 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2258 2259 // First output register 2260 switch (Inst.getOpcode()) { 2261 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2262 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2263 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2264 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2265 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2266 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2267 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2268 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2269 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2270 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2271 return MCDisassembler::Fail; 2272 break; 2273 case ARM::VLD2b16: 2274 case ARM::VLD2b32: 2275 case ARM::VLD2b8: 2276 case ARM::VLD2b16wb_fixed: 2277 case ARM::VLD2b16wb_register: 2278 case ARM::VLD2b32wb_fixed: 2279 case ARM::VLD2b32wb_register: 2280 case ARM::VLD2b8wb_fixed: 2281 case ARM::VLD2b8wb_register: 2282 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2283 return MCDisassembler::Fail; 2284 break; 2285 default: 2286 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2287 return MCDisassembler::Fail; 2288 } 2289 2290 // Second output register 2291 switch (Inst.getOpcode()) { 2292 case ARM::VLD3d8: 2293 case ARM::VLD3d16: 2294 case ARM::VLD3d32: 2295 case ARM::VLD3d8_UPD: 2296 case ARM::VLD3d16_UPD: 2297 case ARM::VLD3d32_UPD: 2298 case ARM::VLD4d8: 2299 case ARM::VLD4d16: 2300 case ARM::VLD4d32: 2301 case ARM::VLD4d8_UPD: 2302 case ARM::VLD4d16_UPD: 2303 case ARM::VLD4d32_UPD: 2304 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2305 return MCDisassembler::Fail; 2306 break; 2307 case ARM::VLD3q8: 2308 case ARM::VLD3q16: 2309 case ARM::VLD3q32: 2310 case ARM::VLD3q8_UPD: 2311 case ARM::VLD3q16_UPD: 2312 case ARM::VLD3q32_UPD: 2313 case ARM::VLD4q8: 2314 case ARM::VLD4q16: 2315 case ARM::VLD4q32: 2316 case ARM::VLD4q8_UPD: 2317 case ARM::VLD4q16_UPD: 2318 case ARM::VLD4q32_UPD: 2319 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2320 return MCDisassembler::Fail; 2321 default: 2322 break; 2323 } 2324 2325 // Third output register 2326 switch(Inst.getOpcode()) { 2327 case ARM::VLD3d8: 2328 case ARM::VLD3d16: 2329 case ARM::VLD3d32: 2330 case ARM::VLD3d8_UPD: 2331 case ARM::VLD3d16_UPD: 2332 case ARM::VLD3d32_UPD: 2333 case ARM::VLD4d8: 2334 case ARM::VLD4d16: 2335 case ARM::VLD4d32: 2336 case ARM::VLD4d8_UPD: 2337 case ARM::VLD4d16_UPD: 2338 case ARM::VLD4d32_UPD: 2339 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2340 return MCDisassembler::Fail; 2341 break; 2342 case ARM::VLD3q8: 2343 case ARM::VLD3q16: 2344 case ARM::VLD3q32: 2345 case ARM::VLD3q8_UPD: 2346 case ARM::VLD3q16_UPD: 2347 case ARM::VLD3q32_UPD: 2348 case ARM::VLD4q8: 2349 case ARM::VLD4q16: 2350 case ARM::VLD4q32: 2351 case ARM::VLD4q8_UPD: 2352 case ARM::VLD4q16_UPD: 2353 case ARM::VLD4q32_UPD: 2354 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2355 return MCDisassembler::Fail; 2356 break; 2357 default: 2358 break; 2359 } 2360 2361 // Fourth output register 2362 switch (Inst.getOpcode()) { 2363 case ARM::VLD4d8: 2364 case ARM::VLD4d16: 2365 case ARM::VLD4d32: 2366 case ARM::VLD4d8_UPD: 2367 case ARM::VLD4d16_UPD: 2368 case ARM::VLD4d32_UPD: 2369 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2370 return MCDisassembler::Fail; 2371 break; 2372 case ARM::VLD4q8: 2373 case ARM::VLD4q16: 2374 case ARM::VLD4q32: 2375 case ARM::VLD4q8_UPD: 2376 case ARM::VLD4q16_UPD: 2377 case ARM::VLD4q32_UPD: 2378 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2379 return MCDisassembler::Fail; 2380 break; 2381 default: 2382 break; 2383 } 2384 2385 // Writeback operand 2386 switch (Inst.getOpcode()) { 2387 case ARM::VLD1d8wb_fixed: 2388 case ARM::VLD1d16wb_fixed: 2389 case ARM::VLD1d32wb_fixed: 2390 case ARM::VLD1d64wb_fixed: 2391 case ARM::VLD1d8wb_register: 2392 case ARM::VLD1d16wb_register: 2393 case ARM::VLD1d32wb_register: 2394 case ARM::VLD1d64wb_register: 2395 case ARM::VLD1q8wb_fixed: 2396 case ARM::VLD1q16wb_fixed: 2397 case ARM::VLD1q32wb_fixed: 2398 case ARM::VLD1q64wb_fixed: 2399 case ARM::VLD1q8wb_register: 2400 case ARM::VLD1q16wb_register: 2401 case ARM::VLD1q32wb_register: 2402 case ARM::VLD1q64wb_register: 2403 case ARM::VLD1d8Twb_fixed: 2404 case ARM::VLD1d8Twb_register: 2405 case ARM::VLD1d16Twb_fixed: 2406 case ARM::VLD1d16Twb_register: 2407 case ARM::VLD1d32Twb_fixed: 2408 case ARM::VLD1d32Twb_register: 2409 case ARM::VLD1d64Twb_fixed: 2410 case ARM::VLD1d64Twb_register: 2411 case ARM::VLD1d8Qwb_fixed: 2412 case ARM::VLD1d8Qwb_register: 2413 case ARM::VLD1d16Qwb_fixed: 2414 case ARM::VLD1d16Qwb_register: 2415 case ARM::VLD1d32Qwb_fixed: 2416 case ARM::VLD1d32Qwb_register: 2417 case ARM::VLD1d64Qwb_fixed: 2418 case ARM::VLD1d64Qwb_register: 2419 case ARM::VLD2d8wb_fixed: 2420 case ARM::VLD2d16wb_fixed: 2421 case ARM::VLD2d32wb_fixed: 2422 case ARM::VLD2q8wb_fixed: 2423 case ARM::VLD2q16wb_fixed: 2424 case ARM::VLD2q32wb_fixed: 2425 case ARM::VLD2d8wb_register: 2426 case ARM::VLD2d16wb_register: 2427 case ARM::VLD2d32wb_register: 2428 case ARM::VLD2q8wb_register: 2429 case ARM::VLD2q16wb_register: 2430 case ARM::VLD2q32wb_register: 2431 case ARM::VLD2b8wb_fixed: 2432 case ARM::VLD2b16wb_fixed: 2433 case ARM::VLD2b32wb_fixed: 2434 case ARM::VLD2b8wb_register: 2435 case ARM::VLD2b16wb_register: 2436 case ARM::VLD2b32wb_register: 2437 Inst.addOperand(MCOperand::CreateImm(0)); 2438 break; 2439 case ARM::VLD3d8_UPD: 2440 case ARM::VLD3d16_UPD: 2441 case ARM::VLD3d32_UPD: 2442 case ARM::VLD3q8_UPD: 2443 case ARM::VLD3q16_UPD: 2444 case ARM::VLD3q32_UPD: 2445 case ARM::VLD4d8_UPD: 2446 case ARM::VLD4d16_UPD: 2447 case ARM::VLD4d32_UPD: 2448 case ARM::VLD4q8_UPD: 2449 case ARM::VLD4q16_UPD: 2450 case ARM::VLD4q32_UPD: 2451 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2452 return MCDisassembler::Fail; 2453 break; 2454 default: 2455 break; 2456 } 2457 2458 // AddrMode6 Base (register+alignment) 2459 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2460 return MCDisassembler::Fail; 2461 2462 // AddrMode6 Offset (register) 2463 switch (Inst.getOpcode()) { 2464 default: 2465 // The below have been updated to have explicit am6offset split 2466 // between fixed and register offset. For those instructions not 2467 // yet updated, we need to add an additional reg0 operand for the 2468 // fixed variant. 2469 // 2470 // The fixed offset encodes as Rm == 0xd, so we check for that. 2471 if (Rm == 0xd) { 2472 Inst.addOperand(MCOperand::CreateReg(0)); 2473 break; 2474 } 2475 // Fall through to handle the register offset variant. 2476 case ARM::VLD1d8wb_fixed: 2477 case ARM::VLD1d16wb_fixed: 2478 case ARM::VLD1d32wb_fixed: 2479 case ARM::VLD1d64wb_fixed: 2480 case ARM::VLD1d8Twb_fixed: 2481 case ARM::VLD1d16Twb_fixed: 2482 case ARM::VLD1d32Twb_fixed: 2483 case ARM::VLD1d64Twb_fixed: 2484 case ARM::VLD1d8Qwb_fixed: 2485 case ARM::VLD1d16Qwb_fixed: 2486 case ARM::VLD1d32Qwb_fixed: 2487 case ARM::VLD1d64Qwb_fixed: 2488 case ARM::VLD1d8wb_register: 2489 case ARM::VLD1d16wb_register: 2490 case ARM::VLD1d32wb_register: 2491 case ARM::VLD1d64wb_register: 2492 case ARM::VLD1q8wb_fixed: 2493 case ARM::VLD1q16wb_fixed: 2494 case ARM::VLD1q32wb_fixed: 2495 case ARM::VLD1q64wb_fixed: 2496 case ARM::VLD1q8wb_register: 2497 case ARM::VLD1q16wb_register: 2498 case ARM::VLD1q32wb_register: 2499 case ARM::VLD1q64wb_register: 2500 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2501 // variant encodes Rm == 0xf. Anything else is a register offset post- 2502 // increment and we need to add the register operand to the instruction. 2503 if (Rm != 0xD && Rm != 0xF && 2504 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2505 return MCDisassembler::Fail; 2506 break; 2507 case ARM::VLD2d8wb_fixed: 2508 case ARM::VLD2d16wb_fixed: 2509 case ARM::VLD2d32wb_fixed: 2510 case ARM::VLD2b8wb_fixed: 2511 case ARM::VLD2b16wb_fixed: 2512 case ARM::VLD2b32wb_fixed: 2513 case ARM::VLD2q8wb_fixed: 2514 case ARM::VLD2q16wb_fixed: 2515 case ARM::VLD2q32wb_fixed: 2516 break; 2517 } 2518 2519 return S; 2520 } 2521 2522 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2523 uint64_t Address, const void *Decoder) { 2524 unsigned type = fieldFromInstruction(Insn, 8, 4); 2525 unsigned align = fieldFromInstruction(Insn, 4, 2); 2526 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2527 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2528 if (type == 10 && align == 3) return MCDisassembler::Fail; 2529 2530 unsigned load = fieldFromInstruction(Insn, 21, 1); 2531 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2532 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2533 } 2534 2535 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2536 uint64_t Address, const void *Decoder) { 2537 unsigned size = fieldFromInstruction(Insn, 6, 2); 2538 if (size == 3) return MCDisassembler::Fail; 2539 2540 unsigned type = fieldFromInstruction(Insn, 8, 4); 2541 unsigned align = fieldFromInstruction(Insn, 4, 2); 2542 if (type == 8 && align == 3) return MCDisassembler::Fail; 2543 if (type == 9 && align == 3) return MCDisassembler::Fail; 2544 2545 unsigned load = fieldFromInstruction(Insn, 21, 1); 2546 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2547 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2548 } 2549 2550 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2551 uint64_t Address, const void *Decoder) { 2552 unsigned size = fieldFromInstruction(Insn, 6, 2); 2553 if (size == 3) return MCDisassembler::Fail; 2554 2555 unsigned align = fieldFromInstruction(Insn, 4, 2); 2556 if (align & 2) return MCDisassembler::Fail; 2557 2558 unsigned load = fieldFromInstruction(Insn, 21, 1); 2559 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2560 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2561 } 2562 2563 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2564 uint64_t Address, const void *Decoder) { 2565 unsigned size = fieldFromInstruction(Insn, 6, 2); 2566 if (size == 3) return MCDisassembler::Fail; 2567 2568 unsigned load = fieldFromInstruction(Insn, 21, 1); 2569 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2570 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2571 } 2572 2573 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2574 uint64_t Address, const void *Decoder) { 2575 DecodeStatus S = MCDisassembler::Success; 2576 2577 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2578 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2579 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2580 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2581 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2582 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2583 2584 // Writeback Operand 2585 switch (Inst.getOpcode()) { 2586 case ARM::VST1d8wb_fixed: 2587 case ARM::VST1d16wb_fixed: 2588 case ARM::VST1d32wb_fixed: 2589 case ARM::VST1d64wb_fixed: 2590 case ARM::VST1d8wb_register: 2591 case ARM::VST1d16wb_register: 2592 case ARM::VST1d32wb_register: 2593 case ARM::VST1d64wb_register: 2594 case ARM::VST1q8wb_fixed: 2595 case ARM::VST1q16wb_fixed: 2596 case ARM::VST1q32wb_fixed: 2597 case ARM::VST1q64wb_fixed: 2598 case ARM::VST1q8wb_register: 2599 case ARM::VST1q16wb_register: 2600 case ARM::VST1q32wb_register: 2601 case ARM::VST1q64wb_register: 2602 case ARM::VST1d8Twb_fixed: 2603 case ARM::VST1d16Twb_fixed: 2604 case ARM::VST1d32Twb_fixed: 2605 case ARM::VST1d64Twb_fixed: 2606 case ARM::VST1d8Twb_register: 2607 case ARM::VST1d16Twb_register: 2608 case ARM::VST1d32Twb_register: 2609 case ARM::VST1d64Twb_register: 2610 case ARM::VST1d8Qwb_fixed: 2611 case ARM::VST1d16Qwb_fixed: 2612 case ARM::VST1d32Qwb_fixed: 2613 case ARM::VST1d64Qwb_fixed: 2614 case ARM::VST1d8Qwb_register: 2615 case ARM::VST1d16Qwb_register: 2616 case ARM::VST1d32Qwb_register: 2617 case ARM::VST1d64Qwb_register: 2618 case ARM::VST2d8wb_fixed: 2619 case ARM::VST2d16wb_fixed: 2620 case ARM::VST2d32wb_fixed: 2621 case ARM::VST2d8wb_register: 2622 case ARM::VST2d16wb_register: 2623 case ARM::VST2d32wb_register: 2624 case ARM::VST2q8wb_fixed: 2625 case ARM::VST2q16wb_fixed: 2626 case ARM::VST2q32wb_fixed: 2627 case ARM::VST2q8wb_register: 2628 case ARM::VST2q16wb_register: 2629 case ARM::VST2q32wb_register: 2630 case ARM::VST2b8wb_fixed: 2631 case ARM::VST2b16wb_fixed: 2632 case ARM::VST2b32wb_fixed: 2633 case ARM::VST2b8wb_register: 2634 case ARM::VST2b16wb_register: 2635 case ARM::VST2b32wb_register: 2636 if (Rm == 0xF) 2637 return MCDisassembler::Fail; 2638 Inst.addOperand(MCOperand::CreateImm(0)); 2639 break; 2640 case ARM::VST3d8_UPD: 2641 case ARM::VST3d16_UPD: 2642 case ARM::VST3d32_UPD: 2643 case ARM::VST3q8_UPD: 2644 case ARM::VST3q16_UPD: 2645 case ARM::VST3q32_UPD: 2646 case ARM::VST4d8_UPD: 2647 case ARM::VST4d16_UPD: 2648 case ARM::VST4d32_UPD: 2649 case ARM::VST4q8_UPD: 2650 case ARM::VST4q16_UPD: 2651 case ARM::VST4q32_UPD: 2652 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2653 return MCDisassembler::Fail; 2654 break; 2655 default: 2656 break; 2657 } 2658 2659 // AddrMode6 Base (register+alignment) 2660 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2661 return MCDisassembler::Fail; 2662 2663 // AddrMode6 Offset (register) 2664 switch (Inst.getOpcode()) { 2665 default: 2666 if (Rm == 0xD) 2667 Inst.addOperand(MCOperand::CreateReg(0)); 2668 else if (Rm != 0xF) { 2669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2670 return MCDisassembler::Fail; 2671 } 2672 break; 2673 case ARM::VST1d8wb_fixed: 2674 case ARM::VST1d16wb_fixed: 2675 case ARM::VST1d32wb_fixed: 2676 case ARM::VST1d64wb_fixed: 2677 case ARM::VST1q8wb_fixed: 2678 case ARM::VST1q16wb_fixed: 2679 case ARM::VST1q32wb_fixed: 2680 case ARM::VST1q64wb_fixed: 2681 case ARM::VST1d8Twb_fixed: 2682 case ARM::VST1d16Twb_fixed: 2683 case ARM::VST1d32Twb_fixed: 2684 case ARM::VST1d64Twb_fixed: 2685 case ARM::VST1d8Qwb_fixed: 2686 case ARM::VST1d16Qwb_fixed: 2687 case ARM::VST1d32Qwb_fixed: 2688 case ARM::VST1d64Qwb_fixed: 2689 case ARM::VST2d8wb_fixed: 2690 case ARM::VST2d16wb_fixed: 2691 case ARM::VST2d32wb_fixed: 2692 case ARM::VST2q8wb_fixed: 2693 case ARM::VST2q16wb_fixed: 2694 case ARM::VST2q32wb_fixed: 2695 case ARM::VST2b8wb_fixed: 2696 case ARM::VST2b16wb_fixed: 2697 case ARM::VST2b32wb_fixed: 2698 break; 2699 } 2700 2701 2702 // First input register 2703 switch (Inst.getOpcode()) { 2704 case ARM::VST1q16: 2705 case ARM::VST1q32: 2706 case ARM::VST1q64: 2707 case ARM::VST1q8: 2708 case ARM::VST1q16wb_fixed: 2709 case ARM::VST1q16wb_register: 2710 case ARM::VST1q32wb_fixed: 2711 case ARM::VST1q32wb_register: 2712 case ARM::VST1q64wb_fixed: 2713 case ARM::VST1q64wb_register: 2714 case ARM::VST1q8wb_fixed: 2715 case ARM::VST1q8wb_register: 2716 case ARM::VST2d16: 2717 case ARM::VST2d32: 2718 case ARM::VST2d8: 2719 case ARM::VST2d16wb_fixed: 2720 case ARM::VST2d16wb_register: 2721 case ARM::VST2d32wb_fixed: 2722 case ARM::VST2d32wb_register: 2723 case ARM::VST2d8wb_fixed: 2724 case ARM::VST2d8wb_register: 2725 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2726 return MCDisassembler::Fail; 2727 break; 2728 case ARM::VST2b16: 2729 case ARM::VST2b32: 2730 case ARM::VST2b8: 2731 case ARM::VST2b16wb_fixed: 2732 case ARM::VST2b16wb_register: 2733 case ARM::VST2b32wb_fixed: 2734 case ARM::VST2b32wb_register: 2735 case ARM::VST2b8wb_fixed: 2736 case ARM::VST2b8wb_register: 2737 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2738 return MCDisassembler::Fail; 2739 break; 2740 default: 2741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2742 return MCDisassembler::Fail; 2743 } 2744 2745 // Second input register 2746 switch (Inst.getOpcode()) { 2747 case ARM::VST3d8: 2748 case ARM::VST3d16: 2749 case ARM::VST3d32: 2750 case ARM::VST3d8_UPD: 2751 case ARM::VST3d16_UPD: 2752 case ARM::VST3d32_UPD: 2753 case ARM::VST4d8: 2754 case ARM::VST4d16: 2755 case ARM::VST4d32: 2756 case ARM::VST4d8_UPD: 2757 case ARM::VST4d16_UPD: 2758 case ARM::VST4d32_UPD: 2759 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2760 return MCDisassembler::Fail; 2761 break; 2762 case ARM::VST3q8: 2763 case ARM::VST3q16: 2764 case ARM::VST3q32: 2765 case ARM::VST3q8_UPD: 2766 case ARM::VST3q16_UPD: 2767 case ARM::VST3q32_UPD: 2768 case ARM::VST4q8: 2769 case ARM::VST4q16: 2770 case ARM::VST4q32: 2771 case ARM::VST4q8_UPD: 2772 case ARM::VST4q16_UPD: 2773 case ARM::VST4q32_UPD: 2774 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2775 return MCDisassembler::Fail; 2776 break; 2777 default: 2778 break; 2779 } 2780 2781 // Third input register 2782 switch (Inst.getOpcode()) { 2783 case ARM::VST3d8: 2784 case ARM::VST3d16: 2785 case ARM::VST3d32: 2786 case ARM::VST3d8_UPD: 2787 case ARM::VST3d16_UPD: 2788 case ARM::VST3d32_UPD: 2789 case ARM::VST4d8: 2790 case ARM::VST4d16: 2791 case ARM::VST4d32: 2792 case ARM::VST4d8_UPD: 2793 case ARM::VST4d16_UPD: 2794 case ARM::VST4d32_UPD: 2795 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2796 return MCDisassembler::Fail; 2797 break; 2798 case ARM::VST3q8: 2799 case ARM::VST3q16: 2800 case ARM::VST3q32: 2801 case ARM::VST3q8_UPD: 2802 case ARM::VST3q16_UPD: 2803 case ARM::VST3q32_UPD: 2804 case ARM::VST4q8: 2805 case ARM::VST4q16: 2806 case ARM::VST4q32: 2807 case ARM::VST4q8_UPD: 2808 case ARM::VST4q16_UPD: 2809 case ARM::VST4q32_UPD: 2810 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2811 return MCDisassembler::Fail; 2812 break; 2813 default: 2814 break; 2815 } 2816 2817 // Fourth input register 2818 switch (Inst.getOpcode()) { 2819 case ARM::VST4d8: 2820 case ARM::VST4d16: 2821 case ARM::VST4d32: 2822 case ARM::VST4d8_UPD: 2823 case ARM::VST4d16_UPD: 2824 case ARM::VST4d32_UPD: 2825 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2826 return MCDisassembler::Fail; 2827 break; 2828 case ARM::VST4q8: 2829 case ARM::VST4q16: 2830 case ARM::VST4q32: 2831 case ARM::VST4q8_UPD: 2832 case ARM::VST4q16_UPD: 2833 case ARM::VST4q32_UPD: 2834 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2835 return MCDisassembler::Fail; 2836 break; 2837 default: 2838 break; 2839 } 2840 2841 return S; 2842 } 2843 2844 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2845 uint64_t Address, const void *Decoder) { 2846 DecodeStatus S = MCDisassembler::Success; 2847 2848 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2849 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2850 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2851 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2852 unsigned align = fieldFromInstruction(Insn, 4, 1); 2853 unsigned size = fieldFromInstruction(Insn, 6, 2); 2854 2855 if (size == 0 && align == 1) 2856 return MCDisassembler::Fail; 2857 align *= (1 << size); 2858 2859 switch (Inst.getOpcode()) { 2860 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2861 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2862 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2863 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2864 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2865 return MCDisassembler::Fail; 2866 break; 2867 default: 2868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2869 return MCDisassembler::Fail; 2870 break; 2871 } 2872 if (Rm != 0xF) { 2873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2874 return MCDisassembler::Fail; 2875 } 2876 2877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2878 return MCDisassembler::Fail; 2879 Inst.addOperand(MCOperand::CreateImm(align)); 2880 2881 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2882 // variant encodes Rm == 0xf. Anything else is a register offset post- 2883 // increment and we need to add the register operand to the instruction. 2884 if (Rm != 0xD && Rm != 0xF && 2885 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2886 return MCDisassembler::Fail; 2887 2888 return S; 2889 } 2890 2891 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2892 uint64_t Address, const void *Decoder) { 2893 DecodeStatus S = MCDisassembler::Success; 2894 2895 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2896 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2897 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2898 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2899 unsigned align = fieldFromInstruction(Insn, 4, 1); 2900 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2901 align *= 2*size; 2902 2903 switch (Inst.getOpcode()) { 2904 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2905 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2906 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2907 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2908 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 break; 2911 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2912 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2913 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2914 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2915 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2916 return MCDisassembler::Fail; 2917 break; 2918 default: 2919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2920 return MCDisassembler::Fail; 2921 break; 2922 } 2923 2924 if (Rm != 0xF) 2925 Inst.addOperand(MCOperand::CreateImm(0)); 2926 2927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2928 return MCDisassembler::Fail; 2929 Inst.addOperand(MCOperand::CreateImm(align)); 2930 2931 if (Rm != 0xD && Rm != 0xF) { 2932 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2933 return MCDisassembler::Fail; 2934 } 2935 2936 return S; 2937 } 2938 2939 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2940 uint64_t Address, const void *Decoder) { 2941 DecodeStatus S = MCDisassembler::Success; 2942 2943 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2944 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2945 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2946 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2947 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2948 2949 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2950 return MCDisassembler::Fail; 2951 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2952 return MCDisassembler::Fail; 2953 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2954 return MCDisassembler::Fail; 2955 if (Rm != 0xF) { 2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 } 2959 2960 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2961 return MCDisassembler::Fail; 2962 Inst.addOperand(MCOperand::CreateImm(0)); 2963 2964 if (Rm == 0xD) 2965 Inst.addOperand(MCOperand::CreateReg(0)); 2966 else if (Rm != 0xF) { 2967 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2968 return MCDisassembler::Fail; 2969 } 2970 2971 return S; 2972 } 2973 2974 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2975 uint64_t Address, const void *Decoder) { 2976 DecodeStatus S = MCDisassembler::Success; 2977 2978 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2979 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2980 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2981 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2982 unsigned size = fieldFromInstruction(Insn, 6, 2); 2983 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2984 unsigned align = fieldFromInstruction(Insn, 4, 1); 2985 2986 if (size == 0x3) { 2987 if (align == 0) 2988 return MCDisassembler::Fail; 2989 align = 16; 2990 } else { 2991 if (size == 2) { 2992 align *= 8; 2993 } else { 2994 size = 1 << size; 2995 align *= 4*size; 2996 } 2997 } 2998 2999 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3000 return MCDisassembler::Fail; 3001 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3002 return MCDisassembler::Fail; 3003 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3004 return MCDisassembler::Fail; 3005 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3006 return MCDisassembler::Fail; 3007 if (Rm != 0xF) { 3008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3009 return MCDisassembler::Fail; 3010 } 3011 3012 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3013 return MCDisassembler::Fail; 3014 Inst.addOperand(MCOperand::CreateImm(align)); 3015 3016 if (Rm == 0xD) 3017 Inst.addOperand(MCOperand::CreateReg(0)); 3018 else if (Rm != 0xF) { 3019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3020 return MCDisassembler::Fail; 3021 } 3022 3023 return S; 3024 } 3025 3026 static DecodeStatus 3027 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3028 uint64_t Address, const void *Decoder) { 3029 DecodeStatus S = MCDisassembler::Success; 3030 3031 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3032 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3033 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3034 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3035 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3036 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3037 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3038 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3039 3040 if (Q) { 3041 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3042 return MCDisassembler::Fail; 3043 } else { 3044 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3045 return MCDisassembler::Fail; 3046 } 3047 3048 Inst.addOperand(MCOperand::CreateImm(imm)); 3049 3050 switch (Inst.getOpcode()) { 3051 case ARM::VORRiv4i16: 3052 case ARM::VORRiv2i32: 3053 case ARM::VBICiv4i16: 3054 case ARM::VBICiv2i32: 3055 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3056 return MCDisassembler::Fail; 3057 break; 3058 case ARM::VORRiv8i16: 3059 case ARM::VORRiv4i32: 3060 case ARM::VBICiv8i16: 3061 case ARM::VBICiv4i32: 3062 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3063 return MCDisassembler::Fail; 3064 break; 3065 default: 3066 break; 3067 } 3068 3069 return S; 3070 } 3071 3072 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3073 uint64_t Address, const void *Decoder) { 3074 DecodeStatus S = MCDisassembler::Success; 3075 3076 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3077 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3078 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3079 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3080 unsigned size = fieldFromInstruction(Insn, 18, 2); 3081 3082 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3083 return MCDisassembler::Fail; 3084 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3085 return MCDisassembler::Fail; 3086 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3087 3088 return S; 3089 } 3090 3091 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3092 uint64_t Address, const void *Decoder) { 3093 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3094 return MCDisassembler::Success; 3095 } 3096 3097 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3098 uint64_t Address, const void *Decoder) { 3099 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3100 return MCDisassembler::Success; 3101 } 3102 3103 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3104 uint64_t Address, const void *Decoder) { 3105 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3106 return MCDisassembler::Success; 3107 } 3108 3109 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3110 uint64_t Address, const void *Decoder) { 3111 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3112 return MCDisassembler::Success; 3113 } 3114 3115 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3116 uint64_t Address, const void *Decoder) { 3117 DecodeStatus S = MCDisassembler::Success; 3118 3119 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3120 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3121 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3122 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3123 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3124 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3125 unsigned op = fieldFromInstruction(Insn, 6, 1); 3126 3127 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3128 return MCDisassembler::Fail; 3129 if (op) { 3130 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3131 return MCDisassembler::Fail; // Writeback 3132 } 3133 3134 switch (Inst.getOpcode()) { 3135 case ARM::VTBL2: 3136 case ARM::VTBX2: 3137 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3138 return MCDisassembler::Fail; 3139 break; 3140 default: 3141 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3142 return MCDisassembler::Fail; 3143 } 3144 3145 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3146 return MCDisassembler::Fail; 3147 3148 return S; 3149 } 3150 3151 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3152 uint64_t Address, const void *Decoder) { 3153 DecodeStatus S = MCDisassembler::Success; 3154 3155 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3156 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3157 3158 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3159 return MCDisassembler::Fail; 3160 3161 switch(Inst.getOpcode()) { 3162 default: 3163 return MCDisassembler::Fail; 3164 case ARM::tADR: 3165 break; // tADR does not explicitly represent the PC as an operand. 3166 case ARM::tADDrSPi: 3167 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3168 break; 3169 } 3170 3171 Inst.addOperand(MCOperand::CreateImm(imm)); 3172 return S; 3173 } 3174 3175 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3176 uint64_t Address, const void *Decoder) { 3177 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3178 true, 2, Inst, Decoder)) 3179 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3180 return MCDisassembler::Success; 3181 } 3182 3183 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3184 uint64_t Address, const void *Decoder) { 3185 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3186 true, 4, Inst, Decoder)) 3187 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3188 return MCDisassembler::Success; 3189 } 3190 3191 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3192 uint64_t Address, const void *Decoder) { 3193 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3194 true, 2, Inst, Decoder)) 3195 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3196 return MCDisassembler::Success; 3197 } 3198 3199 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3200 uint64_t Address, const void *Decoder) { 3201 DecodeStatus S = MCDisassembler::Success; 3202 3203 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3204 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3205 3206 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3207 return MCDisassembler::Fail; 3208 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3209 return MCDisassembler::Fail; 3210 3211 return S; 3212 } 3213 3214 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3215 uint64_t Address, const void *Decoder) { 3216 DecodeStatus S = MCDisassembler::Success; 3217 3218 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3219 unsigned imm = fieldFromInstruction(Val, 3, 5); 3220 3221 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3222 return MCDisassembler::Fail; 3223 Inst.addOperand(MCOperand::CreateImm(imm)); 3224 3225 return S; 3226 } 3227 3228 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3229 uint64_t Address, const void *Decoder) { 3230 unsigned imm = Val << 2; 3231 3232 Inst.addOperand(MCOperand::CreateImm(imm)); 3233 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3234 3235 return MCDisassembler::Success; 3236 } 3237 3238 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3239 uint64_t Address, const void *Decoder) { 3240 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3241 Inst.addOperand(MCOperand::CreateImm(Val)); 3242 3243 return MCDisassembler::Success; 3244 } 3245 3246 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3247 uint64_t Address, const void *Decoder) { 3248 DecodeStatus S = MCDisassembler::Success; 3249 3250 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3251 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3252 unsigned imm = fieldFromInstruction(Val, 0, 2); 3253 3254 // Thumb stores cannot use PC as dest register. 3255 switch (Inst.getOpcode()) { 3256 case ARM::t2STRHs: 3257 case ARM::t2STRBs: 3258 case ARM::t2STRs: 3259 if (Rn == 15) 3260 return MCDisassembler::Fail; 3261 default: 3262 break; 3263 } 3264 3265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3266 return MCDisassembler::Fail; 3267 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3268 return MCDisassembler::Fail; 3269 Inst.addOperand(MCOperand::CreateImm(imm)); 3270 3271 return S; 3272 } 3273 3274 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3275 uint64_t Address, const void *Decoder) { 3276 DecodeStatus S = MCDisassembler::Success; 3277 3278 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3279 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3280 3281 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3282 .getFeatureBits(); 3283 bool hasMP = featureBits & ARM::FeatureMP; 3284 bool hasV7Ops = featureBits & ARM::HasV7Ops; 3285 3286 if (Rn == 15) { 3287 switch (Inst.getOpcode()) { 3288 case ARM::t2LDRBs: 3289 Inst.setOpcode(ARM::t2LDRBpci); 3290 break; 3291 case ARM::t2LDRHs: 3292 Inst.setOpcode(ARM::t2LDRHpci); 3293 break; 3294 case ARM::t2LDRSHs: 3295 Inst.setOpcode(ARM::t2LDRSHpci); 3296 break; 3297 case ARM::t2LDRSBs: 3298 Inst.setOpcode(ARM::t2LDRSBpci); 3299 break; 3300 case ARM::t2LDRs: 3301 Inst.setOpcode(ARM::t2LDRpci); 3302 break; 3303 case ARM::t2PLDs: 3304 Inst.setOpcode(ARM::t2PLDpci); 3305 break; 3306 case ARM::t2PLIs: 3307 Inst.setOpcode(ARM::t2PLIpci); 3308 break; 3309 default: 3310 return MCDisassembler::Fail; 3311 } 3312 3313 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3314 } 3315 3316 if (Rt == 15) { 3317 switch (Inst.getOpcode()) { 3318 case ARM::t2LDRSHs: 3319 return MCDisassembler::Fail; 3320 case ARM::t2LDRHs: 3321 Inst.setOpcode(ARM::t2PLDWs); 3322 break; 3323 case ARM::t2LDRSBs: 3324 Inst.setOpcode(ARM::t2PLIs); 3325 default: 3326 break; 3327 } 3328 } 3329 3330 switch (Inst.getOpcode()) { 3331 case ARM::t2PLDs: 3332 break; 3333 case ARM::t2PLIs: 3334 if (!hasV7Ops) 3335 return MCDisassembler::Fail; 3336 break; 3337 case ARM::t2PLDWs: 3338 if (!hasV7Ops || !hasMP) 3339 return MCDisassembler::Fail; 3340 break; 3341 default: 3342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3343 return MCDisassembler::Fail; 3344 } 3345 3346 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3347 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3348 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3349 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3350 return MCDisassembler::Fail; 3351 3352 return S; 3353 } 3354 3355 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3356 uint64_t Address, const void* Decoder) { 3357 DecodeStatus S = MCDisassembler::Success; 3358 3359 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3360 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3361 unsigned U = fieldFromInstruction(Insn, 9, 1); 3362 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3363 imm |= (U << 8); 3364 imm |= (Rn << 9); 3365 unsigned add = fieldFromInstruction(Insn, 9, 1); 3366 3367 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3368 .getFeatureBits(); 3369 bool hasMP = featureBits & ARM::FeatureMP; 3370 bool hasV7Ops = featureBits & ARM::HasV7Ops; 3371 3372 if (Rn == 15) { 3373 switch (Inst.getOpcode()) { 3374 case ARM::t2LDRi8: 3375 Inst.setOpcode(ARM::t2LDRpci); 3376 break; 3377 case ARM::t2LDRBi8: 3378 Inst.setOpcode(ARM::t2LDRBpci); 3379 break; 3380 case ARM::t2LDRSBi8: 3381 Inst.setOpcode(ARM::t2LDRSBpci); 3382 break; 3383 case ARM::t2LDRHi8: 3384 Inst.setOpcode(ARM::t2LDRHpci); 3385 break; 3386 case ARM::t2LDRSHi8: 3387 Inst.setOpcode(ARM::t2LDRSHpci); 3388 break; 3389 case ARM::t2PLDi8: 3390 Inst.setOpcode(ARM::t2PLDpci); 3391 break; 3392 case ARM::t2PLIi8: 3393 Inst.setOpcode(ARM::t2PLIpci); 3394 break; 3395 default: 3396 return MCDisassembler::Fail; 3397 } 3398 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3399 } 3400 3401 if (Rt == 15) { 3402 switch (Inst.getOpcode()) { 3403 case ARM::t2LDRSHi8: 3404 return MCDisassembler::Fail; 3405 case ARM::t2LDRHi8: 3406 if (!add) 3407 Inst.setOpcode(ARM::t2PLDWi8); 3408 break; 3409 case ARM::t2LDRSBi8: 3410 Inst.setOpcode(ARM::t2PLIi8); 3411 break; 3412 default: 3413 break; 3414 } 3415 } 3416 3417 switch (Inst.getOpcode()) { 3418 case ARM::t2PLDi8: 3419 break; 3420 case ARM::t2PLIi8: 3421 if (!hasV7Ops) 3422 return MCDisassembler::Fail; 3423 break; 3424 case ARM::t2PLDWi8: 3425 if (!hasV7Ops || !hasMP) 3426 return MCDisassembler::Fail; 3427 break; 3428 default: 3429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3430 return MCDisassembler::Fail; 3431 } 3432 3433 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3434 return MCDisassembler::Fail; 3435 return S; 3436 } 3437 3438 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3439 uint64_t Address, const void* Decoder) { 3440 DecodeStatus S = MCDisassembler::Success; 3441 3442 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3443 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3444 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3445 imm |= (Rn << 13); 3446 3447 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3448 .getFeatureBits(); 3449 bool hasMP = (featureBits & ARM::FeatureMP); 3450 bool hasV7Ops = (featureBits & ARM::HasV7Ops); 3451 3452 if (Rn == 15) { 3453 switch (Inst.getOpcode()) { 3454 case ARM::t2LDRi12: 3455 Inst.setOpcode(ARM::t2LDRpci); 3456 break; 3457 case ARM::t2LDRHi12: 3458 Inst.setOpcode(ARM::t2LDRHpci); 3459 break; 3460 case ARM::t2LDRSHi12: 3461 Inst.setOpcode(ARM::t2LDRSHpci); 3462 break; 3463 case ARM::t2LDRBi12: 3464 Inst.setOpcode(ARM::t2LDRBpci); 3465 break; 3466 case ARM::t2LDRSBi12: 3467 Inst.setOpcode(ARM::t2LDRSBpci); 3468 break; 3469 case ARM::t2PLDi12: 3470 Inst.setOpcode(ARM::t2PLDpci); 3471 break; 3472 case ARM::t2PLIi12: 3473 Inst.setOpcode(ARM::t2PLIpci); 3474 break; 3475 default: 3476 return MCDisassembler::Fail; 3477 } 3478 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3479 } 3480 3481 if (Rt == 15) { 3482 switch (Inst.getOpcode()) { 3483 case ARM::t2LDRSHi12: 3484 return MCDisassembler::Fail; 3485 case ARM::t2LDRHi12: 3486 Inst.setOpcode(ARM::t2PLDWi12); 3487 break; 3488 case ARM::t2LDRSBi12: 3489 Inst.setOpcode(ARM::t2PLIi12); 3490 break; 3491 default: 3492 break; 3493 } 3494 } 3495 3496 switch (Inst.getOpcode()) { 3497 case ARM::t2PLDi12: 3498 break; 3499 case ARM::t2PLIi12: 3500 if (!hasV7Ops) 3501 return MCDisassembler::Fail; 3502 break; 3503 case ARM::t2PLDWi12: 3504 if (!hasV7Ops || !hasMP) 3505 return MCDisassembler::Fail; 3506 break; 3507 default: 3508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3509 return MCDisassembler::Fail; 3510 } 3511 3512 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3513 return MCDisassembler::Fail; 3514 return S; 3515 } 3516 3517 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3518 uint64_t Address, const void* Decoder) { 3519 DecodeStatus S = MCDisassembler::Success; 3520 3521 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3522 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3523 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3524 imm |= (Rn << 9); 3525 3526 if (Rn == 15) { 3527 switch (Inst.getOpcode()) { 3528 case ARM::t2LDRT: 3529 Inst.setOpcode(ARM::t2LDRpci); 3530 break; 3531 case ARM::t2LDRBT: 3532 Inst.setOpcode(ARM::t2LDRBpci); 3533 break; 3534 case ARM::t2LDRHT: 3535 Inst.setOpcode(ARM::t2LDRHpci); 3536 break; 3537 case ARM::t2LDRSBT: 3538 Inst.setOpcode(ARM::t2LDRSBpci); 3539 break; 3540 case ARM::t2LDRSHT: 3541 Inst.setOpcode(ARM::t2LDRSHpci); 3542 break; 3543 default: 3544 return MCDisassembler::Fail; 3545 } 3546 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3547 } 3548 3549 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3550 return MCDisassembler::Fail; 3551 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3552 return MCDisassembler::Fail; 3553 return S; 3554 } 3555 3556 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3557 uint64_t Address, const void* Decoder) { 3558 DecodeStatus S = MCDisassembler::Success; 3559 3560 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3561 unsigned U = fieldFromInstruction(Insn, 23, 1); 3562 int imm = fieldFromInstruction(Insn, 0, 12); 3563 3564 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3565 .getFeatureBits(); 3566 bool hasV7Ops = (featureBits & ARM::HasV7Ops); 3567 3568 if (Rt == 15) { 3569 switch (Inst.getOpcode()) { 3570 case ARM::t2LDRBpci: 3571 case ARM::t2LDRHpci: 3572 Inst.setOpcode(ARM::t2PLDpci); 3573 break; 3574 case ARM::t2LDRSBpci: 3575 Inst.setOpcode(ARM::t2PLIpci); 3576 break; 3577 case ARM::t2LDRSHpci: 3578 return MCDisassembler::Fail; 3579 default: 3580 break; 3581 } 3582 } 3583 3584 switch(Inst.getOpcode()) { 3585 case ARM::t2PLDpci: 3586 break; 3587 case ARM::t2PLIpci: 3588 if (!hasV7Ops) 3589 return MCDisassembler::Fail; 3590 break; 3591 default: 3592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3593 return MCDisassembler::Fail; 3594 } 3595 3596 if (!U) { 3597 // Special case for #-0. 3598 if (imm == 0) 3599 imm = INT32_MIN; 3600 else 3601 imm = -imm; 3602 } 3603 Inst.addOperand(MCOperand::CreateImm(imm)); 3604 3605 return S; 3606 } 3607 3608 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3609 uint64_t Address, const void *Decoder) { 3610 if (Val == 0) 3611 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3612 else { 3613 int imm = Val & 0xFF; 3614 3615 if (!(Val & 0x100)) imm *= -1; 3616 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3617 } 3618 3619 return MCDisassembler::Success; 3620 } 3621 3622 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3623 uint64_t Address, const void *Decoder) { 3624 DecodeStatus S = MCDisassembler::Success; 3625 3626 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3627 unsigned imm = fieldFromInstruction(Val, 0, 9); 3628 3629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3630 return MCDisassembler::Fail; 3631 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3632 return MCDisassembler::Fail; 3633 3634 return S; 3635 } 3636 3637 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3638 uint64_t Address, const void *Decoder) { 3639 DecodeStatus S = MCDisassembler::Success; 3640 3641 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3642 unsigned imm = fieldFromInstruction(Val, 0, 8); 3643 3644 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3645 return MCDisassembler::Fail; 3646 3647 Inst.addOperand(MCOperand::CreateImm(imm)); 3648 3649 return S; 3650 } 3651 3652 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3653 uint64_t Address, const void *Decoder) { 3654 int imm = Val & 0xFF; 3655 if (Val == 0) 3656 imm = INT32_MIN; 3657 else if (!(Val & 0x100)) 3658 imm *= -1; 3659 Inst.addOperand(MCOperand::CreateImm(imm)); 3660 3661 return MCDisassembler::Success; 3662 } 3663 3664 3665 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3666 uint64_t Address, const void *Decoder) { 3667 DecodeStatus S = MCDisassembler::Success; 3668 3669 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3670 unsigned imm = fieldFromInstruction(Val, 0, 9); 3671 3672 // Thumb stores cannot use PC as dest register. 3673 switch (Inst.getOpcode()) { 3674 case ARM::t2STRT: 3675 case ARM::t2STRBT: 3676 case ARM::t2STRHT: 3677 case ARM::t2STRi8: 3678 case ARM::t2STRHi8: 3679 case ARM::t2STRBi8: 3680 if (Rn == 15) 3681 return MCDisassembler::Fail; 3682 break; 3683 default: 3684 break; 3685 } 3686 3687 // Some instructions always use an additive offset. 3688 switch (Inst.getOpcode()) { 3689 case ARM::t2LDRT: 3690 case ARM::t2LDRBT: 3691 case ARM::t2LDRHT: 3692 case ARM::t2LDRSBT: 3693 case ARM::t2LDRSHT: 3694 case ARM::t2STRT: 3695 case ARM::t2STRBT: 3696 case ARM::t2STRHT: 3697 imm |= 0x100; 3698 break; 3699 default: 3700 break; 3701 } 3702 3703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3704 return MCDisassembler::Fail; 3705 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3706 return MCDisassembler::Fail; 3707 3708 return S; 3709 } 3710 3711 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3712 uint64_t Address, const void *Decoder) { 3713 DecodeStatus S = MCDisassembler::Success; 3714 3715 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3716 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3717 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3718 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3719 addr |= Rn << 9; 3720 unsigned load = fieldFromInstruction(Insn, 20, 1); 3721 3722 if (Rn == 15) { 3723 switch (Inst.getOpcode()) { 3724 case ARM::t2LDR_PRE: 3725 case ARM::t2LDR_POST: 3726 Inst.setOpcode(ARM::t2LDRpci); 3727 break; 3728 case ARM::t2LDRB_PRE: 3729 case ARM::t2LDRB_POST: 3730 Inst.setOpcode(ARM::t2LDRBpci); 3731 break; 3732 case ARM::t2LDRH_PRE: 3733 case ARM::t2LDRH_POST: 3734 Inst.setOpcode(ARM::t2LDRHpci); 3735 break; 3736 case ARM::t2LDRSB_PRE: 3737 case ARM::t2LDRSB_POST: 3738 if (Rt == 15) 3739 Inst.setOpcode(ARM::t2PLIpci); 3740 else 3741 Inst.setOpcode(ARM::t2LDRSBpci); 3742 break; 3743 case ARM::t2LDRSH_PRE: 3744 case ARM::t2LDRSH_POST: 3745 Inst.setOpcode(ARM::t2LDRSHpci); 3746 break; 3747 default: 3748 return MCDisassembler::Fail; 3749 } 3750 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3751 } 3752 3753 if (!load) { 3754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3755 return MCDisassembler::Fail; 3756 } 3757 3758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3759 return MCDisassembler::Fail; 3760 3761 if (load) { 3762 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3763 return MCDisassembler::Fail; 3764 } 3765 3766 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3767 return MCDisassembler::Fail; 3768 3769 return S; 3770 } 3771 3772 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3773 uint64_t Address, const void *Decoder) { 3774 DecodeStatus S = MCDisassembler::Success; 3775 3776 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3777 unsigned imm = fieldFromInstruction(Val, 0, 12); 3778 3779 // Thumb stores cannot use PC as dest register. 3780 switch (Inst.getOpcode()) { 3781 case ARM::t2STRi12: 3782 case ARM::t2STRBi12: 3783 case ARM::t2STRHi12: 3784 if (Rn == 15) 3785 return MCDisassembler::Fail; 3786 default: 3787 break; 3788 } 3789 3790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3791 return MCDisassembler::Fail; 3792 Inst.addOperand(MCOperand::CreateImm(imm)); 3793 3794 return S; 3795 } 3796 3797 3798 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3799 uint64_t Address, const void *Decoder) { 3800 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3801 3802 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3803 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3804 Inst.addOperand(MCOperand::CreateImm(imm)); 3805 3806 return MCDisassembler::Success; 3807 } 3808 3809 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3810 uint64_t Address, const void *Decoder) { 3811 DecodeStatus S = MCDisassembler::Success; 3812 3813 if (Inst.getOpcode() == ARM::tADDrSP) { 3814 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3815 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3816 3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3818 return MCDisassembler::Fail; 3819 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3821 return MCDisassembler::Fail; 3822 } else if (Inst.getOpcode() == ARM::tADDspr) { 3823 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3824 3825 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3826 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3827 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3828 return MCDisassembler::Fail; 3829 } 3830 3831 return S; 3832 } 3833 3834 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3835 uint64_t Address, const void *Decoder) { 3836 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3837 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3838 3839 Inst.addOperand(MCOperand::CreateImm(imod)); 3840 Inst.addOperand(MCOperand::CreateImm(flags)); 3841 3842 return MCDisassembler::Success; 3843 } 3844 3845 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3846 uint64_t Address, const void *Decoder) { 3847 DecodeStatus S = MCDisassembler::Success; 3848 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3849 unsigned add = fieldFromInstruction(Insn, 4, 1); 3850 3851 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3852 return MCDisassembler::Fail; 3853 Inst.addOperand(MCOperand::CreateImm(add)); 3854 3855 return S; 3856 } 3857 3858 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3859 uint64_t Address, const void *Decoder) { 3860 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3861 // Note only one trailing zero not two. Also the J1 and J2 values are from 3862 // the encoded instruction. So here change to I1 and I2 values via: 3863 // I1 = NOT(J1 EOR S); 3864 // I2 = NOT(J2 EOR S); 3865 // and build the imm32 with two trailing zeros as documented: 3866 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3867 unsigned S = (Val >> 23) & 1; 3868 unsigned J1 = (Val >> 22) & 1; 3869 unsigned J2 = (Val >> 21) & 1; 3870 unsigned I1 = !(J1 ^ S); 3871 unsigned I2 = !(J2 ^ S); 3872 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3873 int imm32 = SignExtend32<25>(tmp << 1); 3874 3875 if (!tryAddingSymbolicOperand(Address, 3876 (Address & ~2u) + imm32 + 4, 3877 true, 4, Inst, Decoder)) 3878 Inst.addOperand(MCOperand::CreateImm(imm32)); 3879 return MCDisassembler::Success; 3880 } 3881 3882 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3883 uint64_t Address, const void *Decoder) { 3884 if (Val == 0xA || Val == 0xB) 3885 return MCDisassembler::Fail; 3886 3887 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3888 .getFeatureBits(); 3889 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15)) 3890 return MCDisassembler::Fail; 3891 3892 Inst.addOperand(MCOperand::CreateImm(Val)); 3893 return MCDisassembler::Success; 3894 } 3895 3896 static DecodeStatus 3897 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3898 uint64_t Address, const void *Decoder) { 3899 DecodeStatus S = MCDisassembler::Success; 3900 3901 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3902 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3903 3904 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3905 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3906 return MCDisassembler::Fail; 3907 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3908 return MCDisassembler::Fail; 3909 return S; 3910 } 3911 3912 static DecodeStatus 3913 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3914 uint64_t Address, const void *Decoder) { 3915 DecodeStatus S = MCDisassembler::Success; 3916 3917 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3918 if (pred == 0xE || pred == 0xF) { 3919 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3920 switch (opc) { 3921 default: 3922 return MCDisassembler::Fail; 3923 case 0xf3bf8f4: 3924 Inst.setOpcode(ARM::t2DSB); 3925 break; 3926 case 0xf3bf8f5: 3927 Inst.setOpcode(ARM::t2DMB); 3928 break; 3929 case 0xf3bf8f6: 3930 Inst.setOpcode(ARM::t2ISB); 3931 break; 3932 } 3933 3934 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3935 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3936 } 3937 3938 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3939 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3940 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3941 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3942 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3943 3944 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3945 return MCDisassembler::Fail; 3946 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3947 return MCDisassembler::Fail; 3948 3949 return S; 3950 } 3951 3952 // Decode a shifted immediate operand. These basically consist 3953 // of an 8-bit value, and a 4-bit directive that specifies either 3954 // a splat operation or a rotation. 3955 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3956 uint64_t Address, const void *Decoder) { 3957 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3958 if (ctrl == 0) { 3959 unsigned byte = fieldFromInstruction(Val, 8, 2); 3960 unsigned imm = fieldFromInstruction(Val, 0, 8); 3961 switch (byte) { 3962 case 0: 3963 Inst.addOperand(MCOperand::CreateImm(imm)); 3964 break; 3965 case 1: 3966 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3967 break; 3968 case 2: 3969 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3970 break; 3971 case 3: 3972 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3973 (imm << 8) | imm)); 3974 break; 3975 } 3976 } else { 3977 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3978 unsigned rot = fieldFromInstruction(Val, 7, 5); 3979 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3980 Inst.addOperand(MCOperand::CreateImm(imm)); 3981 } 3982 3983 return MCDisassembler::Success; 3984 } 3985 3986 static DecodeStatus 3987 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3988 uint64_t Address, const void *Decoder){ 3989 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3990 true, 2, Inst, Decoder)) 3991 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3992 return MCDisassembler::Success; 3993 } 3994 3995 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3996 uint64_t Address, const void *Decoder){ 3997 // Val is passed in as S:J1:J2:imm10:imm11 3998 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3999 // the encoded instruction. So here change to I1 and I2 values via: 4000 // I1 = NOT(J1 EOR S); 4001 // I2 = NOT(J2 EOR S); 4002 // and build the imm32 with one trailing zero as documented: 4003 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4004 unsigned S = (Val >> 23) & 1; 4005 unsigned J1 = (Val >> 22) & 1; 4006 unsigned J2 = (Val >> 21) & 1; 4007 unsigned I1 = !(J1 ^ S); 4008 unsigned I2 = !(J2 ^ S); 4009 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4010 int imm32 = SignExtend32<25>(tmp << 1); 4011 4012 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4013 true, 4, Inst, Decoder)) 4014 Inst.addOperand(MCOperand::CreateImm(imm32)); 4015 return MCDisassembler::Success; 4016 } 4017 4018 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4019 uint64_t Address, const void *Decoder) { 4020 if (Val & ~0xf) 4021 return MCDisassembler::Fail; 4022 4023 Inst.addOperand(MCOperand::CreateImm(Val)); 4024 return MCDisassembler::Success; 4025 } 4026 4027 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4028 uint64_t Address, const void *Decoder) { 4029 if (Val & ~0xf) 4030 return MCDisassembler::Fail; 4031 4032 Inst.addOperand(MCOperand::CreateImm(Val)); 4033 return MCDisassembler::Success; 4034 } 4035 4036 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4037 uint64_t Address, const void *Decoder) { 4038 DecodeStatus S = MCDisassembler::Success; 4039 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 4040 .getFeatureBits(); 4041 if (FeatureBits & ARM::FeatureMClass) { 4042 unsigned ValLow = Val & 0xff; 4043 4044 // Validate the SYSm value first. 4045 switch (ValLow) { 4046 case 0: // apsr 4047 case 1: // iapsr 4048 case 2: // eapsr 4049 case 3: // xpsr 4050 case 5: // ipsr 4051 case 6: // epsr 4052 case 7: // iepsr 4053 case 8: // msp 4054 case 9: // psp 4055 case 16: // primask 4056 case 20: // control 4057 break; 4058 case 17: // basepri 4059 case 18: // basepri_max 4060 case 19: // faultmask 4061 if (!(FeatureBits & ARM::HasV7Ops)) 4062 // Values basepri, basepri_max and faultmask are only valid for v7m. 4063 return MCDisassembler::Fail; 4064 break; 4065 default: 4066 return MCDisassembler::Fail; 4067 } 4068 4069 if (Inst.getOpcode() == ARM::t2MSR_M) { 4070 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4071 if (!(FeatureBits & ARM::HasV7Ops)) { 4072 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4073 // unpredictable. 4074 if (Mask != 2) 4075 S = MCDisassembler::SoftFail; 4076 } 4077 else { 4078 // The ARMv7-M architecture stores an additional 2-bit mask value in 4079 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4080 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4081 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4082 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4083 // only if the processor includes the DSP extension. 4084 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4085 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1))) 4086 S = MCDisassembler::SoftFail; 4087 } 4088 } 4089 } else { 4090 // A/R class 4091 if (Val == 0) 4092 return MCDisassembler::Fail; 4093 } 4094 Inst.addOperand(MCOperand::CreateImm(Val)); 4095 return S; 4096 } 4097 4098 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4099 uint64_t Address, const void *Decoder) { 4100 4101 unsigned R = fieldFromInstruction(Val, 5, 1); 4102 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4103 4104 // The table of encodings for these banked registers comes from B9.2.3 of the 4105 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4106 // neater. So by fiat, these values are UNPREDICTABLE: 4107 if (!R) { 4108 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || 4109 SysM == 0x1a || SysM == 0x1b) 4110 return MCDisassembler::SoftFail; 4111 } else { 4112 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && 4113 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) 4114 return MCDisassembler::SoftFail; 4115 } 4116 4117 Inst.addOperand(MCOperand::CreateImm(Val)); 4118 return MCDisassembler::Success; 4119 } 4120 4121 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4122 uint64_t Address, const void *Decoder) { 4123 DecodeStatus S = MCDisassembler::Success; 4124 4125 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4126 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4127 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4128 4129 if (Rn == 0xF) 4130 S = MCDisassembler::SoftFail; 4131 4132 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4133 return MCDisassembler::Fail; 4134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4135 return MCDisassembler::Fail; 4136 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4137 return MCDisassembler::Fail; 4138 4139 return S; 4140 } 4141 4142 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4143 uint64_t Address, const void *Decoder){ 4144 DecodeStatus S = MCDisassembler::Success; 4145 4146 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4147 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4148 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4149 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4150 4151 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4152 return MCDisassembler::Fail; 4153 4154 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4155 S = MCDisassembler::SoftFail; 4156 4157 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4158 return MCDisassembler::Fail; 4159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4160 return MCDisassembler::Fail; 4161 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4162 return MCDisassembler::Fail; 4163 4164 return S; 4165 } 4166 4167 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4168 uint64_t Address, const void *Decoder) { 4169 DecodeStatus S = MCDisassembler::Success; 4170 4171 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4172 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4173 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4174 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4175 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4176 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4177 4178 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4179 4180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4181 return MCDisassembler::Fail; 4182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4183 return MCDisassembler::Fail; 4184 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4185 return MCDisassembler::Fail; 4186 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4187 return MCDisassembler::Fail; 4188 4189 return S; 4190 } 4191 4192 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4193 uint64_t Address, const void *Decoder) { 4194 DecodeStatus S = MCDisassembler::Success; 4195 4196 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4197 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4198 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4199 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4200 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4201 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4202 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4203 4204 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4205 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4206 4207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4208 return MCDisassembler::Fail; 4209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4210 return MCDisassembler::Fail; 4211 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4212 return MCDisassembler::Fail; 4213 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4214 return MCDisassembler::Fail; 4215 4216 return S; 4217 } 4218 4219 4220 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4221 uint64_t Address, const void *Decoder) { 4222 DecodeStatus S = MCDisassembler::Success; 4223 4224 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4225 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4226 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4227 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4228 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4229 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4230 4231 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4232 4233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4234 return MCDisassembler::Fail; 4235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4236 return MCDisassembler::Fail; 4237 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4238 return MCDisassembler::Fail; 4239 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4240 return MCDisassembler::Fail; 4241 4242 return S; 4243 } 4244 4245 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4246 uint64_t Address, const void *Decoder) { 4247 DecodeStatus S = MCDisassembler::Success; 4248 4249 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4250 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4251 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4252 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4253 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4254 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4255 4256 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4257 4258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4259 return MCDisassembler::Fail; 4260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4261 return MCDisassembler::Fail; 4262 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4263 return MCDisassembler::Fail; 4264 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4265 return MCDisassembler::Fail; 4266 4267 return S; 4268 } 4269 4270 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4271 uint64_t Address, const void *Decoder) { 4272 DecodeStatus S = MCDisassembler::Success; 4273 4274 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4275 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4276 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4277 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4278 unsigned size = fieldFromInstruction(Insn, 10, 2); 4279 4280 unsigned align = 0; 4281 unsigned index = 0; 4282 switch (size) { 4283 default: 4284 return MCDisassembler::Fail; 4285 case 0: 4286 if (fieldFromInstruction(Insn, 4, 1)) 4287 return MCDisassembler::Fail; // UNDEFINED 4288 index = fieldFromInstruction(Insn, 5, 3); 4289 break; 4290 case 1: 4291 if (fieldFromInstruction(Insn, 5, 1)) 4292 return MCDisassembler::Fail; // UNDEFINED 4293 index = fieldFromInstruction(Insn, 6, 2); 4294 if (fieldFromInstruction(Insn, 4, 1)) 4295 align = 2; 4296 break; 4297 case 2: 4298 if (fieldFromInstruction(Insn, 6, 1)) 4299 return MCDisassembler::Fail; // UNDEFINED 4300 index = fieldFromInstruction(Insn, 7, 1); 4301 4302 switch (fieldFromInstruction(Insn, 4, 2)) { 4303 case 0 : 4304 align = 0; break; 4305 case 3: 4306 align = 4; break; 4307 default: 4308 return MCDisassembler::Fail; 4309 } 4310 break; 4311 } 4312 4313 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4314 return MCDisassembler::Fail; 4315 if (Rm != 0xF) { // Writeback 4316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4317 return MCDisassembler::Fail; 4318 } 4319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4320 return MCDisassembler::Fail; 4321 Inst.addOperand(MCOperand::CreateImm(align)); 4322 if (Rm != 0xF) { 4323 if (Rm != 0xD) { 4324 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4325 return MCDisassembler::Fail; 4326 } else 4327 Inst.addOperand(MCOperand::CreateReg(0)); 4328 } 4329 4330 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4331 return MCDisassembler::Fail; 4332 Inst.addOperand(MCOperand::CreateImm(index)); 4333 4334 return S; 4335 } 4336 4337 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4338 uint64_t Address, const void *Decoder) { 4339 DecodeStatus S = MCDisassembler::Success; 4340 4341 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4342 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4343 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4344 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4345 unsigned size = fieldFromInstruction(Insn, 10, 2); 4346 4347 unsigned align = 0; 4348 unsigned index = 0; 4349 switch (size) { 4350 default: 4351 return MCDisassembler::Fail; 4352 case 0: 4353 if (fieldFromInstruction(Insn, 4, 1)) 4354 return MCDisassembler::Fail; // UNDEFINED 4355 index = fieldFromInstruction(Insn, 5, 3); 4356 break; 4357 case 1: 4358 if (fieldFromInstruction(Insn, 5, 1)) 4359 return MCDisassembler::Fail; // UNDEFINED 4360 index = fieldFromInstruction(Insn, 6, 2); 4361 if (fieldFromInstruction(Insn, 4, 1)) 4362 align = 2; 4363 break; 4364 case 2: 4365 if (fieldFromInstruction(Insn, 6, 1)) 4366 return MCDisassembler::Fail; // UNDEFINED 4367 index = fieldFromInstruction(Insn, 7, 1); 4368 4369 switch (fieldFromInstruction(Insn, 4, 2)) { 4370 case 0: 4371 align = 0; break; 4372 case 3: 4373 align = 4; break; 4374 default: 4375 return MCDisassembler::Fail; 4376 } 4377 break; 4378 } 4379 4380 if (Rm != 0xF) { // Writeback 4381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4382 return MCDisassembler::Fail; 4383 } 4384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4385 return MCDisassembler::Fail; 4386 Inst.addOperand(MCOperand::CreateImm(align)); 4387 if (Rm != 0xF) { 4388 if (Rm != 0xD) { 4389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4390 return MCDisassembler::Fail; 4391 } else 4392 Inst.addOperand(MCOperand::CreateReg(0)); 4393 } 4394 4395 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4396 return MCDisassembler::Fail; 4397 Inst.addOperand(MCOperand::CreateImm(index)); 4398 4399 return S; 4400 } 4401 4402 4403 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4404 uint64_t Address, const void *Decoder) { 4405 DecodeStatus S = MCDisassembler::Success; 4406 4407 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4408 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4409 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4410 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4411 unsigned size = fieldFromInstruction(Insn, 10, 2); 4412 4413 unsigned align = 0; 4414 unsigned index = 0; 4415 unsigned inc = 1; 4416 switch (size) { 4417 default: 4418 return MCDisassembler::Fail; 4419 case 0: 4420 index = fieldFromInstruction(Insn, 5, 3); 4421 if (fieldFromInstruction(Insn, 4, 1)) 4422 align = 2; 4423 break; 4424 case 1: 4425 index = fieldFromInstruction(Insn, 6, 2); 4426 if (fieldFromInstruction(Insn, 4, 1)) 4427 align = 4; 4428 if (fieldFromInstruction(Insn, 5, 1)) 4429 inc = 2; 4430 break; 4431 case 2: 4432 if (fieldFromInstruction(Insn, 5, 1)) 4433 return MCDisassembler::Fail; // UNDEFINED 4434 index = fieldFromInstruction(Insn, 7, 1); 4435 if (fieldFromInstruction(Insn, 4, 1) != 0) 4436 align = 8; 4437 if (fieldFromInstruction(Insn, 6, 1)) 4438 inc = 2; 4439 break; 4440 } 4441 4442 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4443 return MCDisassembler::Fail; 4444 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4445 return MCDisassembler::Fail; 4446 if (Rm != 0xF) { // Writeback 4447 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4448 return MCDisassembler::Fail; 4449 } 4450 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4451 return MCDisassembler::Fail; 4452 Inst.addOperand(MCOperand::CreateImm(align)); 4453 if (Rm != 0xF) { 4454 if (Rm != 0xD) { 4455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4456 return MCDisassembler::Fail; 4457 } else 4458 Inst.addOperand(MCOperand::CreateReg(0)); 4459 } 4460 4461 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4462 return MCDisassembler::Fail; 4463 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4464 return MCDisassembler::Fail; 4465 Inst.addOperand(MCOperand::CreateImm(index)); 4466 4467 return S; 4468 } 4469 4470 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4471 uint64_t Address, const void *Decoder) { 4472 DecodeStatus S = MCDisassembler::Success; 4473 4474 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4475 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4476 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4477 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4478 unsigned size = fieldFromInstruction(Insn, 10, 2); 4479 4480 unsigned align = 0; 4481 unsigned index = 0; 4482 unsigned inc = 1; 4483 switch (size) { 4484 default: 4485 return MCDisassembler::Fail; 4486 case 0: 4487 index = fieldFromInstruction(Insn, 5, 3); 4488 if (fieldFromInstruction(Insn, 4, 1)) 4489 align = 2; 4490 break; 4491 case 1: 4492 index = fieldFromInstruction(Insn, 6, 2); 4493 if (fieldFromInstruction(Insn, 4, 1)) 4494 align = 4; 4495 if (fieldFromInstruction(Insn, 5, 1)) 4496 inc = 2; 4497 break; 4498 case 2: 4499 if (fieldFromInstruction(Insn, 5, 1)) 4500 return MCDisassembler::Fail; // UNDEFINED 4501 index = fieldFromInstruction(Insn, 7, 1); 4502 if (fieldFromInstruction(Insn, 4, 1) != 0) 4503 align = 8; 4504 if (fieldFromInstruction(Insn, 6, 1)) 4505 inc = 2; 4506 break; 4507 } 4508 4509 if (Rm != 0xF) { // Writeback 4510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4511 return MCDisassembler::Fail; 4512 } 4513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4514 return MCDisassembler::Fail; 4515 Inst.addOperand(MCOperand::CreateImm(align)); 4516 if (Rm != 0xF) { 4517 if (Rm != 0xD) { 4518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4519 return MCDisassembler::Fail; 4520 } else 4521 Inst.addOperand(MCOperand::CreateReg(0)); 4522 } 4523 4524 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4525 return MCDisassembler::Fail; 4526 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4527 return MCDisassembler::Fail; 4528 Inst.addOperand(MCOperand::CreateImm(index)); 4529 4530 return S; 4531 } 4532 4533 4534 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4535 uint64_t Address, const void *Decoder) { 4536 DecodeStatus S = MCDisassembler::Success; 4537 4538 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4539 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4540 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4541 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4542 unsigned size = fieldFromInstruction(Insn, 10, 2); 4543 4544 unsigned align = 0; 4545 unsigned index = 0; 4546 unsigned inc = 1; 4547 switch (size) { 4548 default: 4549 return MCDisassembler::Fail; 4550 case 0: 4551 if (fieldFromInstruction(Insn, 4, 1)) 4552 return MCDisassembler::Fail; // UNDEFINED 4553 index = fieldFromInstruction(Insn, 5, 3); 4554 break; 4555 case 1: 4556 if (fieldFromInstruction(Insn, 4, 1)) 4557 return MCDisassembler::Fail; // UNDEFINED 4558 index = fieldFromInstruction(Insn, 6, 2); 4559 if (fieldFromInstruction(Insn, 5, 1)) 4560 inc = 2; 4561 break; 4562 case 2: 4563 if (fieldFromInstruction(Insn, 4, 2)) 4564 return MCDisassembler::Fail; // UNDEFINED 4565 index = fieldFromInstruction(Insn, 7, 1); 4566 if (fieldFromInstruction(Insn, 6, 1)) 4567 inc = 2; 4568 break; 4569 } 4570 4571 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4572 return MCDisassembler::Fail; 4573 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4574 return MCDisassembler::Fail; 4575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4576 return MCDisassembler::Fail; 4577 4578 if (Rm != 0xF) { // Writeback 4579 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4580 return MCDisassembler::Fail; 4581 } 4582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4583 return MCDisassembler::Fail; 4584 Inst.addOperand(MCOperand::CreateImm(align)); 4585 if (Rm != 0xF) { 4586 if (Rm != 0xD) { 4587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4588 return MCDisassembler::Fail; 4589 } else 4590 Inst.addOperand(MCOperand::CreateReg(0)); 4591 } 4592 4593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4594 return MCDisassembler::Fail; 4595 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4596 return MCDisassembler::Fail; 4597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4598 return MCDisassembler::Fail; 4599 Inst.addOperand(MCOperand::CreateImm(index)); 4600 4601 return S; 4602 } 4603 4604 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4605 uint64_t Address, const void *Decoder) { 4606 DecodeStatus S = MCDisassembler::Success; 4607 4608 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4609 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4610 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4611 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4612 unsigned size = fieldFromInstruction(Insn, 10, 2); 4613 4614 unsigned align = 0; 4615 unsigned index = 0; 4616 unsigned inc = 1; 4617 switch (size) { 4618 default: 4619 return MCDisassembler::Fail; 4620 case 0: 4621 if (fieldFromInstruction(Insn, 4, 1)) 4622 return MCDisassembler::Fail; // UNDEFINED 4623 index = fieldFromInstruction(Insn, 5, 3); 4624 break; 4625 case 1: 4626 if (fieldFromInstruction(Insn, 4, 1)) 4627 return MCDisassembler::Fail; // UNDEFINED 4628 index = fieldFromInstruction(Insn, 6, 2); 4629 if (fieldFromInstruction(Insn, 5, 1)) 4630 inc = 2; 4631 break; 4632 case 2: 4633 if (fieldFromInstruction(Insn, 4, 2)) 4634 return MCDisassembler::Fail; // UNDEFINED 4635 index = fieldFromInstruction(Insn, 7, 1); 4636 if (fieldFromInstruction(Insn, 6, 1)) 4637 inc = 2; 4638 break; 4639 } 4640 4641 if (Rm != 0xF) { // Writeback 4642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4643 return MCDisassembler::Fail; 4644 } 4645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4646 return MCDisassembler::Fail; 4647 Inst.addOperand(MCOperand::CreateImm(align)); 4648 if (Rm != 0xF) { 4649 if (Rm != 0xD) { 4650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4651 return MCDisassembler::Fail; 4652 } else 4653 Inst.addOperand(MCOperand::CreateReg(0)); 4654 } 4655 4656 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4657 return MCDisassembler::Fail; 4658 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4659 return MCDisassembler::Fail; 4660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4661 return MCDisassembler::Fail; 4662 Inst.addOperand(MCOperand::CreateImm(index)); 4663 4664 return S; 4665 } 4666 4667 4668 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4669 uint64_t Address, const void *Decoder) { 4670 DecodeStatus S = MCDisassembler::Success; 4671 4672 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4673 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4674 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4675 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4676 unsigned size = fieldFromInstruction(Insn, 10, 2); 4677 4678 unsigned align = 0; 4679 unsigned index = 0; 4680 unsigned inc = 1; 4681 switch (size) { 4682 default: 4683 return MCDisassembler::Fail; 4684 case 0: 4685 if (fieldFromInstruction(Insn, 4, 1)) 4686 align = 4; 4687 index = fieldFromInstruction(Insn, 5, 3); 4688 break; 4689 case 1: 4690 if (fieldFromInstruction(Insn, 4, 1)) 4691 align = 8; 4692 index = fieldFromInstruction(Insn, 6, 2); 4693 if (fieldFromInstruction(Insn, 5, 1)) 4694 inc = 2; 4695 break; 4696 case 2: 4697 switch (fieldFromInstruction(Insn, 4, 2)) { 4698 case 0: 4699 align = 0; break; 4700 case 3: 4701 return MCDisassembler::Fail; 4702 default: 4703 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4704 } 4705 4706 index = fieldFromInstruction(Insn, 7, 1); 4707 if (fieldFromInstruction(Insn, 6, 1)) 4708 inc = 2; 4709 break; 4710 } 4711 4712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4713 return MCDisassembler::Fail; 4714 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4715 return MCDisassembler::Fail; 4716 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4717 return MCDisassembler::Fail; 4718 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4719 return MCDisassembler::Fail; 4720 4721 if (Rm != 0xF) { // Writeback 4722 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4723 return MCDisassembler::Fail; 4724 } 4725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4726 return MCDisassembler::Fail; 4727 Inst.addOperand(MCOperand::CreateImm(align)); 4728 if (Rm != 0xF) { 4729 if (Rm != 0xD) { 4730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4731 return MCDisassembler::Fail; 4732 } else 4733 Inst.addOperand(MCOperand::CreateReg(0)); 4734 } 4735 4736 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4737 return MCDisassembler::Fail; 4738 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4739 return MCDisassembler::Fail; 4740 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4741 return MCDisassembler::Fail; 4742 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4743 return MCDisassembler::Fail; 4744 Inst.addOperand(MCOperand::CreateImm(index)); 4745 4746 return S; 4747 } 4748 4749 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4750 uint64_t Address, const void *Decoder) { 4751 DecodeStatus S = MCDisassembler::Success; 4752 4753 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4754 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4755 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4756 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4757 unsigned size = fieldFromInstruction(Insn, 10, 2); 4758 4759 unsigned align = 0; 4760 unsigned index = 0; 4761 unsigned inc = 1; 4762 switch (size) { 4763 default: 4764 return MCDisassembler::Fail; 4765 case 0: 4766 if (fieldFromInstruction(Insn, 4, 1)) 4767 align = 4; 4768 index = fieldFromInstruction(Insn, 5, 3); 4769 break; 4770 case 1: 4771 if (fieldFromInstruction(Insn, 4, 1)) 4772 align = 8; 4773 index = fieldFromInstruction(Insn, 6, 2); 4774 if (fieldFromInstruction(Insn, 5, 1)) 4775 inc = 2; 4776 break; 4777 case 2: 4778 switch (fieldFromInstruction(Insn, 4, 2)) { 4779 case 0: 4780 align = 0; break; 4781 case 3: 4782 return MCDisassembler::Fail; 4783 default: 4784 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4785 } 4786 4787 index = fieldFromInstruction(Insn, 7, 1); 4788 if (fieldFromInstruction(Insn, 6, 1)) 4789 inc = 2; 4790 break; 4791 } 4792 4793 if (Rm != 0xF) { // Writeback 4794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4795 return MCDisassembler::Fail; 4796 } 4797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4798 return MCDisassembler::Fail; 4799 Inst.addOperand(MCOperand::CreateImm(align)); 4800 if (Rm != 0xF) { 4801 if (Rm != 0xD) { 4802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4803 return MCDisassembler::Fail; 4804 } else 4805 Inst.addOperand(MCOperand::CreateReg(0)); 4806 } 4807 4808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4809 return MCDisassembler::Fail; 4810 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4811 return MCDisassembler::Fail; 4812 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4813 return MCDisassembler::Fail; 4814 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4815 return MCDisassembler::Fail; 4816 Inst.addOperand(MCOperand::CreateImm(index)); 4817 4818 return S; 4819 } 4820 4821 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4822 uint64_t Address, const void *Decoder) { 4823 DecodeStatus S = MCDisassembler::Success; 4824 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4825 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4826 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4827 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4828 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4829 4830 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4831 S = MCDisassembler::SoftFail; 4832 4833 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4834 return MCDisassembler::Fail; 4835 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4836 return MCDisassembler::Fail; 4837 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4838 return MCDisassembler::Fail; 4839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4840 return MCDisassembler::Fail; 4841 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4842 return MCDisassembler::Fail; 4843 4844 return S; 4845 } 4846 4847 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4848 uint64_t Address, const void *Decoder) { 4849 DecodeStatus S = MCDisassembler::Success; 4850 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4851 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4852 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4853 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4854 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4855 4856 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4857 S = MCDisassembler::SoftFail; 4858 4859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4860 return MCDisassembler::Fail; 4861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4862 return MCDisassembler::Fail; 4863 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4864 return MCDisassembler::Fail; 4865 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4866 return MCDisassembler::Fail; 4867 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4868 return MCDisassembler::Fail; 4869 4870 return S; 4871 } 4872 4873 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4874 uint64_t Address, const void *Decoder) { 4875 DecodeStatus S = MCDisassembler::Success; 4876 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4877 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4878 4879 if (pred == 0xF) { 4880 pred = 0xE; 4881 S = MCDisassembler::SoftFail; 4882 } 4883 4884 if (mask == 0x0) 4885 return MCDisassembler::Fail; 4886 4887 Inst.addOperand(MCOperand::CreateImm(pred)); 4888 Inst.addOperand(MCOperand::CreateImm(mask)); 4889 return S; 4890 } 4891 4892 static DecodeStatus 4893 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4894 uint64_t Address, const void *Decoder) { 4895 DecodeStatus S = MCDisassembler::Success; 4896 4897 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4898 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4899 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4900 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4901 unsigned W = fieldFromInstruction(Insn, 21, 1); 4902 unsigned U = fieldFromInstruction(Insn, 23, 1); 4903 unsigned P = fieldFromInstruction(Insn, 24, 1); 4904 bool writeback = (W == 1) | (P == 0); 4905 4906 addr |= (U << 8) | (Rn << 9); 4907 4908 if (writeback && (Rn == Rt || Rn == Rt2)) 4909 Check(S, MCDisassembler::SoftFail); 4910 if (Rt == Rt2) 4911 Check(S, MCDisassembler::SoftFail); 4912 4913 // Rt 4914 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4915 return MCDisassembler::Fail; 4916 // Rt2 4917 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4918 return MCDisassembler::Fail; 4919 // Writeback operand 4920 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4921 return MCDisassembler::Fail; 4922 // addr 4923 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4924 return MCDisassembler::Fail; 4925 4926 return S; 4927 } 4928 4929 static DecodeStatus 4930 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4931 uint64_t Address, const void *Decoder) { 4932 DecodeStatus S = MCDisassembler::Success; 4933 4934 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4935 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4936 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4937 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4938 unsigned W = fieldFromInstruction(Insn, 21, 1); 4939 unsigned U = fieldFromInstruction(Insn, 23, 1); 4940 unsigned P = fieldFromInstruction(Insn, 24, 1); 4941 bool writeback = (W == 1) | (P == 0); 4942 4943 addr |= (U << 8) | (Rn << 9); 4944 4945 if (writeback && (Rn == Rt || Rn == Rt2)) 4946 Check(S, MCDisassembler::SoftFail); 4947 4948 // Writeback operand 4949 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4950 return MCDisassembler::Fail; 4951 // Rt 4952 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4953 return MCDisassembler::Fail; 4954 // Rt2 4955 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4956 return MCDisassembler::Fail; 4957 // addr 4958 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4959 return MCDisassembler::Fail; 4960 4961 return S; 4962 } 4963 4964 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4965 uint64_t Address, const void *Decoder) { 4966 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4967 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4968 if (sign1 != sign2) return MCDisassembler::Fail; 4969 4970 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4971 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4972 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4973 Val |= sign1 << 12; 4974 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4975 4976 return MCDisassembler::Success; 4977 } 4978 4979 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4980 uint64_t Address, 4981 const void *Decoder) { 4982 DecodeStatus S = MCDisassembler::Success; 4983 4984 // Shift of "asr #32" is not allowed in Thumb2 mode. 4985 if (Val == 0x20) S = MCDisassembler::SoftFail; 4986 Inst.addOperand(MCOperand::CreateImm(Val)); 4987 return S; 4988 } 4989 4990 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4991 uint64_t Address, const void *Decoder) { 4992 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4993 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4994 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4995 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4996 4997 if (pred == 0xF) 4998 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4999 5000 DecodeStatus S = MCDisassembler::Success; 5001 5002 if (Rt == Rn || Rn == Rt2) 5003 S = MCDisassembler::SoftFail; 5004 5005 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5006 return MCDisassembler::Fail; 5007 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5008 return MCDisassembler::Fail; 5009 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5010 return MCDisassembler::Fail; 5011 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5012 return MCDisassembler::Fail; 5013 5014 return S; 5015 } 5016 5017 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5018 uint64_t Address, const void *Decoder) { 5019 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5020 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5021 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5022 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5023 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5024 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5025 unsigned op = fieldFromInstruction(Insn, 5, 1); 5026 5027 DecodeStatus S = MCDisassembler::Success; 5028 5029 // VMOVv2f32 is ambiguous with these decodings. 5030 if (!(imm & 0x38) && cmode == 0xF) { 5031 if (op == 1) return MCDisassembler::Fail; 5032 Inst.setOpcode(ARM::VMOVv2f32); 5033 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5034 } 5035 5036 if (!(imm & 0x20)) return MCDisassembler::Fail; 5037 5038 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5039 return MCDisassembler::Fail; 5040 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5041 return MCDisassembler::Fail; 5042 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 5043 5044 return S; 5045 } 5046 5047 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5048 uint64_t Address, const void *Decoder) { 5049 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5050 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5051 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5052 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5053 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5054 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5055 unsigned op = fieldFromInstruction(Insn, 5, 1); 5056 5057 DecodeStatus S = MCDisassembler::Success; 5058 5059 // VMOVv4f32 is ambiguous with these decodings. 5060 if (!(imm & 0x38) && cmode == 0xF) { 5061 if (op == 1) return MCDisassembler::Fail; 5062 Inst.setOpcode(ARM::VMOVv4f32); 5063 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5064 } 5065 5066 if (!(imm & 0x20)) return MCDisassembler::Fail; 5067 5068 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5069 return MCDisassembler::Fail; 5070 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5071 return MCDisassembler::Fail; 5072 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 5073 5074 return S; 5075 } 5076 5077 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5078 uint64_t Address, const void *Decoder) { 5079 DecodeStatus S = MCDisassembler::Success; 5080 5081 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5082 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5083 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5084 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5085 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5086 5087 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5088 S = MCDisassembler::SoftFail; 5089 5090 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5091 return MCDisassembler::Fail; 5092 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5093 return MCDisassembler::Fail; 5094 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5095 return MCDisassembler::Fail; 5096 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5097 return MCDisassembler::Fail; 5098 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5099 return MCDisassembler::Fail; 5100 5101 return S; 5102 } 5103 5104 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 5105 uint64_t Address, const void *Decoder) { 5106 5107 DecodeStatus S = MCDisassembler::Success; 5108 5109 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5110 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5111 unsigned cop = fieldFromInstruction(Val, 8, 4); 5112 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5113 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5114 5115 if ((cop & ~0x1) == 0xa) 5116 return MCDisassembler::Fail; 5117 5118 if (Rt == Rt2) 5119 S = MCDisassembler::SoftFail; 5120 5121 Inst.addOperand(MCOperand::CreateImm(cop)); 5122 Inst.addOperand(MCOperand::CreateImm(opc1)); 5123 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5124 return MCDisassembler::Fail; 5125 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5126 return MCDisassembler::Fail; 5127 Inst.addOperand(MCOperand::CreateImm(CRm)); 5128 5129 return S; 5130 } 5131 5132