1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 137 uint64_t Address, const void *Decoder); 138 static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn, 139 uint64_t Address, const void *Decoder); 140 141 142 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 143 uint64_t Address, const void *Decoder); 144 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 145 uint64_t Address, const void *Decoder); 146 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 147 uint64_t Address, const void *Decoder); 148 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 149 uint64_t Address, const void *Decoder); 150 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 151 uint64_t Address, const void *Decoder); 152 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 153 uint64_t Address, const void *Decoder); 154 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 155 uint64_t Address, const void *Decoder); 156 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 157 uint64_t Address, const void *Decoder); 158 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 159 uint64_t Address, const void *Decoder); 160 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 161 uint64_t Address, const void *Decoder); 162 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 163 uint64_t Address, const void *Decoder); 164 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 167 uint64_t Address, const void *Decoder); 168 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 169 uint64_t Address, const void *Decoder); 170 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 171 uint64_t Address, const void *Decoder); 172 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 173 uint64_t Address, const void *Decoder); 174 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 175 uint64_t Address, const void *Decoder); 176 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 177 uint64_t Address, const void *Decoder); 178 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 191 #include "ARMGenDisassemblerTables.inc" 192 #include "ARMGenInstrInfo.inc" 193 #include "ARMGenEDInfo.inc" 194 195 using namespace llvm; 196 197 static MCDisassembler *createARMDisassembler(const Target &T) { 198 return new ARMDisassembler; 199 } 200 201 static MCDisassembler *createThumbDisassembler(const Target &T) { 202 return new ThumbDisassembler; 203 } 204 205 EDInstInfo *ARMDisassembler::getEDInfo() const { 206 return instInfoARM; 207 } 208 209 EDInstInfo *ThumbDisassembler::getEDInfo() const { 210 return instInfoARM; 211 } 212 213 214 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 215 const MemoryObject &Region, 216 uint64_t Address,raw_ostream &os) const { 217 uint8_t bytes[4]; 218 219 // We want to read exactly 4 bytes of data. 220 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 221 return false; 222 223 // Encoded as a small-endian 32-bit word in the stream. 224 uint32_t insn = (bytes[3] << 24) | 225 (bytes[2] << 16) | 226 (bytes[1] << 8) | 227 (bytes[0] << 0); 228 229 // Calling the auto-generated decoder function. 230 bool result = decodeARMInstruction32(MI, insn, Address, this); 231 if (result) { 232 Size = 4; 233 return true; 234 } 235 236 // Instructions that are shared between ARM and Thumb modes. 237 // FIXME: This shouldn't really exist. It's an artifact of the 238 // fact that we fail to encode a few instructions properly for Thumb. 239 MI.clear(); 240 result = decodeCommonInstruction32(MI, insn, Address, this); 241 if (result) { 242 Size = 4; 243 return true; 244 } 245 246 // VFP and NEON instructions, similarly, are shared between ARM 247 // and Thumb modes. 248 MI.clear(); 249 result = decodeVFPInstruction32(MI, insn, Address, this); 250 if (result) { 251 Size = 4; 252 return true; 253 } 254 255 MI.clear(); 256 result = decodeNEONDataInstruction32(MI, insn, Address, this); 257 if (result) { 258 Size = 4; 259 // Add a fake predicate operand, because we share these instruction 260 // definitions with Thumb2 where these instructions are predicable. 261 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 262 return true; 263 } 264 265 MI.clear(); 266 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 267 if (result) { 268 Size = 4; 269 // Add a fake predicate operand, because we share these instruction 270 // definitions with Thumb2 where these instructions are predicable. 271 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 272 return true; 273 } 274 275 MI.clear(); 276 result = decodeNEONDupInstruction32(MI, insn, Address, this); 277 if (result) { 278 Size = 4; 279 // Add a fake predicate operand, because we share these instruction 280 // definitions with Thumb2 where these instructions are predicable. 281 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 282 return true; 283 } 284 285 MI.clear(); 286 287 return false; 288 } 289 290 namespace llvm { 291 extern MCInstrDesc ARMInsts[]; 292 } 293 294 // Thumb1 instructions don't have explicit S bits. Rather, they 295 // implicitly set CPSR. Since it's not represented in the encoding, the 296 // auto-generated decoder won't inject the CPSR operand. We need to fix 297 // that as a post-pass. 298 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 299 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 300 MCInst::iterator I = MI.begin(); 301 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 302 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 303 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 304 return; 305 } 306 } 307 308 if (OpInfo[MI.size()].isOptionalDef() && 309 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 310 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 311 } 312 313 // Most Thumb instructions don't have explicit predicates in the 314 // encoding, but rather get their predicates from IT context. We need 315 // to fix up the predicate operands using this context information as a 316 // post-pass. 317 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 318 // A few instructions actually have predicates encoded in them. Don't 319 // try to overwrite it if we're seeing one of those. 320 switch (MI.getOpcode()) { 321 case ARM::tBcc: 322 case ARM::t2Bcc: 323 return; 324 default: 325 break; 326 } 327 328 // If we're in an IT block, base the predicate on that. Otherwise, 329 // assume a predicate of AL. 330 unsigned CC; 331 if (!ITBlock.empty()) { 332 CC = ITBlock.back(); 333 ITBlock.pop_back(); 334 } else 335 CC = ARMCC::AL; 336 337 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 338 MCInst::iterator I = MI.begin(); 339 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 340 if (OpInfo[i].isPredicate()) { 341 I = MI.insert(I, MCOperand::CreateImm(CC)); 342 ++I; 343 if (CC == ARMCC::AL) 344 MI.insert(I, MCOperand::CreateReg(0)); 345 else 346 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 347 return; 348 } 349 } 350 351 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 352 if (CC == ARMCC::AL) 353 MI.insert(MI.end(), MCOperand::CreateReg(0)); 354 else 355 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 356 } 357 358 // Thumb VFP instructions are a special case. Because we share their 359 // encodings between ARM and Thumb modes, and they are predicable in ARM 360 // mode, the auto-generated decoder will give them an (incorrect) 361 // predicate operand. We need to rewrite these operands based on the IT 362 // context as a post-pass. 363 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 364 unsigned CC; 365 if (!ITBlock.empty()) { 366 CC = ITBlock.back(); 367 ITBlock.pop_back(); 368 } else 369 CC = ARMCC::AL; 370 371 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 372 MCInst::iterator I = MI.begin(); 373 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 374 if (OpInfo[i].isPredicate() ) { 375 I->setImm(CC); 376 ++I; 377 if (CC == ARMCC::AL) 378 I->setReg(0); 379 else 380 I->setReg(ARM::CPSR); 381 return; 382 } 383 } 384 } 385 386 387 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 388 const MemoryObject &Region, 389 uint64_t Address,raw_ostream &os) const { 390 uint8_t bytes[4]; 391 392 // We want to read exactly 2 bytes of data. 393 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 394 return false; 395 396 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 397 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 398 if (result) { 399 Size = 2; 400 bool InITBlock = !ITBlock.empty(); 401 AddThumbPredicate(MI); 402 AddThumb1SBit(MI, InITBlock); 403 return true; 404 } 405 406 MI.clear(); 407 result = decodeThumb2Instruction16(MI, insn16, Address, this); 408 if (result) { 409 Size = 2; 410 AddThumbPredicate(MI); 411 412 // If we find an IT instruction, we need to parse its condition 413 // code and mask operands so that we can apply them correctly 414 // to the subsequent instructions. 415 if (MI.getOpcode() == ARM::t2IT) { 416 unsigned firstcond = MI.getOperand(0).getImm(); 417 uint32_t mask = MI.getOperand(1).getImm(); 418 unsigned zeros = CountTrailingZeros_32(mask); 419 mask >>= zeros+1; 420 421 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 422 if (firstcond ^ (mask & 1)) 423 ITBlock.push_back(firstcond ^ 1); 424 else 425 ITBlock.push_back(firstcond); 426 mask >>= 1; 427 } 428 ITBlock.push_back(firstcond); 429 } 430 431 return true; 432 } 433 434 // We want to read exactly 4 bytes of data. 435 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 436 return false; 437 438 uint32_t insn32 = (bytes[3] << 8) | 439 (bytes[2] << 0) | 440 (bytes[1] << 24) | 441 (bytes[0] << 16); 442 MI.clear(); 443 result = decodeThumbInstruction32(MI, insn32, Address, this); 444 if (result) { 445 Size = 4; 446 bool InITBlock = ITBlock.size(); 447 AddThumbPredicate(MI); 448 AddThumb1SBit(MI, InITBlock); 449 return true; 450 } 451 452 MI.clear(); 453 result = decodeThumb2Instruction32(MI, insn32, Address, this); 454 if (result) { 455 Size = 4; 456 AddThumbPredicate(MI); 457 return true; 458 } 459 460 MI.clear(); 461 result = decodeCommonInstruction32(MI, insn32, Address, this); 462 if (result) { 463 Size = 4; 464 AddThumbPredicate(MI); 465 return true; 466 } 467 468 MI.clear(); 469 result = decodeVFPInstruction32(MI, insn32, Address, this); 470 if (result) { 471 Size = 4; 472 UpdateThumbVFPPredicate(MI); 473 return true; 474 } 475 476 MI.clear(); 477 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 478 uint32_t NEONDataInsn = insn32; 479 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 480 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 481 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 482 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 483 if (result) { 484 Size = 4; 485 AddThumbPredicate(MI); 486 return true; 487 } 488 } 489 490 MI.clear(); 491 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); 492 if (result) { 493 Size = 4; 494 AddThumbPredicate(MI); 495 return true; 496 } 497 498 MI.clear(); 499 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 500 if (result) { 501 Size = 4; 502 AddThumbPredicate(MI); 503 return true; 504 } 505 506 return false; 507 } 508 509 510 extern "C" void LLVMInitializeARMDisassembler() { 511 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 512 createARMDisassembler); 513 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 514 createThumbDisassembler); 515 } 516 517 static const unsigned GPRDecoderTable[] = { 518 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 519 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 520 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 521 ARM::R12, ARM::SP, ARM::LR, ARM::PC 522 }; 523 524 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 525 uint64_t Address, const void *Decoder) { 526 if (RegNo > 15) 527 return false; 528 529 unsigned Register = GPRDecoderTable[RegNo]; 530 Inst.addOperand(MCOperand::CreateReg(Register)); 531 return true; 532 } 533 534 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 535 uint64_t Address, const void *Decoder) { 536 if (RegNo == 15) return false; 537 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 538 } 539 540 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 541 uint64_t Address, const void *Decoder) { 542 if (RegNo > 7) 543 return false; 544 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 545 } 546 547 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 548 uint64_t Address, const void *Decoder) { 549 unsigned Register = 0; 550 switch (RegNo) { 551 case 0: 552 Register = ARM::R0; 553 break; 554 case 1: 555 Register = ARM::R1; 556 break; 557 case 2: 558 Register = ARM::R2; 559 break; 560 case 3: 561 Register = ARM::R3; 562 break; 563 case 9: 564 Register = ARM::R9; 565 break; 566 case 12: 567 Register = ARM::R12; 568 break; 569 default: 570 return false; 571 } 572 573 Inst.addOperand(MCOperand::CreateReg(Register)); 574 return true; 575 } 576 577 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 578 uint64_t Address, const void *Decoder) { 579 if (RegNo == 13 || RegNo == 15) return false; 580 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 581 } 582 583 static const unsigned SPRDecoderTable[] = { 584 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 585 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 586 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 587 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 588 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 589 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 590 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 591 ARM::S28, ARM::S29, ARM::S30, ARM::S31 592 }; 593 594 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 595 uint64_t Address, const void *Decoder) { 596 if (RegNo > 31) 597 return false; 598 599 unsigned Register = SPRDecoderTable[RegNo]; 600 Inst.addOperand(MCOperand::CreateReg(Register)); 601 return true; 602 } 603 604 static const unsigned DPRDecoderTable[] = { 605 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 606 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 607 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 608 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 609 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 610 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 611 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 612 ARM::D28, ARM::D29, ARM::D30, ARM::D31 613 }; 614 615 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 616 uint64_t Address, const void *Decoder) { 617 if (RegNo > 31) 618 return false; 619 620 unsigned Register = DPRDecoderTable[RegNo]; 621 Inst.addOperand(MCOperand::CreateReg(Register)); 622 return true; 623 } 624 625 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 626 uint64_t Address, const void *Decoder) { 627 if (RegNo > 7) 628 return false; 629 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 630 } 631 632 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 633 uint64_t Address, const void *Decoder) { 634 if (RegNo > 15) 635 return false; 636 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 637 } 638 639 static const unsigned QPRDecoderTable[] = { 640 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 641 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 642 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 643 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 644 }; 645 646 647 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 648 uint64_t Address, const void *Decoder) { 649 if (RegNo > 31) 650 return false; 651 RegNo >>= 1; 652 653 unsigned Register = QPRDecoderTable[RegNo]; 654 Inst.addOperand(MCOperand::CreateReg(Register)); 655 return true; 656 } 657 658 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 659 uint64_t Address, const void *Decoder) { 660 if (Val == 0xF) return false; 661 // AL predicate is not allowed on Thumb1 branches. 662 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 663 return false; 664 Inst.addOperand(MCOperand::CreateImm(Val)); 665 if (Val == ARMCC::AL) { 666 Inst.addOperand(MCOperand::CreateReg(0)); 667 } else 668 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 669 return true; 670 } 671 672 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 673 uint64_t Address, const void *Decoder) { 674 if (Val) 675 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 676 else 677 Inst.addOperand(MCOperand::CreateReg(0)); 678 return true; 679 } 680 681 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 682 uint64_t Address, const void *Decoder) { 683 uint32_t imm = Val & 0xFF; 684 uint32_t rot = (Val & 0xF00) >> 7; 685 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 686 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 687 return true; 688 } 689 690 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 691 uint64_t Address, const void *Decoder) { 692 Val <<= 2; 693 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 694 return true; 695 } 696 697 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 698 uint64_t Address, const void *Decoder) { 699 700 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 701 unsigned type = fieldFromInstruction32(Val, 5, 2); 702 unsigned imm = fieldFromInstruction32(Val, 7, 5); 703 704 // Register-immediate 705 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 706 707 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 708 switch (type) { 709 case 0: 710 Shift = ARM_AM::lsl; 711 break; 712 case 1: 713 Shift = ARM_AM::lsr; 714 break; 715 case 2: 716 Shift = ARM_AM::asr; 717 break; 718 case 3: 719 Shift = ARM_AM::ror; 720 break; 721 } 722 723 if (Shift == ARM_AM::ror && imm == 0) 724 Shift = ARM_AM::rrx; 725 726 unsigned Op = Shift | (imm << 3); 727 Inst.addOperand(MCOperand::CreateImm(Op)); 728 729 return true; 730 } 731 732 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 733 uint64_t Address, const void *Decoder) { 734 735 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 736 unsigned type = fieldFromInstruction32(Val, 5, 2); 737 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 738 739 // Register-register 740 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 741 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 742 743 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 744 switch (type) { 745 case 0: 746 Shift = ARM_AM::lsl; 747 break; 748 case 1: 749 Shift = ARM_AM::lsr; 750 break; 751 case 2: 752 Shift = ARM_AM::asr; 753 break; 754 case 3: 755 Shift = ARM_AM::ror; 756 break; 757 } 758 759 Inst.addOperand(MCOperand::CreateImm(Shift)); 760 761 return true; 762 } 763 764 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 765 uint64_t Address, const void *Decoder) { 766 // Empty register lists are not allowed. 767 if (CountPopulation_32(Val) == 0) return false; 768 for (unsigned i = 0; i < 16; ++i) { 769 if (Val & (1 << i)) { 770 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 771 } 772 } 773 774 return true; 775 } 776 777 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 778 uint64_t Address, const void *Decoder) { 779 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 780 unsigned regs = Val & 0xFF; 781 782 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 783 for (unsigned i = 0; i < (regs - 1); ++i) { 784 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 785 } 786 787 return true; 788 } 789 790 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 791 uint64_t Address, const void *Decoder) { 792 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 793 unsigned regs = (Val & 0xFF) / 2; 794 795 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 796 for (unsigned i = 0; i < (regs - 1); ++i) { 797 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 798 } 799 800 return true; 801 } 802 803 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 804 uint64_t Address, const void *Decoder) { 805 // This operand encodes a mask of contiguous zeros between a specified MSB 806 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 807 // the mask of all bits LSB-and-lower, and then xor them to create 808 // the mask of that's all ones on [msb, lsb]. Finally we not it to 809 // create the final mask. 810 unsigned msb = fieldFromInstruction32(Val, 5, 5); 811 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 812 uint32_t msb_mask = (1 << (msb+1)) - 1; 813 uint32_t lsb_mask = (1 << lsb) - 1; 814 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 815 return true; 816 } 817 818 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 819 uint64_t Address, const void *Decoder) { 820 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 821 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 822 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 823 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 824 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 825 unsigned U = fieldFromInstruction32(Insn, 23, 1); 826 827 switch (Inst.getOpcode()) { 828 case ARM::LDC_OFFSET: 829 case ARM::LDC_PRE: 830 case ARM::LDC_POST: 831 case ARM::LDC_OPTION: 832 case ARM::LDCL_OFFSET: 833 case ARM::LDCL_PRE: 834 case ARM::LDCL_POST: 835 case ARM::LDCL_OPTION: 836 case ARM::STC_OFFSET: 837 case ARM::STC_PRE: 838 case ARM::STC_POST: 839 case ARM::STC_OPTION: 840 case ARM::STCL_OFFSET: 841 case ARM::STCL_PRE: 842 case ARM::STCL_POST: 843 case ARM::STCL_OPTION: 844 if (coproc == 0xA || coproc == 0xB) 845 return false; 846 break; 847 default: 848 break; 849 } 850 851 Inst.addOperand(MCOperand::CreateImm(coproc)); 852 Inst.addOperand(MCOperand::CreateImm(CRd)); 853 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 854 switch (Inst.getOpcode()) { 855 case ARM::LDC_OPTION: 856 case ARM::LDCL_OPTION: 857 case ARM::LDC2_OPTION: 858 case ARM::LDC2L_OPTION: 859 case ARM::STC_OPTION: 860 case ARM::STCL_OPTION: 861 case ARM::STC2_OPTION: 862 case ARM::STC2L_OPTION: 863 case ARM::LDCL_POST: 864 case ARM::STCL_POST: 865 break; 866 default: 867 Inst.addOperand(MCOperand::CreateReg(0)); 868 break; 869 } 870 871 unsigned P = fieldFromInstruction32(Insn, 24, 1); 872 unsigned W = fieldFromInstruction32(Insn, 21, 1); 873 874 bool writeback = (P == 0) || (W == 1); 875 unsigned idx_mode = 0; 876 if (P && writeback) 877 idx_mode = ARMII::IndexModePre; 878 else if (!P && writeback) 879 idx_mode = ARMII::IndexModePost; 880 881 switch (Inst.getOpcode()) { 882 case ARM::LDCL_POST: 883 case ARM::STCL_POST: 884 imm |= U << 8; 885 case ARM::LDC_OPTION: 886 case ARM::LDCL_OPTION: 887 case ARM::LDC2_OPTION: 888 case ARM::LDC2L_OPTION: 889 case ARM::STC_OPTION: 890 case ARM::STCL_OPTION: 891 case ARM::STC2_OPTION: 892 case ARM::STC2L_OPTION: 893 Inst.addOperand(MCOperand::CreateImm(imm)); 894 break; 895 default: 896 if (U) 897 Inst.addOperand(MCOperand::CreateImm( 898 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 899 else 900 Inst.addOperand(MCOperand::CreateImm( 901 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 902 break; 903 } 904 905 switch (Inst.getOpcode()) { 906 case ARM::LDC_OFFSET: 907 case ARM::LDC_PRE: 908 case ARM::LDC_POST: 909 case ARM::LDC_OPTION: 910 case ARM::LDCL_OFFSET: 911 case ARM::LDCL_PRE: 912 case ARM::LDCL_POST: 913 case ARM::LDCL_OPTION: 914 case ARM::STC_OFFSET: 915 case ARM::STC_PRE: 916 case ARM::STC_POST: 917 case ARM::STC_OPTION: 918 case ARM::STCL_OFFSET: 919 case ARM::STCL_PRE: 920 case ARM::STCL_POST: 921 case ARM::STCL_OPTION: 922 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 923 break; 924 default: 925 break; 926 } 927 928 return true; 929 } 930 931 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 932 uint64_t Address, const void *Decoder) { 933 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 934 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 935 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 936 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 937 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 938 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 939 unsigned P = fieldFromInstruction32(Insn, 24, 1); 940 unsigned W = fieldFromInstruction32(Insn, 21, 1); 941 942 // On stores, the writeback operand precedes Rt. 943 switch (Inst.getOpcode()) { 944 case ARM::STR_POST_IMM: 945 case ARM::STR_POST_REG: 946 case ARM::STRB_POST_IMM: 947 case ARM::STRB_POST_REG: 948 case ARM::STRTr: 949 case ARM::STRTi: 950 case ARM::STRBT_POST_REG: 951 case ARM::STRBT_POST_IMM: 952 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 953 break; 954 default: 955 break; 956 } 957 958 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 959 960 // On loads, the writeback operand comes after Rt. 961 switch (Inst.getOpcode()) { 962 case ARM::LDR_POST_IMM: 963 case ARM::LDR_POST_REG: 964 case ARM::LDRB_POST_IMM: 965 case ARM::LDRB_POST_REG: 966 case ARM::LDR_PRE: 967 case ARM::LDRBT_POST_REG: 968 case ARM::LDRBT_POST_IMM: 969 case ARM::LDRT_POST_REG: 970 case ARM::LDRT_POST_IMM: 971 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 972 return false; 973 break; 974 default: 975 break; 976 } 977 978 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 979 980 ARM_AM::AddrOpc Op = ARM_AM::add; 981 if (!fieldFromInstruction32(Insn, 23, 1)) 982 Op = ARM_AM::sub; 983 984 bool writeback = (P == 0) || (W == 1); 985 unsigned idx_mode = 0; 986 if (P && writeback) 987 idx_mode = ARMII::IndexModePre; 988 else if (!P && writeback) 989 idx_mode = ARMII::IndexModePost; 990 991 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE 992 993 if (reg) { 994 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 995 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 996 switch( fieldFromInstruction32(Insn, 5, 2)) { 997 case 0: 998 Opc = ARM_AM::lsl; 999 break; 1000 case 1: 1001 Opc = ARM_AM::lsr; 1002 break; 1003 case 2: 1004 Opc = ARM_AM::asr; 1005 break; 1006 case 3: 1007 Opc = ARM_AM::ror; 1008 break; 1009 default: 1010 return false; 1011 } 1012 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1013 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1014 1015 Inst.addOperand(MCOperand::CreateImm(imm)); 1016 } else { 1017 Inst.addOperand(MCOperand::CreateReg(0)); 1018 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1019 Inst.addOperand(MCOperand::CreateImm(tmp)); 1020 } 1021 1022 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1023 1024 return true; 1025 } 1026 1027 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1028 uint64_t Address, const void *Decoder) { 1029 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1030 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1031 unsigned type = fieldFromInstruction32(Val, 5, 2); 1032 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1033 unsigned U = fieldFromInstruction32(Val, 12, 1); 1034 1035 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1036 switch (type) { 1037 case 0: 1038 ShOp = ARM_AM::lsl; 1039 break; 1040 case 1: 1041 ShOp = ARM_AM::lsr; 1042 break; 1043 case 2: 1044 ShOp = ARM_AM::asr; 1045 break; 1046 case 3: 1047 ShOp = ARM_AM::ror; 1048 break; 1049 } 1050 1051 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1052 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1053 unsigned shift; 1054 if (U) 1055 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1056 else 1057 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1058 Inst.addOperand(MCOperand::CreateImm(shift)); 1059 1060 return true; 1061 } 1062 1063 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1064 uint64_t Address, const void *Decoder) { 1065 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1066 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1067 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1068 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1069 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1070 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1071 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1072 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1073 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1074 1075 bool writeback = (W == 1) | (P == 0); 1076 if (writeback) { // Writeback 1077 if (P) 1078 U |= ARMII::IndexModePre << 9; 1079 else 1080 U |= ARMII::IndexModePost << 9; 1081 1082 // On stores, the writeback operand precedes Rt. 1083 switch (Inst.getOpcode()) { 1084 case ARM::STRD: 1085 case ARM::STRD_PRE: 1086 case ARM::STRD_POST: 1087 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1088 return false; 1089 break; 1090 default: 1091 break; 1092 } 1093 } 1094 1095 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1096 return false; 1097 switch (Inst.getOpcode()) { 1098 case ARM::STRD: 1099 case ARM::STRD_PRE: 1100 case ARM::STRD_POST: 1101 case ARM::LDRD: 1102 case ARM::LDRD_PRE: 1103 case ARM::LDRD_POST: 1104 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1105 return false; 1106 break; 1107 default: 1108 break; 1109 } 1110 1111 if (writeback) { 1112 // On loads, the writeback operand comes after Rt. 1113 switch (Inst.getOpcode()) { 1114 case ARM::LDRD: 1115 case ARM::LDRD_PRE: 1116 case ARM::LDRD_POST: 1117 case ARM::LDRHTr: 1118 case ARM::LDRSBTr: 1119 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1120 return false; 1121 break; 1122 default: 1123 break; 1124 } 1125 } 1126 1127 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1128 return false; 1129 1130 if (type) { 1131 Inst.addOperand(MCOperand::CreateReg(0)); 1132 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1133 } else { 1134 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1135 return false; 1136 Inst.addOperand(MCOperand::CreateImm(U)); 1137 } 1138 1139 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1140 1141 return true; 1142 } 1143 1144 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1145 uint64_t Address, const void *Decoder) { 1146 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1147 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1148 1149 switch (mode) { 1150 case 0: 1151 mode = ARM_AM::da; 1152 break; 1153 case 1: 1154 mode = ARM_AM::ia; 1155 break; 1156 case 2: 1157 mode = ARM_AM::db; 1158 break; 1159 case 3: 1160 mode = ARM_AM::ib; 1161 break; 1162 } 1163 1164 Inst.addOperand(MCOperand::CreateImm(mode)); 1165 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1166 1167 return true; 1168 } 1169 1170 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1171 unsigned Insn, 1172 uint64_t Address, const void *Decoder) { 1173 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1174 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1175 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1176 1177 if (pred == 0xF) { 1178 switch (Inst.getOpcode()) { 1179 case ARM::STMDA: 1180 Inst.setOpcode(ARM::RFEDA); 1181 break; 1182 case ARM::STMDA_UPD: 1183 Inst.setOpcode(ARM::RFEDA_UPD); 1184 break; 1185 case ARM::STMDB: 1186 Inst.setOpcode(ARM::RFEDB); 1187 break; 1188 case ARM::STMDB_UPD: 1189 Inst.setOpcode(ARM::RFEDB_UPD); 1190 break; 1191 case ARM::STMIA: 1192 Inst.setOpcode(ARM::RFEIA); 1193 break; 1194 case ARM::STMIA_UPD: 1195 Inst.setOpcode(ARM::RFEIA_UPD); 1196 break; 1197 case ARM::STMIB: 1198 Inst.setOpcode(ARM::RFEIB); 1199 break; 1200 case ARM::STMIB_UPD: 1201 Inst.setOpcode(ARM::RFEIB_UPD); 1202 break; 1203 } 1204 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1205 } 1206 1207 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1208 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1209 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1210 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1211 return false; 1212 1213 return true; 1214 } 1215 1216 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1217 uint64_t Address, const void *Decoder) { 1218 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1219 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1220 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1221 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1222 1223 // imod == '01' --> UNPREDICTABLE 1224 if (imod == 1) return false; 1225 1226 if (M && mode && imod && iflags) { 1227 Inst.setOpcode(ARM::CPS3p); 1228 Inst.addOperand(MCOperand::CreateImm(imod)); 1229 Inst.addOperand(MCOperand::CreateImm(iflags)); 1230 Inst.addOperand(MCOperand::CreateImm(mode)); 1231 return true; 1232 } else if (!mode && !M) { 1233 Inst.setOpcode(ARM::CPS2p); 1234 Inst.addOperand(MCOperand::CreateImm(imod)); 1235 Inst.addOperand(MCOperand::CreateImm(iflags)); 1236 return true; 1237 } else if (!imod && !iflags && M) { 1238 Inst.setOpcode(ARM::CPS1p); 1239 Inst.addOperand(MCOperand::CreateImm(mode)); 1240 return true; 1241 } 1242 1243 return false; 1244 } 1245 1246 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1247 uint64_t Address, const void *Decoder) { 1248 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1249 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1250 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1251 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1252 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1253 1254 if (pred == 0xF) 1255 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1256 1257 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1258 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1259 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1260 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1261 return false; 1262 1263 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1264 1265 return true; 1266 } 1267 1268 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1269 uint64_t Address, const void *Decoder) { 1270 unsigned add = fieldFromInstruction32(Val, 12, 1); 1271 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1272 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1273 1274 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1275 return false; 1276 1277 if (!add) imm *= -1; 1278 if (imm == 0 && !add) imm = INT32_MIN; 1279 Inst.addOperand(MCOperand::CreateImm(imm)); 1280 1281 return true; 1282 } 1283 1284 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1285 uint64_t Address, const void *Decoder) { 1286 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1287 unsigned U = fieldFromInstruction32(Val, 8, 1); 1288 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1289 1290 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1291 return false; 1292 1293 if (U) 1294 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1295 else 1296 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1297 1298 return true; 1299 } 1300 1301 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1302 uint64_t Address, const void *Decoder) { 1303 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1304 } 1305 1306 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1307 uint64_t Address, const void *Decoder) { 1308 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1309 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1310 1311 if (pred == 0xF) { 1312 Inst.setOpcode(ARM::BLXi); 1313 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1314 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1315 return true; 1316 } 1317 1318 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1319 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1320 1321 return true; 1322 } 1323 1324 1325 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1326 uint64_t Address, const void *Decoder) { 1327 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1328 return true; 1329 } 1330 1331 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1332 uint64_t Address, const void *Decoder) { 1333 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1334 unsigned align = fieldFromInstruction32(Val, 4, 2); 1335 1336 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1337 return false; 1338 if (!align) 1339 Inst.addOperand(MCOperand::CreateImm(0)); 1340 else 1341 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1342 1343 return true; 1344 } 1345 1346 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1347 uint64_t Address, const void *Decoder) { 1348 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1349 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1350 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1351 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1352 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1353 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1354 1355 // First output register 1356 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1357 1358 // Second output register 1359 switch (Inst.getOpcode()) { 1360 case ARM::VLD1q8: 1361 case ARM::VLD1q16: 1362 case ARM::VLD1q32: 1363 case ARM::VLD1q64: 1364 case ARM::VLD1q8_UPD: 1365 case ARM::VLD1q16_UPD: 1366 case ARM::VLD1q32_UPD: 1367 case ARM::VLD1q64_UPD: 1368 case ARM::VLD1d8T: 1369 case ARM::VLD1d16T: 1370 case ARM::VLD1d32T: 1371 case ARM::VLD1d64T: 1372 case ARM::VLD1d8T_UPD: 1373 case ARM::VLD1d16T_UPD: 1374 case ARM::VLD1d32T_UPD: 1375 case ARM::VLD1d64T_UPD: 1376 case ARM::VLD1d8Q: 1377 case ARM::VLD1d16Q: 1378 case ARM::VLD1d32Q: 1379 case ARM::VLD1d64Q: 1380 case ARM::VLD1d8Q_UPD: 1381 case ARM::VLD1d16Q_UPD: 1382 case ARM::VLD1d32Q_UPD: 1383 case ARM::VLD1d64Q_UPD: 1384 case ARM::VLD2d8: 1385 case ARM::VLD2d16: 1386 case ARM::VLD2d32: 1387 case ARM::VLD2d8_UPD: 1388 case ARM::VLD2d16_UPD: 1389 case ARM::VLD2d32_UPD: 1390 case ARM::VLD2q8: 1391 case ARM::VLD2q16: 1392 case ARM::VLD2q32: 1393 case ARM::VLD2q8_UPD: 1394 case ARM::VLD2q16_UPD: 1395 case ARM::VLD2q32_UPD: 1396 case ARM::VLD3d8: 1397 case ARM::VLD3d16: 1398 case ARM::VLD3d32: 1399 case ARM::VLD3d8_UPD: 1400 case ARM::VLD3d16_UPD: 1401 case ARM::VLD3d32_UPD: 1402 case ARM::VLD4d8: 1403 case ARM::VLD4d16: 1404 case ARM::VLD4d32: 1405 case ARM::VLD4d8_UPD: 1406 case ARM::VLD4d16_UPD: 1407 case ARM::VLD4d32_UPD: 1408 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1409 break; 1410 case ARM::VLD2b8: 1411 case ARM::VLD2b16: 1412 case ARM::VLD2b32: 1413 case ARM::VLD2b8_UPD: 1414 case ARM::VLD2b16_UPD: 1415 case ARM::VLD2b32_UPD: 1416 case ARM::VLD3q8: 1417 case ARM::VLD3q16: 1418 case ARM::VLD3q32: 1419 case ARM::VLD3q8_UPD: 1420 case ARM::VLD3q16_UPD: 1421 case ARM::VLD3q32_UPD: 1422 case ARM::VLD4q8: 1423 case ARM::VLD4q16: 1424 case ARM::VLD4q32: 1425 case ARM::VLD4q8_UPD: 1426 case ARM::VLD4q16_UPD: 1427 case ARM::VLD4q32_UPD: 1428 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1429 default: 1430 break; 1431 } 1432 1433 // Third output register 1434 switch(Inst.getOpcode()) { 1435 case ARM::VLD1d8T: 1436 case ARM::VLD1d16T: 1437 case ARM::VLD1d32T: 1438 case ARM::VLD1d64T: 1439 case ARM::VLD1d8T_UPD: 1440 case ARM::VLD1d16T_UPD: 1441 case ARM::VLD1d32T_UPD: 1442 case ARM::VLD1d64T_UPD: 1443 case ARM::VLD1d8Q: 1444 case ARM::VLD1d16Q: 1445 case ARM::VLD1d32Q: 1446 case ARM::VLD1d64Q: 1447 case ARM::VLD1d8Q_UPD: 1448 case ARM::VLD1d16Q_UPD: 1449 case ARM::VLD1d32Q_UPD: 1450 case ARM::VLD1d64Q_UPD: 1451 case ARM::VLD2q8: 1452 case ARM::VLD2q16: 1453 case ARM::VLD2q32: 1454 case ARM::VLD2q8_UPD: 1455 case ARM::VLD2q16_UPD: 1456 case ARM::VLD2q32_UPD: 1457 case ARM::VLD3d8: 1458 case ARM::VLD3d16: 1459 case ARM::VLD3d32: 1460 case ARM::VLD3d8_UPD: 1461 case ARM::VLD3d16_UPD: 1462 case ARM::VLD3d32_UPD: 1463 case ARM::VLD4d8: 1464 case ARM::VLD4d16: 1465 case ARM::VLD4d32: 1466 case ARM::VLD4d8_UPD: 1467 case ARM::VLD4d16_UPD: 1468 case ARM::VLD4d32_UPD: 1469 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1470 break; 1471 case ARM::VLD3q8: 1472 case ARM::VLD3q16: 1473 case ARM::VLD3q32: 1474 case ARM::VLD3q8_UPD: 1475 case ARM::VLD3q16_UPD: 1476 case ARM::VLD3q32_UPD: 1477 case ARM::VLD4q8: 1478 case ARM::VLD4q16: 1479 case ARM::VLD4q32: 1480 case ARM::VLD4q8_UPD: 1481 case ARM::VLD4q16_UPD: 1482 case ARM::VLD4q32_UPD: 1483 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1484 break; 1485 default: 1486 break; 1487 } 1488 1489 // Fourth output register 1490 switch (Inst.getOpcode()) { 1491 case ARM::VLD1d8Q: 1492 case ARM::VLD1d16Q: 1493 case ARM::VLD1d32Q: 1494 case ARM::VLD1d64Q: 1495 case ARM::VLD1d8Q_UPD: 1496 case ARM::VLD1d16Q_UPD: 1497 case ARM::VLD1d32Q_UPD: 1498 case ARM::VLD1d64Q_UPD: 1499 case ARM::VLD2q8: 1500 case ARM::VLD2q16: 1501 case ARM::VLD2q32: 1502 case ARM::VLD2q8_UPD: 1503 case ARM::VLD2q16_UPD: 1504 case ARM::VLD2q32_UPD: 1505 case ARM::VLD4d8: 1506 case ARM::VLD4d16: 1507 case ARM::VLD4d32: 1508 case ARM::VLD4d8_UPD: 1509 case ARM::VLD4d16_UPD: 1510 case ARM::VLD4d32_UPD: 1511 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1512 break; 1513 case ARM::VLD4q8: 1514 case ARM::VLD4q16: 1515 case ARM::VLD4q32: 1516 case ARM::VLD4q8_UPD: 1517 case ARM::VLD4q16_UPD: 1518 case ARM::VLD4q32_UPD: 1519 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1520 break; 1521 default: 1522 break; 1523 } 1524 1525 // Writeback operand 1526 switch (Inst.getOpcode()) { 1527 case ARM::VLD1d8_UPD: 1528 case ARM::VLD1d16_UPD: 1529 case ARM::VLD1d32_UPD: 1530 case ARM::VLD1d64_UPD: 1531 case ARM::VLD1q8_UPD: 1532 case ARM::VLD1q16_UPD: 1533 case ARM::VLD1q32_UPD: 1534 case ARM::VLD1q64_UPD: 1535 case ARM::VLD1d8T_UPD: 1536 case ARM::VLD1d16T_UPD: 1537 case ARM::VLD1d32T_UPD: 1538 case ARM::VLD1d64T_UPD: 1539 case ARM::VLD1d8Q_UPD: 1540 case ARM::VLD1d16Q_UPD: 1541 case ARM::VLD1d32Q_UPD: 1542 case ARM::VLD1d64Q_UPD: 1543 case ARM::VLD2d8_UPD: 1544 case ARM::VLD2d16_UPD: 1545 case ARM::VLD2d32_UPD: 1546 case ARM::VLD2q8_UPD: 1547 case ARM::VLD2q16_UPD: 1548 case ARM::VLD2q32_UPD: 1549 case ARM::VLD2b8_UPD: 1550 case ARM::VLD2b16_UPD: 1551 case ARM::VLD2b32_UPD: 1552 case ARM::VLD3d8_UPD: 1553 case ARM::VLD3d16_UPD: 1554 case ARM::VLD3d32_UPD: 1555 case ARM::VLD3q8_UPD: 1556 case ARM::VLD3q16_UPD: 1557 case ARM::VLD3q32_UPD: 1558 case ARM::VLD4d8_UPD: 1559 case ARM::VLD4d16_UPD: 1560 case ARM::VLD4d32_UPD: 1561 case ARM::VLD4q8_UPD: 1562 case ARM::VLD4q16_UPD: 1563 case ARM::VLD4q32_UPD: 1564 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1565 break; 1566 default: 1567 break; 1568 } 1569 1570 // AddrMode6 Base (register+alignment) 1571 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1572 1573 // AddrMode6 Offset (register) 1574 if (Rm == 0xD) 1575 Inst.addOperand(MCOperand::CreateReg(0)); 1576 else if (Rm != 0xF) { 1577 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1578 return false; 1579 } 1580 1581 return true; 1582 } 1583 1584 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1585 uint64_t Address, const void *Decoder) { 1586 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1587 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1588 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1589 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1590 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1591 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1592 1593 // Writeback Operand 1594 switch (Inst.getOpcode()) { 1595 case ARM::VST1d8_UPD: 1596 case ARM::VST1d16_UPD: 1597 case ARM::VST1d32_UPD: 1598 case ARM::VST1d64_UPD: 1599 case ARM::VST1q8_UPD: 1600 case ARM::VST1q16_UPD: 1601 case ARM::VST1q32_UPD: 1602 case ARM::VST1q64_UPD: 1603 case ARM::VST1d8T_UPD: 1604 case ARM::VST1d16T_UPD: 1605 case ARM::VST1d32T_UPD: 1606 case ARM::VST1d64T_UPD: 1607 case ARM::VST1d8Q_UPD: 1608 case ARM::VST1d16Q_UPD: 1609 case ARM::VST1d32Q_UPD: 1610 case ARM::VST1d64Q_UPD: 1611 case ARM::VST2d8_UPD: 1612 case ARM::VST2d16_UPD: 1613 case ARM::VST2d32_UPD: 1614 case ARM::VST2q8_UPD: 1615 case ARM::VST2q16_UPD: 1616 case ARM::VST2q32_UPD: 1617 case ARM::VST2b8_UPD: 1618 case ARM::VST2b16_UPD: 1619 case ARM::VST2b32_UPD: 1620 case ARM::VST3d8_UPD: 1621 case ARM::VST3d16_UPD: 1622 case ARM::VST3d32_UPD: 1623 case ARM::VST3q8_UPD: 1624 case ARM::VST3q16_UPD: 1625 case ARM::VST3q32_UPD: 1626 case ARM::VST4d8_UPD: 1627 case ARM::VST4d16_UPD: 1628 case ARM::VST4d32_UPD: 1629 case ARM::VST4q8_UPD: 1630 case ARM::VST4q16_UPD: 1631 case ARM::VST4q32_UPD: 1632 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1633 return false; 1634 break; 1635 default: 1636 break; 1637 } 1638 1639 // AddrMode6 Base (register+alignment) 1640 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1641 1642 // AddrMode6 Offset (register) 1643 if (Rm == 0xD) 1644 Inst.addOperand(MCOperand::CreateReg(0)); 1645 else if (Rm != 0xF) { 1646 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1647 } 1648 1649 // First input register 1650 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1651 1652 // Second input register 1653 switch (Inst.getOpcode()) { 1654 case ARM::VST1q8: 1655 case ARM::VST1q16: 1656 case ARM::VST1q32: 1657 case ARM::VST1q64: 1658 case ARM::VST1q8_UPD: 1659 case ARM::VST1q16_UPD: 1660 case ARM::VST1q32_UPD: 1661 case ARM::VST1q64_UPD: 1662 case ARM::VST1d8T: 1663 case ARM::VST1d16T: 1664 case ARM::VST1d32T: 1665 case ARM::VST1d64T: 1666 case ARM::VST1d8T_UPD: 1667 case ARM::VST1d16T_UPD: 1668 case ARM::VST1d32T_UPD: 1669 case ARM::VST1d64T_UPD: 1670 case ARM::VST1d8Q: 1671 case ARM::VST1d16Q: 1672 case ARM::VST1d32Q: 1673 case ARM::VST1d64Q: 1674 case ARM::VST1d8Q_UPD: 1675 case ARM::VST1d16Q_UPD: 1676 case ARM::VST1d32Q_UPD: 1677 case ARM::VST1d64Q_UPD: 1678 case ARM::VST2d8: 1679 case ARM::VST2d16: 1680 case ARM::VST2d32: 1681 case ARM::VST2d8_UPD: 1682 case ARM::VST2d16_UPD: 1683 case ARM::VST2d32_UPD: 1684 case ARM::VST2q8: 1685 case ARM::VST2q16: 1686 case ARM::VST2q32: 1687 case ARM::VST2q8_UPD: 1688 case ARM::VST2q16_UPD: 1689 case ARM::VST2q32_UPD: 1690 case ARM::VST3d8: 1691 case ARM::VST3d16: 1692 case ARM::VST3d32: 1693 case ARM::VST3d8_UPD: 1694 case ARM::VST3d16_UPD: 1695 case ARM::VST3d32_UPD: 1696 case ARM::VST4d8: 1697 case ARM::VST4d16: 1698 case ARM::VST4d32: 1699 case ARM::VST4d8_UPD: 1700 case ARM::VST4d16_UPD: 1701 case ARM::VST4d32_UPD: 1702 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1703 break; 1704 case ARM::VST2b8: 1705 case ARM::VST2b16: 1706 case ARM::VST2b32: 1707 case ARM::VST2b8_UPD: 1708 case ARM::VST2b16_UPD: 1709 case ARM::VST2b32_UPD: 1710 case ARM::VST3q8: 1711 case ARM::VST3q16: 1712 case ARM::VST3q32: 1713 case ARM::VST3q8_UPD: 1714 case ARM::VST3q16_UPD: 1715 case ARM::VST3q32_UPD: 1716 case ARM::VST4q8: 1717 case ARM::VST4q16: 1718 case ARM::VST4q32: 1719 case ARM::VST4q8_UPD: 1720 case ARM::VST4q16_UPD: 1721 case ARM::VST4q32_UPD: 1722 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1723 break; 1724 default: 1725 break; 1726 } 1727 1728 // Third input register 1729 switch (Inst.getOpcode()) { 1730 case ARM::VST1d8T: 1731 case ARM::VST1d16T: 1732 case ARM::VST1d32T: 1733 case ARM::VST1d64T: 1734 case ARM::VST1d8T_UPD: 1735 case ARM::VST1d16T_UPD: 1736 case ARM::VST1d32T_UPD: 1737 case ARM::VST1d64T_UPD: 1738 case ARM::VST1d8Q: 1739 case ARM::VST1d16Q: 1740 case ARM::VST1d32Q: 1741 case ARM::VST1d64Q: 1742 case ARM::VST1d8Q_UPD: 1743 case ARM::VST1d16Q_UPD: 1744 case ARM::VST1d32Q_UPD: 1745 case ARM::VST1d64Q_UPD: 1746 case ARM::VST2q8: 1747 case ARM::VST2q16: 1748 case ARM::VST2q32: 1749 case ARM::VST2q8_UPD: 1750 case ARM::VST2q16_UPD: 1751 case ARM::VST2q32_UPD: 1752 case ARM::VST3d8: 1753 case ARM::VST3d16: 1754 case ARM::VST3d32: 1755 case ARM::VST3d8_UPD: 1756 case ARM::VST3d16_UPD: 1757 case ARM::VST3d32_UPD: 1758 case ARM::VST4d8: 1759 case ARM::VST4d16: 1760 case ARM::VST4d32: 1761 case ARM::VST4d8_UPD: 1762 case ARM::VST4d16_UPD: 1763 case ARM::VST4d32_UPD: 1764 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1765 break; 1766 case ARM::VST3q8: 1767 case ARM::VST3q16: 1768 case ARM::VST3q32: 1769 case ARM::VST3q8_UPD: 1770 case ARM::VST3q16_UPD: 1771 case ARM::VST3q32_UPD: 1772 case ARM::VST4q8: 1773 case ARM::VST4q16: 1774 case ARM::VST4q32: 1775 case ARM::VST4q8_UPD: 1776 case ARM::VST4q16_UPD: 1777 case ARM::VST4q32_UPD: 1778 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1779 break; 1780 default: 1781 break; 1782 } 1783 1784 // Fourth input register 1785 switch (Inst.getOpcode()) { 1786 case ARM::VST1d8Q: 1787 case ARM::VST1d16Q: 1788 case ARM::VST1d32Q: 1789 case ARM::VST1d64Q: 1790 case ARM::VST1d8Q_UPD: 1791 case ARM::VST1d16Q_UPD: 1792 case ARM::VST1d32Q_UPD: 1793 case ARM::VST1d64Q_UPD: 1794 case ARM::VST2q8: 1795 case ARM::VST2q16: 1796 case ARM::VST2q32: 1797 case ARM::VST2q8_UPD: 1798 case ARM::VST2q16_UPD: 1799 case ARM::VST2q32_UPD: 1800 case ARM::VST4d8: 1801 case ARM::VST4d16: 1802 case ARM::VST4d32: 1803 case ARM::VST4d8_UPD: 1804 case ARM::VST4d16_UPD: 1805 case ARM::VST4d32_UPD: 1806 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1807 break; 1808 case ARM::VST4q8: 1809 case ARM::VST4q16: 1810 case ARM::VST4q32: 1811 case ARM::VST4q8_UPD: 1812 case ARM::VST4q16_UPD: 1813 case ARM::VST4q32_UPD: 1814 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1815 break; 1816 default: 1817 break; 1818 } 1819 1820 return true; 1821 } 1822 1823 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1824 uint64_t Address, const void *Decoder) { 1825 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1826 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1827 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1828 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1829 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1830 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1831 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1832 1833 align *= (1 << size); 1834 1835 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1836 if (regs == 2) { 1837 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1838 } 1839 if (Rm == 0xD) { 1840 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1841 } 1842 1843 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1844 Inst.addOperand(MCOperand::CreateImm(align)); 1845 1846 if (Rm == 0xD) 1847 Inst.addOperand(MCOperand::CreateReg(0)); 1848 else if (Rm != 0xF) { 1849 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1850 } 1851 1852 return true; 1853 } 1854 1855 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1856 uint64_t Address, const void *Decoder) { 1857 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1858 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1859 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1860 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1861 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1862 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1863 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1864 align *= 2*size; 1865 1866 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1867 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1868 if (Rm == 0xD) { 1869 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1870 } 1871 1872 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1873 Inst.addOperand(MCOperand::CreateImm(align)); 1874 1875 if (Rm == 0xD) 1876 Inst.addOperand(MCOperand::CreateReg(0)); 1877 else if (Rm != 0xF) { 1878 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1879 } 1880 1881 return true; 1882 } 1883 1884 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1885 uint64_t Address, const void *Decoder) { 1886 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1887 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1888 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1889 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1890 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1891 1892 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1893 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1894 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1895 return false; 1896 if (Rm == 0xD) { 1897 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1898 } 1899 1900 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1901 Inst.addOperand(MCOperand::CreateImm(0)); 1902 1903 if (Rm == 0xD) 1904 Inst.addOperand(MCOperand::CreateReg(0)); 1905 else if (Rm != 0xF) { 1906 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1907 } 1908 1909 return true; 1910 } 1911 1912 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1913 uint64_t Address, const void *Decoder) { 1914 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1915 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1916 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1917 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1918 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1919 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1920 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1921 1922 if (size == 0x3) { 1923 size = 4; 1924 align = 16; 1925 } else { 1926 if (size == 2) { 1927 size = 1 << size; 1928 align *= 8; 1929 } else { 1930 size = 1 << size; 1931 align *= 4*size; 1932 } 1933 } 1934 1935 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1936 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1937 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1938 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 1939 return false; 1940 if (Rm == 0xD) { 1941 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1942 } 1943 1944 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1945 Inst.addOperand(MCOperand::CreateImm(align)); 1946 1947 if (Rm == 0xD) 1948 Inst.addOperand(MCOperand::CreateReg(0)); 1949 else if (Rm != 0xF) { 1950 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1951 } 1952 1953 return true; 1954 } 1955 1956 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1957 uint64_t Address, const void *Decoder) { 1958 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1959 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1960 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 1961 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 1962 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 1963 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 1964 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 1965 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 1966 1967 if (Q) { 1968 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1969 } else { 1970 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1971 } 1972 1973 Inst.addOperand(MCOperand::CreateImm(imm)); 1974 1975 switch (Inst.getOpcode()) { 1976 case ARM::VORRiv4i16: 1977 case ARM::VORRiv2i32: 1978 case ARM::VBICiv4i16: 1979 case ARM::VBICiv2i32: 1980 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1981 break; 1982 case ARM::VORRiv8i16: 1983 case ARM::VORRiv4i32: 1984 case ARM::VBICiv8i16: 1985 case ARM::VBICiv4i32: 1986 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1987 break; 1988 default: 1989 break; 1990 } 1991 1992 return true; 1993 } 1994 1995 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 1996 uint64_t Address, const void *Decoder) { 1997 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1998 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1999 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2000 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2001 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2002 2003 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2004 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2005 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2006 2007 return true; 2008 } 2009 2010 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2011 uint64_t Address, const void *Decoder) { 2012 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2013 return true; 2014 } 2015 2016 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2017 uint64_t Address, const void *Decoder) { 2018 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2019 return true; 2020 } 2021 2022 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2023 uint64_t Address, const void *Decoder) { 2024 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2025 return true; 2026 } 2027 2028 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2029 uint64_t Address, const void *Decoder) { 2030 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2031 return true; 2032 } 2033 2034 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2035 uint64_t Address, const void *Decoder) { 2036 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2037 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2038 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2039 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2040 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2041 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2042 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2043 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2044 2045 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2046 if (op) { 2047 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2048 } 2049 2050 for (unsigned i = 0; i < length; ++i) { 2051 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2052 } 2053 2054 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2055 2056 return true; 2057 } 2058 2059 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2060 uint64_t Address, const void *Decoder) { 2061 // The immediate needs to be a fully instantiated float. However, the 2062 // auto-generated decoder is only able to fill in some of the bits 2063 // necessary. For instance, the 'b' bit is replicated multiple times, 2064 // and is even present in inverted form in one bit. We do a little 2065 // binary parsing here to fill in those missing bits, and then 2066 // reinterpret it all as a float. 2067 union { 2068 uint32_t integer; 2069 float fp; 2070 } fp_conv; 2071 2072 fp_conv.integer = Val; 2073 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2074 fp_conv.integer |= b << 26; 2075 fp_conv.integer |= b << 27; 2076 fp_conv.integer |= b << 28; 2077 fp_conv.integer |= b << 29; 2078 fp_conv.integer |= (~b & 0x1) << 30; 2079 2080 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2081 return true; 2082 } 2083 2084 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2085 uint64_t Address, const void *Decoder) { 2086 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2087 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2088 2089 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2090 2091 if (Inst.getOpcode() == ARM::tADR) 2092 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2093 else if (Inst.getOpcode() == ARM::tADDrSPi) 2094 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2095 else 2096 return false; 2097 2098 Inst.addOperand(MCOperand::CreateImm(imm)); 2099 return true; 2100 } 2101 2102 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2103 uint64_t Address, const void *Decoder) { 2104 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2105 return true; 2106 } 2107 2108 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2109 uint64_t Address, const void *Decoder) { 2110 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2111 return true; 2112 } 2113 2114 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2115 uint64_t Address, const void *Decoder) { 2116 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2117 return true; 2118 } 2119 2120 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2121 uint64_t Address, const void *Decoder) { 2122 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2123 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2124 2125 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2126 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2127 return false; 2128 2129 return true; 2130 } 2131 2132 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2133 uint64_t Address, const void *Decoder) { 2134 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2135 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2136 2137 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2138 Inst.addOperand(MCOperand::CreateImm(imm)); 2139 2140 return true; 2141 } 2142 2143 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2144 uint64_t Address, const void *Decoder) { 2145 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2146 2147 return true; 2148 } 2149 2150 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2151 uint64_t Address, const void *Decoder) { 2152 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2153 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2154 2155 return true; 2156 } 2157 2158 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2159 uint64_t Address, const void *Decoder) { 2160 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2161 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2162 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2163 2164 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2165 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2166 return false; 2167 Inst.addOperand(MCOperand::CreateImm(imm)); 2168 2169 return true; 2170 } 2171 2172 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2173 uint64_t Address, const void *Decoder) { 2174 if (Inst.getOpcode() != ARM::t2PLDs) { 2175 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2176 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2177 } 2178 2179 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2180 if (Rn == 0xF) { 2181 switch (Inst.getOpcode()) { 2182 case ARM::t2LDRBs: 2183 Inst.setOpcode(ARM::t2LDRBpci); 2184 break; 2185 case ARM::t2LDRHs: 2186 Inst.setOpcode(ARM::t2LDRHpci); 2187 break; 2188 case ARM::t2LDRSHs: 2189 Inst.setOpcode(ARM::t2LDRSHpci); 2190 break; 2191 case ARM::t2LDRSBs: 2192 Inst.setOpcode(ARM::t2LDRSBpci); 2193 break; 2194 case ARM::t2PLDs: 2195 Inst.setOpcode(ARM::t2PLDi12); 2196 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2197 break; 2198 default: 2199 return false; 2200 } 2201 2202 int imm = fieldFromInstruction32(Insn, 0, 12); 2203 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2204 Inst.addOperand(MCOperand::CreateImm(imm)); 2205 2206 return true; 2207 } 2208 2209 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2210 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2211 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2212 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2213 2214 return true; 2215 } 2216 2217 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2218 uint64_t Address, const void *Decoder) { 2219 int imm = Val & 0xFF; 2220 if (!(Val & 0x100)) imm *= -1; 2221 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2222 2223 return true; 2224 } 2225 2226 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2227 uint64_t Address, const void *Decoder) { 2228 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2229 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2230 2231 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2232 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2233 return false; 2234 2235 return true; 2236 } 2237 2238 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2239 uint64_t Address, const void *Decoder) { 2240 int imm = Val & 0xFF; 2241 if (!(Val & 0x100)) imm *= -1; 2242 Inst.addOperand(MCOperand::CreateImm(imm)); 2243 2244 return true; 2245 } 2246 2247 2248 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2249 uint64_t Address, const void *Decoder) { 2250 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2251 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2252 2253 // Some instructions always use an additive offset. 2254 switch (Inst.getOpcode()) { 2255 case ARM::t2LDRT: 2256 case ARM::t2LDRBT: 2257 case ARM::t2LDRHT: 2258 case ARM::t2LDRSBT: 2259 case ARM::t2LDRSHT: 2260 imm |= 0x100; 2261 break; 2262 default: 2263 break; 2264 } 2265 2266 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2267 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2268 return false; 2269 2270 return true; 2271 } 2272 2273 2274 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2275 uint64_t Address, const void *Decoder) { 2276 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2277 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2278 2279 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2280 Inst.addOperand(MCOperand::CreateImm(imm)); 2281 2282 return true; 2283 } 2284 2285 2286 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2287 uint64_t Address, const void *Decoder) { 2288 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2289 2290 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2291 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2292 Inst.addOperand(MCOperand::CreateImm(imm)); 2293 2294 return true; 2295 } 2296 2297 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2298 uint64_t Address, const void *Decoder) { 2299 if (Inst.getOpcode() == ARM::tADDrSP) { 2300 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2301 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2302 2303 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2304 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2305 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2306 } else if (Inst.getOpcode() == ARM::tADDspr) { 2307 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2308 2309 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2310 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2311 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2312 } 2313 2314 return true; 2315 } 2316 2317 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2318 uint64_t Address, const void *Decoder) { 2319 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2320 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2321 2322 Inst.addOperand(MCOperand::CreateImm(imod)); 2323 Inst.addOperand(MCOperand::CreateImm(flags)); 2324 2325 return true; 2326 } 2327 2328 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2329 uint64_t Address, const void *Decoder) { 2330 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2331 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2332 2333 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2334 Inst.addOperand(MCOperand::CreateImm(add)); 2335 2336 return true; 2337 } 2338 2339 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2340 uint64_t Address, const void *Decoder) { 2341 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2342 return true; 2343 } 2344 2345 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2346 uint64_t Address, const void *Decoder) { 2347 if (Val == 0xA || Val == 0xB) 2348 return false; 2349 2350 Inst.addOperand(MCOperand::CreateImm(Val)); 2351 return true; 2352 } 2353 2354 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2355 uint64_t Address, const void *Decoder) { 2356 if (Val == 0) 2357 Inst.addOperand(MCOperand::CreateImm(32)); 2358 else 2359 Inst.addOperand(MCOperand::CreateImm(Val)); 2360 return true; 2361 } 2362 2363 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2364 uint64_t Address, const void *Decoder) { 2365 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2366 if (pred == 0xE || pred == 0xF) { 2367 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2368 switch (opc) { 2369 default: 2370 return false; 2371 case 0: 2372 Inst.setOpcode(ARM::t2DSB); 2373 break; 2374 case 1: 2375 Inst.setOpcode(ARM::t2DMB); 2376 break; 2377 case 2: 2378 Inst.setOpcode(ARM::t2ISB); 2379 return true; 2380 } 2381 2382 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2383 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2384 } 2385 2386 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2387 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2388 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2389 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2390 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2391 2392 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2393 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2394 return false; 2395 2396 return true; 2397 } 2398 2399 // Decode a shifted immediate operand. These basically consist 2400 // of an 8-bit value, and a 4-bit directive that specifies either 2401 // a splat operation or a rotation. 2402 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2403 uint64_t Address, const void *Decoder) { 2404 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2405 if (ctrl == 0) { 2406 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2407 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2408 switch (byte) { 2409 case 0: 2410 Inst.addOperand(MCOperand::CreateImm(imm)); 2411 break; 2412 case 1: 2413 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2414 break; 2415 case 2: 2416 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2417 break; 2418 case 3: 2419 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2420 (imm << 8) | imm)); 2421 break; 2422 } 2423 } else { 2424 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2425 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2426 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2427 Inst.addOperand(MCOperand::CreateImm(imm)); 2428 } 2429 2430 return true; 2431 } 2432 2433 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2434 uint64_t Address, const void *Decoder){ 2435 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2436 return true; 2437 } 2438 2439 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2440 uint64_t Address, const void *Decoder){ 2441 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2442 return true; 2443 } 2444 2445 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val, 2446 uint64_t Address, const void *Decoder) { 2447 bool isImm = fieldFromInstruction32(Val, 9, 1); 2448 bool isAdd = fieldFromInstruction32(Val, 8, 1); 2449 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2450 2451 if (!isImm) { 2452 if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false; 2453 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8)); 2454 } else { 2455 Inst.addOperand(MCOperand::CreateReg(0)); 2456 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8))); 2457 } 2458 2459 return true; 2460 } 2461 2462 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2463 uint64_t Address, const void *Decoder) { 2464 switch (Val) { 2465 default: 2466 return false; 2467 case 0xF: // SY 2468 case 0xE: // ST 2469 case 0xB: // ISH 2470 case 0xA: // ISHST 2471 case 0x7: // NSH 2472 case 0x6: // NSHST 2473 case 0x3: // OSH 2474 case 0x2: // OSHST 2475 break; 2476 } 2477 2478 Inst.addOperand(MCOperand::CreateImm(Val)); 2479 return true; 2480 } 2481 2482 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2483 uint64_t Address, const void *Decoder) { 2484 if (!Val) return false; 2485 Inst.addOperand(MCOperand::CreateImm(Val)); 2486 return true; 2487 } 2488 2489 static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn, 2490 uint64_t Address, const void *Decoder) { 2491 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2492 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2493 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2494 2495 if (Inst.getOpcode() == ARM::STREXD) 2496 if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2497 2498 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2499 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; 2500 2501 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2502 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2503 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2504 2505 return true; 2506 } 2507 2508 2509