1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &VStream, 141 raw_ostream &CStream) const override; 142 }; 143 144 /// Thumb disassembler for all Thumb platforms. 145 class ThumbDisassembler : public MCDisassembler { 146 public: 147 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 148 MCDisassembler(STI, Ctx) { 149 } 150 151 ~ThumbDisassembler() override = default; 152 153 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 154 ArrayRef<uint8_t> Bytes, uint64_t Address, 155 raw_ostream &VStream, 156 raw_ostream &CStream) const override; 157 158 private: 159 mutable ITStatus ITBlock; 160 mutable VPTStatus VPTBlock; 161 162 DecodeStatus AddThumbPredicate(MCInst&) const; 163 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 164 }; 165 166 } // end anonymous namespace 167 168 static bool Check(DecodeStatus &Out, DecodeStatus In) { 169 switch (In) { 170 case MCDisassembler::Success: 171 // Out stays the same. 172 return true; 173 case MCDisassembler::SoftFail: 174 Out = In; 175 return true; 176 case MCDisassembler::Fail: 177 Out = In; 178 return false; 179 } 180 llvm_unreachable("Invalid DecodeStatus!"); 181 } 182 183 // Forward declare these because the autogenerated code will reference them. 184 // Definitions are further down. 185 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 186 uint64_t Address, const void *Decoder); 187 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 188 uint64_t Address, const void *Decoder); 189 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 190 uint64_t Address, const void *Decoder); 191 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 192 uint64_t Address, const void *Decoder); 193 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 194 unsigned RegNo, uint64_t Address, 195 const void *Decoder); 196 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 197 unsigned RegNo, uint64_t Address, 198 const void *Decoder); 199 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 200 unsigned RegNo, uint64_t Address, 201 const void *Decoder); 202 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 203 uint64_t Address, const void *Decoder); 204 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 205 uint64_t Address, const void *Decoder); 206 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 207 uint64_t Address, const void *Decoder); 208 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 209 uint64_t Address, const void *Decoder); 210 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 211 uint64_t Address, const void *Decoder); 212 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 221 unsigned RegNo, 222 uint64_t Address, 223 const void *Decoder); 224 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 225 uint64_t Address, const void *Decoder); 226 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 231 unsigned RegNo, uint64_t Address, 232 const void *Decoder); 233 234 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 237 uint64_t Address, const void *Decoder); 238 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 239 uint64_t Address, const void *Decoder); 240 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 245 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 250 unsigned Insn, 251 uint64_t Address, 252 const void *Decoder); 253 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 260 uint64_t Address, const void *Decoder); 261 262 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 263 unsigned Insn, 264 uint64_t Adddress, 265 const void *Decoder); 266 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 267 uint64_t Address, const void *Decoder); 268 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 269 uint64_t Address, const void *Decoder); 270 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 271 uint64_t Address, const void *Decoder); 272 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 381 unsigned Val, 382 uint64_t Address, 383 const void *Decoder); 384 385 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 406 uint64_t Address, const void* Decoder); 407 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 408 uint64_t Address, const void* Decoder); 409 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 410 uint64_t Address, const void* Decoder); 411 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 412 uint64_t Address, const void* Decoder); 413 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 414 uint64_t Address, const void *Decoder); 415 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 416 uint64_t Address, const void *Decoder); 417 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 418 uint64_t Address, const void *Decoder); 419 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 420 uint64_t Address, 421 const void *Decoder); 422 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 423 uint64_t Address, const void *Decoder); 424 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 425 uint64_t Address, const void *Decoder); 426 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 427 uint64_t Address, const void *Decoder); 428 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 429 uint64_t Address, const void *Decoder); 430 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 431 uint64_t Address, const void *Decoder); 432 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 433 uint64_t Address, const void *Decoder); 434 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 435 uint64_t Address, const void *Decoder); 436 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 437 uint64_t Address, const void *Decoder); 438 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 439 uint64_t Address, const void *Decoder); 440 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 441 uint64_t Address, const void *Decoder); 442 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 443 uint64_t Address, const void *Decoder); 444 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 447 uint64_t Address, const void *Decoder); 448 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 449 uint64_t Address, const void *Decoder); 450 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 451 uint64_t Address, const void *Decoder); 452 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 453 uint64_t Address, const void *Decoder); 454 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 455 uint64_t Address, const void *Decoder); 456 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 457 uint64_t Address, const void *Decoder); 458 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 459 uint64_t Address, const void *Decoder); 460 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 461 uint64_t Address, const void *Decoder); 462 463 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 464 uint64_t Address, const void *Decoder); 465 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 466 uint64_t Address, const void *Decoder); 467 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 468 uint64_t Address, const void *Decoder); 469 470 template <bool isSigned, bool isNeg, int size> 471 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 472 uint64_t Address, const void *Decoder); 473 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 474 uint64_t Address, 475 const void *Decoder); 476 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 477 uint64_t Address, 478 const void *Decoder); 479 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 480 const void *Decoder); 481 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 482 uint64_t Address, 483 const void *Decoder); 484 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 485 const void *Decoder); 486 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 489 uint64_t Address, const void *Decoder); 490 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 491 uint64_t Address, 492 const void *Decoder); 493 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 494 uint64_t Address, 495 const void *Decoder); 496 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 497 uint64_t Address, 498 const void *Decoder); 499 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 500 unsigned Val, 501 uint64_t Address, 502 const void *Decoder); 503 template<bool Writeback> 504 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 505 uint64_t Address, 506 const void *Decoder); 507 template <int shift> 508 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 509 uint64_t Address, 510 const void *Decoder); 511 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 512 uint64_t Address, 513 const void *Decoder); 514 #include "ARMGenDisassemblerTables.inc" 515 516 static MCDisassembler *createARMDisassembler(const Target &T, 517 const MCSubtargetInfo &STI, 518 MCContext &Ctx) { 519 return new ARMDisassembler(STI, Ctx); 520 } 521 522 static MCDisassembler *createThumbDisassembler(const Target &T, 523 const MCSubtargetInfo &STI, 524 MCContext &Ctx) { 525 return new ThumbDisassembler(STI, Ctx); 526 } 527 528 // Post-decoding checks 529 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 530 uint64_t Address, raw_ostream &OS, 531 raw_ostream &CS, 532 uint32_t Insn, 533 DecodeStatus Result) { 534 switch (MI.getOpcode()) { 535 case ARM::HVC: { 536 // HVC is undefined if condition = 0xf otherwise upredictable 537 // if condition != 0xe 538 uint32_t Cond = (Insn >> 28) & 0xF; 539 if (Cond == 0xF) 540 return MCDisassembler::Fail; 541 if (Cond != 0xE) 542 return MCDisassembler::SoftFail; 543 return Result; 544 } 545 case ARM::t2ADDri: 546 case ARM::t2ADDri12: 547 case ARM::t2ADDrr: 548 case ARM::t2ADDrs: 549 case ARM::t2SUBri: 550 case ARM::t2SUBri12: 551 case ARM::t2SUBrr: 552 case ARM::t2SUBrs: 553 if (MI.getOperand(0).getReg() == ARM::SP && 554 MI.getOperand(1).getReg() != ARM::SP) 555 return MCDisassembler::SoftFail; 556 return Result; 557 default: return Result; 558 } 559 } 560 561 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 562 ArrayRef<uint8_t> Bytes, 563 uint64_t Address, raw_ostream &OS, 564 raw_ostream &CS) const { 565 CommentStream = &CS; 566 567 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 568 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 569 "mode!"); 570 571 // We want to read exactly 4 bytes of data. 572 if (Bytes.size() < 4) { 573 Size = 0; 574 return MCDisassembler::Fail; 575 } 576 577 // Encoded as a small-endian 32-bit word in the stream. 578 uint32_t Insn = 579 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 580 581 // Calling the auto-generated decoder function. 582 DecodeStatus Result = 583 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 584 if (Result != MCDisassembler::Fail) { 585 Size = 4; 586 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 587 } 588 589 struct DecodeTable { 590 const uint8_t *P; 591 bool DecodePred; 592 }; 593 594 const DecodeTable Tables[] = { 595 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 596 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 597 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 598 {DecoderTablev8Crypto32, false}, 599 }; 600 601 for (auto Table : Tables) { 602 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 603 if (Result != MCDisassembler::Fail) { 604 Size = 4; 605 // Add a fake predicate operand, because we share these instruction 606 // definitions with Thumb2 where these instructions are predicable. 607 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 608 return MCDisassembler::Fail; 609 return Result; 610 } 611 } 612 613 Result = 614 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 615 if (Result != MCDisassembler::Fail) { 616 Size = 4; 617 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 618 } 619 620 Size = 4; 621 return MCDisassembler::Fail; 622 } 623 624 namespace llvm { 625 626 extern const MCInstrDesc ARMInsts[]; 627 628 } // end namespace llvm 629 630 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 631 /// immediate Value in the MCInst. The immediate Value has had any PC 632 /// adjustment made by the caller. If the instruction is a branch instruction 633 /// then isBranch is true, else false. If the getOpInfo() function was set as 634 /// part of the setupForSymbolicDisassembly() call then that function is called 635 /// to get any symbolic information at the Address for this instruction. If 636 /// that returns non-zero then the symbolic information it returns is used to 637 /// create an MCExpr and that is added as an operand to the MCInst. If 638 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 639 /// Value is done and if a symbol is found an MCExpr is created with that, else 640 /// an MCExpr with Value is created. This function returns true if it adds an 641 /// operand to the MCInst and false otherwise. 642 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 643 bool isBranch, uint64_t InstSize, 644 MCInst &MI, const void *Decoder) { 645 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 646 // FIXME: Does it make sense for value to be negative? 647 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 648 /* Offset */ 0, InstSize); 649 } 650 651 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 652 /// referenced by a load instruction with the base register that is the Pc. 653 /// These can often be values in a literal pool near the Address of the 654 /// instruction. The Address of the instruction and its immediate Value are 655 /// used as a possible literal pool entry. The SymbolLookUp call back will 656 /// return the name of a symbol referenced by the literal pool's entry if 657 /// the referenced address is that of a symbol. Or it will return a pointer to 658 /// a literal 'C' string if the referenced address of the literal pool's entry 659 /// is an address into a section with 'C' string literals. 660 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 661 const void *Decoder) { 662 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 663 Dis->tryAddingPcLoadReferenceComment(Value, Address); 664 } 665 666 // Thumb1 instructions don't have explicit S bits. Rather, they 667 // implicitly set CPSR. Since it's not represented in the encoding, the 668 // auto-generated decoder won't inject the CPSR operand. We need to fix 669 // that as a post-pass. 670 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 671 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 672 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 673 MCInst::iterator I = MI.begin(); 674 for (unsigned i = 0; i < NumOps; ++i, ++I) { 675 if (I == MI.end()) break; 676 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 677 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 678 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 679 return; 680 } 681 } 682 683 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 684 } 685 686 static bool isVectorPredicable(unsigned Opcode) { 687 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 688 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 689 for (unsigned i = 0; i < NumOps; ++i) { 690 if (ARM::isVpred(OpInfo[i].OperandType)) 691 return true; 692 } 693 return false; 694 } 695 696 // Most Thumb instructions don't have explicit predicates in the 697 // encoding, but rather get their predicates from IT context. We need 698 // to fix up the predicate operands using this context information as a 699 // post-pass. 700 MCDisassembler::DecodeStatus 701 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 702 MCDisassembler::DecodeStatus S = Success; 703 704 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 705 706 // A few instructions actually have predicates encoded in them. Don't 707 // try to overwrite it if we're seeing one of those. 708 switch (MI.getOpcode()) { 709 case ARM::tBcc: 710 case ARM::t2Bcc: 711 case ARM::tCBZ: 712 case ARM::tCBNZ: 713 case ARM::tCPS: 714 case ARM::t2CPS3p: 715 case ARM::t2CPS2p: 716 case ARM::t2CPS1p: 717 case ARM::t2CSEL: 718 case ARM::t2CSINC: 719 case ARM::t2CSINV: 720 case ARM::t2CSNEG: 721 case ARM::tMOVSr: 722 case ARM::tSETEND: 723 // Some instructions (mostly conditional branches) are not 724 // allowed in IT blocks. 725 if (ITBlock.instrInITBlock()) 726 S = SoftFail; 727 else 728 return Success; 729 break; 730 case ARM::t2HINT: 731 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 732 S = SoftFail; 733 break; 734 case ARM::tB: 735 case ARM::t2B: 736 case ARM::t2TBB: 737 case ARM::t2TBH: 738 // Some instructions (mostly unconditional branches) can 739 // only appears at the end of, or outside of, an IT. 740 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 741 S = SoftFail; 742 break; 743 default: 744 break; 745 } 746 747 // Warn on non-VPT predicable instruction in a VPT block and a VPT 748 // predicable instruction in an IT block 749 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 750 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 751 S = SoftFail; 752 753 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 754 // assume a predicate of AL. 755 unsigned CC = ARMCC::AL; 756 unsigned VCC = ARMVCC::None; 757 if (ITBlock.instrInITBlock()) { 758 CC = ITBlock.getITCC(); 759 ITBlock.advanceITState(); 760 } else if (VPTBlock.instrInVPTBlock()) { 761 VCC = VPTBlock.getVPTPred(); 762 VPTBlock.advanceVPTState(); 763 } 764 765 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 766 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 767 768 MCInst::iterator CCI = MI.begin(); 769 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 770 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 771 } 772 773 if (ARMInsts[MI.getOpcode()].isPredicable()) { 774 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 775 ++CCI; 776 if (CC == ARMCC::AL) 777 MI.insert(CCI, MCOperand::createReg(0)); 778 else 779 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 780 } else if (CC != ARMCC::AL) { 781 Check(S, SoftFail); 782 } 783 784 MCInst::iterator VCCI = MI.begin(); 785 unsigned VCCPos; 786 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 787 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 788 } 789 790 if (isVectorPredicable(MI.getOpcode())) { 791 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 792 ++VCCI; 793 if (VCC == ARMVCC::None) 794 MI.insert(VCCI, MCOperand::createReg(0)); 795 else 796 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 797 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 798 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 799 VCCPos + 2, MCOI::TIED_TO); 800 assert(TiedOp >= 0 && 801 "Inactive register in vpred_r is not tied to an output!"); 802 MI.insert(VCCI, MI.getOperand(TiedOp)); 803 } 804 } else if (VCC != ARMVCC::None) { 805 Check(S, SoftFail); 806 } 807 808 return S; 809 } 810 811 // Thumb VFP instructions are a special case. Because we share their 812 // encodings between ARM and Thumb modes, and they are predicable in ARM 813 // mode, the auto-generated decoder will give them an (incorrect) 814 // predicate operand. We need to rewrite these operands based on the IT 815 // context as a post-pass. 816 void ThumbDisassembler::UpdateThumbVFPPredicate( 817 DecodeStatus &S, MCInst &MI) const { 818 unsigned CC; 819 CC = ITBlock.getITCC(); 820 if (CC == 0xF) 821 CC = ARMCC::AL; 822 if (ITBlock.instrInITBlock()) 823 ITBlock.advanceITState(); 824 else if (VPTBlock.instrInVPTBlock()) { 825 CC = VPTBlock.getVPTPred(); 826 VPTBlock.advanceVPTState(); 827 } 828 829 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 830 MCInst::iterator I = MI.begin(); 831 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 832 for (unsigned i = 0; i < NumOps; ++i, ++I) { 833 if (OpInfo[i].isPredicate() ) { 834 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 835 Check(S, SoftFail); 836 I->setImm(CC); 837 ++I; 838 if (CC == ARMCC::AL) 839 I->setReg(0); 840 else 841 I->setReg(ARM::CPSR); 842 return; 843 } 844 } 845 } 846 847 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 848 ArrayRef<uint8_t> Bytes, 849 uint64_t Address, 850 raw_ostream &OS, 851 raw_ostream &CS) const { 852 CommentStream = &CS; 853 854 assert(STI.getFeatureBits()[ARM::ModeThumb] && 855 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 856 857 // We want to read exactly 2 bytes of data. 858 if (Bytes.size() < 2) { 859 Size = 0; 860 return MCDisassembler::Fail; 861 } 862 863 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 864 DecodeStatus Result = 865 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 866 if (Result != MCDisassembler::Fail) { 867 Size = 2; 868 Check(Result, AddThumbPredicate(MI)); 869 return Result; 870 } 871 872 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 873 STI); 874 if (Result) { 875 Size = 2; 876 bool InITBlock = ITBlock.instrInITBlock(); 877 Check(Result, AddThumbPredicate(MI)); 878 AddThumb1SBit(MI, InITBlock); 879 return Result; 880 } 881 882 Result = 883 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 884 if (Result != MCDisassembler::Fail) { 885 Size = 2; 886 887 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 888 // the Thumb predicate. 889 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 890 Result = MCDisassembler::SoftFail; 891 892 Check(Result, AddThumbPredicate(MI)); 893 894 // If we find an IT instruction, we need to parse its condition 895 // code and mask operands so that we can apply them correctly 896 // to the subsequent instructions. 897 if (MI.getOpcode() == ARM::t2IT) { 898 unsigned Firstcond = MI.getOperand(0).getImm(); 899 unsigned Mask = MI.getOperand(1).getImm(); 900 ITBlock.setITState(Firstcond, Mask); 901 902 // An IT instruction that would give a 'NV' predicate is unpredictable. 903 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 904 CS << "unpredictable IT predicate sequence"; 905 } 906 907 return Result; 908 } 909 910 // We want to read exactly 4 bytes of data. 911 if (Bytes.size() < 4) { 912 Size = 0; 913 return MCDisassembler::Fail; 914 } 915 916 uint32_t Insn32 = 917 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 918 919 Result = 920 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 921 if (Result != MCDisassembler::Fail) { 922 Size = 4; 923 924 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 925 // the VPT predicate. 926 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 927 Result = MCDisassembler::SoftFail; 928 929 Check(Result, AddThumbPredicate(MI)); 930 931 if (isVPTOpcode(MI.getOpcode())) { 932 unsigned Mask = MI.getOperand(0).getImm(); 933 VPTBlock.setVPTState(Mask); 934 } 935 936 return Result; 937 } 938 939 Result = 940 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 941 if (Result != MCDisassembler::Fail) { 942 Size = 4; 943 bool InITBlock = ITBlock.instrInITBlock(); 944 Check(Result, AddThumbPredicate(MI)); 945 AddThumb1SBit(MI, InITBlock); 946 return Result; 947 } 948 949 Result = 950 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 951 if (Result != MCDisassembler::Fail) { 952 Size = 4; 953 Check(Result, AddThumbPredicate(MI)); 954 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 955 } 956 957 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 958 Result = 959 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 960 if (Result != MCDisassembler::Fail) { 961 Size = 4; 962 UpdateThumbVFPPredicate(Result, MI); 963 return Result; 964 } 965 } 966 967 Result = 968 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 969 if (Result != MCDisassembler::Fail) { 970 Size = 4; 971 return Result; 972 } 973 974 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 975 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 976 STI); 977 if (Result != MCDisassembler::Fail) { 978 Size = 4; 979 Check(Result, AddThumbPredicate(MI)); 980 return Result; 981 } 982 } 983 984 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 985 uint32_t NEONLdStInsn = Insn32; 986 NEONLdStInsn &= 0xF0FFFFFF; 987 NEONLdStInsn |= 0x04000000; 988 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 989 Address, this, STI); 990 if (Result != MCDisassembler::Fail) { 991 Size = 4; 992 Check(Result, AddThumbPredicate(MI)); 993 return Result; 994 } 995 } 996 997 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 998 uint32_t NEONDataInsn = Insn32; 999 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1000 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1001 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1002 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1003 Address, this, STI); 1004 if (Result != MCDisassembler::Fail) { 1005 Size = 4; 1006 Check(Result, AddThumbPredicate(MI)); 1007 return Result; 1008 } 1009 1010 uint32_t NEONCryptoInsn = Insn32; 1011 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1012 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1013 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1014 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1015 Address, this, STI); 1016 if (Result != MCDisassembler::Fail) { 1017 Size = 4; 1018 return Result; 1019 } 1020 1021 uint32_t NEONv8Insn = Insn32; 1022 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1023 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1024 this, STI); 1025 if (Result != MCDisassembler::Fail) { 1026 Size = 4; 1027 return Result; 1028 } 1029 } 1030 1031 Result = 1032 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1033 if (Result != MCDisassembler::Fail) { 1034 Size = 4; 1035 Check(Result, AddThumbPredicate(MI)); 1036 return Result; 1037 } 1038 1039 Size = 0; 1040 return MCDisassembler::Fail; 1041 } 1042 1043 extern "C" void LLVMInitializeARMDisassembler() { 1044 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1045 createARMDisassembler); 1046 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1047 createARMDisassembler); 1048 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1049 createThumbDisassembler); 1050 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1051 createThumbDisassembler); 1052 } 1053 1054 static const uint16_t GPRDecoderTable[] = { 1055 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1056 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1057 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1058 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1059 }; 1060 1061 static const uint16_t CLRMGPRDecoderTable[] = { 1062 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1063 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1064 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1065 ARM::R12, 0, ARM::LR, ARM::APSR 1066 }; 1067 1068 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1069 uint64_t Address, const void *Decoder) { 1070 if (RegNo > 15) 1071 return MCDisassembler::Fail; 1072 1073 unsigned Register = GPRDecoderTable[RegNo]; 1074 Inst.addOperand(MCOperand::createReg(Register)); 1075 return MCDisassembler::Success; 1076 } 1077 1078 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1079 uint64_t Address, 1080 const void *Decoder) { 1081 if (RegNo > 15) 1082 return MCDisassembler::Fail; 1083 1084 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1085 if (Register == 0) 1086 return MCDisassembler::Fail; 1087 1088 Inst.addOperand(MCOperand::createReg(Register)); 1089 return MCDisassembler::Success; 1090 } 1091 1092 static DecodeStatus 1093 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1094 uint64_t Address, const void *Decoder) { 1095 DecodeStatus S = MCDisassembler::Success; 1096 1097 if (RegNo == 15) 1098 S = MCDisassembler::SoftFail; 1099 1100 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1101 1102 return S; 1103 } 1104 1105 static DecodeStatus 1106 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1107 uint64_t Address, const void *Decoder) { 1108 DecodeStatus S = MCDisassembler::Success; 1109 1110 if (RegNo == 15) 1111 { 1112 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1113 return MCDisassembler::Success; 1114 } 1115 1116 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1117 return S; 1118 } 1119 1120 static DecodeStatus 1121 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1122 uint64_t Address, const void *Decoder) { 1123 DecodeStatus S = MCDisassembler::Success; 1124 1125 if (RegNo == 15) 1126 { 1127 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1128 return MCDisassembler::Success; 1129 } 1130 1131 if (RegNo == 13) 1132 S = MCDisassembler::SoftFail; 1133 1134 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1135 return S; 1136 } 1137 1138 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1139 uint64_t Address, const void *Decoder) { 1140 if (RegNo > 7) 1141 return MCDisassembler::Fail; 1142 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1143 } 1144 1145 static const uint16_t GPRPairDecoderTable[] = { 1146 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1147 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1148 }; 1149 1150 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1151 uint64_t Address, const void *Decoder) { 1152 DecodeStatus S = MCDisassembler::Success; 1153 1154 if (RegNo > 13) 1155 return MCDisassembler::Fail; 1156 1157 if ((RegNo & 1) || RegNo == 0xe) 1158 S = MCDisassembler::SoftFail; 1159 1160 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1161 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1162 return S; 1163 } 1164 1165 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1166 uint64_t Address, const void *Decoder) { 1167 unsigned Register = 0; 1168 switch (RegNo) { 1169 case 0: 1170 Register = ARM::R0; 1171 break; 1172 case 1: 1173 Register = ARM::R1; 1174 break; 1175 case 2: 1176 Register = ARM::R2; 1177 break; 1178 case 3: 1179 Register = ARM::R3; 1180 break; 1181 case 9: 1182 Register = ARM::R9; 1183 break; 1184 case 12: 1185 Register = ARM::R12; 1186 break; 1187 default: 1188 return MCDisassembler::Fail; 1189 } 1190 1191 Inst.addOperand(MCOperand::createReg(Register)); 1192 return MCDisassembler::Success; 1193 } 1194 1195 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1196 uint64_t Address, const void *Decoder) { 1197 DecodeStatus S = MCDisassembler::Success; 1198 1199 const FeatureBitset &featureBits = 1200 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1201 1202 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1203 S = MCDisassembler::SoftFail; 1204 1205 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1206 return S; 1207 } 1208 1209 static const uint16_t SPRDecoderTable[] = { 1210 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1211 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1212 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1213 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1214 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1215 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1216 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1217 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1218 }; 1219 1220 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1221 uint64_t Address, const void *Decoder) { 1222 if (RegNo > 31) 1223 return MCDisassembler::Fail; 1224 1225 unsigned Register = SPRDecoderTable[RegNo]; 1226 Inst.addOperand(MCOperand::createReg(Register)); 1227 return MCDisassembler::Success; 1228 } 1229 1230 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1231 uint64_t Address, const void *Decoder) { 1232 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1233 } 1234 1235 static const uint16_t DPRDecoderTable[] = { 1236 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1237 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1238 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1239 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1240 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1241 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1242 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1243 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1244 }; 1245 1246 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1247 uint64_t Address, const void *Decoder) { 1248 const FeatureBitset &featureBits = 1249 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1250 1251 bool hasD32 = featureBits[ARM::FeatureD32]; 1252 1253 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1254 return MCDisassembler::Fail; 1255 1256 unsigned Register = DPRDecoderTable[RegNo]; 1257 Inst.addOperand(MCOperand::createReg(Register)); 1258 return MCDisassembler::Success; 1259 } 1260 1261 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1262 uint64_t Address, const void *Decoder) { 1263 if (RegNo > 7) 1264 return MCDisassembler::Fail; 1265 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1266 } 1267 1268 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1269 uint64_t Address, const void *Decoder) { 1270 if (RegNo > 15) 1271 return MCDisassembler::Fail; 1272 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1273 } 1274 1275 static DecodeStatus 1276 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1277 uint64_t Address, const void *Decoder) { 1278 if (RegNo > 15) 1279 return MCDisassembler::Fail; 1280 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1281 } 1282 1283 static const uint16_t QPRDecoderTable[] = { 1284 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1285 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1286 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1287 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1288 }; 1289 1290 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1291 uint64_t Address, const void *Decoder) { 1292 if (RegNo > 31 || (RegNo & 1) != 0) 1293 return MCDisassembler::Fail; 1294 RegNo >>= 1; 1295 1296 unsigned Register = QPRDecoderTable[RegNo]; 1297 Inst.addOperand(MCOperand::createReg(Register)); 1298 return MCDisassembler::Success; 1299 } 1300 1301 static const uint16_t DPairDecoderTable[] = { 1302 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1303 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1304 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1305 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1306 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1307 ARM::Q15 1308 }; 1309 1310 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1311 uint64_t Address, const void *Decoder) { 1312 if (RegNo > 30) 1313 return MCDisassembler::Fail; 1314 1315 unsigned Register = DPairDecoderTable[RegNo]; 1316 Inst.addOperand(MCOperand::createReg(Register)); 1317 return MCDisassembler::Success; 1318 } 1319 1320 static const uint16_t DPairSpacedDecoderTable[] = { 1321 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1322 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1323 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1324 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1325 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1326 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1327 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1328 ARM::D28_D30, ARM::D29_D31 1329 }; 1330 1331 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1332 unsigned RegNo, 1333 uint64_t Address, 1334 const void *Decoder) { 1335 if (RegNo > 29) 1336 return MCDisassembler::Fail; 1337 1338 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1339 Inst.addOperand(MCOperand::createReg(Register)); 1340 return MCDisassembler::Success; 1341 } 1342 1343 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1344 uint64_t Address, const void *Decoder) { 1345 DecodeStatus S = MCDisassembler::Success; 1346 if (Val == 0xF) return MCDisassembler::Fail; 1347 // AL predicate is not allowed on Thumb1 branches. 1348 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1349 return MCDisassembler::Fail; 1350 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1351 Check(S, MCDisassembler::SoftFail); 1352 Inst.addOperand(MCOperand::createImm(Val)); 1353 if (Val == ARMCC::AL) { 1354 Inst.addOperand(MCOperand::createReg(0)); 1355 } else 1356 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1357 return S; 1358 } 1359 1360 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1361 uint64_t Address, const void *Decoder) { 1362 if (Val) 1363 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1364 else 1365 Inst.addOperand(MCOperand::createReg(0)); 1366 return MCDisassembler::Success; 1367 } 1368 1369 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1370 uint64_t Address, const void *Decoder) { 1371 DecodeStatus S = MCDisassembler::Success; 1372 1373 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1374 unsigned type = fieldFromInstruction(Val, 5, 2); 1375 unsigned imm = fieldFromInstruction(Val, 7, 5); 1376 1377 // Register-immediate 1378 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1379 return MCDisassembler::Fail; 1380 1381 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1382 switch (type) { 1383 case 0: 1384 Shift = ARM_AM::lsl; 1385 break; 1386 case 1: 1387 Shift = ARM_AM::lsr; 1388 break; 1389 case 2: 1390 Shift = ARM_AM::asr; 1391 break; 1392 case 3: 1393 Shift = ARM_AM::ror; 1394 break; 1395 } 1396 1397 if (Shift == ARM_AM::ror && imm == 0) 1398 Shift = ARM_AM::rrx; 1399 1400 unsigned Op = Shift | (imm << 3); 1401 Inst.addOperand(MCOperand::createImm(Op)); 1402 1403 return S; 1404 } 1405 1406 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1407 uint64_t Address, const void *Decoder) { 1408 DecodeStatus S = MCDisassembler::Success; 1409 1410 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1411 unsigned type = fieldFromInstruction(Val, 5, 2); 1412 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1413 1414 // Register-register 1415 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1416 return MCDisassembler::Fail; 1417 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1418 return MCDisassembler::Fail; 1419 1420 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1421 switch (type) { 1422 case 0: 1423 Shift = ARM_AM::lsl; 1424 break; 1425 case 1: 1426 Shift = ARM_AM::lsr; 1427 break; 1428 case 2: 1429 Shift = ARM_AM::asr; 1430 break; 1431 case 3: 1432 Shift = ARM_AM::ror; 1433 break; 1434 } 1435 1436 Inst.addOperand(MCOperand::createImm(Shift)); 1437 1438 return S; 1439 } 1440 1441 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1442 uint64_t Address, const void *Decoder) { 1443 DecodeStatus S = MCDisassembler::Success; 1444 1445 bool NeedDisjointWriteback = false; 1446 unsigned WritebackReg = 0; 1447 bool CLRM = false; 1448 switch (Inst.getOpcode()) { 1449 default: 1450 break; 1451 case ARM::LDMIA_UPD: 1452 case ARM::LDMDB_UPD: 1453 case ARM::LDMIB_UPD: 1454 case ARM::LDMDA_UPD: 1455 case ARM::t2LDMIA_UPD: 1456 case ARM::t2LDMDB_UPD: 1457 case ARM::t2STMIA_UPD: 1458 case ARM::t2STMDB_UPD: 1459 NeedDisjointWriteback = true; 1460 WritebackReg = Inst.getOperand(0).getReg(); 1461 break; 1462 case ARM::t2CLRM: 1463 CLRM = true; 1464 break; 1465 } 1466 1467 // Empty register lists are not allowed. 1468 if (Val == 0) return MCDisassembler::Fail; 1469 for (unsigned i = 0; i < 16; ++i) { 1470 if (Val & (1 << i)) { 1471 if (CLRM) { 1472 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1473 return MCDisassembler::Fail; 1474 } 1475 } else { 1476 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1477 return MCDisassembler::Fail; 1478 // Writeback not allowed if Rn is in the target list. 1479 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1480 Check(S, MCDisassembler::SoftFail); 1481 } 1482 } 1483 } 1484 1485 return S; 1486 } 1487 1488 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1489 uint64_t Address, const void *Decoder) { 1490 DecodeStatus S = MCDisassembler::Success; 1491 1492 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1493 unsigned regs = fieldFromInstruction(Val, 0, 8); 1494 1495 // In case of unpredictable encoding, tweak the operands. 1496 if (regs == 0 || (Vd + regs) > 32) { 1497 regs = Vd + regs > 32 ? 32 - Vd : regs; 1498 regs = std::max( 1u, regs); 1499 S = MCDisassembler::SoftFail; 1500 } 1501 1502 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1503 return MCDisassembler::Fail; 1504 for (unsigned i = 0; i < (regs - 1); ++i) { 1505 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1506 return MCDisassembler::Fail; 1507 } 1508 1509 return S; 1510 } 1511 1512 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1513 uint64_t Address, const void *Decoder) { 1514 DecodeStatus S = MCDisassembler::Success; 1515 1516 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1517 unsigned regs = fieldFromInstruction(Val, 1, 7); 1518 1519 // In case of unpredictable encoding, tweak the operands. 1520 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1521 regs = Vd + regs > 32 ? 32 - Vd : regs; 1522 regs = std::max( 1u, regs); 1523 regs = std::min(16u, regs); 1524 S = MCDisassembler::SoftFail; 1525 } 1526 1527 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1528 return MCDisassembler::Fail; 1529 for (unsigned i = 0; i < (regs - 1); ++i) { 1530 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1531 return MCDisassembler::Fail; 1532 } 1533 1534 return S; 1535 } 1536 1537 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1538 uint64_t Address, const void *Decoder) { 1539 // This operand encodes a mask of contiguous zeros between a specified MSB 1540 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1541 // the mask of all bits LSB-and-lower, and then xor them to create 1542 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1543 // create the final mask. 1544 unsigned msb = fieldFromInstruction(Val, 5, 5); 1545 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1546 1547 DecodeStatus S = MCDisassembler::Success; 1548 if (lsb > msb) { 1549 Check(S, MCDisassembler::SoftFail); 1550 // The check above will cause the warning for the "potentially undefined 1551 // instruction encoding" but we can't build a bad MCOperand value here 1552 // with a lsb > msb or else printing the MCInst will cause a crash. 1553 lsb = msb; 1554 } 1555 1556 uint32_t msb_mask = 0xFFFFFFFF; 1557 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1558 uint32_t lsb_mask = (1U << lsb) - 1; 1559 1560 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1561 return S; 1562 } 1563 1564 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1565 uint64_t Address, const void *Decoder) { 1566 DecodeStatus S = MCDisassembler::Success; 1567 1568 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1569 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1570 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1571 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1572 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1573 unsigned U = fieldFromInstruction(Insn, 23, 1); 1574 const FeatureBitset &featureBits = 1575 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1576 1577 switch (Inst.getOpcode()) { 1578 case ARM::LDC_OFFSET: 1579 case ARM::LDC_PRE: 1580 case ARM::LDC_POST: 1581 case ARM::LDC_OPTION: 1582 case ARM::LDCL_OFFSET: 1583 case ARM::LDCL_PRE: 1584 case ARM::LDCL_POST: 1585 case ARM::LDCL_OPTION: 1586 case ARM::STC_OFFSET: 1587 case ARM::STC_PRE: 1588 case ARM::STC_POST: 1589 case ARM::STC_OPTION: 1590 case ARM::STCL_OFFSET: 1591 case ARM::STCL_PRE: 1592 case ARM::STCL_POST: 1593 case ARM::STCL_OPTION: 1594 case ARM::t2LDC_OFFSET: 1595 case ARM::t2LDC_PRE: 1596 case ARM::t2LDC_POST: 1597 case ARM::t2LDC_OPTION: 1598 case ARM::t2LDCL_OFFSET: 1599 case ARM::t2LDCL_PRE: 1600 case ARM::t2LDCL_POST: 1601 case ARM::t2LDCL_OPTION: 1602 case ARM::t2STC_OFFSET: 1603 case ARM::t2STC_PRE: 1604 case ARM::t2STC_POST: 1605 case ARM::t2STC_OPTION: 1606 case ARM::t2STCL_OFFSET: 1607 case ARM::t2STCL_PRE: 1608 case ARM::t2STCL_POST: 1609 case ARM::t2STCL_OPTION: 1610 case ARM::t2LDC2_OFFSET: 1611 case ARM::t2LDC2L_OFFSET: 1612 case ARM::t2LDC2_PRE: 1613 case ARM::t2LDC2L_PRE: 1614 case ARM::t2STC2_OFFSET: 1615 case ARM::t2STC2L_OFFSET: 1616 case ARM::t2STC2_PRE: 1617 case ARM::t2STC2L_PRE: 1618 case ARM::LDC2_OFFSET: 1619 case ARM::LDC2L_OFFSET: 1620 case ARM::LDC2_PRE: 1621 case ARM::LDC2L_PRE: 1622 case ARM::STC2_OFFSET: 1623 case ARM::STC2L_OFFSET: 1624 case ARM::STC2_PRE: 1625 case ARM::STC2L_PRE: 1626 case ARM::t2LDC2_OPTION: 1627 case ARM::t2STC2_OPTION: 1628 case ARM::t2LDC2_POST: 1629 case ARM::t2LDC2L_POST: 1630 case ARM::t2STC2_POST: 1631 case ARM::t2STC2L_POST: 1632 case ARM::LDC2_POST: 1633 case ARM::LDC2L_POST: 1634 case ARM::STC2_POST: 1635 case ARM::STC2L_POST: 1636 if (coproc == 0xA || coproc == 0xB || 1637 (featureBits[ARM::HasV8_1MMainlineOps] && 1638 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1639 coproc == 0xE || coproc == 0xF))) 1640 return MCDisassembler::Fail; 1641 break; 1642 default: 1643 break; 1644 } 1645 1646 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1647 return MCDisassembler::Fail; 1648 1649 Inst.addOperand(MCOperand::createImm(coproc)); 1650 Inst.addOperand(MCOperand::createImm(CRd)); 1651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1652 return MCDisassembler::Fail; 1653 1654 switch (Inst.getOpcode()) { 1655 case ARM::t2LDC2_OFFSET: 1656 case ARM::t2LDC2L_OFFSET: 1657 case ARM::t2LDC2_PRE: 1658 case ARM::t2LDC2L_PRE: 1659 case ARM::t2STC2_OFFSET: 1660 case ARM::t2STC2L_OFFSET: 1661 case ARM::t2STC2_PRE: 1662 case ARM::t2STC2L_PRE: 1663 case ARM::LDC2_OFFSET: 1664 case ARM::LDC2L_OFFSET: 1665 case ARM::LDC2_PRE: 1666 case ARM::LDC2L_PRE: 1667 case ARM::STC2_OFFSET: 1668 case ARM::STC2L_OFFSET: 1669 case ARM::STC2_PRE: 1670 case ARM::STC2L_PRE: 1671 case ARM::t2LDC_OFFSET: 1672 case ARM::t2LDCL_OFFSET: 1673 case ARM::t2LDC_PRE: 1674 case ARM::t2LDCL_PRE: 1675 case ARM::t2STC_OFFSET: 1676 case ARM::t2STCL_OFFSET: 1677 case ARM::t2STC_PRE: 1678 case ARM::t2STCL_PRE: 1679 case ARM::LDC_OFFSET: 1680 case ARM::LDCL_OFFSET: 1681 case ARM::LDC_PRE: 1682 case ARM::LDCL_PRE: 1683 case ARM::STC_OFFSET: 1684 case ARM::STCL_OFFSET: 1685 case ARM::STC_PRE: 1686 case ARM::STCL_PRE: 1687 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1688 Inst.addOperand(MCOperand::createImm(imm)); 1689 break; 1690 case ARM::t2LDC2_POST: 1691 case ARM::t2LDC2L_POST: 1692 case ARM::t2STC2_POST: 1693 case ARM::t2STC2L_POST: 1694 case ARM::LDC2_POST: 1695 case ARM::LDC2L_POST: 1696 case ARM::STC2_POST: 1697 case ARM::STC2L_POST: 1698 case ARM::t2LDC_POST: 1699 case ARM::t2LDCL_POST: 1700 case ARM::t2STC_POST: 1701 case ARM::t2STCL_POST: 1702 case ARM::LDC_POST: 1703 case ARM::LDCL_POST: 1704 case ARM::STC_POST: 1705 case ARM::STCL_POST: 1706 imm |= U << 8; 1707 LLVM_FALLTHROUGH; 1708 default: 1709 // The 'option' variant doesn't encode 'U' in the immediate since 1710 // the immediate is unsigned [0,255]. 1711 Inst.addOperand(MCOperand::createImm(imm)); 1712 break; 1713 } 1714 1715 switch (Inst.getOpcode()) { 1716 case ARM::LDC_OFFSET: 1717 case ARM::LDC_PRE: 1718 case ARM::LDC_POST: 1719 case ARM::LDC_OPTION: 1720 case ARM::LDCL_OFFSET: 1721 case ARM::LDCL_PRE: 1722 case ARM::LDCL_POST: 1723 case ARM::LDCL_OPTION: 1724 case ARM::STC_OFFSET: 1725 case ARM::STC_PRE: 1726 case ARM::STC_POST: 1727 case ARM::STC_OPTION: 1728 case ARM::STCL_OFFSET: 1729 case ARM::STCL_PRE: 1730 case ARM::STCL_POST: 1731 case ARM::STCL_OPTION: 1732 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1733 return MCDisassembler::Fail; 1734 break; 1735 default: 1736 break; 1737 } 1738 1739 return S; 1740 } 1741 1742 static DecodeStatus 1743 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1744 uint64_t Address, const void *Decoder) { 1745 DecodeStatus S = MCDisassembler::Success; 1746 1747 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1748 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1749 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1750 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1751 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1752 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1753 unsigned P = fieldFromInstruction(Insn, 24, 1); 1754 unsigned W = fieldFromInstruction(Insn, 21, 1); 1755 1756 // On stores, the writeback operand precedes Rt. 1757 switch (Inst.getOpcode()) { 1758 case ARM::STR_POST_IMM: 1759 case ARM::STR_POST_REG: 1760 case ARM::STRB_POST_IMM: 1761 case ARM::STRB_POST_REG: 1762 case ARM::STRT_POST_REG: 1763 case ARM::STRT_POST_IMM: 1764 case ARM::STRBT_POST_REG: 1765 case ARM::STRBT_POST_IMM: 1766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1767 return MCDisassembler::Fail; 1768 break; 1769 default: 1770 break; 1771 } 1772 1773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1774 return MCDisassembler::Fail; 1775 1776 // On loads, the writeback operand comes after Rt. 1777 switch (Inst.getOpcode()) { 1778 case ARM::LDR_POST_IMM: 1779 case ARM::LDR_POST_REG: 1780 case ARM::LDRB_POST_IMM: 1781 case ARM::LDRB_POST_REG: 1782 case ARM::LDRBT_POST_REG: 1783 case ARM::LDRBT_POST_IMM: 1784 case ARM::LDRT_POST_REG: 1785 case ARM::LDRT_POST_IMM: 1786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1787 return MCDisassembler::Fail; 1788 break; 1789 default: 1790 break; 1791 } 1792 1793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 1796 ARM_AM::AddrOpc Op = ARM_AM::add; 1797 if (!fieldFromInstruction(Insn, 23, 1)) 1798 Op = ARM_AM::sub; 1799 1800 bool writeback = (P == 0) || (W == 1); 1801 unsigned idx_mode = 0; 1802 if (P && writeback) 1803 idx_mode = ARMII::IndexModePre; 1804 else if (!P && writeback) 1805 idx_mode = ARMII::IndexModePost; 1806 1807 if (writeback && (Rn == 15 || Rn == Rt)) 1808 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1809 1810 if (reg) { 1811 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1812 return MCDisassembler::Fail; 1813 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1814 switch( fieldFromInstruction(Insn, 5, 2)) { 1815 case 0: 1816 Opc = ARM_AM::lsl; 1817 break; 1818 case 1: 1819 Opc = ARM_AM::lsr; 1820 break; 1821 case 2: 1822 Opc = ARM_AM::asr; 1823 break; 1824 case 3: 1825 Opc = ARM_AM::ror; 1826 break; 1827 default: 1828 return MCDisassembler::Fail; 1829 } 1830 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1831 if (Opc == ARM_AM::ror && amt == 0) 1832 Opc = ARM_AM::rrx; 1833 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1834 1835 Inst.addOperand(MCOperand::createImm(imm)); 1836 } else { 1837 Inst.addOperand(MCOperand::createReg(0)); 1838 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1839 Inst.addOperand(MCOperand::createImm(tmp)); 1840 } 1841 1842 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1843 return MCDisassembler::Fail; 1844 1845 return S; 1846 } 1847 1848 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1849 uint64_t Address, const void *Decoder) { 1850 DecodeStatus S = MCDisassembler::Success; 1851 1852 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1853 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1854 unsigned type = fieldFromInstruction(Val, 5, 2); 1855 unsigned imm = fieldFromInstruction(Val, 7, 5); 1856 unsigned U = fieldFromInstruction(Val, 12, 1); 1857 1858 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1859 switch (type) { 1860 case 0: 1861 ShOp = ARM_AM::lsl; 1862 break; 1863 case 1: 1864 ShOp = ARM_AM::lsr; 1865 break; 1866 case 2: 1867 ShOp = ARM_AM::asr; 1868 break; 1869 case 3: 1870 ShOp = ARM_AM::ror; 1871 break; 1872 } 1873 1874 if (ShOp == ARM_AM::ror && imm == 0) 1875 ShOp = ARM_AM::rrx; 1876 1877 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1878 return MCDisassembler::Fail; 1879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1880 return MCDisassembler::Fail; 1881 unsigned shift; 1882 if (U) 1883 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1884 else 1885 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1886 Inst.addOperand(MCOperand::createImm(shift)); 1887 1888 return S; 1889 } 1890 1891 static DecodeStatus 1892 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1893 uint64_t Address, const void *Decoder) { 1894 DecodeStatus S = MCDisassembler::Success; 1895 1896 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1897 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1898 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1899 unsigned type = fieldFromInstruction(Insn, 22, 1); 1900 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1901 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1902 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1903 unsigned W = fieldFromInstruction(Insn, 21, 1); 1904 unsigned P = fieldFromInstruction(Insn, 24, 1); 1905 unsigned Rt2 = Rt + 1; 1906 1907 bool writeback = (W == 1) | (P == 0); 1908 1909 // For {LD,ST}RD, Rt must be even, else undefined. 1910 switch (Inst.getOpcode()) { 1911 case ARM::STRD: 1912 case ARM::STRD_PRE: 1913 case ARM::STRD_POST: 1914 case ARM::LDRD: 1915 case ARM::LDRD_PRE: 1916 case ARM::LDRD_POST: 1917 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1918 break; 1919 default: 1920 break; 1921 } 1922 switch (Inst.getOpcode()) { 1923 case ARM::STRD: 1924 case ARM::STRD_PRE: 1925 case ARM::STRD_POST: 1926 if (P == 0 && W == 1) 1927 S = MCDisassembler::SoftFail; 1928 1929 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1930 S = MCDisassembler::SoftFail; 1931 if (type && Rm == 15) 1932 S = MCDisassembler::SoftFail; 1933 if (Rt2 == 15) 1934 S = MCDisassembler::SoftFail; 1935 if (!type && fieldFromInstruction(Insn, 8, 4)) 1936 S = MCDisassembler::SoftFail; 1937 break; 1938 case ARM::STRH: 1939 case ARM::STRH_PRE: 1940 case ARM::STRH_POST: 1941 if (Rt == 15) 1942 S = MCDisassembler::SoftFail; 1943 if (writeback && (Rn == 15 || Rn == Rt)) 1944 S = MCDisassembler::SoftFail; 1945 if (!type && Rm == 15) 1946 S = MCDisassembler::SoftFail; 1947 break; 1948 case ARM::LDRD: 1949 case ARM::LDRD_PRE: 1950 case ARM::LDRD_POST: 1951 if (type && Rn == 15) { 1952 if (Rt2 == 15) 1953 S = MCDisassembler::SoftFail; 1954 break; 1955 } 1956 if (P == 0 && W == 1) 1957 S = MCDisassembler::SoftFail; 1958 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1959 S = MCDisassembler::SoftFail; 1960 if (!type && writeback && Rn == 15) 1961 S = MCDisassembler::SoftFail; 1962 if (writeback && (Rn == Rt || Rn == Rt2)) 1963 S = MCDisassembler::SoftFail; 1964 break; 1965 case ARM::LDRH: 1966 case ARM::LDRH_PRE: 1967 case ARM::LDRH_POST: 1968 if (type && Rn == 15) { 1969 if (Rt == 15) 1970 S = MCDisassembler::SoftFail; 1971 break; 1972 } 1973 if (Rt == 15) 1974 S = MCDisassembler::SoftFail; 1975 if (!type && Rm == 15) 1976 S = MCDisassembler::SoftFail; 1977 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1978 S = MCDisassembler::SoftFail; 1979 break; 1980 case ARM::LDRSH: 1981 case ARM::LDRSH_PRE: 1982 case ARM::LDRSH_POST: 1983 case ARM::LDRSB: 1984 case ARM::LDRSB_PRE: 1985 case ARM::LDRSB_POST: 1986 if (type && Rn == 15) { 1987 if (Rt == 15) 1988 S = MCDisassembler::SoftFail; 1989 break; 1990 } 1991 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1992 S = MCDisassembler::SoftFail; 1993 if (!type && (Rt == 15 || Rm == 15)) 1994 S = MCDisassembler::SoftFail; 1995 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1996 S = MCDisassembler::SoftFail; 1997 break; 1998 default: 1999 break; 2000 } 2001 2002 if (writeback) { // Writeback 2003 if (P) 2004 U |= ARMII::IndexModePre << 9; 2005 else 2006 U |= ARMII::IndexModePost << 9; 2007 2008 // On stores, the writeback operand precedes Rt. 2009 switch (Inst.getOpcode()) { 2010 case ARM::STRD: 2011 case ARM::STRD_PRE: 2012 case ARM::STRD_POST: 2013 case ARM::STRH: 2014 case ARM::STRH_PRE: 2015 case ARM::STRH_POST: 2016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2017 return MCDisassembler::Fail; 2018 break; 2019 default: 2020 break; 2021 } 2022 } 2023 2024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2025 return MCDisassembler::Fail; 2026 switch (Inst.getOpcode()) { 2027 case ARM::STRD: 2028 case ARM::STRD_PRE: 2029 case ARM::STRD_POST: 2030 case ARM::LDRD: 2031 case ARM::LDRD_PRE: 2032 case ARM::LDRD_POST: 2033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2034 return MCDisassembler::Fail; 2035 break; 2036 default: 2037 break; 2038 } 2039 2040 if (writeback) { 2041 // On loads, the writeback operand comes after Rt. 2042 switch (Inst.getOpcode()) { 2043 case ARM::LDRD: 2044 case ARM::LDRD_PRE: 2045 case ARM::LDRD_POST: 2046 case ARM::LDRH: 2047 case ARM::LDRH_PRE: 2048 case ARM::LDRH_POST: 2049 case ARM::LDRSH: 2050 case ARM::LDRSH_PRE: 2051 case ARM::LDRSH_POST: 2052 case ARM::LDRSB: 2053 case ARM::LDRSB_PRE: 2054 case ARM::LDRSB_POST: 2055 case ARM::LDRHTr: 2056 case ARM::LDRSBTr: 2057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2058 return MCDisassembler::Fail; 2059 break; 2060 default: 2061 break; 2062 } 2063 } 2064 2065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2066 return MCDisassembler::Fail; 2067 2068 if (type) { 2069 Inst.addOperand(MCOperand::createReg(0)); 2070 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2071 } else { 2072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2073 return MCDisassembler::Fail; 2074 Inst.addOperand(MCOperand::createImm(U)); 2075 } 2076 2077 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2078 return MCDisassembler::Fail; 2079 2080 return S; 2081 } 2082 2083 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2084 uint64_t Address, const void *Decoder) { 2085 DecodeStatus S = MCDisassembler::Success; 2086 2087 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2088 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2089 2090 switch (mode) { 2091 case 0: 2092 mode = ARM_AM::da; 2093 break; 2094 case 1: 2095 mode = ARM_AM::ia; 2096 break; 2097 case 2: 2098 mode = ARM_AM::db; 2099 break; 2100 case 3: 2101 mode = ARM_AM::ib; 2102 break; 2103 } 2104 2105 Inst.addOperand(MCOperand::createImm(mode)); 2106 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2107 return MCDisassembler::Fail; 2108 2109 return S; 2110 } 2111 2112 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2113 uint64_t Address, const void *Decoder) { 2114 DecodeStatus S = MCDisassembler::Success; 2115 2116 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2117 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2118 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2119 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2120 2121 if (pred == 0xF) 2122 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2123 2124 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2125 return MCDisassembler::Fail; 2126 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2127 return MCDisassembler::Fail; 2128 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2129 return MCDisassembler::Fail; 2130 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2131 return MCDisassembler::Fail; 2132 return S; 2133 } 2134 2135 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2136 unsigned Insn, 2137 uint64_t Address, const void *Decoder) { 2138 DecodeStatus S = MCDisassembler::Success; 2139 2140 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2141 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2142 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2143 2144 if (pred == 0xF) { 2145 // Ambiguous with RFE and SRS 2146 switch (Inst.getOpcode()) { 2147 case ARM::LDMDA: 2148 Inst.setOpcode(ARM::RFEDA); 2149 break; 2150 case ARM::LDMDA_UPD: 2151 Inst.setOpcode(ARM::RFEDA_UPD); 2152 break; 2153 case ARM::LDMDB: 2154 Inst.setOpcode(ARM::RFEDB); 2155 break; 2156 case ARM::LDMDB_UPD: 2157 Inst.setOpcode(ARM::RFEDB_UPD); 2158 break; 2159 case ARM::LDMIA: 2160 Inst.setOpcode(ARM::RFEIA); 2161 break; 2162 case ARM::LDMIA_UPD: 2163 Inst.setOpcode(ARM::RFEIA_UPD); 2164 break; 2165 case ARM::LDMIB: 2166 Inst.setOpcode(ARM::RFEIB); 2167 break; 2168 case ARM::LDMIB_UPD: 2169 Inst.setOpcode(ARM::RFEIB_UPD); 2170 break; 2171 case ARM::STMDA: 2172 Inst.setOpcode(ARM::SRSDA); 2173 break; 2174 case ARM::STMDA_UPD: 2175 Inst.setOpcode(ARM::SRSDA_UPD); 2176 break; 2177 case ARM::STMDB: 2178 Inst.setOpcode(ARM::SRSDB); 2179 break; 2180 case ARM::STMDB_UPD: 2181 Inst.setOpcode(ARM::SRSDB_UPD); 2182 break; 2183 case ARM::STMIA: 2184 Inst.setOpcode(ARM::SRSIA); 2185 break; 2186 case ARM::STMIA_UPD: 2187 Inst.setOpcode(ARM::SRSIA_UPD); 2188 break; 2189 case ARM::STMIB: 2190 Inst.setOpcode(ARM::SRSIB); 2191 break; 2192 case ARM::STMIB_UPD: 2193 Inst.setOpcode(ARM::SRSIB_UPD); 2194 break; 2195 default: 2196 return MCDisassembler::Fail; 2197 } 2198 2199 // For stores (which become SRS's, the only operand is the mode. 2200 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2201 // Check SRS encoding constraints 2202 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2203 fieldFromInstruction(Insn, 20, 1) == 0)) 2204 return MCDisassembler::Fail; 2205 2206 Inst.addOperand( 2207 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2208 return S; 2209 } 2210 2211 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2212 } 2213 2214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2215 return MCDisassembler::Fail; 2216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2217 return MCDisassembler::Fail; // Tied 2218 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2219 return MCDisassembler::Fail; 2220 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2221 return MCDisassembler::Fail; 2222 2223 return S; 2224 } 2225 2226 // Check for UNPREDICTABLE predicated ESB instruction 2227 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2228 uint64_t Address, const void *Decoder) { 2229 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2230 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2231 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2232 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2233 2234 DecodeStatus S = MCDisassembler::Success; 2235 2236 Inst.addOperand(MCOperand::createImm(imm8)); 2237 2238 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2239 return MCDisassembler::Fail; 2240 2241 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2242 // so all predicates should be allowed. 2243 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2244 S = MCDisassembler::SoftFail; 2245 2246 return S; 2247 } 2248 2249 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2250 uint64_t Address, const void *Decoder) { 2251 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2252 unsigned M = fieldFromInstruction(Insn, 17, 1); 2253 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2254 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2255 2256 DecodeStatus S = MCDisassembler::Success; 2257 2258 // This decoder is called from multiple location that do not check 2259 // the full encoding is valid before they do. 2260 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2261 fieldFromInstruction(Insn, 16, 1) != 0 || 2262 fieldFromInstruction(Insn, 20, 8) != 0x10) 2263 return MCDisassembler::Fail; 2264 2265 // imod == '01' --> UNPREDICTABLE 2266 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2267 // return failure here. The '01' imod value is unprintable, so there's 2268 // nothing useful we could do even if we returned UNPREDICTABLE. 2269 2270 if (imod == 1) return MCDisassembler::Fail; 2271 2272 if (imod && M) { 2273 Inst.setOpcode(ARM::CPS3p); 2274 Inst.addOperand(MCOperand::createImm(imod)); 2275 Inst.addOperand(MCOperand::createImm(iflags)); 2276 Inst.addOperand(MCOperand::createImm(mode)); 2277 } else if (imod && !M) { 2278 Inst.setOpcode(ARM::CPS2p); 2279 Inst.addOperand(MCOperand::createImm(imod)); 2280 Inst.addOperand(MCOperand::createImm(iflags)); 2281 if (mode) S = MCDisassembler::SoftFail; 2282 } else if (!imod && M) { 2283 Inst.setOpcode(ARM::CPS1p); 2284 Inst.addOperand(MCOperand::createImm(mode)); 2285 if (iflags) S = MCDisassembler::SoftFail; 2286 } else { 2287 // imod == '00' && M == '0' --> UNPREDICTABLE 2288 Inst.setOpcode(ARM::CPS1p); 2289 Inst.addOperand(MCOperand::createImm(mode)); 2290 S = MCDisassembler::SoftFail; 2291 } 2292 2293 return S; 2294 } 2295 2296 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2297 uint64_t Address, const void *Decoder) { 2298 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2299 unsigned M = fieldFromInstruction(Insn, 8, 1); 2300 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2301 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2302 2303 DecodeStatus S = MCDisassembler::Success; 2304 2305 // imod == '01' --> UNPREDICTABLE 2306 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2307 // return failure here. The '01' imod value is unprintable, so there's 2308 // nothing useful we could do even if we returned UNPREDICTABLE. 2309 2310 if (imod == 1) return MCDisassembler::Fail; 2311 2312 if (imod && M) { 2313 Inst.setOpcode(ARM::t2CPS3p); 2314 Inst.addOperand(MCOperand::createImm(imod)); 2315 Inst.addOperand(MCOperand::createImm(iflags)); 2316 Inst.addOperand(MCOperand::createImm(mode)); 2317 } else if (imod && !M) { 2318 Inst.setOpcode(ARM::t2CPS2p); 2319 Inst.addOperand(MCOperand::createImm(imod)); 2320 Inst.addOperand(MCOperand::createImm(iflags)); 2321 if (mode) S = MCDisassembler::SoftFail; 2322 } else if (!imod && M) { 2323 Inst.setOpcode(ARM::t2CPS1p); 2324 Inst.addOperand(MCOperand::createImm(mode)); 2325 if (iflags) S = MCDisassembler::SoftFail; 2326 } else { 2327 // imod == '00' && M == '0' --> this is a HINT instruction 2328 int imm = fieldFromInstruction(Insn, 0, 8); 2329 // HINT are defined only for immediate in [0..4] 2330 if(imm > 4) return MCDisassembler::Fail; 2331 Inst.setOpcode(ARM::t2HINT); 2332 Inst.addOperand(MCOperand::createImm(imm)); 2333 } 2334 2335 return S; 2336 } 2337 2338 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2339 uint64_t Address, const void *Decoder) { 2340 DecodeStatus S = MCDisassembler::Success; 2341 2342 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2343 unsigned imm = 0; 2344 2345 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2346 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2347 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2348 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2349 2350 if (Inst.getOpcode() == ARM::t2MOVTi16) 2351 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2352 return MCDisassembler::Fail; 2353 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2354 return MCDisassembler::Fail; 2355 2356 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2357 Inst.addOperand(MCOperand::createImm(imm)); 2358 2359 return S; 2360 } 2361 2362 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2363 uint64_t Address, const void *Decoder) { 2364 DecodeStatus S = MCDisassembler::Success; 2365 2366 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2367 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2368 unsigned imm = 0; 2369 2370 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2371 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2372 2373 if (Inst.getOpcode() == ARM::MOVTi16) 2374 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2375 return MCDisassembler::Fail; 2376 2377 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2378 return MCDisassembler::Fail; 2379 2380 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2381 Inst.addOperand(MCOperand::createImm(imm)); 2382 2383 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2384 return MCDisassembler::Fail; 2385 2386 return S; 2387 } 2388 2389 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2390 uint64_t Address, const void *Decoder) { 2391 DecodeStatus S = MCDisassembler::Success; 2392 2393 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2394 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2395 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2396 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2397 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2398 2399 if (pred == 0xF) 2400 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2401 2402 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2403 return MCDisassembler::Fail; 2404 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2405 return MCDisassembler::Fail; 2406 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2407 return MCDisassembler::Fail; 2408 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2409 return MCDisassembler::Fail; 2410 2411 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2412 return MCDisassembler::Fail; 2413 2414 return S; 2415 } 2416 2417 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2418 uint64_t Address, const void *Decoder) { 2419 DecodeStatus S = MCDisassembler::Success; 2420 2421 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2422 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2423 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2424 2425 if (Pred == 0xF) 2426 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2427 2428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2429 return MCDisassembler::Fail; 2430 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2431 return MCDisassembler::Fail; 2432 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2433 return MCDisassembler::Fail; 2434 2435 return S; 2436 } 2437 2438 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2439 uint64_t Address, const void *Decoder) { 2440 DecodeStatus S = MCDisassembler::Success; 2441 2442 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2443 2444 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2445 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2446 2447 if (!FeatureBits[ARM::HasV8_1aOps] || 2448 !FeatureBits[ARM::HasV8Ops]) 2449 return MCDisassembler::Fail; 2450 2451 // Decoder can be called from DecodeTST, which does not check the full 2452 // encoding is valid. 2453 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2454 fieldFromInstruction(Insn, 4,4) != 0) 2455 return MCDisassembler::Fail; 2456 if (fieldFromInstruction(Insn, 10,10) != 0 || 2457 fieldFromInstruction(Insn, 0,4) != 0) 2458 S = MCDisassembler::SoftFail; 2459 2460 Inst.setOpcode(ARM::SETPAN); 2461 Inst.addOperand(MCOperand::createImm(Imm)); 2462 2463 return S; 2464 } 2465 2466 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2467 uint64_t Address, const void *Decoder) { 2468 DecodeStatus S = MCDisassembler::Success; 2469 2470 unsigned add = fieldFromInstruction(Val, 12, 1); 2471 unsigned imm = fieldFromInstruction(Val, 0, 12); 2472 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2473 2474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2475 return MCDisassembler::Fail; 2476 2477 if (!add) imm *= -1; 2478 if (imm == 0 && !add) imm = INT32_MIN; 2479 Inst.addOperand(MCOperand::createImm(imm)); 2480 if (Rn == 15) 2481 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2482 2483 return S; 2484 } 2485 2486 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2487 uint64_t Address, const void *Decoder) { 2488 DecodeStatus S = MCDisassembler::Success; 2489 2490 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2491 // U == 1 to add imm, 0 to subtract it. 2492 unsigned U = fieldFromInstruction(Val, 8, 1); 2493 unsigned imm = fieldFromInstruction(Val, 0, 8); 2494 2495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2496 return MCDisassembler::Fail; 2497 2498 if (U) 2499 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2500 else 2501 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2502 2503 return S; 2504 } 2505 2506 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2507 uint64_t Address, const void *Decoder) { 2508 DecodeStatus S = MCDisassembler::Success; 2509 2510 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2511 // U == 1 to add imm, 0 to subtract it. 2512 unsigned U = fieldFromInstruction(Val, 8, 1); 2513 unsigned imm = fieldFromInstruction(Val, 0, 8); 2514 2515 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2516 return MCDisassembler::Fail; 2517 2518 if (U) 2519 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2520 else 2521 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2522 2523 return S; 2524 } 2525 2526 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2527 uint64_t Address, const void *Decoder) { 2528 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2529 } 2530 2531 static DecodeStatus 2532 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2533 uint64_t Address, const void *Decoder) { 2534 DecodeStatus Status = MCDisassembler::Success; 2535 2536 // Note the J1 and J2 values are from the encoded instruction. So here 2537 // change them to I1 and I2 values via as documented: 2538 // I1 = NOT(J1 EOR S); 2539 // I2 = NOT(J2 EOR S); 2540 // and build the imm32 with one trailing zero as documented: 2541 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2542 unsigned S = fieldFromInstruction(Insn, 26, 1); 2543 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2544 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2545 unsigned I1 = !(J1 ^ S); 2546 unsigned I2 = !(J2 ^ S); 2547 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2548 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2549 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2550 int imm32 = SignExtend32<25>(tmp << 1); 2551 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2552 true, 4, Inst, Decoder)) 2553 Inst.addOperand(MCOperand::createImm(imm32)); 2554 2555 return Status; 2556 } 2557 2558 static DecodeStatus 2559 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2560 uint64_t Address, const void *Decoder) { 2561 DecodeStatus S = MCDisassembler::Success; 2562 2563 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2564 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2565 2566 if (pred == 0xF) { 2567 Inst.setOpcode(ARM::BLXi); 2568 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2569 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2570 true, 4, Inst, Decoder)) 2571 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2572 return S; 2573 } 2574 2575 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2576 true, 4, Inst, Decoder)) 2577 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2578 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2579 return MCDisassembler::Fail; 2580 2581 return S; 2582 } 2583 2584 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2585 uint64_t Address, const void *Decoder) { 2586 DecodeStatus S = MCDisassembler::Success; 2587 2588 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2589 unsigned align = fieldFromInstruction(Val, 4, 2); 2590 2591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2592 return MCDisassembler::Fail; 2593 if (!align) 2594 Inst.addOperand(MCOperand::createImm(0)); 2595 else 2596 Inst.addOperand(MCOperand::createImm(4 << align)); 2597 2598 return S; 2599 } 2600 2601 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2602 uint64_t Address, const void *Decoder) { 2603 DecodeStatus S = MCDisassembler::Success; 2604 2605 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2606 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2607 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2608 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2609 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2610 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2611 2612 // First output register 2613 switch (Inst.getOpcode()) { 2614 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2615 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2616 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2617 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2618 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2619 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2620 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2621 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2622 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2623 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2624 return MCDisassembler::Fail; 2625 break; 2626 case ARM::VLD2b16: 2627 case ARM::VLD2b32: 2628 case ARM::VLD2b8: 2629 case ARM::VLD2b16wb_fixed: 2630 case ARM::VLD2b16wb_register: 2631 case ARM::VLD2b32wb_fixed: 2632 case ARM::VLD2b32wb_register: 2633 case ARM::VLD2b8wb_fixed: 2634 case ARM::VLD2b8wb_register: 2635 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2636 return MCDisassembler::Fail; 2637 break; 2638 default: 2639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2640 return MCDisassembler::Fail; 2641 } 2642 2643 // Second output register 2644 switch (Inst.getOpcode()) { 2645 case ARM::VLD3d8: 2646 case ARM::VLD3d16: 2647 case ARM::VLD3d32: 2648 case ARM::VLD3d8_UPD: 2649 case ARM::VLD3d16_UPD: 2650 case ARM::VLD3d32_UPD: 2651 case ARM::VLD4d8: 2652 case ARM::VLD4d16: 2653 case ARM::VLD4d32: 2654 case ARM::VLD4d8_UPD: 2655 case ARM::VLD4d16_UPD: 2656 case ARM::VLD4d32_UPD: 2657 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2658 return MCDisassembler::Fail; 2659 break; 2660 case ARM::VLD3q8: 2661 case ARM::VLD3q16: 2662 case ARM::VLD3q32: 2663 case ARM::VLD3q8_UPD: 2664 case ARM::VLD3q16_UPD: 2665 case ARM::VLD3q32_UPD: 2666 case ARM::VLD4q8: 2667 case ARM::VLD4q16: 2668 case ARM::VLD4q32: 2669 case ARM::VLD4q8_UPD: 2670 case ARM::VLD4q16_UPD: 2671 case ARM::VLD4q32_UPD: 2672 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2673 return MCDisassembler::Fail; 2674 break; 2675 default: 2676 break; 2677 } 2678 2679 // Third output register 2680 switch(Inst.getOpcode()) { 2681 case ARM::VLD3d8: 2682 case ARM::VLD3d16: 2683 case ARM::VLD3d32: 2684 case ARM::VLD3d8_UPD: 2685 case ARM::VLD3d16_UPD: 2686 case ARM::VLD3d32_UPD: 2687 case ARM::VLD4d8: 2688 case ARM::VLD4d16: 2689 case ARM::VLD4d32: 2690 case ARM::VLD4d8_UPD: 2691 case ARM::VLD4d16_UPD: 2692 case ARM::VLD4d32_UPD: 2693 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2694 return MCDisassembler::Fail; 2695 break; 2696 case ARM::VLD3q8: 2697 case ARM::VLD3q16: 2698 case ARM::VLD3q32: 2699 case ARM::VLD3q8_UPD: 2700 case ARM::VLD3q16_UPD: 2701 case ARM::VLD3q32_UPD: 2702 case ARM::VLD4q8: 2703 case ARM::VLD4q16: 2704 case ARM::VLD4q32: 2705 case ARM::VLD4q8_UPD: 2706 case ARM::VLD4q16_UPD: 2707 case ARM::VLD4q32_UPD: 2708 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2709 return MCDisassembler::Fail; 2710 break; 2711 default: 2712 break; 2713 } 2714 2715 // Fourth output register 2716 switch (Inst.getOpcode()) { 2717 case ARM::VLD4d8: 2718 case ARM::VLD4d16: 2719 case ARM::VLD4d32: 2720 case ARM::VLD4d8_UPD: 2721 case ARM::VLD4d16_UPD: 2722 case ARM::VLD4d32_UPD: 2723 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2724 return MCDisassembler::Fail; 2725 break; 2726 case ARM::VLD4q8: 2727 case ARM::VLD4q16: 2728 case ARM::VLD4q32: 2729 case ARM::VLD4q8_UPD: 2730 case ARM::VLD4q16_UPD: 2731 case ARM::VLD4q32_UPD: 2732 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2733 return MCDisassembler::Fail; 2734 break; 2735 default: 2736 break; 2737 } 2738 2739 // Writeback operand 2740 switch (Inst.getOpcode()) { 2741 case ARM::VLD1d8wb_fixed: 2742 case ARM::VLD1d16wb_fixed: 2743 case ARM::VLD1d32wb_fixed: 2744 case ARM::VLD1d64wb_fixed: 2745 case ARM::VLD1d8wb_register: 2746 case ARM::VLD1d16wb_register: 2747 case ARM::VLD1d32wb_register: 2748 case ARM::VLD1d64wb_register: 2749 case ARM::VLD1q8wb_fixed: 2750 case ARM::VLD1q16wb_fixed: 2751 case ARM::VLD1q32wb_fixed: 2752 case ARM::VLD1q64wb_fixed: 2753 case ARM::VLD1q8wb_register: 2754 case ARM::VLD1q16wb_register: 2755 case ARM::VLD1q32wb_register: 2756 case ARM::VLD1q64wb_register: 2757 case ARM::VLD1d8Twb_fixed: 2758 case ARM::VLD1d8Twb_register: 2759 case ARM::VLD1d16Twb_fixed: 2760 case ARM::VLD1d16Twb_register: 2761 case ARM::VLD1d32Twb_fixed: 2762 case ARM::VLD1d32Twb_register: 2763 case ARM::VLD1d64Twb_fixed: 2764 case ARM::VLD1d64Twb_register: 2765 case ARM::VLD1d8Qwb_fixed: 2766 case ARM::VLD1d8Qwb_register: 2767 case ARM::VLD1d16Qwb_fixed: 2768 case ARM::VLD1d16Qwb_register: 2769 case ARM::VLD1d32Qwb_fixed: 2770 case ARM::VLD1d32Qwb_register: 2771 case ARM::VLD1d64Qwb_fixed: 2772 case ARM::VLD1d64Qwb_register: 2773 case ARM::VLD2d8wb_fixed: 2774 case ARM::VLD2d16wb_fixed: 2775 case ARM::VLD2d32wb_fixed: 2776 case ARM::VLD2q8wb_fixed: 2777 case ARM::VLD2q16wb_fixed: 2778 case ARM::VLD2q32wb_fixed: 2779 case ARM::VLD2d8wb_register: 2780 case ARM::VLD2d16wb_register: 2781 case ARM::VLD2d32wb_register: 2782 case ARM::VLD2q8wb_register: 2783 case ARM::VLD2q16wb_register: 2784 case ARM::VLD2q32wb_register: 2785 case ARM::VLD2b8wb_fixed: 2786 case ARM::VLD2b16wb_fixed: 2787 case ARM::VLD2b32wb_fixed: 2788 case ARM::VLD2b8wb_register: 2789 case ARM::VLD2b16wb_register: 2790 case ARM::VLD2b32wb_register: 2791 Inst.addOperand(MCOperand::createImm(0)); 2792 break; 2793 case ARM::VLD3d8_UPD: 2794 case ARM::VLD3d16_UPD: 2795 case ARM::VLD3d32_UPD: 2796 case ARM::VLD3q8_UPD: 2797 case ARM::VLD3q16_UPD: 2798 case ARM::VLD3q32_UPD: 2799 case ARM::VLD4d8_UPD: 2800 case ARM::VLD4d16_UPD: 2801 case ARM::VLD4d32_UPD: 2802 case ARM::VLD4q8_UPD: 2803 case ARM::VLD4q16_UPD: 2804 case ARM::VLD4q32_UPD: 2805 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2806 return MCDisassembler::Fail; 2807 break; 2808 default: 2809 break; 2810 } 2811 2812 // AddrMode6 Base (register+alignment) 2813 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2814 return MCDisassembler::Fail; 2815 2816 // AddrMode6 Offset (register) 2817 switch (Inst.getOpcode()) { 2818 default: 2819 // The below have been updated to have explicit am6offset split 2820 // between fixed and register offset. For those instructions not 2821 // yet updated, we need to add an additional reg0 operand for the 2822 // fixed variant. 2823 // 2824 // The fixed offset encodes as Rm == 0xd, so we check for that. 2825 if (Rm == 0xd) { 2826 Inst.addOperand(MCOperand::createReg(0)); 2827 break; 2828 } 2829 // Fall through to handle the register offset variant. 2830 LLVM_FALLTHROUGH; 2831 case ARM::VLD1d8wb_fixed: 2832 case ARM::VLD1d16wb_fixed: 2833 case ARM::VLD1d32wb_fixed: 2834 case ARM::VLD1d64wb_fixed: 2835 case ARM::VLD1d8Twb_fixed: 2836 case ARM::VLD1d16Twb_fixed: 2837 case ARM::VLD1d32Twb_fixed: 2838 case ARM::VLD1d64Twb_fixed: 2839 case ARM::VLD1d8Qwb_fixed: 2840 case ARM::VLD1d16Qwb_fixed: 2841 case ARM::VLD1d32Qwb_fixed: 2842 case ARM::VLD1d64Qwb_fixed: 2843 case ARM::VLD1d8wb_register: 2844 case ARM::VLD1d16wb_register: 2845 case ARM::VLD1d32wb_register: 2846 case ARM::VLD1d64wb_register: 2847 case ARM::VLD1q8wb_fixed: 2848 case ARM::VLD1q16wb_fixed: 2849 case ARM::VLD1q32wb_fixed: 2850 case ARM::VLD1q64wb_fixed: 2851 case ARM::VLD1q8wb_register: 2852 case ARM::VLD1q16wb_register: 2853 case ARM::VLD1q32wb_register: 2854 case ARM::VLD1q64wb_register: 2855 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2856 // variant encodes Rm == 0xf. Anything else is a register offset post- 2857 // increment and we need to add the register operand to the instruction. 2858 if (Rm != 0xD && Rm != 0xF && 2859 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2860 return MCDisassembler::Fail; 2861 break; 2862 case ARM::VLD2d8wb_fixed: 2863 case ARM::VLD2d16wb_fixed: 2864 case ARM::VLD2d32wb_fixed: 2865 case ARM::VLD2b8wb_fixed: 2866 case ARM::VLD2b16wb_fixed: 2867 case ARM::VLD2b32wb_fixed: 2868 case ARM::VLD2q8wb_fixed: 2869 case ARM::VLD2q16wb_fixed: 2870 case ARM::VLD2q32wb_fixed: 2871 break; 2872 } 2873 2874 return S; 2875 } 2876 2877 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2878 uint64_t Address, const void *Decoder) { 2879 unsigned type = fieldFromInstruction(Insn, 8, 4); 2880 unsigned align = fieldFromInstruction(Insn, 4, 2); 2881 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2882 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2883 if (type == 10 && align == 3) return MCDisassembler::Fail; 2884 2885 unsigned load = fieldFromInstruction(Insn, 21, 1); 2886 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2887 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2888 } 2889 2890 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2891 uint64_t Address, const void *Decoder) { 2892 unsigned size = fieldFromInstruction(Insn, 6, 2); 2893 if (size == 3) return MCDisassembler::Fail; 2894 2895 unsigned type = fieldFromInstruction(Insn, 8, 4); 2896 unsigned align = fieldFromInstruction(Insn, 4, 2); 2897 if (type == 8 && align == 3) return MCDisassembler::Fail; 2898 if (type == 9 && align == 3) return MCDisassembler::Fail; 2899 2900 unsigned load = fieldFromInstruction(Insn, 21, 1); 2901 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2902 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2903 } 2904 2905 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2906 uint64_t Address, const void *Decoder) { 2907 unsigned size = fieldFromInstruction(Insn, 6, 2); 2908 if (size == 3) return MCDisassembler::Fail; 2909 2910 unsigned align = fieldFromInstruction(Insn, 4, 2); 2911 if (align & 2) return MCDisassembler::Fail; 2912 2913 unsigned load = fieldFromInstruction(Insn, 21, 1); 2914 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2915 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2916 } 2917 2918 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2919 uint64_t Address, const void *Decoder) { 2920 unsigned size = fieldFromInstruction(Insn, 6, 2); 2921 if (size == 3) return MCDisassembler::Fail; 2922 2923 unsigned load = fieldFromInstruction(Insn, 21, 1); 2924 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2925 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2926 } 2927 2928 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2929 uint64_t Address, const void *Decoder) { 2930 DecodeStatus S = MCDisassembler::Success; 2931 2932 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2933 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2934 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2935 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2936 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2937 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2938 2939 // Writeback Operand 2940 switch (Inst.getOpcode()) { 2941 case ARM::VST1d8wb_fixed: 2942 case ARM::VST1d16wb_fixed: 2943 case ARM::VST1d32wb_fixed: 2944 case ARM::VST1d64wb_fixed: 2945 case ARM::VST1d8wb_register: 2946 case ARM::VST1d16wb_register: 2947 case ARM::VST1d32wb_register: 2948 case ARM::VST1d64wb_register: 2949 case ARM::VST1q8wb_fixed: 2950 case ARM::VST1q16wb_fixed: 2951 case ARM::VST1q32wb_fixed: 2952 case ARM::VST1q64wb_fixed: 2953 case ARM::VST1q8wb_register: 2954 case ARM::VST1q16wb_register: 2955 case ARM::VST1q32wb_register: 2956 case ARM::VST1q64wb_register: 2957 case ARM::VST1d8Twb_fixed: 2958 case ARM::VST1d16Twb_fixed: 2959 case ARM::VST1d32Twb_fixed: 2960 case ARM::VST1d64Twb_fixed: 2961 case ARM::VST1d8Twb_register: 2962 case ARM::VST1d16Twb_register: 2963 case ARM::VST1d32Twb_register: 2964 case ARM::VST1d64Twb_register: 2965 case ARM::VST1d8Qwb_fixed: 2966 case ARM::VST1d16Qwb_fixed: 2967 case ARM::VST1d32Qwb_fixed: 2968 case ARM::VST1d64Qwb_fixed: 2969 case ARM::VST1d8Qwb_register: 2970 case ARM::VST1d16Qwb_register: 2971 case ARM::VST1d32Qwb_register: 2972 case ARM::VST1d64Qwb_register: 2973 case ARM::VST2d8wb_fixed: 2974 case ARM::VST2d16wb_fixed: 2975 case ARM::VST2d32wb_fixed: 2976 case ARM::VST2d8wb_register: 2977 case ARM::VST2d16wb_register: 2978 case ARM::VST2d32wb_register: 2979 case ARM::VST2q8wb_fixed: 2980 case ARM::VST2q16wb_fixed: 2981 case ARM::VST2q32wb_fixed: 2982 case ARM::VST2q8wb_register: 2983 case ARM::VST2q16wb_register: 2984 case ARM::VST2q32wb_register: 2985 case ARM::VST2b8wb_fixed: 2986 case ARM::VST2b16wb_fixed: 2987 case ARM::VST2b32wb_fixed: 2988 case ARM::VST2b8wb_register: 2989 case ARM::VST2b16wb_register: 2990 case ARM::VST2b32wb_register: 2991 if (Rm == 0xF) 2992 return MCDisassembler::Fail; 2993 Inst.addOperand(MCOperand::createImm(0)); 2994 break; 2995 case ARM::VST3d8_UPD: 2996 case ARM::VST3d16_UPD: 2997 case ARM::VST3d32_UPD: 2998 case ARM::VST3q8_UPD: 2999 case ARM::VST3q16_UPD: 3000 case ARM::VST3q32_UPD: 3001 case ARM::VST4d8_UPD: 3002 case ARM::VST4d16_UPD: 3003 case ARM::VST4d32_UPD: 3004 case ARM::VST4q8_UPD: 3005 case ARM::VST4q16_UPD: 3006 case ARM::VST4q32_UPD: 3007 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3008 return MCDisassembler::Fail; 3009 break; 3010 default: 3011 break; 3012 } 3013 3014 // AddrMode6 Base (register+alignment) 3015 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3016 return MCDisassembler::Fail; 3017 3018 // AddrMode6 Offset (register) 3019 switch (Inst.getOpcode()) { 3020 default: 3021 if (Rm == 0xD) 3022 Inst.addOperand(MCOperand::createReg(0)); 3023 else if (Rm != 0xF) { 3024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3025 return MCDisassembler::Fail; 3026 } 3027 break; 3028 case ARM::VST1d8wb_fixed: 3029 case ARM::VST1d16wb_fixed: 3030 case ARM::VST1d32wb_fixed: 3031 case ARM::VST1d64wb_fixed: 3032 case ARM::VST1q8wb_fixed: 3033 case ARM::VST1q16wb_fixed: 3034 case ARM::VST1q32wb_fixed: 3035 case ARM::VST1q64wb_fixed: 3036 case ARM::VST1d8Twb_fixed: 3037 case ARM::VST1d16Twb_fixed: 3038 case ARM::VST1d32Twb_fixed: 3039 case ARM::VST1d64Twb_fixed: 3040 case ARM::VST1d8Qwb_fixed: 3041 case ARM::VST1d16Qwb_fixed: 3042 case ARM::VST1d32Qwb_fixed: 3043 case ARM::VST1d64Qwb_fixed: 3044 case ARM::VST2d8wb_fixed: 3045 case ARM::VST2d16wb_fixed: 3046 case ARM::VST2d32wb_fixed: 3047 case ARM::VST2q8wb_fixed: 3048 case ARM::VST2q16wb_fixed: 3049 case ARM::VST2q32wb_fixed: 3050 case ARM::VST2b8wb_fixed: 3051 case ARM::VST2b16wb_fixed: 3052 case ARM::VST2b32wb_fixed: 3053 break; 3054 } 3055 3056 // First input register 3057 switch (Inst.getOpcode()) { 3058 case ARM::VST1q16: 3059 case ARM::VST1q32: 3060 case ARM::VST1q64: 3061 case ARM::VST1q8: 3062 case ARM::VST1q16wb_fixed: 3063 case ARM::VST1q16wb_register: 3064 case ARM::VST1q32wb_fixed: 3065 case ARM::VST1q32wb_register: 3066 case ARM::VST1q64wb_fixed: 3067 case ARM::VST1q64wb_register: 3068 case ARM::VST1q8wb_fixed: 3069 case ARM::VST1q8wb_register: 3070 case ARM::VST2d16: 3071 case ARM::VST2d32: 3072 case ARM::VST2d8: 3073 case ARM::VST2d16wb_fixed: 3074 case ARM::VST2d16wb_register: 3075 case ARM::VST2d32wb_fixed: 3076 case ARM::VST2d32wb_register: 3077 case ARM::VST2d8wb_fixed: 3078 case ARM::VST2d8wb_register: 3079 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3080 return MCDisassembler::Fail; 3081 break; 3082 case ARM::VST2b16: 3083 case ARM::VST2b32: 3084 case ARM::VST2b8: 3085 case ARM::VST2b16wb_fixed: 3086 case ARM::VST2b16wb_register: 3087 case ARM::VST2b32wb_fixed: 3088 case ARM::VST2b32wb_register: 3089 case ARM::VST2b8wb_fixed: 3090 case ARM::VST2b8wb_register: 3091 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3092 return MCDisassembler::Fail; 3093 break; 3094 default: 3095 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3096 return MCDisassembler::Fail; 3097 } 3098 3099 // Second input register 3100 switch (Inst.getOpcode()) { 3101 case ARM::VST3d8: 3102 case ARM::VST3d16: 3103 case ARM::VST3d32: 3104 case ARM::VST3d8_UPD: 3105 case ARM::VST3d16_UPD: 3106 case ARM::VST3d32_UPD: 3107 case ARM::VST4d8: 3108 case ARM::VST4d16: 3109 case ARM::VST4d32: 3110 case ARM::VST4d8_UPD: 3111 case ARM::VST4d16_UPD: 3112 case ARM::VST4d32_UPD: 3113 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3114 return MCDisassembler::Fail; 3115 break; 3116 case ARM::VST3q8: 3117 case ARM::VST3q16: 3118 case ARM::VST3q32: 3119 case ARM::VST3q8_UPD: 3120 case ARM::VST3q16_UPD: 3121 case ARM::VST3q32_UPD: 3122 case ARM::VST4q8: 3123 case ARM::VST4q16: 3124 case ARM::VST4q32: 3125 case ARM::VST4q8_UPD: 3126 case ARM::VST4q16_UPD: 3127 case ARM::VST4q32_UPD: 3128 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3129 return MCDisassembler::Fail; 3130 break; 3131 default: 3132 break; 3133 } 3134 3135 // Third input register 3136 switch (Inst.getOpcode()) { 3137 case ARM::VST3d8: 3138 case ARM::VST3d16: 3139 case ARM::VST3d32: 3140 case ARM::VST3d8_UPD: 3141 case ARM::VST3d16_UPD: 3142 case ARM::VST3d32_UPD: 3143 case ARM::VST4d8: 3144 case ARM::VST4d16: 3145 case ARM::VST4d32: 3146 case ARM::VST4d8_UPD: 3147 case ARM::VST4d16_UPD: 3148 case ARM::VST4d32_UPD: 3149 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3150 return MCDisassembler::Fail; 3151 break; 3152 case ARM::VST3q8: 3153 case ARM::VST3q16: 3154 case ARM::VST3q32: 3155 case ARM::VST3q8_UPD: 3156 case ARM::VST3q16_UPD: 3157 case ARM::VST3q32_UPD: 3158 case ARM::VST4q8: 3159 case ARM::VST4q16: 3160 case ARM::VST4q32: 3161 case ARM::VST4q8_UPD: 3162 case ARM::VST4q16_UPD: 3163 case ARM::VST4q32_UPD: 3164 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3165 return MCDisassembler::Fail; 3166 break; 3167 default: 3168 break; 3169 } 3170 3171 // Fourth input register 3172 switch (Inst.getOpcode()) { 3173 case ARM::VST4d8: 3174 case ARM::VST4d16: 3175 case ARM::VST4d32: 3176 case ARM::VST4d8_UPD: 3177 case ARM::VST4d16_UPD: 3178 case ARM::VST4d32_UPD: 3179 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3180 return MCDisassembler::Fail; 3181 break; 3182 case ARM::VST4q8: 3183 case ARM::VST4q16: 3184 case ARM::VST4q32: 3185 case ARM::VST4q8_UPD: 3186 case ARM::VST4q16_UPD: 3187 case ARM::VST4q32_UPD: 3188 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3189 return MCDisassembler::Fail; 3190 break; 3191 default: 3192 break; 3193 } 3194 3195 return S; 3196 } 3197 3198 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3199 uint64_t Address, const void *Decoder) { 3200 DecodeStatus S = MCDisassembler::Success; 3201 3202 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3203 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3204 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3205 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3206 unsigned align = fieldFromInstruction(Insn, 4, 1); 3207 unsigned size = fieldFromInstruction(Insn, 6, 2); 3208 3209 if (size == 0 && align == 1) 3210 return MCDisassembler::Fail; 3211 align *= (1 << size); 3212 3213 switch (Inst.getOpcode()) { 3214 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3215 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3216 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3217 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3218 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3219 return MCDisassembler::Fail; 3220 break; 3221 default: 3222 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3223 return MCDisassembler::Fail; 3224 break; 3225 } 3226 if (Rm != 0xF) { 3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3228 return MCDisassembler::Fail; 3229 } 3230 3231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3232 return MCDisassembler::Fail; 3233 Inst.addOperand(MCOperand::createImm(align)); 3234 3235 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3236 // variant encodes Rm == 0xf. Anything else is a register offset post- 3237 // increment and we need to add the register operand to the instruction. 3238 if (Rm != 0xD && Rm != 0xF && 3239 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3240 return MCDisassembler::Fail; 3241 3242 return S; 3243 } 3244 3245 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3246 uint64_t Address, const void *Decoder) { 3247 DecodeStatus S = MCDisassembler::Success; 3248 3249 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3250 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3251 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3252 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3253 unsigned align = fieldFromInstruction(Insn, 4, 1); 3254 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3255 align *= 2*size; 3256 3257 switch (Inst.getOpcode()) { 3258 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3259 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3260 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3261 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3262 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3263 return MCDisassembler::Fail; 3264 break; 3265 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3266 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3267 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3268 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3269 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3270 return MCDisassembler::Fail; 3271 break; 3272 default: 3273 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3274 return MCDisassembler::Fail; 3275 break; 3276 } 3277 3278 if (Rm != 0xF) 3279 Inst.addOperand(MCOperand::createImm(0)); 3280 3281 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3282 return MCDisassembler::Fail; 3283 Inst.addOperand(MCOperand::createImm(align)); 3284 3285 if (Rm != 0xD && Rm != 0xF) { 3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3287 return MCDisassembler::Fail; 3288 } 3289 3290 return S; 3291 } 3292 3293 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3294 uint64_t Address, const void *Decoder) { 3295 DecodeStatus S = MCDisassembler::Success; 3296 3297 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3298 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3299 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3300 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3301 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3302 3303 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3304 return MCDisassembler::Fail; 3305 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3306 return MCDisassembler::Fail; 3307 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3308 return MCDisassembler::Fail; 3309 if (Rm != 0xF) { 3310 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3311 return MCDisassembler::Fail; 3312 } 3313 3314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3315 return MCDisassembler::Fail; 3316 Inst.addOperand(MCOperand::createImm(0)); 3317 3318 if (Rm == 0xD) 3319 Inst.addOperand(MCOperand::createReg(0)); 3320 else if (Rm != 0xF) { 3321 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3322 return MCDisassembler::Fail; 3323 } 3324 3325 return S; 3326 } 3327 3328 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3329 uint64_t Address, const void *Decoder) { 3330 DecodeStatus S = MCDisassembler::Success; 3331 3332 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3333 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3334 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3335 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3336 unsigned size = fieldFromInstruction(Insn, 6, 2); 3337 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3338 unsigned align = fieldFromInstruction(Insn, 4, 1); 3339 3340 if (size == 0x3) { 3341 if (align == 0) 3342 return MCDisassembler::Fail; 3343 align = 16; 3344 } else { 3345 if (size == 2) { 3346 align *= 8; 3347 } else { 3348 size = 1 << size; 3349 align *= 4*size; 3350 } 3351 } 3352 3353 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3354 return MCDisassembler::Fail; 3355 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3356 return MCDisassembler::Fail; 3357 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3358 return MCDisassembler::Fail; 3359 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3360 return MCDisassembler::Fail; 3361 if (Rm != 0xF) { 3362 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3363 return MCDisassembler::Fail; 3364 } 3365 3366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3367 return MCDisassembler::Fail; 3368 Inst.addOperand(MCOperand::createImm(align)); 3369 3370 if (Rm == 0xD) 3371 Inst.addOperand(MCOperand::createReg(0)); 3372 else if (Rm != 0xF) { 3373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3374 return MCDisassembler::Fail; 3375 } 3376 3377 return S; 3378 } 3379 3380 static DecodeStatus 3381 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3382 uint64_t Address, const void *Decoder) { 3383 DecodeStatus S = MCDisassembler::Success; 3384 3385 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3386 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3387 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3388 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3389 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3390 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3391 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3392 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3393 3394 if (Q) { 3395 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3396 return MCDisassembler::Fail; 3397 } else { 3398 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3399 return MCDisassembler::Fail; 3400 } 3401 3402 Inst.addOperand(MCOperand::createImm(imm)); 3403 3404 switch (Inst.getOpcode()) { 3405 case ARM::VORRiv4i16: 3406 case ARM::VORRiv2i32: 3407 case ARM::VBICiv4i16: 3408 case ARM::VBICiv2i32: 3409 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3410 return MCDisassembler::Fail; 3411 break; 3412 case ARM::VORRiv8i16: 3413 case ARM::VORRiv4i32: 3414 case ARM::VBICiv8i16: 3415 case ARM::VBICiv4i32: 3416 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3417 return MCDisassembler::Fail; 3418 break; 3419 default: 3420 break; 3421 } 3422 3423 return S; 3424 } 3425 3426 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3427 uint64_t Address, const void *Decoder) { 3428 DecodeStatus S = MCDisassembler::Success; 3429 3430 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3431 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3432 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3433 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3434 unsigned size = fieldFromInstruction(Insn, 18, 2); 3435 3436 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3437 return MCDisassembler::Fail; 3438 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3439 return MCDisassembler::Fail; 3440 Inst.addOperand(MCOperand::createImm(8 << size)); 3441 3442 return S; 3443 } 3444 3445 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3446 uint64_t Address, const void *Decoder) { 3447 Inst.addOperand(MCOperand::createImm(8 - Val)); 3448 return MCDisassembler::Success; 3449 } 3450 3451 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3452 uint64_t Address, const void *Decoder) { 3453 Inst.addOperand(MCOperand::createImm(16 - Val)); 3454 return MCDisassembler::Success; 3455 } 3456 3457 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3458 uint64_t Address, const void *Decoder) { 3459 Inst.addOperand(MCOperand::createImm(32 - Val)); 3460 return MCDisassembler::Success; 3461 } 3462 3463 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3464 uint64_t Address, const void *Decoder) { 3465 Inst.addOperand(MCOperand::createImm(64 - Val)); 3466 return MCDisassembler::Success; 3467 } 3468 3469 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3470 uint64_t Address, const void *Decoder) { 3471 DecodeStatus S = MCDisassembler::Success; 3472 3473 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3474 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3475 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3476 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3477 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3478 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3479 unsigned op = fieldFromInstruction(Insn, 6, 1); 3480 3481 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3482 return MCDisassembler::Fail; 3483 if (op) { 3484 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3485 return MCDisassembler::Fail; // Writeback 3486 } 3487 3488 switch (Inst.getOpcode()) { 3489 case ARM::VTBL2: 3490 case ARM::VTBX2: 3491 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3492 return MCDisassembler::Fail; 3493 break; 3494 default: 3495 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3496 return MCDisassembler::Fail; 3497 } 3498 3499 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 3502 return S; 3503 } 3504 3505 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3506 uint64_t Address, const void *Decoder) { 3507 DecodeStatus S = MCDisassembler::Success; 3508 3509 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3510 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3511 3512 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3513 return MCDisassembler::Fail; 3514 3515 switch(Inst.getOpcode()) { 3516 default: 3517 return MCDisassembler::Fail; 3518 case ARM::tADR: 3519 break; // tADR does not explicitly represent the PC as an operand. 3520 case ARM::tADDrSPi: 3521 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3522 break; 3523 } 3524 3525 Inst.addOperand(MCOperand::createImm(imm)); 3526 return S; 3527 } 3528 3529 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3530 uint64_t Address, const void *Decoder) { 3531 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3532 true, 2, Inst, Decoder)) 3533 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3534 return MCDisassembler::Success; 3535 } 3536 3537 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3538 uint64_t Address, const void *Decoder) { 3539 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3540 true, 4, Inst, Decoder)) 3541 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3542 return MCDisassembler::Success; 3543 } 3544 3545 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3546 uint64_t Address, const void *Decoder) { 3547 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3548 true, 2, Inst, Decoder)) 3549 Inst.addOperand(MCOperand::createImm(Val << 1)); 3550 return MCDisassembler::Success; 3551 } 3552 3553 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3554 uint64_t Address, const void *Decoder) { 3555 DecodeStatus S = MCDisassembler::Success; 3556 3557 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3558 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3559 3560 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3561 return MCDisassembler::Fail; 3562 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 3565 return S; 3566 } 3567 3568 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3569 uint64_t Address, const void *Decoder) { 3570 DecodeStatus S = MCDisassembler::Success; 3571 3572 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3573 unsigned imm = fieldFromInstruction(Val, 3, 5); 3574 3575 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3576 return MCDisassembler::Fail; 3577 Inst.addOperand(MCOperand::createImm(imm)); 3578 3579 return S; 3580 } 3581 3582 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3583 uint64_t Address, const void *Decoder) { 3584 unsigned imm = Val << 2; 3585 3586 Inst.addOperand(MCOperand::createImm(imm)); 3587 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3588 3589 return MCDisassembler::Success; 3590 } 3591 3592 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3593 uint64_t Address, const void *Decoder) { 3594 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3595 Inst.addOperand(MCOperand::createImm(Val)); 3596 3597 return MCDisassembler::Success; 3598 } 3599 3600 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3601 uint64_t Address, const void *Decoder) { 3602 DecodeStatus S = MCDisassembler::Success; 3603 3604 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3605 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3606 unsigned imm = fieldFromInstruction(Val, 0, 2); 3607 3608 // Thumb stores cannot use PC as dest register. 3609 switch (Inst.getOpcode()) { 3610 case ARM::t2STRHs: 3611 case ARM::t2STRBs: 3612 case ARM::t2STRs: 3613 if (Rn == 15) 3614 return MCDisassembler::Fail; 3615 break; 3616 default: 3617 break; 3618 } 3619 3620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3621 return MCDisassembler::Fail; 3622 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3623 return MCDisassembler::Fail; 3624 Inst.addOperand(MCOperand::createImm(imm)); 3625 3626 return S; 3627 } 3628 3629 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3630 uint64_t Address, const void *Decoder) { 3631 DecodeStatus S = MCDisassembler::Success; 3632 3633 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3634 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3635 3636 const FeatureBitset &featureBits = 3637 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3638 3639 bool hasMP = featureBits[ARM::FeatureMP]; 3640 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3641 3642 if (Rn == 15) { 3643 switch (Inst.getOpcode()) { 3644 case ARM::t2LDRBs: 3645 Inst.setOpcode(ARM::t2LDRBpci); 3646 break; 3647 case ARM::t2LDRHs: 3648 Inst.setOpcode(ARM::t2LDRHpci); 3649 break; 3650 case ARM::t2LDRSHs: 3651 Inst.setOpcode(ARM::t2LDRSHpci); 3652 break; 3653 case ARM::t2LDRSBs: 3654 Inst.setOpcode(ARM::t2LDRSBpci); 3655 break; 3656 case ARM::t2LDRs: 3657 Inst.setOpcode(ARM::t2LDRpci); 3658 break; 3659 case ARM::t2PLDs: 3660 Inst.setOpcode(ARM::t2PLDpci); 3661 break; 3662 case ARM::t2PLIs: 3663 Inst.setOpcode(ARM::t2PLIpci); 3664 break; 3665 default: 3666 return MCDisassembler::Fail; 3667 } 3668 3669 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3670 } 3671 3672 if (Rt == 15) { 3673 switch (Inst.getOpcode()) { 3674 case ARM::t2LDRSHs: 3675 return MCDisassembler::Fail; 3676 case ARM::t2LDRHs: 3677 Inst.setOpcode(ARM::t2PLDWs); 3678 break; 3679 case ARM::t2LDRSBs: 3680 Inst.setOpcode(ARM::t2PLIs); 3681 break; 3682 default: 3683 break; 3684 } 3685 } 3686 3687 switch (Inst.getOpcode()) { 3688 case ARM::t2PLDs: 3689 break; 3690 case ARM::t2PLIs: 3691 if (!hasV7Ops) 3692 return MCDisassembler::Fail; 3693 break; 3694 case ARM::t2PLDWs: 3695 if (!hasV7Ops || !hasMP) 3696 return MCDisassembler::Fail; 3697 break; 3698 default: 3699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3700 return MCDisassembler::Fail; 3701 } 3702 3703 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3704 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3705 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3706 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3707 return MCDisassembler::Fail; 3708 3709 return S; 3710 } 3711 3712 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3713 uint64_t Address, const void* Decoder) { 3714 DecodeStatus S = MCDisassembler::Success; 3715 3716 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3717 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3718 unsigned U = fieldFromInstruction(Insn, 9, 1); 3719 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3720 imm |= (U << 8); 3721 imm |= (Rn << 9); 3722 unsigned add = fieldFromInstruction(Insn, 9, 1); 3723 3724 const FeatureBitset &featureBits = 3725 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3726 3727 bool hasMP = featureBits[ARM::FeatureMP]; 3728 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3729 3730 if (Rn == 15) { 3731 switch (Inst.getOpcode()) { 3732 case ARM::t2LDRi8: 3733 Inst.setOpcode(ARM::t2LDRpci); 3734 break; 3735 case ARM::t2LDRBi8: 3736 Inst.setOpcode(ARM::t2LDRBpci); 3737 break; 3738 case ARM::t2LDRSBi8: 3739 Inst.setOpcode(ARM::t2LDRSBpci); 3740 break; 3741 case ARM::t2LDRHi8: 3742 Inst.setOpcode(ARM::t2LDRHpci); 3743 break; 3744 case ARM::t2LDRSHi8: 3745 Inst.setOpcode(ARM::t2LDRSHpci); 3746 break; 3747 case ARM::t2PLDi8: 3748 Inst.setOpcode(ARM::t2PLDpci); 3749 break; 3750 case ARM::t2PLIi8: 3751 Inst.setOpcode(ARM::t2PLIpci); 3752 break; 3753 default: 3754 return MCDisassembler::Fail; 3755 } 3756 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3757 } 3758 3759 if (Rt == 15) { 3760 switch (Inst.getOpcode()) { 3761 case ARM::t2LDRSHi8: 3762 return MCDisassembler::Fail; 3763 case ARM::t2LDRHi8: 3764 if (!add) 3765 Inst.setOpcode(ARM::t2PLDWi8); 3766 break; 3767 case ARM::t2LDRSBi8: 3768 Inst.setOpcode(ARM::t2PLIi8); 3769 break; 3770 default: 3771 break; 3772 } 3773 } 3774 3775 switch (Inst.getOpcode()) { 3776 case ARM::t2PLDi8: 3777 break; 3778 case ARM::t2PLIi8: 3779 if (!hasV7Ops) 3780 return MCDisassembler::Fail; 3781 break; 3782 case ARM::t2PLDWi8: 3783 if (!hasV7Ops || !hasMP) 3784 return MCDisassembler::Fail; 3785 break; 3786 default: 3787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3788 return MCDisassembler::Fail; 3789 } 3790 3791 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3792 return MCDisassembler::Fail; 3793 return S; 3794 } 3795 3796 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3797 uint64_t Address, const void* Decoder) { 3798 DecodeStatus S = MCDisassembler::Success; 3799 3800 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3801 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3802 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3803 imm |= (Rn << 13); 3804 3805 const FeatureBitset &featureBits = 3806 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3807 3808 bool hasMP = featureBits[ARM::FeatureMP]; 3809 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3810 3811 if (Rn == 15) { 3812 switch (Inst.getOpcode()) { 3813 case ARM::t2LDRi12: 3814 Inst.setOpcode(ARM::t2LDRpci); 3815 break; 3816 case ARM::t2LDRHi12: 3817 Inst.setOpcode(ARM::t2LDRHpci); 3818 break; 3819 case ARM::t2LDRSHi12: 3820 Inst.setOpcode(ARM::t2LDRSHpci); 3821 break; 3822 case ARM::t2LDRBi12: 3823 Inst.setOpcode(ARM::t2LDRBpci); 3824 break; 3825 case ARM::t2LDRSBi12: 3826 Inst.setOpcode(ARM::t2LDRSBpci); 3827 break; 3828 case ARM::t2PLDi12: 3829 Inst.setOpcode(ARM::t2PLDpci); 3830 break; 3831 case ARM::t2PLIi12: 3832 Inst.setOpcode(ARM::t2PLIpci); 3833 break; 3834 default: 3835 return MCDisassembler::Fail; 3836 } 3837 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3838 } 3839 3840 if (Rt == 15) { 3841 switch (Inst.getOpcode()) { 3842 case ARM::t2LDRSHi12: 3843 return MCDisassembler::Fail; 3844 case ARM::t2LDRHi12: 3845 Inst.setOpcode(ARM::t2PLDWi12); 3846 break; 3847 case ARM::t2LDRSBi12: 3848 Inst.setOpcode(ARM::t2PLIi12); 3849 break; 3850 default: 3851 break; 3852 } 3853 } 3854 3855 switch (Inst.getOpcode()) { 3856 case ARM::t2PLDi12: 3857 break; 3858 case ARM::t2PLIi12: 3859 if (!hasV7Ops) 3860 return MCDisassembler::Fail; 3861 break; 3862 case ARM::t2PLDWi12: 3863 if (!hasV7Ops || !hasMP) 3864 return MCDisassembler::Fail; 3865 break; 3866 default: 3867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3868 return MCDisassembler::Fail; 3869 } 3870 3871 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3872 return MCDisassembler::Fail; 3873 return S; 3874 } 3875 3876 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3877 uint64_t Address, const void* Decoder) { 3878 DecodeStatus S = MCDisassembler::Success; 3879 3880 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3881 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3882 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3883 imm |= (Rn << 9); 3884 3885 if (Rn == 15) { 3886 switch (Inst.getOpcode()) { 3887 case ARM::t2LDRT: 3888 Inst.setOpcode(ARM::t2LDRpci); 3889 break; 3890 case ARM::t2LDRBT: 3891 Inst.setOpcode(ARM::t2LDRBpci); 3892 break; 3893 case ARM::t2LDRHT: 3894 Inst.setOpcode(ARM::t2LDRHpci); 3895 break; 3896 case ARM::t2LDRSBT: 3897 Inst.setOpcode(ARM::t2LDRSBpci); 3898 break; 3899 case ARM::t2LDRSHT: 3900 Inst.setOpcode(ARM::t2LDRSHpci); 3901 break; 3902 default: 3903 return MCDisassembler::Fail; 3904 } 3905 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3906 } 3907 3908 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3909 return MCDisassembler::Fail; 3910 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3911 return MCDisassembler::Fail; 3912 return S; 3913 } 3914 3915 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3916 uint64_t Address, const void* Decoder) { 3917 DecodeStatus S = MCDisassembler::Success; 3918 3919 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3920 unsigned U = fieldFromInstruction(Insn, 23, 1); 3921 int imm = fieldFromInstruction(Insn, 0, 12); 3922 3923 const FeatureBitset &featureBits = 3924 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3925 3926 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3927 3928 if (Rt == 15) { 3929 switch (Inst.getOpcode()) { 3930 case ARM::t2LDRBpci: 3931 case ARM::t2LDRHpci: 3932 Inst.setOpcode(ARM::t2PLDpci); 3933 break; 3934 case ARM::t2LDRSBpci: 3935 Inst.setOpcode(ARM::t2PLIpci); 3936 break; 3937 case ARM::t2LDRSHpci: 3938 return MCDisassembler::Fail; 3939 default: 3940 break; 3941 } 3942 } 3943 3944 switch(Inst.getOpcode()) { 3945 case ARM::t2PLDpci: 3946 break; 3947 case ARM::t2PLIpci: 3948 if (!hasV7Ops) 3949 return MCDisassembler::Fail; 3950 break; 3951 default: 3952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3953 return MCDisassembler::Fail; 3954 } 3955 3956 if (!U) { 3957 // Special case for #-0. 3958 if (imm == 0) 3959 imm = INT32_MIN; 3960 else 3961 imm = -imm; 3962 } 3963 Inst.addOperand(MCOperand::createImm(imm)); 3964 3965 return S; 3966 } 3967 3968 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3969 uint64_t Address, const void *Decoder) { 3970 if (Val == 0) 3971 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3972 else { 3973 int imm = Val & 0xFF; 3974 3975 if (!(Val & 0x100)) imm *= -1; 3976 Inst.addOperand(MCOperand::createImm(imm * 4)); 3977 } 3978 3979 return MCDisassembler::Success; 3980 } 3981 3982 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 3983 const void *Decoder) { 3984 if (Val == 0) 3985 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 3986 else { 3987 int imm = Val & 0x7F; 3988 3989 if (!(Val & 0x80)) 3990 imm *= -1; 3991 Inst.addOperand(MCOperand::createImm(imm * 4)); 3992 } 3993 3994 return MCDisassembler::Success; 3995 } 3996 3997 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3998 uint64_t Address, const void *Decoder) { 3999 DecodeStatus S = MCDisassembler::Success; 4000 4001 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4002 unsigned imm = fieldFromInstruction(Val, 0, 9); 4003 4004 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4005 return MCDisassembler::Fail; 4006 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4007 return MCDisassembler::Fail; 4008 4009 return S; 4010 } 4011 4012 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4013 uint64_t Address, 4014 const void *Decoder) { 4015 DecodeStatus S = MCDisassembler::Success; 4016 4017 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4018 unsigned imm = fieldFromInstruction(Val, 0, 8); 4019 4020 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4021 return MCDisassembler::Fail; 4022 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 4025 return S; 4026 } 4027 4028 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4029 uint64_t Address, const void *Decoder) { 4030 DecodeStatus S = MCDisassembler::Success; 4031 4032 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4033 unsigned imm = fieldFromInstruction(Val, 0, 8); 4034 4035 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4036 return MCDisassembler::Fail; 4037 4038 Inst.addOperand(MCOperand::createImm(imm)); 4039 4040 return S; 4041 } 4042 4043 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4044 uint64_t Address, const void *Decoder) { 4045 int imm = Val & 0xFF; 4046 if (Val == 0) 4047 imm = INT32_MIN; 4048 else if (!(Val & 0x100)) 4049 imm *= -1; 4050 Inst.addOperand(MCOperand::createImm(imm)); 4051 4052 return MCDisassembler::Success; 4053 } 4054 4055 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4056 uint64_t Address, const void *Decoder) { 4057 DecodeStatus S = MCDisassembler::Success; 4058 4059 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4060 unsigned imm = fieldFromInstruction(Val, 0, 9); 4061 4062 // Thumb stores cannot use PC as dest register. 4063 switch (Inst.getOpcode()) { 4064 case ARM::t2STRT: 4065 case ARM::t2STRBT: 4066 case ARM::t2STRHT: 4067 case ARM::t2STRi8: 4068 case ARM::t2STRHi8: 4069 case ARM::t2STRBi8: 4070 if (Rn == 15) 4071 return MCDisassembler::Fail; 4072 break; 4073 default: 4074 break; 4075 } 4076 4077 // Some instructions always use an additive offset. 4078 switch (Inst.getOpcode()) { 4079 case ARM::t2LDRT: 4080 case ARM::t2LDRBT: 4081 case ARM::t2LDRHT: 4082 case ARM::t2LDRSBT: 4083 case ARM::t2LDRSHT: 4084 case ARM::t2STRT: 4085 case ARM::t2STRBT: 4086 case ARM::t2STRHT: 4087 imm |= 0x100; 4088 break; 4089 default: 4090 break; 4091 } 4092 4093 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4094 return MCDisassembler::Fail; 4095 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4096 return MCDisassembler::Fail; 4097 4098 return S; 4099 } 4100 4101 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4102 uint64_t Address, const void *Decoder) { 4103 DecodeStatus S = MCDisassembler::Success; 4104 4105 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4106 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4107 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4108 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4109 addr |= Rn << 9; 4110 unsigned load = fieldFromInstruction(Insn, 20, 1); 4111 4112 if (Rn == 15) { 4113 switch (Inst.getOpcode()) { 4114 case ARM::t2LDR_PRE: 4115 case ARM::t2LDR_POST: 4116 Inst.setOpcode(ARM::t2LDRpci); 4117 break; 4118 case ARM::t2LDRB_PRE: 4119 case ARM::t2LDRB_POST: 4120 Inst.setOpcode(ARM::t2LDRBpci); 4121 break; 4122 case ARM::t2LDRH_PRE: 4123 case ARM::t2LDRH_POST: 4124 Inst.setOpcode(ARM::t2LDRHpci); 4125 break; 4126 case ARM::t2LDRSB_PRE: 4127 case ARM::t2LDRSB_POST: 4128 if (Rt == 15) 4129 Inst.setOpcode(ARM::t2PLIpci); 4130 else 4131 Inst.setOpcode(ARM::t2LDRSBpci); 4132 break; 4133 case ARM::t2LDRSH_PRE: 4134 case ARM::t2LDRSH_POST: 4135 Inst.setOpcode(ARM::t2LDRSHpci); 4136 break; 4137 default: 4138 return MCDisassembler::Fail; 4139 } 4140 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4141 } 4142 4143 if (!load) { 4144 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4145 return MCDisassembler::Fail; 4146 } 4147 4148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4149 return MCDisassembler::Fail; 4150 4151 if (load) { 4152 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4153 return MCDisassembler::Fail; 4154 } 4155 4156 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4157 return MCDisassembler::Fail; 4158 4159 return S; 4160 } 4161 4162 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4163 uint64_t Address, const void *Decoder) { 4164 DecodeStatus S = MCDisassembler::Success; 4165 4166 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4167 unsigned imm = fieldFromInstruction(Val, 0, 12); 4168 4169 // Thumb stores cannot use PC as dest register. 4170 switch (Inst.getOpcode()) { 4171 case ARM::t2STRi12: 4172 case ARM::t2STRBi12: 4173 case ARM::t2STRHi12: 4174 if (Rn == 15) 4175 return MCDisassembler::Fail; 4176 break; 4177 default: 4178 break; 4179 } 4180 4181 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4182 return MCDisassembler::Fail; 4183 Inst.addOperand(MCOperand::createImm(imm)); 4184 4185 return S; 4186 } 4187 4188 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4189 uint64_t Address, const void *Decoder) { 4190 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4191 4192 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4193 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4194 Inst.addOperand(MCOperand::createImm(imm)); 4195 4196 return MCDisassembler::Success; 4197 } 4198 4199 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4200 uint64_t Address, const void *Decoder) { 4201 DecodeStatus S = MCDisassembler::Success; 4202 4203 if (Inst.getOpcode() == ARM::tADDrSP) { 4204 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4205 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4206 4207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4208 return MCDisassembler::Fail; 4209 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4211 return MCDisassembler::Fail; 4212 } else if (Inst.getOpcode() == ARM::tADDspr) { 4213 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4214 4215 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4216 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4218 return MCDisassembler::Fail; 4219 } 4220 4221 return S; 4222 } 4223 4224 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4225 uint64_t Address, const void *Decoder) { 4226 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4227 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4228 4229 Inst.addOperand(MCOperand::createImm(imod)); 4230 Inst.addOperand(MCOperand::createImm(flags)); 4231 4232 return MCDisassembler::Success; 4233 } 4234 4235 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4236 uint64_t Address, const void *Decoder) { 4237 DecodeStatus S = MCDisassembler::Success; 4238 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4239 unsigned add = fieldFromInstruction(Insn, 4, 1); 4240 4241 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4242 return MCDisassembler::Fail; 4243 Inst.addOperand(MCOperand::createImm(add)); 4244 4245 return S; 4246 } 4247 4248 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4249 uint64_t Address, const void *Decoder) { 4250 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4251 // Note only one trailing zero not two. Also the J1 and J2 values are from 4252 // the encoded instruction. So here change to I1 and I2 values via: 4253 // I1 = NOT(J1 EOR S); 4254 // I2 = NOT(J2 EOR S); 4255 // and build the imm32 with two trailing zeros as documented: 4256 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4257 unsigned S = (Val >> 23) & 1; 4258 unsigned J1 = (Val >> 22) & 1; 4259 unsigned J2 = (Val >> 21) & 1; 4260 unsigned I1 = !(J1 ^ S); 4261 unsigned I2 = !(J2 ^ S); 4262 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4263 int imm32 = SignExtend32<25>(tmp << 1); 4264 4265 if (!tryAddingSymbolicOperand(Address, 4266 (Address & ~2u) + imm32 + 4, 4267 true, 4, Inst, Decoder)) 4268 Inst.addOperand(MCOperand::createImm(imm32)); 4269 return MCDisassembler::Success; 4270 } 4271 4272 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4273 uint64_t Address, const void *Decoder) { 4274 if (Val == 0xA || Val == 0xB) 4275 return MCDisassembler::Fail; 4276 4277 const FeatureBitset &featureBits = 4278 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4279 4280 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) 4281 return MCDisassembler::Fail; 4282 4283 // For Armv8.1-M Mainline coprocessors matching 100x,101x or 111x should 4284 // decode as VFP/MVE instructions. 4285 if (featureBits[ARM::HasV8_1MMainlineOps] && 4286 ((Val & 0xE) == 0x8 || (Val & 0xE) == 0xA || 4287 (Val & 0xE) == 0xE)) 4288 return MCDisassembler::Fail; 4289 4290 Inst.addOperand(MCOperand::createImm(Val)); 4291 return MCDisassembler::Success; 4292 } 4293 4294 static DecodeStatus 4295 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4296 uint64_t Address, const void *Decoder) { 4297 DecodeStatus S = MCDisassembler::Success; 4298 4299 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4300 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4301 4302 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4303 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4304 return MCDisassembler::Fail; 4305 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4306 return MCDisassembler::Fail; 4307 return S; 4308 } 4309 4310 static DecodeStatus 4311 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4312 uint64_t Address, const void *Decoder) { 4313 DecodeStatus S = MCDisassembler::Success; 4314 4315 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4316 if (pred == 0xE || pred == 0xF) { 4317 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4318 switch (opc) { 4319 default: 4320 return MCDisassembler::Fail; 4321 case 0xf3bf8f4: 4322 Inst.setOpcode(ARM::t2DSB); 4323 break; 4324 case 0xf3bf8f5: 4325 Inst.setOpcode(ARM::t2DMB); 4326 break; 4327 case 0xf3bf8f6: 4328 Inst.setOpcode(ARM::t2ISB); 4329 break; 4330 } 4331 4332 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4333 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4334 } 4335 4336 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4337 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4338 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4339 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4340 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4341 4342 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4343 return MCDisassembler::Fail; 4344 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4345 return MCDisassembler::Fail; 4346 4347 return S; 4348 } 4349 4350 // Decode a shifted immediate operand. These basically consist 4351 // of an 8-bit value, and a 4-bit directive that specifies either 4352 // a splat operation or a rotation. 4353 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4354 uint64_t Address, const void *Decoder) { 4355 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4356 if (ctrl == 0) { 4357 unsigned byte = fieldFromInstruction(Val, 8, 2); 4358 unsigned imm = fieldFromInstruction(Val, 0, 8); 4359 switch (byte) { 4360 case 0: 4361 Inst.addOperand(MCOperand::createImm(imm)); 4362 break; 4363 case 1: 4364 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4365 break; 4366 case 2: 4367 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4368 break; 4369 case 3: 4370 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4371 (imm << 8) | imm)); 4372 break; 4373 } 4374 } else { 4375 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4376 unsigned rot = fieldFromInstruction(Val, 7, 5); 4377 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4378 Inst.addOperand(MCOperand::createImm(imm)); 4379 } 4380 4381 return MCDisassembler::Success; 4382 } 4383 4384 static DecodeStatus 4385 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4386 uint64_t Address, const void *Decoder) { 4387 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4388 true, 2, Inst, Decoder)) 4389 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4390 return MCDisassembler::Success; 4391 } 4392 4393 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4394 uint64_t Address, 4395 const void *Decoder) { 4396 // Val is passed in as S:J1:J2:imm10:imm11 4397 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4398 // the encoded instruction. So here change to I1 and I2 values via: 4399 // I1 = NOT(J1 EOR S); 4400 // I2 = NOT(J2 EOR S); 4401 // and build the imm32 with one trailing zero as documented: 4402 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4403 unsigned S = (Val >> 23) & 1; 4404 unsigned J1 = (Val >> 22) & 1; 4405 unsigned J2 = (Val >> 21) & 1; 4406 unsigned I1 = !(J1 ^ S); 4407 unsigned I2 = !(J2 ^ S); 4408 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4409 int imm32 = SignExtend32<25>(tmp << 1); 4410 4411 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4412 true, 4, Inst, Decoder)) 4413 Inst.addOperand(MCOperand::createImm(imm32)); 4414 return MCDisassembler::Success; 4415 } 4416 4417 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4418 uint64_t Address, const void *Decoder) { 4419 if (Val & ~0xf) 4420 return MCDisassembler::Fail; 4421 4422 Inst.addOperand(MCOperand::createImm(Val)); 4423 return MCDisassembler::Success; 4424 } 4425 4426 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4427 uint64_t Address, const void *Decoder) { 4428 if (Val & ~0xf) 4429 return MCDisassembler::Fail; 4430 4431 Inst.addOperand(MCOperand::createImm(Val)); 4432 return MCDisassembler::Success; 4433 } 4434 4435 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4436 uint64_t Address, const void *Decoder) { 4437 DecodeStatus S = MCDisassembler::Success; 4438 const FeatureBitset &FeatureBits = 4439 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4440 4441 if (FeatureBits[ARM::FeatureMClass]) { 4442 unsigned ValLow = Val & 0xff; 4443 4444 // Validate the SYSm value first. 4445 switch (ValLow) { 4446 case 0: // apsr 4447 case 1: // iapsr 4448 case 2: // eapsr 4449 case 3: // xpsr 4450 case 5: // ipsr 4451 case 6: // epsr 4452 case 7: // iepsr 4453 case 8: // msp 4454 case 9: // psp 4455 case 16: // primask 4456 case 20: // control 4457 break; 4458 case 17: // basepri 4459 case 18: // basepri_max 4460 case 19: // faultmask 4461 if (!(FeatureBits[ARM::HasV7Ops])) 4462 // Values basepri, basepri_max and faultmask are only valid for v7m. 4463 return MCDisassembler::Fail; 4464 break; 4465 case 0x8a: // msplim_ns 4466 case 0x8b: // psplim_ns 4467 case 0x91: // basepri_ns 4468 case 0x93: // faultmask_ns 4469 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4470 return MCDisassembler::Fail; 4471 LLVM_FALLTHROUGH; 4472 case 10: // msplim 4473 case 11: // psplim 4474 case 0x88: // msp_ns 4475 case 0x89: // psp_ns 4476 case 0x90: // primask_ns 4477 case 0x94: // control_ns 4478 case 0x98: // sp_ns 4479 if (!(FeatureBits[ARM::Feature8MSecExt])) 4480 return MCDisassembler::Fail; 4481 break; 4482 default: 4483 // Architecturally defined as unpredictable 4484 S = MCDisassembler::SoftFail; 4485 break; 4486 } 4487 4488 if (Inst.getOpcode() == ARM::t2MSR_M) { 4489 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4490 if (!(FeatureBits[ARM::HasV7Ops])) { 4491 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4492 // unpredictable. 4493 if (Mask != 2) 4494 S = MCDisassembler::SoftFail; 4495 } 4496 else { 4497 // The ARMv7-M architecture stores an additional 2-bit mask value in 4498 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4499 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4500 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4501 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4502 // only if the processor includes the DSP extension. 4503 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4504 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4505 S = MCDisassembler::SoftFail; 4506 } 4507 } 4508 } else { 4509 // A/R class 4510 if (Val == 0) 4511 return MCDisassembler::Fail; 4512 } 4513 Inst.addOperand(MCOperand::createImm(Val)); 4514 return S; 4515 } 4516 4517 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4518 uint64_t Address, const void *Decoder) { 4519 unsigned R = fieldFromInstruction(Val, 5, 1); 4520 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4521 4522 // The table of encodings for these banked registers comes from B9.2.3 of the 4523 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4524 // neater. So by fiat, these values are UNPREDICTABLE: 4525 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4526 return MCDisassembler::Fail; 4527 4528 Inst.addOperand(MCOperand::createImm(Val)); 4529 return MCDisassembler::Success; 4530 } 4531 4532 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4533 uint64_t Address, const void *Decoder) { 4534 DecodeStatus S = MCDisassembler::Success; 4535 4536 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4537 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4538 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4539 4540 if (Rn == 0xF) 4541 S = MCDisassembler::SoftFail; 4542 4543 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4544 return MCDisassembler::Fail; 4545 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4546 return MCDisassembler::Fail; 4547 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4548 return MCDisassembler::Fail; 4549 4550 return S; 4551 } 4552 4553 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4554 uint64_t Address, 4555 const void *Decoder) { 4556 DecodeStatus S = MCDisassembler::Success; 4557 4558 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4559 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4560 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4561 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4562 4563 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4564 return MCDisassembler::Fail; 4565 4566 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4567 S = MCDisassembler::SoftFail; 4568 4569 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4570 return MCDisassembler::Fail; 4571 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4572 return MCDisassembler::Fail; 4573 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4574 return MCDisassembler::Fail; 4575 4576 return S; 4577 } 4578 4579 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4580 uint64_t Address, const void *Decoder) { 4581 DecodeStatus S = MCDisassembler::Success; 4582 4583 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4584 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4585 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4586 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4587 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4588 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4589 4590 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4591 4592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4593 return MCDisassembler::Fail; 4594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4595 return MCDisassembler::Fail; 4596 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4597 return MCDisassembler::Fail; 4598 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4599 return MCDisassembler::Fail; 4600 4601 return S; 4602 } 4603 4604 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4605 uint64_t Address, const void *Decoder) { 4606 DecodeStatus S = MCDisassembler::Success; 4607 4608 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4609 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4610 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4611 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4612 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4613 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4614 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4615 4616 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4617 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4618 4619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4620 return MCDisassembler::Fail; 4621 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4622 return MCDisassembler::Fail; 4623 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4624 return MCDisassembler::Fail; 4625 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4626 return MCDisassembler::Fail; 4627 4628 return S; 4629 } 4630 4631 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4632 uint64_t Address, const void *Decoder) { 4633 DecodeStatus S = MCDisassembler::Success; 4634 4635 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4636 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4637 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4638 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4639 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4640 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4641 4642 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4643 4644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4645 return MCDisassembler::Fail; 4646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4647 return MCDisassembler::Fail; 4648 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4649 return MCDisassembler::Fail; 4650 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4651 return MCDisassembler::Fail; 4652 4653 return S; 4654 } 4655 4656 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4657 uint64_t Address, const void *Decoder) { 4658 DecodeStatus S = MCDisassembler::Success; 4659 4660 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4661 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4662 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4663 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4664 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4665 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4666 4667 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4668 4669 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4670 return MCDisassembler::Fail; 4671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4672 return MCDisassembler::Fail; 4673 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4674 return MCDisassembler::Fail; 4675 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4676 return MCDisassembler::Fail; 4677 4678 return S; 4679 } 4680 4681 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4682 uint64_t Address, const void *Decoder) { 4683 DecodeStatus S = MCDisassembler::Success; 4684 4685 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4686 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4687 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4688 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4689 unsigned size = fieldFromInstruction(Insn, 10, 2); 4690 4691 unsigned align = 0; 4692 unsigned index = 0; 4693 switch (size) { 4694 default: 4695 return MCDisassembler::Fail; 4696 case 0: 4697 if (fieldFromInstruction(Insn, 4, 1)) 4698 return MCDisassembler::Fail; // UNDEFINED 4699 index = fieldFromInstruction(Insn, 5, 3); 4700 break; 4701 case 1: 4702 if (fieldFromInstruction(Insn, 5, 1)) 4703 return MCDisassembler::Fail; // UNDEFINED 4704 index = fieldFromInstruction(Insn, 6, 2); 4705 if (fieldFromInstruction(Insn, 4, 1)) 4706 align = 2; 4707 break; 4708 case 2: 4709 if (fieldFromInstruction(Insn, 6, 1)) 4710 return MCDisassembler::Fail; // UNDEFINED 4711 index = fieldFromInstruction(Insn, 7, 1); 4712 4713 switch (fieldFromInstruction(Insn, 4, 2)) { 4714 case 0 : 4715 align = 0; break; 4716 case 3: 4717 align = 4; break; 4718 default: 4719 return MCDisassembler::Fail; 4720 } 4721 break; 4722 } 4723 4724 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4725 return MCDisassembler::Fail; 4726 if (Rm != 0xF) { // Writeback 4727 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4728 return MCDisassembler::Fail; 4729 } 4730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4731 return MCDisassembler::Fail; 4732 Inst.addOperand(MCOperand::createImm(align)); 4733 if (Rm != 0xF) { 4734 if (Rm != 0xD) { 4735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4736 return MCDisassembler::Fail; 4737 } else 4738 Inst.addOperand(MCOperand::createReg(0)); 4739 } 4740 4741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4742 return MCDisassembler::Fail; 4743 Inst.addOperand(MCOperand::createImm(index)); 4744 4745 return S; 4746 } 4747 4748 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4749 uint64_t Address, const void *Decoder) { 4750 DecodeStatus S = MCDisassembler::Success; 4751 4752 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4753 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4754 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4755 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4756 unsigned size = fieldFromInstruction(Insn, 10, 2); 4757 4758 unsigned align = 0; 4759 unsigned index = 0; 4760 switch (size) { 4761 default: 4762 return MCDisassembler::Fail; 4763 case 0: 4764 if (fieldFromInstruction(Insn, 4, 1)) 4765 return MCDisassembler::Fail; // UNDEFINED 4766 index = fieldFromInstruction(Insn, 5, 3); 4767 break; 4768 case 1: 4769 if (fieldFromInstruction(Insn, 5, 1)) 4770 return MCDisassembler::Fail; // UNDEFINED 4771 index = fieldFromInstruction(Insn, 6, 2); 4772 if (fieldFromInstruction(Insn, 4, 1)) 4773 align = 2; 4774 break; 4775 case 2: 4776 if (fieldFromInstruction(Insn, 6, 1)) 4777 return MCDisassembler::Fail; // UNDEFINED 4778 index = fieldFromInstruction(Insn, 7, 1); 4779 4780 switch (fieldFromInstruction(Insn, 4, 2)) { 4781 case 0: 4782 align = 0; break; 4783 case 3: 4784 align = 4; break; 4785 default: 4786 return MCDisassembler::Fail; 4787 } 4788 break; 4789 } 4790 4791 if (Rm != 0xF) { // Writeback 4792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4793 return MCDisassembler::Fail; 4794 } 4795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4796 return MCDisassembler::Fail; 4797 Inst.addOperand(MCOperand::createImm(align)); 4798 if (Rm != 0xF) { 4799 if (Rm != 0xD) { 4800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4801 return MCDisassembler::Fail; 4802 } else 4803 Inst.addOperand(MCOperand::createReg(0)); 4804 } 4805 4806 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4807 return MCDisassembler::Fail; 4808 Inst.addOperand(MCOperand::createImm(index)); 4809 4810 return S; 4811 } 4812 4813 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4814 uint64_t Address, const void *Decoder) { 4815 DecodeStatus S = MCDisassembler::Success; 4816 4817 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4818 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4819 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4820 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4821 unsigned size = fieldFromInstruction(Insn, 10, 2); 4822 4823 unsigned align = 0; 4824 unsigned index = 0; 4825 unsigned inc = 1; 4826 switch (size) { 4827 default: 4828 return MCDisassembler::Fail; 4829 case 0: 4830 index = fieldFromInstruction(Insn, 5, 3); 4831 if (fieldFromInstruction(Insn, 4, 1)) 4832 align = 2; 4833 break; 4834 case 1: 4835 index = fieldFromInstruction(Insn, 6, 2); 4836 if (fieldFromInstruction(Insn, 4, 1)) 4837 align = 4; 4838 if (fieldFromInstruction(Insn, 5, 1)) 4839 inc = 2; 4840 break; 4841 case 2: 4842 if (fieldFromInstruction(Insn, 5, 1)) 4843 return MCDisassembler::Fail; // UNDEFINED 4844 index = fieldFromInstruction(Insn, 7, 1); 4845 if (fieldFromInstruction(Insn, 4, 1) != 0) 4846 align = 8; 4847 if (fieldFromInstruction(Insn, 6, 1)) 4848 inc = 2; 4849 break; 4850 } 4851 4852 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4853 return MCDisassembler::Fail; 4854 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4855 return MCDisassembler::Fail; 4856 if (Rm != 0xF) { // Writeback 4857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4858 return MCDisassembler::Fail; 4859 } 4860 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4861 return MCDisassembler::Fail; 4862 Inst.addOperand(MCOperand::createImm(align)); 4863 if (Rm != 0xF) { 4864 if (Rm != 0xD) { 4865 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4866 return MCDisassembler::Fail; 4867 } else 4868 Inst.addOperand(MCOperand::createReg(0)); 4869 } 4870 4871 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4872 return MCDisassembler::Fail; 4873 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4874 return MCDisassembler::Fail; 4875 Inst.addOperand(MCOperand::createImm(index)); 4876 4877 return S; 4878 } 4879 4880 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4881 uint64_t Address, const void *Decoder) { 4882 DecodeStatus S = MCDisassembler::Success; 4883 4884 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4885 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4886 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4887 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4888 unsigned size = fieldFromInstruction(Insn, 10, 2); 4889 4890 unsigned align = 0; 4891 unsigned index = 0; 4892 unsigned inc = 1; 4893 switch (size) { 4894 default: 4895 return MCDisassembler::Fail; 4896 case 0: 4897 index = fieldFromInstruction(Insn, 5, 3); 4898 if (fieldFromInstruction(Insn, 4, 1)) 4899 align = 2; 4900 break; 4901 case 1: 4902 index = fieldFromInstruction(Insn, 6, 2); 4903 if (fieldFromInstruction(Insn, 4, 1)) 4904 align = 4; 4905 if (fieldFromInstruction(Insn, 5, 1)) 4906 inc = 2; 4907 break; 4908 case 2: 4909 if (fieldFromInstruction(Insn, 5, 1)) 4910 return MCDisassembler::Fail; // UNDEFINED 4911 index = fieldFromInstruction(Insn, 7, 1); 4912 if (fieldFromInstruction(Insn, 4, 1) != 0) 4913 align = 8; 4914 if (fieldFromInstruction(Insn, 6, 1)) 4915 inc = 2; 4916 break; 4917 } 4918 4919 if (Rm != 0xF) { // Writeback 4920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4921 return MCDisassembler::Fail; 4922 } 4923 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4924 return MCDisassembler::Fail; 4925 Inst.addOperand(MCOperand::createImm(align)); 4926 if (Rm != 0xF) { 4927 if (Rm != 0xD) { 4928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4929 return MCDisassembler::Fail; 4930 } else 4931 Inst.addOperand(MCOperand::createReg(0)); 4932 } 4933 4934 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4935 return MCDisassembler::Fail; 4936 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4937 return MCDisassembler::Fail; 4938 Inst.addOperand(MCOperand::createImm(index)); 4939 4940 return S; 4941 } 4942 4943 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4944 uint64_t Address, const void *Decoder) { 4945 DecodeStatus S = MCDisassembler::Success; 4946 4947 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4948 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4949 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4950 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4951 unsigned size = fieldFromInstruction(Insn, 10, 2); 4952 4953 unsigned align = 0; 4954 unsigned index = 0; 4955 unsigned inc = 1; 4956 switch (size) { 4957 default: 4958 return MCDisassembler::Fail; 4959 case 0: 4960 if (fieldFromInstruction(Insn, 4, 1)) 4961 return MCDisassembler::Fail; // UNDEFINED 4962 index = fieldFromInstruction(Insn, 5, 3); 4963 break; 4964 case 1: 4965 if (fieldFromInstruction(Insn, 4, 1)) 4966 return MCDisassembler::Fail; // UNDEFINED 4967 index = fieldFromInstruction(Insn, 6, 2); 4968 if (fieldFromInstruction(Insn, 5, 1)) 4969 inc = 2; 4970 break; 4971 case 2: 4972 if (fieldFromInstruction(Insn, 4, 2)) 4973 return MCDisassembler::Fail; // UNDEFINED 4974 index = fieldFromInstruction(Insn, 7, 1); 4975 if (fieldFromInstruction(Insn, 6, 1)) 4976 inc = 2; 4977 break; 4978 } 4979 4980 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4981 return MCDisassembler::Fail; 4982 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4983 return MCDisassembler::Fail; 4984 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4985 return MCDisassembler::Fail; 4986 4987 if (Rm != 0xF) { // Writeback 4988 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4989 return MCDisassembler::Fail; 4990 } 4991 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4992 return MCDisassembler::Fail; 4993 Inst.addOperand(MCOperand::createImm(align)); 4994 if (Rm != 0xF) { 4995 if (Rm != 0xD) { 4996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4997 return MCDisassembler::Fail; 4998 } else 4999 Inst.addOperand(MCOperand::createReg(0)); 5000 } 5001 5002 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5003 return MCDisassembler::Fail; 5004 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5005 return MCDisassembler::Fail; 5006 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5007 return MCDisassembler::Fail; 5008 Inst.addOperand(MCOperand::createImm(index)); 5009 5010 return S; 5011 } 5012 5013 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5014 uint64_t Address, const void *Decoder) { 5015 DecodeStatus S = MCDisassembler::Success; 5016 5017 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5018 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5019 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5020 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5021 unsigned size = fieldFromInstruction(Insn, 10, 2); 5022 5023 unsigned align = 0; 5024 unsigned index = 0; 5025 unsigned inc = 1; 5026 switch (size) { 5027 default: 5028 return MCDisassembler::Fail; 5029 case 0: 5030 if (fieldFromInstruction(Insn, 4, 1)) 5031 return MCDisassembler::Fail; // UNDEFINED 5032 index = fieldFromInstruction(Insn, 5, 3); 5033 break; 5034 case 1: 5035 if (fieldFromInstruction(Insn, 4, 1)) 5036 return MCDisassembler::Fail; // UNDEFINED 5037 index = fieldFromInstruction(Insn, 6, 2); 5038 if (fieldFromInstruction(Insn, 5, 1)) 5039 inc = 2; 5040 break; 5041 case 2: 5042 if (fieldFromInstruction(Insn, 4, 2)) 5043 return MCDisassembler::Fail; // UNDEFINED 5044 index = fieldFromInstruction(Insn, 7, 1); 5045 if (fieldFromInstruction(Insn, 6, 1)) 5046 inc = 2; 5047 break; 5048 } 5049 5050 if (Rm != 0xF) { // Writeback 5051 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5052 return MCDisassembler::Fail; 5053 } 5054 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5055 return MCDisassembler::Fail; 5056 Inst.addOperand(MCOperand::createImm(align)); 5057 if (Rm != 0xF) { 5058 if (Rm != 0xD) { 5059 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5060 return MCDisassembler::Fail; 5061 } else 5062 Inst.addOperand(MCOperand::createReg(0)); 5063 } 5064 5065 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5066 return MCDisassembler::Fail; 5067 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5068 return MCDisassembler::Fail; 5069 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5070 return MCDisassembler::Fail; 5071 Inst.addOperand(MCOperand::createImm(index)); 5072 5073 return S; 5074 } 5075 5076 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5077 uint64_t Address, const void *Decoder) { 5078 DecodeStatus S = MCDisassembler::Success; 5079 5080 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5081 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5082 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5083 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5084 unsigned size = fieldFromInstruction(Insn, 10, 2); 5085 5086 unsigned align = 0; 5087 unsigned index = 0; 5088 unsigned inc = 1; 5089 switch (size) { 5090 default: 5091 return MCDisassembler::Fail; 5092 case 0: 5093 if (fieldFromInstruction(Insn, 4, 1)) 5094 align = 4; 5095 index = fieldFromInstruction(Insn, 5, 3); 5096 break; 5097 case 1: 5098 if (fieldFromInstruction(Insn, 4, 1)) 5099 align = 8; 5100 index = fieldFromInstruction(Insn, 6, 2); 5101 if (fieldFromInstruction(Insn, 5, 1)) 5102 inc = 2; 5103 break; 5104 case 2: 5105 switch (fieldFromInstruction(Insn, 4, 2)) { 5106 case 0: 5107 align = 0; break; 5108 case 3: 5109 return MCDisassembler::Fail; 5110 default: 5111 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5112 } 5113 5114 index = fieldFromInstruction(Insn, 7, 1); 5115 if (fieldFromInstruction(Insn, 6, 1)) 5116 inc = 2; 5117 break; 5118 } 5119 5120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5121 return MCDisassembler::Fail; 5122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5123 return MCDisassembler::Fail; 5124 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5125 return MCDisassembler::Fail; 5126 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5127 return MCDisassembler::Fail; 5128 5129 if (Rm != 0xF) { // Writeback 5130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5131 return MCDisassembler::Fail; 5132 } 5133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5134 return MCDisassembler::Fail; 5135 Inst.addOperand(MCOperand::createImm(align)); 5136 if (Rm != 0xF) { 5137 if (Rm != 0xD) { 5138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5139 return MCDisassembler::Fail; 5140 } else 5141 Inst.addOperand(MCOperand::createReg(0)); 5142 } 5143 5144 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5145 return MCDisassembler::Fail; 5146 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5147 return MCDisassembler::Fail; 5148 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5149 return MCDisassembler::Fail; 5150 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5151 return MCDisassembler::Fail; 5152 Inst.addOperand(MCOperand::createImm(index)); 5153 5154 return S; 5155 } 5156 5157 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5158 uint64_t Address, const void *Decoder) { 5159 DecodeStatus S = MCDisassembler::Success; 5160 5161 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5162 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5163 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5164 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5165 unsigned size = fieldFromInstruction(Insn, 10, 2); 5166 5167 unsigned align = 0; 5168 unsigned index = 0; 5169 unsigned inc = 1; 5170 switch (size) { 5171 default: 5172 return MCDisassembler::Fail; 5173 case 0: 5174 if (fieldFromInstruction(Insn, 4, 1)) 5175 align = 4; 5176 index = fieldFromInstruction(Insn, 5, 3); 5177 break; 5178 case 1: 5179 if (fieldFromInstruction(Insn, 4, 1)) 5180 align = 8; 5181 index = fieldFromInstruction(Insn, 6, 2); 5182 if (fieldFromInstruction(Insn, 5, 1)) 5183 inc = 2; 5184 break; 5185 case 2: 5186 switch (fieldFromInstruction(Insn, 4, 2)) { 5187 case 0: 5188 align = 0; break; 5189 case 3: 5190 return MCDisassembler::Fail; 5191 default: 5192 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5193 } 5194 5195 index = fieldFromInstruction(Insn, 7, 1); 5196 if (fieldFromInstruction(Insn, 6, 1)) 5197 inc = 2; 5198 break; 5199 } 5200 5201 if (Rm != 0xF) { // Writeback 5202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5203 return MCDisassembler::Fail; 5204 } 5205 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5206 return MCDisassembler::Fail; 5207 Inst.addOperand(MCOperand::createImm(align)); 5208 if (Rm != 0xF) { 5209 if (Rm != 0xD) { 5210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5211 return MCDisassembler::Fail; 5212 } else 5213 Inst.addOperand(MCOperand::createReg(0)); 5214 } 5215 5216 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5217 return MCDisassembler::Fail; 5218 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5219 return MCDisassembler::Fail; 5220 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5221 return MCDisassembler::Fail; 5222 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5223 return MCDisassembler::Fail; 5224 Inst.addOperand(MCOperand::createImm(index)); 5225 5226 return S; 5227 } 5228 5229 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5230 uint64_t Address, const void *Decoder) { 5231 DecodeStatus S = MCDisassembler::Success; 5232 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5233 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5234 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5235 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5236 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5237 5238 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5239 S = MCDisassembler::SoftFail; 5240 5241 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5242 return MCDisassembler::Fail; 5243 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5244 return MCDisassembler::Fail; 5245 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5246 return MCDisassembler::Fail; 5247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5248 return MCDisassembler::Fail; 5249 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5250 return MCDisassembler::Fail; 5251 5252 return S; 5253 } 5254 5255 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5256 uint64_t Address, const void *Decoder) { 5257 DecodeStatus S = MCDisassembler::Success; 5258 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5259 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5260 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5261 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5262 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5263 5264 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5265 S = MCDisassembler::SoftFail; 5266 5267 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5268 return MCDisassembler::Fail; 5269 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5270 return MCDisassembler::Fail; 5271 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5272 return MCDisassembler::Fail; 5273 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5274 return MCDisassembler::Fail; 5275 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5276 return MCDisassembler::Fail; 5277 5278 return S; 5279 } 5280 5281 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5282 uint64_t Address, const void *Decoder) { 5283 DecodeStatus S = MCDisassembler::Success; 5284 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5285 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5286 5287 if (pred == 0xF) { 5288 pred = 0xE; 5289 S = MCDisassembler::SoftFail; 5290 } 5291 5292 if (mask == 0x0) 5293 return MCDisassembler::Fail; 5294 5295 // IT masks are encoded as a sequence of replacement low-order bits 5296 // for the condition code. So if the low bit of the starting 5297 // condition code is 1, then we have to flip all the bits above the 5298 // terminating bit (which is the lowest 1 bit). 5299 if (pred & 1) { 5300 unsigned LowBit = mask & -mask; 5301 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5302 mask ^= BitsAboveLowBit; 5303 } 5304 5305 Inst.addOperand(MCOperand::createImm(pred)); 5306 Inst.addOperand(MCOperand::createImm(mask)); 5307 return S; 5308 } 5309 5310 static DecodeStatus 5311 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5312 uint64_t Address, const void *Decoder) { 5313 DecodeStatus S = MCDisassembler::Success; 5314 5315 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5316 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5317 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5318 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5319 unsigned W = fieldFromInstruction(Insn, 21, 1); 5320 unsigned U = fieldFromInstruction(Insn, 23, 1); 5321 unsigned P = fieldFromInstruction(Insn, 24, 1); 5322 bool writeback = (W == 1) | (P == 0); 5323 5324 addr |= (U << 8) | (Rn << 9); 5325 5326 if (writeback && (Rn == Rt || Rn == Rt2)) 5327 Check(S, MCDisassembler::SoftFail); 5328 if (Rt == Rt2) 5329 Check(S, MCDisassembler::SoftFail); 5330 5331 // Rt 5332 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5333 return MCDisassembler::Fail; 5334 // Rt2 5335 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5336 return MCDisassembler::Fail; 5337 // Writeback operand 5338 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5339 return MCDisassembler::Fail; 5340 // addr 5341 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5342 return MCDisassembler::Fail; 5343 5344 return S; 5345 } 5346 5347 static DecodeStatus 5348 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5349 uint64_t Address, const void *Decoder) { 5350 DecodeStatus S = MCDisassembler::Success; 5351 5352 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5353 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5354 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5355 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5356 unsigned W = fieldFromInstruction(Insn, 21, 1); 5357 unsigned U = fieldFromInstruction(Insn, 23, 1); 5358 unsigned P = fieldFromInstruction(Insn, 24, 1); 5359 bool writeback = (W == 1) | (P == 0); 5360 5361 addr |= (U << 8) | (Rn << 9); 5362 5363 if (writeback && (Rn == Rt || Rn == Rt2)) 5364 Check(S, MCDisassembler::SoftFail); 5365 5366 // Writeback operand 5367 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5368 return MCDisassembler::Fail; 5369 // Rt 5370 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5371 return MCDisassembler::Fail; 5372 // Rt2 5373 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5374 return MCDisassembler::Fail; 5375 // addr 5376 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5377 return MCDisassembler::Fail; 5378 5379 return S; 5380 } 5381 5382 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5383 uint64_t Address, const void *Decoder) { 5384 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5385 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5386 if (sign1 != sign2) return MCDisassembler::Fail; 5387 5388 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5389 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5390 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5391 Val |= sign1 << 12; 5392 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5393 5394 return MCDisassembler::Success; 5395 } 5396 5397 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5398 uint64_t Address, 5399 const void *Decoder) { 5400 DecodeStatus S = MCDisassembler::Success; 5401 5402 // Shift of "asr #32" is not allowed in Thumb2 mode. 5403 if (Val == 0x20) S = MCDisassembler::Fail; 5404 Inst.addOperand(MCOperand::createImm(Val)); 5405 return S; 5406 } 5407 5408 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5409 uint64_t Address, const void *Decoder) { 5410 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5411 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5412 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5413 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5414 5415 if (pred == 0xF) 5416 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5417 5418 DecodeStatus S = MCDisassembler::Success; 5419 5420 if (Rt == Rn || Rn == Rt2) 5421 S = MCDisassembler::SoftFail; 5422 5423 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5424 return MCDisassembler::Fail; 5425 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5426 return MCDisassembler::Fail; 5427 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5428 return MCDisassembler::Fail; 5429 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5430 return MCDisassembler::Fail; 5431 5432 return S; 5433 } 5434 5435 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5436 uint64_t Address, const void *Decoder) { 5437 const FeatureBitset &featureBits = 5438 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5439 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5440 5441 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5442 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5443 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5444 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5445 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5446 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5447 unsigned op = fieldFromInstruction(Insn, 5, 1); 5448 5449 DecodeStatus S = MCDisassembler::Success; 5450 5451 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5452 if (!(imm & 0x38)) { 5453 if (cmode == 0xF) { 5454 if (op == 1) return MCDisassembler::Fail; 5455 Inst.setOpcode(ARM::VMOVv2f32); 5456 } 5457 if (hasFullFP16) { 5458 if (cmode == 0xE) { 5459 if (op == 1) { 5460 Inst.setOpcode(ARM::VMOVv1i64); 5461 } else { 5462 Inst.setOpcode(ARM::VMOVv8i8); 5463 } 5464 } 5465 if (cmode == 0xD) { 5466 if (op == 1) { 5467 Inst.setOpcode(ARM::VMVNv2i32); 5468 } else { 5469 Inst.setOpcode(ARM::VMOVv2i32); 5470 } 5471 } 5472 if (cmode == 0xC) { 5473 if (op == 1) { 5474 Inst.setOpcode(ARM::VMVNv2i32); 5475 } else { 5476 Inst.setOpcode(ARM::VMOVv2i32); 5477 } 5478 } 5479 } 5480 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5481 } 5482 5483 if (!(imm & 0x20)) return MCDisassembler::Fail; 5484 5485 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5486 return MCDisassembler::Fail; 5487 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5488 return MCDisassembler::Fail; 5489 Inst.addOperand(MCOperand::createImm(64 - imm)); 5490 5491 return S; 5492 } 5493 5494 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5495 uint64_t Address, const void *Decoder) { 5496 const FeatureBitset &featureBits = 5497 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5498 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5499 5500 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5501 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5502 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5503 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5504 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5505 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5506 unsigned op = fieldFromInstruction(Insn, 5, 1); 5507 5508 DecodeStatus S = MCDisassembler::Success; 5509 5510 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5511 if (!(imm & 0x38)) { 5512 if (cmode == 0xF) { 5513 if (op == 1) return MCDisassembler::Fail; 5514 Inst.setOpcode(ARM::VMOVv4f32); 5515 } 5516 if (hasFullFP16) { 5517 if (cmode == 0xE) { 5518 if (op == 1) { 5519 Inst.setOpcode(ARM::VMOVv2i64); 5520 } else { 5521 Inst.setOpcode(ARM::VMOVv16i8); 5522 } 5523 } 5524 if (cmode == 0xD) { 5525 if (op == 1) { 5526 Inst.setOpcode(ARM::VMVNv4i32); 5527 } else { 5528 Inst.setOpcode(ARM::VMOVv4i32); 5529 } 5530 } 5531 if (cmode == 0xC) { 5532 if (op == 1) { 5533 Inst.setOpcode(ARM::VMVNv4i32); 5534 } else { 5535 Inst.setOpcode(ARM::VMOVv4i32); 5536 } 5537 } 5538 } 5539 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5540 } 5541 5542 if (!(imm & 0x20)) return MCDisassembler::Fail; 5543 5544 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5545 return MCDisassembler::Fail; 5546 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5547 return MCDisassembler::Fail; 5548 Inst.addOperand(MCOperand::createImm(64 - imm)); 5549 5550 return S; 5551 } 5552 5553 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5554 unsigned Insn, 5555 uint64_t Address, 5556 const void *Decoder) { 5557 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5558 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5559 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5560 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5561 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5562 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5563 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5564 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5565 5566 DecodeStatus S = MCDisassembler::Success; 5567 5568 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5569 5570 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5571 return MCDisassembler::Fail; 5572 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5573 return MCDisassembler::Fail; 5574 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5575 return MCDisassembler::Fail; 5576 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5577 return MCDisassembler::Fail; 5578 // The lane index does not have any bits in the encoding, because it can only 5579 // be 0. 5580 Inst.addOperand(MCOperand::createImm(0)); 5581 Inst.addOperand(MCOperand::createImm(rotate)); 5582 5583 return S; 5584 } 5585 5586 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5587 uint64_t Address, const void *Decoder) { 5588 DecodeStatus S = MCDisassembler::Success; 5589 5590 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5591 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5592 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5593 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5594 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5595 5596 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5597 S = MCDisassembler::SoftFail; 5598 5599 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5600 return MCDisassembler::Fail; 5601 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5602 return MCDisassembler::Fail; 5603 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5604 return MCDisassembler::Fail; 5605 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5606 return MCDisassembler::Fail; 5607 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5608 return MCDisassembler::Fail; 5609 5610 return S; 5611 } 5612 5613 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5614 uint64_t Address, const void *Decoder) { 5615 DecodeStatus S = MCDisassembler::Success; 5616 5617 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5618 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5619 unsigned cop = fieldFromInstruction(Val, 8, 4); 5620 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5621 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5622 5623 if ((cop & ~0x1) == 0xa) 5624 return MCDisassembler::Fail; 5625 5626 if (Rt == Rt2) 5627 S = MCDisassembler::SoftFail; 5628 5629 // We have to check if the instruction is MRRC2 5630 // or MCRR2 when constructing the operands for 5631 // Inst. Reason is because MRRC2 stores to two 5632 // registers so it's tablegen desc has has two 5633 // outputs whereas MCRR doesn't store to any 5634 // registers so all of it's operands are listed 5635 // as inputs, therefore the operand order for 5636 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5637 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5638 5639 if (Inst.getOpcode() == ARM::MRRC2) { 5640 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5641 return MCDisassembler::Fail; 5642 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5643 return MCDisassembler::Fail; 5644 } 5645 Inst.addOperand(MCOperand::createImm(cop)); 5646 Inst.addOperand(MCOperand::createImm(opc1)); 5647 if (Inst.getOpcode() == ARM::MCRR2) { 5648 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5649 return MCDisassembler::Fail; 5650 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5651 return MCDisassembler::Fail; 5652 } 5653 Inst.addOperand(MCOperand::createImm(CRm)); 5654 5655 return S; 5656 } 5657 5658 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5659 uint64_t Address, 5660 const void *Decoder) { 5661 const FeatureBitset &featureBits = 5662 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5663 DecodeStatus S = MCDisassembler::Success; 5664 5665 // Add explicit operand for the destination sysreg, for cases where 5666 // we have to model it for code generation purposes. 5667 switch (Inst.getOpcode()) { 5668 case ARM::VMSR_FPSCR_NZCVQC: 5669 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5670 break; 5671 case ARM::VMSR_P0: 5672 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5673 break; 5674 } 5675 5676 if (Inst.getOpcode() != ARM::FMSTAT) { 5677 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5678 5679 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5680 if (Rt == 13 || Rt == 15) 5681 S = MCDisassembler::SoftFail; 5682 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5683 } else 5684 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5685 } 5686 5687 // Add explicit operand for the source sysreg, similarly to above. 5688 switch (Inst.getOpcode()) { 5689 case ARM::VMRS_FPSCR_NZCVQC: 5690 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5691 break; 5692 case ARM::VMRS_P0: 5693 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5694 break; 5695 } 5696 5697 if (featureBits[ARM::ModeThumb]) { 5698 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5699 Inst.addOperand(MCOperand::createReg(0)); 5700 } else { 5701 unsigned pred = fieldFromInstruction(Val, 28, 4); 5702 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5703 return MCDisassembler::Fail; 5704 } 5705 5706 return S; 5707 } 5708 5709 template <bool isSigned, bool isNeg, int size> 5710 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5711 uint64_t Address, 5712 const void *Decoder) { 5713 DecodeStatus S = MCDisassembler::Success; 5714 if (Val == 0) 5715 S = MCDisassembler::SoftFail; 5716 5717 uint64_t DecVal; 5718 if (isSigned) 5719 DecVal = SignExtend32<size + 1>(Val << 1); 5720 else 5721 DecVal = (Val << 1); 5722 5723 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5724 Decoder)) 5725 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5726 return S; 5727 } 5728 5729 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5730 uint64_t Address, 5731 const void *Decoder) { 5732 5733 uint64_t LocImm = Inst.getOperand(0).getImm(); 5734 Val = LocImm + (2 << Val); 5735 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5736 Decoder)) 5737 Inst.addOperand(MCOperand::createImm(Val)); 5738 return MCDisassembler::Success; 5739 } 5740 5741 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5742 uint64_t Address, 5743 const void *Decoder) { 5744 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5745 return MCDisassembler::Fail; 5746 Inst.addOperand(MCOperand::createImm(Val)); 5747 return MCDisassembler::Success; 5748 } 5749 5750 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5751 const void *Decoder) { 5752 DecodeStatus S = MCDisassembler::Success; 5753 5754 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5755 fieldFromInstruction(Insn, 1, 10) << 1; 5756 switch (Inst.getOpcode()) { 5757 case ARM::t2LEUpdate: 5758 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5759 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5760 LLVM_FALLTHROUGH; 5761 case ARM::t2LE: 5762 if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address, 5763 Decoder))) 5764 return MCDisassembler::Fail; 5765 break; 5766 case ARM::t2WLS: 5767 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5768 if (!Check(S, 5769 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5770 Address, Decoder)) || 5771 !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address, 5772 Decoder))) 5773 return MCDisassembler::Fail; 5774 break; 5775 case ARM::t2DLS: 5776 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5777 if (Rn == 0xF) { 5778 return MCDisassembler::Fail; 5779 } else { 5780 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5781 if (!Check(S, DecoderGPRRegisterClass(Inst, 5782 fieldFromInstruction(Insn, 16, 4), 5783 Address, Decoder))) 5784 return MCDisassembler::Fail; 5785 } 5786 break; 5787 } 5788 return S; 5789 } 5790 5791 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 5792 uint64_t Address, 5793 const void *Decoder) { 5794 DecodeStatus S = MCDisassembler::Success; 5795 5796 if (Val == 0) 5797 Val = 32; 5798 5799 Inst.addOperand(MCOperand::createImm(Val)); 5800 5801 return S; 5802 } 5803 5804 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 5805 uint64_t Address, const void *Decoder) { 5806 if ((RegNo) + 1 > 11) 5807 return MCDisassembler::Fail; 5808 5809 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 5810 Inst.addOperand(MCOperand::createReg(Register)); 5811 return MCDisassembler::Success; 5812 } 5813 5814 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 5815 uint64_t Address, const void *Decoder) { 5816 if ((RegNo) > 14) 5817 return MCDisassembler::Fail; 5818 5819 unsigned Register = GPRDecoderTable[(RegNo)]; 5820 Inst.addOperand(MCOperand::createReg(Register)); 5821 return MCDisassembler::Success; 5822 } 5823 5824 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 5825 const void *Decoder) { 5826 DecodeStatus S = MCDisassembler::Success; 5827 5828 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5829 Inst.addOperand(MCOperand::createReg(0)); 5830 if (Inst.getOpcode() == ARM::VSCCLRMD) { 5831 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 5832 (fieldFromInstruction(Insn, 12, 4) << 8) | 5833 (fieldFromInstruction(Insn, 22, 1) << 12); 5834 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 5835 return MCDisassembler::Fail; 5836 } 5837 } else { 5838 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 5839 (fieldFromInstruction(Insn, 22, 1) << 8) | 5840 (fieldFromInstruction(Insn, 12, 4) << 9); 5841 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 5842 return MCDisassembler::Fail; 5843 } 5844 } 5845 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5846 5847 return S; 5848 } 5849 5850 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 5851 uint64_t Address, 5852 const void *Decoder) { 5853 if (RegNo > 7) 5854 return MCDisassembler::Fail; 5855 5856 unsigned Register = QPRDecoderTable[RegNo]; 5857 Inst.addOperand(MCOperand::createReg(Register)); 5858 return MCDisassembler::Success; 5859 } 5860 5861 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 5862 uint64_t Address, 5863 const void *Decoder) { 5864 DecodeStatus S = MCDisassembler::Success; 5865 5866 // Parse VPT mask and encode it in the MCInst as an immediate with the same 5867 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 5868 // 't' as 0 and finish with a 1. 5869 unsigned Imm = 0; 5870 // We always start with a 't'. 5871 unsigned CurBit = 0; 5872 for (int i = 3; i >= 0; --i) { 5873 // If the bit we are looking at is not the same as last one, invert the 5874 // CurBit, if it is the same leave it as is. 5875 CurBit ^= (Val >> i) & 1U; 5876 5877 // Encode the CurBit at the right place in the immediate. 5878 Imm |= (CurBit << i); 5879 5880 // If we are done, finish the encoding with a 1. 5881 if ((Val & ~(~0U << i)) == 0) { 5882 Imm |= 1U << i; 5883 break; 5884 } 5885 } 5886 5887 Inst.addOperand(MCOperand::createImm(Imm)); 5888 5889 return S; 5890 } 5891 5892 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 5893 uint64_t Address, const void *Decoder) { 5894 // The vpred_r operand type includes an MQPR register field derived 5895 // from the encoding. But we don't actually want to add an operand 5896 // to the MCInst at this stage, because AddThumbPredicate will do it 5897 // later, and will infer the register number from the TIED_TO 5898 // constraint. So this is a deliberately empty decoder method that 5899 // will inhibit the auto-generated disassembly code from adding an 5900 // operand at all. 5901 return MCDisassembler::Success; 5902 } 5903 5904 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 5905 unsigned Val, 5906 uint64_t Address, 5907 const void *Decoder) { 5908 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 5909 return MCDisassembler::Success; 5910 } 5911 5912 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 5913 unsigned Val, 5914 uint64_t Address, 5915 const void *Decoder) { 5916 unsigned Code; 5917 switch (Val & 0x3) { 5918 case 0: 5919 Code = ARMCC::GE; 5920 break; 5921 case 1: 5922 Code = ARMCC::LT; 5923 break; 5924 case 2: 5925 Code = ARMCC::GT; 5926 break; 5927 case 3: 5928 Code = ARMCC::LE; 5929 break; 5930 } 5931 Inst.addOperand(MCOperand::createImm(Code)); 5932 return MCDisassembler::Success; 5933 } 5934 5935 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 5936 unsigned Val, 5937 uint64_t Address, 5938 const void *Decoder) { 5939 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 5940 return MCDisassembler::Success; 5941 } 5942 5943 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 5944 uint64_t Address, 5945 const void *Decoder) { 5946 unsigned Code; 5947 switch (Val) { 5948 default: 5949 return MCDisassembler::Fail; 5950 case 0: 5951 Code = ARMCC::EQ; 5952 break; 5953 case 1: 5954 Code = ARMCC::NE; 5955 break; 5956 case 4: 5957 Code = ARMCC::GE; 5958 break; 5959 case 5: 5960 Code = ARMCC::LT; 5961 break; 5962 case 6: 5963 Code = ARMCC::GT; 5964 break; 5965 case 7: 5966 Code = ARMCC::LE; 5967 break; 5968 } 5969 5970 Inst.addOperand(MCOperand::createImm(Code)); 5971 return MCDisassembler::Success; 5972 } 5973 5974 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 5975 switch (Opcode) { 5976 case ARM::VSTR_P0_off: 5977 case ARM::VSTR_P0_pre: 5978 case ARM::VSTR_P0_post: 5979 case ARM::VLDR_P0_off: 5980 case ARM::VLDR_P0_pre: 5981 case ARM::VLDR_P0_post: 5982 return ARM::P0; 5983 default: 5984 return 0; 5985 } 5986 } 5987 5988 template<bool Writeback> 5989 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 5990 uint64_t Address, 5991 const void *Decoder) { 5992 switch (Inst.getOpcode()) { 5993 case ARM::VSTR_FPSCR_pre: 5994 case ARM::VSTR_FPSCR_NZCVQC_pre: 5995 case ARM::VLDR_FPSCR_pre: 5996 case ARM::VLDR_FPSCR_NZCVQC_pre: 5997 case ARM::VSTR_FPSCR_off: 5998 case ARM::VSTR_FPSCR_NZCVQC_off: 5999 case ARM::VLDR_FPSCR_off: 6000 case ARM::VLDR_FPSCR_NZCVQC_off: 6001 case ARM::VSTR_FPSCR_post: 6002 case ARM::VSTR_FPSCR_NZCVQC_post: 6003 case ARM::VLDR_FPSCR_post: 6004 case ARM::VLDR_FPSCR_NZCVQC_post: 6005 const FeatureBitset &featureBits = 6006 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6007 6008 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6009 return MCDisassembler::Fail; 6010 } 6011 6012 DecodeStatus S = MCDisassembler::Success; 6013 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6014 Inst.addOperand(MCOperand::createReg(Sysreg)); 6015 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6016 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6017 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6018 6019 if (Writeback) { 6020 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6021 return MCDisassembler::Fail; 6022 } 6023 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6024 return MCDisassembler::Fail; 6025 6026 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6027 Inst.addOperand(MCOperand::createReg(0)); 6028 6029 return S; 6030 } 6031 6032 template <int shift> 6033 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6034 uint64_t Address, 6035 const void *Decoder) { 6036 Val <<= shift; 6037 6038 Inst.addOperand(MCOperand::createImm(Val)); 6039 return MCDisassembler::Success; 6040 } 6041 6042 static DecodeStatus DecodeMVEOverlappingLongShift( 6043 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6044 DecodeStatus S = MCDisassembler::Success; 6045 6046 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6047 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6048 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6049 6050 if (RdaHi == 14) { 6051 // This value of RdaHi (really indicating pc, because RdaHi has to 6052 // be an odd-numbered register, so the low bit will be set by the 6053 // decode function below) indicates that we must decode as SQRSHR 6054 // or UQRSHL, which both have a single Rda register field with all 6055 // four bits. 6056 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6057 6058 switch (Inst.getOpcode()) { 6059 case ARM::MVE_ASRLr: 6060 case ARM::MVE_SQRSHRL: 6061 Inst.setOpcode(ARM::MVE_SQRSHR); 6062 break; 6063 case ARM::MVE_LSLLr: 6064 case ARM::MVE_UQRSHLL: 6065 Inst.setOpcode(ARM::MVE_UQRSHL); 6066 break; 6067 default: 6068 llvm_unreachable("Unexpected starting opcode!"); 6069 } 6070 6071 // Rda as output parameter 6072 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6073 return MCDisassembler::Fail; 6074 6075 // Rda again as input parameter 6076 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6077 return MCDisassembler::Fail; 6078 6079 // Rm, the amount to shift by 6080 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6081 return MCDisassembler::Fail; 6082 6083 return S; 6084 } 6085 6086 // Otherwise, we decode as whichever opcode our caller has already 6087 // put into Inst. Those all look the same: 6088 6089 // RdaLo,RdaHi as output parameters 6090 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6091 return MCDisassembler::Fail; 6092 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6093 return MCDisassembler::Fail; 6094 6095 // RdaLo,RdaHi again as input parameters 6096 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6097 return MCDisassembler::Fail; 6098 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6099 return MCDisassembler::Fail; 6100 6101 // Rm, the amount to shift by 6102 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6103 return MCDisassembler::Fail; 6104 6105 return S; 6106 } 6107