1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #define DEBUG_TYPE "arm-disassembler" 11 12 #include "ARMDisassembler.h" 13 #include "ARM.h" 14 #include "ARMRegisterInfo.h" 15 #include "MCTargetDesc/ARMAddressingModes.h" 16 #include "MCTargetDesc/ARMBaseInfo.h" 17 #include "llvm/MC/EDInstInfo.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/Target/TargetRegistry.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/Support/MemoryObject.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 // Forward declare these because the autogenerated code will reference them. 28 // Definitions are further down. 29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 30 uint64_t Address, const void *Decoder); 31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 32 uint64_t Address, const void *Decoder); 33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 34 uint64_t Address, const void *Decoder); 35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 36 uint64_t Address, const void *Decoder); 37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 38 uint64_t Address, const void *Decoder); 39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 40 uint64_t Address, const void *Decoder); 41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 42 uint64_t Address, const void *Decoder); 43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 44 uint64_t Address, const void *Decoder); 45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 46 uint64_t Address, const void *Decoder); 47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 48 uint64_t Address, const void *Decoder); 49 50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 51 uint64_t Address, const void *Decoder); 52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 53 uint64_t Address, const void *Decoder); 54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 55 uint64_t Address, const void *Decoder); 56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 57 uint64_t Address, const void *Decoder); 58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 59 uint64_t Address, const void *Decoder); 60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 61 uint64_t Address, const void *Decoder); 62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 63 uint64_t Address, const void *Decoder); 64 65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 66 uint64_t Address, const void *Decoder); 67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 68 uint64_t Address, const void *Decoder); 69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 70 uint64_t Address, const void *Decoder); 71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 72 uint64_t Address, const void *Decoder); 73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 74 uint64_t Address, const void *Decoder); 75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 76 uint64_t Address, const void *Decoder); 77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 78 uint64_t Address, const void *Decoder); 79 80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, 81 unsigned Insn, 82 uint64_t Adddress, 83 const void *Decoder); 84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 85 uint64_t Address, const void *Decoder); 86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 87 uint64_t Address, const void *Decoder); 88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 89 uint64_t Address, const void *Decoder); 90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 91 uint64_t Address, const void *Decoder); 92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 93 uint64_t Address, const void *Decoder); 94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 95 uint64_t Address, const void *Decoder); 96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 97 uint64_t Address, const void *Decoder); 98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 99 uint64_t Address, const void *Decoder); 100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val, 101 uint64_t Address, const void *Decoder); 102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val, 103 uint64_t Address, const void *Decoder); 104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val, 105 uint64_t Address, const void *Decoder); 106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val, 107 uint64_t Address, const void *Decoder); 108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val, 109 uint64_t Address, const void *Decoder); 110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val, 111 uint64_t Address, const void *Decoder); 112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val, 113 uint64_t Address, const void *Decoder); 114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val, 115 uint64_t Address, const void *Decoder); 116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 117 uint64_t Address, const void *Decoder); 118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 119 uint64_t Address, const void *Decoder); 120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 121 uint64_t Address, const void *Decoder); 122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 123 uint64_t Address, const void *Decoder); 124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 125 uint64_t Address, const void *Decoder); 126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 127 uint64_t Address, const void *Decoder); 128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 129 uint64_t Address, const void *Decoder); 130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn, 131 uint64_t Address, const void *Decoder); 132 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn, 133 uint64_t Address, const void *Decoder); 134 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn, 135 uint64_t Address, const void *Decoder); 136 static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 137 uint64_t Address, const void *Decoder); 138 static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 139 uint64_t Address, const void *Decoder); 140 static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 141 uint64_t Address, const void *Decoder); 142 static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 143 uint64_t Address, const void *Decoder); 144 static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 145 uint64_t Address, const void *Decoder); 146 static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 147 uint64_t Address, const void *Decoder); 148 static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 149 uint64_t Address, const void *Decoder); 150 static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 151 uint64_t Address, const void *Decoder); 152 static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 153 uint64_t Address, const void *Decoder); 154 static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 155 uint64_t Address, const void *Decoder); 156 static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 157 uint64_t Address, const void *Decoder); 158 static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 159 uint64_t Address, const void *Decoder); 160 161 162 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 163 uint64_t Address, const void *Decoder); 164 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 165 uint64_t Address, const void *Decoder); 166 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 167 uint64_t Address, const void *Decoder); 168 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 169 uint64_t Address, const void *Decoder); 170 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 171 uint64_t Address, const void *Decoder); 172 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 173 uint64_t Address, const void *Decoder); 174 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 175 uint64_t Address, const void *Decoder); 176 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 177 uint64_t Address, const void *Decoder); 178 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 179 uint64_t Address, const void *Decoder); 180 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val, 181 uint64_t Address, const void *Decoder); 182 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 183 uint64_t Address, const void *Decoder); 184 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 185 uint64_t Address, const void *Decoder); 186 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 187 uint64_t Address, const void *Decoder); 188 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 189 uint64_t Address, const void *Decoder); 190 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val, 191 uint64_t Address, const void *Decoder); 192 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 193 uint64_t Address, const void *Decoder); 194 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 195 uint64_t Address, const void *Decoder); 196 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 199 uint64_t Address, const void *Decoder); 200 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 201 uint64_t Address, const void *Decoder); 202 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val, 203 uint64_t Address, const void *Decoder); 204 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 205 uint64_t Address, const void *Decoder); 206 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 207 uint64_t Address, const void *Decoder); 208 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 209 uint64_t Address, const void *Decoder); 210 211 #include "ARMGenDisassemblerTables.inc" 212 #include "ARMGenInstrInfo.inc" 213 #include "ARMGenEDInfo.inc" 214 215 using namespace llvm; 216 217 static MCDisassembler *createARMDisassembler(const Target &T) { 218 return new ARMDisassembler; 219 } 220 221 static MCDisassembler *createThumbDisassembler(const Target &T) { 222 return new ThumbDisassembler; 223 } 224 225 EDInstInfo *ARMDisassembler::getEDInfo() const { 226 return instInfoARM; 227 } 228 229 EDInstInfo *ThumbDisassembler::getEDInfo() const { 230 return instInfoARM; 231 } 232 233 234 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 235 const MemoryObject &Region, 236 uint64_t Address,raw_ostream &os) const { 237 uint8_t bytes[4]; 238 239 // We want to read exactly 4 bytes of data. 240 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 241 return false; 242 243 // Encoded as a small-endian 32-bit word in the stream. 244 uint32_t insn = (bytes[3] << 24) | 245 (bytes[2] << 16) | 246 (bytes[1] << 8) | 247 (bytes[0] << 0); 248 249 // Calling the auto-generated decoder function. 250 bool result = decodeARMInstruction32(MI, insn, Address, this); 251 if (result) { 252 Size = 4; 253 return true; 254 } 255 256 // Instructions that are shared between ARM and Thumb modes. 257 // FIXME: This shouldn't really exist. It's an artifact of the 258 // fact that we fail to encode a few instructions properly for Thumb. 259 MI.clear(); 260 result = decodeCommonInstruction32(MI, insn, Address, this); 261 if (result) { 262 Size = 4; 263 return true; 264 } 265 266 // VFP and NEON instructions, similarly, are shared between ARM 267 // and Thumb modes. 268 MI.clear(); 269 result = decodeVFPInstruction32(MI, insn, Address, this); 270 if (result) { 271 Size = 4; 272 return true; 273 } 274 275 MI.clear(); 276 result = decodeNEONDataInstruction32(MI, insn, Address, this); 277 if (result) { 278 Size = 4; 279 // Add a fake predicate operand, because we share these instruction 280 // definitions with Thumb2 where these instructions are predicable. 281 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 282 return true; 283 } 284 285 MI.clear(); 286 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this); 287 if (result) { 288 Size = 4; 289 // Add a fake predicate operand, because we share these instruction 290 // definitions with Thumb2 where these instructions are predicable. 291 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 292 return true; 293 } 294 295 MI.clear(); 296 result = decodeNEONDupInstruction32(MI, insn, Address, this); 297 if (result) { 298 Size = 4; 299 // Add a fake predicate operand, because we share these instruction 300 // definitions with Thumb2 where these instructions are predicable. 301 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false; 302 return true; 303 } 304 305 MI.clear(); 306 307 return false; 308 } 309 310 namespace llvm { 311 extern MCInstrDesc ARMInsts[]; 312 } 313 314 // Thumb1 instructions don't have explicit S bits. Rather, they 315 // implicitly set CPSR. Since it's not represented in the encoding, the 316 // auto-generated decoder won't inject the CPSR operand. We need to fix 317 // that as a post-pass. 318 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 319 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 320 MCInst::iterator I = MI.begin(); 321 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 322 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 323 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 324 return; 325 } 326 } 327 328 if (OpInfo[MI.size()].isOptionalDef() && 329 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID) 330 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 331 } 332 333 // Most Thumb instructions don't have explicit predicates in the 334 // encoding, but rather get their predicates from IT context. We need 335 // to fix up the predicate operands using this context information as a 336 // post-pass. 337 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 338 // A few instructions actually have predicates encoded in them. Don't 339 // try to overwrite it if we're seeing one of those. 340 switch (MI.getOpcode()) { 341 case ARM::tBcc: 342 case ARM::t2Bcc: 343 return; 344 default: 345 break; 346 } 347 348 // If we're in an IT block, base the predicate on that. Otherwise, 349 // assume a predicate of AL. 350 unsigned CC; 351 if (!ITBlock.empty()) { 352 CC = ITBlock.back(); 353 ITBlock.pop_back(); 354 } else 355 CC = ARMCC::AL; 356 357 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 358 MCInst::iterator I = MI.begin(); 359 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 360 if (OpInfo[i].isPredicate()) { 361 I = MI.insert(I, MCOperand::CreateImm(CC)); 362 ++I; 363 if (CC == ARMCC::AL) 364 MI.insert(I, MCOperand::CreateReg(0)); 365 else 366 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 367 return; 368 } 369 } 370 371 MI.insert(MI.end(), MCOperand::CreateImm(CC)); 372 if (CC == ARMCC::AL) 373 MI.insert(MI.end(), MCOperand::CreateReg(0)); 374 else 375 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR)); 376 } 377 378 // Thumb VFP instructions are a special case. Because we share their 379 // encodings between ARM and Thumb modes, and they are predicable in ARM 380 // mode, the auto-generated decoder will give them an (incorrect) 381 // predicate operand. We need to rewrite these operands based on the IT 382 // context as a post-pass. 383 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 384 unsigned CC; 385 if (!ITBlock.empty()) { 386 CC = ITBlock.back(); 387 ITBlock.pop_back(); 388 } else 389 CC = ARMCC::AL; 390 391 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 392 MCInst::iterator I = MI.begin(); 393 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) { 394 if (OpInfo[i].isPredicate() ) { 395 I->setImm(CC); 396 ++I; 397 if (CC == ARMCC::AL) 398 I->setReg(0); 399 else 400 I->setReg(ARM::CPSR); 401 return; 402 } 403 } 404 } 405 406 407 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 408 const MemoryObject &Region, 409 uint64_t Address,raw_ostream &os) const { 410 uint8_t bytes[4]; 411 412 // We want to read exactly 2 bytes of data. 413 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) 414 return false; 415 416 uint16_t insn16 = (bytes[1] << 8) | bytes[0]; 417 bool result = decodeThumbInstruction16(MI, insn16, Address, this); 418 if (result) { 419 Size = 2; 420 bool InITBlock = !ITBlock.empty(); 421 AddThumbPredicate(MI); 422 AddThumb1SBit(MI, InITBlock); 423 return true; 424 } 425 426 MI.clear(); 427 result = decodeThumb2Instruction16(MI, insn16, Address, this); 428 if (result) { 429 Size = 2; 430 AddThumbPredicate(MI); 431 432 // If we find an IT instruction, we need to parse its condition 433 // code and mask operands so that we can apply them correctly 434 // to the subsequent instructions. 435 if (MI.getOpcode() == ARM::t2IT) { 436 unsigned firstcond = MI.getOperand(0).getImm(); 437 uint32_t mask = MI.getOperand(1).getImm(); 438 unsigned zeros = CountTrailingZeros_32(mask); 439 mask >>= zeros+1; 440 441 for (unsigned i = 0; i < 4 - (zeros+1); ++i) { 442 if (firstcond ^ (mask & 1)) 443 ITBlock.push_back(firstcond ^ 1); 444 else 445 ITBlock.push_back(firstcond); 446 mask >>= 1; 447 } 448 ITBlock.push_back(firstcond); 449 } 450 451 return true; 452 } 453 454 // We want to read exactly 4 bytes of data. 455 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) 456 return false; 457 458 uint32_t insn32 = (bytes[3] << 8) | 459 (bytes[2] << 0) | 460 (bytes[1] << 24) | 461 (bytes[0] << 16); 462 MI.clear(); 463 result = decodeThumbInstruction32(MI, insn32, Address, this); 464 if (result) { 465 Size = 4; 466 bool InITBlock = ITBlock.size(); 467 AddThumbPredicate(MI); 468 AddThumb1SBit(MI, InITBlock); 469 return true; 470 } 471 472 MI.clear(); 473 result = decodeThumb2Instruction32(MI, insn32, Address, this); 474 if (result) { 475 Size = 4; 476 AddThumbPredicate(MI); 477 return true; 478 } 479 480 MI.clear(); 481 result = decodeCommonInstruction32(MI, insn32, Address, this); 482 if (result) { 483 Size = 4; 484 AddThumbPredicate(MI); 485 return true; 486 } 487 488 MI.clear(); 489 result = decodeVFPInstruction32(MI, insn32, Address, this); 490 if (result) { 491 Size = 4; 492 UpdateThumbVFPPredicate(MI); 493 return true; 494 } 495 496 MI.clear(); 497 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) { 498 uint32_t NEONDataInsn = insn32; 499 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 500 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 501 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 502 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this); 503 if (result) { 504 Size = 4; 505 AddThumbPredicate(MI); 506 return true; 507 } 508 } 509 510 MI.clear(); 511 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this); 512 if (result) { 513 Size = 4; 514 AddThumbPredicate(MI); 515 return true; 516 } 517 518 MI.clear(); 519 result = decodeNEONDupInstruction32(MI, insn32, Address, this); 520 if (result) { 521 Size = 4; 522 AddThumbPredicate(MI); 523 return true; 524 } 525 526 return false; 527 } 528 529 530 extern "C" void LLVMInitializeARMDisassembler() { 531 TargetRegistry::RegisterMCDisassembler(TheARMTarget, 532 createARMDisassembler); 533 TargetRegistry::RegisterMCDisassembler(TheThumbTarget, 534 createThumbDisassembler); 535 } 536 537 static const unsigned GPRDecoderTable[] = { 538 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 539 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 540 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 541 ARM::R12, ARM::SP, ARM::LR, ARM::PC 542 }; 543 544 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 545 uint64_t Address, const void *Decoder) { 546 if (RegNo > 15) 547 return false; 548 549 unsigned Register = GPRDecoderTable[RegNo]; 550 Inst.addOperand(MCOperand::CreateReg(Register)); 551 return true; 552 } 553 554 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 555 uint64_t Address, const void *Decoder) { 556 if (RegNo == 15) return false; 557 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 558 } 559 560 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 561 uint64_t Address, const void *Decoder) { 562 if (RegNo > 7) 563 return false; 564 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 565 } 566 567 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 568 uint64_t Address, const void *Decoder) { 569 unsigned Register = 0; 570 switch (RegNo) { 571 case 0: 572 Register = ARM::R0; 573 break; 574 case 1: 575 Register = ARM::R1; 576 break; 577 case 2: 578 Register = ARM::R2; 579 break; 580 case 3: 581 Register = ARM::R3; 582 break; 583 case 9: 584 Register = ARM::R9; 585 break; 586 case 12: 587 Register = ARM::R12; 588 break; 589 default: 590 return false; 591 } 592 593 Inst.addOperand(MCOperand::CreateReg(Register)); 594 return true; 595 } 596 597 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 598 uint64_t Address, const void *Decoder) { 599 if (RegNo == 13 || RegNo == 15) return false; 600 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 601 } 602 603 static const unsigned SPRDecoderTable[] = { 604 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 605 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 606 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 607 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 608 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 609 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 610 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 611 ARM::S28, ARM::S29, ARM::S30, ARM::S31 612 }; 613 614 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 615 uint64_t Address, const void *Decoder) { 616 if (RegNo > 31) 617 return false; 618 619 unsigned Register = SPRDecoderTable[RegNo]; 620 Inst.addOperand(MCOperand::CreateReg(Register)); 621 return true; 622 } 623 624 static const unsigned DPRDecoderTable[] = { 625 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 626 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 627 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 628 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 629 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 630 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 631 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 632 ARM::D28, ARM::D29, ARM::D30, ARM::D31 633 }; 634 635 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 636 uint64_t Address, const void *Decoder) { 637 if (RegNo > 31) 638 return false; 639 640 unsigned Register = DPRDecoderTable[RegNo]; 641 Inst.addOperand(MCOperand::CreateReg(Register)); 642 return true; 643 } 644 645 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 646 uint64_t Address, const void *Decoder) { 647 if (RegNo > 7) 648 return false; 649 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 650 } 651 652 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 653 uint64_t Address, const void *Decoder) { 654 if (RegNo > 15) 655 return false; 656 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 657 } 658 659 static const unsigned QPRDecoderTable[] = { 660 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 661 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 662 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 663 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 664 }; 665 666 667 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 668 uint64_t Address, const void *Decoder) { 669 if (RegNo > 31) 670 return false; 671 RegNo >>= 1; 672 673 unsigned Register = QPRDecoderTable[RegNo]; 674 Inst.addOperand(MCOperand::CreateReg(Register)); 675 return true; 676 } 677 678 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val, 679 uint64_t Address, const void *Decoder) { 680 if (Val == 0xF) return false; 681 // AL predicate is not allowed on Thumb1 branches. 682 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 683 return false; 684 Inst.addOperand(MCOperand::CreateImm(Val)); 685 if (Val == ARMCC::AL) { 686 Inst.addOperand(MCOperand::CreateReg(0)); 687 } else 688 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 689 return true; 690 } 691 692 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val, 693 uint64_t Address, const void *Decoder) { 694 if (Val) 695 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 696 else 697 Inst.addOperand(MCOperand::CreateReg(0)); 698 return true; 699 } 700 701 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val, 702 uint64_t Address, const void *Decoder) { 703 uint32_t imm = Val & 0xFF; 704 uint32_t rot = (Val & 0xF00) >> 7; 705 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot)); 706 Inst.addOperand(MCOperand::CreateImm(rot_imm)); 707 return true; 708 } 709 710 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 711 uint64_t Address, const void *Decoder) { 712 Val <<= 2; 713 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val))); 714 return true; 715 } 716 717 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val, 718 uint64_t Address, const void *Decoder) { 719 720 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 721 unsigned type = fieldFromInstruction32(Val, 5, 2); 722 unsigned imm = fieldFromInstruction32(Val, 7, 5); 723 724 // Register-immediate 725 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 726 727 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 728 switch (type) { 729 case 0: 730 Shift = ARM_AM::lsl; 731 break; 732 case 1: 733 Shift = ARM_AM::lsr; 734 break; 735 case 2: 736 Shift = ARM_AM::asr; 737 break; 738 case 3: 739 Shift = ARM_AM::ror; 740 break; 741 } 742 743 if (Shift == ARM_AM::ror && imm == 0) 744 Shift = ARM_AM::rrx; 745 746 unsigned Op = Shift | (imm << 3); 747 Inst.addOperand(MCOperand::CreateImm(Op)); 748 749 return true; 750 } 751 752 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, 753 uint64_t Address, const void *Decoder) { 754 755 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 756 unsigned type = fieldFromInstruction32(Val, 5, 2); 757 unsigned Rs = fieldFromInstruction32(Val, 8, 4); 758 759 // Register-register 760 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 761 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; 762 763 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 764 switch (type) { 765 case 0: 766 Shift = ARM_AM::lsl; 767 break; 768 case 1: 769 Shift = ARM_AM::lsr; 770 break; 771 case 2: 772 Shift = ARM_AM::asr; 773 break; 774 case 3: 775 Shift = ARM_AM::ror; 776 break; 777 } 778 779 Inst.addOperand(MCOperand::CreateImm(Shift)); 780 781 return true; 782 } 783 784 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val, 785 uint64_t Address, const void *Decoder) { 786 // Empty register lists are not allowed. 787 if (CountPopulation_32(Val) == 0) return false; 788 for (unsigned i = 0; i < 16; ++i) { 789 if (Val & (1 << i)) { 790 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false; 791 } 792 } 793 794 return true; 795 } 796 797 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 798 uint64_t Address, const void *Decoder) { 799 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 800 unsigned regs = Val & 0xFF; 801 802 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 803 for (unsigned i = 0; i < (regs - 1); ++i) { 804 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 805 } 806 807 return true; 808 } 809 810 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val, 811 uint64_t Address, const void *Decoder) { 812 unsigned Vd = fieldFromInstruction32(Val, 8, 4); 813 unsigned regs = (Val & 0xFF) / 2; 814 815 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false; 816 for (unsigned i = 0; i < (regs - 1); ++i) { 817 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false; 818 } 819 820 return true; 821 } 822 823 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val, 824 uint64_t Address, const void *Decoder) { 825 // This operand encodes a mask of contiguous zeros between a specified MSB 826 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 827 // the mask of all bits LSB-and-lower, and then xor them to create 828 // the mask of that's all ones on [msb, lsb]. Finally we not it to 829 // create the final mask. 830 unsigned msb = fieldFromInstruction32(Val, 5, 5); 831 unsigned lsb = fieldFromInstruction32(Val, 0, 5); 832 uint32_t msb_mask = (1 << (msb+1)) - 1; 833 uint32_t lsb_mask = (1 << lsb) - 1; 834 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 835 return true; 836 } 837 838 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 839 uint64_t Address, const void *Decoder) { 840 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 841 unsigned CRd = fieldFromInstruction32(Insn, 12, 4); 842 unsigned coproc = fieldFromInstruction32(Insn, 8, 4); 843 unsigned imm = fieldFromInstruction32(Insn, 0, 8); 844 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 845 unsigned U = fieldFromInstruction32(Insn, 23, 1); 846 847 switch (Inst.getOpcode()) { 848 case ARM::LDC_OFFSET: 849 case ARM::LDC_PRE: 850 case ARM::LDC_POST: 851 case ARM::LDC_OPTION: 852 case ARM::LDCL_OFFSET: 853 case ARM::LDCL_PRE: 854 case ARM::LDCL_POST: 855 case ARM::LDCL_OPTION: 856 case ARM::STC_OFFSET: 857 case ARM::STC_PRE: 858 case ARM::STC_POST: 859 case ARM::STC_OPTION: 860 case ARM::STCL_OFFSET: 861 case ARM::STCL_PRE: 862 case ARM::STCL_POST: 863 case ARM::STCL_OPTION: 864 if (coproc == 0xA || coproc == 0xB) 865 return false; 866 break; 867 default: 868 break; 869 } 870 871 Inst.addOperand(MCOperand::CreateImm(coproc)); 872 Inst.addOperand(MCOperand::CreateImm(CRd)); 873 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 874 switch (Inst.getOpcode()) { 875 case ARM::LDC_OPTION: 876 case ARM::LDCL_OPTION: 877 case ARM::LDC2_OPTION: 878 case ARM::LDC2L_OPTION: 879 case ARM::STC_OPTION: 880 case ARM::STCL_OPTION: 881 case ARM::STC2_OPTION: 882 case ARM::STC2L_OPTION: 883 case ARM::LDCL_POST: 884 case ARM::STCL_POST: 885 break; 886 default: 887 Inst.addOperand(MCOperand::CreateReg(0)); 888 break; 889 } 890 891 unsigned P = fieldFromInstruction32(Insn, 24, 1); 892 unsigned W = fieldFromInstruction32(Insn, 21, 1); 893 894 bool writeback = (P == 0) || (W == 1); 895 unsigned idx_mode = 0; 896 if (P && writeback) 897 idx_mode = ARMII::IndexModePre; 898 else if (!P && writeback) 899 idx_mode = ARMII::IndexModePost; 900 901 switch (Inst.getOpcode()) { 902 case ARM::LDCL_POST: 903 case ARM::STCL_POST: 904 imm |= U << 8; 905 case ARM::LDC_OPTION: 906 case ARM::LDCL_OPTION: 907 case ARM::LDC2_OPTION: 908 case ARM::LDC2L_OPTION: 909 case ARM::STC_OPTION: 910 case ARM::STCL_OPTION: 911 case ARM::STC2_OPTION: 912 case ARM::STC2L_OPTION: 913 Inst.addOperand(MCOperand::CreateImm(imm)); 914 break; 915 default: 916 if (U) 917 Inst.addOperand(MCOperand::CreateImm( 918 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode))); 919 else 920 Inst.addOperand(MCOperand::CreateImm( 921 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode))); 922 break; 923 } 924 925 switch (Inst.getOpcode()) { 926 case ARM::LDC_OFFSET: 927 case ARM::LDC_PRE: 928 case ARM::LDC_POST: 929 case ARM::LDC_OPTION: 930 case ARM::LDCL_OFFSET: 931 case ARM::LDCL_PRE: 932 case ARM::LDCL_POST: 933 case ARM::LDCL_OPTION: 934 case ARM::STC_OFFSET: 935 case ARM::STC_PRE: 936 case ARM::STC_POST: 937 case ARM::STC_OPTION: 938 case ARM::STCL_OFFSET: 939 case ARM::STCL_PRE: 940 case ARM::STCL_POST: 941 case ARM::STCL_OPTION: 942 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 943 break; 944 default: 945 break; 946 } 947 948 return true; 949 } 950 951 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, 952 uint64_t Address, const void *Decoder) { 953 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 954 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 955 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 956 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 957 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 958 unsigned reg = fieldFromInstruction32(Insn, 25, 1); 959 unsigned P = fieldFromInstruction32(Insn, 24, 1); 960 unsigned W = fieldFromInstruction32(Insn, 21, 1); 961 962 // On stores, the writeback operand precedes Rt. 963 switch (Inst.getOpcode()) { 964 case ARM::STR_POST_IMM: 965 case ARM::STR_POST_REG: 966 case ARM::STRB_POST_IMM: 967 case ARM::STRB_POST_REG: 968 case ARM::STRT_POST_REG: 969 case ARM::STRT_POST_IMM: 970 case ARM::STRBT_POST_REG: 971 case ARM::STRBT_POST_IMM: 972 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 973 break; 974 default: 975 break; 976 } 977 978 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 979 980 // On loads, the writeback operand comes after Rt. 981 switch (Inst.getOpcode()) { 982 case ARM::LDR_POST_IMM: 983 case ARM::LDR_POST_REG: 984 case ARM::LDRB_POST_IMM: 985 case ARM::LDRB_POST_REG: 986 case ARM::LDR_PRE: 987 case ARM::LDRB_PRE: 988 case ARM::LDRBT_POST_REG: 989 case ARM::LDRBT_POST_IMM: 990 case ARM::LDRT_POST_REG: 991 case ARM::LDRT_POST_IMM: 992 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 993 return false; 994 break; 995 default: 996 break; 997 } 998 999 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1000 1001 ARM_AM::AddrOpc Op = ARM_AM::add; 1002 if (!fieldFromInstruction32(Insn, 23, 1)) 1003 Op = ARM_AM::sub; 1004 1005 bool writeback = (P == 0) || (W == 1); 1006 unsigned idx_mode = 0; 1007 if (P && writeback) 1008 idx_mode = ARMII::IndexModePre; 1009 else if (!P && writeback) 1010 idx_mode = ARMII::IndexModePost; 1011 1012 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE 1013 1014 if (reg) { 1015 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; 1016 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1017 switch( fieldFromInstruction32(Insn, 5, 2)) { 1018 case 0: 1019 Opc = ARM_AM::lsl; 1020 break; 1021 case 1: 1022 Opc = ARM_AM::lsr; 1023 break; 1024 case 2: 1025 Opc = ARM_AM::asr; 1026 break; 1027 case 3: 1028 Opc = ARM_AM::ror; 1029 break; 1030 default: 1031 return false; 1032 } 1033 unsigned amt = fieldFromInstruction32(Insn, 7, 5); 1034 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1035 1036 Inst.addOperand(MCOperand::CreateImm(imm)); 1037 } else { 1038 Inst.addOperand(MCOperand::CreateReg(0)); 1039 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1040 Inst.addOperand(MCOperand::CreateImm(tmp)); 1041 } 1042 1043 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1044 1045 return true; 1046 } 1047 1048 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val, 1049 uint64_t Address, const void *Decoder) { 1050 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1051 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1052 unsigned type = fieldFromInstruction32(Val, 5, 2); 1053 unsigned imm = fieldFromInstruction32(Val, 7, 5); 1054 unsigned U = fieldFromInstruction32(Val, 12, 1); 1055 1056 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1057 switch (type) { 1058 case 0: 1059 ShOp = ARM_AM::lsl; 1060 break; 1061 case 1: 1062 ShOp = ARM_AM::lsr; 1063 break; 1064 case 2: 1065 ShOp = ARM_AM::asr; 1066 break; 1067 case 3: 1068 ShOp = ARM_AM::ror; 1069 break; 1070 } 1071 1072 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1073 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1074 unsigned shift; 1075 if (U) 1076 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1077 else 1078 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1079 Inst.addOperand(MCOperand::CreateImm(shift)); 1080 1081 return true; 1082 } 1083 1084 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, 1085 uint64_t Address, const void *Decoder) { 1086 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 1087 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1088 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1089 unsigned type = fieldFromInstruction32(Insn, 22, 1); 1090 unsigned imm = fieldFromInstruction32(Insn, 8, 4); 1091 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8; 1092 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1093 unsigned W = fieldFromInstruction32(Insn, 21, 1); 1094 unsigned P = fieldFromInstruction32(Insn, 24, 1); 1095 1096 bool writeback = (W == 1) | (P == 0); 1097 1098 // For {LD,ST}RD, Rt must be even, else undefined. 1099 switch (Inst.getOpcode()) { 1100 case ARM::STRD: 1101 case ARM::STRD_PRE: 1102 case ARM::STRD_POST: 1103 case ARM::LDRD: 1104 case ARM::LDRD_PRE: 1105 case ARM::LDRD_POST: 1106 if (Rt & 0x1) return false; 1107 break; 1108 default: 1109 break; 1110 } 1111 1112 if (writeback) { // Writeback 1113 if (P) 1114 U |= ARMII::IndexModePre << 9; 1115 else 1116 U |= ARMII::IndexModePost << 9; 1117 1118 // On stores, the writeback operand precedes Rt. 1119 switch (Inst.getOpcode()) { 1120 case ARM::STRD: 1121 case ARM::STRD_PRE: 1122 case ARM::STRD_POST: 1123 case ARM::STRH: 1124 case ARM::STRH_PRE: 1125 case ARM::STRH_POST: 1126 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1127 return false; 1128 break; 1129 default: 1130 break; 1131 } 1132 } 1133 1134 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) 1135 return false; 1136 switch (Inst.getOpcode()) { 1137 case ARM::STRD: 1138 case ARM::STRD_PRE: 1139 case ARM::STRD_POST: 1140 case ARM::LDRD: 1141 case ARM::LDRD_PRE: 1142 case ARM::LDRD_POST: 1143 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) 1144 return false; 1145 break; 1146 default: 1147 break; 1148 } 1149 1150 if (writeback) { 1151 // On loads, the writeback operand comes after Rt. 1152 switch (Inst.getOpcode()) { 1153 case ARM::LDRD: 1154 case ARM::LDRD_PRE: 1155 case ARM::LDRD_POST: 1156 case ARM::LDRH: 1157 case ARM::LDRH_PRE: 1158 case ARM::LDRH_POST: 1159 case ARM::LDRSH: 1160 case ARM::LDRSH_PRE: 1161 case ARM::LDRSH_POST: 1162 case ARM::LDRSB: 1163 case ARM::LDRSB_PRE: 1164 case ARM::LDRSB_POST: 1165 case ARM::LDRHTr: 1166 case ARM::LDRSBTr: 1167 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1168 return false; 1169 break; 1170 default: 1171 break; 1172 } 1173 } 1174 1175 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1176 return false; 1177 1178 if (type) { 1179 Inst.addOperand(MCOperand::CreateReg(0)); 1180 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1181 } else { 1182 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1183 return false; 1184 Inst.addOperand(MCOperand::CreateImm(U)); 1185 } 1186 1187 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1188 1189 return true; 1190 } 1191 1192 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, 1193 uint64_t Address, const void *Decoder) { 1194 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1195 unsigned mode = fieldFromInstruction32(Insn, 23, 2); 1196 1197 switch (mode) { 1198 case 0: 1199 mode = ARM_AM::da; 1200 break; 1201 case 1: 1202 mode = ARM_AM::ia; 1203 break; 1204 case 2: 1205 mode = ARM_AM::db; 1206 break; 1207 case 3: 1208 mode = ARM_AM::ib; 1209 break; 1210 } 1211 1212 Inst.addOperand(MCOperand::CreateImm(mode)); 1213 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1214 1215 return true; 1216 } 1217 1218 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, 1219 unsigned Insn, 1220 uint64_t Address, const void *Decoder) { 1221 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1222 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1223 unsigned reglist = fieldFromInstruction32(Insn, 0, 16); 1224 1225 if (pred == 0xF) { 1226 switch (Inst.getOpcode()) { 1227 case ARM::STMDA: 1228 Inst.setOpcode(ARM::RFEDA); 1229 break; 1230 case ARM::STMDA_UPD: 1231 Inst.setOpcode(ARM::RFEDA_UPD); 1232 break; 1233 case ARM::STMDB: 1234 Inst.setOpcode(ARM::RFEDB); 1235 break; 1236 case ARM::STMDB_UPD: 1237 Inst.setOpcode(ARM::RFEDB_UPD); 1238 break; 1239 case ARM::STMIA: 1240 Inst.setOpcode(ARM::RFEIA); 1241 break; 1242 case ARM::STMIA_UPD: 1243 Inst.setOpcode(ARM::RFEIA_UPD); 1244 break; 1245 case ARM::STMIB: 1246 Inst.setOpcode(ARM::RFEIB); 1247 break; 1248 case ARM::STMIB_UPD: 1249 Inst.setOpcode(ARM::RFEIB_UPD); 1250 break; 1251 } 1252 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1253 } 1254 1255 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 1256 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied 1257 !DecodePredicateOperand(Inst, pred, Address, Decoder) || 1258 !DecodeRegListOperand(Inst, reglist, Address, Decoder)) 1259 return false; 1260 1261 return true; 1262 } 1263 1264 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, 1265 uint64_t Address, const void *Decoder) { 1266 unsigned imod = fieldFromInstruction32(Insn, 18, 2); 1267 unsigned M = fieldFromInstruction32(Insn, 17, 1); 1268 unsigned iflags = fieldFromInstruction32(Insn, 6, 3); 1269 unsigned mode = fieldFromInstruction32(Insn, 0, 5); 1270 1271 // imod == '01' --> UNPREDICTABLE 1272 if (imod == 1) return false; 1273 1274 if (M && mode && imod && iflags) { 1275 Inst.setOpcode(ARM::CPS3p); 1276 Inst.addOperand(MCOperand::CreateImm(imod)); 1277 Inst.addOperand(MCOperand::CreateImm(iflags)); 1278 Inst.addOperand(MCOperand::CreateImm(mode)); 1279 return true; 1280 } else if (!mode && !M) { 1281 Inst.setOpcode(ARM::CPS2p); 1282 Inst.addOperand(MCOperand::CreateImm(imod)); 1283 Inst.addOperand(MCOperand::CreateImm(iflags)); 1284 return true; 1285 } else if (!imod && !iflags && M) { 1286 Inst.setOpcode(ARM::CPS1p); 1287 Inst.addOperand(MCOperand::CreateImm(mode)); 1288 return true; 1289 } 1290 1291 return false; 1292 } 1293 1294 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, 1295 uint64_t Address, const void *Decoder) { 1296 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); 1297 unsigned Rn = fieldFromInstruction32(Insn, 0, 4); 1298 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); 1299 unsigned Ra = fieldFromInstruction32(Insn, 12, 4); 1300 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1301 1302 if (pred == 0xF) 1303 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1304 1305 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) || 1306 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) || 1307 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) || 1308 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)) 1309 return false; 1310 1311 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1312 1313 return true; 1314 } 1315 1316 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, 1317 uint64_t Address, const void *Decoder) { 1318 unsigned add = fieldFromInstruction32(Val, 12, 1); 1319 unsigned imm = fieldFromInstruction32(Val, 0, 12); 1320 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 1321 1322 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1323 return false; 1324 1325 if (!add) imm *= -1; 1326 if (imm == 0 && !add) imm = INT32_MIN; 1327 Inst.addOperand(MCOperand::CreateImm(imm)); 1328 1329 return true; 1330 } 1331 1332 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, 1333 uint64_t Address, const void *Decoder) { 1334 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 1335 unsigned U = fieldFromInstruction32(Val, 8, 1); 1336 unsigned imm = fieldFromInstruction32(Val, 0, 8); 1337 1338 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 1339 return false; 1340 1341 if (U) 1342 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 1343 else 1344 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 1345 1346 return true; 1347 } 1348 1349 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val, 1350 uint64_t Address, const void *Decoder) { 1351 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 1352 } 1353 1354 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, 1355 uint64_t Address, const void *Decoder) { 1356 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 1357 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2; 1358 1359 if (pred == 0xF) { 1360 Inst.setOpcode(ARM::BLXi); 1361 imm |= fieldFromInstruction32(Insn, 24, 1) << 1; 1362 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1363 return true; 1364 } 1365 1366 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 1367 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 1368 1369 return true; 1370 } 1371 1372 1373 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val, 1374 uint64_t Address, const void *Decoder) { 1375 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 1376 return true; 1377 } 1378 1379 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val, 1380 uint64_t Address, const void *Decoder) { 1381 unsigned Rm = fieldFromInstruction32(Val, 0, 4); 1382 unsigned align = fieldFromInstruction32(Val, 4, 2); 1383 1384 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1385 return false; 1386 if (!align) 1387 Inst.addOperand(MCOperand::CreateImm(0)); 1388 else 1389 Inst.addOperand(MCOperand::CreateImm(4 << align)); 1390 1391 return true; 1392 } 1393 1394 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, 1395 uint64_t Address, const void *Decoder) { 1396 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1397 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1398 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1399 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1400 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1401 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1402 1403 // First output register 1404 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1405 1406 // Second output register 1407 switch (Inst.getOpcode()) { 1408 case ARM::VLD1q8: 1409 case ARM::VLD1q16: 1410 case ARM::VLD1q32: 1411 case ARM::VLD1q64: 1412 case ARM::VLD1q8_UPD: 1413 case ARM::VLD1q16_UPD: 1414 case ARM::VLD1q32_UPD: 1415 case ARM::VLD1q64_UPD: 1416 case ARM::VLD1d8T: 1417 case ARM::VLD1d16T: 1418 case ARM::VLD1d32T: 1419 case ARM::VLD1d64T: 1420 case ARM::VLD1d8T_UPD: 1421 case ARM::VLD1d16T_UPD: 1422 case ARM::VLD1d32T_UPD: 1423 case ARM::VLD1d64T_UPD: 1424 case ARM::VLD1d8Q: 1425 case ARM::VLD1d16Q: 1426 case ARM::VLD1d32Q: 1427 case ARM::VLD1d64Q: 1428 case ARM::VLD1d8Q_UPD: 1429 case ARM::VLD1d16Q_UPD: 1430 case ARM::VLD1d32Q_UPD: 1431 case ARM::VLD1d64Q_UPD: 1432 case ARM::VLD2d8: 1433 case ARM::VLD2d16: 1434 case ARM::VLD2d32: 1435 case ARM::VLD2d8_UPD: 1436 case ARM::VLD2d16_UPD: 1437 case ARM::VLD2d32_UPD: 1438 case ARM::VLD2q8: 1439 case ARM::VLD2q16: 1440 case ARM::VLD2q32: 1441 case ARM::VLD2q8_UPD: 1442 case ARM::VLD2q16_UPD: 1443 case ARM::VLD2q32_UPD: 1444 case ARM::VLD3d8: 1445 case ARM::VLD3d16: 1446 case ARM::VLD3d32: 1447 case ARM::VLD3d8_UPD: 1448 case ARM::VLD3d16_UPD: 1449 case ARM::VLD3d32_UPD: 1450 case ARM::VLD4d8: 1451 case ARM::VLD4d16: 1452 case ARM::VLD4d32: 1453 case ARM::VLD4d8_UPD: 1454 case ARM::VLD4d16_UPD: 1455 case ARM::VLD4d32_UPD: 1456 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1457 break; 1458 case ARM::VLD2b8: 1459 case ARM::VLD2b16: 1460 case ARM::VLD2b32: 1461 case ARM::VLD2b8_UPD: 1462 case ARM::VLD2b16_UPD: 1463 case ARM::VLD2b32_UPD: 1464 case ARM::VLD3q8: 1465 case ARM::VLD3q16: 1466 case ARM::VLD3q32: 1467 case ARM::VLD3q8_UPD: 1468 case ARM::VLD3q16_UPD: 1469 case ARM::VLD3q32_UPD: 1470 case ARM::VLD4q8: 1471 case ARM::VLD4q16: 1472 case ARM::VLD4q32: 1473 case ARM::VLD4q8_UPD: 1474 case ARM::VLD4q16_UPD: 1475 case ARM::VLD4q32_UPD: 1476 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1477 default: 1478 break; 1479 } 1480 1481 // Third output register 1482 switch(Inst.getOpcode()) { 1483 case ARM::VLD1d8T: 1484 case ARM::VLD1d16T: 1485 case ARM::VLD1d32T: 1486 case ARM::VLD1d64T: 1487 case ARM::VLD1d8T_UPD: 1488 case ARM::VLD1d16T_UPD: 1489 case ARM::VLD1d32T_UPD: 1490 case ARM::VLD1d64T_UPD: 1491 case ARM::VLD1d8Q: 1492 case ARM::VLD1d16Q: 1493 case ARM::VLD1d32Q: 1494 case ARM::VLD1d64Q: 1495 case ARM::VLD1d8Q_UPD: 1496 case ARM::VLD1d16Q_UPD: 1497 case ARM::VLD1d32Q_UPD: 1498 case ARM::VLD1d64Q_UPD: 1499 case ARM::VLD2q8: 1500 case ARM::VLD2q16: 1501 case ARM::VLD2q32: 1502 case ARM::VLD2q8_UPD: 1503 case ARM::VLD2q16_UPD: 1504 case ARM::VLD2q32_UPD: 1505 case ARM::VLD3d8: 1506 case ARM::VLD3d16: 1507 case ARM::VLD3d32: 1508 case ARM::VLD3d8_UPD: 1509 case ARM::VLD3d16_UPD: 1510 case ARM::VLD3d32_UPD: 1511 case ARM::VLD4d8: 1512 case ARM::VLD4d16: 1513 case ARM::VLD4d32: 1514 case ARM::VLD4d8_UPD: 1515 case ARM::VLD4d16_UPD: 1516 case ARM::VLD4d32_UPD: 1517 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1518 break; 1519 case ARM::VLD3q8: 1520 case ARM::VLD3q16: 1521 case ARM::VLD3q32: 1522 case ARM::VLD3q8_UPD: 1523 case ARM::VLD3q16_UPD: 1524 case ARM::VLD3q32_UPD: 1525 case ARM::VLD4q8: 1526 case ARM::VLD4q16: 1527 case ARM::VLD4q32: 1528 case ARM::VLD4q8_UPD: 1529 case ARM::VLD4q16_UPD: 1530 case ARM::VLD4q32_UPD: 1531 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1532 break; 1533 default: 1534 break; 1535 } 1536 1537 // Fourth output register 1538 switch (Inst.getOpcode()) { 1539 case ARM::VLD1d8Q: 1540 case ARM::VLD1d16Q: 1541 case ARM::VLD1d32Q: 1542 case ARM::VLD1d64Q: 1543 case ARM::VLD1d8Q_UPD: 1544 case ARM::VLD1d16Q_UPD: 1545 case ARM::VLD1d32Q_UPD: 1546 case ARM::VLD1d64Q_UPD: 1547 case ARM::VLD2q8: 1548 case ARM::VLD2q16: 1549 case ARM::VLD2q32: 1550 case ARM::VLD2q8_UPD: 1551 case ARM::VLD2q16_UPD: 1552 case ARM::VLD2q32_UPD: 1553 case ARM::VLD4d8: 1554 case ARM::VLD4d16: 1555 case ARM::VLD4d32: 1556 case ARM::VLD4d8_UPD: 1557 case ARM::VLD4d16_UPD: 1558 case ARM::VLD4d32_UPD: 1559 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1560 break; 1561 case ARM::VLD4q8: 1562 case ARM::VLD4q16: 1563 case ARM::VLD4q32: 1564 case ARM::VLD4q8_UPD: 1565 case ARM::VLD4q16_UPD: 1566 case ARM::VLD4q32_UPD: 1567 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1568 break; 1569 default: 1570 break; 1571 } 1572 1573 // Writeback operand 1574 switch (Inst.getOpcode()) { 1575 case ARM::VLD1d8_UPD: 1576 case ARM::VLD1d16_UPD: 1577 case ARM::VLD1d32_UPD: 1578 case ARM::VLD1d64_UPD: 1579 case ARM::VLD1q8_UPD: 1580 case ARM::VLD1q16_UPD: 1581 case ARM::VLD1q32_UPD: 1582 case ARM::VLD1q64_UPD: 1583 case ARM::VLD1d8T_UPD: 1584 case ARM::VLD1d16T_UPD: 1585 case ARM::VLD1d32T_UPD: 1586 case ARM::VLD1d64T_UPD: 1587 case ARM::VLD1d8Q_UPD: 1588 case ARM::VLD1d16Q_UPD: 1589 case ARM::VLD1d32Q_UPD: 1590 case ARM::VLD1d64Q_UPD: 1591 case ARM::VLD2d8_UPD: 1592 case ARM::VLD2d16_UPD: 1593 case ARM::VLD2d32_UPD: 1594 case ARM::VLD2q8_UPD: 1595 case ARM::VLD2q16_UPD: 1596 case ARM::VLD2q32_UPD: 1597 case ARM::VLD2b8_UPD: 1598 case ARM::VLD2b16_UPD: 1599 case ARM::VLD2b32_UPD: 1600 case ARM::VLD3d8_UPD: 1601 case ARM::VLD3d16_UPD: 1602 case ARM::VLD3d32_UPD: 1603 case ARM::VLD3q8_UPD: 1604 case ARM::VLD3q16_UPD: 1605 case ARM::VLD3q32_UPD: 1606 case ARM::VLD4d8_UPD: 1607 case ARM::VLD4d16_UPD: 1608 case ARM::VLD4d32_UPD: 1609 case ARM::VLD4q8_UPD: 1610 case ARM::VLD4q16_UPD: 1611 case ARM::VLD4q32_UPD: 1612 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false; 1613 break; 1614 default: 1615 break; 1616 } 1617 1618 // AddrMode6 Base (register+alignment) 1619 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1620 1621 // AddrMode6 Offset (register) 1622 if (Rm == 0xD) 1623 Inst.addOperand(MCOperand::CreateReg(0)); 1624 else if (Rm != 0xF) { 1625 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 1626 return false; 1627 } 1628 1629 return true; 1630 } 1631 1632 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, 1633 uint64_t Address, const void *Decoder) { 1634 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1635 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1636 unsigned wb = fieldFromInstruction32(Insn, 16, 4); 1637 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1638 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4; 1639 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1640 1641 // Writeback Operand 1642 switch (Inst.getOpcode()) { 1643 case ARM::VST1d8_UPD: 1644 case ARM::VST1d16_UPD: 1645 case ARM::VST1d32_UPD: 1646 case ARM::VST1d64_UPD: 1647 case ARM::VST1q8_UPD: 1648 case ARM::VST1q16_UPD: 1649 case ARM::VST1q32_UPD: 1650 case ARM::VST1q64_UPD: 1651 case ARM::VST1d8T_UPD: 1652 case ARM::VST1d16T_UPD: 1653 case ARM::VST1d32T_UPD: 1654 case ARM::VST1d64T_UPD: 1655 case ARM::VST1d8Q_UPD: 1656 case ARM::VST1d16Q_UPD: 1657 case ARM::VST1d32Q_UPD: 1658 case ARM::VST1d64Q_UPD: 1659 case ARM::VST2d8_UPD: 1660 case ARM::VST2d16_UPD: 1661 case ARM::VST2d32_UPD: 1662 case ARM::VST2q8_UPD: 1663 case ARM::VST2q16_UPD: 1664 case ARM::VST2q32_UPD: 1665 case ARM::VST2b8_UPD: 1666 case ARM::VST2b16_UPD: 1667 case ARM::VST2b32_UPD: 1668 case ARM::VST3d8_UPD: 1669 case ARM::VST3d16_UPD: 1670 case ARM::VST3d32_UPD: 1671 case ARM::VST3q8_UPD: 1672 case ARM::VST3q16_UPD: 1673 case ARM::VST3q32_UPD: 1674 case ARM::VST4d8_UPD: 1675 case ARM::VST4d16_UPD: 1676 case ARM::VST4d32_UPD: 1677 case ARM::VST4q8_UPD: 1678 case ARM::VST4q16_UPD: 1679 case ARM::VST4q32_UPD: 1680 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) 1681 return false; 1682 break; 1683 default: 1684 break; 1685 } 1686 1687 // AddrMode6 Base (register+alignment) 1688 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false; 1689 1690 // AddrMode6 Offset (register) 1691 if (Rm == 0xD) 1692 Inst.addOperand(MCOperand::CreateReg(0)); 1693 else if (Rm != 0xF) { 1694 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1695 } 1696 1697 // First input register 1698 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1699 1700 // Second input register 1701 switch (Inst.getOpcode()) { 1702 case ARM::VST1q8: 1703 case ARM::VST1q16: 1704 case ARM::VST1q32: 1705 case ARM::VST1q64: 1706 case ARM::VST1q8_UPD: 1707 case ARM::VST1q16_UPD: 1708 case ARM::VST1q32_UPD: 1709 case ARM::VST1q64_UPD: 1710 case ARM::VST1d8T: 1711 case ARM::VST1d16T: 1712 case ARM::VST1d32T: 1713 case ARM::VST1d64T: 1714 case ARM::VST1d8T_UPD: 1715 case ARM::VST1d16T_UPD: 1716 case ARM::VST1d32T_UPD: 1717 case ARM::VST1d64T_UPD: 1718 case ARM::VST1d8Q: 1719 case ARM::VST1d16Q: 1720 case ARM::VST1d32Q: 1721 case ARM::VST1d64Q: 1722 case ARM::VST1d8Q_UPD: 1723 case ARM::VST1d16Q_UPD: 1724 case ARM::VST1d32Q_UPD: 1725 case ARM::VST1d64Q_UPD: 1726 case ARM::VST2d8: 1727 case ARM::VST2d16: 1728 case ARM::VST2d32: 1729 case ARM::VST2d8_UPD: 1730 case ARM::VST2d16_UPD: 1731 case ARM::VST2d32_UPD: 1732 case ARM::VST2q8: 1733 case ARM::VST2q16: 1734 case ARM::VST2q32: 1735 case ARM::VST2q8_UPD: 1736 case ARM::VST2q16_UPD: 1737 case ARM::VST2q32_UPD: 1738 case ARM::VST3d8: 1739 case ARM::VST3d16: 1740 case ARM::VST3d32: 1741 case ARM::VST3d8_UPD: 1742 case ARM::VST3d16_UPD: 1743 case ARM::VST3d32_UPD: 1744 case ARM::VST4d8: 1745 case ARM::VST4d16: 1746 case ARM::VST4d32: 1747 case ARM::VST4d8_UPD: 1748 case ARM::VST4d16_UPD: 1749 case ARM::VST4d32_UPD: 1750 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1751 break; 1752 case ARM::VST2b8: 1753 case ARM::VST2b16: 1754 case ARM::VST2b32: 1755 case ARM::VST2b8_UPD: 1756 case ARM::VST2b16_UPD: 1757 case ARM::VST2b32_UPD: 1758 case ARM::VST3q8: 1759 case ARM::VST3q16: 1760 case ARM::VST3q32: 1761 case ARM::VST3q8_UPD: 1762 case ARM::VST3q16_UPD: 1763 case ARM::VST3q32_UPD: 1764 case ARM::VST4q8: 1765 case ARM::VST4q16: 1766 case ARM::VST4q32: 1767 case ARM::VST4q8_UPD: 1768 case ARM::VST4q16_UPD: 1769 case ARM::VST4q32_UPD: 1770 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1771 break; 1772 default: 1773 break; 1774 } 1775 1776 // Third input register 1777 switch (Inst.getOpcode()) { 1778 case ARM::VST1d8T: 1779 case ARM::VST1d16T: 1780 case ARM::VST1d32T: 1781 case ARM::VST1d64T: 1782 case ARM::VST1d8T_UPD: 1783 case ARM::VST1d16T_UPD: 1784 case ARM::VST1d32T_UPD: 1785 case ARM::VST1d64T_UPD: 1786 case ARM::VST1d8Q: 1787 case ARM::VST1d16Q: 1788 case ARM::VST1d32Q: 1789 case ARM::VST1d64Q: 1790 case ARM::VST1d8Q_UPD: 1791 case ARM::VST1d16Q_UPD: 1792 case ARM::VST1d32Q_UPD: 1793 case ARM::VST1d64Q_UPD: 1794 case ARM::VST2q8: 1795 case ARM::VST2q16: 1796 case ARM::VST2q32: 1797 case ARM::VST2q8_UPD: 1798 case ARM::VST2q16_UPD: 1799 case ARM::VST2q32_UPD: 1800 case ARM::VST3d8: 1801 case ARM::VST3d16: 1802 case ARM::VST3d32: 1803 case ARM::VST3d8_UPD: 1804 case ARM::VST3d16_UPD: 1805 case ARM::VST3d32_UPD: 1806 case ARM::VST4d8: 1807 case ARM::VST4d16: 1808 case ARM::VST4d32: 1809 case ARM::VST4d8_UPD: 1810 case ARM::VST4d16_UPD: 1811 case ARM::VST4d32_UPD: 1812 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false; 1813 break; 1814 case ARM::VST3q8: 1815 case ARM::VST3q16: 1816 case ARM::VST3q32: 1817 case ARM::VST3q8_UPD: 1818 case ARM::VST3q16_UPD: 1819 case ARM::VST3q32_UPD: 1820 case ARM::VST4q8: 1821 case ARM::VST4q16: 1822 case ARM::VST4q32: 1823 case ARM::VST4q8_UPD: 1824 case ARM::VST4q16_UPD: 1825 case ARM::VST4q32_UPD: 1826 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false; 1827 break; 1828 default: 1829 break; 1830 } 1831 1832 // Fourth input register 1833 switch (Inst.getOpcode()) { 1834 case ARM::VST1d8Q: 1835 case ARM::VST1d16Q: 1836 case ARM::VST1d32Q: 1837 case ARM::VST1d64Q: 1838 case ARM::VST1d8Q_UPD: 1839 case ARM::VST1d16Q_UPD: 1840 case ARM::VST1d32Q_UPD: 1841 case ARM::VST1d64Q_UPD: 1842 case ARM::VST2q8: 1843 case ARM::VST2q16: 1844 case ARM::VST2q32: 1845 case ARM::VST2q8_UPD: 1846 case ARM::VST2q16_UPD: 1847 case ARM::VST2q32_UPD: 1848 case ARM::VST4d8: 1849 case ARM::VST4d16: 1850 case ARM::VST4d32: 1851 case ARM::VST4d8_UPD: 1852 case ARM::VST4d16_UPD: 1853 case ARM::VST4d32_UPD: 1854 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false; 1855 break; 1856 case ARM::VST4q8: 1857 case ARM::VST4q16: 1858 case ARM::VST4q32: 1859 case ARM::VST4q8_UPD: 1860 case ARM::VST4q16_UPD: 1861 case ARM::VST4q32_UPD: 1862 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false; 1863 break; 1864 default: 1865 break; 1866 } 1867 1868 return true; 1869 } 1870 1871 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1872 uint64_t Address, const void *Decoder) { 1873 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1874 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1875 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1876 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1877 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1878 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1879 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1; 1880 1881 align *= (1 << size); 1882 1883 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1884 if (regs == 2) { 1885 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false; 1886 } 1887 if (Rm == 0xD) { 1888 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1889 } 1890 1891 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1892 Inst.addOperand(MCOperand::CreateImm(align)); 1893 1894 if (Rm == 0xD) 1895 Inst.addOperand(MCOperand::CreateReg(0)); 1896 else if (Rm != 0xF) { 1897 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1898 } 1899 1900 return true; 1901 } 1902 1903 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1904 uint64_t Address, const void *Decoder) { 1905 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1906 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1907 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1908 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1909 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1910 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2); 1911 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1912 align *= 2*size; 1913 1914 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 1915 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false; 1916 if (Rm == 0xD) { 1917 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1918 } 1919 1920 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1921 Inst.addOperand(MCOperand::CreateImm(align)); 1922 1923 if (Rm == 0xD) 1924 Inst.addOperand(MCOperand::CreateReg(0)); 1925 else if (Rm != 0xF) { 1926 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1927 } 1928 1929 return true; 1930 } 1931 1932 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1933 uint64_t Address, const void *Decoder) { 1934 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1935 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1936 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1937 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1938 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1939 1940 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1941 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1942 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)) 1943 return false; 1944 if (Rm == 0xD) { 1945 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1946 } 1947 1948 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1949 Inst.addOperand(MCOperand::CreateImm(0)); 1950 1951 if (Rm == 0xD) 1952 Inst.addOperand(MCOperand::CreateReg(0)); 1953 else if (Rm != 0xF) { 1954 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1955 } 1956 1957 return true; 1958 } 1959 1960 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, 1961 uint64_t Address, const void *Decoder) { 1962 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 1963 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 1964 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 1965 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 1966 unsigned size = fieldFromInstruction32(Insn, 6, 2); 1967 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1; 1968 unsigned align = fieldFromInstruction32(Insn, 4, 1); 1969 1970 if (size == 0x3) { 1971 size = 4; 1972 align = 16; 1973 } else { 1974 if (size == 2) { 1975 size = 1 << size; 1976 align *= 8; 1977 } else { 1978 size = 1 << size; 1979 align *= 4*size; 1980 } 1981 } 1982 1983 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) || 1984 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) || 1985 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) || 1986 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)) 1987 return false; 1988 if (Rm == 0xD) { 1989 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1990 } 1991 1992 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 1993 Inst.addOperand(MCOperand::CreateImm(align)); 1994 1995 if (Rm == 0xD) 1996 Inst.addOperand(MCOperand::CreateReg(0)); 1997 else if (Rm != 0xF) { 1998 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 1999 } 2000 2001 return true; 2002 } 2003 2004 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, 2005 uint64_t Address, const void *Decoder) { 2006 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2007 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2008 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2009 imm |= fieldFromInstruction32(Insn, 16, 3) << 4; 2010 imm |= fieldFromInstruction32(Insn, 24, 1) << 7; 2011 imm |= fieldFromInstruction32(Insn, 8, 4) << 8; 2012 imm |= fieldFromInstruction32(Insn, 5, 1) << 12; 2013 unsigned Q = fieldFromInstruction32(Insn, 6, 1); 2014 2015 if (Q) { 2016 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2017 } else { 2018 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2019 } 2020 2021 Inst.addOperand(MCOperand::CreateImm(imm)); 2022 2023 switch (Inst.getOpcode()) { 2024 case ARM::VORRiv4i16: 2025 case ARM::VORRiv2i32: 2026 case ARM::VBICiv4i16: 2027 case ARM::VBICiv2i32: 2028 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2029 break; 2030 case ARM::VORRiv8i16: 2031 case ARM::VORRiv4i32: 2032 case ARM::VBICiv8i16: 2033 case ARM::VBICiv4i32: 2034 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2035 break; 2036 default: 2037 break; 2038 } 2039 2040 return true; 2041 } 2042 2043 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, 2044 uint64_t Address, const void *Decoder) { 2045 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2046 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2047 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2048 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2049 unsigned size = fieldFromInstruction32(Insn, 18, 2); 2050 2051 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2052 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2053 Inst.addOperand(MCOperand::CreateImm(8 << size)); 2054 2055 return true; 2056 } 2057 2058 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val, 2059 uint64_t Address, const void *Decoder) { 2060 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 2061 return true; 2062 } 2063 2064 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val, 2065 uint64_t Address, const void *Decoder) { 2066 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 2067 return true; 2068 } 2069 2070 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val, 2071 uint64_t Address, const void *Decoder) { 2072 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 2073 return true; 2074 } 2075 2076 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val, 2077 uint64_t Address, const void *Decoder) { 2078 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 2079 return true; 2080 } 2081 2082 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, 2083 uint64_t Address, const void *Decoder) { 2084 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2085 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2086 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2087 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4; 2088 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2089 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4; 2090 unsigned op = fieldFromInstruction32(Insn, 6, 1); 2091 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1; 2092 2093 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2094 if (op) { 2095 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback 2096 } 2097 2098 for (unsigned i = 0; i < length; ++i) { 2099 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false; 2100 } 2101 2102 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2103 2104 return true; 2105 } 2106 2107 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val, 2108 uint64_t Address, const void *Decoder) { 2109 // The immediate needs to be a fully instantiated float. However, the 2110 // auto-generated decoder is only able to fill in some of the bits 2111 // necessary. For instance, the 'b' bit is replicated multiple times, 2112 // and is even present in inverted form in one bit. We do a little 2113 // binary parsing here to fill in those missing bits, and then 2114 // reinterpret it all as a float. 2115 union { 2116 uint32_t integer; 2117 float fp; 2118 } fp_conv; 2119 2120 fp_conv.integer = Val; 2121 uint32_t b = fieldFromInstruction32(Val, 25, 1); 2122 fp_conv.integer |= b << 26; 2123 fp_conv.integer |= b << 27; 2124 fp_conv.integer |= b << 28; 2125 fp_conv.integer |= b << 29; 2126 fp_conv.integer |= (~b & 0x1) << 30; 2127 2128 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp)); 2129 return true; 2130 } 2131 2132 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, 2133 uint64_t Address, const void *Decoder) { 2134 unsigned dst = fieldFromInstruction16(Insn, 8, 3); 2135 unsigned imm = fieldFromInstruction16(Insn, 0, 8); 2136 2137 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false; 2138 2139 if (Inst.getOpcode() == ARM::tADR) 2140 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2141 else if (Inst.getOpcode() == ARM::tADDrSPi) 2142 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2143 else 2144 return false; 2145 2146 Inst.addOperand(MCOperand::CreateImm(imm)); 2147 return true; 2148 } 2149 2150 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val, 2151 uint64_t Address, const void *Decoder) { 2152 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 2153 return true; 2154 } 2155 2156 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val, 2157 uint64_t Address, const void *Decoder) { 2158 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 2159 return true; 2160 } 2161 2162 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val, 2163 uint64_t Address, const void *Decoder) { 2164 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1))); 2165 return true; 2166 } 2167 2168 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val, 2169 uint64_t Address, const void *Decoder) { 2170 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2171 unsigned Rm = fieldFromInstruction32(Val, 3, 3); 2172 2173 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) || 2174 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)) 2175 return false; 2176 2177 return true; 2178 } 2179 2180 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val, 2181 uint64_t Address, const void *Decoder) { 2182 unsigned Rn = fieldFromInstruction32(Val, 0, 3); 2183 unsigned imm = fieldFromInstruction32(Val, 3, 5); 2184 2185 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2186 Inst.addOperand(MCOperand::CreateImm(imm)); 2187 2188 return true; 2189 } 2190 2191 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val, 2192 uint64_t Address, const void *Decoder) { 2193 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2194 2195 return true; 2196 } 2197 2198 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val, 2199 uint64_t Address, const void *Decoder) { 2200 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2201 Inst.addOperand(MCOperand::CreateImm(Val << 2)); 2202 2203 return true; 2204 } 2205 2206 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val, 2207 uint64_t Address, const void *Decoder) { 2208 unsigned Rn = fieldFromInstruction32(Val, 6, 4); 2209 unsigned Rm = fieldFromInstruction32(Val, 2, 4); 2210 unsigned imm = fieldFromInstruction32(Val, 0, 2); 2211 2212 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2213 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)) 2214 return false; 2215 Inst.addOperand(MCOperand::CreateImm(imm)); 2216 2217 return true; 2218 } 2219 2220 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, 2221 uint64_t Address, const void *Decoder) { 2222 if (Inst.getOpcode() != ARM::t2PLDs) { 2223 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2224 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2225 } 2226 2227 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2228 if (Rn == 0xF) { 2229 switch (Inst.getOpcode()) { 2230 case ARM::t2LDRBs: 2231 Inst.setOpcode(ARM::t2LDRBpci); 2232 break; 2233 case ARM::t2LDRHs: 2234 Inst.setOpcode(ARM::t2LDRHpci); 2235 break; 2236 case ARM::t2LDRSHs: 2237 Inst.setOpcode(ARM::t2LDRSHpci); 2238 break; 2239 case ARM::t2LDRSBs: 2240 Inst.setOpcode(ARM::t2LDRSBpci); 2241 break; 2242 case ARM::t2PLDs: 2243 Inst.setOpcode(ARM::t2PLDi12); 2244 Inst.addOperand(MCOperand::CreateReg(ARM::PC)); 2245 break; 2246 default: 2247 return false; 2248 } 2249 2250 int imm = fieldFromInstruction32(Insn, 0, 12); 2251 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1; 2252 Inst.addOperand(MCOperand::CreateImm(imm)); 2253 2254 return true; 2255 } 2256 2257 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2); 2258 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2; 2259 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6; 2260 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder); 2261 2262 return true; 2263 } 2264 2265 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val, 2266 uint64_t Address, const void *Decoder) { 2267 int imm = Val & 0xFF; 2268 if (!(Val & 0x100)) imm *= -1; 2269 Inst.addOperand(MCOperand::CreateImm(imm << 2)); 2270 2271 return true; 2272 } 2273 2274 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val, 2275 uint64_t Address, const void *Decoder) { 2276 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2277 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2278 2279 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2280 !DecodeT2Imm8S4(Inst, imm, Address, Decoder)) 2281 return false; 2282 2283 return true; 2284 } 2285 2286 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val, 2287 uint64_t Address, const void *Decoder) { 2288 int imm = Val & 0xFF; 2289 if (!(Val & 0x100)) imm *= -1; 2290 Inst.addOperand(MCOperand::CreateImm(imm)); 2291 2292 return true; 2293 } 2294 2295 2296 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val, 2297 uint64_t Address, const void *Decoder) { 2298 unsigned Rn = fieldFromInstruction32(Val, 9, 4); 2299 unsigned imm = fieldFromInstruction32(Val, 0, 9); 2300 2301 // Some instructions always use an additive offset. 2302 switch (Inst.getOpcode()) { 2303 case ARM::t2LDRT: 2304 case ARM::t2LDRBT: 2305 case ARM::t2LDRHT: 2306 case ARM::t2LDRSBT: 2307 case ARM::t2LDRSHT: 2308 imm |= 0x100; 2309 break; 2310 default: 2311 break; 2312 } 2313 2314 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || 2315 !DecodeT2Imm8(Inst, imm, Address, Decoder)) 2316 return false; 2317 2318 return true; 2319 } 2320 2321 2322 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val, 2323 uint64_t Address, const void *Decoder) { 2324 unsigned Rn = fieldFromInstruction32(Val, 13, 4); 2325 unsigned imm = fieldFromInstruction32(Val, 0, 12); 2326 2327 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2328 Inst.addOperand(MCOperand::CreateImm(imm)); 2329 2330 return true; 2331 } 2332 2333 2334 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, 2335 uint64_t Address, const void *Decoder) { 2336 unsigned imm = fieldFromInstruction16(Insn, 0, 7); 2337 2338 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2339 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2340 Inst.addOperand(MCOperand::CreateImm(imm)); 2341 2342 return true; 2343 } 2344 2345 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, 2346 uint64_t Address, const void *Decoder) { 2347 if (Inst.getOpcode() == ARM::tADDrSP) { 2348 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3); 2349 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3; 2350 2351 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2352 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2353 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false; 2354 } else if (Inst.getOpcode() == ARM::tADDspr) { 2355 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); 2356 2357 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2358 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 2359 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2360 } 2361 2362 return true; 2363 } 2364 2365 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, 2366 uint64_t Address, const void *Decoder) { 2367 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2; 2368 unsigned flags = fieldFromInstruction16(Insn, 0, 3); 2369 2370 Inst.addOperand(MCOperand::CreateImm(imod)); 2371 Inst.addOperand(MCOperand::CreateImm(flags)); 2372 2373 return true; 2374 } 2375 2376 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, 2377 uint64_t Address, const void *Decoder) { 2378 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2379 unsigned add = fieldFromInstruction32(Insn, 4, 1); 2380 2381 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false; 2382 Inst.addOperand(MCOperand::CreateImm(add)); 2383 2384 return true; 2385 } 2386 2387 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val, 2388 uint64_t Address, const void *Decoder) { 2389 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2390 return true; 2391 } 2392 2393 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val, 2394 uint64_t Address, const void *Decoder) { 2395 if (Val == 0xA || Val == 0xB) 2396 return false; 2397 2398 Inst.addOperand(MCOperand::CreateImm(Val)); 2399 return true; 2400 } 2401 2402 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val, 2403 uint64_t Address, const void *Decoder) { 2404 if (Val == 0) 2405 Inst.addOperand(MCOperand::CreateImm(32)); 2406 else 2407 Inst.addOperand(MCOperand::CreateImm(Val)); 2408 return true; 2409 } 2410 2411 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, 2412 uint64_t Address, const void *Decoder) { 2413 unsigned pred = fieldFromInstruction32(Insn, 22, 4); 2414 if (pred == 0xE || pred == 0xF) { 2415 unsigned opc = fieldFromInstruction32(Insn, 4, 2); 2416 switch (opc) { 2417 default: 2418 return false; 2419 case 0: 2420 Inst.setOpcode(ARM::t2DSB); 2421 break; 2422 case 1: 2423 Inst.setOpcode(ARM::t2DMB); 2424 break; 2425 case 2: 2426 Inst.setOpcode(ARM::t2ISB); 2427 return true; 2428 } 2429 2430 unsigned imm = fieldFromInstruction32(Insn, 0, 4); 2431 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 2432 } 2433 2434 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1; 2435 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19; 2436 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18; 2437 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12; 2438 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20; 2439 2440 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) || 2441 !DecodePredicateOperand(Inst, pred, Address, Decoder)) 2442 return false; 2443 2444 return true; 2445 } 2446 2447 // Decode a shifted immediate operand. These basically consist 2448 // of an 8-bit value, and a 4-bit directive that specifies either 2449 // a splat operation or a rotation. 2450 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val, 2451 uint64_t Address, const void *Decoder) { 2452 unsigned ctrl = fieldFromInstruction32(Val, 10, 2); 2453 if (ctrl == 0) { 2454 unsigned byte = fieldFromInstruction32(Val, 8, 2); 2455 unsigned imm = fieldFromInstruction32(Val, 0, 8); 2456 switch (byte) { 2457 case 0: 2458 Inst.addOperand(MCOperand::CreateImm(imm)); 2459 break; 2460 case 1: 2461 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 2462 break; 2463 case 2: 2464 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 2465 break; 2466 case 3: 2467 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 2468 (imm << 8) | imm)); 2469 break; 2470 } 2471 } else { 2472 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80; 2473 unsigned rot = fieldFromInstruction32(Val, 7, 5); 2474 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 2475 Inst.addOperand(MCOperand::CreateImm(imm)); 2476 } 2477 2478 return true; 2479 } 2480 2481 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val, 2482 uint64_t Address, const void *Decoder){ 2483 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 2484 return true; 2485 } 2486 2487 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val, 2488 uint64_t Address, const void *Decoder){ 2489 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1))); 2490 return true; 2491 } 2492 2493 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val, 2494 uint64_t Address, const void *Decoder) { 2495 switch (Val) { 2496 default: 2497 return false; 2498 case 0xF: // SY 2499 case 0xE: // ST 2500 case 0xB: // ISH 2501 case 0xA: // ISHST 2502 case 0x7: // NSH 2503 case 0x6: // NSHST 2504 case 0x3: // OSH 2505 case 0x2: // OSHST 2506 break; 2507 } 2508 2509 Inst.addOperand(MCOperand::CreateImm(Val)); 2510 return true; 2511 } 2512 2513 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val, 2514 uint64_t Address, const void *Decoder) { 2515 if (!Val) return false; 2516 Inst.addOperand(MCOperand::CreateImm(Val)); 2517 return true; 2518 } 2519 2520 static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, 2521 uint64_t Address, const void *Decoder) { 2522 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2523 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2524 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2525 2526 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2527 2528 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2529 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2530 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2531 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2532 2533 return true; 2534 } 2535 2536 2537 static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, 2538 uint64_t Address, const void *Decoder) { 2539 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2540 unsigned Rt = fieldFromInstruction32(Insn, 0, 4); 2541 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2542 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2543 2544 if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2545 2546 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false; 2547 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false; 2548 2549 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2550 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false; 2551 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2552 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2553 2554 return true; 2555 } 2556 2557 static bool DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, 2558 uint64_t Address, const void *Decoder) { 2559 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2560 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2561 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2562 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2563 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2564 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2565 2566 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2567 2568 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2569 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2570 if (!DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)) return false; 2571 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2572 2573 return true; 2574 } 2575 2576 static bool DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, 2577 uint64_t Address, const void *Decoder) { 2578 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2579 unsigned Rt = fieldFromInstruction32(Insn, 12, 4); 2580 unsigned imm = fieldFromInstruction32(Insn, 0, 12); 2581 imm |= fieldFromInstruction32(Insn, 16, 4) << 13; 2582 imm |= fieldFromInstruction32(Insn, 23, 1) << 12; 2583 unsigned pred = fieldFromInstruction32(Insn, 28, 4); 2584 2585 if (Rn == 0xF || Rn == Rt) return false; // UNPREDICTABLE 2586 2587 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2588 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false; 2589 if (!DecodeSORegMemOperand(Inst, imm, Address, Decoder)) return false; 2590 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; 2591 2592 return true; 2593 } 2594 2595 static bool DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, 2596 uint64_t Address, const void *Decoder) { 2597 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2598 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2599 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2600 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2601 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2602 2603 unsigned align = 0; 2604 unsigned index = 0; 2605 switch (size) { 2606 default: 2607 return false; 2608 case 0: 2609 if (fieldFromInstruction32(Insn, 4, 1)) 2610 return false; // UNDEFINED 2611 index = fieldFromInstruction32(Insn, 5, 3); 2612 break; 2613 case 1: 2614 if (fieldFromInstruction32(Insn, 5, 1)) 2615 return false; // UNDEFINED 2616 index = fieldFromInstruction32(Insn, 6, 2); 2617 if (fieldFromInstruction32(Insn, 4, 1)) 2618 align = 2; 2619 break; 2620 case 2: 2621 if (fieldFromInstruction32(Insn, 6, 1)) 2622 return false; // UNDEFINED 2623 index = fieldFromInstruction32(Insn, 7, 1); 2624 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2625 align = 4; 2626 } 2627 2628 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2629 if (Rm != 0xF) { // Writeback 2630 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2631 return false; 2632 } 2633 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2634 Inst.addOperand(MCOperand::CreateImm(align)); 2635 if (Rm != 0xF && Rm != 0xD) { 2636 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2637 return false; 2638 } 2639 2640 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2641 Inst.addOperand(MCOperand::CreateImm(index)); 2642 2643 return true; 2644 } 2645 2646 static bool DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, 2647 uint64_t Address, const void *Decoder) { 2648 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2649 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2650 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2651 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2652 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2653 2654 unsigned align = 0; 2655 unsigned index = 0; 2656 switch (size) { 2657 default: 2658 return false; 2659 case 0: 2660 if (fieldFromInstruction32(Insn, 4, 1)) 2661 return false; // UNDEFINED 2662 index = fieldFromInstruction32(Insn, 5, 3); 2663 break; 2664 case 1: 2665 if (fieldFromInstruction32(Insn, 5, 1)) 2666 return false; // UNDEFINED 2667 index = fieldFromInstruction32(Insn, 6, 2); 2668 if (fieldFromInstruction32(Insn, 4, 1)) 2669 align = 2; 2670 break; 2671 case 2: 2672 if (fieldFromInstruction32(Insn, 6, 1)) 2673 return false; // UNDEFINED 2674 index = fieldFromInstruction32(Insn, 7, 1); 2675 if (fieldFromInstruction32(Insn, 4, 2) != 0) 2676 align = 4; 2677 } 2678 2679 if (Rm != 0xF) { // Writeback 2680 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2681 return false; 2682 } 2683 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2684 Inst.addOperand(MCOperand::CreateImm(align)); 2685 if (Rm != 0xF && Rm != 0xD) { 2686 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2687 return false; 2688 } 2689 2690 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2691 Inst.addOperand(MCOperand::CreateImm(index)); 2692 2693 return true; 2694 } 2695 2696 2697 static bool DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, 2698 uint64_t Address, const void *Decoder) { 2699 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2700 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2701 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2702 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2703 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2704 2705 unsigned align = 0; 2706 unsigned index = 0; 2707 unsigned inc = 1; 2708 switch (size) { 2709 default: 2710 return false; 2711 case 0: 2712 index = fieldFromInstruction32(Insn, 5, 3); 2713 if (fieldFromInstruction32(Insn, 4, 1)) 2714 align = 2; 2715 break; 2716 case 1: 2717 index = fieldFromInstruction32(Insn, 6, 2); 2718 if (fieldFromInstruction32(Insn, 4, 1)) 2719 align = 4; 2720 if (fieldFromInstruction32(Insn, 5, 1)) 2721 inc = 2; 2722 break; 2723 case 2: 2724 if (fieldFromInstruction32(Insn, 5, 1)) 2725 return false; // UNDEFINED 2726 index = fieldFromInstruction32(Insn, 7, 1); 2727 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2728 align = 8; 2729 if (fieldFromInstruction32(Insn, 6, 1)) 2730 inc = 2; 2731 break; 2732 } 2733 2734 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2735 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2736 if (Rm != 0xF) { // Writeback 2737 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2738 return false; 2739 } 2740 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2741 Inst.addOperand(MCOperand::CreateImm(align)); 2742 if (Rm != 0xF && Rm != 0xD) { 2743 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2744 return false; 2745 } 2746 2747 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2748 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2749 Inst.addOperand(MCOperand::CreateImm(index)); 2750 2751 return true; 2752 } 2753 2754 static bool DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, 2755 uint64_t Address, const void *Decoder) { 2756 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2757 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2758 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2759 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2760 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2761 2762 unsigned align = 0; 2763 unsigned index = 0; 2764 unsigned inc = 1; 2765 switch (size) { 2766 default: 2767 return false; 2768 case 0: 2769 index = fieldFromInstruction32(Insn, 5, 3); 2770 if (fieldFromInstruction32(Insn, 4, 1)) 2771 align = 2; 2772 break; 2773 case 1: 2774 index = fieldFromInstruction32(Insn, 6, 2); 2775 if (fieldFromInstruction32(Insn, 4, 1)) 2776 align = 4; 2777 if (fieldFromInstruction32(Insn, 5, 1)) 2778 inc = 2; 2779 break; 2780 case 2: 2781 if (fieldFromInstruction32(Insn, 5, 1)) 2782 return false; // UNDEFINED 2783 index = fieldFromInstruction32(Insn, 7, 1); 2784 if (fieldFromInstruction32(Insn, 4, 1) != 0) 2785 align = 8; 2786 if (fieldFromInstruction32(Insn, 6, 1)) 2787 inc = 2; 2788 break; 2789 } 2790 2791 if (Rm != 0xF) { // Writeback 2792 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2793 return false; 2794 } 2795 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2796 Inst.addOperand(MCOperand::CreateImm(align)); 2797 if (Rm != 0xF && Rm != 0xD) { 2798 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2799 return false; 2800 } 2801 2802 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2803 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2804 Inst.addOperand(MCOperand::CreateImm(index)); 2805 2806 return true; 2807 } 2808 2809 2810 static bool DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, 2811 uint64_t Address, const void *Decoder) { 2812 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2813 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2814 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2815 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2816 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2817 2818 unsigned align = 0; 2819 unsigned index = 0; 2820 unsigned inc = 1; 2821 switch (size) { 2822 default: 2823 return false; 2824 case 0: 2825 if (fieldFromInstruction32(Insn, 4, 1)) 2826 return false; // UNDEFINED 2827 index = fieldFromInstruction32(Insn, 5, 3); 2828 break; 2829 case 1: 2830 if (fieldFromInstruction32(Insn, 4, 1)) 2831 return false; // UNDEFINED 2832 index = fieldFromInstruction32(Insn, 6, 2); 2833 if (fieldFromInstruction32(Insn, 5, 1)) 2834 inc = 2; 2835 break; 2836 case 2: 2837 if (fieldFromInstruction32(Insn, 4, 2)) 2838 return false; // UNDEFINED 2839 index = fieldFromInstruction32(Insn, 7, 1); 2840 if (fieldFromInstruction32(Insn, 6, 1)) 2841 inc = 2; 2842 break; 2843 } 2844 2845 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2846 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2847 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2848 2849 if (Rm != 0xF) { // Writeback 2850 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2851 return false; 2852 } 2853 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2854 Inst.addOperand(MCOperand::CreateImm(align)); 2855 if (Rm != 0xF && Rm != 0xD) { 2856 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2857 return false; 2858 } 2859 2860 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2861 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2862 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2863 Inst.addOperand(MCOperand::CreateImm(index)); 2864 2865 return true; 2866 } 2867 2868 static bool DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, 2869 uint64_t Address, const void *Decoder) { 2870 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2871 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2872 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2873 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2874 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2875 2876 unsigned align = 0; 2877 unsigned index = 0; 2878 unsigned inc = 1; 2879 switch (size) { 2880 default: 2881 return false; 2882 case 0: 2883 if (fieldFromInstruction32(Insn, 4, 1)) 2884 return false; // UNDEFINED 2885 index = fieldFromInstruction32(Insn, 5, 3); 2886 break; 2887 case 1: 2888 if (fieldFromInstruction32(Insn, 4, 1)) 2889 return false; // UNDEFINED 2890 index = fieldFromInstruction32(Insn, 6, 2); 2891 if (fieldFromInstruction32(Insn, 5, 1)) 2892 inc = 2; 2893 break; 2894 case 2: 2895 if (fieldFromInstruction32(Insn, 4, 2)) 2896 return false; // UNDEFINED 2897 index = fieldFromInstruction32(Insn, 7, 1); 2898 if (fieldFromInstruction32(Insn, 6, 1)) 2899 inc = 2; 2900 break; 2901 } 2902 2903 if (Rm != 0xF) { // Writeback 2904 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2905 return false; 2906 } 2907 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2908 Inst.addOperand(MCOperand::CreateImm(align)); 2909 if (Rm != 0xF && Rm != 0xD) { 2910 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2911 return false; 2912 } 2913 2914 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2915 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2916 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2917 Inst.addOperand(MCOperand::CreateImm(index)); 2918 2919 return true; 2920 } 2921 2922 2923 static bool DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, 2924 uint64_t Address, const void *Decoder) { 2925 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2926 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2927 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2928 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2929 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2930 2931 unsigned align = 0; 2932 unsigned index = 0; 2933 unsigned inc = 1; 2934 switch (size) { 2935 default: 2936 return false; 2937 case 0: 2938 if (fieldFromInstruction32(Insn, 4, 1)) 2939 align = 4; 2940 index = fieldFromInstruction32(Insn, 5, 3); 2941 break; 2942 case 1: 2943 if (fieldFromInstruction32(Insn, 4, 1)) 2944 align = 8; 2945 index = fieldFromInstruction32(Insn, 6, 2); 2946 if (fieldFromInstruction32(Insn, 5, 1)) 2947 inc = 2; 2948 break; 2949 case 2: 2950 if (fieldFromInstruction32(Insn, 4, 2)) 2951 align = 4 << fieldFromInstruction32(Insn, 4, 2); 2952 index = fieldFromInstruction32(Insn, 7, 1); 2953 if (fieldFromInstruction32(Insn, 6, 1)) 2954 inc = 2; 2955 break; 2956 } 2957 2958 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2959 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2960 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2961 if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; 2962 2963 if (Rm != 0xF) { // Writeback 2964 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 2965 return false; 2966 } 2967 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 2968 Inst.addOperand(MCOperand::CreateImm(align)); 2969 if (Rm != 0xF && Rm != 0xD) { 2970 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 2971 return false; 2972 } 2973 2974 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 2975 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 2976 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 2977 if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; 2978 Inst.addOperand(MCOperand::CreateImm(index)); 2979 2980 return true; 2981 } 2982 2983 static bool DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, 2984 uint64_t Address, const void *Decoder) { 2985 unsigned Rn = fieldFromInstruction32(Insn, 16, 4); 2986 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); 2987 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); 2988 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4; 2989 unsigned size = fieldFromInstruction32(Insn, 10, 2); 2990 2991 unsigned align = 0; 2992 unsigned index = 0; 2993 unsigned inc = 1; 2994 switch (size) { 2995 default: 2996 return false; 2997 case 0: 2998 if (fieldFromInstruction32(Insn, 4, 1)) 2999 align = 4; 3000 index = fieldFromInstruction32(Insn, 5, 3); 3001 break; 3002 case 1: 3003 if (fieldFromInstruction32(Insn, 4, 1)) 3004 align = 8; 3005 index = fieldFromInstruction32(Insn, 6, 2); 3006 if (fieldFromInstruction32(Insn, 5, 1)) 3007 inc = 2; 3008 break; 3009 case 2: 3010 if (fieldFromInstruction32(Insn, 4, 2)) 3011 align = 4 << fieldFromInstruction32(Insn, 4, 2); 3012 index = fieldFromInstruction32(Insn, 7, 1); 3013 if (fieldFromInstruction32(Insn, 6, 1)) 3014 inc = 2; 3015 break; 3016 } 3017 3018 if (Rm != 0xF) { // Writeback 3019 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) 3020 return false; 3021 } 3022 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false; 3023 Inst.addOperand(MCOperand::CreateImm(align)); 3024 if (Rm != 0xF && Rm != 0xD) { 3025 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) 3026 return false; 3027 } 3028 3029 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; 3030 if (!DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)) return false; 3031 if (!DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)) return false; 3032 if (!DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)) return false; 3033 Inst.addOperand(MCOperand::CreateImm(index)); 3034 3035 return true; 3036 } 3037 3038